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1 /**
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2 ******************************************************************************
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3 * @file stm32l4xx_hal_flash.h
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4 * @author MCD Application Team
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5 * @version V1.6.0
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6 * @date 28-October-2016
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7 * @brief Header file of FLASH HAL module.
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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12 *
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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23 *
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 *
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35 ******************************************************************************
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36 */
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37
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32L4xx_HAL_FLASH_H
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40 #define __STM32L4xx_HAL_FLASH_H
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41
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42 #ifdef __cplusplus
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43 extern "C" {
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44 #endif
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32l4xx_hal_def.h"
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48
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49 /** @addtogroup STM32L4xx_HAL_Driver
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50 * @{
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51 */
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52
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53 /** @addtogroup FLASH
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54 * @{
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55 */
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56
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup FLASH_Exported_Types FLASH Exported Types
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59 * @{
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60 */
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61
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62 /**
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63 * @brief FLASH Erase structure definition
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64 */
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65 typedef struct
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66 {
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67 uint32_t TypeErase; /*!< Mass erase or page erase.
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68 This parameter can be a value of @ref FLASH_Type_Erase */
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69 uint32_t Banks; /*!< Select bank to erase.
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70 This parameter must be a value of @ref FLASH_Banks
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71 (FLASH_BANK_BOTH should be used only for mass erase) */
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72 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled
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73 This parameter must be a value between 0 and (max number of pages in the bank - 1)
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74 (eg : 255 for 1MB dual bank) */
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75 uint32_t NbPages; /*!< Number of pages to be erased.
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76 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
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77 } FLASH_EraseInitTypeDef;
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78
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79 /**
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80 * @brief FLASH Option Bytes Program structure definition
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81 */
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82 typedef struct
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83 {
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84 uint32_t OptionType; /*!< Option byte to be configured.
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85 This parameter can be a combination of the values of @ref FLASH_OB_Type */
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86 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
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87 Only one WRP area could be programmed at the same time.
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88 This parameter can be value of @ref FLASH_OB_WRP_Area */
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89 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
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90 This parameter must be a value between 0 and (max number of pages in the bank - 1)
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91 (eg : 25 for 1MB dual bank) */
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92 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
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93 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
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94 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
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95 This parameter can be a value of @ref FLASH_OB_Read_Protection */
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96 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
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97 This parameter can be a combination of @ref FLASH_OB_USER_Type */
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98 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
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99 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
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100 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
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101 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
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102 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
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103 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2,
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104 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1,
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105 @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
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106 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
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107 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
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108 and @ref FLASH_OB_PCROP_RDP */
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109 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
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110 This parameter must be a value between begin and end of bank
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111 => Be careful of the bank swapping for the address */
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112 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
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113 This parameter must be a value between PCROP Start address and end of bank */
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114 } FLASH_OBProgramInitTypeDef;
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115
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116 /**
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117 * @brief FLASH Procedure structure definition
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118 */
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119 typedef enum
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120 {
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121 FLASH_PROC_NONE = 0,
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122 FLASH_PROC_PAGE_ERASE,
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123 FLASH_PROC_MASS_ERASE,
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124 FLASH_PROC_PROGRAM,
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125 FLASH_PROC_PROGRAM_LAST
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126 } FLASH_ProcedureTypeDef;
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127
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128 /**
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129 * @brief FLASH Cache structure definition
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130 */
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131 typedef enum
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132 {
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133 FLASH_CACHE_DISABLED = 0,
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134 FLASH_CACHE_ICACHE_ENABLED,
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135 FLASH_CACHE_DCACHE_ENABLED,
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136 FLASH_CACHE_ICACHE_DCACHE_ENABLED
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137 } FLASH_CacheTypeDef;
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138
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139 /**
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140 * @brief FLASH handle Structure definition
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141 */
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142 typedef struct
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143 {
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144 HAL_LockTypeDef Lock; /* FLASH locking object */
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145 __IO uint32_t ErrorCode; /* FLASH error code */
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146 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
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147 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
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148 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
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149 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
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150 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
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151 __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
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152 }FLASH_ProcessTypeDef;
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153
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154 /**
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155 * @}
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156 */
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157
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158 /* Exported constants --------------------------------------------------------*/
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159 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
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160 * @{
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161 */
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162
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163 /** @defgroup FLASH_Error FLASH Error
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164 * @{
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165 */
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166 #define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)
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167 #define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001)
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168 #define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002)
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169 #define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004)
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170 #define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)
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171 #define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010)
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172 #define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020)
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173 #define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040)
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174 #define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080)
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175 #define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100)
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176 #define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200)
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177 #define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400)
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178 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
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179 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
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180 #define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800)
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181 #endif
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182 /**
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183 * @}
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184 */
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185
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186 /** @defgroup FLASH_Type_Erase FLASH Erase Type
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187 * @{
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188 */
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189 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
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190 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
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191 /**
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192 * @}
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193 */
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194
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195 /** @defgroup FLASH_Banks FLASH Banks
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196 * @{
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197 */
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198 #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */
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199 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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200 #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */
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201 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
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202 #else
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203 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /*!< Bank 1 */
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204 #endif
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205 /**
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206 * @}
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207 */
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208
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209
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210 /** @defgroup FLASH_Type_Program FLASH Program Type
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211 * @{
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212 */
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213 #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /*!<Program a double-word (64-bit) at a specified address.*/
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214 #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
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215 And another 32 row double-word (64-bit) will be programmed */
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216 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
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217 And this is the last 32 row double-word (64-bit) programmed */
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218 /**
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219 * @}
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220 */
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221
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222 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type
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223 * @{
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224 */
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225 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */
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226 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
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227 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
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228 #define OPTIONBYTE_PCROP ((uint32_t)0x08) /*!< PCROP option byte configuration */
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229 /**
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230 * @}
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231 */
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232
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233 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
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234 * @{
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235 */
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236 #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */
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237 #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */
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238 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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239 #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */
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240 #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */
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241 #endif
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242 /**
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243 * @}
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244 */
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245
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246 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
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247 * @{
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248 */
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249 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA)
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250 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB)
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251 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2
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252 it's no more possible to go back to level 1 or 0 */
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253 /**
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254 * @}
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255 */
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256
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257 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
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258 * @{
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259 */
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260 #define OB_USER_BOR_LEV ((uint32_t)0x0001) /*!< BOR reset Level */
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261 #define OB_USER_nRST_STOP ((uint32_t)0x0002) /*!< Reset generated when entering the stop mode */
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262 #define OB_USER_nRST_STDBY ((uint32_t)0x0004) /*!< Reset generated when entering the standby mode */
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263 #define OB_USER_IWDG_SW ((uint32_t)0x0008) /*!< Independent watchdog selection */
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264 #define OB_USER_IWDG_STOP ((uint32_t)0x0010) /*!< Independent watchdog counter freeze in stop mode */
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265 #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */
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266 #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */
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267 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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268 #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */
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269 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */
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270 #endif
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271 #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */
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272 #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */
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273 #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */
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274 #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */
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275 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
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276 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
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277 #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */
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278 #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */
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279 #endif
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280 /**
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281 * @}
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282 */
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283
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284 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
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285 * @{
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286 */
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287 #define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 1.7V */
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288 #define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.0V */
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289 #define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.2V */
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290 #define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /*!< Reset level threshold is around 2.5V */
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291 #define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /*!< Reset level threshold is around 2.8V */
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292 /**
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293 * @}
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294 */
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295
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296 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
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297 * @{
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298 */
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299 #define OB_STOP_RST ((uint32_t)0x0000) /*!< Reset generated when entering the stop mode */
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300 #define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */
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301 /**
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302 * @}
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303 */
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304
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305 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
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306 * @{
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307 */
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308 #define OB_STANDBY_RST ((uint32_t)0x0000) /*!< Reset generated when entering the standby mode */
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309 #define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */
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310 /**
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311 * @}
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312 */
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313
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314 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
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315 * @{
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316 */
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317 #define OB_SHUTDOWN_RST ((uint32_t)0x0000) /*!< Reset generated when entering the shutdown mode */
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318 #define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */
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319 /**
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320 * @}
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321 */
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322
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323 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
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324 * @{
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325 */
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326 #define OB_IWDG_HW ((uint32_t)0x00000) /*!< Hardware independent watchdog */
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327 #define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */
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328 /**
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329 * @}
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330 */
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331
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332 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
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333 * @{
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334 */
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335 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Stop mode */
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336 #define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */
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337 /**
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338 * @}
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339 */
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340
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341 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
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342 * @{
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343 */
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344 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Standby mode */
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345 #define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */
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346 /**
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347 * @}
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348 */
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349
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350 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
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351 * @{
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352 */
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353 #define OB_WWDG_HW ((uint32_t)0x00000) /*!< Hardware window watchdog */
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354 #define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */
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355 /**
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356 * @}
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357 */
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358
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359 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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360 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
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361 * @{
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362 */
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363 #define OB_BFB2_DISABLE ((uint32_t)0x000000) /*!< Dual-bank boot disable */
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364 #define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /*!< Dual-bank boot enable */
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365 /**
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366 * @}
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367 */
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368 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
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369 * @{
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370 */
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371 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 256 KB/512 KB Single-bank Flash */
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372 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /*!< 256 KB/512 KB Dual-bank Flash */
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373 /**
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374 * @}
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375 */
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376 #endif
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377
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378 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
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379 * @{
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380 */
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381 #define OB_BOOT1_SRAM ((uint32_t)0x000000) /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
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382 #define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */
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383 /**
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384 * @}
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385 */
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386
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387 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
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388 * @{
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389 */
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390 #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /*!< SRAM2 parity check enable */
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391 #define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /*!< SRAM2 parity check disable */
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392 /**
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393 * @}
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394 */
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395
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396 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
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397 * @{
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398 */
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399 #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /*!< SRAM2 erased when a system reset occurs */
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400 #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /*!< SRAM2 is not erased when a system reset occurs */
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401 /**
|
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402 * @}
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403 */
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404
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|
405 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
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406 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
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407 /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
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|
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408 * @{
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|
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409 */
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|
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410 #define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /*!< BOOT0 taken from the option bit nBOOT0 */
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411 #define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */
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|
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412 /**
|
|
|
413 * @}
|
|
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414 */
|
|
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415
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|
|
416 /** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
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|
|
417 * @{
|
|
|
418 */
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|
|
419 #define OB_BOOT0_RESET ((uint32_t)0x0000000) /*!< nBOOT0 = 0 */
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|
420 #define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */
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421 /**
|
|
|
422 * @}
|
|
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423 */
|
|
|
424 #endif
|
|
|
425
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|
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426 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
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427 * @{
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428 */
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|
|
429 #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level
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|
|
430 is decreased from Level 1 to Level 0 */
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431 #define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is
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|
|
432 decreased from Level 1 to Level 0 (full mass erase) */
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433 /**
|
|
|
434 * @}
|
|
|
435 */
|
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|
436
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|
|
437 /** @defgroup FLASH_Latency FLASH Latency
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|
438 * @{
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439 */
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440 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
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441 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
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442 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
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443 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
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444 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
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445 /**
|
|
|
446 * @}
|
|
|
447 */
|
|
|
448
|
|
|
449 /** @defgroup FLASH_Keys FLASH Keys
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|
|
450 * @{
|
|
|
451 */
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|
|
452 #define FLASH_KEY1 ((uint32_t)0x45670123U) /*!< Flash key1 */
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|
|
453 #define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) /*!< Flash key2: used with FLASH_KEY1
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|
|
454 to unlock the FLASH registers access */
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455
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|
|
456 #define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */
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|
|
457 #define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
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|
|
458 to unlock the RUN_PD bit in FLASH_ACR */
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|
459
|
|
|
460 #define FLASH_OPTKEY1 ((uint32_t)0x08192A3BU) /*!< Flash option byte key1 */
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|
|
461 #define FLASH_OPTKEY2 ((uint32_t)0x4C5D6E7FU) /*!< Flash option byte key2: used with FLASH_OPTKEY1
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|
|
462 to allow option bytes operations */
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|
|
463 /**
|
|
|
464 * @}
|
|
|
465 */
|
|
|
466
|
|
|
467 /** @defgroup FLASH_Flags FLASH Flags Definition
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|
|
468 * @{
|
|
|
469 */
|
|
|
470 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
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|
|
471 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
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|
|
472 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */
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|
473 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
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|
474 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
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|
475 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
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|
|
476 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
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|
|
477 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
|
|
|
478 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
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|
|
479 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
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|
|
480 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
|
|
|
481 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
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|
|
482 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
|
|
|
483 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
|
|
|
484 #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */
|
|
|
485 #endif
|
|
|
486 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
|
|
|
487 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
|
|
|
488
|
|
|
489 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
|
|
|
490 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
|
|
|
491 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
|
|
|
492 FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)
|
|
|
493 /**
|
|
|
494 * @}
|
|
|
495 */
|
|
|
496
|
|
|
497 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
|
|
|
498 * @brief FLASH Interrupt definition
|
|
|
499 * @{
|
|
|
500 */
|
|
|
501 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
|
|
502 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
|
|
|
503 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/
|
|
|
504 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */
|
|
|
505 /**
|
|
|
506 * @}
|
|
|
507 */
|
|
|
508
|
|
|
509 /**
|
|
|
510 * @}
|
|
|
511 */
|
|
|
512
|
|
|
513 /* Exported macros -----------------------------------------------------------*/
|
|
|
514 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
|
|
515 * @brief macros to control FLASH features
|
|
|
516 * @{
|
|
|
517 */
|
|
|
518
|
|
|
519 /**
|
|
|
520 * @brief Set the FLASH Latency.
|
|
|
521 * @param __LATENCY__: FLASH Latency
|
|
|
522 * This parameter can be one of the following values :
|
|
|
523 * @arg FLASH_LATENCY_0: FLASH Zero wait state
|
|
|
524 * @arg FLASH_LATENCY_1: FLASH One wait state
|
|
|
525 * @arg FLASH_LATENCY_2: FLASH Two wait states
|
|
|
526 * @arg FLASH_LATENCY_3: FLASH Three wait states
|
|
|
527 * @arg FLASH_LATENCY_4: FLASH Four wait states
|
|
|
528 * @retval None
|
|
|
529 */
|
|
|
530 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
|
|
|
531
|
|
|
532 /**
|
|
|
533 * @brief Get the FLASH Latency.
|
|
|
534 * @retval FLASH Latency
|
|
|
535 * This parameter can be one of the following values :
|
|
|
536 * @arg FLASH_LATENCY_0: FLASH Zero wait state
|
|
|
537 * @arg FLASH_LATENCY_1: FLASH One wait state
|
|
|
538 * @arg FLASH_LATENCY_2: FLASH Two wait states
|
|
|
539 * @arg FLASH_LATENCY_3: FLASH Three wait states
|
|
|
540 * @arg FLASH_LATENCY_4: FLASH Four wait states
|
|
|
541 */
|
|
|
542 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
|
|
|
543
|
|
|
544 /**
|
|
|
545 * @brief Enable the FLASH prefetch buffer.
|
|
|
546 * @retval None
|
|
|
547 */
|
|
|
548 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
|
|
549
|
|
|
550 /**
|
|
|
551 * @brief Disable the FLASH prefetch buffer.
|
|
|
552 * @retval None
|
|
|
553 */
|
|
|
554 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
|
|
555
|
|
|
556 /**
|
|
|
557 * @brief Enable the FLASH instruction cache.
|
|
|
558 * @retval none
|
|
|
559 */
|
|
|
560 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
|
|
|
561
|
|
|
562 /**
|
|
|
563 * @brief Disable the FLASH instruction cache.
|
|
|
564 * @retval none
|
|
|
565 */
|
|
|
566 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
|
|
|
567
|
|
|
568 /**
|
|
|
569 * @brief Enable the FLASH data cache.
|
|
|
570 * @retval none
|
|
|
571 */
|
|
|
572 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
|
|
|
573
|
|
|
574 /**
|
|
|
575 * @brief Disable the FLASH data cache.
|
|
|
576 * @retval none
|
|
|
577 */
|
|
|
578 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
|
|
|
579
|
|
|
580 /**
|
|
|
581 * @brief Reset the FLASH instruction Cache.
|
|
|
582 * @note This function must be used only when the Instruction Cache is disabled.
|
|
|
583 * @retval None
|
|
|
584 */
|
|
|
585 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
|
|
|
586 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
|
|
|
587 } while (0)
|
|
|
588
|
|
|
589 /**
|
|
|
590 * @brief Reset the FLASH data Cache.
|
|
|
591 * @note This function must be used only when the data Cache is disabled.
|
|
|
592 * @retval None
|
|
|
593 */
|
|
|
594 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
|
|
|
595 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
|
|
|
596 } while (0)
|
|
|
597
|
|
|
598 /**
|
|
|
599 * @brief Enable the FLASH power down during Low-power run mode.
|
|
|
600 * @note Writing this bit to 0 this bit, automatically the keys are
|
|
|
601 * loss and a new unlock sequence is necessary to re-write it to 1.
|
|
|
602 */
|
|
|
603 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
|
|
|
604 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
|
|
|
605 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
|
|
|
606 } while (0)
|
|
|
607
|
|
|
608 /**
|
|
|
609 * @brief Disable the FLASH power down during Low-power run mode.
|
|
|
610 * @note Writing this bit to 0 this bit, automatically the keys are
|
|
|
611 * loss and a new unlock sequence is necessary to re-write it to 1.
|
|
|
612 */
|
|
|
613 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
|
|
|
614 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
|
|
|
615 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
|
|
|
616 } while (0)
|
|
|
617
|
|
|
618 /**
|
|
|
619 * @brief Enable the FLASH power down during Low-Power sleep mode
|
|
|
620 * @retval none
|
|
|
621 */
|
|
|
622 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
|
|
|
623
|
|
|
624 /**
|
|
|
625 * @brief Disable the FLASH power down during Low-Power sleep mode
|
|
|
626 * @retval none
|
|
|
627 */
|
|
|
628 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
|
|
|
629
|
|
|
630 /**
|
|
|
631 * @}
|
|
|
632 */
|
|
|
633
|
|
|
634 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros
|
|
|
635 * @brief macros to handle FLASH interrupts
|
|
|
636 * @{
|
|
|
637 */
|
|
|
638
|
|
|
639 /**
|
|
|
640 * @brief Enable the specified FLASH interrupt.
|
|
|
641 * @param __INTERRUPT__: FLASH interrupt
|
|
|
642 * This parameter can be any combination of the following values:
|
|
|
643 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
|
|
644 * @arg FLASH_IT_OPERR: Error Interrupt
|
|
|
645 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
|
|
|
646 * @arg FLASH_IT_ECCC: ECC Correction Interrupt
|
|
|
647 * @retval none
|
|
|
648 */
|
|
|
649 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
|
|
|
650 if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
|
|
|
651 } while(0)
|
|
|
652
|
|
|
653 /**
|
|
|
654 * @brief Disable the specified FLASH interrupt.
|
|
|
655 * @param __INTERRUPT__: FLASH interrupt
|
|
|
656 * This parameter can be any combination of the following values:
|
|
|
657 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
|
|
658 * @arg FLASH_IT_OPERR: Error Interrupt
|
|
|
659 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
|
|
|
660 * @arg FLASH_IT_ECCC: ECC Correction Interrupt
|
|
|
661 * @retval none
|
|
|
662 */
|
|
|
663 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
|
|
|
664 if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
|
|
|
665 } while(0)
|
|
|
666
|
|
|
667 /**
|
|
|
668 * @brief Check whether the specified FLASH flag is set or not.
|
|
|
669 * @param __FLAG__: specifies the FLASH flag to check.
|
|
|
670 * This parameter can be one of the following values:
|
|
|
671 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
|
|
|
672 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
|
|
|
673 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
|
|
|
674 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
|
|
|
675 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
|
|
|
676 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
|
|
|
677 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
|
|
|
678 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
|
|
|
679 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
|
|
|
680 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
|
|
|
681 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
|
|
|
682 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
|
|
|
683 * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
|
|
|
684 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
|
|
|
685 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
|
|
|
686 * @retval The new state of FLASH_FLAG (SET or RESET).
|
|
|
687 */
|
|
|
688 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \
|
|
|
689 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
|
|
|
690 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
|
|
|
691
|
|
|
692 /**
|
|
|
693 * @brief Clear the FLASH's pending flags.
|
|
|
694 * @param __FLAG__: specifies the FLASH flags to clear.
|
|
|
695 * This parameter can be any combination of the following values:
|
|
|
696 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
|
|
|
697 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
|
|
|
698 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
|
|
|
699 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
|
|
|
700 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
|
|
|
701 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
|
|
|
702 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
|
|
|
703 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
|
|
|
704 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
|
|
|
705 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
|
|
|
706 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
|
|
|
707 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
|
|
|
708 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
|
|
|
709 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
|
|
|
710 * @retval None
|
|
|
711 */
|
|
|
712 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
|
|
|
713 if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
|
|
|
714 } while(0)
|
|
|
715 /**
|
|
|
716 * @}
|
|
|
717 */
|
|
|
718
|
|
|
719 /* Include FLASH HAL Extended module */
|
|
|
720 #include "stm32l4xx_hal_flash_ex.h"
|
|
|
721 #include "stm32l4xx_hal_flash_ramfunc.h"
|
|
|
722
|
|
|
723 /* Exported functions --------------------------------------------------------*/
|
|
|
724 /** @addtogroup FLASH_Exported_Functions
|
|
|
725 * @{
|
|
|
726 */
|
|
|
727
|
|
|
728 /* Program operation functions ***********************************************/
|
|
|
729 /** @addtogroup FLASH_Exported_Functions_Group1
|
|
|
730 * @{
|
|
|
731 */
|
|
|
732 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
|
|
733 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
|
|
734 /* FLASH IRQ handler method */
|
|
|
735 void HAL_FLASH_IRQHandler(void);
|
|
|
736 /* Callbacks in non blocking modes */
|
|
|
737 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
|
|
738 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
|
|
739 /**
|
|
|
740 * @}
|
|
|
741 */
|
|
|
742
|
|
|
743 /* Peripheral Control functions **********************************************/
|
|
|
744 /** @addtogroup FLASH_Exported_Functions_Group2
|
|
|
745 * @{
|
|
|
746 */
|
|
|
747 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
|
|
748 HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
|
|
749 /* Option bytes control */
|
|
|
750 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
|
|
751 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
|
|
752 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
|
|
753 /**
|
|
|
754 * @}
|
|
|
755 */
|
|
|
756
|
|
|
757 /* Peripheral State functions ************************************************/
|
|
|
758 /** @addtogroup FLASH_Exported_Functions_Group3
|
|
|
759 * @{
|
|
|
760 */
|
|
|
761 uint32_t HAL_FLASH_GetError(void);
|
|
|
762 /**
|
|
|
763 * @}
|
|
|
764 */
|
|
|
765
|
|
|
766 /**
|
|
|
767 * @}
|
|
|
768 */
|
|
|
769
|
|
|
770 /* Private constants --------------------------------------------------------*/
|
|
|
771 /** @defgroup FLASH_Private_Constants FLASH Private Constants
|
|
|
772 * @{
|
|
|
773 */
|
|
|
774 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
|
|
|
775
|
|
|
776 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
|
|
|
777 #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \
|
|
|
778 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
|
|
|
779 #else
|
|
|
780 #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
|
|
|
781 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
|
|
|
782 #endif
|
|
|
783
|
|
|
784 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
785 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
|
|
|
786 #else
|
|
|
787 #define FLASH_BANK_SIZE (FLASH_SIZE)
|
|
|
788 #endif
|
|
|
789
|
|
|
790 #define FLASH_PAGE_SIZE ((uint32_t)0x800)
|
|
|
791
|
|
|
792 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
|
|
|
793 /**
|
|
|
794 * @}
|
|
|
795 */
|
|
|
796
|
|
|
797 /* Private macros ------------------------------------------------------------*/
|
|
|
798 /** @defgroup FLASH_Private_Macros FLASH Private Macros
|
|
|
799 * @{
|
|
|
800 */
|
|
|
801
|
|
|
802 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
|
|
|
803 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
|
|
804
|
|
|
805 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
806 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
|
|
|
807 ((BANK) == FLASH_BANK_2) || \
|
|
|
808 ((BANK) == FLASH_BANK_BOTH))
|
|
|
809
|
|
|
810 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
|
|
|
811 ((BANK) == FLASH_BANK_2))
|
|
|
812 #else
|
|
|
813 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
|
|
|
814
|
|
|
815 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
|
|
|
816 #endif
|
|
|
817
|
|
|
818 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
|
|
|
819 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
|
|
|
820 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
|
|
|
821
|
|
|
822 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
|
|
|
823 ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
|
|
|
824 ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
|
|
|
825 ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \
|
|
|
826 ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))))
|
|
|
827
|
|
|
828 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
|
|
|
829
|
|
|
830 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
|
|
|
831
|
|
|
832 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
|
833 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
|
|
|
834 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
|
|
|
835 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
|
|
|
836 ((PAGE) < 256)))))
|
|
|
837 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
|
|
|
838 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \
|
|
|
839 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
|
|
|
840 ((PAGE) < 256))))
|
|
|
841 #else
|
|
|
842 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
|
|
|
843 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \
|
|
|
844 ((PAGE) < 128))))
|
|
|
845 #endif
|
|
|
846
|
|
|
847 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
|
|
|
848
|
|
|
849 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
850 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
|
|
|
851 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
|
|
|
852 #else
|
|
|
853 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
|
|
|
854 #endif
|
|
|
855
|
|
|
856 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
|
|
857 ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
|
|
|
858 ((LEVEL) == OB_RDP_LEVEL_2)*/)
|
|
|
859
|
|
|
860 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
|
861 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
|
|
|
862 #else
|
|
|
863 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0))
|
|
|
864 #endif
|
|
|
865
|
|
|
866 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
|
|
|
867 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
|
|
|
868 ((LEVEL) == OB_BOR_LEVEL_4))
|
|
|
869
|
|
|
870 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
|
|
|
871
|
|
|
872 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
|
|
|
873
|
|
|
874 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
|
|
|
875
|
|
|
876 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
|
|
|
877
|
|
|
878 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
|
|
|
879
|
|
|
880 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
|
|
|
881
|
|
|
882 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
|
|
|
883
|
|
|
884 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
885 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
|
|
|
886
|
|
|
887 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
|
|
|
888 #endif
|
|
|
889
|
|
|
890 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
|
|
|
891
|
|
|
892 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
|
|
|
893
|
|
|
894 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
|
|
|
895
|
|
|
896 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
|
|
|
897 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
|
|
|
898 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
|
|
|
899
|
|
|
900 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))
|
|
|
901 #endif
|
|
|
902
|
|
|
903 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
|
|
|
904
|
|
|
905 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
|
|
|
906 ((LATENCY) == FLASH_LATENCY_1) || \
|
|
|
907 ((LATENCY) == FLASH_LATENCY_2) || \
|
|
|
908 ((LATENCY) == FLASH_LATENCY_3) || \
|
|
|
909 ((LATENCY) == FLASH_LATENCY_4))
|
|
|
910 /**
|
|
|
911 * @}
|
|
|
912 */
|
|
|
913
|
|
|
914 /**
|
|
|
915 * @}
|
|
|
916 */
|
|
|
917
|
|
|
918 /**
|
|
|
919 * @}
|
|
|
920 */
|
|
|
921
|
|
|
922 #ifdef __cplusplus
|
|
|
923 }
|
|
|
924 #endif
|
|
|
925
|
|
|
926 #endif /* __STM32L4xx_HAL_FLASH_H */
|
|
|
927
|
|
|
928 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
