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1 /**
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2 ******************************************************************************
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3 * @file stm32l4xx_hal_flash_ex.c
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4 * @author MCD Application Team
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5 * @version V1.6.0
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6 * @date 28-October-2016
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7 * @brief Extended FLASH HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the FLASH extended peripheral:
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10 * + Extended programming operations functions
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11 *
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12 @verbatim
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13 ==============================================================================
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14 ##### Flash Extended features #####
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15 ==============================================================================
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16
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17 [..] Comparing to other previous devices, the FLASH interface for STM32L4xx
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18 devices contains the following additional features
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19
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20 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
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21 capability (RWW)
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22 (+) Dual bank memory organization
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23 (+) PCROP protection for all banks
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24
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25 ##### How to use this driver #####
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26 ==============================================================================
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27 [..] This driver provides functions to configure and program the FLASH memory
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28 of all STM32L4xx devices. It includes
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29 (#) Flash Memory Erase functions:
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30 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
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31 HAL_FLASH_Lock() functions
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32 (++) Erase function: Erase page, erase all sectors
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33 (++) There are two modes of erase :
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34 (+++) Polling Mode using HAL_FLASHEx_Erase()
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35 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
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36
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37 (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
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38 (++) Set/Reset the write protection
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39 (++) Set the Read protection Level
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40 (++) Program the user Option Bytes
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41 (++) Configure the PCROP protection
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42
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43 (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
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44 (++) Get the value of a write protection area
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45 (++) Know if the read protection is activated
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46 (++) Get the value of the user Option Bytes
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47 (++) Get the value of a PCROP area
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48
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49 @endverbatim
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50 ******************************************************************************
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51 * @attention
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52 *
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53 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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54 *
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55 * Redistribution and use in source and binary forms, with or without modification,
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56 * are permitted provided that the following conditions are met:
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57 * 1. Redistributions of source code must retain the above copyright notice,
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58 * this list of conditions and the following disclaimer.
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59 * 2. Redistributions in binary form must reproduce the above copyright notice,
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60 * this list of conditions and the following disclaimer in the documentation
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61 * and/or other materials provided with the distribution.
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62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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63 * may be used to endorse or promote products derived from this software
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64 * without specific prior written permission.
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65 *
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66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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76 *
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77 ******************************************************************************
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78 */
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79
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80 /* Includes ------------------------------------------------------------------*/
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81 #include "stm32l4xx_hal.h"
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82
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83 /** @addtogroup STM32L4xx_HAL_Driver
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84 * @{
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85 */
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86
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87 /** @defgroup FLASHEx FLASHEx
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88 * @brief FALSH Extended HAL module driver
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89 * @{
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90 */
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91
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92 #ifdef HAL_FLASH_MODULE_ENABLED
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93
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94 /* Private typedef -----------------------------------------------------------*/
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95 /* Private define ------------------------------------------------------------*/
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96 /* Private macro -------------------------------------------------------------*/
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97 /* Private variables ---------------------------------------------------------*/
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98 /** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables
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99 * @{
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100 */
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101 extern FLASH_ProcessTypeDef pFlash;
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102 /**
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103 * @}
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104 */
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105
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106 /* Private function prototypes -----------------------------------------------*/
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107 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
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108 * @{
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109 */
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110 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
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111 void FLASH_PageErase(uint32_t Page, uint32_t Banks);
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112 static void FLASH_MassErase(uint32_t Banks);
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113 void FLASH_FlushCaches(void);
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114 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
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115 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
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116 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
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117 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
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118 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);
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119 static uint32_t FLASH_OB_GetRDP(void);
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120 static uint32_t FLASH_OB_GetUser(void);
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121 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);
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122 /**
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123 * @}
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124 */
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125
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126 /* Exported functions -------------------------------------------------------*/
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127 /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
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128 * @{
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129 */
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130
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131 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
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132 * @brief Extended IO operation functions
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133 *
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134 @verbatim
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135 ===============================================================================
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136 ##### Extended programming operation functions #####
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137 ===============================================================================
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138 [..]
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139 This subsection provides a set of functions allowing to manage the Extended FLASH
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140 programming operations Operations.
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141
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142 @endverbatim
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143 * @{
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144 */
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145 /**
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146 * @brief Perform a mass erase or erase the specified FLASH memory pages.
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147 * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
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148 * contains the configuration information for the erasing.
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149 *
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150 * @param[out] PageError : pointer to variable that contains the configuration
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151 * information on faulty page in case of error (0xFFFFFFFF means that all
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152 * the pages have been correctly erased)
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153 *
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154 * @retval HAL Status
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155 */
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156 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
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157 {
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158 HAL_StatusTypeDef status = HAL_ERROR;
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159 uint32_t page_index = 0;
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160
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161 /* Process Locked */
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162 __HAL_LOCK(&pFlash);
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163
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164 /* Check the parameters */
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165 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
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166
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167 /* Wait for last operation to be completed */
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168 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
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169
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170 if (status == HAL_OK)
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171 {
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172 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
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173
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174 /* Deactivate the cache if they are activated to avoid data misbehavior */
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175 if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
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176 {
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177 /* Disable instruction cache */
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178 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
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179
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180 if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
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181 {
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182 /* Disable data cache */
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183 __HAL_FLASH_DATA_CACHE_DISABLE();
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184 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
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185 }
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186 else
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187 {
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188 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
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189 }
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190 }
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191 else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
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192 {
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193 /* Disable data cache */
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194 __HAL_FLASH_DATA_CACHE_DISABLE();
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195 pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
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196 }
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197 else
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198 {
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199 pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
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200 }
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201
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202 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
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203 {
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204 /* Mass erase to be done */
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205 FLASH_MassErase(pEraseInit->Banks);
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206
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207 /* Wait for last operation to be completed */
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208 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
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209
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210 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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211 /* If the erase operation is completed, disable the MER1 and MER2 Bits */
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212 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
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213 #else
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214 /* If the erase operation is completed, disable the MER1 Bit */
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215 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
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216 #endif
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217 }
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218 else
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219 {
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220 /*Initialization of PageError variable*/
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221 *PageError = 0xFFFFFFFF;
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222
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223 for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
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224 {
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225 FLASH_PageErase(page_index, pEraseInit->Banks);
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226
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227 /* Wait for last operation to be completed */
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228 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
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229
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230 /* If the erase operation is completed, disable the PER Bit */
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231 CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
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232
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233 if (status != HAL_OK)
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234 {
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235 /* In case of error, stop erase procedure and return the faulty address */
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236 *PageError = page_index;
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237 break;
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238 }
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239 }
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240 }
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241
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242 /* Flush the caches to be sure of the data consistency */
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243 FLASH_FlushCaches();
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244 }
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245
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246 /* Process Unlocked */
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247 __HAL_UNLOCK(&pFlash);
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248
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249 return status;
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250 }
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251
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252 /**
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253 * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
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254 * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
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255 * contains the configuration information for the erasing.
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256 *
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257 * @retval HAL Status
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258 */
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259 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
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260 {
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261 HAL_StatusTypeDef status = HAL_OK;
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262
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263 /* Process Locked */
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264 __HAL_LOCK(&pFlash);
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265
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266 /* Check the parameters */
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267 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
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268
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269 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
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270
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271 /* Deactivate the cache if they are activated to avoid data misbehavior */
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272 if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
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273 {
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274 /* Disable instruction cache */
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275 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
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276
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277 if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
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278 {
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279 /* Disable data cache */
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280 __HAL_FLASH_DATA_CACHE_DISABLE();
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281 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
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282 }
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283 else
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284 {
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285 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
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286 }
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287 }
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288 else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
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289 {
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290 /* Disable data cache */
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291 __HAL_FLASH_DATA_CACHE_DISABLE();
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292 pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
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293 }
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294 else
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295 {
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296 pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
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297 }
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298
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299 /* Enable End of Operation and Error interrupts */
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300 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
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301
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302 pFlash.Bank = pEraseInit->Banks;
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303
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304 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
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305 {
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306 /* Mass erase to be done */
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307 pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
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308 FLASH_MassErase(pEraseInit->Banks);
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309 }
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310 else
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311 {
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312 /* Erase by page to be done */
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313 pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
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314 pFlash.NbPagesToErase = pEraseInit->NbPages;
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315 pFlash.Page = pEraseInit->Page;
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316
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317 /*Erase 1st page and wait for IT */
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318 FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
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319 }
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320
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321 return status;
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322 }
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323
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324 /**
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325 * @brief Program Option bytes.
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326 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
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327 * contains the configuration information for the programming.
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328 *
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329 * @retval HAL Status
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330 */
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331 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
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332 {
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333 HAL_StatusTypeDef status = HAL_ERROR;
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334
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335 /* Process Locked */
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336 __HAL_LOCK(&pFlash);
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337
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338 /* Check the parameters */
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339 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
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340
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341 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
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342
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343 /* Write protection configuration */
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344 if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET)
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345 {
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346 /* Configure of Write protection on the selected area */
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347 status = FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
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348 }
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349
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350 /* Read protection configuration */
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351 if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
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352 {
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353 /* Configure the Read protection level */
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354 status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
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355 }
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356
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357 /* User Configuration */
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358 if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
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359 {
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360 /* Configure the user option bytes */
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361 status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
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362 }
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363
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364 /* PCROP Configuration */
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365 if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
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366 {
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367 if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)
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368 {
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369 /* Configure the Proprietary code readout protection */
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370 status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr);
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371 }
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372 }
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373
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374 /* Process Unlocked */
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375 __HAL_UNLOCK(&pFlash);
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376
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377 return status;
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378 }
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379
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380 /**
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381 * @brief Get the Option bytes configuration.
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382 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the
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383 * configuration information.
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384 * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
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385 * which area is requested for the WRP and PCROP, else no information will be returned
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386 *
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387 * @retval None
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388 */
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389 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
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390 {
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391 pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
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392
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393 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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394 if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
|
|
|
395 (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
|
|
|
396 #else
|
|
|
397 if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
|
|
|
398 #endif
|
|
|
399 {
|
|
|
400 pOBInit->OptionType |= OPTIONBYTE_WRP;
|
|
|
401 /* Get write protection on the selected area */
|
|
|
402 FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
|
|
|
403 }
|
|
|
404
|
|
|
405 /* Get Read protection level */
|
|
|
406 pOBInit->RDPLevel = FLASH_OB_GetRDP();
|
|
|
407
|
|
|
408 /* Get the user option bytes */
|
|
|
409 pOBInit->USERConfig = FLASH_OB_GetUser();
|
|
|
410
|
|
|
411 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
412 if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))
|
|
|
413 #else
|
|
|
414 if(pOBInit->PCROPConfig == FLASH_BANK_1)
|
|
|
415 #endif
|
|
|
416 {
|
|
|
417 pOBInit->OptionType |= OPTIONBYTE_PCROP;
|
|
|
418 /* Get the Proprietary code readout protection */
|
|
|
419 FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
|
|
|
420 }
|
|
|
421 }
|
|
|
422
|
|
|
423 /**
|
|
|
424 * @}
|
|
|
425 */
|
|
|
426
|
|
|
427 /**
|
|
|
428 * @}
|
|
|
429 */
|
|
|
430
|
|
|
431 /* Private functions ---------------------------------------------------------*/
|
|
|
432
|
|
|
433 /** @addtogroup FLASHEx_Private_Functions
|
|
|
434 * @{
|
|
|
435 */
|
|
|
436 /**
|
|
|
437 * @brief Mass erase of FLASH memory.
|
|
|
438 * @param Banks: Banks to be erased
|
|
|
439 * This parameter can be one of the following values:
|
|
|
440 * @arg FLASH_BANK_1: Bank1 to be erased
|
|
|
441 * @arg FLASH_BANK_2: Bank2 to be erased
|
|
|
442 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
|
|
|
443 * @retval None
|
|
|
444 */
|
|
|
445 static void FLASH_MassErase(uint32_t Banks)
|
|
|
446 {
|
|
|
447 {
|
|
|
448 /* Check the parameters */
|
|
|
449 assert_param(IS_FLASH_BANK(Banks));
|
|
|
450
|
|
|
451 /* Set the Mass Erase Bit for the bank 1 if requested */
|
|
|
452 if((Banks & FLASH_BANK_1) != RESET)
|
|
|
453 {
|
|
|
454 SET_BIT(FLASH->CR, FLASH_CR_MER1);
|
|
|
455 }
|
|
|
456
|
|
|
457 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
458 /* Set the Mass Erase Bit for the bank 2 if requested */
|
|
|
459 if((Banks & FLASH_BANK_2) != RESET)
|
|
|
460 {
|
|
|
461 SET_BIT(FLASH->CR, FLASH_CR_MER2);
|
|
|
462 }
|
|
|
463 #endif
|
|
|
464 }
|
|
|
465
|
|
|
466 /* Proceed to erase all sectors */
|
|
|
467 SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
|
|
468 }
|
|
|
469
|
|
|
470 /**
|
|
|
471 * @brief Erase the specified FLASH memory page.
|
|
|
472 * @param Page: FLASH page to erase
|
|
|
473 * This parameter must be a value between 0 and (max number of pages in the bank - 1)
|
|
|
474 * @param Banks: Bank(s) where the page will be erased
|
|
|
475 * This parameter can be one or a combination of the following values:
|
|
|
476 * @arg FLASH_BANK_1: Page in bank 1 to be erased
|
|
|
477 * @arg FLASH_BANK_2: Page in bank 2 to be erased
|
|
|
478 * @retval None
|
|
|
479 */
|
|
|
480 void FLASH_PageErase(uint32_t Page, uint32_t Banks)
|
|
|
481 {
|
|
|
482 /* Check the parameters */
|
|
|
483 assert_param(IS_FLASH_PAGE(Page));
|
|
|
484
|
|
|
485 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
486 {
|
|
|
487 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
|
|
|
488
|
|
|
489 if((Banks & FLASH_BANK_1) != RESET)
|
|
|
490 {
|
|
|
491 CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
|
|
|
492 }
|
|
|
493 else
|
|
|
494 {
|
|
|
495 SET_BIT(FLASH->CR, FLASH_CR_BKER);
|
|
|
496 }
|
|
|
497 }
|
|
|
498 #endif
|
|
|
499
|
|
|
500 /* Proceed to erase the page */
|
|
|
501 MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << POSITION_VAL(FLASH_CR_PNB)));
|
|
|
502 SET_BIT(FLASH->CR, FLASH_CR_PER);
|
|
|
503 SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
|
|
504 }
|
|
|
505
|
|
|
506 /**
|
|
|
507 * @brief Flush the instruction and data caches.
|
|
|
508 * @retval None
|
|
|
509 */
|
|
|
510 void FLASH_FlushCaches(void)
|
|
|
511 {
|
|
|
512 /* Flush instruction cache */
|
|
|
513 if((pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_ENABLED) ||
|
|
|
514 (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
|
|
|
515 {
|
|
|
516 /* Reset instruction cache */
|
|
|
517 __HAL_FLASH_INSTRUCTION_CACHE_RESET();
|
|
|
518 /* Enable instruction cache */
|
|
|
519 __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
|
|
520 }
|
|
|
521
|
|
|
522 /* Flush data cache */
|
|
|
523 if((pFlash.CacheToReactivate == FLASH_CACHE_DCACHE_ENABLED) ||
|
|
|
524 (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
|
|
|
525 {
|
|
|
526 /* Reset data cache */
|
|
|
527 __HAL_FLASH_DATA_CACHE_RESET();
|
|
|
528 /* Enable data cache */
|
|
|
529 __HAL_FLASH_DATA_CACHE_ENABLE();
|
|
|
530 }
|
|
|
531
|
|
|
532 /* Reset internal variable */
|
|
|
533 pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
|
|
|
534 }
|
|
|
535
|
|
|
536 /**
|
|
|
537 * @brief Configure the write protection of the desired pages.
|
|
|
538 *
|
|
|
539 * @note When the memory read protection level is selected (RDP level = 1),
|
|
|
540 * it is not possible to program or erase Flash memory if the CPU debug
|
|
|
541 * features are connected (JTAG or single wire) or boot code is being
|
|
|
542 * executed from RAM or System flash, even if WRP is not activated.
|
|
|
543 * @note To configure the WRP options, the option lock bit OPTLOCK must be
|
|
|
544 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
|
|
|
545 * @note To validate the WRP options, the option bytes must be reloaded
|
|
|
546 * through the call of the HAL_FLASH_OB_Launch() function.
|
|
|
547 *
|
|
|
548 * @param WRPArea: specifies the area to be configured.
|
|
|
549 * This parameter can be one of the following values:
|
|
|
550 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
|
|
|
551 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
|
|
|
552 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices)
|
|
|
553 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices)
|
|
|
554 *
|
|
|
555 * @param WRPStartOffset: specifies the start page of the write protected area
|
|
|
556 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
|
|
|
557 *
|
|
|
558 * @param WRDPEndOffset: specifies the end page of the write protected area
|
|
|
559 * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
|
|
|
560 *
|
|
|
561 * @retval HAL Status
|
|
|
562 */
|
|
|
563 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
|
|
|
564 {
|
|
|
565 HAL_StatusTypeDef status = HAL_OK;
|
|
|
566
|
|
|
567 /* Check the parameters */
|
|
|
568 assert_param(IS_OB_WRPAREA(WRPArea));
|
|
|
569 assert_param(IS_FLASH_PAGE(WRPStartOffset));
|
|
|
570 assert_param(IS_FLASH_PAGE(WRDPEndOffset));
|
|
|
571
|
|
|
572 /* Wait for last operation to be completed */
|
|
|
573 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
|
574
|
|
|
575 if(status == HAL_OK)
|
|
|
576 {
|
|
|
577 /* Configure the write protected area */
|
|
|
578 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
|
|
|
579 {
|
|
|
580 MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
|
|
|
581 (WRPStartOffset | (WRDPEndOffset << 16)));
|
|
|
582 }
|
|
|
583 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
|
|
|
584 {
|
|
|
585 MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
|
|
|
586 (WRPStartOffset | (WRDPEndOffset << 16)));
|
|
|
587 }
|
|
|
588 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
589 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
|
|
|
590 {
|
|
|
591 MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),
|
|
|
592 (WRPStartOffset | (WRDPEndOffset << 16)));
|
|
|
593 }
|
|
|
594 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
|
|
|
595 {
|
|
|
596 MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),
|
|
|
597 (WRPStartOffset | (WRDPEndOffset << 16)));
|
|
|
598 }
|
|
|
599 #endif
|
|
|
600
|
|
|
601 /* Set OPTSTRT Bit */
|
|
|
602 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
|
|
|
603
|
|
|
604 /* Wait for last operation to be completed */
|
|
|
605 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
|
606
|
|
|
607 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
|
|
|
608 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
|
|
|
609 }
|
|
|
610
|
|
|
611 return status;
|
|
|
612 }
|
|
|
613
|
|
|
614 /**
|
|
|
615 * @brief Set the read protection level.
|
|
|
616 *
|
|
|
617 * @note To configure the RDP level, the option lock bit OPTLOCK must be
|
|
|
618 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
|
|
|
619 * @note To validate the RDP level, the option bytes must be reloaded
|
|
|
620 * through the call of the HAL_FLASH_OB_Launch() function.
|
|
|
621 * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
|
|
|
622 * to go back to level 1 or 0 !!!
|
|
|
623 *
|
|
|
624 * @param RDPLevel: specifies the read protection level.
|
|
|
625 * This parameter can be one of the following values:
|
|
|
626 * @arg OB_RDP_LEVEL_0: No protection
|
|
|
627 * @arg OB_RDP_LEVEL_1: Read protection of the memory
|
|
|
628 * @arg OB_RDP_LEVEL_2: Full chip protection
|
|
|
629 *
|
|
|
630 * @retval HAL status
|
|
|
631 */
|
|
|
632 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
|
|
|
633 {
|
|
|
634 HAL_StatusTypeDef status = HAL_OK;
|
|
|
635
|
|
|
636 /* Check the parameters */
|
|
|
637 assert_param(IS_OB_RDP_LEVEL(RDPLevel));
|
|
|
638
|
|
|
639 /* Wait for last operation to be completed */
|
|
|
640 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
|
641
|
|
|
642 if(status == HAL_OK)
|
|
|
643 {
|
|
|
644 /* Configure the RDP level in the option bytes register */
|
|
|
645 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
|
|
|
646
|
|
|
647 /* Set OPTSTRT Bit */
|
|
|
648 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
|
|
|
649
|
|
|
650 /* Wait for last operation to be completed */
|
|
|
651 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
|
652
|
|
|
653 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
|
|
|
654 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
|
|
|
655 }
|
|
|
656
|
|
|
657 return status;
|
|
|
658 }
|
|
|
659
|
|
|
660 /**
|
|
|
661 * @brief Program the FLASH User Option Byte.
|
|
|
662 *
|
|
|
663 * @note To configure the user option bytes, the option lock bit OPTLOCK must
|
|
|
664 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
|
|
|
665 * @note To validate the user option bytes, the option bytes must be reloaded
|
|
|
666 * through the call of the HAL_FLASH_OB_Launch() function.
|
|
|
667 *
|
|
|
668 * @param UserType: The FLASH User Option Bytes to be modified
|
|
|
669 * @param UserConfig: The FLASH User Option Bytes values:
|
|
|
670 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),
|
|
|
671 * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20),
|
|
|
672 * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
|
|
|
673 *
|
|
|
674 * @retval HAL status
|
|
|
675 */
|
|
|
676 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
|
|
|
677 {
|
|
|
678 uint32_t optr_reg_val = 0;
|
|
|
679 uint32_t optr_reg_mask = 0;
|
|
|
680 HAL_StatusTypeDef status = HAL_OK;
|
|
|
681
|
|
|
682 /* Check the parameters */
|
|
|
683 assert_param(IS_OB_USER_TYPE(UserType));
|
|
|
684
|
|
|
685 /* Wait for last operation to be completed */
|
|
|
686 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
|
687
|
|
|
688 if(status == HAL_OK)
|
|
|
689 {
|
|
|
690 if((UserType & OB_USER_BOR_LEV) != RESET)
|
|
|
691 {
|
|
|
692 /* BOR level option byte should be modified */
|
|
|
693 assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
|
|
|
694
|
|
|
695 /* Set value and mask for BOR level option byte */
|
|
|
696 optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
|
|
|
697 optr_reg_mask |= FLASH_OPTR_BOR_LEV;
|
|
|
698 }
|
|
|
699
|
|
|
700 if((UserType & OB_USER_nRST_STOP) != RESET)
|
|
|
701 {
|
|
|
702 /* nRST_STOP option byte should be modified */
|
|
|
703 assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
|
|
|
704
|
|
|
705 /* Set value and mask for nRST_STOP option byte */
|
|
|
706 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
|
|
|
707 optr_reg_mask |= FLASH_OPTR_nRST_STOP;
|
|
|
708 }
|
|
|
709
|
|
|
710 if((UserType & OB_USER_nRST_STDBY) != RESET)
|
|
|
711 {
|
|
|
712 /* nRST_STDBY option byte should be modified */
|
|
|
713 assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
|
|
|
714
|
|
|
715 /* Set value and mask for nRST_STDBY option byte */
|
|
|
716 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
|
|
|
717 optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
|
|
|
718 }
|
|
|
719
|
|
|
720 if((UserType & OB_USER_nRST_SHDW) != RESET)
|
|
|
721 {
|
|
|
722 /* nRST_SHDW option byte should be modified */
|
|
|
723 assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
|
|
|
724
|
|
|
725 /* Set value and mask for nRST_SHDW option byte */
|
|
|
726 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
|
|
|
727 optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
|
|
|
728 }
|
|
|
729
|
|
|
730 if((UserType & OB_USER_IWDG_SW) != RESET)
|
|
|
731 {
|
|
|
732 /* IWDG_SW option byte should be modified */
|
|
|
733 assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
|
|
|
734
|
|
|
735 /* Set value and mask for IWDG_SW option byte */
|
|
|
736 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
|
|
|
737 optr_reg_mask |= FLASH_OPTR_IWDG_SW;
|
|
|
738 }
|
|
|
739
|
|
|
740 if((UserType & OB_USER_IWDG_STOP) != RESET)
|
|
|
741 {
|
|
|
742 /* IWDG_STOP option byte should be modified */
|
|
|
743 assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
|
|
|
744
|
|
|
745 /* Set value and mask for IWDG_STOP option byte */
|
|
|
746 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
|
|
|
747 optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
|
|
|
748 }
|
|
|
749
|
|
|
750 if((UserType & OB_USER_IWDG_STDBY) != RESET)
|
|
|
751 {
|
|
|
752 /* IWDG_STDBY option byte should be modified */
|
|
|
753 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
|
|
|
754
|
|
|
755 /* Set value and mask for IWDG_STDBY option byte */
|
|
|
756 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
|
|
|
757 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
|
|
|
758 }
|
|
|
759
|
|
|
760 if((UserType & OB_USER_WWDG_SW) != RESET)
|
|
|
761 {
|
|
|
762 /* WWDG_SW option byte should be modified */
|
|
|
763 assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
|
|
|
764
|
|
|
765 /* Set value and mask for WWDG_SW option byte */
|
|
|
766 optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
|
|
|
767 optr_reg_mask |= FLASH_OPTR_WWDG_SW;
|
|
|
768 }
|
|
|
769
|
|
|
770 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
771 if((UserType & OB_USER_BFB2) != RESET)
|
|
|
772 {
|
|
|
773 /* BFB2 option byte should be modified */
|
|
|
774 assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
|
|
|
775
|
|
|
776 /* Set value and mask for BFB2 option byte */
|
|
|
777 optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
|
|
|
778 optr_reg_mask |= FLASH_OPTR_BFB2;
|
|
|
779 }
|
|
|
780
|
|
|
781 if((UserType & OB_USER_DUALBANK) != RESET)
|
|
|
782 {
|
|
|
783 /* DUALBANK option byte should be modified */
|
|
|
784 assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
|
|
|
785
|
|
|
786 /* Set value and mask for DUALBANK option byte */
|
|
|
787 optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
|
|
|
788 optr_reg_mask |= FLASH_OPTR_DUALBANK;
|
|
|
789 }
|
|
|
790 #endif
|
|
|
791
|
|
|
792 if((UserType & OB_USER_nBOOT1) != RESET)
|
|
|
793 {
|
|
|
794 /* nBOOT1 option byte should be modified */
|
|
|
795 assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
|
|
|
796
|
|
|
797 /* Set value and mask for nBOOT1 option byte */
|
|
|
798 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
|
|
|
799 optr_reg_mask |= FLASH_OPTR_nBOOT1;
|
|
|
800 }
|
|
|
801
|
|
|
802 if((UserType & OB_USER_SRAM2_PE) != RESET)
|
|
|
803 {
|
|
|
804 /* SRAM2_PE option byte should be modified */
|
|
|
805 assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
|
|
|
806
|
|
|
807 /* Set value and mask for SRAM2_PE option byte */
|
|
|
808 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
|
|
|
809 optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
|
|
|
810 }
|
|
|
811
|
|
|
812 if((UserType & OB_USER_SRAM2_RST) != RESET)
|
|
|
813 {
|
|
|
814 /* SRAM2_RST option byte should be modified */
|
|
|
815 assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
|
|
|
816
|
|
|
817 /* Set value and mask for SRAM2_RST option byte */
|
|
|
818 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
|
|
|
819 optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
|
|
|
820 }
|
|
|
821
|
|
|
822 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
|
|
|
823 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
|
|
|
824 if((UserType & OB_USER_nSWBOOT0) != RESET)
|
|
|
825 {
|
|
|
826 /* nSWBOOT0 option byte should be modified */
|
|
|
827 assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
|
|
|
828
|
|
|
829 /* Set value and mask for nSWBOOT0 option byte */
|
|
|
830 optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
|
|
|
831 optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
|
|
|
832 }
|
|
|
833
|
|
|
834 if((UserType & OB_USER_nBOOT0) != RESET)
|
|
|
835 {
|
|
|
836 /* nBOOT0 option byte should be modified */
|
|
|
837 assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
|
|
|
838
|
|
|
839 /* Set value and mask for nBOOT0 option byte */
|
|
|
840 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
|
|
|
841 optr_reg_mask |= FLASH_OPTR_nBOOT0;
|
|
|
842 }
|
|
|
843 #endif
|
|
|
844
|
|
|
845 /* Configure the option bytes register */
|
|
|
846 MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
|
|
|
847
|
|
|
848 /* Set OPTSTRT Bit */
|
|
|
849 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
|
|
|
850
|
|
|
851 /* Wait for last operation to be completed */
|
|
|
852 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
|
853
|
|
|
854 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
|
|
|
855 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
|
|
|
856 }
|
|
|
857
|
|
|
858 return status;
|
|
|
859 }
|
|
|
860
|
|
|
861 /**
|
|
|
862 * @brief Configure the Proprietary code readout protection of the desired addresses.
|
|
|
863 *
|
|
|
864 * @note To configure the PCROP options, the option lock bit OPTLOCK must be
|
|
|
865 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
|
|
|
866 * @note To validate the PCROP options, the option bytes must be reloaded
|
|
|
867 * through the call of the HAL_FLASH_OB_Launch() function.
|
|
|
868 *
|
|
|
869 * @param PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).
|
|
|
870 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
|
|
|
871 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
|
|
|
872 *
|
|
|
873 * @param PCROPStartAddr: specifies the start address of the Proprietary code readout protection
|
|
|
874 * This parameter can be an address between begin and end of the bank
|
|
|
875 *
|
|
|
876 * @param PCROPEndAddr: specifies the end address of the Proprietary code readout protection
|
|
|
877 * This parameter can be an address between PCROPStartAddr and end of the bank
|
|
|
878 *
|
|
|
879 * @retval HAL Status
|
|
|
880 */
|
|
|
881 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
|
|
|
882 {
|
|
|
883 HAL_StatusTypeDef status = HAL_OK;
|
|
|
884 uint32_t reg_value = 0;
|
|
|
885 uint32_t bank1_addr;
|
|
|
886 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
887 uint32_t bank2_addr;
|
|
|
888 #endif
|
|
|
889
|
|
|
890 /* Check the parameters */
|
|
|
891 assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
|
|
|
892 assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
|
|
|
893 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
|
|
|
894 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
|
|
|
895
|
|
|
896 /* Wait for last operation to be completed */
|
|
|
897 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
|
898
|
|
|
899 if(status == HAL_OK)
|
|
|
900 {
|
|
|
901 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
902 /* Get the information about the bank swapping */
|
|
|
903 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
|
|
|
904 {
|
|
|
905 bank1_addr = FLASH_BASE;
|
|
|
906 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
|
|
|
907 }
|
|
|
908 else
|
|
|
909 {
|
|
|
910 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
|
|
|
911 bank2_addr = FLASH_BASE;
|
|
|
912 }
|
|
|
913 #else
|
|
|
914 bank1_addr = FLASH_BASE;
|
|
|
915 #endif
|
|
|
916
|
|
|
917 {
|
|
|
918 /* Configure the Proprietary code readout protection */
|
|
|
919 if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
|
|
|
920 {
|
|
|
921 reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
|
|
|
922 MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
|
|
|
923
|
|
|
924 reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
|
|
|
925 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
|
|
|
926 }
|
|
|
927 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
928 else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
|
|
|
929 {
|
|
|
930 reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
|
|
|
931 MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
|
|
|
932
|
|
|
933 reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
|
|
|
934 MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
|
|
|
935 }
|
|
|
936 #endif
|
|
|
937 }
|
|
|
938
|
|
|
939 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
|
|
|
940
|
|
|
941 /* Set OPTSTRT Bit */
|
|
|
942 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
|
|
|
943
|
|
|
944 /* Wait for last operation to be completed */
|
|
|
945 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
|
946
|
|
|
947 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
|
|
|
948 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
|
|
|
949 }
|
|
|
950
|
|
|
951 return status;
|
|
|
952 }
|
|
|
953
|
|
|
954 /**
|
|
|
955 * @brief Return the FLASH Write Protection Option Bytes value.
|
|
|
956 *
|
|
|
957 * @param[in] WRPArea: specifies the area to be returned.
|
|
|
958 * This parameter can be one of the following values:
|
|
|
959 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
|
|
|
960 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
|
|
|
961 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)
|
|
|
962 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)
|
|
|
963 *
|
|
|
964 * @param[out] WRPStartOffset: specifies the address where to copied the start page
|
|
|
965 * of the write protected area
|
|
|
966 *
|
|
|
967 * @param[out] WRDPEndOffset: specifies the address where to copied the end page of
|
|
|
968 * the write protected area
|
|
|
969 *
|
|
|
970 * @retval None
|
|
|
971 */
|
|
|
972 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
|
|
|
973 {
|
|
|
974 /* Get the configuration of the write protected area */
|
|
|
975 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
|
|
|
976 {
|
|
|
977 *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
|
|
|
978 *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);
|
|
|
979 }
|
|
|
980 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
|
|
|
981 {
|
|
|
982 *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
|
|
|
983 *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
|
|
|
984 }
|
|
|
985 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
986 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
|
|
|
987 {
|
|
|
988 *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
|
|
|
989 *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);
|
|
|
990 }
|
|
|
991 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
|
|
|
992 {
|
|
|
993 *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
|
|
|
994 *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);
|
|
|
995 }
|
|
|
996 #endif
|
|
|
997 }
|
|
|
998
|
|
|
999 /**
|
|
|
1000 * @brief Return the FLASH Read Protection level.
|
|
|
1001 * @retval FLASH ReadOut Protection Status:
|
|
|
1002 * This return value can be one of the following values:
|
|
|
1003 * @arg OB_RDP_LEVEL_0: No protection
|
|
|
1004 * @arg OB_RDP_LEVEL_1: Read protection of the memory
|
|
|
1005 * @arg OB_RDP_LEVEL_2: Full chip protection
|
|
|
1006 */
|
|
|
1007 static uint32_t FLASH_OB_GetRDP(void)
|
|
|
1008 {
|
|
|
1009 if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) &&
|
|
|
1010 (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2))
|
|
|
1011 {
|
|
|
1012 return (OB_RDP_LEVEL_1);
|
|
|
1013 }
|
|
|
1014 else
|
|
|
1015 {
|
|
|
1016 return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));
|
|
|
1017 }
|
|
|
1018 }
|
|
|
1019
|
|
|
1020 /**
|
|
|
1021 * @brief Return the FLASH User Option Byte value.
|
|
|
1022 * @retval The FLASH User Option Bytes values:
|
|
|
1023 * For STM32L47x/STM32L48x devices :
|
|
|
1024 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
|
|
|
1025 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
|
|
|
1026 * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
|
|
|
1027 * For STM32L43x/STM32L44x devices :
|
|
|
1028 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
|
|
|
1029 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
|
|
|
1030 * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27).
|
|
|
1031 */
|
|
|
1032 static uint32_t FLASH_OB_GetUser(void)
|
|
|
1033 {
|
|
|
1034 uint32_t user_config = READ_REG(FLASH->OPTR);
|
|
|
1035 CLEAR_BIT(user_config, FLASH_OPTR_RDP);
|
|
|
1036
|
|
|
1037 return user_config;
|
|
|
1038 }
|
|
|
1039
|
|
|
1040 /**
|
|
|
1041 * @brief Return the FLASH Write Protection Option Bytes value.
|
|
|
1042 *
|
|
|
1043 * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).
|
|
|
1044 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
|
|
|
1045 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
|
|
|
1046 *
|
|
|
1047 * @param PCROPStartAddr [out]: specifies the address where to copied the start address
|
|
|
1048 * of the Proprietary code readout protection
|
|
|
1049 *
|
|
|
1050 * @param PCROPEndAddr [out]: specifies the address where to copied the end address of
|
|
|
1051 * the Proprietary code readout protection
|
|
|
1052 *
|
|
|
1053 * @retval None
|
|
|
1054 */
|
|
|
1055 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)
|
|
|
1056 {
|
|
|
1057 uint32_t reg_value = 0;
|
|
|
1058 uint32_t bank1_addr;
|
|
|
1059 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
1060 uint32_t bank2_addr;
|
|
|
1061 #endif
|
|
|
1062
|
|
|
1063 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
1064 /* Get the information about the bank swapping */
|
|
|
1065 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
|
|
|
1066 {
|
|
|
1067 bank1_addr = FLASH_BASE;
|
|
|
1068 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
|
|
|
1069 }
|
|
|
1070 else
|
|
|
1071 {
|
|
|
1072 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
|
|
|
1073 bank2_addr = FLASH_BASE;
|
|
|
1074 }
|
|
|
1075 #else
|
|
|
1076 bank1_addr = FLASH_BASE;
|
|
|
1077 #endif
|
|
|
1078
|
|
|
1079 {
|
|
|
1080 if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
|
|
|
1081 {
|
|
|
1082 reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
|
|
|
1083 *PCROPStartAddr = (reg_value << 3) + bank1_addr;
|
|
|
1084
|
|
|
1085 reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
|
|
|
1086 *PCROPEndAddr = (reg_value << 3) + bank1_addr;
|
|
|
1087 }
|
|
|
1088 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
1089 else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
|
|
|
1090 {
|
|
|
1091 reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
|
|
|
1092 *PCROPStartAddr = (reg_value << 3) + bank2_addr;
|
|
|
1093
|
|
|
1094 reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
|
|
|
1095 *PCROPEndAddr = (reg_value << 3) + bank2_addr;
|
|
|
1096 }
|
|
|
1097 #endif
|
|
|
1098 }
|
|
|
1099
|
|
|
1100 *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
|
|
|
1101 }
|
|
|
1102 /**
|
|
|
1103 * @}
|
|
|
1104 */
|
|
|
1105
|
|
|
1106 /**
|
|
|
1107 * @}
|
|
|
1108 */
|
|
|
1109
|
|
|
1110 #endif /* HAL_FLASH_MODULE_ENABLED */
|
|
|
1111
|
|
|
1112 /**
|
|
|
1113 * @}
|
|
|
1114 */
|
|
|
1115
|
|
|
1116 /**
|
|
|
1117 * @}
|
|
|
1118 */
|
|
|
1119
|
|
|
1120 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
