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1 /**
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2 ******************************************************************************
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3 * @file stm32l431xx.h
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4 * @author MCD Application Team
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5 * @version V1.1.0
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6 * @date 26-February-2016
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7 * @brief CMSIS STM32L431xx Device Peripheral Access Layer Header File.
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8 *
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9 * This file contains:
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10 * - Data structures and the address mapping for all peripherals
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11 * - Peripheral's registers declarations and bits definition
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12 * - Macros to access peripheral�s registers hardware
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13 *
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14 ******************************************************************************
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15 * @attention
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16 *
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17 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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18 *
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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29 *
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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40 *
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41 ******************************************************************************
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42 */
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43
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44 /** @addtogroup CMSIS_Device
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45 * @{
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46 */
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47
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48 /** @addtogroup stm32l431xx
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49 * @{
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50 */
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51
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52 #ifndef __STM32L431xx_H
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53 #define __STM32L431xx_H
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54
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55 #ifdef __cplusplus
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56 extern "C" {
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57 #endif /* __cplusplus */
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58
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59 /** @addtogroup Configuration_section_for_CMSIS
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60 * @{
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61 */
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62
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63 /**
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64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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65 */
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66 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
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67 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
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68 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
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69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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70 #define __FPU_PRESENT 1 /*!< FPU present */
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71
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72 /**
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73 * @}
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74 */
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75
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76 /** @addtogroup Peripheral_interrupt_number_definition
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77 * @{
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78 */
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79
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80 /**
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81 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
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82 * in @ref Library_configuration_section
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83 */
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84 typedef enum
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85 {
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86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
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87 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
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88 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
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89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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96 /****** STM32 specific Interrupt Numbers **********************************************************************/
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97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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98 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
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99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
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100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
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101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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102 RCC_IRQn = 5, /*!< RCC global Interrupt */
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103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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108 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
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109 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
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110 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
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111 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
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112 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
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113 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
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114 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
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115 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
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116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
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117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
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118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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121 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
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122 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
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123 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
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124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
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133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
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134 USART3_IRQn = 39, /*!< USART3 global Interrupt */
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135 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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136 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
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137 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
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138 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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139 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
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140 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
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141 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
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142 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
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143 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
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144 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
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145 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
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146 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
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147 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
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148 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
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149 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
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150 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
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151 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
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152 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
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153 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
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154 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
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155 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
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156 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
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157 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
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158 RNG_IRQn = 80, /*!< RNG global interrupt */
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159 FPU_IRQn = 81, /*!< FPU global interrupt */
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160 CRS_IRQn = 82 /*!< CRS global interrupt */
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161 } IRQn_Type;
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162
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163 /**
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164 * @}
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165 */
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166
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167 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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168 #include "system_stm32l4xx.h"
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169 #include <stdint.h>
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170
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171 /** @addtogroup Peripheral_registers_structures
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172 * @{
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173 */
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174
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175 /**
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176 * @brief Analog to Digital Converter
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177 */
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178
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179 typedef struct
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180 {
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181 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
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182 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
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183 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
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184 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
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185 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
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186 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
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187 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
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188 uint32_t RESERVED1; /*!< Reserved, 0x1C */
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189 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
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190 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
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191 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
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192 uint32_t RESERVED2; /*!< Reserved, 0x2C */
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193 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
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194 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
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195 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
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196 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
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197 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
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198 uint32_t RESERVED3; /*!< Reserved, 0x44 */
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199 uint32_t RESERVED4; /*!< Reserved, 0x48 */
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200 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
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201 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
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202 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
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203 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
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204 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
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205 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
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206 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
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207 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
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208 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
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209 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
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210 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
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211 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
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212 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
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213 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
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214 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
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215 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
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216 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
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217 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
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218
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219 } ADC_TypeDef;
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220
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221 typedef struct
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222 {
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223 uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
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224 uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
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225 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
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226 uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
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227 } ADC_Common_TypeDef;
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228
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229
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230 /**
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231 * @brief Controller Area Network TxMailBox
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232 */
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233
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234 typedef struct
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235 {
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236 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
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237 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
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238 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
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239 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
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240 } CAN_TxMailBox_TypeDef;
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241
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242 /**
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243 * @brief Controller Area Network FIFOMailBox
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244 */
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245
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246 typedef struct
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247 {
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248 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
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249 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
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250 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
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251 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
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252 } CAN_FIFOMailBox_TypeDef;
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253
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254 /**
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255 * @brief Controller Area Network FilterRegister
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256 */
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257
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258 typedef struct
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259 {
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260 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
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261 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
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262 } CAN_FilterRegister_TypeDef;
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263
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264 /**
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265 * @brief Controller Area Network
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266 */
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267
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268 typedef struct
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269 {
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270 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
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271 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
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272 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
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273 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
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274 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
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275 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
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276 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
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277 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
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278 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
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279 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
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280 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
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281 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
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282 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
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283 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
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284 uint32_t RESERVED2; /*!< Reserved, 0x208 */
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285 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
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286 uint32_t RESERVED3; /*!< Reserved, 0x210 */
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287 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
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288 uint32_t RESERVED4; /*!< Reserved, 0x218 */
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289 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
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290 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
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291 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
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292 } CAN_TypeDef;
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293
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294
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295 /**
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296 * @brief Comparator
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297 */
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298
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299 typedef struct
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300 {
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301 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
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302 } COMP_TypeDef;
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303
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304 typedef struct
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305 {
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306 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
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307 } COMP_Common_TypeDef;
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308
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309 /**
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310 * @brief CRC calculation unit
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311 */
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312
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313 typedef struct
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314 {
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315 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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316 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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317 uint8_t RESERVED0; /*!< Reserved, 0x05 */
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318 uint16_t RESERVED1; /*!< Reserved, 0x06 */
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319 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
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320 uint32_t RESERVED2; /*!< Reserved, 0x0C */
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321 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
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322 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
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323 } CRC_TypeDef;
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324
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325 /**
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326 * @brief Clock Recovery System
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327 */
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328 typedef struct
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329 {
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330 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
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331 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
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332 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
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333 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
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334 } CRS_TypeDef;
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335
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336 /**
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337 * @brief Digital to Analog Converter
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338 */
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339
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340 typedef struct
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341 {
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342 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
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343 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
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344 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
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345 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
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346 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
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347 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
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348 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
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349 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
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350 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
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351 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
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352 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
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353 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
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354 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
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355 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
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356 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
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357 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
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358 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
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359 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
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360 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
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361 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
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362 } DAC_TypeDef;
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363
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364
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365 /**
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366 * @brief Debug MCU
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367 */
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368
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369 typedef struct
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370 {
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371 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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372 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
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373 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
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374 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
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375 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
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376 } DBGMCU_TypeDef;
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377
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378
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379 /**
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380 * @brief DMA Controller
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381 */
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382
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383 typedef struct
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384 {
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385 __IO uint32_t CCR; /*!< DMA channel x configuration register */
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386 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
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387 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
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388 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
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389 } DMA_Channel_TypeDef;
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390
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391 typedef struct
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392 {
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393 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
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394 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
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395 } DMA_TypeDef;
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396
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397 typedef struct
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398 {
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399 __IO uint32_t CSELR; /*!< DMA channel selection register */
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400 } DMA_Request_TypeDef;
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401
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402 /* Legacy define */
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403 #define DMA_request_TypeDef DMA_Request_TypeDef
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404
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405 /**
|
|
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406 * @brief External Interrupt/Event Controller
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407 */
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408
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409 typedef struct
|
|
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410 {
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411 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
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412 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
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413 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
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414 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
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415 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
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416 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
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417 uint32_t RESERVED1; /*!< Reserved, 0x18 */
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|
418 uint32_t RESERVED2; /*!< Reserved, 0x1C */
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419 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
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|
420 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
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421 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
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|
422 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
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|
423 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
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424 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
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|
425 } EXTI_TypeDef;
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426
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427
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|
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428 /**
|
|
|
429 * @brief Firewall
|
|
|
430 */
|
|
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431
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432 typedef struct
|
|
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433 {
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434 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
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|
435 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
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|
|
436 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
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|
|
437 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
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|
|
438 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
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|
|
439 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
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|
440 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
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|
|
441 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
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|
|
442 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
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|
|
443 } FIREWALL_TypeDef;
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|
|
444
|
|
|
445
|
|
|
446 /**
|
|
|
447 * @brief FLASH Registers
|
|
|
448 */
|
|
|
449
|
|
|
450 typedef struct
|
|
|
451 {
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|
|
452 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
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|
|
453 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
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|
|
454 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
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|
455 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
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|
|
456 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
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|
|
457 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
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|
|
458 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
|
|
|
459 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
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|
|
460 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
|
|
|
461 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
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|
|
462 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
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|
|
463 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
|
|
|
464 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
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|
|
465 } FLASH_TypeDef;
|
|
|
466
|
|
|
467
|
|
|
468
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|
|
469 /**
|
|
|
470 * @brief General Purpose I/O
|
|
|
471 */
|
|
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472
|
|
|
473 typedef struct
|
|
|
474 {
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|
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475 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
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|
|
476 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
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|
|
477 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
|
|
|
478 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
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|
|
479 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
|
|
480 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
|
|
481 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
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|
|
482 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
|
|
483 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
|
|
484 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
|
|
|
485
|
|
|
486 } GPIO_TypeDef;
|
|
|
487
|
|
|
488
|
|
|
489 /**
|
|
|
490 * @brief Inter-integrated Circuit Interface
|
|
|
491 */
|
|
|
492
|
|
|
493 typedef struct
|
|
|
494 {
|
|
|
495 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
|
|
|
496 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
|
|
|
497 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
|
|
|
498 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
|
|
|
499 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
|
|
|
500 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
|
|
|
501 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
|
|
|
502 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
|
|
|
503 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
|
|
|
504 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
|
|
|
505 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
|
|
|
506 } I2C_TypeDef;
|
|
|
507
|
|
|
508 /**
|
|
|
509 * @brief Independent WATCHDOG
|
|
|
510 */
|
|
|
511
|
|
|
512 typedef struct
|
|
|
513 {
|
|
|
514 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
|
|
|
515 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
|
|
|
516 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
|
|
|
517 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
|
|
|
518 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
|
|
|
519 } IWDG_TypeDef;
|
|
|
520
|
|
|
521 /**
|
|
|
522 * @brief LPTIMER
|
|
|
523 */
|
|
|
524 typedef struct
|
|
|
525 {
|
|
|
526 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
|
|
|
527 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
|
|
|
528 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
|
|
|
529 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
|
|
|
530 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
|
|
|
531 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
|
|
|
532 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
|
|
|
533 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
|
|
|
534 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
|
|
|
535 } LPTIM_TypeDef;
|
|
|
536
|
|
|
537
|
|
|
538 /**
|
|
|
539 * @brief Operational Amplifier (OPAMP)
|
|
|
540 */
|
|
|
541
|
|
|
542 typedef struct
|
|
|
543 {
|
|
|
544 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
|
|
|
545 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
|
|
|
546 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
|
|
|
547 } OPAMP_TypeDef;
|
|
|
548
|
|
|
549 typedef struct
|
|
|
550 {
|
|
|
551 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
|
|
|
552 } OPAMP_Common_TypeDef;
|
|
|
553
|
|
|
554 /**
|
|
|
555 * @brief Power Control
|
|
|
556 */
|
|
|
557
|
|
|
558 typedef struct
|
|
|
559 {
|
|
|
560 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
|
|
|
561 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
|
|
|
562 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
|
|
|
563 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
|
|
|
564 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
|
|
|
565 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
|
|
|
566 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
|
|
|
567 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
|
|
|
568 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
|
|
|
569 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
|
|
|
570 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
|
|
|
571 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
|
|
|
572 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
|
|
|
573 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
|
|
|
574 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
|
|
|
575 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
|
|
|
576 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
|
|
|
577 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
|
|
|
578 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */
|
|
|
579 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */
|
|
|
580 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */
|
|
|
581 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */
|
|
|
582 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
|
|
|
583 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
|
|
|
584 } PWR_TypeDef;
|
|
|
585
|
|
|
586
|
|
|
587 /**
|
|
|
588 * @brief QUAD Serial Peripheral Interface
|
|
|
589 */
|
|
|
590
|
|
|
591 typedef struct
|
|
|
592 {
|
|
|
593 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
|
|
|
594 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
|
|
|
595 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
|
|
|
596 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
|
|
|
597 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
|
|
|
598 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
|
|
|
599 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
|
|
|
600 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
|
|
|
601 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
|
|
|
602 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
|
|
|
603 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
|
|
|
604 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
|
|
|
605 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
|
|
|
606 } QUADSPI_TypeDef;
|
|
|
607
|
|
|
608
|
|
|
609 /**
|
|
|
610 * @brief Reset and Clock Control
|
|
|
611 */
|
|
|
612
|
|
|
613 typedef struct
|
|
|
614 {
|
|
|
615 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
|
|
|
616 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
|
|
|
617 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
|
|
|
618 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
|
|
|
619 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
|
|
|
620 uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */
|
|
|
621 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
|
|
|
622 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
|
|
|
623 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
|
|
|
624 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
|
|
|
625 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
|
|
|
626 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
|
|
|
627 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
|
|
|
628 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
|
|
|
629 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
|
|
|
630 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
|
|
|
631 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
|
|
|
632 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
|
|
|
633 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
|
|
|
634 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
|
|
|
635 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
|
|
|
636 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
|
|
|
637 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
|
|
|
638 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
|
|
|
639 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
|
|
|
640 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
|
|
|
641 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
|
|
|
642 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
|
|
|
643 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
|
|
|
644 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
|
|
|
645 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
|
|
|
646 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
|
|
|
647 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
|
|
|
648 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
|
|
|
649 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
|
|
|
650 __IO uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
|
|
|
651 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
|
|
|
652 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
|
|
|
653 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
|
|
|
654 } RCC_TypeDef;
|
|
|
655
|
|
|
656 /**
|
|
|
657 * @brief Real-Time Clock
|
|
|
658 */
|
|
|
659
|
|
|
660 typedef struct
|
|
|
661 {
|
|
|
662 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
|
|
|
663 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
|
|
|
664 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
|
|
|
665 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
|
|
|
666 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
|
|
|
667 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
|
|
|
668 uint32_t reserved; /*!< Reserved */
|
|
|
669 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
|
|
|
670 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
|
|
|
671 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
|
|
|
672 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
|
|
|
673 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
|
|
|
674 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
|
|
|
675 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
|
|
|
676 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
|
|
|
677 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
|
|
|
678 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
|
|
|
679 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
|
|
|
680 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
|
|
|
681 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
|
|
|
682 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
|
|
|
683 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
|
|
|
684 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
|
|
685 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
|
|
686 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
|
|
687 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
|
|
|
688 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
|
|
|
689 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
|
|
|
690 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
|
|
|
691 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
|
|
|
692 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
|
|
|
693 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
|
|
|
694 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
|
|
|
695 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
|
|
696 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
|
|
697 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
|
|
698 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
|
|
|
699 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
|
|
|
700 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
|
|
|
701 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
|
|
|
702 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
|
|
|
703 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
|
|
|
704 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
|
|
|
705 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
|
|
|
706 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
|
|
|
707 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
|
|
|
708 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
|
|
|
709 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
|
|
|
710 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
|
|
|
711 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
|
|
|
712 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
|
|
|
713 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
|
|
|
714 } RTC_TypeDef;
|
|
|
715
|
|
|
716
|
|
|
717 /**
|
|
|
718 * @brief Serial Audio Interface
|
|
|
719 */
|
|
|
720
|
|
|
721 typedef struct
|
|
|
722 {
|
|
|
723 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
|
|
|
724 } SAI_TypeDef;
|
|
|
725
|
|
|
726 typedef struct
|
|
|
727 {
|
|
|
728 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
|
|
|
729 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
|
|
|
730 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
|
|
|
731 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
|
|
|
732 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
|
|
|
733 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
|
|
|
734 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
|
|
|
735 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
|
|
|
736 } SAI_Block_TypeDef;
|
|
|
737
|
|
|
738
|
|
|
739 /**
|
|
|
740 * @brief Secure digital input/output Interface
|
|
|
741 */
|
|
|
742
|
|
|
743 typedef struct
|
|
|
744 {
|
|
|
745 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
|
|
|
746 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
|
|
|
747 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
|
|
|
748 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
|
|
|
749 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
|
|
|
750 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
|
|
|
751 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
|
|
|
752 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
|
|
|
753 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
|
|
|
754 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
|
|
|
755 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
|
|
|
756 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
|
|
|
757 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
|
|
|
758 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
|
|
|
759 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
|
|
|
760 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
|
|
|
761 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
|
|
|
762 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
|
|
|
763 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
|
|
|
764 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
|
|
|
765 } SDMMC_TypeDef;
|
|
|
766
|
|
|
767
|
|
|
768 /**
|
|
|
769 * @brief Serial Peripheral Interface
|
|
|
770 */
|
|
|
771
|
|
|
772 typedef struct
|
|
|
773 {
|
|
|
774 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
|
|
|
775 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
|
|
776 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
|
|
777 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
|
|
778 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
|
|
|
779 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
|
|
|
780 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
|
|
|
781 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
|
|
|
782 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
|
|
|
783 } SPI_TypeDef;
|
|
|
784
|
|
|
785
|
|
|
786 /**
|
|
|
787 * @brief Single Wire Protocol Master Interface SPWMI
|
|
|
788 */
|
|
|
789
|
|
|
790 typedef struct
|
|
|
791 {
|
|
|
792 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
|
|
|
793 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
|
|
|
794 uint32_t RESERVED1; /*!< Reserved, 0x08 */
|
|
|
795 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
|
|
|
796 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
|
|
|
797 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
|
|
|
798 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
|
|
|
799 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
|
|
|
800 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
|
|
|
801 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
|
|
|
802 } SWPMI_TypeDef;
|
|
|
803
|
|
|
804
|
|
|
805 /**
|
|
|
806 * @brief System configuration controller
|
|
|
807 */
|
|
|
808
|
|
|
809 typedef struct
|
|
|
810 {
|
|
|
811 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
|
|
|
812 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
|
|
|
813 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
|
|
|
814 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
|
|
|
815 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
|
|
|
816 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
|
|
|
817 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
|
|
|
818 } SYSCFG_TypeDef;
|
|
|
819
|
|
|
820
|
|
|
821 /**
|
|
|
822 * @brief TIM
|
|
|
823 */
|
|
|
824
|
|
|
825 typedef struct
|
|
|
826 {
|
|
|
827 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
|
|
|
828 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
|
|
|
829 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
|
|
|
830 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
|
|
|
831 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
|
|
|
832 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
|
|
|
833 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
|
|
|
834 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
|
|
|
835 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
|
|
|
836 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
|
|
|
837 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
|
|
|
838 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
|
|
|
839 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
|
|
|
840 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
|
|
|
841 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
|
|
|
842 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
|
|
|
843 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
|
|
|
844 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
|
|
|
845 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
|
|
|
846 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
|
|
|
847 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
|
|
|
848 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
|
|
|
849 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
|
|
|
850 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
|
|
|
851 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
|
|
|
852 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
|
|
|
853 } TIM_TypeDef;
|
|
|
854
|
|
|
855
|
|
|
856 /**
|
|
|
857 * @brief Touch Sensing Controller (TSC)
|
|
|
858 */
|
|
|
859
|
|
|
860 typedef struct
|
|
|
861 {
|
|
|
862 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
|
|
|
863 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
|
|
|
864 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
|
|
|
865 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
|
|
|
866 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
|
|
|
867 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
|
|
|
868 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
|
|
|
869 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
|
|
|
870 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
|
|
|
871 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
|
|
|
872 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
|
|
|
873 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
|
|
|
874 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
|
|
|
875 __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
|
|
|
876 } TSC_TypeDef;
|
|
|
877
|
|
|
878 /**
|
|
|
879 * @brief Universal Synchronous Asynchronous Receiver Transmitter
|
|
|
880 */
|
|
|
881
|
|
|
882 typedef struct
|
|
|
883 {
|
|
|
884 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
|
|
|
885 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
|
|
|
886 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
|
|
|
887 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
|
|
|
888 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
|
|
|
889 uint16_t RESERVED2; /*!< Reserved, 0x12 */
|
|
|
890 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
|
|
|
891 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
|
|
|
892 uint16_t RESERVED3; /*!< Reserved, 0x1A */
|
|
|
893 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
|
|
|
894 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
|
|
|
895 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
|
|
|
896 uint16_t RESERVED4; /*!< Reserved, 0x26 */
|
|
|
897 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
|
|
|
898 uint16_t RESERVED5; /*!< Reserved, 0x2A */
|
|
|
899 } USART_TypeDef;
|
|
|
900
|
|
|
901 /**
|
|
|
902 * @brief VREFBUF
|
|
|
903 */
|
|
|
904
|
|
|
905 typedef struct
|
|
|
906 {
|
|
|
907 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
|
|
|
908 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
|
|
|
909 } VREFBUF_TypeDef;
|
|
|
910
|
|
|
911 /**
|
|
|
912 * @brief Window WATCHDOG
|
|
|
913 */
|
|
|
914
|
|
|
915 typedef struct
|
|
|
916 {
|
|
|
917 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
|
|
|
918 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
|
|
|
919 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
|
|
|
920 } WWDG_TypeDef;
|
|
|
921
|
|
|
922 /**
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923 * @brief RNG
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924 */
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925
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926 typedef struct
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927 {
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928 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
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929 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
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930 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
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931 } RNG_TypeDef;
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932
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933 /**
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934 * @}
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935 */
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936
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937 /** @addtogroup Peripheral_memory_map
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938 * @{
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939 */
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940 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
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941 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address*/
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942 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
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943 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address*/
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944 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
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945 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
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946 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
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947 #define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
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948
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949 /* Legacy defines */
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950 #define SRAM_BASE SRAM1_BASE
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951 #define SRAM_BB_BASE SRAM1_BB_BASE
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952
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953 #define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */
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954 #define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */
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955
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956 /*!< Peripheral memory map */
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957 #define APB1PERIPH_BASE PERIPH_BASE
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958 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
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959 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
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960 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
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961
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962
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963 /*!< APB1 peripherals */
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964 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
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965 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
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966 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
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967 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
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968 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
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969 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
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970 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
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971 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
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972 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
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973 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
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974 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
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975 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
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976 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
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977 #define CRS_BASE (APB1PERIPH_BASE + 0x6000U)
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978 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
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979 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
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980 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
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981 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
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982 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
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983 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
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984 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
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985 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
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986 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
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987 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
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988
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989
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990 /*!< APB2 peripherals */
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991 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
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992 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
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993 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
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994 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
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995 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
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996 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
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997 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
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998 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
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999 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
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1000 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
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1001 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
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1002 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
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1003 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
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1004 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
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1005 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
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|
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1006
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|
|
1007 /*!< AHB1 peripherals */
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|
1008 #define DMA1_BASE (AHB1PERIPH_BASE)
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|
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1009 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
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1010 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
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1011 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
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1012 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
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|
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1013 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
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|
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1014
|
|
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1015
|
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1016 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
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1017 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
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|
|
1018 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
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|
|
1019 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
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|
|
1020 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
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|
|
1021 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
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1022 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
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|
|
1023 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
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|
|
1024
|
|
|
1025
|
|
|
1026 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
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|
|
1027 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
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|
|
1028 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
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|
|
1029 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
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|
|
1030 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
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|
|
1031 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
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|
|
1032 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
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|
|
1033 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
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|
|
1034
|
|
|
1035
|
|
|
1036 /*!< AHB2 peripherals */
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|
|
1037 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
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|
|
1038 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
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|
|
1039 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
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|
|
1040 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
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|
|
1041 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
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|
|
1042 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
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|
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1043
|
|
|
1044
|
|
|
1045 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
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|
|
1046 #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
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|
|
1047
|
|
|
1048
|
|
|
1049 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
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|
|
1050
|
|
|
1051
|
|
|
1052 /* Debug MCU registers base address */
|
|
|
1053 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
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|
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1054
|
|
|
1055
|
|
|
1056 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
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|
|
1057 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
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|
|
1058 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
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|
|
1059 /**
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|
|
1060 * @}
|
|
|
1061 */
|
|
|
1062
|
|
|
1063 /** @addtogroup Peripheral_declaration
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|
|
1064 * @{
|
|
|
1065 */
|
|
|
1066 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
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|
|
1067 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
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|
|
1068 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
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|
|
1069 #define RTC ((RTC_TypeDef *) RTC_BASE)
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|
|
1070 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
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|
|
1071 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
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|
|
1072 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
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|
|
1073 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
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|
|
1074 #define USART2 ((USART_TypeDef *) USART2_BASE)
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|
|
1075 #define USART3 ((USART_TypeDef *) USART3_BASE)
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|
|
1076 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
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|
|
1077 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
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|
|
1078 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
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|
|
1079 #define CRS ((CRS_TypeDef *) CRS_BASE)
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|
|
1080 #define CAN ((CAN_TypeDef *) CAN1_BASE)
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|
|
1081 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
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|
|
1082 #define PWR ((PWR_TypeDef *) PWR_BASE)
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|
|
1083 #define DAC ((DAC_TypeDef *) DAC1_BASE)
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|
|
1084 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
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|
|
1085 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
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|
|
1086 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
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|
|
1087 #define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
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|
|
1088 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
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|
|
1089 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
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|
|
1090 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
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|
|
1091 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
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|
|
1092
|
|
|
1093 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
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|
|
1094 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
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|
|
1095 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
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|
|
1096 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
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|
|
1097 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
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|
|
1098 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
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|
|
1099 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
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|
|
1100 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
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|
|
1101 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
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|
|
1102 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
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|
|
1103 #define USART1 ((USART_TypeDef *) USART1_BASE)
|
|
|
1104 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
|
|
|
1105 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
|
|
|
1106 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
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|
|
1107 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
|
|
|
1108 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
|
|
|
1109 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
|
|
1110 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
|
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|
1111 #define RCC ((RCC_TypeDef *) RCC_BASE)
|
|
|
1112 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
|
|
1113 #define CRC ((CRC_TypeDef *) CRC_BASE)
|
|
|
1114 #define TSC ((TSC_TypeDef *) TSC_BASE)
|
|
|
1115
|
|
|
1116 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
|
|
1117 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
|
|
1118 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
|
|
1119 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
|
|
1120 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
|
|
1121 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
|
|
|
1122 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
|
|
1123 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
|
|
|
1124 #define RNG ((RNG_TypeDef *) RNG_BASE)
|
|
|
1125
|
|
|
1126
|
|
|
1127 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
|
|
|
1128 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
|
|
|
1129 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
|
|
|
1130 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
|
|
|
1131 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
|
|
|
1132 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
|
|
|
1133 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
|
|
|
1134 #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
|
|
|
1135
|
|
|
1136
|
|
|
1137 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
|
|
|
1138 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
|
|
|
1139 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
|
|
|
1140 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
|
|
|
1141 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
|
|
|
1142 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
|
|
|
1143 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
|
|
|
1144 #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
|
|
|
1145
|
|
|
1146
|
|
|
1147
|
|
|
1148 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
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|
|
1149
|
|
|
1150 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
|
|
1151
|
|
|
1152 /**
|
|
|
1153 * @}
|
|
|
1154 */
|
|
|
1155
|
|
|
1156 /** @addtogroup Exported_constants
|
|
|
1157 * @{
|
|
|
1158 */
|
|
|
1159
|
|
|
1160 /** @addtogroup Peripheral_Registers_Bits_Definition
|
|
|
1161 * @{
|
|
|
1162 */
|
|
|
1163
|
|
|
1164 /******************************************************************************/
|
|
|
1165 /* Peripheral Registers_Bits_Definition */
|
|
|
1166 /******************************************************************************/
|
|
|
1167
|
|
|
1168 /******************************************************************************/
|
|
|
1169 /* */
|
|
|
1170 /* Analog to Digital Converter */
|
|
|
1171 /* */
|
|
|
1172 /******************************************************************************/
|
|
|
1173
|
|
|
1174 /*
|
|
|
1175 * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
|
|
|
1176 */
|
|
|
1177 /* Note: No specific macro feature on this device */
|
|
|
1178
|
|
|
1179 /******************** Bit definition for ADC_ISR register *******************/
|
|
|
1180 #define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC ready flag */
|
|
|
1181 #define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling flag */
|
|
|
1182 #define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion flag */
|
|
|
1183 #define ADC_ISR_EOS ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions flag */
|
|
|
1184 #define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< ADC group regular overrun flag */
|
|
|
1185 #define ADC_ISR_JEOC ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion flag */
|
|
|
1186 #define ADC_ISR_JEOS ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions flag */
|
|
|
1187 #define ADC_ISR_AWD1 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 flag */
|
|
|
1188 #define ADC_ISR_AWD2 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 flag */
|
|
|
1189 #define ADC_ISR_AWD3 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 flag */
|
|
|
1190 #define ADC_ISR_JQOVF ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow flag */
|
|
|
1191
|
|
|
1192 /******************** Bit definition for ADC_IER register *******************/
|
|
|
1193 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC ready interrupt */
|
|
|
1194 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling interrupt */
|
|
|
1195 #define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion interrupt */
|
|
|
1196 #define ADC_IER_EOSIE ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions interrupt */
|
|
|
1197 #define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< ADC group regular overrun interrupt */
|
|
|
1198 #define ADC_IER_JEOCIE ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion interrupt */
|
|
|
1199 #define ADC_IER_JEOSIE ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions interrupt */
|
|
|
1200 #define ADC_IER_AWD1IE ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 interrupt */
|
|
|
1201 #define ADC_IER_AWD2IE ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 interrupt */
|
|
|
1202 #define ADC_IER_AWD3IE ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 interrupt */
|
|
|
1203 #define ADC_IER_JQOVFIE ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow interrupt */
|
|
|
1204
|
|
|
1205 /* Legacy defines */
|
|
|
1206 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
|
|
|
1207 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
|
|
|
1208 #define ADC_IER_EOC (ADC_IER_EOCIE)
|
|
|
1209 #define ADC_IER_EOS (ADC_IER_EOSIE)
|
|
|
1210 #define ADC_IER_OVR (ADC_IER_OVRIE)
|
|
|
1211 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
|
|
|
1212 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
|
|
|
1213 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
|
|
|
1214 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
|
|
|
1215 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
|
|
|
1216 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
|
|
|
1217
|
|
|
1218 /******************** Bit definition for ADC_CR register ********************/
|
|
|
1219 #define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable */
|
|
|
1220 #define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable */
|
|
|
1221 #define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC group regular conversion start */
|
|
|
1222 #define ADC_CR_JADSTART ((uint32_t)0x00000008U) /*!< ADC group injected conversion start */
|
|
|
1223 #define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC group regular conversion stop */
|
|
|
1224 #define ADC_CR_JADSTP ((uint32_t)0x00000020U) /*!< ADC group injected conversion stop */
|
|
|
1225 #define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC voltage regulator enable */
|
|
|
1226 #define ADC_CR_DEEPPWD ((uint32_t)0x20000000U) /*!< ADC deep power down enable */
|
|
|
1227 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000U) /*!< ADC differential mode for calibration */
|
|
|
1228 #define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */
|
|
|
1229
|
|
|
1230 /******************** Bit definition for ADC_CFGR register ******************/
|
|
|
1231 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001U) /*!< ADC DMA transfer enable */
|
|
|
1232 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002U) /*!< ADC DMA transfer configuration */
|
|
|
1233
|
|
|
1234 #define ADC_CFGR_RES ((uint32_t)0x00000018U) /*!< ADC data resolution */
|
|
|
1235 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008U) /*!< bit 0 */
|
|
|
1236 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010U) /*!< bit 1 */
|
|
|
1237
|
|
|
1238 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020U) /*!< ADC data alignement */
|
|
|
1239
|
|
|
1240 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0U) /*!< ADC group regular external trigger source */
|
|
|
1241 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1242 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1243 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1244 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1245
|
|
|
1246 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00U) /*!< ADC group regular external trigger polarity */
|
|
|
1247 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400U) /*!< bit 0 */
|
|
|
1248 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800U) /*!< bit 1 */
|
|
|
1249
|
|
|
1250 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000U) /*!< ADC group regular overrun configuration */
|
|
|
1251 #define ADC_CFGR_CONT ((uint32_t)0x00002000U) /*!< ADC group regular continuous conversion mode */
|
|
|
1252 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000U) /*!< ADC low power auto wait */
|
|
|
1253
|
|
|
1254 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000U) /*!< ADC group regular sequencer discontinuous mode */
|
|
|
1255
|
|
|
1256 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000U) /*!< ADC group regular sequencer discontinuous number of ranks */
|
|
|
1257 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000U) /*!< bit 0 */
|
|
|
1258 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000U) /*!< bit 1 */
|
|
|
1259 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000U) /*!< bit 2 */
|
|
|
1260
|
|
|
1261 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000U) /*!< ADC group injected sequencer discontinuous mode */
|
|
|
1262 #define ADC_CFGR_JQM ((uint32_t)0x00200000U) /*!< ADC group injected contexts queue mode */
|
|
|
1263 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
|
|
|
1264 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */
|
|
|
1265 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */
|
|
|
1266 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000U) /*!< ADC group injected automatic trigger mode */
|
|
|
1267
|
|
|
1268 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000U) /*!< ADC analog watchdog 1 monitored channel selection */
|
|
|
1269 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
|
|
|
1270 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
|
|
|
1271 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
|
|
|
1272 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
|
|
|
1273 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
|
|
|
1274
|
|
|
1275 #define ADC_CFGR_JQDIS ((uint32_t)0x80000000U) /*!< ADC group injected contexts queue disable */
|
|
|
1276
|
|
|
1277 /******************** Bit definition for ADC_CFGR2 register *****************/
|
|
|
1278 #define ADC_CFGR2_ROVSE ((uint32_t)0x00000001U) /*!< ADC oversampler enable on scope ADC group regular */
|
|
|
1279 #define ADC_CFGR2_JOVSE ((uint32_t)0x00000002U) /*!< ADC oversampler enable on scope ADC group injected */
|
|
|
1280
|
|
|
1281 #define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< ADC oversampling ratio */
|
|
|
1282 #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< bit 0 */
|
|
|
1283 #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< bit 1 */
|
|
|
1284 #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< bit 2 */
|
|
|
1285
|
|
|
1286 #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< ADC oversampling shift */
|
|
|
1287 #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< bit 0 */
|
|
|
1288 #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< bit 1 */
|
|
|
1289 #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< bit 2 */
|
|
|
1290 #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< bit 3 */
|
|
|
1291
|
|
|
1292 #define ADC_CFGR2_TROVS ((uint32_t)0x00000200U) /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
|
|
|
1293 #define ADC_CFGR2_ROVSM ((uint32_t)0x00000400U) /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
|
|
|
1294
|
|
|
1295 /******************** Bit definition for ADC_SMPR1 register *****************/
|
|
|
1296 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */
|
|
|
1297 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1298 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1299 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1300
|
|
|
1301 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */
|
|
|
1302 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008U) /*!< bit 0 */
|
|
|
1303 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010U) /*!< bit 1 */
|
|
|
1304 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020U) /*!< bit 2 */
|
|
|
1305
|
|
|
1306 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */
|
|
|
1307 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1308 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1309 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1310
|
|
|
1311 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */
|
|
|
1312 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200U) /*!< bit 0 */
|
|
|
1313 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400U) /*!< bit 1 */
|
|
|
1314 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800U) /*!< bit 2 */
|
|
|
1315
|
|
|
1316 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */
|
|
|
1317 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1318 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1319 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1320
|
|
|
1321 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */
|
|
|
1322 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000U) /*!< bit 0 */
|
|
|
1323 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000U) /*!< bit 1 */
|
|
|
1324 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000U) /*!< bit 2 */
|
|
|
1325
|
|
|
1326 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */
|
|
|
1327 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1328 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1329 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1330
|
|
|
1331 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */
|
|
|
1332 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000U) /*!< bit 0 */
|
|
|
1333 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000U) /*!< bit 1 */
|
|
|
1334 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000U) /*!< bit 2 */
|
|
|
1335
|
|
|
1336 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */
|
|
|
1337 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1338 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1339 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1340
|
|
|
1341 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */
|
|
|
1342 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000U) /*!< bit 0 */
|
|
|
1343 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000U) /*!< bit 1 */
|
|
|
1344 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000U) /*!< bit 2 */
|
|
|
1345
|
|
|
1346 /******************** Bit definition for ADC_SMPR2 register *****************/
|
|
|
1347 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */
|
|
|
1348 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1349 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1350 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1351
|
|
|
1352 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */
|
|
|
1353 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< bit 0 */
|
|
|
1354 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< bit 1 */
|
|
|
1355 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< bit 2 */
|
|
|
1356
|
|
|
1357 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */
|
|
|
1358 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1359 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1360 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1361
|
|
|
1362 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */
|
|
|
1363 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< bit 0 */
|
|
|
1364 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< bit 1 */
|
|
|
1365 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< bit 2 */
|
|
|
1366
|
|
|
1367 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */
|
|
|
1368 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1369 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1370 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1371
|
|
|
1372 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 15 sampling time selection */
|
|
|
1373 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< bit 0 */
|
|
|
1374 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< bit 1 */
|
|
|
1375 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< bit 2 */
|
|
|
1376
|
|
|
1377 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */
|
|
|
1378 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1379 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1380 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1381
|
|
|
1382 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */
|
|
|
1383 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< bit 0 */
|
|
|
1384 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< bit 1 */
|
|
|
1385 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< bit 2 */
|
|
|
1386
|
|
|
1387 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */
|
|
|
1388 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1389 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1390 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1391
|
|
|
1392 /******************** Bit definition for ADC_TR1 register *******************/
|
|
|
1393 #define ADC_TR1_LT1 ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */
|
|
|
1394 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1395 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1396 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1397 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1398 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1399 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1400 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1401 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1402 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1403 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1404 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1405 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1406
|
|
|
1407 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000U) /*!< ADC Analog watchdog 1 threshold high */
|
|
|
1408 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
1409 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
1410 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000U) /*!< bit 2 */
|
|
|
1411 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000U) /*!< bit 3 */
|
|
|
1412 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000U) /*!< bit 4 */
|
|
|
1413 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000U) /*!< bit 5 */
|
|
|
1414 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000U) /*!< bit 6 */
|
|
|
1415 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000U) /*!< bit 7 */
|
|
|
1416 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000U) /*!< bit 8 */
|
|
|
1417 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000U) /*!< bit 9 */
|
|
|
1418 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000U) /*!< bit 10 */
|
|
|
1419 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000U) /*!< bit 11 */
|
|
|
1420
|
|
|
1421 /******************** Bit definition for ADC_TR2 register *******************/
|
|
|
1422 #define ADC_TR2_LT2 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 2 threshold low */
|
|
|
1423 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1424 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1425 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1426 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1427 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1428 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1429 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1430 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1431
|
|
|
1432 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 2 threshold high */
|
|
|
1433 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
1434 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
1435 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000U) /*!< bit 2 */
|
|
|
1436 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000U) /*!< bit 3 */
|
|
|
1437 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000U) /*!< bit 4 */
|
|
|
1438 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000U) /*!< bit 5 */
|
|
|
1439 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000U) /*!< bit 6 */
|
|
|
1440 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000U) /*!< bit 7 */
|
|
|
1441
|
|
|
1442 /******************** Bit definition for ADC_TR3 register *******************/
|
|
|
1443 #define ADC_TR3_LT3 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 3 threshold low */
|
|
|
1444 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1445 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1446 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1447 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1448 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1449 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1450 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1451 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1452
|
|
|
1453 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 3 threshold high */
|
|
|
1454 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
1455 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
1456 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000U) /*!< bit 2 */
|
|
|
1457 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000U) /*!< bit 3 */
|
|
|
1458 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000U) /*!< bit 4 */
|
|
|
1459 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000U) /*!< bit 5 */
|
|
|
1460 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000U) /*!< bit 6 */
|
|
|
1461 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000U) /*!< bit 7 */
|
|
|
1462
|
|
|
1463 /******************** Bit definition for ADC_SQR1 register ******************/
|
|
|
1464 #define ADC_SQR1_L ((uint32_t)0x0000000FU) /*!< ADC group regular sequencer scan length */
|
|
|
1465 #define ADC_SQR1_L_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1466 #define ADC_SQR1_L_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1467 #define ADC_SQR1_L_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1468 #define ADC_SQR1_L_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1469
|
|
|
1470 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 1 */
|
|
|
1471 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1472 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1473 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1474 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1475 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400U) /*!< bit 4 */
|
|
|
1476
|
|
|
1477 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 2 */
|
|
|
1478 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1479 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1480 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1481 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000U) /*!< bit 3 */
|
|
|
1482 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000U) /*!< bit 4 */
|
|
|
1483
|
|
|
1484 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 3 */
|
|
|
1485 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1486 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1487 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1488 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000U) /*!< bit 3 */
|
|
|
1489 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000U) /*!< bit 4 */
|
|
|
1490
|
|
|
1491 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 4 */
|
|
|
1492 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1493 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1494 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1495 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000U) /*!< bit 3 */
|
|
|
1496 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000U) /*!< bit 4 */
|
|
|
1497
|
|
|
1498 /******************** Bit definition for ADC_SQR2 register ******************/
|
|
|
1499 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 5 */
|
|
|
1500 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1501 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1502 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1503 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1504 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1505
|
|
|
1506 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 6 */
|
|
|
1507 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1508 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1509 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1510 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1511 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400U) /*!< bit 4 */
|
|
|
1512
|
|
|
1513 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 7 */
|
|
|
1514 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1515 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1516 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1517 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000U) /*!< bit 3 */
|
|
|
1518 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000U) /*!< bit 4 */
|
|
|
1519
|
|
|
1520 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 8 */
|
|
|
1521 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1522 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1523 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1524 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000U) /*!< bit 3 */
|
|
|
1525 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000U) /*!< bit 4 */
|
|
|
1526
|
|
|
1527 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 9 */
|
|
|
1528 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1529 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1530 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1531 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000U) /*!< bit 3 */
|
|
|
1532 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000U) /*!< bit 4 */
|
|
|
1533
|
|
|
1534 /******************** Bit definition for ADC_SQR3 register ******************/
|
|
|
1535 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 10 */
|
|
|
1536 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1537 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1538 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1539 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1540 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1541
|
|
|
1542 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 11 */
|
|
|
1543 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1544 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1545 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1546 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1547 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400U) /*!< bit 4 */
|
|
|
1548
|
|
|
1549 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 12 */
|
|
|
1550 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1551 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1552 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1553 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000U) /*!< bit 3 */
|
|
|
1554 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000U) /*!< bit 4 */
|
|
|
1555
|
|
|
1556 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 13 */
|
|
|
1557 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1558 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1559 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1560 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000U) /*!< bit 3 */
|
|
|
1561 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000U) /*!< bit 4 */
|
|
|
1562
|
|
|
1563 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 14 */
|
|
|
1564 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1565 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1566 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1567 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000U) /*!< bit 3 */
|
|
|
1568 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000U) /*!< bit 4 */
|
|
|
1569
|
|
|
1570 /******************** Bit definition for ADC_SQR4 register ******************/
|
|
|
1571 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 15 */
|
|
|
1572 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1573 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1574 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1575 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1576 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010U) /*!<5 bit 4 */
|
|
|
1577
|
|
|
1578 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 16 */
|
|
|
1579 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1580 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1581 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1582 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1583 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400U) /*!< bit 4 */
|
|
|
1584
|
|
|
1585 /******************** Bit definition for ADC_DR register ********************/
|
|
|
1586 #define ADC_DR_RDATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */
|
|
|
1587 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1588 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1589 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1590 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1591 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1592 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1593 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1594 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1595 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1596 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1597 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1598 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1599 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
|
|
|
1600 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
|
|
|
1601 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
|
|
|
1602 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
|
|
|
1603
|
|
|
1604 /******************** Bit definition for ADC_JSQR register ******************/
|
|
|
1605 #define ADC_JSQR_JL ((uint32_t)0x00000003U) /*!< ADC group injected sequencer scan length */
|
|
|
1606 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1607 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1608
|
|
|
1609 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003CU) /*!< ADC group injected external trigger source */
|
|
|
1610 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004U) /*!< bit 0 */
|
|
|
1611 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008U) /*!< bit 1 */
|
|
|
1612 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010U) /*!< bit 2 */
|
|
|
1613 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020U) /*!< bit 3 */
|
|
|
1614
|
|
|
1615 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0U) /*!< ADC group injected external trigger polarity */
|
|
|
1616 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1617 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1618
|
|
|
1619 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00U) /*!< ADC group injected sequencer rank 1 */
|
|
|
1620 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100U) /*!< bit 0 */
|
|
|
1621 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200U) /*!< bit 1 */
|
|
|
1622 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400U) /*!< bit 2 */
|
|
|
1623 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800U) /*!< bit 3 */
|
|
|
1624 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000U) /*!< bit 4 */
|
|
|
1625
|
|
|
1626 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000U) /*!< ADC group injected sequencer rank 2 */
|
|
|
1627 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000U) /*!< bit 0 */
|
|
|
1628 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000U) /*!< bit 1 */
|
|
|
1629 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000U) /*!< bit 2 */
|
|
|
1630 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000U) /*!< bit 3 */
|
|
|
1631 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000U) /*!< bit 4 */
|
|
|
1632
|
|
|
1633 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000U) /*!< ADC group injected sequencer rank 3 */
|
|
|
1634 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000U) /*!< bit 0 */
|
|
|
1635 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000U) /*!< bit 1 */
|
|
|
1636 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000U) /*!< bit 2 */
|
|
|
1637 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000U) /*!< bit 3 */
|
|
|
1638 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000U) /*!< bit 4 */
|
|
|
1639
|
|
|
1640 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000U) /*!< ADC group injected sequencer rank 4 */
|
|
|
1641 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000U) /*!< bit 0 */
|
|
|
1642 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000U) /*!< bit 1 */
|
|
|
1643 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000U) /*!< bit 2 */
|
|
|
1644 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000U) /*!< bit 3 */
|
|
|
1645 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000U) /*!< bit 4 */
|
|
|
1646
|
|
|
1647
|
|
|
1648 /******************** Bit definition for ADC_OFR1 register ******************/
|
|
|
1649 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC offset number 1 offset level */
|
|
|
1650 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1651 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1652 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1653 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1654 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1655 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1656 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1657 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1658 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1659 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1660 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1661 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1662
|
|
|
1663 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 1 channel selection */
|
|
|
1664 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
|
|
|
1665 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
|
|
|
1666 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
|
|
|
1667 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
|
|
|
1668 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
|
|
|
1669
|
|
|
1670 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000U) /*!< ADC offset number 1 enable */
|
|
|
1671
|
|
|
1672 /******************** Bit definition for ADC_OFR2 register ******************/
|
|
|
1673 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC offset number 2 offset level */
|
|
|
1674 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1675 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1676 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1677 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1678 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1679 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1680 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1681 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1682 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1683 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1684 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1685 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1686
|
|
|
1687 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 2 channel selection */
|
|
|
1688 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
|
|
|
1689 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
|
|
|
1690 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
|
|
|
1691 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
|
|
|
1692 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
|
|
|
1693
|
|
|
1694 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000U) /*!< ADC offset number 2 enable */
|
|
|
1695
|
|
|
1696 /******************** Bit definition for ADC_OFR3 register ******************/
|
|
|
1697 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC offset number 3 offset level */
|
|
|
1698 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1699 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1700 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1701 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1702 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1703 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1704 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1705 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1706 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1707 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1708 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1709 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1710
|
|
|
1711 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 3 channel selection */
|
|
|
1712 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
|
|
|
1713 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
|
|
|
1714 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
|
|
|
1715 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
|
|
|
1716 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
|
|
|
1717
|
|
|
1718 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000U) /*!< ADC offset number 3 enable */
|
|
|
1719
|
|
|
1720 /******************** Bit definition for ADC_OFR4 register ******************/
|
|
|
1721 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC offset number 4 offset level */
|
|
|
1722 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1723 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1724 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1725 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1726 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1727 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1728 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1729 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1730 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1731 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1732 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1733 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1734
|
|
|
1735 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 4 channel selection */
|
|
|
1736 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
|
|
|
1737 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
|
|
|
1738 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
|
|
|
1739 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
|
|
|
1740 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
|
|
|
1741
|
|
|
1742 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000U) /*!< ADC offset number 4 enable */
|
|
|
1743
|
|
|
1744 /******************** Bit definition for ADC_JDR1 register ******************/
|
|
|
1745 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */
|
|
|
1746 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1747 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1748 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1749 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1750 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1751 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1752 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1753 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1754 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1755 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1756 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1757 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1758 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
|
|
|
1759 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
|
|
|
1760 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
|
|
|
1761 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
|
|
|
1762
|
|
|
1763 /******************** Bit definition for ADC_JDR2 register ******************/
|
|
|
1764 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */
|
|
|
1765 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1766 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1767 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1768 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1769 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1770 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1771 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1772 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1773 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1774 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1775 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1776 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1777 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
|
|
|
1778 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
|
|
|
1779 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
|
|
|
1780 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
|
|
|
1781
|
|
|
1782 /******************** Bit definition for ADC_JDR3 register ******************/
|
|
|
1783 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */
|
|
|
1784 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1785 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1786 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1787 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1788 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1789 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1790 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1791 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1792 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1793 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1794 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1795 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1796 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
|
|
|
1797 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
|
|
|
1798 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
|
|
|
1799 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
|
|
|
1800
|
|
|
1801 /******************** Bit definition for ADC_JDR4 register ******************/
|
|
|
1802 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */
|
|
|
1803 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1804 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1805 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1806 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1807 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1808 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1809 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1810 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1811 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1812 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1813 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1814 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1815 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
|
|
|
1816 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
|
|
|
1817 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
|
|
|
1818 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
|
|
|
1819
|
|
|
1820 /******************** Bit definition for ADC_AWD2CR register ****************/
|
|
|
1821 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 2 monitored channel selection */
|
|
|
1822 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 2 monitoring channel 0 */
|
|
|
1823 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 2 monitoring channel 1 */
|
|
|
1824 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 2 monitoring channel 2 */
|
|
|
1825 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 2 monitoring channel 3 */
|
|
|
1826 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 2 monitoring channel 4 */
|
|
|
1827 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 2 monitoring channel 5 */
|
|
|
1828 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 2 monitoring channel 6 */
|
|
|
1829 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 2 monitoring channel 7 */
|
|
|
1830 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 monitoring channel 8 */
|
|
|
1831 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 2 monitoring channel 9 */
|
|
|
1832 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 2 monitoring channel 10 */
|
|
|
1833 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 2 monitoring channel 11 */
|
|
|
1834 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 2 monitoring channel 12 */
|
|
|
1835 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 2 monitoring channel 13 */
|
|
|
1836 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 2 monitoring channel 14 */
|
|
|
1837 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 2 monitoring channel 15 */
|
|
|
1838 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 2 monitoring channel 16 */
|
|
|
1839 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 2 monitoring channel 17 */
|
|
|
1840 #define ADC_AWD2CR_AWD2CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 2 monitoring channel 18 */
|
|
|
1841
|
|
|
1842 /******************** Bit definition for ADC_AWD3CR register ****************/
|
|
|
1843 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 3 monitored channel selection */
|
|
|
1844 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 3 monitoring channel 0 */
|
|
|
1845 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 3 monitoring channel 1 */
|
|
|
1846 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 3 monitoring channel 2 */
|
|
|
1847 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 3 monitoring channel 3 */
|
|
|
1848 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 3 monitoring channel 4 */
|
|
|
1849 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 3 monitoring channel 5 */
|
|
|
1850 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 3 monitoring channel 6 */
|
|
|
1851 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 3 monitoring channel 7 */
|
|
|
1852 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 3 monitoring channel 8 */
|
|
|
1853 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 monitoring channel 9 */
|
|
|
1854 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 3 monitoring channel 10 */
|
|
|
1855 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 3 monitoring channel 11 */
|
|
|
1856 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 3 monitoring channel 12 */
|
|
|
1857 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 3 monitoring channel 13 */
|
|
|
1858 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 3 monitoring channel 14 */
|
|
|
1859 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 3 monitoring channel 15 */
|
|
|
1860 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 3 monitoring channel 16 */
|
|
|
1861 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 3 monitoring channel 17 */
|
|
|
1862 #define ADC_AWD3CR_AWD3CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 3 monitoring channel 18 */
|
|
|
1863
|
|
|
1864 /******************** Bit definition for ADC_DIFSEL register ****************/
|
|
|
1865 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFFU) /*!< ADC channel differential or single-ended mode */
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|
|
1866 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1867 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1868 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1869 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1870 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1871 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1872 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1873 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1874 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000100U) /*!< bit 8 */
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|
|
1875 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1876 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1877 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1878 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00001000U) /*!< bit 12 */
|
|
|
1879 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00002000U) /*!< bit 13 */
|
|
|
1880 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00004000U) /*!< bit 14 */
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|
|
1881 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00008000U) /*!< bit 15 */
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|
|
1882 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00010000U) /*!< bit 16 */
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|
|
1883 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00020000U) /*!< bit 17 */
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|
|
1884 #define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00040000U) /*!< bit 18 */
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|
|
1885
|
|
|
1886 /******************** Bit definition for ADC_CALFACT register ***************/
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|
|
1887 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007FU) /*!< ADC calibration factor in single-ended mode */
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|
|
1888 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1889 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1890 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004U) /*!< bit 2 */
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|
|
1891 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008U) /*!< bit 3 */
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|
|
1892 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1893 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020U) /*!< bit 5 */
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|
|
1894 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040U) /*!< bit 6 */
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|
|
1895
|
|
|
1896 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000U) /*!< ADC calibration factor in differential mode */
|
|
|
1897 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
1898 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
1899 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000U) /*!< bit 2 */
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|
|
1900 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000U) /*!< bit 3 */
|
|
|
1901 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000U) /*!< bit 4 */
|
|
|
1902 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000U) /*!< bit 5 */
|
|
|
1903 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000U) /*!< bit 6 */
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|
|
1904
|
|
|
1905 /************************* ADC Common registers *****************************/
|
|
|
1906 /******************** Bit definition for ADC_CCR register *******************/
|
|
|
1907 #define ADC_CCR_CKMODE ((uint32_t)0x00030000U) /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
|
|
|
1908 #define ADC_CCR_CKMODE_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
1909 #define ADC_CCR_CKMODE_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
1910
|
|
|
1911 #define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< ADC common clock prescaler, only for clock source asynchronous */
|
|
|
1912 #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1913 #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1914 #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1915 #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< bit 3 */
|
|
|
1916
|
|
|
1917 #define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< ADC internal path to VrefInt enable */
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|
|
1918 #define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< ADC internal path to temperature sensor enable */
|
|
|
1919 #define ADC_CCR_VBATEN ((uint32_t)0x01000000U) /*!< ADC internal path to battery voltage enable */
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|
|
1920
|
|
|
1921 /******************************************************************************/
|
|
|
1922 /* */
|
|
|
1923 /* Controller Area Network */
|
|
|
1924 /* */
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|
|
1925 /******************************************************************************/
|
|
|
1926 /*!<CAN control and status registers */
|
|
|
1927 /******************* Bit definition for CAN_MCR register ********************/
|
|
|
1928 #define CAN_MCR_INRQ ((uint16_t)0x0001U) /*!<Initialization Request */
|
|
|
1929 #define CAN_MCR_SLEEP ((uint16_t)0x0002U) /*!<Sleep Mode Request */
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|
|
1930 #define CAN_MCR_TXFP ((uint16_t)0x0004U) /*!<Transmit FIFO Priority */
|
|
|
1931 #define CAN_MCR_RFLM ((uint16_t)0x0008U) /*!<Receive FIFO Locked Mode */
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|
|
1932 #define CAN_MCR_NART ((uint16_t)0x0010U) /*!<No Automatic Retransmission */
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|
|
1933 #define CAN_MCR_AWUM ((uint16_t)0x0020U) /*!<Automatic Wakeup Mode */
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|
|
1934 #define CAN_MCR_ABOM ((uint16_t)0x0040U) /*!<Automatic Bus-Off Management */
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|
|
1935 #define CAN_MCR_TTCM ((uint16_t)0x0080U) /*!<Time Triggered Communication Mode */
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|
|
1936 #define CAN_MCR_RESET ((uint16_t)0x8000U) /*!<bxCAN software master reset */
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|
|
1937
|
|
|
1938 /******************* Bit definition for CAN_MSR register ********************/
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|
|
1939 #define CAN_MSR_INAK ((uint16_t)0x0001U) /*!<Initialization Acknowledge */
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|
|
1940 #define CAN_MSR_SLAK ((uint16_t)0x0002U) /*!<Sleep Acknowledge */
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|
1941 #define CAN_MSR_ERRI ((uint16_t)0x0004U) /*!<Error Interrupt */
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|
|
1942 #define CAN_MSR_WKUI ((uint16_t)0x0008U) /*!<Wakeup Interrupt */
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|
|
1943 #define CAN_MSR_SLAKI ((uint16_t)0x0010U) /*!<Sleep Acknowledge Interrupt */
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|
|
1944 #define CAN_MSR_TXM ((uint16_t)0x0100U) /*!<Transmit Mode */
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|
|
1945 #define CAN_MSR_RXM ((uint16_t)0x0200U) /*!<Receive Mode */
|
|
|
1946 #define CAN_MSR_SAMP ((uint16_t)0x0400U) /*!<Last Sample Point */
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|
|
1947 #define CAN_MSR_RX ((uint16_t)0x0800U) /*!<CAN Rx Signal */
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|
|
1948
|
|
|
1949 /******************* Bit definition for CAN_TSR register ********************/
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|
|
1950 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001U) /*!<Request Completed Mailbox0 */
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|
|
1951 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002U) /*!<Transmission OK of Mailbox0 */
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|
|
1952 #define CAN_TSR_ALST0 ((uint32_t)0x00000004U) /*!<Arbitration Lost for Mailbox0 */
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|
|
1953 #define CAN_TSR_TERR0 ((uint32_t)0x00000008U) /*!<Transmission Error of Mailbox0 */
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|
|
1954 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080U) /*!<Abort Request for Mailbox0 */
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|
|
1955 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100U) /*!<Request Completed Mailbox1 */
|
|
|
1956 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200U) /*!<Transmission OK of Mailbox1 */
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|
|
1957 #define CAN_TSR_ALST1 ((uint32_t)0x00000400U) /*!<Arbitration Lost for Mailbox1 */
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|
|
1958 #define CAN_TSR_TERR1 ((uint32_t)0x00000800U) /*!<Transmission Error of Mailbox1 */
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|
|
1959 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000U) /*!<Abort Request for Mailbox 1 */
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|
|
1960 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000U) /*!<Request Completed Mailbox2 */
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|
|
1961 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000U) /*!<Transmission OK of Mailbox 2 */
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|
|
1962 #define CAN_TSR_ALST2 ((uint32_t)0x00040000U) /*!<Arbitration Lost for mailbox 2 */
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|
|
1963 #define CAN_TSR_TERR2 ((uint32_t)0x00080000U) /*!<Transmission Error of Mailbox 2 */
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|
1964 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000U) /*!<Abort Request for Mailbox 2 */
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|
1965 #define CAN_TSR_CODE ((uint32_t)0x03000000U) /*!<Mailbox Code */
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|
|
1966
|
|
|
1967 #define CAN_TSR_TME ((uint32_t)0x1C000000U) /*!<TME[2:0] bits */
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|
|
1968 #define CAN_TSR_TME0 ((uint32_t)0x04000000U) /*!<Transmit Mailbox 0 Empty */
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|
1969 #define CAN_TSR_TME1 ((uint32_t)0x08000000U) /*!<Transmit Mailbox 1 Empty */
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|
1970 #define CAN_TSR_TME2 ((uint32_t)0x10000000U) /*!<Transmit Mailbox 2 Empty */
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|
|
1971
|
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|
1972 #define CAN_TSR_LOW ((uint32_t)0xE0000000U) /*!<LOW[2:0] bits */
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|
1973 #define CAN_TSR_LOW0 ((uint32_t)0x20000000U) /*!<Lowest Priority Flag for Mailbox 0 */
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|
|
1974 #define CAN_TSR_LOW1 ((uint32_t)0x40000000U) /*!<Lowest Priority Flag for Mailbox 1 */
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|
|
1975 #define CAN_TSR_LOW2 ((uint32_t)0x80000000U) /*!<Lowest Priority Flag for Mailbox 2 */
|
|
|
1976
|
|
|
1977 /******************* Bit definition for CAN_RF0R register *******************/
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|
|
1978 #define CAN_RF0R_FMP0 ((uint8_t)0x03U) /*!<FIFO 0 Message Pending */
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|
1979 #define CAN_RF0R_FULL0 ((uint8_t)0x08U) /*!<FIFO 0 Full */
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|
|
1980 #define CAN_RF0R_FOVR0 ((uint8_t)0x10U) /*!<FIFO 0 Overrun */
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|
|
1981 #define CAN_RF0R_RFOM0 ((uint8_t)0x20U) /*!<Release FIFO 0 Output Mailbox */
|
|
|
1982
|
|
|
1983 /******************* Bit definition for CAN_RF1R register *******************/
|
|
|
1984 #define CAN_RF1R_FMP1 ((uint8_t)0x03U) /*!<FIFO 1 Message Pending */
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|
|
1985 #define CAN_RF1R_FULL1 ((uint8_t)0x08U) /*!<FIFO 1 Full */
|
|
|
1986 #define CAN_RF1R_FOVR1 ((uint8_t)0x10U) /*!<FIFO 1 Overrun */
|
|
|
1987 #define CAN_RF1R_RFOM1 ((uint8_t)0x20U) /*!<Release FIFO 1 Output Mailbox */
|
|
|
1988
|
|
|
1989 /******************** Bit definition for CAN_IER register *******************/
|
|
|
1990 #define CAN_IER_TMEIE ((uint32_t)0x00000001U) /*!<Transmit Mailbox Empty Interrupt Enable */
|
|
|
1991 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002U) /*!<FIFO Message Pending Interrupt Enable */
|
|
|
1992 #define CAN_IER_FFIE0 ((uint32_t)0x00000004U) /*!<FIFO Full Interrupt Enable */
|
|
|
1993 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008U) /*!<FIFO Overrun Interrupt Enable */
|
|
|
1994 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010U) /*!<FIFO Message Pending Interrupt Enable */
|
|
|
1995 #define CAN_IER_FFIE1 ((uint32_t)0x00000020U) /*!<FIFO Full Interrupt Enable */
|
|
|
1996 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040U) /*!<FIFO Overrun Interrupt Enable */
|
|
|
1997 #define CAN_IER_EWGIE ((uint32_t)0x00000100U) /*!<Error Warning Interrupt Enable */
|
|
|
1998 #define CAN_IER_EPVIE ((uint32_t)0x00000200U) /*!<Error Passive Interrupt Enable */
|
|
|
1999 #define CAN_IER_BOFIE ((uint32_t)0x00000400U) /*!<Bus-Off Interrupt Enable */
|
|
|
2000 #define CAN_IER_LECIE ((uint32_t)0x00000800U) /*!<Last Error Code Interrupt Enable */
|
|
|
2001 #define CAN_IER_ERRIE ((uint32_t)0x00008000U) /*!<Error Interrupt Enable */
|
|
|
2002 #define CAN_IER_WKUIE ((uint32_t)0x00010000U) /*!<Wakeup Interrupt Enable */
|
|
|
2003 #define CAN_IER_SLKIE ((uint32_t)0x00020000U) /*!<Sleep Interrupt Enable */
|
|
|
2004
|
|
|
2005 /******************** Bit definition for CAN_ESR register *******************/
|
|
|
2006 #define CAN_ESR_EWGF ((uint32_t)0x00000001U) /*!<Error Warning Flag */
|
|
|
2007 #define CAN_ESR_EPVF ((uint32_t)0x00000002U) /*!<Error Passive Flag */
|
|
|
2008 #define CAN_ESR_BOFF ((uint32_t)0x00000004U) /*!<Bus-Off Flag */
|
|
|
2009
|
|
|
2010 #define CAN_ESR_LEC ((uint32_t)0x00000070U) /*!<LEC[2:0] bits (Last Error Code) */
|
|
|
2011 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
2012 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
2013 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
2014
|
|
|
2015 #define CAN_ESR_TEC ((uint32_t)0x00FF0000U) /*!<Least significant byte of the 9-bit Transmit Error Counter */
|
|
|
2016 #define CAN_ESR_REC ((uint32_t)0xFF000000U) /*!<Receive Error Counter */
|
|
|
2017
|
|
|
2018 /******************* Bit definition for CAN_BTR register ********************/
|
|
|
2019 #define CAN_BTR_BRP ((uint32_t)0x000003FFU) /*!<Baud Rate Prescaler */
|
|
|
2020 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000U) /*!<Time Segment 1 (Bit 0) */
|
|
|
2021 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000U) /*!<Time Segment 1 (Bit 1) */
|
|
|
2022 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000U) /*!<Time Segment 1 (Bit 2) */
|
|
|
2023 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000U) /*!<Time Segment 1 (Bit 3) */
|
|
|
2024 #define CAN_BTR_TS1 ((uint32_t)0x000F0000U) /*!<Time Segment 1 */
|
|
|
2025 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000U) /*!<Time Segment 2 (Bit 0) */
|
|
|
2026 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000U) /*!<Time Segment 2 (Bit 1) */
|
|
|
2027 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000U) /*!<Time Segment 2 (Bit 2) */
|
|
|
2028 #define CAN_BTR_TS2 ((uint32_t)0x00700000U) /*!<Time Segment 2 */
|
|
|
2029 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000U) /*!<Resynchronization Jump Width (Bit 0) */
|
|
|
2030 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000U) /*!<Resynchronization Jump Width (Bit 1) */
|
|
|
2031 #define CAN_BTR_SJW ((uint32_t)0x03000000U) /*!<Resynchronization Jump Width */
|
|
|
2032 #define CAN_BTR_LBKM ((uint32_t)0x40000000U) /*!<Loop Back Mode (Debug) */
|
|
|
2033 #define CAN_BTR_SILM ((uint32_t)0x80000000U) /*!<Silent Mode */
|
|
|
2034
|
|
|
2035 /*!<Mailbox registers */
|
|
|
2036 /****************** Bit definition for CAN_TI0R register ********************/
|
|
|
2037 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
|
|
|
2038 #define CAN_TI0R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2039 #define CAN_TI0R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2040 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
|
|
|
2041 #define CAN_TI0R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2042
|
|
|
2043 /****************** Bit definition for CAN_TDT0R register *******************/
|
|
|
2044 #define CAN_TDT0R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2045 #define CAN_TDT0R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
|
|
|
2046 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2047
|
|
|
2048 /****************** Bit definition for CAN_TDL0R register *******************/
|
|
|
2049 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2050 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2051 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2052 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2053
|
|
|
2054 /****************** Bit definition for CAN_TDH0R register *******************/
|
|
|
2055 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2056 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2057 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2058 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2059
|
|
|
2060 /******************* Bit definition for CAN_TI1R register *******************/
|
|
|
2061 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
|
|
|
2062 #define CAN_TI1R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2063 #define CAN_TI1R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2064 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
|
|
|
2065 #define CAN_TI1R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2066
|
|
|
2067 /******************* Bit definition for CAN_TDT1R register ******************/
|
|
|
2068 #define CAN_TDT1R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2069 #define CAN_TDT1R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
|
|
|
2070 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2071
|
|
|
2072 /******************* Bit definition for CAN_TDL1R register ******************/
|
|
|
2073 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2074 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2075 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2076 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2077
|
|
|
2078 /******************* Bit definition for CAN_TDH1R register ******************/
|
|
|
2079 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2080 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2081 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2082 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2083
|
|
|
2084 /******************* Bit definition for CAN_TI2R register *******************/
|
|
|
2085 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
|
|
|
2086 #define CAN_TI2R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2087 #define CAN_TI2R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2088 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended identifier */
|
|
|
2089 #define CAN_TI2R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2090
|
|
|
2091 /******************* Bit definition for CAN_TDT2R register ******************/
|
|
|
2092 #define CAN_TDT2R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2093 #define CAN_TDT2R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
|
|
|
2094 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2095
|
|
|
2096 /******************* Bit definition for CAN_TDL2R register ******************/
|
|
|
2097 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2098 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2099 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2100 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2101
|
|
|
2102 /******************* Bit definition for CAN_TDH2R register ******************/
|
|
|
2103 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2104 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2105 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2106 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2107
|
|
|
2108 /******************* Bit definition for CAN_RI0R register *******************/
|
|
|
2109 #define CAN_RI0R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2110 #define CAN_RI0R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2111 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
|
|
|
2112 #define CAN_RI0R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2113
|
|
|
2114 /******************* Bit definition for CAN_RDT0R register ******************/
|
|
|
2115 #define CAN_RDT0R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2116 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00U) /*!<Filter Match Index */
|
|
|
2117 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2118
|
|
|
2119 /******************* Bit definition for CAN_RDL0R register ******************/
|
|
|
2120 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2121 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2122 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2123 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2124
|
|
|
2125 /******************* Bit definition for CAN_RDH0R register ******************/
|
|
|
2126 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2127 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2128 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2129 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2130
|
|
|
2131 /******************* Bit definition for CAN_RI1R register *******************/
|
|
|
2132 #define CAN_RI1R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2133 #define CAN_RI1R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2134 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended identifier */
|
|
|
2135 #define CAN_RI1R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2136
|
|
|
2137 /******************* Bit definition for CAN_RDT1R register ******************/
|
|
|
2138 #define CAN_RDT1R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2139 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00U) /*!<Filter Match Index */
|
|
|
2140 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2141
|
|
|
2142 /******************* Bit definition for CAN_RDL1R register ******************/
|
|
|
2143 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2144 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2145 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2146 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2147
|
|
|
2148 /******************* Bit definition for CAN_RDH1R register ******************/
|
|
|
2149 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2150 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2151 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2152 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2153
|
|
|
2154 /*!<CAN filter registers */
|
|
|
2155 /******************* Bit definition for CAN_FMR register ********************/
|
|
|
2156 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
|
|
|
2157
|
|
|
2158 /******************* Bit definition for CAN_FM1R register *******************/
|
|
|
2159 #define CAN_FM1R_FBM ((uint16_t)0x3FFFU) /*!<Filter Mode */
|
|
|
2160 #define CAN_FM1R_FBM0 ((uint16_t)0x0001U) /*!<Filter Init Mode bit 0 */
|
|
|
2161 #define CAN_FM1R_FBM1 ((uint16_t)0x0002U) /*!<Filter Init Mode bit 1 */
|
|
|
2162 #define CAN_FM1R_FBM2 ((uint16_t)0x0004U) /*!<Filter Init Mode bit 2 */
|
|
|
2163 #define CAN_FM1R_FBM3 ((uint16_t)0x0008U) /*!<Filter Init Mode bit 3 */
|
|
|
2164 #define CAN_FM1R_FBM4 ((uint16_t)0x0010U) /*!<Filter Init Mode bit 4 */
|
|
|
2165 #define CAN_FM1R_FBM5 ((uint16_t)0x0020U) /*!<Filter Init Mode bit 5 */
|
|
|
2166 #define CAN_FM1R_FBM6 ((uint16_t)0x0040U) /*!<Filter Init Mode bit 6 */
|
|
|
2167 #define CAN_FM1R_FBM7 ((uint16_t)0x0080U) /*!<Filter Init Mode bit 7 */
|
|
|
2168 #define CAN_FM1R_FBM8 ((uint16_t)0x0100U) /*!<Filter Init Mode bit 8 */
|
|
|
2169 #define CAN_FM1R_FBM9 ((uint16_t)0x0200U) /*!<Filter Init Mode bit 9 */
|
|
|
2170 #define CAN_FM1R_FBM10 ((uint16_t)0x0400U) /*!<Filter Init Mode bit 10 */
|
|
|
2171 #define CAN_FM1R_FBM11 ((uint16_t)0x0800U) /*!<Filter Init Mode bit 11 */
|
|
|
2172 #define CAN_FM1R_FBM12 ((uint16_t)0x1000U) /*!<Filter Init Mode bit 12 */
|
|
|
2173 #define CAN_FM1R_FBM13 ((uint16_t)0x2000U) /*!<Filter Init Mode bit 13 */
|
|
|
2174
|
|
|
2175 /******************* Bit definition for CAN_FS1R register *******************/
|
|
|
2176 #define CAN_FS1R_FSC ((uint16_t)0x3FFFU) /*!<Filter Scale Configuration */
|
|
|
2177 #define CAN_FS1R_FSC0 ((uint16_t)0x0001U) /*!<Filter Scale Configuration bit 0 */
|
|
|
2178 #define CAN_FS1R_FSC1 ((uint16_t)0x0002U) /*!<Filter Scale Configuration bit 1 */
|
|
|
2179 #define CAN_FS1R_FSC2 ((uint16_t)0x0004U) /*!<Filter Scale Configuration bit 2 */
|
|
|
2180 #define CAN_FS1R_FSC3 ((uint16_t)0x0008U) /*!<Filter Scale Configuration bit 3 */
|
|
|
2181 #define CAN_FS1R_FSC4 ((uint16_t)0x0010U) /*!<Filter Scale Configuration bit 4 */
|
|
|
2182 #define CAN_FS1R_FSC5 ((uint16_t)0x0020U) /*!<Filter Scale Configuration bit 5 */
|
|
|
2183 #define CAN_FS1R_FSC6 ((uint16_t)0x0040U) /*!<Filter Scale Configuration bit 6 */
|
|
|
2184 #define CAN_FS1R_FSC7 ((uint16_t)0x0080U) /*!<Filter Scale Configuration bit 7 */
|
|
|
2185 #define CAN_FS1R_FSC8 ((uint16_t)0x0100U) /*!<Filter Scale Configuration bit 8 */
|
|
|
2186 #define CAN_FS1R_FSC9 ((uint16_t)0x0200U) /*!<Filter Scale Configuration bit 9 */
|
|
|
2187 #define CAN_FS1R_FSC10 ((uint16_t)0x0400U) /*!<Filter Scale Configuration bit 10 */
|
|
|
2188 #define CAN_FS1R_FSC11 ((uint16_t)0x0800U) /*!<Filter Scale Configuration bit 11 */
|
|
|
2189 #define CAN_FS1R_FSC12 ((uint16_t)0x1000U) /*!<Filter Scale Configuration bit 12 */
|
|
|
2190 #define CAN_FS1R_FSC13 ((uint16_t)0x2000U) /*!<Filter Scale Configuration bit 13 */
|
|
|
2191
|
|
|
2192 /****************** Bit definition for CAN_FFA1R register *******************/
|
|
|
2193 #define CAN_FFA1R_FFA ((uint16_t)0x3FFFU) /*!<Filter FIFO Assignment */
|
|
|
2194 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001U) /*!<Filter FIFO Assignment for Filter 0 */
|
|
|
2195 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002U) /*!<Filter FIFO Assignment for Filter 1 */
|
|
|
2196 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004U) /*!<Filter FIFO Assignment for Filter 2 */
|
|
|
2197 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008U) /*!<Filter FIFO Assignment for Filter 3 */
|
|
|
2198 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010U) /*!<Filter FIFO Assignment for Filter 4 */
|
|
|
2199 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020U) /*!<Filter FIFO Assignment for Filter 5 */
|
|
|
2200 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040U) /*!<Filter FIFO Assignment for Filter 6 */
|
|
|
2201 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080U) /*!<Filter FIFO Assignment for Filter 7 */
|
|
|
2202 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100U) /*!<Filter FIFO Assignment for Filter 8 */
|
|
|
2203 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200U) /*!<Filter FIFO Assignment for Filter 9 */
|
|
|
2204 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400U) /*!<Filter FIFO Assignment for Filter 10 */
|
|
|
2205 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800U) /*!<Filter FIFO Assignment for Filter 11 */
|
|
|
2206 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000U) /*!<Filter FIFO Assignment for Filter 12 */
|
|
|
2207 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000U) /*!<Filter FIFO Assignment for Filter 13 */
|
|
|
2208
|
|
|
2209 /******************* Bit definition for CAN_FA1R register *******************/
|
|
|
2210 #define CAN_FA1R_FACT ((uint16_t)0x3FFFU) /*!<Filter Active */
|
|
|
2211 #define CAN_FA1R_FACT0 ((uint16_t)0x0001U) /*!<Filter 0 Active */
|
|
|
2212 #define CAN_FA1R_FACT1 ((uint16_t)0x0002U) /*!<Filter 1 Active */
|
|
|
2213 #define CAN_FA1R_FACT2 ((uint16_t)0x0004U) /*!<Filter 2 Active */
|
|
|
2214 #define CAN_FA1R_FACT3 ((uint16_t)0x0008U) /*!<Filter 3 Active */
|
|
|
2215 #define CAN_FA1R_FACT4 ((uint16_t)0x0010U) /*!<Filter 4 Active */
|
|
|
2216 #define CAN_FA1R_FACT5 ((uint16_t)0x0020U) /*!<Filter 5 Active */
|
|
|
2217 #define CAN_FA1R_FACT6 ((uint16_t)0x0040U) /*!<Filter 6 Active */
|
|
|
2218 #define CAN_FA1R_FACT7 ((uint16_t)0x0080U) /*!<Filter 7 Active */
|
|
|
2219 #define CAN_FA1R_FACT8 ((uint16_t)0x0100U) /*!<Filter 8 Active */
|
|
|
2220 #define CAN_FA1R_FACT9 ((uint16_t)0x0200U) /*!<Filter 9 Active */
|
|
|
2221 #define CAN_FA1R_FACT10 ((uint16_t)0x0400U) /*!<Filter 10 Active */
|
|
|
2222 #define CAN_FA1R_FACT11 ((uint16_t)0x0800U) /*!<Filter 11 Active */
|
|
|
2223 #define CAN_FA1R_FACT12 ((uint16_t)0x1000U) /*!<Filter 12 Active */
|
|
|
2224 #define CAN_FA1R_FACT13 ((uint16_t)0x2000U) /*!<Filter 13 Active */
|
|
|
2225
|
|
|
2226 /******************* Bit definition for CAN_F0R1 register *******************/
|
|
|
2227 #define CAN_F0R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2228 #define CAN_F0R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2229 #define CAN_F0R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2230 #define CAN_F0R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2231 #define CAN_F0R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2232 #define CAN_F0R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2233 #define CAN_F0R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2234 #define CAN_F0R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2235 #define CAN_F0R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2236 #define CAN_F0R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2237 #define CAN_F0R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2238 #define CAN_F0R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2239 #define CAN_F0R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2240 #define CAN_F0R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2241 #define CAN_F0R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2242 #define CAN_F0R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2243 #define CAN_F0R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2244 #define CAN_F0R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2245 #define CAN_F0R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2246 #define CAN_F0R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2247 #define CAN_F0R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2248 #define CAN_F0R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2249 #define CAN_F0R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2250 #define CAN_F0R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2251 #define CAN_F0R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2252 #define CAN_F0R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2253 #define CAN_F0R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2254 #define CAN_F0R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2255 #define CAN_F0R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2256 #define CAN_F0R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2257 #define CAN_F0R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2258 #define CAN_F0R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2259
|
|
|
2260 /******************* Bit definition for CAN_F1R1 register *******************/
|
|
|
2261 #define CAN_F1R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2262 #define CAN_F1R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2263 #define CAN_F1R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2264 #define CAN_F1R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2265 #define CAN_F1R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2266 #define CAN_F1R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2267 #define CAN_F1R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2268 #define CAN_F1R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2269 #define CAN_F1R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2270 #define CAN_F1R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2271 #define CAN_F1R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2272 #define CAN_F1R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2273 #define CAN_F1R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2274 #define CAN_F1R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2275 #define CAN_F1R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2276 #define CAN_F1R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2277 #define CAN_F1R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2278 #define CAN_F1R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2279 #define CAN_F1R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2280 #define CAN_F1R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2281 #define CAN_F1R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2282 #define CAN_F1R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2283 #define CAN_F1R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2284 #define CAN_F1R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2285 #define CAN_F1R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2286 #define CAN_F1R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2287 #define CAN_F1R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2288 #define CAN_F1R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2289 #define CAN_F1R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2290 #define CAN_F1R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2291 #define CAN_F1R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2292 #define CAN_F1R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2293
|
|
|
2294 /******************* Bit definition for CAN_F2R1 register *******************/
|
|
|
2295 #define CAN_F2R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2296 #define CAN_F2R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2297 #define CAN_F2R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2298 #define CAN_F2R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2299 #define CAN_F2R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2300 #define CAN_F2R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2301 #define CAN_F2R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2302 #define CAN_F2R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2303 #define CAN_F2R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2304 #define CAN_F2R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2305 #define CAN_F2R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2306 #define CAN_F2R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2307 #define CAN_F2R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2308 #define CAN_F2R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2309 #define CAN_F2R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2310 #define CAN_F2R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2311 #define CAN_F2R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2312 #define CAN_F2R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2313 #define CAN_F2R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2314 #define CAN_F2R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2315 #define CAN_F2R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2316 #define CAN_F2R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2317 #define CAN_F2R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2318 #define CAN_F2R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2319 #define CAN_F2R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2320 #define CAN_F2R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2321 #define CAN_F2R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2322 #define CAN_F2R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2323 #define CAN_F2R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2324 #define CAN_F2R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2325 #define CAN_F2R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2326 #define CAN_F2R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2327
|
|
|
2328 /******************* Bit definition for CAN_F3R1 register *******************/
|
|
|
2329 #define CAN_F3R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2330 #define CAN_F3R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2331 #define CAN_F3R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2332 #define CAN_F3R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2333 #define CAN_F3R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2334 #define CAN_F3R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2335 #define CAN_F3R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2336 #define CAN_F3R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2337 #define CAN_F3R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2338 #define CAN_F3R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2339 #define CAN_F3R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2340 #define CAN_F3R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2341 #define CAN_F3R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2342 #define CAN_F3R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2343 #define CAN_F3R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2344 #define CAN_F3R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2345 #define CAN_F3R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2346 #define CAN_F3R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2347 #define CAN_F3R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2348 #define CAN_F3R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2349 #define CAN_F3R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2350 #define CAN_F3R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2351 #define CAN_F3R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2352 #define CAN_F3R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2353 #define CAN_F3R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2354 #define CAN_F3R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2355 #define CAN_F3R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2356 #define CAN_F3R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2357 #define CAN_F3R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2358 #define CAN_F3R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2359 #define CAN_F3R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2360 #define CAN_F3R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2361
|
|
|
2362 /******************* Bit definition for CAN_F4R1 register *******************/
|
|
|
2363 #define CAN_F4R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2364 #define CAN_F4R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2365 #define CAN_F4R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2366 #define CAN_F4R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2367 #define CAN_F4R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2368 #define CAN_F4R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2369 #define CAN_F4R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2370 #define CAN_F4R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2371 #define CAN_F4R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2372 #define CAN_F4R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2373 #define CAN_F4R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2374 #define CAN_F4R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2375 #define CAN_F4R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2376 #define CAN_F4R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2377 #define CAN_F4R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2378 #define CAN_F4R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2379 #define CAN_F4R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2380 #define CAN_F4R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2381 #define CAN_F4R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2382 #define CAN_F4R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2383 #define CAN_F4R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2384 #define CAN_F4R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2385 #define CAN_F4R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2386 #define CAN_F4R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2387 #define CAN_F4R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2388 #define CAN_F4R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2389 #define CAN_F4R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2390 #define CAN_F4R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2391 #define CAN_F4R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2392 #define CAN_F4R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2393 #define CAN_F4R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2394 #define CAN_F4R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2395
|
|
|
2396 /******************* Bit definition for CAN_F5R1 register *******************/
|
|
|
2397 #define CAN_F5R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2398 #define CAN_F5R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2399 #define CAN_F5R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2400 #define CAN_F5R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2401 #define CAN_F5R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2402 #define CAN_F5R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2403 #define CAN_F5R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2404 #define CAN_F5R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2405 #define CAN_F5R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2406 #define CAN_F5R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2407 #define CAN_F5R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2408 #define CAN_F5R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2409 #define CAN_F5R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2410 #define CAN_F5R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2411 #define CAN_F5R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2412 #define CAN_F5R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2413 #define CAN_F5R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2414 #define CAN_F5R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2415 #define CAN_F5R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2416 #define CAN_F5R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2417 #define CAN_F5R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2418 #define CAN_F5R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2419 #define CAN_F5R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2420 #define CAN_F5R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2421 #define CAN_F5R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2422 #define CAN_F5R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2423 #define CAN_F5R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2424 #define CAN_F5R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2425 #define CAN_F5R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2426 #define CAN_F5R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2427 #define CAN_F5R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2428 #define CAN_F5R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2429
|
|
|
2430 /******************* Bit definition for CAN_F6R1 register *******************/
|
|
|
2431 #define CAN_F6R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2432 #define CAN_F6R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2433 #define CAN_F6R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2434 #define CAN_F6R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2435 #define CAN_F6R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2436 #define CAN_F6R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2437 #define CAN_F6R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2438 #define CAN_F6R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2439 #define CAN_F6R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2440 #define CAN_F6R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2441 #define CAN_F6R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2442 #define CAN_F6R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2443 #define CAN_F6R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2444 #define CAN_F6R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2445 #define CAN_F6R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2446 #define CAN_F6R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2447 #define CAN_F6R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2448 #define CAN_F6R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2449 #define CAN_F6R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2450 #define CAN_F6R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2451 #define CAN_F6R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2452 #define CAN_F6R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2453 #define CAN_F6R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2454 #define CAN_F6R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2455 #define CAN_F6R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2456 #define CAN_F6R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2457 #define CAN_F6R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2458 #define CAN_F6R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2459 #define CAN_F6R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2460 #define CAN_F6R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2461 #define CAN_F6R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2462 #define CAN_F6R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2463
|
|
|
2464 /******************* Bit definition for CAN_F7R1 register *******************/
|
|
|
2465 #define CAN_F7R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2466 #define CAN_F7R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2467 #define CAN_F7R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2468 #define CAN_F7R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2469 #define CAN_F7R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2470 #define CAN_F7R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2471 #define CAN_F7R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2472 #define CAN_F7R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2473 #define CAN_F7R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2474 #define CAN_F7R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2475 #define CAN_F7R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2476 #define CAN_F7R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2477 #define CAN_F7R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2478 #define CAN_F7R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2479 #define CAN_F7R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2480 #define CAN_F7R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2481 #define CAN_F7R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2482 #define CAN_F7R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2483 #define CAN_F7R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2484 #define CAN_F7R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2485 #define CAN_F7R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2486 #define CAN_F7R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2487 #define CAN_F7R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2488 #define CAN_F7R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2489 #define CAN_F7R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2490 #define CAN_F7R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2491 #define CAN_F7R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2492 #define CAN_F7R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2493 #define CAN_F7R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2494 #define CAN_F7R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2495 #define CAN_F7R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2496 #define CAN_F7R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2497
|
|
|
2498 /******************* Bit definition for CAN_F8R1 register *******************/
|
|
|
2499 #define CAN_F8R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2500 #define CAN_F8R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2501 #define CAN_F8R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2502 #define CAN_F8R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2503 #define CAN_F8R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2504 #define CAN_F8R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2505 #define CAN_F8R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2506 #define CAN_F8R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2507 #define CAN_F8R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2508 #define CAN_F8R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2509 #define CAN_F8R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2510 #define CAN_F8R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2511 #define CAN_F8R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2512 #define CAN_F8R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2513 #define CAN_F8R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2514 #define CAN_F8R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2515 #define CAN_F8R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2516 #define CAN_F8R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2517 #define CAN_F8R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2518 #define CAN_F8R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2519 #define CAN_F8R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2520 #define CAN_F8R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2521 #define CAN_F8R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2522 #define CAN_F8R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2523 #define CAN_F8R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2524 #define CAN_F8R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2525 #define CAN_F8R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2526 #define CAN_F8R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2527 #define CAN_F8R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2528 #define CAN_F8R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2529 #define CAN_F8R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2530 #define CAN_F8R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2531
|
|
|
2532 /******************* Bit definition for CAN_F9R1 register *******************/
|
|
|
2533 #define CAN_F9R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2534 #define CAN_F9R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2535 #define CAN_F9R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2536 #define CAN_F9R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2537 #define CAN_F9R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2538 #define CAN_F9R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2539 #define CAN_F9R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2540 #define CAN_F9R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2541 #define CAN_F9R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2542 #define CAN_F9R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2543 #define CAN_F9R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2544 #define CAN_F9R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2545 #define CAN_F9R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2546 #define CAN_F9R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2547 #define CAN_F9R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2548 #define CAN_F9R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2549 #define CAN_F9R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2550 #define CAN_F9R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2551 #define CAN_F9R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2552 #define CAN_F9R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2553 #define CAN_F9R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2554 #define CAN_F9R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2555 #define CAN_F9R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2556 #define CAN_F9R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2557 #define CAN_F9R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2558 #define CAN_F9R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2559 #define CAN_F9R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2560 #define CAN_F9R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2561 #define CAN_F9R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2562 #define CAN_F9R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2563 #define CAN_F9R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2564 #define CAN_F9R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2565
|
|
|
2566 /******************* Bit definition for CAN_F10R1 register ******************/
|
|
|
2567 #define CAN_F10R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2568 #define CAN_F10R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2569 #define CAN_F10R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2570 #define CAN_F10R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2571 #define CAN_F10R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2572 #define CAN_F10R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2573 #define CAN_F10R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2574 #define CAN_F10R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2575 #define CAN_F10R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2576 #define CAN_F10R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2577 #define CAN_F10R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2578 #define CAN_F10R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2579 #define CAN_F10R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2580 #define CAN_F10R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2581 #define CAN_F10R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2582 #define CAN_F10R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2583 #define CAN_F10R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2584 #define CAN_F10R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2585 #define CAN_F10R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2586 #define CAN_F10R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2587 #define CAN_F10R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2588 #define CAN_F10R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2589 #define CAN_F10R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2590 #define CAN_F10R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2591 #define CAN_F10R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2592 #define CAN_F10R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2593 #define CAN_F10R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2594 #define CAN_F10R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2595 #define CAN_F10R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2596 #define CAN_F10R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2597 #define CAN_F10R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2598 #define CAN_F10R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2599
|
|
|
2600 /******************* Bit definition for CAN_F11R1 register ******************/
|
|
|
2601 #define CAN_F11R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2602 #define CAN_F11R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2603 #define CAN_F11R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2604 #define CAN_F11R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2605 #define CAN_F11R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2606 #define CAN_F11R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2607 #define CAN_F11R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2608 #define CAN_F11R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2609 #define CAN_F11R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2610 #define CAN_F11R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2611 #define CAN_F11R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2612 #define CAN_F11R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2613 #define CAN_F11R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2614 #define CAN_F11R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2615 #define CAN_F11R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2616 #define CAN_F11R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2617 #define CAN_F11R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2618 #define CAN_F11R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2619 #define CAN_F11R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2620 #define CAN_F11R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2621 #define CAN_F11R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2622 #define CAN_F11R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2623 #define CAN_F11R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2624 #define CAN_F11R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2625 #define CAN_F11R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2626 #define CAN_F11R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2627 #define CAN_F11R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2628 #define CAN_F11R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2629 #define CAN_F11R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2630 #define CAN_F11R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2631 #define CAN_F11R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2632 #define CAN_F11R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2633
|
|
|
2634 /******************* Bit definition for CAN_F12R1 register ******************/
|
|
|
2635 #define CAN_F12R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2636 #define CAN_F12R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2637 #define CAN_F12R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2638 #define CAN_F12R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2639 #define CAN_F12R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2640 #define CAN_F12R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2641 #define CAN_F12R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2642 #define CAN_F12R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2643 #define CAN_F12R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2644 #define CAN_F12R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2645 #define CAN_F12R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2646 #define CAN_F12R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2647 #define CAN_F12R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2648 #define CAN_F12R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2649 #define CAN_F12R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2650 #define CAN_F12R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2651 #define CAN_F12R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2652 #define CAN_F12R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2653 #define CAN_F12R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2654 #define CAN_F12R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2655 #define CAN_F12R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2656 #define CAN_F12R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2657 #define CAN_F12R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2658 #define CAN_F12R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2659 #define CAN_F12R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2660 #define CAN_F12R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2661 #define CAN_F12R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2662 #define CAN_F12R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2663 #define CAN_F12R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2664 #define CAN_F12R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2665 #define CAN_F12R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2666 #define CAN_F12R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2667
|
|
|
2668 /******************* Bit definition for CAN_F13R1 register ******************/
|
|
|
2669 #define CAN_F13R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2670 #define CAN_F13R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2671 #define CAN_F13R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2672 #define CAN_F13R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2673 #define CAN_F13R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2674 #define CAN_F13R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2675 #define CAN_F13R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2676 #define CAN_F13R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2677 #define CAN_F13R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2678 #define CAN_F13R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2679 #define CAN_F13R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2680 #define CAN_F13R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2681 #define CAN_F13R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2682 #define CAN_F13R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2683 #define CAN_F13R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2684 #define CAN_F13R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2685 #define CAN_F13R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2686 #define CAN_F13R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2687 #define CAN_F13R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2688 #define CAN_F13R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2689 #define CAN_F13R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2690 #define CAN_F13R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2691 #define CAN_F13R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2692 #define CAN_F13R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2693 #define CAN_F13R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2694 #define CAN_F13R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2695 #define CAN_F13R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2696 #define CAN_F13R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2697 #define CAN_F13R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2698 #define CAN_F13R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2699 #define CAN_F13R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2700 #define CAN_F13R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2701
|
|
|
2702 /******************* Bit definition for CAN_F0R2 register *******************/
|
|
|
2703 #define CAN_F0R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2704 #define CAN_F0R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2705 #define CAN_F0R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2706 #define CAN_F0R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2707 #define CAN_F0R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2708 #define CAN_F0R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2709 #define CAN_F0R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2710 #define CAN_F0R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2711 #define CAN_F0R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2712 #define CAN_F0R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2713 #define CAN_F0R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2714 #define CAN_F0R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2715 #define CAN_F0R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2716 #define CAN_F0R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2717 #define CAN_F0R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2718 #define CAN_F0R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2719 #define CAN_F0R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2720 #define CAN_F0R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2721 #define CAN_F0R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2722 #define CAN_F0R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2723 #define CAN_F0R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2724 #define CAN_F0R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2725 #define CAN_F0R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2726 #define CAN_F0R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2727 #define CAN_F0R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2728 #define CAN_F0R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2729 #define CAN_F0R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2730 #define CAN_F0R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2731 #define CAN_F0R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2732 #define CAN_F0R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2733 #define CAN_F0R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2734 #define CAN_F0R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2735
|
|
|
2736 /******************* Bit definition for CAN_F1R2 register *******************/
|
|
|
2737 #define CAN_F1R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2738 #define CAN_F1R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2739 #define CAN_F1R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2740 #define CAN_F1R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2741 #define CAN_F1R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2742 #define CAN_F1R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2743 #define CAN_F1R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2744 #define CAN_F1R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2745 #define CAN_F1R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2746 #define CAN_F1R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2747 #define CAN_F1R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2748 #define CAN_F1R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2749 #define CAN_F1R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2750 #define CAN_F1R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2751 #define CAN_F1R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2752 #define CAN_F1R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2753 #define CAN_F1R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2754 #define CAN_F1R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2755 #define CAN_F1R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2756 #define CAN_F1R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2757 #define CAN_F1R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2758 #define CAN_F1R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2759 #define CAN_F1R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2760 #define CAN_F1R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2761 #define CAN_F1R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2762 #define CAN_F1R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2763 #define CAN_F1R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2764 #define CAN_F1R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2765 #define CAN_F1R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2766 #define CAN_F1R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2767 #define CAN_F1R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2768 #define CAN_F1R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2769
|
|
|
2770 /******************* Bit definition for CAN_F2R2 register *******************/
|
|
|
2771 #define CAN_F2R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2772 #define CAN_F2R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2773 #define CAN_F2R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2774 #define CAN_F2R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2775 #define CAN_F2R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2776 #define CAN_F2R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2777 #define CAN_F2R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2778 #define CAN_F2R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2779 #define CAN_F2R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2780 #define CAN_F2R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2781 #define CAN_F2R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2782 #define CAN_F2R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2783 #define CAN_F2R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2784 #define CAN_F2R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2785 #define CAN_F2R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2786 #define CAN_F2R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2787 #define CAN_F2R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2788 #define CAN_F2R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2789 #define CAN_F2R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2790 #define CAN_F2R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2791 #define CAN_F2R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2792 #define CAN_F2R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2793 #define CAN_F2R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2794 #define CAN_F2R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2795 #define CAN_F2R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2796 #define CAN_F2R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2797 #define CAN_F2R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2798 #define CAN_F2R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2799 #define CAN_F2R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2800 #define CAN_F2R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2801 #define CAN_F2R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2802 #define CAN_F2R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2803
|
|
|
2804 /******************* Bit definition for CAN_F3R2 register *******************/
|
|
|
2805 #define CAN_F3R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2806 #define CAN_F3R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2807 #define CAN_F3R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2808 #define CAN_F3R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2809 #define CAN_F3R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2810 #define CAN_F3R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2811 #define CAN_F3R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2812 #define CAN_F3R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2813 #define CAN_F3R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2814 #define CAN_F3R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2815 #define CAN_F3R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2816 #define CAN_F3R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2817 #define CAN_F3R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2818 #define CAN_F3R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2819 #define CAN_F3R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2820 #define CAN_F3R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2821 #define CAN_F3R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2822 #define CAN_F3R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2823 #define CAN_F3R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2824 #define CAN_F3R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2825 #define CAN_F3R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2826 #define CAN_F3R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2827 #define CAN_F3R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2828 #define CAN_F3R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2829 #define CAN_F3R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2830 #define CAN_F3R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2831 #define CAN_F3R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2832 #define CAN_F3R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2833 #define CAN_F3R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2834 #define CAN_F3R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2835 #define CAN_F3R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2836 #define CAN_F3R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2837
|
|
|
2838 /******************* Bit definition for CAN_F4R2 register *******************/
|
|
|
2839 #define CAN_F4R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2840 #define CAN_F4R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2841 #define CAN_F4R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2842 #define CAN_F4R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2843 #define CAN_F4R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2844 #define CAN_F4R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2845 #define CAN_F4R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2846 #define CAN_F4R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2847 #define CAN_F4R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2848 #define CAN_F4R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2849 #define CAN_F4R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2850 #define CAN_F4R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2851 #define CAN_F4R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2852 #define CAN_F4R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2853 #define CAN_F4R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2854 #define CAN_F4R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2855 #define CAN_F4R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2856 #define CAN_F4R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2857 #define CAN_F4R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2858 #define CAN_F4R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2859 #define CAN_F4R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2860 #define CAN_F4R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2861 #define CAN_F4R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2862 #define CAN_F4R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2863 #define CAN_F4R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2864 #define CAN_F4R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2865 #define CAN_F4R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2866 #define CAN_F4R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2867 #define CAN_F4R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2868 #define CAN_F4R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2869 #define CAN_F4R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2870 #define CAN_F4R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2871
|
|
|
2872 /******************* Bit definition for CAN_F5R2 register *******************/
|
|
|
2873 #define CAN_F5R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2874 #define CAN_F5R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2875 #define CAN_F5R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2876 #define CAN_F5R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2877 #define CAN_F5R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2878 #define CAN_F5R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2879 #define CAN_F5R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2880 #define CAN_F5R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2881 #define CAN_F5R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2882 #define CAN_F5R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2883 #define CAN_F5R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2884 #define CAN_F5R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2885 #define CAN_F5R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2886 #define CAN_F5R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2887 #define CAN_F5R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2888 #define CAN_F5R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2889 #define CAN_F5R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2890 #define CAN_F5R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2891 #define CAN_F5R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2892 #define CAN_F5R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2893 #define CAN_F5R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2894 #define CAN_F5R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2895 #define CAN_F5R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2896 #define CAN_F5R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2897 #define CAN_F5R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2898 #define CAN_F5R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2899 #define CAN_F5R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2900 #define CAN_F5R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2901 #define CAN_F5R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2902 #define CAN_F5R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2903 #define CAN_F5R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2904 #define CAN_F5R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2905
|
|
|
2906 /******************* Bit definition for CAN_F6R2 register *******************/
|
|
|
2907 #define CAN_F6R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2908 #define CAN_F6R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2909 #define CAN_F6R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2910 #define CAN_F6R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2911 #define CAN_F6R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2912 #define CAN_F6R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2913 #define CAN_F6R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2914 #define CAN_F6R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2915 #define CAN_F6R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2916 #define CAN_F6R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2917 #define CAN_F6R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2918 #define CAN_F6R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2919 #define CAN_F6R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2920 #define CAN_F6R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2921 #define CAN_F6R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2922 #define CAN_F6R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2923 #define CAN_F6R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2924 #define CAN_F6R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2925 #define CAN_F6R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2926 #define CAN_F6R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2927 #define CAN_F6R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2928 #define CAN_F6R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2929 #define CAN_F6R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2930 #define CAN_F6R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2931 #define CAN_F6R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2932 #define CAN_F6R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2933 #define CAN_F6R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2934 #define CAN_F6R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2935 #define CAN_F6R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2936 #define CAN_F6R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2937 #define CAN_F6R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2938 #define CAN_F6R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2939
|
|
|
2940 /******************* Bit definition for CAN_F7R2 register *******************/
|
|
|
2941 #define CAN_F7R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2942 #define CAN_F7R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2943 #define CAN_F7R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2944 #define CAN_F7R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2945 #define CAN_F7R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2946 #define CAN_F7R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2947 #define CAN_F7R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2948 #define CAN_F7R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2949 #define CAN_F7R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2950 #define CAN_F7R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2951 #define CAN_F7R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2952 #define CAN_F7R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2953 #define CAN_F7R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2954 #define CAN_F7R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2955 #define CAN_F7R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2956 #define CAN_F7R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2957 #define CAN_F7R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2958 #define CAN_F7R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2959 #define CAN_F7R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2960 #define CAN_F7R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2961 #define CAN_F7R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2962 #define CAN_F7R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2963 #define CAN_F7R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2964 #define CAN_F7R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2965 #define CAN_F7R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2966 #define CAN_F7R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2967 #define CAN_F7R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2968 #define CAN_F7R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2969 #define CAN_F7R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2970 #define CAN_F7R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2971 #define CAN_F7R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2972 #define CAN_F7R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2973
|
|
|
2974 /******************* Bit definition for CAN_F8R2 register *******************/
|
|
|
2975 #define CAN_F8R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2976 #define CAN_F8R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2977 #define CAN_F8R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2978 #define CAN_F8R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2979 #define CAN_F8R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2980 #define CAN_F8R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2981 #define CAN_F8R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2982 #define CAN_F8R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2983 #define CAN_F8R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2984 #define CAN_F8R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2985 #define CAN_F8R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2986 #define CAN_F8R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2987 #define CAN_F8R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2988 #define CAN_F8R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2989 #define CAN_F8R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2990 #define CAN_F8R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2991 #define CAN_F8R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2992 #define CAN_F8R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2993 #define CAN_F8R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2994 #define CAN_F8R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2995 #define CAN_F8R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2996 #define CAN_F8R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2997 #define CAN_F8R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2998 #define CAN_F8R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2999 #define CAN_F8R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3000 #define CAN_F8R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3001 #define CAN_F8R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3002 #define CAN_F8R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3003 #define CAN_F8R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3004 #define CAN_F8R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3005 #define CAN_F8R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3006 #define CAN_F8R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3007
|
|
|
3008 /******************* Bit definition for CAN_F9R2 register *******************/
|
|
|
3009 #define CAN_F9R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3010 #define CAN_F9R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3011 #define CAN_F9R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3012 #define CAN_F9R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3013 #define CAN_F9R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3014 #define CAN_F9R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3015 #define CAN_F9R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3016 #define CAN_F9R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3017 #define CAN_F9R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3018 #define CAN_F9R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3019 #define CAN_F9R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3020 #define CAN_F9R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3021 #define CAN_F9R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3022 #define CAN_F9R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3023 #define CAN_F9R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3024 #define CAN_F9R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3025 #define CAN_F9R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3026 #define CAN_F9R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3027 #define CAN_F9R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3028 #define CAN_F9R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3029 #define CAN_F9R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3030 #define CAN_F9R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3031 #define CAN_F9R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3032 #define CAN_F9R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3033 #define CAN_F9R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3034 #define CAN_F9R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3035 #define CAN_F9R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3036 #define CAN_F9R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3037 #define CAN_F9R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3038 #define CAN_F9R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3039 #define CAN_F9R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3040 #define CAN_F9R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3041
|
|
|
3042 /******************* Bit definition for CAN_F10R2 register ******************/
|
|
|
3043 #define CAN_F10R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3044 #define CAN_F10R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3045 #define CAN_F10R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3046 #define CAN_F10R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3047 #define CAN_F10R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3048 #define CAN_F10R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3049 #define CAN_F10R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3050 #define CAN_F10R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3051 #define CAN_F10R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3052 #define CAN_F10R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3053 #define CAN_F10R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3054 #define CAN_F10R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3055 #define CAN_F10R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3056 #define CAN_F10R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3057 #define CAN_F10R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3058 #define CAN_F10R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3059 #define CAN_F10R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3060 #define CAN_F10R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3061 #define CAN_F10R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3062 #define CAN_F10R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3063 #define CAN_F10R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3064 #define CAN_F10R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3065 #define CAN_F10R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3066 #define CAN_F10R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3067 #define CAN_F10R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3068 #define CAN_F10R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3069 #define CAN_F10R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3070 #define CAN_F10R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3071 #define CAN_F10R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3072 #define CAN_F10R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3073 #define CAN_F10R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3074 #define CAN_F10R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3075
|
|
|
3076 /******************* Bit definition for CAN_F11R2 register ******************/
|
|
|
3077 #define CAN_F11R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3078 #define CAN_F11R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3079 #define CAN_F11R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3080 #define CAN_F11R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3081 #define CAN_F11R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3082 #define CAN_F11R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3083 #define CAN_F11R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3084 #define CAN_F11R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3085 #define CAN_F11R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3086 #define CAN_F11R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3087 #define CAN_F11R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3088 #define CAN_F11R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3089 #define CAN_F11R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3090 #define CAN_F11R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3091 #define CAN_F11R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3092 #define CAN_F11R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3093 #define CAN_F11R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3094 #define CAN_F11R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3095 #define CAN_F11R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3096 #define CAN_F11R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3097 #define CAN_F11R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3098 #define CAN_F11R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3099 #define CAN_F11R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3100 #define CAN_F11R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3101 #define CAN_F11R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3102 #define CAN_F11R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3103 #define CAN_F11R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3104 #define CAN_F11R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3105 #define CAN_F11R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3106 #define CAN_F11R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3107 #define CAN_F11R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3108 #define CAN_F11R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3109
|
|
|
3110 /******************* Bit definition for CAN_F12R2 register ******************/
|
|
|
3111 #define CAN_F12R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3112 #define CAN_F12R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3113 #define CAN_F12R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3114 #define CAN_F12R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3115 #define CAN_F12R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3116 #define CAN_F12R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3117 #define CAN_F12R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3118 #define CAN_F12R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3119 #define CAN_F12R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3120 #define CAN_F12R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3121 #define CAN_F12R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3122 #define CAN_F12R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3123 #define CAN_F12R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3124 #define CAN_F12R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3125 #define CAN_F12R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3126 #define CAN_F12R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3127 #define CAN_F12R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3128 #define CAN_F12R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3129 #define CAN_F12R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3130 #define CAN_F12R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3131 #define CAN_F12R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3132 #define CAN_F12R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3133 #define CAN_F12R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3134 #define CAN_F12R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3135 #define CAN_F12R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3136 #define CAN_F12R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3137 #define CAN_F12R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3138 #define CAN_F12R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3139 #define CAN_F12R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3140 #define CAN_F12R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3141 #define CAN_F12R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3142 #define CAN_F12R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3143
|
|
|
3144 /******************* Bit definition for CAN_F13R2 register ******************/
|
|
|
3145 #define CAN_F13R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3146 #define CAN_F13R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3147 #define CAN_F13R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3148 #define CAN_F13R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3149 #define CAN_F13R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3150 #define CAN_F13R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3151 #define CAN_F13R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3152 #define CAN_F13R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3153 #define CAN_F13R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3154 #define CAN_F13R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3155 #define CAN_F13R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3156 #define CAN_F13R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3157 #define CAN_F13R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3158 #define CAN_F13R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3159 #define CAN_F13R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3160 #define CAN_F13R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3161 #define CAN_F13R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3162 #define CAN_F13R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3163 #define CAN_F13R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3164 #define CAN_F13R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3165 #define CAN_F13R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3166 #define CAN_F13R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3167 #define CAN_F13R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3168 #define CAN_F13R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3169 #define CAN_F13R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3170 #define CAN_F13R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3171 #define CAN_F13R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3172 #define CAN_F13R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3173 #define CAN_F13R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3174 #define CAN_F13R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3175 #define CAN_F13R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3176 #define CAN_F13R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3177
|
|
|
3178 /******************************************************************************/
|
|
|
3179 /* */
|
|
|
3180 /* CRC calculation unit */
|
|
|
3181 /* */
|
|
|
3182 /******************************************************************************/
|
|
|
3183 /******************* Bit definition for CRC_DR register *********************/
|
|
|
3184 #define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
|
|
|
3185
|
|
|
3186 /******************* Bit definition for CRC_IDR register ********************/
|
|
|
3187 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
|
|
|
3188
|
|
|
3189 /******************** Bit definition for CRC_CR register ********************/
|
|
|
3190 #define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
|
|
|
3191 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */
|
|
|
3192 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
|
|
|
3193 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
|
|
|
3194 #define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
|
|
|
3195 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
|
|
|
3196 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
|
|
|
3197 #define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
|
|
|
3198
|
|
|
3199 /******************* Bit definition for CRC_INIT register *******************/
|
|
|
3200 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
|
|
|
3201
|
|
|
3202 /******************* Bit definition for CRC_POL register ********************/
|
|
|
3203 #define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
|
|
|
3204
|
|
|
3205 /******************************************************************************/
|
|
|
3206 /* */
|
|
|
3207 /* CRS Clock Recovery System */
|
|
|
3208 /******************************************************************************/
|
|
|
3209
|
|
|
3210 /******************* Bit definition for CRS_CR register *********************/
|
|
|
3211 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /*!< SYNC event OK interrupt enable */
|
|
|
3212 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /*!< SYNC warning interrupt enable */
|
|
|
3213 #define CRS_CR_ERRIE ((uint32_t)0x00000004U) /*!< SYNC error or trimming error interrupt enable */
|
|
|
3214 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /*!< Expected SYNC interrupt enable */
|
|
|
3215 #define CRS_CR_CEN ((uint32_t)0x00000020U) /*!< Frequency error counter enable */
|
|
|
3216 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /*!< Automatic trimming enable */
|
|
|
3217 #define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /*!< Generate software SYNC event */
|
|
|
3218 #define CRS_CR_TRIM ((uint32_t)0x00003F00U) /*!< HSI48 oscillator smooth trimming */
|
|
|
3219
|
|
|
3220 /******************* Bit definition for CRS_CFGR register *********************/
|
|
|
3221 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /*!< Counter reload value */
|
|
|
3222 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /*!< Frequency error limit */
|
|
|
3223
|
|
|
3224 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /*!< SYNC divider */
|
|
|
3225 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /*!< SYNC divider bit 0 */
|
|
|
3226 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /*!< SYNC divider bit 1 */
|
|
|
3227 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /*!< SYNC divider bit 2 */
|
|
|
3228
|
|
|
3229 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /*!< SYNC signal source selection */
|
|
|
3230 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /*!< SYNC signal source selection bit 0 */
|
|
|
3231 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /*!< SYNC signal source selection bit 1 */
|
|
|
3232
|
|
|
3233 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /*!< SYNC polarity selection */
|
|
|
3234
|
|
|
3235 /******************* Bit definition for CRS_ISR register *********************/
|
|
|
3236 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /*!< SYNC event OK flag */
|
|
|
3237 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /*!< SYNC warning flag */
|
|
|
3238 #define CRS_ISR_ERRF ((uint32_t)0x00000004U) /*!< Error flag */
|
|
|
3239 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /*!< Expected SYNC flag */
|
|
|
3240 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /*!< SYNC error */
|
|
|
3241 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /*!< SYNC missed */
|
|
|
3242 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /*!< Trimming overflow or underflow */
|
|
|
3243 #define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /*!< Frequency error direction */
|
|
|
3244 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /*!< Frequency error capture */
|
|
|
3245
|
|
|
3246 /******************* Bit definition for CRS_ICR register *********************/
|
|
|
3247 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /*!< SYNC event OK clear flag */
|
|
|
3248 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /*!< SYNC warning clear flag */
|
|
|
3249 #define CRS_ICR_ERRC ((uint32_t)0x00000004U) /*!< Error clear flag */
|
|
|
3250 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /*!< Expected SYNC clear flag */
|
|
|
3251
|
|
|
3252 /******************************************************************************/
|
|
|
3253 /* */
|
|
|
3254 /* Digital to Analog Converter */
|
|
|
3255 /* */
|
|
|
3256 /******************************************************************************/
|
|
|
3257 /******************** Bit definition for DAC_CR register ********************/
|
|
|
3258 #define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!<DAC channel1 enable */
|
|
|
3259 #define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!<DAC channel1 Trigger enable */
|
|
|
3260
|
|
|
3261 #define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
|
|
|
3262 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
|
|
|
3263 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
|
|
|
3264 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
|
|
|
3265
|
|
|
3266 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
|
|
|
3267 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
|
|
|
3268 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
|
|
|
3269
|
|
|
3270 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
|
|
|
3271 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
3272 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
3273 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
3274 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
3275
|
|
|
3276 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!<DAC channel1 DMA enable */
|
|
|
3277 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!<DAC channel 1 DMA underrun interrupt enable >*/
|
|
|
3278 #define DAC_CR_CEN1 ((uint32_t)0x00004000U) /*!<DAC channel 1 calibration enable >*/
|
|
|
3279
|
|
|
3280 #define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!<DAC channel2 enable */
|
|
|
3281 #define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!<DAC channel2 Trigger enable */
|
|
|
3282
|
|
|
3283 #define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
|
|
|
3284 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!<Bit 0 */
|
|
|
3285 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!<Bit 1 */
|
|
|
3286 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!<Bit 2 */
|
|
|
3287
|
|
|
3288 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
|
|
|
3289 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
|
|
|
3290 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
|
|
|
3291
|
|
|
3292 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
|
|
|
3293 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
3294 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
3295 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
3296 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
3297
|
|
|
3298 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!<DAC channel2 DMA enabled */
|
|
|
3299 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun interrupt enable >*/
|
|
|
3300 #define DAC_CR_CEN2 ((uint32_t)0x40000000U) /*!<DAC channel2 calibration enable >*/
|
|
|
3301
|
|
|
3302 /***************** Bit definition for DAC_SWTRIGR register ******************/
|
|
|
3303 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!<DAC channel1 software trigger */
|
|
|
3304 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!<DAC channel2 software trigger */
|
|
|
3305
|
|
|
3306 /***************** Bit definition for DAC_DHR12R1 register ******************/
|
|
|
3307 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
|
|
|
3308
|
|
|
3309 /***************** Bit definition for DAC_DHR12L1 register ******************/
|
|
|
3310 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
|
|
|
3311
|
|
|
3312 /****************** Bit definition for DAC_DHR8R1 register ******************/
|
|
|
3313 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
|
|
|
3314
|
|
|
3315 /***************** Bit definition for DAC_DHR12R2 register ******************/
|
|
|
3316 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!<DAC channel2 12-bit Right aligned data */
|
|
|
3317
|
|
|
3318 /***************** Bit definition for DAC_DHR12L2 register ******************/
|
|
|
3319 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel2 12-bit Left aligned data */
|
|
|
3320
|
|
|
3321 /****************** Bit definition for DAC_DHR8R2 register ******************/
|
|
|
3322 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!<DAC channel2 8-bit Right aligned data */
|
|
|
3323
|
|
|
3324 /***************** Bit definition for DAC_DHR12RD register ******************/
|
|
|
3325 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
|
|
|
3326 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!<DAC channel2 12-bit Right aligned data */
|
|
|
3327
|
|
|
3328 /***************** Bit definition for DAC_DHR12LD register ******************/
|
|
|
3329 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
|
|
|
3330 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!<DAC channel2 12-bit Left aligned data */
|
|
|
3331
|
|
|
3332 /****************** Bit definition for DAC_DHR8RD register ******************/
|
|
|
3333 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
|
|
|
3334 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!<DAC channel2 8-bit Right aligned data */
|
|
|
3335
|
|
|
3336 /******************* Bit definition for DAC_DOR1 register *******************/
|
|
|
3337 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFFU) /*!<DAC channel1 data output */
|
|
|
3338
|
|
|
3339 /******************* Bit definition for DAC_DOR2 register *******************/
|
|
|
3340 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFFU) /*!<DAC channel2 data output */
|
|
|
3341
|
|
|
3342 /******************** Bit definition for DAC_SR register ********************/
|
|
|
3343 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!<DAC channel1 DMA underrun flag */
|
|
|
3344 #define DAC_SR_CAL_FLAG1 ((uint32_t)0x00004000U) /*!<DAC channel1 calibration offset status */
|
|
|
3345 #define DAC_SR_BWST1 ((uint32_t)0x20008000U) /*!<DAC channel1 busy writing sample time flag */
|
|
|
3346
|
|
|
3347 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun flag */
|
|
|
3348 #define DAC_SR_CAL_FLAG2 ((uint32_t)0x40000000U) /*!<DAC channel2 calibration offset status */
|
|
|
3349 #define DAC_SR_BWST2 ((uint32_t)0x80000000U) /*!<DAC channel2 busy writing sample time flag */
|
|
|
3350
|
|
|
3351 /******************* Bit definition for DAC_CCR register ********************/
|
|
|
3352 #define DAC_CCR_OTRIM1 ((uint32_t)0x0000001FU) /*!<DAC channel1 offset trimming value */
|
|
|
3353 #define DAC_CCR_OTRIM2 ((uint32_t)0x001F0000U) /*!<DAC channel2 offset trimming value */
|
|
|
3354
|
|
|
3355 /******************* Bit definition for DAC_MCR register *******************/
|
|
|
3356 #define DAC_MCR_MODE1 ((uint32_t)0x00000007U) /*!<MODE1[2:0] (DAC channel1 mode) */
|
|
|
3357 #define DAC_MCR_MODE1_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
3358 #define DAC_MCR_MODE1_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
3359 #define DAC_MCR_MODE1_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
3360
|
|
|
3361 #define DAC_MCR_MODE2 ((uint32_t)0x00070000U) /*!<MODE2[2:0] (DAC channel2 mode) */
|
|
|
3362 #define DAC_MCR_MODE2_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
3363 #define DAC_MCR_MODE2_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
3364 #define DAC_MCR_MODE2_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
3365
|
|
|
3366 /****************** Bit definition for DAC_SHSR1 register ******************/
|
|
|
3367 #define DAC_SHSR1_TSAMPLE1 ((uint32_t)0x000003FFU) /*!<DAC channel1 sample time */
|
|
|
3368
|
|
|
3369 /****************** Bit definition for DAC_SHSR2 register ******************/
|
|
|
3370 #define DAC_SHSR2_TSAMPLE2 ((uint32_t)0x000003FFU) /*!<DAC channel2 sample time */
|
|
|
3371
|
|
|
3372 /****************** Bit definition for DAC_SHHR register ******************/
|
|
|
3373 #define DAC_SHHR_THOLD1 ((uint32_t)0x000003FFU) /*!<DAC channel1 hold time */
|
|
|
3374 #define DAC_SHHR_THOLD2 ((uint32_t)0x03FF0000U) /*!<DAC channel2 hold time */
|
|
|
3375
|
|
|
3376 /****************** Bit definition for DAC_SHRR register ******************/
|
|
|
3377 #define DAC_SHRR_TREFRESH1 ((uint32_t)0x000000FFU) /*!<DAC channel1 refresh time */
|
|
|
3378 #define DAC_SHRR_TREFRESH2 ((uint32_t)0x00FF0000U) /*!<DAC channel2 refresh time */
|
|
|
3379
|
|
|
3380
|
|
|
3381
|
|
|
3382 /******************************************************************************/
|
|
|
3383 /* */
|
|
|
3384 /* DMA Controller (DMA) */
|
|
|
3385 /* */
|
|
|
3386 /******************************************************************************/
|
|
|
3387
|
|
|
3388 /******************* Bit definition for DMA_ISR register ********************/
|
|
|
3389 #define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
|
|
|
3390 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
|
|
|
3391 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
|
|
|
3392 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
|
|
|
3393 #define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
|
|
|
3394 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
|
|
|
3395 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
|
|
|
3396 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
|
|
|
3397 #define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
|
|
|
3398 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
|
|
|
3399 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
|
|
|
3400 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
|
|
|
3401 #define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
|
|
|
3402 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
|
|
|
3403 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
|
|
|
3404 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
|
|
|
3405 #define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
|
|
|
3406 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
|
|
|
3407 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
|
|
|
3408 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
|
|
|
3409 #define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
|
|
|
3410 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
|
|
|
3411 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
|
|
|
3412 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
|
|
|
3413 #define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
|
|
|
3414 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
|
|
|
3415 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
|
|
|
3416 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
|
|
|
3417
|
|
|
3418 /******************* Bit definition for DMA_IFCR register *******************/
|
|
|
3419 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clearr */
|
|
|
3420 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
|
|
|
3421 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
|
|
|
3422 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
|
|
|
3423 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
|
|
|
3424 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
|
|
|
3425 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
|
|
|
3426 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
|
|
|
3427 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
|
|
|
3428 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
|
|
|
3429 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
|
|
|
3430 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
|
|
|
3431 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
|
|
|
3432 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
|
|
|
3433 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
|
|
|
3434 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
|
|
|
3435 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
|
|
|
3436 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
|
|
|
3437 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
|
|
|
3438 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
|
|
|
3439 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
|
|
|
3440 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
|
|
|
3441 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
|
|
|
3442 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
|
|
|
3443 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
|
|
|
3444 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
|
|
|
3445 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
|
|
|
3446 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
|
|
|
3447
|
|
|
3448 /******************* Bit definition for DMA_CCR register ********************/
|
|
|
3449 #define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */
|
|
|
3450 #define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
|
|
|
3451 #define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
|
|
|
3452 #define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
|
|
|
3453 #define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
|
|
|
3454 #define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
|
|
|
3455 #define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
|
|
|
3456 #define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
|
|
|
3457
|
|
|
3458 #define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
|
|
|
3459 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
3460 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
3461
|
|
|
3462 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
|
|
|
3463 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
|
|
|
3464 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
|
|
|
3465
|
|
|
3466 #define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/
|
|
|
3467 #define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
|
|
|
3468 #define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
|
|
|
3469
|
|
|
3470 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
|
|
|
3471
|
|
|
3472 /****************** Bit definition for DMA_CNDTR register *******************/
|
|
|
3473 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
|
|
|
3474
|
|
|
3475 /****************** Bit definition for DMA_CPAR register ********************/
|
|
|
3476 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
|
|
|
3477
|
|
|
3478 /****************** Bit definition for DMA_CMAR register ********************/
|
|
|
3479 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
|
|
|
3480
|
|
|
3481
|
|
|
3482 /******************* Bit definition for DMA_CSELR register *******************/
|
|
|
3483 #define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */
|
|
|
3484 #define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */
|
|
|
3485 #define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */
|
|
|
3486 #define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */
|
|
|
3487 #define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */
|
|
|
3488 #define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */
|
|
|
3489 #define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */
|
|
|
3490
|
|
|
3491
|
|
|
3492 /******************************************************************************/
|
|
|
3493 /* */
|
|
|
3494 /* External Interrupt/Event Controller */
|
|
|
3495 /* */
|
|
|
3496 /******************************************************************************/
|
|
|
3497 /******************* Bit definition for EXTI_IMR1 register ******************/
|
|
|
3498 #define EXTI_IMR1_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
|
|
|
3499 #define EXTI_IMR1_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
|
|
|
3500 #define EXTI_IMR1_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
|
|
|
3501 #define EXTI_IMR1_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
|
|
|
3502 #define EXTI_IMR1_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
|
|
|
3503 #define EXTI_IMR1_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
|
|
|
3504 #define EXTI_IMR1_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
|
|
|
3505 #define EXTI_IMR1_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
|
|
|
3506 #define EXTI_IMR1_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
|
|
|
3507 #define EXTI_IMR1_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
|
|
|
3508 #define EXTI_IMR1_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
|
|
|
3509 #define EXTI_IMR1_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
|
|
|
3510 #define EXTI_IMR1_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
|
|
|
3511 #define EXTI_IMR1_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
|
|
|
3512 #define EXTI_IMR1_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
|
|
|
3513 #define EXTI_IMR1_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
|
|
|
3514 #define EXTI_IMR1_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
|
|
|
3515 #define EXTI_IMR1_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
|
|
|
3516 #define EXTI_IMR1_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
|
|
|
3517 #define EXTI_IMR1_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
|
|
|
3518 #define EXTI_IMR1_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
|
|
|
3519 #define EXTI_IMR1_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
|
|
|
3520 #define EXTI_IMR1_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
|
|
|
3521 #define EXTI_IMR1_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
|
|
|
3522 #define EXTI_IMR1_IM24 ((uint32_t)0x01000000U) /*!< Interrupt Mask on line 24 */
|
|
|
3523 #define EXTI_IMR1_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */
|
|
|
3524 #define EXTI_IMR1_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */
|
|
|
3525 #define EXTI_IMR1_IM27 ((uint32_t)0x08000000U) /*!< Interrupt Mask on line 27 */
|
|
|
3526 #define EXTI_IMR1_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */
|
|
|
3527 #define EXTI_IMR1_IM31 ((uint32_t)0x80000000U) /*!< Interrupt Mask on line 31 */
|
|
|
3528 #define EXTI_IMR1_IM ((uint32_t)0x3FFFFFFFU) /*!< Interrupt Mask All */
|
|
|
3529
|
|
|
3530 /******************* Bit definition for EXTI_EMR1 register ******************/
|
|
|
3531 #define EXTI_EMR1_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
|
|
|
3532 #define EXTI_EMR1_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
|
|
|
3533 #define EXTI_EMR1_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
|
|
|
3534 #define EXTI_EMR1_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
|
|
|
3535 #define EXTI_EMR1_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
|
|
|
3536 #define EXTI_EMR1_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
|
|
|
3537 #define EXTI_EMR1_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
|
|
|
3538 #define EXTI_EMR1_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
|
|
|
3539 #define EXTI_EMR1_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
|
|
|
3540 #define EXTI_EMR1_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
|
|
|
3541 #define EXTI_EMR1_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
|
|
|
3542 #define EXTI_EMR1_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
|
|
|
3543 #define EXTI_EMR1_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
|
|
|
3544 #define EXTI_EMR1_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
|
|
|
3545 #define EXTI_EMR1_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
|
|
|
3546 #define EXTI_EMR1_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
|
|
|
3547 #define EXTI_EMR1_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
|
|
|
3548 #define EXTI_EMR1_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
|
|
|
3549 #define EXTI_EMR1_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
|
|
|
3550 #define EXTI_EMR1_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
|
|
|
3551 #define EXTI_EMR1_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
|
|
|
3552 #define EXTI_EMR1_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
|
|
|
3553 #define EXTI_EMR1_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
|
|
|
3554 #define EXTI_EMR1_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
|
|
|
3555 #define EXTI_EMR1_EM24 ((uint32_t)0x01000000U) /*!< Event Mask on line 24 */
|
|
|
3556 #define EXTI_EMR1_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */
|
|
|
3557 #define EXTI_EMR1_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */
|
|
|
3558 #define EXTI_EMR1_EM27 ((uint32_t)0x08000000U) /*!< Event Mask on line 27 */
|
|
|
3559 #define EXTI_EMR1_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */
|
|
|
3560 #define EXTI_EMR1_EM31 ((uint32_t)0x80000000U) /*!< Event Mask on line 31 */
|
|
|
3561
|
|
|
3562 /****************** Bit definition for EXTI_RTSR1 register ******************/
|
|
|
3563 #define EXTI_RTSR1_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
|
|
|
3564 #define EXTI_RTSR1_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
|
|
|
3565 #define EXTI_RTSR1_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
|
|
|
3566 #define EXTI_RTSR1_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
|
|
|
3567 #define EXTI_RTSR1_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
|
|
|
3568 #define EXTI_RTSR1_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
|
|
|
3569 #define EXTI_RTSR1_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
|
|
|
3570 #define EXTI_RTSR1_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
|
|
|
3571 #define EXTI_RTSR1_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
|
|
|
3572 #define EXTI_RTSR1_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
|
|
|
3573 #define EXTI_RTSR1_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
|
|
|
3574 #define EXTI_RTSR1_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
|
|
|
3575 #define EXTI_RTSR1_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
|
|
|
3576 #define EXTI_RTSR1_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
|
|
|
3577 #define EXTI_RTSR1_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
|
|
|
3578 #define EXTI_RTSR1_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
|
|
|
3579 #define EXTI_RTSR1_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
|
|
|
3580 #define EXTI_RTSR1_RT18 ((uint32_t)0x00040000U) /*!< Rising trigger event configuration bit of line 18 */
|
|
|
3581 #define EXTI_RTSR1_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
|
|
|
3582 #define EXTI_RTSR1_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
|
|
|
3583 #define EXTI_RTSR1_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
|
|
|
3584 #define EXTI_RTSR1_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
|
|
|
3585
|
|
|
3586 /****************** Bit definition for EXTI_FTSR1 register ******************/
|
|
|
3587 #define EXTI_FTSR1_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
|
|
|
3588 #define EXTI_FTSR1_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
|
|
|
3589 #define EXTI_FTSR1_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
|
|
|
3590 #define EXTI_FTSR1_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
|
|
|
3591 #define EXTI_FTSR1_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
|
|
|
3592 #define EXTI_FTSR1_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
|
|
|
3593 #define EXTI_FTSR1_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
|
|
|
3594 #define EXTI_FTSR1_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
|
|
|
3595 #define EXTI_FTSR1_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
|
|
|
3596 #define EXTI_FTSR1_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
|
|
|
3597 #define EXTI_FTSR1_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
|
|
|
3598 #define EXTI_FTSR1_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
|
|
|
3599 #define EXTI_FTSR1_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
|
|
|
3600 #define EXTI_FTSR1_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
|
|
|
3601 #define EXTI_FTSR1_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
|
|
|
3602 #define EXTI_FTSR1_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
|
|
|
3603 #define EXTI_FTSR1_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
|
|
|
3604 #define EXTI_FTSR1_FT18 ((uint32_t)0x00040000U) /*!< Falling trigger event configuration bit of line 18 */
|
|
|
3605 #define EXTI_FTSR1_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
|
|
|
3606 #define EXTI_FTSR1_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
|
|
|
3607 #define EXTI_FTSR1_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
|
|
|
3608 #define EXTI_FTSR1_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
|
|
|
3609
|
|
|
3610 /****************** Bit definition for EXTI_SWIER1 register *****************/
|
|
|
3611 #define EXTI_SWIER1_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
|
|
|
3612 #define EXTI_SWIER1_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
|
|
|
3613 #define EXTI_SWIER1_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
|
|
|
3614 #define EXTI_SWIER1_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
|
|
|
3615 #define EXTI_SWIER1_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
|
|
|
3616 #define EXTI_SWIER1_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
|
|
|
3617 #define EXTI_SWIER1_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
|
|
|
3618 #define EXTI_SWIER1_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
|
|
|
3619 #define EXTI_SWIER1_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
|
|
|
3620 #define EXTI_SWIER1_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
|
|
|
3621 #define EXTI_SWIER1_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
|
|
|
3622 #define EXTI_SWIER1_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
|
|
|
3623 #define EXTI_SWIER1_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
|
|
|
3624 #define EXTI_SWIER1_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
|
|
|
3625 #define EXTI_SWIER1_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
|
|
|
3626 #define EXTI_SWIER1_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
|
|
|
3627 #define EXTI_SWIER1_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
|
|
|
3628 #define EXTI_SWIER1_SWI18 ((uint32_t)0x00040000U) /*!< Software Interrupt on line 18 */
|
|
|
3629 #define EXTI_SWIER1_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
|
|
|
3630 #define EXTI_SWIER1_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
|
|
|
3631 #define EXTI_SWIER1_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
|
|
|
3632 #define EXTI_SWIER1_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
|
|
|
3633
|
|
|
3634 /******************* Bit definition for EXTI_PR1 register *******************/
|
|
|
3635 #define EXTI_PR1_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit for line 0 */
|
|
|
3636 #define EXTI_PR1_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit for line 1 */
|
|
|
3637 #define EXTI_PR1_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit for line 2 */
|
|
|
3638 #define EXTI_PR1_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit for line 3 */
|
|
|
3639 #define EXTI_PR1_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit for line 4 */
|
|
|
3640 #define EXTI_PR1_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit for line 5 */
|
|
|
3641 #define EXTI_PR1_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit for line 6 */
|
|
|
3642 #define EXTI_PR1_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit for line 7 */
|
|
|
3643 #define EXTI_PR1_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit for line 8 */
|
|
|
3644 #define EXTI_PR1_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit for line 9 */
|
|
|
3645 #define EXTI_PR1_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit for line 10 */
|
|
|
3646 #define EXTI_PR1_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit for line 11 */
|
|
|
3647 #define EXTI_PR1_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit for line 12 */
|
|
|
3648 #define EXTI_PR1_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit for line 13 */
|
|
|
3649 #define EXTI_PR1_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit for line 14 */
|
|
|
3650 #define EXTI_PR1_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit for line 15 */
|
|
|
3651 #define EXTI_PR1_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit for line 16 */
|
|
|
3652 #define EXTI_PR1_PIF18 ((uint32_t)0x00040000U) /*!< Pending bit for line 18 */
|
|
|
3653 #define EXTI_PR1_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit for line 19 */
|
|
|
3654 #define EXTI_PR1_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit for line 20 */
|
|
|
3655 #define EXTI_PR1_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit for line 21 */
|
|
|
3656 #define EXTI_PR1_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit for line 22 */
|
|
|
3657
|
|
|
3658 /******************* Bit definition for EXTI_IMR2 register ******************/
|
|
|
3659 #define EXTI_IMR2_IM32 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 32 */
|
|
|
3660 #define EXTI_IMR2_IM33 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 33 */
|
|
|
3661 #define EXTI_IMR2_IM34 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 34 */
|
|
|
3662 #define EXTI_IMR2_IM35 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 35 */
|
|
|
3663 #define EXTI_IMR2_IM36 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 36 */
|
|
|
3664 #define EXTI_IMR2_IM37 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 37 */
|
|
|
3665 #define EXTI_IMR2_IM38 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 38 */
|
|
|
3666 #define EXTI_IMR2_IM39 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 39 */
|
|
|
3667 #define EXTI_IMR2_IM ((uint32_t)0x000000FFU) /*!< Interrupt Mask on line 39 */
|
|
|
3668
|
|
|
3669 /******************* Bit definition for EXTI_EMR2 register ******************/
|
|
|
3670 #define EXTI_EMR2_EM32 ((uint32_t)0x00000001U) /*!< Event Mask on line 32 */
|
|
|
3671 #define EXTI_EMR2_EM33 ((uint32_t)0x00000002U) /*!< Event Mask on line 33 */
|
|
|
3672 #define EXTI_EMR2_EM34 ((uint32_t)0x00000004U) /*!< Event Mask on line 34 */
|
|
|
3673 #define EXTI_EMR2_EM35 ((uint32_t)0x00000008U) /*!< Event Mask on line 35 */
|
|
|
3674 #define EXTI_EMR2_EM36 ((uint32_t)0x00000010U) /*!< Event Mask on line 36 */
|
|
|
3675 #define EXTI_EMR2_EM37 ((uint32_t)0x00000020U) /*!< Event Mask on line 37 */
|
|
|
3676 #define EXTI_EMR2_EM38 ((uint32_t)0x00000040U) /*!< Event Mask on line 38 */
|
|
|
3677 #define EXTI_EMR2_EM39 ((uint32_t)0x00000080U) /*!< Event Mask on line 39 */
|
|
|
3678
|
|
|
3679 /****************** Bit definition for EXTI_RTSR2 register ******************/
|
|
|
3680 #define EXTI_RTSR2_RT35 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 35 */
|
|
|
3681 #define EXTI_RTSR2_RT36 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 36 */
|
|
|
3682 #define EXTI_RTSR2_RT37 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 37 */
|
|
|
3683 #define EXTI_RTSR2_RT38 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 38 */
|
|
|
3684
|
|
|
3685 /****************** Bit definition for EXTI_FTSR2 register ******************/
|
|
|
3686 #define EXTI_FTSR2_FT35 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 35 */
|
|
|
3687 #define EXTI_FTSR2_FT36 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 36 */
|
|
|
3688 #define EXTI_FTSR2_FT37 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 37 */
|
|
|
3689 #define EXTI_FTSR2_FT38 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 38 */
|
|
|
3690
|
|
|
3691 /****************** Bit definition for EXTI_SWIER2 register *****************/
|
|
|
3692 #define EXTI_SWIER2_SWI35 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 35 */
|
|
|
3693 #define EXTI_SWIER2_SWI36 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 36 */
|
|
|
3694 #define EXTI_SWIER2_SWI37 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 37 */
|
|
|
3695 #define EXTI_SWIER2_SWI38 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 38 */
|
|
|
3696
|
|
|
3697 /******************* Bit definition for EXTI_PR2 register *******************/
|
|
|
3698 #define EXTI_PR2_PIF35 ((uint32_t)0x00000008U) /*!< Pending bit for line 35 */
|
|
|
3699 #define EXTI_PR2_PIF36 ((uint32_t)0x00000010U) /*!< Pending bit for line 36 */
|
|
|
3700 #define EXTI_PR2_PIF37 ((uint32_t)0x00000020U) /*!< Pending bit for line 37 */
|
|
|
3701 #define EXTI_PR2_PIF38 ((uint32_t)0x00000040U) /*!< Pending bit for line 38 */
|
|
|
3702
|
|
|
3703
|
|
|
3704 /******************************************************************************/
|
|
|
3705 /* */
|
|
|
3706 /* FLASH */
|
|
|
3707 /* */
|
|
|
3708 /******************************************************************************/
|
|
|
3709 /******************* Bits definition for FLASH_ACR register *****************/
|
|
|
3710 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007U)
|
|
|
3711 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000U)
|
|
|
3712 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001U)
|
|
|
3713 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002U)
|
|
|
3714 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003U)
|
|
|
3715 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004U)
|
|
|
3716 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100U)
|
|
|
3717 #define FLASH_ACR_ICEN ((uint32_t)0x00000200U)
|
|
|
3718 #define FLASH_ACR_DCEN ((uint32_t)0x00000400U)
|
|
|
3719 #define FLASH_ACR_ICRST ((uint32_t)0x00000800U)
|
|
|
3720 #define FLASH_ACR_DCRST ((uint32_t)0x00001000U)
|
|
|
3721 #define FLASH_ACR_RUN_PD ((uint32_t)0x00002000U) /*!< Flash power down mode during run */
|
|
|
3722 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00004000U) /*!< Flash power down mode during sleep */
|
|
|
3723
|
|
|
3724 /******************* Bits definition for FLASH_SR register ******************/
|
|
|
3725 #define FLASH_SR_EOP ((uint32_t)0x00000001U)
|
|
|
3726 #define FLASH_SR_OPERR ((uint32_t)0x00000002U)
|
|
|
3727 #define FLASH_SR_PROGERR ((uint32_t)0x00000008U)
|
|
|
3728 #define FLASH_SR_WRPERR ((uint32_t)0x00000010U)
|
|
|
3729 #define FLASH_SR_PGAERR ((uint32_t)0x00000020U)
|
|
|
3730 #define FLASH_SR_SIZERR ((uint32_t)0x00000040U)
|
|
|
3731 #define FLASH_SR_PGSERR ((uint32_t)0x00000080U)
|
|
|
3732 #define FLASH_SR_MISERR ((uint32_t)0x00000100U)
|
|
|
3733 #define FLASH_SR_FASTERR ((uint32_t)0x00000200U)
|
|
|
3734 #define FLASH_SR_RDERR ((uint32_t)0x00004000U)
|
|
|
3735 #define FLASH_SR_OPTVERR ((uint32_t)0x00008000U)
|
|
|
3736 #define FLASH_SR_BSY ((uint32_t)0x00010000U)
|
|
|
3737 #define FLASH_SR_PEMPTY ((uint32_t)0x00020000U)
|
|
|
3738
|
|
|
3739 /******************* Bits definition for FLASH_CR register ******************/
|
|
|
3740 #define FLASH_CR_PG ((uint32_t)0x00000001U)
|
|
|
3741 #define FLASH_CR_PER ((uint32_t)0x00000002U)
|
|
|
3742 #define FLASH_CR_MER1 ((uint32_t)0x00000004U)
|
|
|
3743 #define FLASH_CR_PNB ((uint32_t)0x000007F8U)
|
|
|
3744 #define FLASH_CR_STRT ((uint32_t)0x00010000U)
|
|
|
3745 #define FLASH_CR_OPTSTRT ((uint32_t)0x00020000U)
|
|
|
3746 #define FLASH_CR_FSTPG ((uint32_t)0x00040000U)
|
|
|
3747 #define FLASH_CR_EOPIE ((uint32_t)0x01000000U)
|
|
|
3748 #define FLASH_CR_ERRIE ((uint32_t)0x02000000U)
|
|
|
3749 #define FLASH_CR_RDERRIE ((uint32_t)0x04000000U)
|
|
|
3750 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x08000000U)
|
|
|
3751 #define FLASH_CR_OPTLOCK ((uint32_t)0x40000000U)
|
|
|
3752 #define FLASH_CR_LOCK ((uint32_t)0x80000000U)
|
|
|
3753
|
|
|
3754 /******************* Bits definition for FLASH_ECCR register ***************/
|
|
|
3755 #define FLASH_ECCR_ADDR_ECC ((uint32_t)0x0007FFFFU)
|
|
|
3756 #define FLASH_ECCR_SYSF_ECC ((uint32_t)0x00100000U)
|
|
|
3757 #define FLASH_ECCR_ECCIE ((uint32_t)0x01000000U)
|
|
|
3758 #define FLASH_ECCR_ECCC ((uint32_t)0x40000000U)
|
|
|
3759 #define FLASH_ECCR_ECCD ((uint32_t)0x80000000U)
|
|
|
3760
|
|
|
3761 /******************* Bits definition for FLASH_OPTR register ***************/
|
|
|
3762 #define FLASH_OPTR_RDP ((uint32_t)0x000000FFU)
|
|
|
3763 #define FLASH_OPTR_BOR_LEV ((uint32_t)0x00000700U)
|
|
|
3764 #define FLASH_OPTR_BOR_LEV_0 ((uint32_t)0x00000000U)
|
|
|
3765 #define FLASH_OPTR_BOR_LEV_1 ((uint32_t)0x00000100U)
|
|
|
3766 #define FLASH_OPTR_BOR_LEV_2 ((uint32_t)0x00000200U)
|
|
|
3767 #define FLASH_OPTR_BOR_LEV_3 ((uint32_t)0x00000300U)
|
|
|
3768 #define FLASH_OPTR_BOR_LEV_4 ((uint32_t)0x00000400U)
|
|
|
3769 #define FLASH_OPTR_nRST_STOP ((uint32_t)0x00001000U)
|
|
|
3770 #define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00002000U)
|
|
|
3771 #define FLASH_OPTR_nRST_SHDW ((uint32_t)0x00004000U)
|
|
|
3772 #define FLASH_OPTR_IWDG_SW ((uint32_t)0x00010000U)
|
|
|
3773 #define FLASH_OPTR_IWDG_STOP ((uint32_t)0x00020000U)
|
|
|
3774 #define FLASH_OPTR_IWDG_STDBY ((uint32_t)0x00040000U)
|
|
|
3775 #define FLASH_OPTR_WWDG_SW ((uint32_t)0x00080000U)
|
|
|
3776 #define FLASH_OPTR_nBOOT1 ((uint32_t)0x00800000U)
|
|
|
3777 #define FLASH_OPTR_SRAM2_PE ((uint32_t)0x01000000U)
|
|
|
3778 #define FLASH_OPTR_SRAM2_RST ((uint32_t)0x02000000U)
|
|
|
3779 #define FLASH_OPTR_nSWBOOT0 ((uint32_t)0x04000000U)
|
|
|
3780 #define FLASH_OPTR_nBOOT0 ((uint32_t)0x08000000U)
|
|
|
3781
|
|
|
3782 /****************** Bits definition for FLASH_PCROP1SR register **********/
|
|
|
3783 #define FLASH_PCROP1SR_PCROP1_STRT ((uint32_t)0x0000FFFFU)
|
|
|
3784
|
|
|
3785 /****************** Bits definition for FLASH_PCROP1ER register ***********/
|
|
|
3786 #define FLASH_PCROP1ER_PCROP1_END ((uint32_t)0x0000FFFFU)
|
|
|
3787 #define FLASH_PCROP1ER_PCROP_RDP ((uint32_t)0x80000000U)
|
|
|
3788
|
|
|
3789 /****************** Bits definition for FLASH_WRP1AR register ***************/
|
|
|
3790 #define FLASH_WRP1AR_WRP1A_STRT ((uint32_t)0x000000FFU)
|
|
|
3791 #define FLASH_WRP1AR_WRP1A_END ((uint32_t)0x00FF0000U)
|
|
|
3792
|
|
|
3793 /****************** Bits definition for FLASH_WRPB1R register ***************/
|
|
|
3794 #define FLASH_WRP1BR_WRP1B_STRT ((uint32_t)0x000000FFU)
|
|
|
3795 #define FLASH_WRP1BR_WRP1B_END ((uint32_t)0x00FF0000U)
|
|
|
3796
|
|
|
3797
|
|
|
3798
|
|
|
3799
|
|
|
3800 /******************************************************************************/
|
|
|
3801 /* */
|
|
|
3802 /* General Purpose IOs (GPIO) */
|
|
|
3803 /* */
|
|
|
3804 /******************************************************************************/
|
|
|
3805 /****************** Bits definition for GPIO_MODER register *****************/
|
|
|
3806 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
|
|
|
3807 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
|
|
|
3808 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
|
|
|
3809 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
|
|
|
3810 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
|
|
|
3811 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
|
|
|
3812 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
|
|
|
3813 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
|
|
|
3814 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
|
|
|
3815 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
|
|
|
3816 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
|
|
|
3817 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
|
|
|
3818 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
|
|
|
3819 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
|
|
|
3820 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
|
|
|
3821 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
|
|
|
3822 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
|
|
|
3823 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
|
|
|
3824 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
|
|
|
3825 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
|
|
|
3826 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
|
|
|
3827 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
|
|
|
3828 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
|
|
|
3829 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
|
|
|
3830 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
|
|
|
3831 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
|
|
|
3832 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
|
|
|
3833 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
|
|
|
3834 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
|
|
|
3835 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
|
|
|
3836 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
|
|
|
3837 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
|
|
|
3838 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
|
|
|
3839 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
|
|
|
3840 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
|
|
|
3841 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
|
|
|
3842 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
|
|
|
3843 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
|
|
|
3844 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
|
|
|
3845 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
|
|
|
3846 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
|
|
|
3847 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
|
|
|
3848 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
|
|
|
3849 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
|
|
|
3850 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
|
|
|
3851 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
|
|
|
3852 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
|
|
|
3853 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
|
|
|
3854
|
|
|
3855 /* Legacy defines */
|
|
|
3856 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
|
|
|
3857 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
|
|
|
3858 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
|
|
|
3859 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
|
|
|
3860 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
|
|
|
3861 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
|
|
|
3862 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
|
|
|
3863 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
|
|
|
3864 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
|
|
|
3865 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
|
|
|
3866 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
|
|
|
3867 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
|
|
|
3868 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
|
|
|
3869 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
|
|
|
3870 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
|
|
|
3871 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
|
|
|
3872 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
|
|
|
3873 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
|
|
|
3874 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
|
|
|
3875 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
|
|
|
3876 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
|
|
|
3877 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
|
|
|
3878 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
|
|
|
3879 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
|
|
|
3880 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
|
|
|
3881 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
|
|
|
3882 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
|
|
|
3883 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
|
|
|
3884 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
|
|
|
3885 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
|
|
|
3886 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
|
|
|
3887 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
|
|
|
3888 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
|
|
|
3889 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
|
|
|
3890 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
|
|
|
3891 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
|
|
|
3892 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
|
|
|
3893 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
|
|
|
3894 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
|
|
|
3895 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
|
|
|
3896 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
|
|
|
3897 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
|
|
|
3898 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
|
|
|
3899 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
|
|
|
3900 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
|
|
|
3901 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
|
|
|
3902 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
|
|
|
3903 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
|
|
|
3904
|
|
|
3905 /****************** Bits definition for GPIO_OTYPER register ****************/
|
|
|
3906 #define GPIO_OTYPER_OT0 ((uint32_t)0x00000001U)
|
|
|
3907 #define GPIO_OTYPER_OT1 ((uint32_t)0x00000002U)
|
|
|
3908 #define GPIO_OTYPER_OT2 ((uint32_t)0x00000004U)
|
|
|
3909 #define GPIO_OTYPER_OT3 ((uint32_t)0x00000008U)
|
|
|
3910 #define GPIO_OTYPER_OT4 ((uint32_t)0x00000010U)
|
|
|
3911 #define GPIO_OTYPER_OT5 ((uint32_t)0x00000020U)
|
|
|
3912 #define GPIO_OTYPER_OT6 ((uint32_t)0x00000040U)
|
|
|
3913 #define GPIO_OTYPER_OT7 ((uint32_t)0x00000080U)
|
|
|
3914 #define GPIO_OTYPER_OT8 ((uint32_t)0x00000100U)
|
|
|
3915 #define GPIO_OTYPER_OT9 ((uint32_t)0x00000200U)
|
|
|
3916 #define GPIO_OTYPER_OT10 ((uint32_t)0x00000400U)
|
|
|
3917 #define GPIO_OTYPER_OT11 ((uint32_t)0x00000800U)
|
|
|
3918 #define GPIO_OTYPER_OT12 ((uint32_t)0x00001000U)
|
|
|
3919 #define GPIO_OTYPER_OT13 ((uint32_t)0x00002000U)
|
|
|
3920 #define GPIO_OTYPER_OT14 ((uint32_t)0x00004000U)
|
|
|
3921 #define GPIO_OTYPER_OT15 ((uint32_t)0x00008000U)
|
|
|
3922
|
|
|
3923 /* Legacy defines */
|
|
|
3924 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
|
|
|
3925 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
|
|
|
3926 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
|
|
|
3927 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
|
|
|
3928 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
|
|
|
3929 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
|
|
|
3930 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
|
|
|
3931 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
|
|
|
3932 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
|
|
|
3933 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
|
|
|
3934 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
|
|
|
3935 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
|
|
|
3936 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
|
|
|
3937 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
|
|
|
3938 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
|
|
|
3939 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
|
|
|
3940
|
|
|
3941 /****************** Bits definition for GPIO_OSPEEDR register ***************/
|
|
|
3942 #define GPIO_OSPEEDR_OSPEED0 ((uint32_t)0x00000003U)
|
|
|
3943 #define GPIO_OSPEEDR_OSPEED0_0 ((uint32_t)0x00000001U)
|
|
|
3944 #define GPIO_OSPEEDR_OSPEED0_1 ((uint32_t)0x00000002U)
|
|
|
3945 #define GPIO_OSPEEDR_OSPEED1 ((uint32_t)0x0000000CU)
|
|
|
3946 #define GPIO_OSPEEDR_OSPEED1_0 ((uint32_t)0x00000004U)
|
|
|
3947 #define GPIO_OSPEEDR_OSPEED1_1 ((uint32_t)0x00000008U)
|
|
|
3948 #define GPIO_OSPEEDR_OSPEED2 ((uint32_t)0x00000030U)
|
|
|
3949 #define GPIO_OSPEEDR_OSPEED2_0 ((uint32_t)0x00000010U)
|
|
|
3950 #define GPIO_OSPEEDR_OSPEED2_1 ((uint32_t)0x00000020U)
|
|
|
3951 #define GPIO_OSPEEDR_OSPEED3 ((uint32_t)0x000000C0U)
|
|
|
3952 #define GPIO_OSPEEDR_OSPEED3_0 ((uint32_t)0x00000040U)
|
|
|
3953 #define GPIO_OSPEEDR_OSPEED3_1 ((uint32_t)0x00000080U)
|
|
|
3954 #define GPIO_OSPEEDR_OSPEED4 ((uint32_t)0x00000300U)
|
|
|
3955 #define GPIO_OSPEEDR_OSPEED4_0 ((uint32_t)0x00000100U)
|
|
|
3956 #define GPIO_OSPEEDR_OSPEED4_1 ((uint32_t)0x00000200U)
|
|
|
3957 #define GPIO_OSPEEDR_OSPEED5 ((uint32_t)0x00000C00U)
|
|
|
3958 #define GPIO_OSPEEDR_OSPEED5_0 ((uint32_t)0x00000400U)
|
|
|
3959 #define GPIO_OSPEEDR_OSPEED5_1 ((uint32_t)0x00000800U)
|
|
|
3960 #define GPIO_OSPEEDR_OSPEED6 ((uint32_t)0x00003000U)
|
|
|
3961 #define GPIO_OSPEEDR_OSPEED6_0 ((uint32_t)0x00001000U)
|
|
|
3962 #define GPIO_OSPEEDR_OSPEED6_1 ((uint32_t)0x00002000U)
|
|
|
3963 #define GPIO_OSPEEDR_OSPEED7 ((uint32_t)0x0000C000U)
|
|
|
3964 #define GPIO_OSPEEDR_OSPEED7_0 ((uint32_t)0x00004000U)
|
|
|
3965 #define GPIO_OSPEEDR_OSPEED7_1 ((uint32_t)0x00008000U)
|
|
|
3966 #define GPIO_OSPEEDR_OSPEED8 ((uint32_t)0x00030000U)
|
|
|
3967 #define GPIO_OSPEEDR_OSPEED8_0 ((uint32_t)0x00010000U)
|
|
|
3968 #define GPIO_OSPEEDR_OSPEED8_1 ((uint32_t)0x00020000U)
|
|
|
3969 #define GPIO_OSPEEDR_OSPEED9 ((uint32_t)0x000C0000U)
|
|
|
3970 #define GPIO_OSPEEDR_OSPEED9_0 ((uint32_t)0x00040000U)
|
|
|
3971 #define GPIO_OSPEEDR_OSPEED9_1 ((uint32_t)0x00080000U)
|
|
|
3972 #define GPIO_OSPEEDR_OSPEED10 ((uint32_t)0x00300000U)
|
|
|
3973 #define GPIO_OSPEEDR_OSPEED10_0 ((uint32_t)0x00100000U)
|
|
|
3974 #define GPIO_OSPEEDR_OSPEED10_1 ((uint32_t)0x00200000U)
|
|
|
3975 #define GPIO_OSPEEDR_OSPEED11 ((uint32_t)0x00C00000U)
|
|
|
3976 #define GPIO_OSPEEDR_OSPEED11_0 ((uint32_t)0x00400000U)
|
|
|
3977 #define GPIO_OSPEEDR_OSPEED11_1 ((uint32_t)0x00800000U)
|
|
|
3978 #define GPIO_OSPEEDR_OSPEED12 ((uint32_t)0x03000000U)
|
|
|
3979 #define GPIO_OSPEEDR_OSPEED12_0 ((uint32_t)0x01000000U)
|
|
|
3980 #define GPIO_OSPEEDR_OSPEED12_1 ((uint32_t)0x02000000U)
|
|
|
3981 #define GPIO_OSPEEDR_OSPEED13 ((uint32_t)0x0C000000U)
|
|
|
3982 #define GPIO_OSPEEDR_OSPEED13_0 ((uint32_t)0x04000000U)
|
|
|
3983 #define GPIO_OSPEEDR_OSPEED13_1 ((uint32_t)0x08000000U)
|
|
|
3984 #define GPIO_OSPEEDR_OSPEED14 ((uint32_t)0x30000000U)
|
|
|
3985 #define GPIO_OSPEEDR_OSPEED14_0 ((uint32_t)0x10000000U)
|
|
|
3986 #define GPIO_OSPEEDR_OSPEED14_1 ((uint32_t)0x20000000U)
|
|
|
3987 #define GPIO_OSPEEDR_OSPEED15 ((uint32_t)0xC0000000U)
|
|
|
3988 #define GPIO_OSPEEDR_OSPEED15_0 ((uint32_t)0x40000000U)
|
|
|
3989 #define GPIO_OSPEEDR_OSPEED15_1 ((uint32_t)0x80000000U)
|
|
|
3990
|
|
|
3991 /* Legacy defines */
|
|
|
3992 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
|
|
|
3993 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
|
|
|
3994 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
|
|
|
3995 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
|
|
|
3996 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
|
|
|
3997 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
|
|
|
3998 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
|
|
|
3999 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
|
|
|
4000 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
|
|
|
4001 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
|
|
|
4002 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
|
|
|
4003 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
|
|
|
4004 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
|
|
|
4005 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
|
|
|
4006 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
|
|
|
4007 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
|
|
|
4008 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
|
|
|
4009 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
|
|
|
4010 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
|
|
|
4011 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
|
|
|
4012 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
|
|
|
4013 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
|
|
|
4014 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
|
|
|
4015 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
|
|
|
4016 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
|
|
|
4017 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
|
|
|
4018 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
|
|
|
4019 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
|
|
|
4020 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
|
|
|
4021 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
|
|
|
4022 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
|
|
|
4023 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
|
|
|
4024 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
|
|
|
4025 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
|
|
|
4026 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
|
|
|
4027 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
|
|
|
4028 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
|
|
|
4029 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
|
|
|
4030 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
|
|
|
4031 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
|
|
|
4032 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
|
|
|
4033 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
|
|
|
4034 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
|
|
|
4035 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
|
|
|
4036 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
|
|
|
4037 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
|
|
|
4038 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
|
|
|
4039 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
|
|
|
4040
|
|
|
4041 /****************** Bits definition for GPIO_PUPDR register *****************/
|
|
|
4042 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
|
|
|
4043 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
|
|
|
4044 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
|
|
|
4045 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
|
|
|
4046 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
|
|
|
4047 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
|
|
|
4048 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
|
|
|
4049 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
|
|
|
4050 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
|
|
|
4051 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
|
|
|
4052 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
|
|
|
4053 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
|
|
|
4054 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
|
|
|
4055 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
|
|
|
4056 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
|
|
|
4057 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
|
|
|
4058 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
|
|
|
4059 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
|
|
|
4060 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
|
|
|
4061 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
|
|
|
4062 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
|
|
|
4063 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
|
|
|
4064 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
|
|
|
4065 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
|
|
|
4066 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
|
|
|
4067 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
|
|
|
4068 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
|
|
|
4069 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
|
|
|
4070 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
|
|
|
4071 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
|
|
|
4072 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
|
|
|
4073 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
|
|
|
4074 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
|
|
|
4075 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
|
|
|
4076 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
|
|
|
4077 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
|
|
|
4078 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
|
|
|
4079 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
|
|
|
4080 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
|
|
|
4081 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
|
|
|
4082 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
|
|
|
4083 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
|
|
|
4084 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
|
|
|
4085 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
|
|
|
4086 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
|
|
|
4087 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
|
|
|
4088 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
|
|
|
4089 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
|
|
|
4090
|
|
|
4091 /* Legacy defines */
|
|
|
4092 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
|
|
|
4093 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
|
|
|
4094 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
|
|
|
4095 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
|
|
|
4096 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
|
|
|
4097 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
|
|
|
4098 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
|
|
|
4099 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
|
|
|
4100 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
|
|
|
4101 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
|
|
|
4102 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
|
|
|
4103 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
|
|
|
4104 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
|
|
|
4105 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
|
|
|
4106 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
|
|
|
4107 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
|
|
|
4108 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
|
|
|
4109 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
|
|
|
4110 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
|
|
|
4111 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
|
|
|
4112 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
|
|
|
4113 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
|
|
|
4114 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
|
|
|
4115 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
|
|
|
4116 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
|
|
|
4117 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
|
|
|
4118 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
|
|
|
4119 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
|
|
|
4120 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
|
|
|
4121 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
|
|
|
4122 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
|
|
|
4123 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
|
|
|
4124 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
|
|
|
4125 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
|
|
|
4126 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
|
|
|
4127 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
|
|
|
4128 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
|
|
|
4129 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
|
|
|
4130 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
|
|
|
4131 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
|
|
|
4132 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
|
|
|
4133 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
|
|
|
4134 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
|
|
|
4135 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
|
|
|
4136 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
|
|
|
4137 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
|
|
|
4138 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
|
|
|
4139 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
|
|
|
4140
|
|
|
4141 /****************** Bits definition for GPIO_IDR register *******************/
|
|
|
4142 #define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
|
|
|
4143 #define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
|
|
|
4144 #define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
|
|
|
4145 #define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
|
|
|
4146 #define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
|
|
|
4147 #define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
|
|
|
4148 #define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
|
|
|
4149 #define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
|
|
|
4150 #define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
|
|
|
4151 #define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
|
|
|
4152 #define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
|
|
|
4153 #define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
|
|
|
4154 #define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
|
|
|
4155 #define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
|
|
|
4156 #define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
|
|
|
4157 #define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
|
|
|
4158
|
|
|
4159 /* Legacy defines */
|
|
|
4160 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
|
|
|
4161 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
|
|
|
4162 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
|
|
|
4163 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
|
|
|
4164 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
|
|
|
4165 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
|
|
|
4166 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
|
|
|
4167 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
|
|
|
4168 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
|
|
|
4169 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
|
|
|
4170 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
|
|
|
4171 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
|
|
|
4172 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
|
|
|
4173 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
|
|
|
4174 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
|
|
|
4175 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
|
|
|
4176
|
|
|
4177 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
|
|
|
4178 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
|
|
|
4179 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
|
|
|
4180 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
|
|
|
4181 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
|
|
|
4182 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
|
|
|
4183 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
|
|
|
4184 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
|
|
|
4185 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
|
|
|
4186 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
|
|
|
4187 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
|
|
|
4188 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
|
|
|
4189 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
|
|
|
4190 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
|
|
|
4191 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
|
|
|
4192 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
|
|
|
4193 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
|
|
|
4194
|
|
|
4195 /****************** Bits definition for GPIO_ODR register *******************/
|
|
|
4196 #define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
|
|
|
4197 #define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
|
|
|
4198 #define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
|
|
|
4199 #define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
|
|
|
4200 #define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
|
|
|
4201 #define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
|
|
|
4202 #define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
|
|
|
4203 #define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
|
|
|
4204 #define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
|
|
|
4205 #define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
|
|
|
4206 #define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
|
|
|
4207 #define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
|
|
|
4208 #define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
|
|
|
4209 #define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
|
|
|
4210 #define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
|
|
|
4211 #define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
|
|
|
4212
|
|
|
4213 /* Legacy defines */
|
|
|
4214 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
|
|
|
4215 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
|
|
|
4216 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
|
|
|
4217 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
|
|
|
4218 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
|
|
|
4219 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
|
|
|
4220 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
|
|
|
4221 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
|
|
|
4222 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
|
|
|
4223 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
|
|
|
4224 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
|
|
|
4225 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
|
|
|
4226 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
|
|
|
4227 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
|
|
|
4228 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
|
|
|
4229 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
|
|
|
4230
|
|
|
4231 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
|
|
|
4232 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
|
|
|
4233 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
|
|
|
4234 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
|
|
|
4235 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
|
|
|
4236 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
|
|
|
4237 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
|
|
|
4238 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
|
|
|
4239 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
|
|
|
4240 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
|
|
|
4241 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
|
|
|
4242 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
|
|
|
4243 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
|
|
|
4244 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
|
|
|
4245 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
|
|
|
4246 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
|
|
|
4247 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
|
|
|
4248
|
|
|
4249 /****************** Bits definition for GPIO_BSRR register ******************/
|
|
|
4250 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001U)
|
|
|
4251 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002U)
|
|
|
4252 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004U)
|
|
|
4253 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008U)
|
|
|
4254 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010U)
|
|
|
4255 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020U)
|
|
|
4256 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040U)
|
|
|
4257 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080U)
|
|
|
4258 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100U)
|
|
|
4259 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200U)
|
|
|
4260 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400U)
|
|
|
4261 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800U)
|
|
|
4262 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000U)
|
|
|
4263 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000U)
|
|
|
4264 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000U)
|
|
|
4265 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000U)
|
|
|
4266 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000U)
|
|
|
4267 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000U)
|
|
|
4268 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000U)
|
|
|
4269 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000U)
|
|
|
4270 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000U)
|
|
|
4271 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000U)
|
|
|
4272 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000U)
|
|
|
4273 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000U)
|
|
|
4274 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000U)
|
|
|
4275 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000U)
|
|
|
4276 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000U)
|
|
|
4277 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000U)
|
|
|
4278 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000U)
|
|
|
4279 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000U)
|
|
|
4280 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000U)
|
|
|
4281 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000U)
|
|
|
4282
|
|
|
4283 /* Legacy defines */
|
|
|
4284 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
|
|
|
4285 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
|
|
|
4286 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
|
|
|
4287 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
|
|
|
4288 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
|
|
|
4289 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
|
|
|
4290 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
|
|
|
4291 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
|
|
|
4292 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
|
|
|
4293 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
|
|
|
4294 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
|
|
|
4295 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
|
|
|
4296 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
|
|
|
4297 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
|
|
|
4298 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
|
|
|
4299 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
|
|
|
4300 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
|
|
|
4301 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
|
|
|
4302 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
|
|
|
4303 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
|
|
|
4304 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
|
|
|
4305 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
|
|
|
4306 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
|
|
|
4307 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
|
|
|
4308 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
|
|
|
4309 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
|
|
|
4310 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
|
|
|
4311 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
|
|
|
4312 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
|
|
|
4313 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
|
|
|
4314 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
|
|
|
4315 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
|
|
|
4316
|
|
|
4317 /****************** Bit definition for GPIO_LCKR register *********************/
|
|
|
4318 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
|
|
|
4319 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
|
|
|
4320 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
|
|
|
4321 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
|
|
|
4322 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
|
|
|
4323 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
|
|
|
4324 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
|
|
|
4325 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
|
|
|
4326 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
|
|
|
4327 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
|
|
|
4328 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
|
|
|
4329 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
|
|
|
4330 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
|
|
|
4331 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
|
|
|
4332 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
|
|
|
4333 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
|
|
|
4334 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
|
|
|
4335
|
|
|
4336 /****************** Bit definition for GPIO_AFRL register *********************/
|
|
|
4337 #define GPIO_AFRL_AFSEL0 ((uint32_t)0x0000000FU)
|
|
|
4338 #define GPIO_AFRL_AFSEL0_0 ((uint32_t)0x00000001U)
|
|
|
4339 #define GPIO_AFRL_AFSEL0_1 ((uint32_t)0x00000002U)
|
|
|
4340 #define GPIO_AFRL_AFSEL0_2 ((uint32_t)0x00000004U)
|
|
|
4341 #define GPIO_AFRL_AFSEL0_3 ((uint32_t)0x00000008U)
|
|
|
4342 #define GPIO_AFRL_AFSEL1 ((uint32_t)0x000000F0U)
|
|
|
4343 #define GPIO_AFRL_AFSEL1_0 ((uint32_t)0x00000010U)
|
|
|
4344 #define GPIO_AFRL_AFSEL1_1 ((uint32_t)0x00000020U)
|
|
|
4345 #define GPIO_AFRL_AFSEL1_2 ((uint32_t)0x00000040U)
|
|
|
4346 #define GPIO_AFRL_AFSEL1_3 ((uint32_t)0x00000080U)
|
|
|
4347 #define GPIO_AFRL_AFSEL2 ((uint32_t)0x00000F00U)
|
|
|
4348 #define GPIO_AFRL_AFSEL2_0 ((uint32_t)0x00000100U)
|
|
|
4349 #define GPIO_AFRL_AFSEL2_1 ((uint32_t)0x00000200U)
|
|
|
4350 #define GPIO_AFRL_AFSEL2_2 ((uint32_t)0x00000400U)
|
|
|
4351 #define GPIO_AFRL_AFSEL2_3 ((uint32_t)0x00000800U)
|
|
|
4352 #define GPIO_AFRL_AFSEL3 ((uint32_t)0x0000F000U)
|
|
|
4353 #define GPIO_AFRL_AFSEL3_0 ((uint32_t)0x00001000U)
|
|
|
4354 #define GPIO_AFRL_AFSEL3_1 ((uint32_t)0x00002000U)
|
|
|
4355 #define GPIO_AFRL_AFSEL3_2 ((uint32_t)0x00004000U)
|
|
|
4356 #define GPIO_AFRL_AFSEL3_3 ((uint32_t)0x00008000U)
|
|
|
4357 #define GPIO_AFRL_AFSEL4 ((uint32_t)0x000F0000U)
|
|
|
4358 #define GPIO_AFRL_AFSEL4_0 ((uint32_t)0x00010000U)
|
|
|
4359 #define GPIO_AFRL_AFSEL4_1 ((uint32_t)0x00020000U)
|
|
|
4360 #define GPIO_AFRL_AFSEL4_2 ((uint32_t)0x00040000U)
|
|
|
4361 #define GPIO_AFRL_AFSEL4_3 ((uint32_t)0x00080000U)
|
|
|
4362 #define GPIO_AFRL_AFSEL5 ((uint32_t)0x00F00000U)
|
|
|
4363 #define GPIO_AFRL_AFSEL5_0 ((uint32_t)0x00100000U)
|
|
|
4364 #define GPIO_AFRL_AFSEL5_1 ((uint32_t)0x00200000U)
|
|
|
4365 #define GPIO_AFRL_AFSEL5_2 ((uint32_t)0x00400000U)
|
|
|
4366 #define GPIO_AFRL_AFSEL5_3 ((uint32_t)0x00800000U)
|
|
|
4367 #define GPIO_AFRL_AFSEL6 ((uint32_t)0x0F000000U)
|
|
|
4368 #define GPIO_AFRL_AFSEL6_0 ((uint32_t)0x01000000U)
|
|
|
4369 #define GPIO_AFRL_AFSEL6_1 ((uint32_t)0x02000000U)
|
|
|
4370 #define GPIO_AFRL_AFSEL6_2 ((uint32_t)0x04000000U)
|
|
|
4371 #define GPIO_AFRL_AFSEL6_3 ((uint32_t)0x08000000U)
|
|
|
4372 #define GPIO_AFRL_AFSEL7 ((uint32_t)0xF0000000U)
|
|
|
4373 #define GPIO_AFRL_AFSEL7_0 ((uint32_t)0x10000000U)
|
|
|
4374 #define GPIO_AFRL_AFSEL7_1 ((uint32_t)0x20000000U)
|
|
|
4375 #define GPIO_AFRL_AFSEL7_2 ((uint32_t)0x40000000U)
|
|
|
4376 #define GPIO_AFRL_AFSEL7_3 ((uint32_t)0x80000000U)
|
|
|
4377
|
|
|
4378 /* Legacy defines */
|
|
|
4379 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
|
|
|
4380 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
|
|
|
4381 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
|
|
|
4382 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
|
|
|
4383 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
|
|
|
4384 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
|
|
|
4385 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
|
|
|
4386 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
|
|
|
4387
|
|
|
4388 /****************** Bit definition for GPIO_AFRH register *********************/
|
|
|
4389 #define GPIO_AFRH_AFSEL8 ((uint32_t)0x0000000FU)
|
|
|
4390 #define GPIO_AFRH_AFSEL8_0 ((uint32_t)0x00000001U)
|
|
|
4391 #define GPIO_AFRH_AFSEL8_1 ((uint32_t)0x00000002U)
|
|
|
4392 #define GPIO_AFRH_AFSEL8_2 ((uint32_t)0x00000004U)
|
|
|
4393 #define GPIO_AFRH_AFSEL8_3 ((uint32_t)0x00000008U)
|
|
|
4394 #define GPIO_AFRH_AFSEL9 ((uint32_t)0x000000F0U)
|
|
|
4395 #define GPIO_AFRH_AFSEL9_0 ((uint32_t)0x00000010U)
|
|
|
4396 #define GPIO_AFRH_AFSEL9_1 ((uint32_t)0x00000020U)
|
|
|
4397 #define GPIO_AFRH_AFSEL9_2 ((uint32_t)0x00000040U)
|
|
|
4398 #define GPIO_AFRH_AFSEL9_3 ((uint32_t)0x00000080U)
|
|
|
4399 #define GPIO_AFRH_AFSEL10 ((uint32_t)0x00000F00U)
|
|
|
4400 #define GPIO_AFRH_AFSEL10_0 ((uint32_t)0x00000100U)
|
|
|
4401 #define GPIO_AFRH_AFSEL10_1 ((uint32_t)0x00000200U)
|
|
|
4402 #define GPIO_AFRH_AFSEL10_2 ((uint32_t)0x00000400U)
|
|
|
4403 #define GPIO_AFRH_AFSEL10_3 ((uint32_t)0x00000800U)
|
|
|
4404 #define GPIO_AFRH_AFSEL11 ((uint32_t)0x0000F000U)
|
|
|
4405 #define GPIO_AFRH_AFSEL11_0 ((uint32_t)0x00001000U)
|
|
|
4406 #define GPIO_AFRH_AFSEL11_1 ((uint32_t)0x00002000U)
|
|
|
4407 #define GPIO_AFRH_AFSEL11_2 ((uint32_t)0x00004000U)
|
|
|
4408 #define GPIO_AFRH_AFSEL11_3 ((uint32_t)0x00008000U)
|
|
|
4409 #define GPIO_AFRH_AFSEL12 ((uint32_t)0x000F0000U)
|
|
|
4410 #define GPIO_AFRH_AFSEL12_0 ((uint32_t)0x00010000U)
|
|
|
4411 #define GPIO_AFRH_AFSEL12_1 ((uint32_t)0x00020000U)
|
|
|
4412 #define GPIO_AFRH_AFSEL12_2 ((uint32_t)0x00040000U)
|
|
|
4413 #define GPIO_AFRH_AFSEL12_3 ((uint32_t)0x00080000U)
|
|
|
4414 #define GPIO_AFRH_AFSEL13 ((uint32_t)0x00F00000U)
|
|
|
4415 #define GPIO_AFRH_AFSEL13_0 ((uint32_t)0x00100000U)
|
|
|
4416 #define GPIO_AFRH_AFSEL13_1 ((uint32_t)0x00200000U)
|
|
|
4417 #define GPIO_AFRH_AFSEL13_2 ((uint32_t)0x00400000U)
|
|
|
4418 #define GPIO_AFRH_AFSEL13_3 ((uint32_t)0x00800000U)
|
|
|
4419 #define GPIO_AFRH_AFSEL14 ((uint32_t)0x0F000000U)
|
|
|
4420 #define GPIO_AFRH_AFSEL14_0 ((uint32_t)0x01000000U)
|
|
|
4421 #define GPIO_AFRH_AFSEL14_1 ((uint32_t)0x02000000U)
|
|
|
4422 #define GPIO_AFRH_AFSEL14_2 ((uint32_t)0x04000000U)
|
|
|
4423 #define GPIO_AFRH_AFSEL14_3 ((uint32_t)0x08000000U)
|
|
|
4424 #define GPIO_AFRH_AFSEL15 ((uint32_t)0xF0000000U)
|
|
|
4425 #define GPIO_AFRH_AFSEL15_0 ((uint32_t)0x10000000U)
|
|
|
4426 #define GPIO_AFRH_AFSEL15_1 ((uint32_t)0x20000000U)
|
|
|
4427 #define GPIO_AFRH_AFSEL15_2 ((uint32_t)0x40000000U)
|
|
|
4428 #define GPIO_AFRH_AFSEL15_3 ((uint32_t)0x80000000U)
|
|
|
4429
|
|
|
4430 /* Legacy defines */
|
|
|
4431 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
|
|
|
4432 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
|
|
|
4433 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
|
|
|
4434 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
|
|
|
4435 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
|
|
|
4436 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
|
|
|
4437 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
|
|
|
4438 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
|
|
|
4439
|
|
|
4440 /****************** Bits definition for GPIO_BRR register ******************/
|
|
|
4441 #define GPIO_BRR_BR0 ((uint32_t)0x00000001U)
|
|
|
4442 #define GPIO_BRR_BR1 ((uint32_t)0x00000002U)
|
|
|
4443 #define GPIO_BRR_BR2 ((uint32_t)0x00000004U)
|
|
|
4444 #define GPIO_BRR_BR3 ((uint32_t)0x00000008U)
|
|
|
4445 #define GPIO_BRR_BR4 ((uint32_t)0x00000010U)
|
|
|
4446 #define GPIO_BRR_BR5 ((uint32_t)0x00000020U)
|
|
|
4447 #define GPIO_BRR_BR6 ((uint32_t)0x00000040U)
|
|
|
4448 #define GPIO_BRR_BR7 ((uint32_t)0x00000080U)
|
|
|
4449 #define GPIO_BRR_BR8 ((uint32_t)0x00000100U)
|
|
|
4450 #define GPIO_BRR_BR9 ((uint32_t)0x00000200U)
|
|
|
4451 #define GPIO_BRR_BR10 ((uint32_t)0x00000400U)
|
|
|
4452 #define GPIO_BRR_BR11 ((uint32_t)0x00000800U)
|
|
|
4453 #define GPIO_BRR_BR12 ((uint32_t)0x00001000U)
|
|
|
4454 #define GPIO_BRR_BR13 ((uint32_t)0x00002000U)
|
|
|
4455 #define GPIO_BRR_BR14 ((uint32_t)0x00004000U)
|
|
|
4456 #define GPIO_BRR_BR15 ((uint32_t)0x00008000U)
|
|
|
4457
|
|
|
4458 /* Legacy defines */
|
|
|
4459 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
|
|
|
4460 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
|
|
|
4461 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
|
|
|
4462 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
|
|
|
4463 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
|
|
|
4464 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
|
|
|
4465 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
|
|
|
4466 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
|
|
|
4467 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
|
|
|
4468 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
|
|
|
4469 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
|
|
|
4470 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
|
|
|
4471 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
|
|
|
4472 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
|
|
|
4473 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
|
|
|
4474 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
|
|
|
4475
|
|
|
4476
|
|
|
4477
|
|
|
4478 /******************************************************************************/
|
|
|
4479 /* */
|
|
|
4480 /* Inter-integrated Circuit Interface (I2C) */
|
|
|
4481 /* */
|
|
|
4482 /******************************************************************************/
|
|
|
4483 /******************* Bit definition for I2C_CR1 register *******************/
|
|
|
4484 #define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */
|
|
|
4485 #define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */
|
|
|
4486 #define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */
|
|
|
4487 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */
|
|
|
4488 #define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */
|
|
|
4489 #define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */
|
|
|
4490 #define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */
|
|
|
4491 #define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */
|
|
|
4492 #define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */
|
|
|
4493 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */
|
|
|
4494 #define I2C_CR1_SWRST ((uint32_t)0x00002000U) /*!< Software reset */
|
|
|
4495 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */
|
|
|
4496 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */
|
|
|
4497 #define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */
|
|
|
4498 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */
|
|
|
4499 #define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */
|
|
|
4500 #define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */
|
|
|
4501 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */
|
|
|
4502 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */
|
|
|
4503 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */
|
|
|
4504 #define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */
|
|
|
4505
|
|
|
4506 /****************** Bit definition for I2C_CR2 register ********************/
|
|
|
4507 #define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */
|
|
|
4508 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */
|
|
|
4509 #define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */
|
|
|
4510 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */
|
|
|
4511 #define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */
|
|
|
4512 #define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */
|
|
|
4513 #define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */
|
|
|
4514 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */
|
|
|
4515 #define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */
|
|
|
4516 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */
|
|
|
4517 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */
|
|
|
4518
|
|
|
4519 /******************* Bit definition for I2C_OAR1 register ******************/
|
|
|
4520 #define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */
|
|
|
4521 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */
|
|
|
4522 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */
|
|
|
4523
|
|
|
4524 /******************* Bit definition for I2C_OAR2 register ******************/
|
|
|
4525 #define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */
|
|
|
4526 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */
|
|
|
4527 #define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */
|
|
|
4528 #define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
|
|
4529 #define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
|
|
4530 #define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
|
|
4531 #define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
|
|
4532 #define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
|
|
4533 #define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
|
|
4534 #define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */
|
|
|
4535 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */
|
|
|
4536
|
|
|
4537 /******************* Bit definition for I2C_TIMINGR register *******************/
|
|
|
4538 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */
|
|
|
4539 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */
|
|
|
4540 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */
|
|
|
4541 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */
|
|
|
4542 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */
|
|
|
4543
|
|
|
4544 /******************* Bit definition for I2C_TIMEOUTR register *******************/
|
|
|
4545 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */
|
|
|
4546 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */
|
|
|
4547 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */
|
|
|
4548 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B */
|
|
|
4549 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */
|
|
|
4550
|
|
|
4551 /****************** Bit definition for I2C_ISR register *********************/
|
|
|
4552 #define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */
|
|
|
4553 #define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */
|
|
|
4554 #define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */
|
|
|
4555 #define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode) */
|
|
|
4556 #define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */
|
|
|
4557 #define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */
|
|
|
4558 #define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */
|
|
|
4559 #define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */
|
|
|
4560 #define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */
|
|
|
4561 #define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */
|
|
|
4562 #define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */
|
|
|
4563 #define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */
|
|
|
4564 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */
|
|
|
4565 #define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */
|
|
|
4566 #define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */
|
|
|
4567 #define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */
|
|
|
4568 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */
|
|
|
4569
|
|
|
4570 /****************** Bit definition for I2C_ICR register *********************/
|
|
|
4571 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */
|
|
|
4572 #define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */
|
|
|
4573 #define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */
|
|
|
4574 #define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */
|
|
|
4575 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */
|
|
|
4576 #define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */
|
|
|
4577 #define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */
|
|
|
4578 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */
|
|
|
4579 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */
|
|
|
4580
|
|
|
4581 /****************** Bit definition for I2C_PECR register *********************/
|
|
|
4582 #define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */
|
|
|
4583
|
|
|
4584 /****************** Bit definition for I2C_RXDR register *********************/
|
|
|
4585 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */
|
|
|
4586
|
|
|
4587 /****************** Bit definition for I2C_TXDR register *********************/
|
|
|
4588 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */
|
|
|
4589
|
|
|
4590 /******************************************************************************/
|
|
|
4591 /* */
|
|
|
4592 /* Independent WATCHDOG */
|
|
|
4593 /* */
|
|
|
4594 /******************************************************************************/
|
|
|
4595 /******************* Bit definition for IWDG_KR register ********************/
|
|
|
4596 #define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!<Key value (write only, read 0000h) */
|
|
|
4597
|
|
|
4598 /******************* Bit definition for IWDG_PR register ********************/
|
|
|
4599 #define IWDG_PR_PR ((uint32_t)0x00000007U) /*!<PR[2:0] (Prescaler divider) */
|
|
|
4600 #define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
4601 #define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
4602 #define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
4603
|
|
|
4604 /******************* Bit definition for IWDG_RLR register *******************/
|
|
|
4605 #define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!<Watchdog counter reload value */
|
|
|
4606
|
|
|
4607 /******************* Bit definition for IWDG_SR register ********************/
|
|
|
4608 #define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
|
|
|
4609 #define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
|
|
|
4610 #define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */
|
|
|
4611
|
|
|
4612 /******************* Bit definition for IWDG_KR register ********************/
|
|
|
4613 #define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */
|
|
|
4614
|
|
|
4615 /******************************************************************************/
|
|
|
4616 /* */
|
|
|
4617 /* Firewall */
|
|
|
4618 /* */
|
|
|
4619 /******************************************************************************/
|
|
|
4620
|
|
|
4621 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */
|
|
|
4622 #define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */
|
|
|
4623 #define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */
|
|
|
4624 #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */
|
|
|
4625 #define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */
|
|
|
4626 #define FW_VDSSA_ADD ((uint32_t)0x0001FFC0U) /*!< Volatile Data Segment Start Address */
|
|
|
4627 #define FW_VDSL_LENG ((uint32_t)0x0001FFC0U) /*!< Volatile Data Segment Length */
|
|
|
4628 #define FW_LSSA_ADD ((uint32_t)0x0007FF80U) /*!< Library Segment Start Address*/
|
|
|
4629 #define FW_LSL_LENG ((uint32_t)0x0007FF80U) /*!< Library Segment Length*/
|
|
|
4630
|
|
|
4631 /**************************Bit definition for CR register *********************/
|
|
|
4632 #define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/
|
|
|
4633 #define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/
|
|
|
4634 #define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/
|
|
|
4635
|
|
|
4636 /******************************************************************************/
|
|
|
4637 /* */
|
|
|
4638 /* Power Control */
|
|
|
4639 /* */
|
|
|
4640 /******************************************************************************/
|
|
|
4641
|
|
|
4642 /******************** Bit definition for PWR_CR1 register ********************/
|
|
|
4643
|
|
|
4644 #define PWR_CR1_LPR ((uint32_t)0x00004000U) /*!< Regulator low-power mode */
|
|
|
4645 #define PWR_CR1_VOS ((uint32_t)0x00000600U) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
|
|
|
4646 #define PWR_CR1_VOS_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
|
|
|
4647 #define PWR_CR1_VOS_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
|
|
|
4648 #define PWR_CR1_DBP ((uint32_t)0x00000100U) /*!< Disable Back-up domain Protection */
|
|
|
4649 #define PWR_CR1_LPMS ((uint32_t)0x00000007U) /*!< Low-power mode selection field */
|
|
|
4650 #define PWR_CR1_LPMS_STOP0 ((uint32_t)0x00000000U) /*!< Stop 0 mode */
|
|
|
4651 #define PWR_CR1_LPMS_STOP1 ((uint32_t)0x00000001U) /*!< Stop 1 mode */
|
|
|
4652 #define PWR_CR1_LPMS_STOP2 ((uint32_t)0x00000002U) /*!< Stop 2 mode */
|
|
|
4653 #define PWR_CR1_LPMS_STANDBY ((uint32_t)0x00000003U) /*!< Stand-by mode */
|
|
|
4654 #define PWR_CR1_LPMS_SHUTDOWN ((uint32_t)0x00000004U) /*!< Shut-down mode */
|
|
|
4655
|
|
|
4656
|
|
|
4657 /******************** Bit definition for PWR_CR2 register ********************/
|
|
|
4658 /*!< PVME Peripheral Voltage Monitor Enable */
|
|
|
4659 #define PWR_CR2_PVME ((uint32_t)0x000000C0U) /*!< PVM bits field */
|
|
|
4660 #define PWR_CR2_PVME4 ((uint32_t)0x00000080U) /*!< PVM 4 Enable */
|
|
|
4661 #define PWR_CR2_PVME3 ((uint32_t)0x00000040U) /*!< PVM 3 Enable */
|
|
|
4662 /*!< PVD level configuration */
|
|
|
4663 #define PWR_CR2_PLS ((uint32_t)0x0000000EU) /*!< PVD level selection */
|
|
|
4664 #define PWR_CR2_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
|
|
|
4665 #define PWR_CR2_PLS_LEV1 ((uint32_t)0x00000002U) /*!< PVD level 1 */
|
|
|
4666 #define PWR_CR2_PLS_LEV2 ((uint32_t)0x00000004U) /*!< PVD level 2 */
|
|
|
4667 #define PWR_CR2_PLS_LEV3 ((uint32_t)0x00000006U) /*!< PVD level 3 */
|
|
|
4668 #define PWR_CR2_PLS_LEV4 ((uint32_t)0x00000008U) /*!< PVD level 4 */
|
|
|
4669 #define PWR_CR2_PLS_LEV5 ((uint32_t)0x0000000AU) /*!< PVD level 5 */
|
|
|
4670 #define PWR_CR2_PLS_LEV6 ((uint32_t)0x0000000CU) /*!< PVD level 6 */
|
|
|
4671 #define PWR_CR2_PLS_LEV7 ((uint32_t)0x0000000EU) /*!< PVD level 7 */
|
|
|
4672 #define PWR_CR2_PVDE ((uint32_t)0x00000001U) /*!< Power Voltage Detector Enable */
|
|
|
4673
|
|
|
4674 /******************** Bit definition for PWR_CR3 register ********************/
|
|
|
4675 #define PWR_CR3_EIWF ((uint32_t)0x00008000U) /*!< Enable Internal Wake-up line */
|
|
|
4676 #define PWR_CR3_APC ((uint32_t)0x00000400U) /*!< Apply pull-up and pull-down configuration */
|
|
|
4677 #define PWR_CR3_RRS ((uint32_t)0x00000100U) /*!< SRAM2 Retention in Stand-by mode */
|
|
|
4678 #define PWR_CR3_EWUP5 ((uint32_t)0x00000010U) /*!< Enable Wake-Up Pin 5 */
|
|
|
4679 #define PWR_CR3_EWUP4 ((uint32_t)0x00000008U) /*!< Enable Wake-Up Pin 4 */
|
|
|
4680 #define PWR_CR3_EWUP3 ((uint32_t)0x00000004U) /*!< Enable Wake-Up Pin 3 */
|
|
|
4681 #define PWR_CR3_EWUP2 ((uint32_t)0x00000002U) /*!< Enable Wake-Up Pin 2 */
|
|
|
4682 #define PWR_CR3_EWUP1 ((uint32_t)0x00000001U) /*!< Enable Wake-Up Pin 1 */
|
|
|
4683 #define PWR_CR3_EWUP ((uint32_t)0x0000001FU) /*!< Enable Wake-Up Pins */
|
|
|
4684
|
|
|
4685 /******************** Bit definition for PWR_CR4 register ********************/
|
|
|
4686 #define PWR_CR4_VBRS ((uint32_t)0x00000200U) /*!< VBAT Battery charging Resistor Selection */
|
|
|
4687 #define PWR_CR4_VBE ((uint32_t)0x00000100U) /*!< VBAT Battery charging Enable */
|
|
|
4688 #define PWR_CR4_WP5 ((uint32_t)0x00000010U) /*!< Wake-Up Pin 5 polarity */
|
|
|
4689 #define PWR_CR4_WP4 ((uint32_t)0x00000008U) /*!< Wake-Up Pin 4 polarity */
|
|
|
4690 #define PWR_CR4_WP3 ((uint32_t)0x00000004U) /*!< Wake-Up Pin 3 polarity */
|
|
|
4691 #define PWR_CR4_WP2 ((uint32_t)0x00000002U) /*!< Wake-Up Pin 2 polarity */
|
|
|
4692 #define PWR_CR4_WP1 ((uint32_t)0x00000001U) /*!< Wake-Up Pin 1 polarity */
|
|
|
4693
|
|
|
4694 /******************** Bit definition for PWR_SR1 register ********************/
|
|
|
4695 #define PWR_SR1_WUFI ((uint32_t)0x00008000U) /*!< Wake-Up Flag Internal */
|
|
|
4696 #define PWR_SR1_SBF ((uint32_t)0x00000100U) /*!< Stand-By Flag */
|
|
|
4697 #define PWR_SR1_WUF ((uint32_t)0x0000001FU) /*!< Wake-up Flags */
|
|
|
4698 #define PWR_SR1_WUF5 ((uint32_t)0x00000010U) /*!< Wake-up Flag 5 */
|
|
|
4699 #define PWR_SR1_WUF4 ((uint32_t)0x00000008U) /*!< Wake-up Flag 4 */
|
|
|
4700 #define PWR_SR1_WUF3 ((uint32_t)0x00000004U) /*!< Wake-up Flag 3 */
|
|
|
4701 #define PWR_SR1_WUF2 ((uint32_t)0x00000002U) /*!< Wake-up Flag 2 */
|
|
|
4702 #define PWR_SR1_WUF1 ((uint32_t)0x00000001U) /*!< Wake-up Flag 1 */
|
|
|
4703
|
|
|
4704 /******************** Bit definition for PWR_SR2 register ********************/
|
|
|
4705 #define PWR_SR2_PVMO4 ((uint32_t)0x00008000U) /*!< Peripheral Voltage Monitoring Output 4 */
|
|
|
4706 #define PWR_SR2_PVMO3 ((uint32_t)0x00004000U) /*!< Peripheral Voltage Monitoring Output 3 */
|
|
|
4707 #define PWR_SR2_PVDO ((uint32_t)0x00000800U) /*!< Power Voltage Detector Output */
|
|
|
4708 #define PWR_SR2_VOSF ((uint32_t)0x00000400U) /*!< Voltage Scaling Flag */
|
|
|
4709 #define PWR_SR2_REGLPF ((uint32_t)0x00000200U) /*!< Low-power Regulator Flag */
|
|
|
4710 #define PWR_SR2_REGLPS ((uint32_t)0x00000100U) /*!< Low-power Regulator Started */
|
|
|
4711
|
|
|
4712 /******************** Bit definition for PWR_SCR register ********************/
|
|
|
4713 #define PWR_SCR_CSBF ((uint32_t)0x00000100U) /*!< Clear Stand-By Flag */
|
|
|
4714 #define PWR_SCR_CWUF ((uint32_t)0x0000001FU) /*!< Clear Wake-up Flags */
|
|
|
4715 #define PWR_SCR_CWUF5 ((uint32_t)0x00000010U) /*!< Clear Wake-up Flag 5 */
|
|
|
4716 #define PWR_SCR_CWUF4 ((uint32_t)0x00000008U) /*!< Clear Wake-up Flag 4 */
|
|
|
4717 #define PWR_SCR_CWUF3 ((uint32_t)0x00000004U) /*!< Clear Wake-up Flag 3 */
|
|
|
4718 #define PWR_SCR_CWUF2 ((uint32_t)0x00000002U) /*!< Clear Wake-up Flag 2 */
|
|
|
4719 #define PWR_SCR_CWUF1 ((uint32_t)0x00000001U) /*!< Clear Wake-up Flag 1 */
|
|
|
4720
|
|
|
4721 /******************** Bit definition for PWR_PUCRA register ********************/
|
|
|
4722 #define PWR_PUCRA_PA15 ((uint32_t)0x00008000U) /*!< Port PA15 Pull-Up set */
|
|
|
4723 #define PWR_PUCRA_PA13 ((uint32_t)0x00002000U) /*!< Port PA13 Pull-Up set */
|
|
|
4724 #define PWR_PUCRA_PA12 ((uint32_t)0x00001000U) /*!< Port PA12 Pull-Up set */
|
|
|
4725 #define PWR_PUCRA_PA11 ((uint32_t)0x00000800U) /*!< Port PA11 Pull-Up set */
|
|
|
4726 #define PWR_PUCRA_PA10 ((uint32_t)0x00000400U) /*!< Port PA10 Pull-Up set */
|
|
|
4727 #define PWR_PUCRA_PA9 ((uint32_t)0x00000200U) /*!< Port PA9 Pull-Up set */
|
|
|
4728 #define PWR_PUCRA_PA8 ((uint32_t)0x00000100U) /*!< Port PA8 Pull-Up set */
|
|
|
4729 #define PWR_PUCRA_PA7 ((uint32_t)0x00000080U) /*!< Port PA7 Pull-Up set */
|
|
|
4730 #define PWR_PUCRA_PA6 ((uint32_t)0x00000040U) /*!< Port PA6 Pull-Up set */
|
|
|
4731 #define PWR_PUCRA_PA5 ((uint32_t)0x00000020U) /*!< Port PA5 Pull-Up set */
|
|
|
4732 #define PWR_PUCRA_PA4 ((uint32_t)0x00000010U) /*!< Port PA4 Pull-Up set */
|
|
|
4733 #define PWR_PUCRA_PA3 ((uint32_t)0x00000008U) /*!< Port PA3 Pull-Up set */
|
|
|
4734 #define PWR_PUCRA_PA2 ((uint32_t)0x00000004U) /*!< Port PA2 Pull-Up set */
|
|
|
4735 #define PWR_PUCRA_PA1 ((uint32_t)0x00000002U) /*!< Port PA1 Pull-Up set */
|
|
|
4736 #define PWR_PUCRA_PA0 ((uint32_t)0x00000001U) /*!< Port PA0 Pull-Up set */
|
|
|
4737
|
|
|
4738 /******************** Bit definition for PWR_PDCRA register ********************/
|
|
|
4739 #define PWR_PDCRA_PA14 ((uint32_t)0x00004000U) /*!< Port PA14 Pull-Down set */
|
|
|
4740 #define PWR_PDCRA_PA12 ((uint32_t)0x00001000U) /*!< Port PA12 Pull-Down set */
|
|
|
4741 #define PWR_PDCRA_PA11 ((uint32_t)0x00000800U) /*!< Port PA11 Pull-Down set */
|
|
|
4742 #define PWR_PDCRA_PA10 ((uint32_t)0x00000400U) /*!< Port PA10 Pull-Down set */
|
|
|
4743 #define PWR_PDCRA_PA9 ((uint32_t)0x00000200U) /*!< Port PA9 Pull-Down set */
|
|
|
4744 #define PWR_PDCRA_PA8 ((uint32_t)0x00000100U) /*!< Port PA8 Pull-Down set */
|
|
|
4745 #define PWR_PDCRA_PA7 ((uint32_t)0x00000080U) /*!< Port PA7 Pull-Down set */
|
|
|
4746 #define PWR_PDCRA_PA6 ((uint32_t)0x00000040U) /*!< Port PA6 Pull-Down set */
|
|
|
4747 #define PWR_PDCRA_PA5 ((uint32_t)0x00000020U) /*!< Port PA5 Pull-Down set */
|
|
|
4748 #define PWR_PDCRA_PA4 ((uint32_t)0x00000010U) /*!< Port PA4 Pull-Down set */
|
|
|
4749 #define PWR_PDCRA_PA3 ((uint32_t)0x00000008U) /*!< Port PA3 Pull-Down set */
|
|
|
4750 #define PWR_PDCRA_PA2 ((uint32_t)0x00000004U) /*!< Port PA2 Pull-Down set */
|
|
|
4751 #define PWR_PDCRA_PA1 ((uint32_t)0x00000002U) /*!< Port PA1 Pull-Down set */
|
|
|
4752 #define PWR_PDCRA_PA0 ((uint32_t)0x00000001U) /*!< Port PA0 Pull-Down set */
|
|
|
4753
|
|
|
4754 /******************** Bit definition for PWR_PUCRB register ********************/
|
|
|
4755 #define PWR_PUCRB_PB15 ((uint32_t)0x00008000U) /*!< Port PB15 Pull-Up set */
|
|
|
4756 #define PWR_PUCRB_PB14 ((uint32_t)0x00004000U) /*!< Port PB14 Pull-Up set */
|
|
|
4757 #define PWR_PUCRB_PB13 ((uint32_t)0x00002000U) /*!< Port PB13 Pull-Up set */
|
|
|
4758 #define PWR_PUCRB_PB12 ((uint32_t)0x00001000U) /*!< Port PB12 Pull-Up set */
|
|
|
4759 #define PWR_PUCRB_PB11 ((uint32_t)0x00000800U) /*!< Port PB11 Pull-Up set */
|
|
|
4760 #define PWR_PUCRB_PB10 ((uint32_t)0x00000400U) /*!< Port PB10 Pull-Up set */
|
|
|
4761 #define PWR_PUCRB_PB9 ((uint32_t)0x00000200U) /*!< Port PB9 Pull-Up set */
|
|
|
4762 #define PWR_PUCRB_PB8 ((uint32_t)0x00000100U) /*!< Port PB8 Pull-Up set */
|
|
|
4763 #define PWR_PUCRB_PB7 ((uint32_t)0x00000080U) /*!< Port PB7 Pull-Up set */
|
|
|
4764 #define PWR_PUCRB_PB6 ((uint32_t)0x00000040U) /*!< Port PB6 Pull-Up set */
|
|
|
4765 #define PWR_PUCRB_PB5 ((uint32_t)0x00000020U) /*!< Port PB5 Pull-Up set */
|
|
|
4766 #define PWR_PUCRB_PB4 ((uint32_t)0x00000010U) /*!< Port PB4 Pull-Up set */
|
|
|
4767 #define PWR_PUCRB_PB3 ((uint32_t)0x00000008U) /*!< Port PB3 Pull-Up set */
|
|
|
4768 #define PWR_PUCRB_PB2 ((uint32_t)0x00000004U) /*!< Port PB2 Pull-Up set */
|
|
|
4769 #define PWR_PUCRB_PB1 ((uint32_t)0x00000002U) /*!< Port PB1 Pull-Up set */
|
|
|
4770 #define PWR_PUCRB_PB0 ((uint32_t)0x00000001U) /*!< Port PB0 Pull-Up set */
|
|
|
4771
|
|
|
4772 /******************** Bit definition for PWR_PDCRB register ********************/
|
|
|
4773 #define PWR_PDCRB_PB15 ((uint32_t)0x00008000U) /*!< Port PB15 Pull-Down set */
|
|
|
4774 #define PWR_PDCRB_PB14 ((uint32_t)0x00004000U) /*!< Port PB14 Pull-Down set */
|
|
|
4775 #define PWR_PDCRB_PB13 ((uint32_t)0x00002000U) /*!< Port PB13 Pull-Down set */
|
|
|
4776 #define PWR_PDCRB_PB12 ((uint32_t)0x00001000U) /*!< Port PB12 Pull-Down set */
|
|
|
4777 #define PWR_PDCRB_PB11 ((uint32_t)0x00000800U) /*!< Port PB11 Pull-Down set */
|
|
|
4778 #define PWR_PDCRB_PB10 ((uint32_t)0x00000400U) /*!< Port PB10 Pull-Down set */
|
|
|
4779 #define PWR_PDCRB_PB9 ((uint32_t)0x00000200U) /*!< Port PB9 Pull-Down set */
|
|
|
4780 #define PWR_PDCRB_PB8 ((uint32_t)0x00000100U) /*!< Port PB8 Pull-Down set */
|
|
|
4781 #define PWR_PDCRB_PB7 ((uint32_t)0x00000080U) /*!< Port PB7 Pull-Down set */
|
|
|
4782 #define PWR_PDCRB_PB6 ((uint32_t)0x00000040U) /*!< Port PB6 Pull-Down set */
|
|
|
4783 #define PWR_PDCRB_PB5 ((uint32_t)0x00000020U) /*!< Port PB5 Pull-Down set */
|
|
|
4784 #define PWR_PDCRB_PB3 ((uint32_t)0x00000008U) /*!< Port PB3 Pull-Down set */
|
|
|
4785 #define PWR_PDCRB_PB2 ((uint32_t)0x00000004U) /*!< Port PB2 Pull-Down set */
|
|
|
4786 #define PWR_PDCRB_PB1 ((uint32_t)0x00000002U) /*!< Port PB1 Pull-Down set */
|
|
|
4787 #define PWR_PDCRB_PB0 ((uint32_t)0x00000001U) /*!< Port PB0 Pull-Down set */
|
|
|
4788
|
|
|
4789 /******************** Bit definition for PWR_PUCRC register ********************/
|
|
|
4790 #define PWR_PUCRC_PC15 ((uint32_t)0x00008000U) /*!< Port PC15 Pull-Up set */
|
|
|
4791 #define PWR_PUCRC_PC14 ((uint32_t)0x00004000U) /*!< Port PC14 Pull-Up set */
|
|
|
4792 #define PWR_PUCRC_PC13 ((uint32_t)0x00002000U) /*!< Port PC13 Pull-Up set */
|
|
|
4793 #define PWR_PUCRC_PC12 ((uint32_t)0x00001000U) /*!< Port PC12 Pull-Up set */
|
|
|
4794 #define PWR_PUCRC_PC11 ((uint32_t)0x00000800U) /*!< Port PC11 Pull-Up set */
|
|
|
4795 #define PWR_PUCRC_PC10 ((uint32_t)0x00000400U) /*!< Port PC10 Pull-Up set */
|
|
|
4796 #define PWR_PUCRC_PC9 ((uint32_t)0x00000200U) /*!< Port PC9 Pull-Up set */
|
|
|
4797 #define PWR_PUCRC_PC8 ((uint32_t)0x00000100U) /*!< Port PC8 Pull-Up set */
|
|
|
4798 #define PWR_PUCRC_PC7 ((uint32_t)0x00000080U) /*!< Port PC7 Pull-Up set */
|
|
|
4799 #define PWR_PUCRC_PC6 ((uint32_t)0x00000040U) /*!< Port PC6 Pull-Up set */
|
|
|
4800 #define PWR_PUCRC_PC5 ((uint32_t)0x00000020U) /*!< Port PC5 Pull-Up set */
|
|
|
4801 #define PWR_PUCRC_PC4 ((uint32_t)0x00000010U) /*!< Port PC4 Pull-Up set */
|
|
|
4802 #define PWR_PUCRC_PC3 ((uint32_t)0x00000008U) /*!< Port PC3 Pull-Up set */
|
|
|
4803 #define PWR_PUCRC_PC2 ((uint32_t)0x00000004U) /*!< Port PC2 Pull-Up set */
|
|
|
4804 #define PWR_PUCRC_PC1 ((uint32_t)0x00000002U) /*!< Port PC1 Pull-Up set */
|
|
|
4805 #define PWR_PUCRC_PC0 ((uint32_t)0x00000001U) /*!< Port PC0 Pull-Up set */
|
|
|
4806
|
|
|
4807 /******************** Bit definition for PWR_PDCRC register ********************/
|
|
|
4808 #define PWR_PDCRC_PC15 ((uint32_t)0x00008000U) /*!< Port PC15 Pull-Down set */
|
|
|
4809 #define PWR_PDCRC_PC14 ((uint32_t)0x00004000U) /*!< Port PC14 Pull-Down set */
|
|
|
4810 #define PWR_PDCRC_PC13 ((uint32_t)0x00002000U) /*!< Port PC13 Pull-Down set */
|
|
|
4811 #define PWR_PDCRC_PC12 ((uint32_t)0x00001000U) /*!< Port PC12 Pull-Down set */
|
|
|
4812 #define PWR_PDCRC_PC11 ((uint32_t)0x00000800U) /*!< Port PC11 Pull-Down set */
|
|
|
4813 #define PWR_PDCRC_PC10 ((uint32_t)0x00000400U) /*!< Port PC10 Pull-Down set */
|
|
|
4814 #define PWR_PDCRC_PC9 ((uint32_t)0x00000200U) /*!< Port PC9 Pull-Down set */
|
|
|
4815 #define PWR_PDCRC_PC8 ((uint32_t)0x00000100U) /*!< Port PC8 Pull-Down set */
|
|
|
4816 #define PWR_PDCRC_PC7 ((uint32_t)0x00000080U) /*!< Port PC7 Pull-Down set */
|
|
|
4817 #define PWR_PDCRC_PC6 ((uint32_t)0x00000040U) /*!< Port PC6 Pull-Down set */
|
|
|
4818 #define PWR_PDCRC_PC5 ((uint32_t)0x00000020U) /*!< Port PC5 Pull-Down set */
|
|
|
4819 #define PWR_PDCRC_PC4 ((uint32_t)0x00000010U) /*!< Port PC4 Pull-Down set */
|
|
|
4820 #define PWR_PDCRC_PC3 ((uint32_t)0x00000008U) /*!< Port PC3 Pull-Down set */
|
|
|
4821 #define PWR_PDCRC_PC2 ((uint32_t)0x00000004U) /*!< Port PC2 Pull-Down set */
|
|
|
4822 #define PWR_PDCRC_PC1 ((uint32_t)0x00000002U) /*!< Port PC1 Pull-Down set */
|
|
|
4823 #define PWR_PDCRC_PC0 ((uint32_t)0x00000001U) /*!< Port PC0 Pull-Down set */
|
|
|
4824
|
|
|
4825 /******************** Bit definition for PWR_PUCRD register ********************/
|
|
|
4826 #define PWR_PUCRD_PD15 ((uint32_t)0x00008000U) /*!< Port PD15 Pull-Up set */
|
|
|
4827 #define PWR_PUCRD_PD14 ((uint32_t)0x00004000U) /*!< Port PD14 Pull-Up set */
|
|
|
4828 #define PWR_PUCRD_PD13 ((uint32_t)0x00002000U) /*!< Port PD13 Pull-Up set */
|
|
|
4829 #define PWR_PUCRD_PD12 ((uint32_t)0x00001000U) /*!< Port PD12 Pull-Up set */
|
|
|
4830 #define PWR_PUCRD_PD11 ((uint32_t)0x00000800U) /*!< Port PD11 Pull-Up set */
|
|
|
4831 #define PWR_PUCRD_PD10 ((uint32_t)0x00000400U) /*!< Port PD10 Pull-Up set */
|
|
|
4832 #define PWR_PUCRD_PD9 ((uint32_t)0x00000200U) /*!< Port PD9 Pull-Up set */
|
|
|
4833 #define PWR_PUCRD_PD8 ((uint32_t)0x00000100U) /*!< Port PD8 Pull-Up set */
|
|
|
4834 #define PWR_PUCRD_PD7 ((uint32_t)0x00000080U) /*!< Port PD7 Pull-Up set */
|
|
|
4835 #define PWR_PUCRD_PD6 ((uint32_t)0x00000040U) /*!< Port PD6 Pull-Up set */
|
|
|
4836 #define PWR_PUCRD_PD5 ((uint32_t)0x00000020U) /*!< Port PD5 Pull-Up set */
|
|
|
4837 #define PWR_PUCRD_PD4 ((uint32_t)0x00000010U) /*!< Port PD4 Pull-Up set */
|
|
|
4838 #define PWR_PUCRD_PD3 ((uint32_t)0x00000008U) /*!< Port PD3 Pull-Up set */
|
|
|
4839 #define PWR_PUCRD_PD2 ((uint32_t)0x00000004U) /*!< Port PD2 Pull-Up set */
|
|
|
4840 #define PWR_PUCRD_PD1 ((uint32_t)0x00000002U) /*!< Port PD1 Pull-Up set */
|
|
|
4841 #define PWR_PUCRD_PD0 ((uint32_t)0x00000001U) /*!< Port PD0 Pull-Up set */
|
|
|
4842
|
|
|
4843 /******************** Bit definition for PWR_PDCRD register ********************/
|
|
|
4844 #define PWR_PDCRD_PD15 ((uint32_t)0x00008000U) /*!< Port PD15 Pull-Down set */
|
|
|
4845 #define PWR_PDCRD_PD14 ((uint32_t)0x00004000U) /*!< Port PD14 Pull-Down set */
|
|
|
4846 #define PWR_PDCRD_PD13 ((uint32_t)0x00002000U) /*!< Port PD13 Pull-Down set */
|
|
|
4847 #define PWR_PDCRD_PD12 ((uint32_t)0x00001000U) /*!< Port PD12 Pull-Down set */
|
|
|
4848 #define PWR_PDCRD_PD11 ((uint32_t)0x00000800U) /*!< Port PD11 Pull-Down set */
|
|
|
4849 #define PWR_PDCRD_PD10 ((uint32_t)0x00000400U) /*!< Port PD10 Pull-Down set */
|
|
|
4850 #define PWR_PDCRD_PD9 ((uint32_t)0x00000200U) /*!< Port PD9 Pull-Down set */
|
|
|
4851 #define PWR_PDCRD_PD8 ((uint32_t)0x00000100U) /*!< Port PD8 Pull-Down set */
|
|
|
4852 #define PWR_PDCRD_PD7 ((uint32_t)0x00000080U) /*!< Port PD7 Pull-Down set */
|
|
|
4853 #define PWR_PDCRD_PD6 ((uint32_t)0x00000040U) /*!< Port PD6 Pull-Down set */
|
|
|
4854 #define PWR_PDCRD_PD5 ((uint32_t)0x00000020U) /*!< Port PD5 Pull-Down set */
|
|
|
4855 #define PWR_PDCRD_PD4 ((uint32_t)0x00000010U) /*!< Port PD4 Pull-Down set */
|
|
|
4856 #define PWR_PDCRD_PD3 ((uint32_t)0x00000008U) /*!< Port PD3 Pull-Down set */
|
|
|
4857 #define PWR_PDCRD_PD2 ((uint32_t)0x00000004U) /*!< Port PD2 Pull-Down set */
|
|
|
4858 #define PWR_PDCRD_PD1 ((uint32_t)0x00000002U) /*!< Port PD1 Pull-Down set */
|
|
|
4859 #define PWR_PDCRD_PD0 ((uint32_t)0x00000001U) /*!< Port PD0 Pull-Down set */
|
|
|
4860
|
|
|
4861 /******************** Bit definition for PWR_PUCRE register ********************/
|
|
|
4862 #define PWR_PUCRE_PE15 ((uint32_t)0x00008000U) /*!< Port PE15 Pull-Up set */
|
|
|
4863 #define PWR_PUCRE_PE14 ((uint32_t)0x00004000U) /*!< Port PE14 Pull-Up set */
|
|
|
4864 #define PWR_PUCRE_PE13 ((uint32_t)0x00002000U) /*!< Port PE13 Pull-Up set */
|
|
|
4865 #define PWR_PUCRE_PE12 ((uint32_t)0x00001000U) /*!< Port PE12 Pull-Up set */
|
|
|
4866 #define PWR_PUCRE_PE11 ((uint32_t)0x00000800U) /*!< Port PE11 Pull-Up set */
|
|
|
4867 #define PWR_PUCRE_PE10 ((uint32_t)0x00000400U) /*!< Port PE10 Pull-Up set */
|
|
|
4868 #define PWR_PUCRE_PE9 ((uint32_t)0x00000200U) /*!< Port PE9 Pull-Up set */
|
|
|
4869 #define PWR_PUCRE_PE8 ((uint32_t)0x00000100U) /*!< Port PE8 Pull-Up set */
|
|
|
4870 #define PWR_PUCRE_PE7 ((uint32_t)0x00000080U) /*!< Port PE7 Pull-Up set */
|
|
|
4871 #define PWR_PUCRE_PE6 ((uint32_t)0x00000040U) /*!< Port PE6 Pull-Up set */
|
|
|
4872 #define PWR_PUCRE_PE5 ((uint32_t)0x00000020U) /*!< Port PE5 Pull-Up set */
|
|
|
4873 #define PWR_PUCRE_PE4 ((uint32_t)0x00000010U) /*!< Port PE4 Pull-Up set */
|
|
|
4874 #define PWR_PUCRE_PE3 ((uint32_t)0x00000008U) /*!< Port PE3 Pull-Up set */
|
|
|
4875 #define PWR_PUCRE_PE2 ((uint32_t)0x00000004U) /*!< Port PE2 Pull-Up set */
|
|
|
4876 #define PWR_PUCRE_PE1 ((uint32_t)0x00000002U) /*!< Port PE1 Pull-Up set */
|
|
|
4877 #define PWR_PUCRE_PE0 ((uint32_t)0x00000001U) /*!< Port PE0 Pull-Up set */
|
|
|
4878
|
|
|
4879 /******************** Bit definition for PWR_PDCRE register ********************/
|
|
|
4880 #define PWR_PDCRE_PE15 ((uint32_t)0x00008000U) /*!< Port PE15 Pull-Down set */
|
|
|
4881 #define PWR_PDCRE_PE14 ((uint32_t)0x00004000U) /*!< Port PE14 Pull-Down set */
|
|
|
4882 #define PWR_PDCRE_PE13 ((uint32_t)0x00002000U) /*!< Port PE13 Pull-Down set */
|
|
|
4883 #define PWR_PDCRE_PE12 ((uint32_t)0x00001000U) /*!< Port PE12 Pull-Down set */
|
|
|
4884 #define PWR_PDCRE_PE11 ((uint32_t)0x00000800U) /*!< Port PE11 Pull-Down set */
|
|
|
4885 #define PWR_PDCRE_PE10 ((uint32_t)0x00000400U) /*!< Port PE10 Pull-Down set */
|
|
|
4886 #define PWR_PDCRE_PE9 ((uint32_t)0x00000200U) /*!< Port PE9 Pull-Down set */
|
|
|
4887 #define PWR_PDCRE_PE8 ((uint32_t)0x00000100U) /*!< Port PE8 Pull-Down set */
|
|
|
4888 #define PWR_PDCRE_PE7 ((uint32_t)0x00000080U) /*!< Port PE7 Pull-Down set */
|
|
|
4889 #define PWR_PDCRE_PE6 ((uint32_t)0x00000040U) /*!< Port PE6 Pull-Down set */
|
|
|
4890 #define PWR_PDCRE_PE5 ((uint32_t)0x00000020U) /*!< Port PE5 Pull-Down set */
|
|
|
4891 #define PWR_PDCRE_PE4 ((uint32_t)0x00000010U) /*!< Port PE4 Pull-Down set */
|
|
|
4892 #define PWR_PDCRE_PE3 ((uint32_t)0x00000008U) /*!< Port PE3 Pull-Down set */
|
|
|
4893 #define PWR_PDCRE_PE2 ((uint32_t)0x00000004U) /*!< Port PE2 Pull-Down set */
|
|
|
4894 #define PWR_PDCRE_PE1 ((uint32_t)0x00000002U) /*!< Port PE1 Pull-Down set */
|
|
|
4895 #define PWR_PDCRE_PE0 ((uint32_t)0x00000001U) /*!< Port PE0 Pull-Down set */
|
|
|
4896
|
|
|
4897
|
|
|
4898 /******************** Bit definition for PWR_PUCRH register ********************/
|
|
|
4899 #define PWR_PUCRH_PH3 ((uint32_t)0x00000008U) /*!< Port PH3 Pull-Down set */
|
|
|
4900 #define PWR_PUCRH_PH1 ((uint32_t)0x00000002U) /*!< Port PH1 Pull-Up set */
|
|
|
4901 #define PWR_PUCRH_PH0 ((uint32_t)0x00000001U) /*!< Port PH0 Pull-Up set */
|
|
|
4902
|
|
|
4903 /******************** Bit definition for PWR_PDCRH register ********************/
|
|
|
4904 #define PWR_PDCRH_PH3 ((uint32_t)0x00000008U) /*!< Port PH3 Pull-Down set */
|
|
|
4905 #define PWR_PDCRH_PH1 ((uint32_t)0x00000002U) /*!< Port PH1 Pull-Down set */
|
|
|
4906 #define PWR_PDCRH_PH0 ((uint32_t)0x00000001U) /*!< Port PH0 Pull-Down set */
|
|
|
4907
|
|
|
4908
|
|
|
4909 /******************************************************************************/
|
|
|
4910 /* */
|
|
|
4911 /* Reset and Clock Control */
|
|
|
4912 /* */
|
|
|
4913 /******************************************************************************/
|
|
|
4914 /*
|
|
|
4915 * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
|
|
|
4916 */
|
|
|
4917 #define RCC_HSI48_SUPPORT
|
|
|
4918 #define RCC_PLLP_DIV_2_31_SUPPORT
|
|
|
4919 #define RCC_PLLSAI1P_DIV_2_31_SUPPORT
|
|
|
4920
|
|
|
4921 /******************** Bit definition for RCC_CR register ********************/
|
|
|
4922 #define RCC_CR_MSION ((uint32_t)0x00000001U) /*!< Internal Multi Speed oscillator (MSI) clock enable */
|
|
|
4923 #define RCC_CR_MSIRDY ((uint32_t)0x00000002U) /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
|
|
|
4924 #define RCC_CR_MSIPLLEN ((uint32_t)0x00000004U) /*!< Internal Multi Speed oscillator (MSI) PLL enable */
|
|
|
4925 #define RCC_CR_MSIRGSEL ((uint32_t)0x00000008U) /*!< Internal Multi Speed oscillator (MSI) range selection */
|
|
|
4926
|
|
|
4927 /*!< MSIRANGE configuration : 12 frequency ranges available */
|
|
|
4928 #define RCC_CR_MSIRANGE ((uint32_t)0x000000F0U) /*!< Internal Multi Speed oscillator (MSI) clock Range */
|
|
|
4929 #define RCC_CR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed oscillator (MSI) clock Range 100 KHz */
|
|
|
4930 #define RCC_CR_MSIRANGE_1 ((uint32_t)0x00000010U) /*!< Internal Multi Speed oscillator (MSI) clock Range 200 KHz */
|
|
|
4931 #define RCC_CR_MSIRANGE_2 ((uint32_t)0x00000020U) /*!< Internal Multi Speed oscillator (MSI) clock Range 400 KHz */
|
|
|
4932 #define RCC_CR_MSIRANGE_3 ((uint32_t)0x00000030U) /*!< Internal Multi Speed oscillator (MSI) clock Range 800 KHz */
|
|
|
4933 #define RCC_CR_MSIRANGE_4 ((uint32_t)0x00000040U) /*!< Internal Multi Speed oscillator (MSI) clock Range 1 MHz */
|
|
|
4934 #define RCC_CR_MSIRANGE_5 ((uint32_t)0x00000050U) /*!< Internal Multi Speed oscillator (MSI) clock Range 2 MHz */
|
|
|
4935 #define RCC_CR_MSIRANGE_6 ((uint32_t)0x00000060U) /*!< Internal Multi Speed oscillator (MSI) clock Range 4 MHz */
|
|
|
4936 #define RCC_CR_MSIRANGE_7 ((uint32_t)0x00000070U) /*!< Internal Multi Speed oscillator (MSI) clock Range 8 KHz */
|
|
|
4937 #define RCC_CR_MSIRANGE_8 ((uint32_t)0x00000080U) /*!< Internal Multi Speed oscillator (MSI) clock Range 16 MHz */
|
|
|
4938 #define RCC_CR_MSIRANGE_9 ((uint32_t)0x00000090U) /*!< Internal Multi Speed oscillator (MSI) clock Range 24 MHz */
|
|
|
4939 #define RCC_CR_MSIRANGE_10 ((uint32_t)0x000000A0U) /*!< Internal Multi Speed oscillator (MSI) clock Range 32 MHz */
|
|
|
4940 #define RCC_CR_MSIRANGE_11 ((uint32_t)0x000000B0U) /*!< Internal Multi Speed oscillator (MSI) clock Range 48 MHz */
|
|
|
4941
|
|
|
4942 #define RCC_CR_HSION ((uint32_t)0x00000100U) /*!< Internal High Speed oscillator (HSI16) clock enable */
|
|
|
4943 #define RCC_CR_HSIKERON ((uint32_t)0x00000200U) /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
|
|
|
4944 #define RCC_CR_HSIRDY ((uint32_t)0x00000400U) /*!< Internal High Speed oscillator (HSI16) clock ready flag */
|
|
|
4945 #define RCC_CR_HSIASFS ((uint32_t)0x00000800U) /*!< HSI16 Automatic Start from Stop */
|
|
|
4946
|
|
|
4947 #define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed oscillator (HSE) clock enable */
|
|
|
4948 #define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed oscillator (HSE) clock ready */
|
|
|
4949 #define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed oscillator (HSE) clock bypass */
|
|
|
4950 #define RCC_CR_CSSON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */
|
|
|
4951
|
|
|
4952 #define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< System PLL clock enable */
|
|
|
4953 #define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< System PLL clock ready */
|
|
|
4954 #define RCC_CR_PLLSAI1ON ((uint32_t)0x04000000U) /*!< SAI1 PLL enable */
|
|
|
4955 #define RCC_CR_PLLSAI1RDY ((uint32_t)0x08000000U) /*!< SAI1 PLL ready */
|
|
|
4956
|
|
|
4957 /******************** Bit definition for RCC_ICSCR register ***************/
|
|
|
4958 /*!< MSICAL configuration */
|
|
|
4959 #define RCC_ICSCR_MSICAL ((uint32_t)0x000000FFU) /*!< MSICAL[7:0] bits */
|
|
|
4960 #define RCC_ICSCR_MSICAL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
4961 #define RCC_ICSCR_MSICAL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
4962 #define RCC_ICSCR_MSICAL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
4963 #define RCC_ICSCR_MSICAL_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
4964 #define RCC_ICSCR_MSICAL_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
4965 #define RCC_ICSCR_MSICAL_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
4966 #define RCC_ICSCR_MSICAL_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
4967 #define RCC_ICSCR_MSICAL_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
|
|
|
4968
|
|
|
4969 /*!< MSITRIM configuration */
|
|
|
4970 #define RCC_ICSCR_MSITRIM ((uint32_t)0x0000FF00U) /*!< MSITRIM[7:0] bits */
|
|
|
4971 #define RCC_ICSCR_MSITRIM_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
4972 #define RCC_ICSCR_MSITRIM_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
4973 #define RCC_ICSCR_MSITRIM_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
4974 #define RCC_ICSCR_MSITRIM_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
4975 #define RCC_ICSCR_MSITRIM_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
4976 #define RCC_ICSCR_MSITRIM_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
|
|
|
4977 #define RCC_ICSCR_MSITRIM_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
|
|
|
4978 #define RCC_ICSCR_MSITRIM_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
|
|
|
4979
|
|
|
4980 /*!< HSICAL configuration */
|
|
|
4981 #define RCC_ICSCR_HSICAL ((uint32_t)0x00FF0000U) /*!< HSICAL[7:0] bits */
|
|
|
4982 #define RCC_ICSCR_HSICAL_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
4983 #define RCC_ICSCR_HSICAL_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
4984 #define RCC_ICSCR_HSICAL_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
4985 #define RCC_ICSCR_HSICAL_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
|
|
|
4986 #define RCC_ICSCR_HSICAL_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
|
|
|
4987 #define RCC_ICSCR_HSICAL_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
|
|
|
4988 #define RCC_ICSCR_HSICAL_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
|
|
|
4989 #define RCC_ICSCR_HSICAL_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
|
|
|
4990
|
|
|
4991 /*!< HSITRIM configuration */
|
|
|
4992 #define RCC_ICSCR_HSITRIM ((uint32_t)0x1F000000U) /*!< HSITRIM[4:0] bits */
|
|
|
4993 #define RCC_ICSCR_HSITRIM_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
4994 #define RCC_ICSCR_HSITRIM_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
4995 #define RCC_ICSCR_HSITRIM_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
4996 #define RCC_ICSCR_HSITRIM_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
4997 #define RCC_ICSCR_HSITRIM_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
|
|
|
4998
|
|
|
4999 /******************** Bit definition for RCC_CFGR register ******************/
|
|
|
5000 /*!< SW configuration */
|
|
|
5001 #define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
|
|
|
5002 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
5003 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
5004
|
|
|
5005 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator selection as system clock */
|
|
|
5006 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI16 oscillator selection as system clock */
|
|
|
5007 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE oscillator selection as system clock */
|
|
|
5008 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selection as system clock */
|
|
|
5009
|
|
|
5010 /*!< SWS configuration */
|
|
|
5011 #define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
|
|
|
5012 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
5013 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
5014
|
|
|
5015 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
|
|
|
5016 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI16 oscillator used as system clock */
|
|
|
5017 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
|
|
|
5018 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
|
|
|
5019
|
|
|
5020 /*!< HPRE configuration */
|
|
|
5021 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
|
|
|
5022 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
5023 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
5024 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
5025 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
|
|
|
5026
|
|
|
5027 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
|
|
|
5028 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
|
|
|
5029 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
|
|
|
5030 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
|
|
|
5031 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
|
|
|
5032 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
|
|
|
5033 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
|
|
|
5034 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
|
|
|
5035 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
|
|
|
5036
|
|
|
5037 /*!< PPRE1 configuration */
|
|
|
5038 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB2 prescaler) */
|
|
|
5039 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
5040 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
5041 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
5042
|
|
|
5043 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
|
|
|
5044 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
|
|
|
5045 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
|
|
|
5046 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
|
|
|
5047 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
|
|
|
5048
|
|
|
5049 /*!< PPRE2 configuration */
|
|
|
5050 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
|
|
|
5051 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!<Bit 0 */
|
|
|
5052 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!<Bit 1 */
|
|
|
5053 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!<Bit 2 */
|
|
|
5054
|
|
|
5055 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
|
|
|
5056 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
|
|
|
5057 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
|
|
|
5058 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
|
|
|
5059 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
|
|
|
5060
|
|
|
5061 #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from stop and CSS backup clock selection */
|
|
|
5062
|
|
|
5063 /*!< MCOSEL configuration */
|
|
|
5064 #define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCOSEL [3:0] bits (Clock output selection) */
|
|
|
5065 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
5066 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
5067 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
5068 #define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
5069
|
|
|
5070 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */
|
|
|
5071 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
|
|
|
5072 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
|
|
|
5073 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
|
|
|
5074
|
|
|
5075 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
|
|
|
5076 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
|
|
|
5077 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
|
|
|
5078 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
|
|
|
5079 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
|
|
|
5080
|
|
|
5081 /* Legacy aliases */
|
|
|
5082 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
|
|
|
5083 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
|
|
|
5084 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
|
|
|
5085 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
|
|
|
5086 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
|
|
|
5087 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
|
|
|
5088
|
|
|
5089 /******************** Bit definition for RCC_PLLCFGR register ***************/
|
|
|
5090 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00000003U)
|
|
|
5091
|
|
|
5092 #define RCC_PLLCFGR_PLLSRC_MSI ((uint32_t)0x00000001U) /*!< MSI oscillator source clock selected */
|
|
|
5093 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000002U) /*!< HSI16 oscillator source clock selected */
|
|
|
5094 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00000003U) /*!< HSE oscillator source clock selected */
|
|
|
5095
|
|
|
5096 #define RCC_PLLCFGR_PLLM ((uint32_t)0x00000070U)
|
|
|
5097 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000010U)
|
|
|
5098 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000020U)
|
|
|
5099 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000040U)
|
|
|
5100
|
|
|
5101 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007F00U)
|
|
|
5102 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000100U)
|
|
|
5103 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000200U)
|
|
|
5104 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000400U)
|
|
|
5105 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000800U)
|
|
|
5106 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00001000U)
|
|
|
5107 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00002000U)
|
|
|
5108 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00004000U)
|
|
|
5109
|
|
|
5110 #define RCC_PLLCFGR_PLLPEN ((uint32_t)0x00010000U)
|
|
|
5111 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00020000U)
|
|
|
5112 #define RCC_PLLCFGR_PLLQEN ((uint32_t)0x00100000U)
|
|
|
5113
|
|
|
5114 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x00600000U)
|
|
|
5115 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x00200000U)
|
|
|
5116 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x00400000U)
|
|
|
5117
|
|
|
5118 #define RCC_PLLCFGR_PLLREN ((uint32_t)0x01000000U)
|
|
|
5119 #define RCC_PLLCFGR_PLLR ((uint32_t)0x06000000U)
|
|
|
5120 #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x02000000U)
|
|
|
5121 #define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x04000000U)
|
|
|
5122
|
|
|
5123 #define RCC_PLLCFGR_PLLPDIV ((uint32_t)0xF8000000U)
|
|
|
5124 #define RCC_PLLCFGR_PLLPDIV_0 ((uint32_t)0x08000000U)
|
|
|
5125 #define RCC_PLLCFGR_PLLPDIV_1 ((uint32_t)0x10000000U)
|
|
|
5126 #define RCC_PLLCFGR_PLLPDIV_2 ((uint32_t)0x20000000U)
|
|
|
5127 #define RCC_PLLCFGR_PLLPDIV_3 ((uint32_t)0x40000000U)
|
|
|
5128 #define RCC_PLLCFGR_PLLPDIV_4 ((uint32_t)0x80000000U)
|
|
|
5129
|
|
|
5130 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
|
|
|
5131 #define RCC_PLLSAI1CFGR_PLLSAI1N ((uint32_t)0x00007F00U)
|
|
|
5132 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 ((uint32_t)0x00000100U)
|
|
|
5133 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 ((uint32_t)0x00000200U)
|
|
|
5134 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 ((uint32_t)0x00000400U)
|
|
|
5135 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 ((uint32_t)0x00000800U)
|
|
|
5136 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 ((uint32_t)0x00001000U)
|
|
|
5137 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 ((uint32_t)0x00002000U)
|
|
|
5138 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 ((uint32_t)0x00004000U)
|
|
|
5139
|
|
|
5140 #define RCC_PLLSAI1CFGR_PLLSAI1PEN ((uint32_t)0x00010000U)
|
|
|
5141 #define RCC_PLLSAI1CFGR_PLLSAI1P ((uint32_t)0x00020000U)
|
|
|
5142
|
|
|
5143 #define RCC_PLLSAI1CFGR_PLLSAI1QEN ((uint32_t)0x00100000U)
|
|
|
5144 #define RCC_PLLSAI1CFGR_PLLSAI1Q ((uint32_t)0x00600000U)
|
|
|
5145 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 ((uint32_t)0x00200000U)
|
|
|
5146 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 ((uint32_t)0x00400000U)
|
|
|
5147
|
|
|
5148 #define RCC_PLLSAI1CFGR_PLLSAI1REN ((uint32_t)0x01000000U)
|
|
|
5149 #define RCC_PLLSAI1CFGR_PLLSAI1R ((uint32_t)0x06000000U)
|
|
|
5150 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 ((uint32_t)0x02000000U)
|
|
|
5151 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 ((uint32_t)0x04000000U)
|
|
|
5152
|
|
|
5153 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV ((uint32_t)0xF8000000U)
|
|
|
5154 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 ((uint32_t)0x08000000U)
|
|
|
5155 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 ((uint32_t)0x10000000U)
|
|
|
5156 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 ((uint32_t)0x20000000U)
|
|
|
5157 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 ((uint32_t)0x40000000U)
|
|
|
5158 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 ((uint32_t)0x80000000U)
|
|
|
5159
|
|
|
5160 /******************** Bit definition for RCC_CIER register ******************/
|
|
|
5161 #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U)
|
|
|
5162 #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U)
|
|
|
5163 #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000004U)
|
|
|
5164 #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000008U)
|
|
|
5165 #define RCC_CIER_HSERDYIE ((uint32_t)0x00000010U)
|
|
|
5166 #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000020U)
|
|
|
5167 #define RCC_CIER_PLLSAI1RDYIE ((uint32_t)0x00000040U)
|
|
|
5168 #define RCC_CIER_LSECSSIE ((uint32_t)0x00000200U)
|
|
|
5169 #define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000400U)
|
|
|
5170
|
|
|
5171 /******************** Bit definition for RCC_CIFR register ******************/
|
|
|
5172 #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U)
|
|
|
5173 #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U)
|
|
|
5174 #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000004U)
|
|
|
5175 #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000008U)
|
|
|
5176 #define RCC_CIFR_HSERDYF ((uint32_t)0x00000010U)
|
|
|
5177 #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000020U)
|
|
|
5178 #define RCC_CIFR_PLLSAI1RDYF ((uint32_t)0x00000040U)
|
|
|
5179 #define RCC_CIFR_CSSF ((uint32_t)0x00000100U)
|
|
|
5180 #define RCC_CIFR_LSECSSF ((uint32_t)0x00000200U)
|
|
|
5181 #define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000400U)
|
|
|
5182
|
|
|
5183 /******************** Bit definition for RCC_CICR register ******************/
|
|
|
5184 #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U)
|
|
|
5185 #define RCC_CICR_LSERDYC ((uint32_t)0x00000002U)
|
|
|
5186 #define RCC_CICR_MSIRDYC ((uint32_t)0x00000004U)
|
|
|
5187 #define RCC_CICR_HSIRDYC ((uint32_t)0x00000008U)
|
|
|
5188 #define RCC_CICR_HSERDYC ((uint32_t)0x00000010U)
|
|
|
5189 #define RCC_CICR_PLLRDYC ((uint32_t)0x00000020U)
|
|
|
5190 #define RCC_CICR_PLLSAI1RDYC ((uint32_t)0x00000040U)
|
|
|
5191 #define RCC_CICR_CSSC ((uint32_t)0x00000100U)
|
|
|
5192 #define RCC_CICR_LSECSSC ((uint32_t)0x00000200U)
|
|
|
5193 #define RCC_CICR_HSI48RDYC ((uint32_t)0x00000400U)
|
|
|
5194
|
|
|
5195 /******************** Bit definition for RCC_AHB1RSTR register **************/
|
|
|
5196 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00000001U)
|
|
|
5197 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00000002U)
|
|
|
5198 #define RCC_AHB1RSTR_FLASHRST ((uint32_t)0x00000100U)
|
|
|
5199 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000U)
|
|
|
5200 #define RCC_AHB1RSTR_TSCRST ((uint32_t)0x00010000U)
|
|
|
5201
|
|
|
5202 /******************** Bit definition for RCC_AHB2RSTR register **************/
|
|
|
5203 #define RCC_AHB2RSTR_GPIOARST ((uint32_t)0x00000001U)
|
|
|
5204 #define RCC_AHB2RSTR_GPIOBRST ((uint32_t)0x00000002U)
|
|
|
5205 #define RCC_AHB2RSTR_GPIOCRST ((uint32_t)0x00000004U)
|
|
|
5206 #define RCC_AHB2RSTR_GPIODRST ((uint32_t)0x00000008U)
|
|
|
5207 #define RCC_AHB2RSTR_GPIOERST ((uint32_t)0x00000010U)
|
|
|
5208 #define RCC_AHB2RSTR_GPIOHRST ((uint32_t)0x00000080U)
|
|
|
5209 #define RCC_AHB2RSTR_ADCRST ((uint32_t)0x00002000U)
|
|
|
5210 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00040000U)
|
|
|
5211
|
|
|
5212 /******************** Bit definition for RCC_AHB3RSTR register **************/
|
|
|
5213 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000100U)
|
|
|
5214
|
|
|
5215 /******************** Bit definition for RCC_APB1RSTR1 register **************/
|
|
|
5216 #define RCC_APB1RSTR1_TIM2RST ((uint32_t)0x00000001U)
|
|
|
5217 #define RCC_APB1RSTR1_TIM6RST ((uint32_t)0x00000010U)
|
|
|
5218 #define RCC_APB1RSTR1_TIM7RST ((uint32_t)0x00000020U)
|
|
|
5219 #define RCC_APB1RSTR1_SPI2RST ((uint32_t)0x00004000U)
|
|
|
5220 #define RCC_APB1RSTR1_SPI3RST ((uint32_t)0x00008000U)
|
|
|
5221 #define RCC_APB1RSTR1_USART2RST ((uint32_t)0x00020000U)
|
|
|
5222 #define RCC_APB1RSTR1_USART3RST ((uint32_t)0x00040000U)
|
|
|
5223 #define RCC_APB1RSTR1_I2C1RST ((uint32_t)0x00200000U)
|
|
|
5224 #define RCC_APB1RSTR1_I2C2RST ((uint32_t)0x00400000U)
|
|
|
5225 #define RCC_APB1RSTR1_I2C3RST ((uint32_t)0x00800000U)
|
|
|
5226 #define RCC_APB1RSTR1_CRSRST ((uint32_t)0x01000000U)
|
|
|
5227 #define RCC_APB1RSTR1_CAN1RST ((uint32_t)0x02000000U)
|
|
|
5228 #define RCC_APB1RSTR1_PWRRST ((uint32_t)0x10000000U)
|
|
|
5229 #define RCC_APB1RSTR1_DAC1RST ((uint32_t)0x20000000U)
|
|
|
5230 #define RCC_APB1RSTR1_OPAMPRST ((uint32_t)0x40000000U)
|
|
|
5231 #define RCC_APB1RSTR1_LPTIM1RST ((uint32_t)0x80000000U)
|
|
|
5232
|
|
|
5233 /******************** Bit definition for RCC_APB1RSTR2 register **************/
|
|
|
5234 #define RCC_APB1RSTR2_LPUART1RST ((uint32_t)0x00000001U)
|
|
|
5235 #define RCC_APB1RSTR2_SWPMI1RST ((uint32_t)0x00000004U)
|
|
|
5236 #define RCC_APB1RSTR2_LPTIM2RST ((uint32_t)0x00000020U)
|
|
|
5237
|
|
|
5238 /******************** Bit definition for RCC_APB2RSTR register **************/
|
|
|
5239 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U)
|
|
|
5240 #define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000400U)
|
|
|
5241 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800U)
|
|
|
5242 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U)
|
|
|
5243 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U)
|
|
|
5244 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000U)
|
|
|
5245 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000U)
|
|
|
5246 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00200000U)
|
|
|
5247
|
|
|
5248 /******************** Bit definition for RCC_AHB1ENR register ***************/
|
|
|
5249 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00000001U)
|
|
|
5250 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00000002U)
|
|
|
5251 #define RCC_AHB1ENR_FLASHEN ((uint32_t)0x00000100U)
|
|
|
5252 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000U)
|
|
|
5253 #define RCC_AHB1ENR_TSCEN ((uint32_t)0x00010000U)
|
|
|
5254
|
|
|
5255 /******************** Bit definition for RCC_AHB2ENR register ***************/
|
|
|
5256 #define RCC_AHB2ENR_GPIOAEN ((uint32_t)0x00000001U)
|
|
|
5257 #define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002U)
|
|
|
5258 #define RCC_AHB2ENR_GPIOCEN ((uint32_t)0x00000004U)
|
|
|
5259 #define RCC_AHB2ENR_GPIODEN ((uint32_t)0x00000008U)
|
|
|
5260 #define RCC_AHB2ENR_GPIOEEN ((uint32_t)0x00000010U)
|
|
|
5261 #define RCC_AHB2ENR_GPIOHEN ((uint32_t)0x00000080U)
|
|
|
5262 #define RCC_AHB2ENR_ADCEN ((uint32_t)0x00002000U)
|
|
|
5263 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00040000U)
|
|
|
5264
|
|
|
5265 /******************** Bit definition for RCC_AHB3ENR register ***************/
|
|
|
5266 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000100U)
|
|
|
5267
|
|
|
5268 /******************** Bit definition for RCC_APB1ENR1 register ***************/
|
|
|
5269 #define RCC_APB1ENR1_TIM2EN ((uint32_t)0x00000001U)
|
|
|
5270 #define RCC_APB1ENR1_TIM6EN ((uint32_t)0x00000010U)
|
|
|
5271 #define RCC_APB1ENR1_TIM7EN ((uint32_t)0x00000020U)
|
|
|
5272 #define RCC_APB1ENR1_RTCAPBEN ((uint32_t)0x00000400U)
|
|
|
5273 #define RCC_APB1ENR1_WWDGEN ((uint32_t)0x00000800U)
|
|
|
5274 #define RCC_APB1ENR1_SPI2EN ((uint32_t)0x00004000U)
|
|
|
5275 #define RCC_APB1ENR1_SPI3EN ((uint32_t)0x00008000U)
|
|
|
5276 #define RCC_APB1ENR1_USART2EN ((uint32_t)0x00020000U)
|
|
|
5277 #define RCC_APB1ENR1_USART3EN ((uint32_t)0x00040000U)
|
|
|
5278 #define RCC_APB1ENR1_I2C1EN ((uint32_t)0x00200000U)
|
|
|
5279 #define RCC_APB1ENR1_I2C2EN ((uint32_t)0x00400000U)
|
|
|
5280 #define RCC_APB1ENR1_I2C3EN ((uint32_t)0x00800000U)
|
|
|
5281 #define RCC_APB1ENR1_CRSEN ((uint32_t)0x01000000U)
|
|
|
5282 #define RCC_APB1ENR1_CAN1EN ((uint32_t)0x02000000U)
|
|
|
5283 #define RCC_APB1ENR1_PWREN ((uint32_t)0x10000000U)
|
|
|
5284 #define RCC_APB1ENR1_DAC1EN ((uint32_t)0x20000000U)
|
|
|
5285 #define RCC_APB1ENR1_OPAMPEN ((uint32_t)0x40000000U)
|
|
|
5286 #define RCC_APB1ENR1_LPTIM1EN ((uint32_t)0x80000000U)
|
|
|
5287
|
|
|
5288 /******************** Bit definition for RCC_APB1RSTR2 register **************/
|
|
|
5289 #define RCC_APB1ENR2_LPUART1EN ((uint32_t)0x00000001U)
|
|
|
5290 #define RCC_APB1ENR2_SWPMI1EN ((uint32_t)0x00000004U)
|
|
|
5291 #define RCC_APB1ENR2_LPTIM2EN ((uint32_t)0x00000020U)
|
|
|
5292
|
|
|
5293 /******************** Bit definition for RCC_APB2ENR register ***************/
|
|
|
5294 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U)
|
|
|
5295 #define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U)
|
|
|
5296 #define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000400U)
|
|
|
5297 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800U)
|
|
|
5298 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U)
|
|
|
5299 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U)
|
|
|
5300 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000U)
|
|
|
5301 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000U)
|
|
|
5302 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00200000U)
|
|
|
5303
|
|
|
5304 /******************** Bit definition for RCC_AHB1SMENR register ***************/
|
|
|
5305 #define RCC_AHB1SMENR_DMA1SMEN ((uint32_t)0x00000001U)
|
|
|
5306 #define RCC_AHB1SMENR_DMA2SMEN ((uint32_t)0x00000002U)
|
|
|
5307 #define RCC_AHB1SMENR_FLASHSMEN ((uint32_t)0x00000100U)
|
|
|
5308 #define RCC_AHB1SMENR_SRAM1SMEN ((uint32_t)0x00000200U)
|
|
|
5309 #define RCC_AHB1SMENR_CRCSMEN ((uint32_t)0x00001000U)
|
|
|
5310 #define RCC_AHB1SMENR_TSCSMEN ((uint32_t)0x00010000U)
|
|
|
5311
|
|
|
5312 /******************** Bit definition for RCC_AHB2SMENR register *************/
|
|
|
5313 #define RCC_AHB2SMENR_GPIOASMEN ((uint32_t)0x00000001U)
|
|
|
5314 #define RCC_AHB2SMENR_GPIOBSMEN ((uint32_t)0x00000002U)
|
|
|
5315 #define RCC_AHB2SMENR_GPIOCSMEN ((uint32_t)0x00000004U)
|
|
|
5316 #define RCC_AHB2SMENR_GPIODSMEN ((uint32_t)0x00000008U)
|
|
|
5317 #define RCC_AHB2SMENR_GPIOESMEN ((uint32_t)0x00000010U)
|
|
|
5318 #define RCC_AHB2SMENR_GPIOHSMEN ((uint32_t)0x00000080U)
|
|
|
5319 #define RCC_AHB2SMENR_SRAM2SMEN ((uint32_t)0x00000200U)
|
|
|
5320 #define RCC_AHB2SMENR_ADCSMEN ((uint32_t)0x00002000U)
|
|
|
5321 #define RCC_AHB2SMENR_RNGSMEN ((uint32_t)0x00040000U)
|
|
|
5322
|
|
|
5323 /******************** Bit definition for RCC_AHB3SMENR register *************/
|
|
|
5324 #define RCC_AHB3SMENR_QSPISMEN ((uint32_t)0x00000100U)
|
|
|
5325
|
|
|
5326 /******************** Bit definition for RCC_APB1SMENR1 register *************/
|
|
|
5327 #define RCC_APB1SMENR1_TIM2SMEN ((uint32_t)0x00000001U)
|
|
|
5328 #define RCC_APB1SMENR1_TIM6SMEN ((uint32_t)0x00000010U)
|
|
|
5329 #define RCC_APB1SMENR1_TIM7SMEN ((uint32_t)0x00000020U)
|
|
|
5330 #define RCC_APB1SMENR1_RTCAPBSMEN ((uint32_t)0x00000400U)
|
|
|
5331 #define RCC_APB1SMENR1_WWDGSMEN ((uint32_t)0x00000800U)
|
|
|
5332 #define RCC_APB1SMENR1_SPI2SMEN ((uint32_t)0x00004000U)
|
|
|
5333 #define RCC_APB1SMENR1_SPI3SMEN ((uint32_t)0x00008000U)
|
|
|
5334 #define RCC_APB1SMENR1_USART2SMEN ((uint32_t)0x00020000U)
|
|
|
5335 #define RCC_APB1SMENR1_USART3SMEN ((uint32_t)0x00040000U)
|
|
|
5336 #define RCC_APB1SMENR1_I2C1SMEN ((uint32_t)0x00200000U)
|
|
|
5337 #define RCC_APB1SMENR1_I2C2SMEN ((uint32_t)0x00400000U)
|
|
|
5338 #define RCC_APB1SMENR1_I2C3SMEN ((uint32_t)0x00800000U)
|
|
|
5339 #define RCC_APB1SMENR1_CRSSMEN ((uint32_t)0x01000000U)
|
|
|
5340 #define RCC_APB1SMENR1_CAN1SMEN ((uint32_t)0x02000000U)
|
|
|
5341 #define RCC_APB1SMENR1_PWRSMEN ((uint32_t)0x10000000U)
|
|
|
5342 #define RCC_APB1SMENR1_DAC1SMEN ((uint32_t)0x20000000U)
|
|
|
5343 #define RCC_APB1SMENR1_OPAMPSMEN ((uint32_t)0x40000000U)
|
|
|
5344 #define RCC_APB1SMENR1_LPTIM1SMEN ((uint32_t)0x80000000U)
|
|
|
5345
|
|
|
5346 /******************** Bit definition for RCC_APB1SMENR2 register *************/
|
|
|
5347 #define RCC_APB1SMENR2_LPUART1SMEN ((uint32_t)0x00000001U)
|
|
|
5348 #define RCC_APB1SMENR2_SWPMI1SMEN ((uint32_t)0x00000004U)
|
|
|
5349 #define RCC_APB1SMENR2_LPTIM2SMEN ((uint32_t)0x00000020U)
|
|
|
5350
|
|
|
5351 /******************** Bit definition for RCC_APB2SMENR register *************/
|
|
|
5352 #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U)
|
|
|
5353 #define RCC_APB2SMENR_SDMMC1SMEN ((uint32_t)0x00000400U)
|
|
|
5354 #define RCC_APB2SMENR_TIM1SMEN ((uint32_t)0x00000800U)
|
|
|
5355 #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U)
|
|
|
5356 #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U)
|
|
|
5357 #define RCC_APB2SMENR_TIM15SMEN ((uint32_t)0x00010000U)
|
|
|
5358 #define RCC_APB2SMENR_TIM16SMEN ((uint32_t)0x00020000U)
|
|
|
5359 #define RCC_APB2SMENR_SAI1SMEN ((uint32_t)0x00200000U)
|
|
|
5360
|
|
|
5361 /******************** Bit definition for RCC_CCIPR register ******************/
|
|
|
5362 #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U)
|
|
|
5363 #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U)
|
|
|
5364 #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U)
|
|
|
5365
|
|
|
5366 #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU)
|
|
|
5367 #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U)
|
|
|
5368 #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U)
|
|
|
5369
|
|
|
5370 #define RCC_CCIPR_USART3SEL ((uint32_t)0x00000030U)
|
|
|
5371 #define RCC_CCIPR_USART3SEL_0 ((uint32_t)0x00000010U)
|
|
|
5372 #define RCC_CCIPR_USART3SEL_1 ((uint32_t)0x00000020U)
|
|
|
5373
|
|
|
5374 #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x00000C00U)
|
|
|
5375 #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x00000400U)
|
|
|
5376 #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x00000800U)
|
|
|
5377
|
|
|
5378 #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U)
|
|
|
5379 #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U)
|
|
|
5380 #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U)
|
|
|
5381
|
|
|
5382 #define RCC_CCIPR_I2C2SEL ((uint32_t)0x0000C000U)
|
|
|
5383 #define RCC_CCIPR_I2C2SEL_0 ((uint32_t)0x00004000U)
|
|
|
5384 #define RCC_CCIPR_I2C2SEL_1 ((uint32_t)0x00008000U)
|
|
|
5385
|
|
|
5386 #define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000U)
|
|
|
5387 #define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000U)
|
|
|
5388 #define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000U)
|
|
|
5389
|
|
|
5390 #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U)
|
|
|
5391 #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U)
|
|
|
5392 #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U)
|
|
|
5393
|
|
|
5394 #define RCC_CCIPR_LPTIM2SEL ((uint32_t)0x00300000U)
|
|
|
5395 #define RCC_CCIPR_LPTIM2SEL_0 ((uint32_t)0x00100000U)
|
|
|
5396 #define RCC_CCIPR_LPTIM2SEL_1 ((uint32_t)0x00200000U)
|
|
|
5397
|
|
|
5398 #define RCC_CCIPR_SAI1SEL ((uint32_t)0x00C00000U)
|
|
|
5399 #define RCC_CCIPR_SAI1SEL_0 ((uint32_t)0x00400000U)
|
|
|
5400 #define RCC_CCIPR_SAI1SEL_1 ((uint32_t)0x00800000U)
|
|
|
5401
|
|
|
5402 #define RCC_CCIPR_CLK48SEL ((uint32_t)0x0C000000U)
|
|
|
5403 #define RCC_CCIPR_CLK48SEL_0 ((uint32_t)0x04000000U)
|
|
|
5404 #define RCC_CCIPR_CLK48SEL_1 ((uint32_t)0x08000000U)
|
|
|
5405
|
|
|
5406 #define RCC_CCIPR_ADCSEL ((uint32_t)0x30000000U)
|
|
|
5407 #define RCC_CCIPR_ADCSEL_0 ((uint32_t)0x10000000U)
|
|
|
5408 #define RCC_CCIPR_ADCSEL_1 ((uint32_t)0x20000000U)
|
|
|
5409
|
|
|
5410 #define RCC_CCIPR_SWPMI1SEL ((uint32_t)0x40000000U)
|
|
|
5411
|
|
|
5412 /******************** Bit definition for RCC_BDCR register ******************/
|
|
|
5413 #define RCC_BDCR_LSEON ((uint32_t)0x00000001U)
|
|
|
5414 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002U)
|
|
|
5415 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004U)
|
|
|
5416
|
|
|
5417 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018U)
|
|
|
5418 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008U)
|
|
|
5419 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010U)
|
|
|
5420
|
|
|
5421 #define RCC_BDCR_LSECSSON ((uint32_t)0x00000020U)
|
|
|
5422 #define RCC_BDCR_LSECSSD ((uint32_t)0x00000040U)
|
|
|
5423
|
|
|
5424 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300U)
|
|
|
5425 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100U)
|
|
|
5426 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200U)
|
|
|
5427
|
|
|
5428 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000U)
|
|
|
5429 #define RCC_BDCR_BDRST ((uint32_t)0x00010000U)
|
|
|
5430 #define RCC_BDCR_LSCOEN ((uint32_t)0x01000000U)
|
|
|
5431 #define RCC_BDCR_LSCOSEL ((uint32_t)0x02000000U)
|
|
|
5432
|
|
|
5433 /******************** Bit definition for RCC_CSR register *******************/
|
|
|
5434 #define RCC_CSR_LSION ((uint32_t)0x00000001U)
|
|
|
5435 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002U)
|
|
|
5436
|
|
|
5437 #define RCC_CSR_MSISRANGE ((uint32_t)0x00000F00U)
|
|
|
5438 #define RCC_CSR_MSISRANGE_1 ((uint32_t)0x00000400U) /*!< MSI frequency 1MHZ */
|
|
|
5439 #define RCC_CSR_MSISRANGE_2 ((uint32_t)0x00000500U) /*!< MSI frequency 2MHZ */
|
|
|
5440 #define RCC_CSR_MSISRANGE_4 ((uint32_t)0x00000600U) /*!< The default frequency 4MHZ */
|
|
|
5441 #define RCC_CSR_MSISRANGE_8 ((uint32_t)0x00000700U) /*!< MSI frequency 8MHZ */
|
|
|
5442
|
|
|
5443 #define RCC_CSR_RMVF ((uint32_t)0x00800000U)
|
|
|
5444 #define RCC_CSR_FWRSTF ((uint32_t)0x01000000U)
|
|
|
5445 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U)
|
|
|
5446 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000U)
|
|
|
5447 #define RCC_CSR_BORRSTF ((uint32_t)0x08000000U)
|
|
|
5448 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U)
|
|
|
5449 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U)
|
|
|
5450 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U)
|
|
|
5451 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U)
|
|
|
5452
|
|
|
5453 /******************** Bit definition for RCC_CRRCR register *****************/
|
|
|
5454 #define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U)
|
|
|
5455 #define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U)
|
|
|
5456
|
|
|
5457 /*!< HSI48CAL configuration */
|
|
|
5458 #define RCC_CRRCR_HSI48CAL ((uint32_t)0x00FF8000U) /*!< HSI48CAL[8:0] bits */
|
|
|
5459 #define RCC_CRRCR_HSI48CAL_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
5460 #define RCC_CRRCR_HSI48CAL_1 ((uint32_t)0x00010000U) /*!<Bit 1 */
|
|
|
5461 #define RCC_CRRCR_HSI48CAL_2 ((uint32_t)0x00020000U) /*!<Bit 2 */
|
|
|
5462 #define RCC_CRRCR_HSI48CAL_3 ((uint32_t)0x00040000U) /*!<Bit 3 */
|
|
|
5463 #define RCC_CRRCR_HSI48CAL_4 ((uint32_t)0x00080000U) /*!<Bit 4 */
|
|
|
5464 #define RCC_CRRCR_HSI48CAL_5 ((uint32_t)0x00100000U) /*!<Bit 5 */
|
|
|
5465 #define RCC_CRRCR_HSI48CAL_6 ((uint32_t)0x00200000U) /*!<Bit 6 */
|
|
|
5466 #define RCC_CRRCR_HSI48CAL_7 ((uint32_t)0x00400000U) /*!<Bit 7 */
|
|
|
5467 #define RCC_CRRCR_HSI48CAL_8 ((uint32_t)0x00800000U) /*!<Bit 8 */
|
|
|
5468
|
|
|
5469
|
|
|
5470
|
|
|
5471 /******************************************************************************/
|
|
|
5472 /* */
|
|
|
5473 /* RNG */
|
|
|
5474 /* */
|
|
|
5475 /******************************************************************************/
|
|
|
5476 /******************** Bits definition for RNG_CR register *******************/
|
|
|
5477 #define RNG_CR_RNGEN ((uint32_t)0x00000004U)
|
|
|
5478 #define RNG_CR_IE ((uint32_t)0x00000008U)
|
|
|
5479
|
|
|
5480 /******************** Bits definition for RNG_SR register *******************/
|
|
|
5481 #define RNG_SR_DRDY ((uint32_t)0x00000001U)
|
|
|
5482 #define RNG_SR_CECS ((uint32_t)0x00000002U)
|
|
|
5483 #define RNG_SR_SECS ((uint32_t)0x00000004U)
|
|
|
5484 #define RNG_SR_CEIS ((uint32_t)0x00000020U)
|
|
|
5485 #define RNG_SR_SEIS ((uint32_t)0x00000040U)
|
|
|
5486
|
|
|
5487 /******************************************************************************/
|
|
|
5488 /* */
|
|
|
5489 /* Real-Time Clock (RTC) */
|
|
|
5490 /* */
|
|
|
5491 /******************************************************************************/
|
|
|
5492 /*
|
|
|
5493 * @brief Specific device feature definitions
|
|
|
5494 */
|
|
|
5495 #define RTC_TAMPER1_SUPPORT
|
|
|
5496 #define RTC_TAMPER2_SUPPORT
|
|
|
5497 #define RTC_TAMPER3_SUPPORT
|
|
|
5498 #define RTC_WAKEUP_SUPPORT
|
|
|
5499 #define RTC_BACKUP_SUPPORT
|
|
|
5500
|
|
|
5501 /******************** Bits definition for RTC_TR register *******************/
|
|
|
5502 #define RTC_TR_PM ((uint32_t)0x00400000U)
|
|
|
5503 #define RTC_TR_HT ((uint32_t)0x00300000U)
|
|
|
5504 #define RTC_TR_HT_0 ((uint32_t)0x00100000U)
|
|
|
5505 #define RTC_TR_HT_1 ((uint32_t)0x00200000U)
|
|
|
5506 #define RTC_TR_HU ((uint32_t)0x000F0000U)
|
|
|
5507 #define RTC_TR_HU_0 ((uint32_t)0x00010000U)
|
|
|
5508 #define RTC_TR_HU_1 ((uint32_t)0x00020000U)
|
|
|
5509 #define RTC_TR_HU_2 ((uint32_t)0x00040000U)
|
|
|
5510 #define RTC_TR_HU_3 ((uint32_t)0x00080000U)
|
|
|
5511 #define RTC_TR_MNT ((uint32_t)0x00007000U)
|
|
|
5512 #define RTC_TR_MNT_0 ((uint32_t)0x00001000U)
|
|
|
5513 #define RTC_TR_MNT_1 ((uint32_t)0x00002000U)
|
|
|
5514 #define RTC_TR_MNT_2 ((uint32_t)0x00004000U)
|
|
|
5515 #define RTC_TR_MNU ((uint32_t)0x00000F00U)
|
|
|
5516 #define RTC_TR_MNU_0 ((uint32_t)0x00000100U)
|
|
|
5517 #define RTC_TR_MNU_1 ((uint32_t)0x00000200U)
|
|
|
5518 #define RTC_TR_MNU_2 ((uint32_t)0x00000400U)
|
|
|
5519 #define RTC_TR_MNU_3 ((uint32_t)0x00000800U)
|
|
|
5520 #define RTC_TR_ST ((uint32_t)0x00000070U)
|
|
|
5521 #define RTC_TR_ST_0 ((uint32_t)0x00000010U)
|
|
|
5522 #define RTC_TR_ST_1 ((uint32_t)0x00000020U)
|
|
|
5523 #define RTC_TR_ST_2 ((uint32_t)0x00000040U)
|
|
|
5524 #define RTC_TR_SU ((uint32_t)0x0000000FU)
|
|
|
5525 #define RTC_TR_SU_0 ((uint32_t)0x00000001U)
|
|
|
5526 #define RTC_TR_SU_1 ((uint32_t)0x00000002U)
|
|
|
5527 #define RTC_TR_SU_2 ((uint32_t)0x00000004U)
|
|
|
5528 #define RTC_TR_SU_3 ((uint32_t)0x00000008U)
|
|
|
5529
|
|
|
5530 /******************** Bits definition for RTC_DR register *******************/
|
|
|
5531 #define RTC_DR_YT ((uint32_t)0x00F00000U)
|
|
|
5532 #define RTC_DR_YT_0 ((uint32_t)0x00100000U)
|
|
|
5533 #define RTC_DR_YT_1 ((uint32_t)0x00200000U)
|
|
|
5534 #define RTC_DR_YT_2 ((uint32_t)0x00400000U)
|
|
|
5535 #define RTC_DR_YT_3 ((uint32_t)0x00800000U)
|
|
|
5536 #define RTC_DR_YU ((uint32_t)0x000F0000U)
|
|
|
5537 #define RTC_DR_YU_0 ((uint32_t)0x00010000U)
|
|
|
5538 #define RTC_DR_YU_1 ((uint32_t)0x00020000U)
|
|
|
5539 #define RTC_DR_YU_2 ((uint32_t)0x00040000U)
|
|
|
5540 #define RTC_DR_YU_3 ((uint32_t)0x00080000U)
|
|
|
5541 #define RTC_DR_WDU ((uint32_t)0x0000E000U)
|
|
|
5542 #define RTC_DR_WDU_0 ((uint32_t)0x00002000U)
|
|
|
5543 #define RTC_DR_WDU_1 ((uint32_t)0x00004000U)
|
|
|
5544 #define RTC_DR_WDU_2 ((uint32_t)0x00008000U)
|
|
|
5545 #define RTC_DR_MT ((uint32_t)0x00001000U)
|
|
|
5546 #define RTC_DR_MU ((uint32_t)0x00000F00U)
|
|
|
5547 #define RTC_DR_MU_0 ((uint32_t)0x00000100U)
|
|
|
5548 #define RTC_DR_MU_1 ((uint32_t)0x00000200U)
|
|
|
5549 #define RTC_DR_MU_2 ((uint32_t)0x00000400U)
|
|
|
5550 #define RTC_DR_MU_3 ((uint32_t)0x00000800U)
|
|
|
5551 #define RTC_DR_DT ((uint32_t)0x00000030U)
|
|
|
5552 #define RTC_DR_DT_0 ((uint32_t)0x00000010U)
|
|
|
5553 #define RTC_DR_DT_1 ((uint32_t)0x00000020U)
|
|
|
5554 #define RTC_DR_DU ((uint32_t)0x0000000FU)
|
|
|
5555 #define RTC_DR_DU_0 ((uint32_t)0x00000001U)
|
|
|
5556 #define RTC_DR_DU_1 ((uint32_t)0x00000002U)
|
|
|
5557 #define RTC_DR_DU_2 ((uint32_t)0x00000004U)
|
|
|
5558 #define RTC_DR_DU_3 ((uint32_t)0x00000008U)
|
|
|
5559
|
|
|
5560 /******************** Bits definition for RTC_CR register *******************/
|
|
|
5561 #define RTC_CR_ITSE ((uint32_t)0x01000000U)
|
|
|
5562 #define RTC_CR_COE ((uint32_t)0x00800000U)
|
|
|
5563 #define RTC_CR_OSEL ((uint32_t)0x00600000U)
|
|
|
5564 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000U)
|
|
|
5565 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000U)
|
|
|
5566 #define RTC_CR_POL ((uint32_t)0x00100000U)
|
|
|
5567 #define RTC_CR_COSEL ((uint32_t)0x00080000U)
|
|
|
5568 #define RTC_CR_BCK ((uint32_t)0x00040000U)
|
|
|
5569 #define RTC_CR_SUB1H ((uint32_t)0x00020000U)
|
|
|
5570 #define RTC_CR_ADD1H ((uint32_t)0x00010000U)
|
|
|
5571 #define RTC_CR_TSIE ((uint32_t)0x00008000U)
|
|
|
5572 #define RTC_CR_WUTIE ((uint32_t)0x00004000U)
|
|
|
5573 #define RTC_CR_ALRBIE ((uint32_t)0x00002000U)
|
|
|
5574 #define RTC_CR_ALRAIE ((uint32_t)0x00001000U)
|
|
|
5575 #define RTC_CR_TSE ((uint32_t)0x00000800U)
|
|
|
5576 #define RTC_CR_WUTE ((uint32_t)0x00000400U)
|
|
|
5577 #define RTC_CR_ALRBE ((uint32_t)0x00000200U)
|
|
|
5578 #define RTC_CR_ALRAE ((uint32_t)0x00000100U)
|
|
|
5579 #define RTC_CR_FMT ((uint32_t)0x00000040U)
|
|
|
5580 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020U)
|
|
|
5581 #define RTC_CR_REFCKON ((uint32_t)0x00000010U)
|
|
|
5582 #define RTC_CR_TSEDGE ((uint32_t)0x00000008U)
|
|
|
5583 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007U)
|
|
|
5584 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U)
|
|
|
5585 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U)
|
|
|
5586 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U)
|
|
|
5587
|
|
|
5588 /******************** Bits definition for RTC_ISR register ******************/
|
|
|
5589 #define RTC_ISR_ITSF ((uint32_t)0x00020000U)
|
|
|
5590 #define RTC_ISR_RECALPF ((uint32_t)0x00010000U)
|
|
|
5591 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000U)
|
|
|
5592 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000U)
|
|
|
5593 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000U)
|
|
|
5594 #define RTC_ISR_TSOVF ((uint32_t)0x00001000U)
|
|
|
5595 #define RTC_ISR_TSF ((uint32_t)0x00000800U)
|
|
|
5596 #define RTC_ISR_WUTF ((uint32_t)0x00000400U)
|
|
|
5597 #define RTC_ISR_ALRBF ((uint32_t)0x00000200U)
|
|
|
5598 #define RTC_ISR_ALRAF ((uint32_t)0x00000100U)
|
|
|
5599 #define RTC_ISR_INIT ((uint32_t)0x00000080U)
|
|
|
5600 #define RTC_ISR_INITF ((uint32_t)0x00000040U)
|
|
|
5601 #define RTC_ISR_RSF ((uint32_t)0x00000020U)
|
|
|
5602 #define RTC_ISR_INITS ((uint32_t)0x00000010U)
|
|
|
5603 #define RTC_ISR_SHPF ((uint32_t)0x00000008U)
|
|
|
5604 #define RTC_ISR_WUTWF ((uint32_t)0x00000004U)
|
|
|
5605 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002U)
|
|
|
5606 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001U)
|
|
|
5607
|
|
|
5608 /******************** Bits definition for RTC_PRER register *****************/
|
|
|
5609 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U)
|
|
|
5610 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU)
|
|
|
5611
|
|
|
5612 /******************** Bits definition for RTC_WUTR register *****************/
|
|
|
5613 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
|
|
|
5614
|
|
|
5615 /******************** Bits definition for RTC_ALRMAR register ***************/
|
|
|
5616 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U)
|
|
|
5617 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U)
|
|
|
5618 #define RTC_ALRMAR_DT ((uint32_t)0x30000000U)
|
|
|
5619 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U)
|
|
|
5620 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U)
|
|
|
5621 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000U)
|
|
|
5622 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U)
|
|
|
5623 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U)
|
|
|
5624 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U)
|
|
|
5625 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U)
|
|
|
5626 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U)
|
|
|
5627 #define RTC_ALRMAR_PM ((uint32_t)0x00400000U)
|
|
|
5628 #define RTC_ALRMAR_HT ((uint32_t)0x00300000U)
|
|
|
5629 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U)
|
|
|
5630 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U)
|
|
|
5631 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000U)
|
|
|
5632 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U)
|
|
|
5633 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U)
|
|
|
5634 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U)
|
|
|
5635 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U)
|
|
|
5636 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U)
|
|
|
5637 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000U)
|
|
|
5638 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U)
|
|
|
5639 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U)
|
|
|
5640 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U)
|
|
|
5641 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U)
|
|
|
5642 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U)
|
|
|
5643 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U)
|
|
|
5644 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U)
|
|
|
5645 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U)
|
|
|
5646 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U)
|
|
|
5647 #define RTC_ALRMAR_ST ((uint32_t)0x00000070U)
|
|
|
5648 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U)
|
|
|
5649 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U)
|
|
|
5650 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U)
|
|
|
5651 #define RTC_ALRMAR_SU ((uint32_t)0x0000000FU)
|
|
|
5652 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U)
|
|
|
5653 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U)
|
|
|
5654 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U)
|
|
|
5655 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U)
|
|
|
5656
|
|
|
5657 /******************** Bits definition for RTC_ALRMBR register ***************/
|
|
|
5658 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U)
|
|
|
5659 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U)
|
|
|
5660 #define RTC_ALRMBR_DT ((uint32_t)0x30000000U)
|
|
|
5661 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U)
|
|
|
5662 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U)
|
|
|
5663 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000U)
|
|
|
5664 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U)
|
|
|
5665 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U)
|
|
|
5666 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U)
|
|
|
5667 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U)
|
|
|
5668 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U)
|
|
|
5669 #define RTC_ALRMBR_PM ((uint32_t)0x00400000U)
|
|
|
5670 #define RTC_ALRMBR_HT ((uint32_t)0x00300000U)
|
|
|
5671 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U)
|
|
|
5672 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U)
|
|
|
5673 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000U)
|
|
|
5674 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U)
|
|
|
5675 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U)
|
|
|
5676 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U)
|
|
|
5677 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U)
|
|
|
5678 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U)
|
|
|
5679 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000U)
|
|
|
5680 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U)
|
|
|
5681 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U)
|
|
|
5682 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U)
|
|
|
5683 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U)
|
|
|
5684 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U)
|
|
|
5685 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U)
|
|
|
5686 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U)
|
|
|
5687 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U)
|
|
|
5688 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U)
|
|
|
5689 #define RTC_ALRMBR_ST ((uint32_t)0x00000070U)
|
|
|
5690 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U)
|
|
|
5691 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U)
|
|
|
5692 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U)
|
|
|
5693 #define RTC_ALRMBR_SU ((uint32_t)0x0000000FU)
|
|
|
5694 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U)
|
|
|
5695 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U)
|
|
|
5696 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U)
|
|
|
5697 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U)
|
|
|
5698
|
|
|
5699 /******************** Bits definition for RTC_WPR register ******************/
|
|
|
5700 #define RTC_WPR_KEY ((uint32_t)0x000000FFU)
|
|
|
5701
|
|
|
5702 /******************** Bits definition for RTC_SSR register ******************/
|
|
|
5703 #define RTC_SSR_SS ((uint32_t)0x0000FFFFU)
|
|
|
5704
|
|
|
5705 /******************** Bits definition for RTC_SHIFTR register ***************/
|
|
|
5706 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU)
|
|
|
5707 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U)
|
|
|
5708
|
|
|
5709 /******************** Bits definition for RTC_TSTR register *****************/
|
|
|
5710 #define RTC_TSTR_PM ((uint32_t)0x00400000U)
|
|
|
5711 #define RTC_TSTR_HT ((uint32_t)0x00300000U)
|
|
|
5712 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000U)
|
|
|
5713 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000U)
|
|
|
5714 #define RTC_TSTR_HU ((uint32_t)0x000F0000U)
|
|
|
5715 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000U)
|
|
|
5716 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000U)
|
|
|
5717 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000U)
|
|
|
5718 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000U)
|
|
|
5719 #define RTC_TSTR_MNT ((uint32_t)0x00007000U)
|
|
|
5720 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U)
|
|
|
5721 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U)
|
|
|
5722 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U)
|
|
|
5723 #define RTC_TSTR_MNU ((uint32_t)0x00000F00U)
|
|
|
5724 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U)
|
|
|
5725 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U)
|
|
|
5726 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U)
|
|
|
5727 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U)
|
|
|
5728 #define RTC_TSTR_ST ((uint32_t)0x00000070U)
|
|
|
5729 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010U)
|
|
|
5730 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020U)
|
|
|
5731 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040U)
|
|
|
5732 #define RTC_TSTR_SU ((uint32_t)0x0000000FU)
|
|
|
5733 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001U)
|
|
|
5734 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002U)
|
|
|
5735 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004U)
|
|
|
5736 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008U)
|
|
|
5737
|
|
|
5738 /******************** Bits definition for RTC_TSDR register *****************/
|
|
|
5739 #define RTC_TSDR_WDU ((uint32_t)0x0000E000U)
|
|
|
5740 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U)
|
|
|
5741 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U)
|
|
|
5742 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U)
|
|
|
5743 #define RTC_TSDR_MT ((uint32_t)0x00001000U)
|
|
|
5744 #define RTC_TSDR_MU ((uint32_t)0x00000F00U)
|
|
|
5745 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100U)
|
|
|
5746 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200U)
|
|
|
5747 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400U)
|
|
|
5748 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800U)
|
|
|
5749 #define RTC_TSDR_DT ((uint32_t)0x00000030U)
|
|
|
5750 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010U)
|
|
|
5751 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020U)
|
|
|
5752 #define RTC_TSDR_DU ((uint32_t)0x0000000FU)
|
|
|
5753 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001U)
|
|
|
5754 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002U)
|
|
|
5755 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004U)
|
|
|
5756 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008U)
|
|
|
5757
|
|
|
5758 /******************** Bits definition for RTC_TSSSR register ****************/
|
|
|
5759 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
|
|
|
5760
|
|
|
5761 /******************** Bits definition for RTC_CAL register *****************/
|
|
|
5762 #define RTC_CALR_CALP ((uint32_t)0x00008000U)
|
|
|
5763 #define RTC_CALR_CALW8 ((uint32_t)0x00004000U)
|
|
|
5764 #define RTC_CALR_CALW16 ((uint32_t)0x00002000U)
|
|
|
5765 #define RTC_CALR_CALM ((uint32_t)0x000001FFU)
|
|
|
5766 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001U)
|
|
|
5767 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002U)
|
|
|
5768 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004U)
|
|
|
5769 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008U)
|
|
|
5770 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010U)
|
|
|
5771 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020U)
|
|
|
5772 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040U)
|
|
|
5773 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080U)
|
|
|
5774 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100U)
|
|
|
5775
|
|
|
5776 /******************** Bits definition for RTC_TAMPCR register ***************/
|
|
|
5777 #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U)
|
|
|
5778 #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U)
|
|
|
5779 #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U)
|
|
|
5780 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U)
|
|
|
5781 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U)
|
|
|
5782 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U)
|
|
|
5783 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U)
|
|
|
5784 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U)
|
|
|
5785 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U)
|
|
|
5786 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U)
|
|
|
5787 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U)
|
|
|
5788 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U)
|
|
|
5789 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U)
|
|
|
5790 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U)
|
|
|
5791 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U)
|
|
|
5792 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U)
|
|
|
5793 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U)
|
|
|
5794 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U)
|
|
|
5795 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U)
|
|
|
5796 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U)
|
|
|
5797 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U)
|
|
|
5798 #define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U)
|
|
|
5799 #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U)
|
|
|
5800 #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U)
|
|
|
5801 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U)
|
|
|
5802 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U)
|
|
|
5803 #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U)
|
|
|
5804 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U)
|
|
|
5805
|
|
|
5806 /******************** Bits definition for RTC_ALRMASSR register *************/
|
|
|
5807 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
|
|
|
5808 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
|
|
|
5809 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
|
|
|
5810 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
|
|
|
5811 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
|
|
|
5812 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
|
|
|
5813
|
|
|
5814 /******************** Bits definition for RTC_ALRMBSSR register *************/
|
|
|
5815 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
|
|
|
5816 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
|
|
|
5817 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
|
|
|
5818 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
|
|
|
5819 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
|
|
|
5820 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
|
|
|
5821
|
|
|
5822 /******************** Bits definition for RTC_0R register *******************/
|
|
|
5823 #define RTC_OR_OUT_RMP ((uint32_t)0x00000002U)
|
|
|
5824 #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U)
|
|
|
5825
|
|
|
5826
|
|
|
5827 /******************** Bits definition for RTC_BKP0R register ****************/
|
|
|
5828 #define RTC_BKP0R ((uint32_t)0xFFFFFFFFU)
|
|
|
5829
|
|
|
5830 /******************** Bits definition for RTC_BKP1R register ****************/
|
|
|
5831 #define RTC_BKP1R ((uint32_t)0xFFFFFFFFU)
|
|
|
5832
|
|
|
5833 /******************** Bits definition for RTC_BKP2R register ****************/
|
|
|
5834 #define RTC_BKP2R ((uint32_t)0xFFFFFFFFU)
|
|
|
5835
|
|
|
5836 /******************** Bits definition for RTC_BKP3R register ****************/
|
|
|
5837 #define RTC_BKP3R ((uint32_t)0xFFFFFFFFU)
|
|
|
5838
|
|
|
5839 /******************** Bits definition for RTC_BKP4R register ****************/
|
|
|
5840 #define RTC_BKP4R ((uint32_t)0xFFFFFFFFU)
|
|
|
5841
|
|
|
5842 /******************** Bits definition for RTC_BKP5R register ****************/
|
|
|
5843 #define RTC_BKP5R ((uint32_t)0xFFFFFFFFU)
|
|
|
5844
|
|
|
5845 /******************** Bits definition for RTC_BKP6R register ****************/
|
|
|
5846 #define RTC_BKP6R ((uint32_t)0xFFFFFFFFU)
|
|
|
5847
|
|
|
5848 /******************** Bits definition for RTC_BKP7R register ****************/
|
|
|
5849 #define RTC_BKP7R ((uint32_t)0xFFFFFFFFU)
|
|
|
5850
|
|
|
5851 /******************** Bits definition for RTC_BKP8R register ****************/
|
|
|
5852 #define RTC_BKP8R ((uint32_t)0xFFFFFFFFU)
|
|
|
5853
|
|
|
5854 /******************** Bits definition for RTC_BKP9R register ****************/
|
|
|
5855 #define RTC_BKP9R ((uint32_t)0xFFFFFFFFU)
|
|
|
5856
|
|
|
5857 /******************** Bits definition for RTC_BKP10R register ***************/
|
|
|
5858 #define RTC_BKP10R ((uint32_t)0xFFFFFFFFU)
|
|
|
5859
|
|
|
5860 /******************** Bits definition for RTC_BKP11R register ***************/
|
|
|
5861 #define RTC_BKP11R ((uint32_t)0xFFFFFFFFU)
|
|
|
5862
|
|
|
5863 /******************** Bits definition for RTC_BKP12R register ***************/
|
|
|
5864 #define RTC_BKP12R ((uint32_t)0xFFFFFFFFU)
|
|
|
5865
|
|
|
5866 /******************** Bits definition for RTC_BKP13R register ***************/
|
|
|
5867 #define RTC_BKP13R ((uint32_t)0xFFFFFFFFU)
|
|
|
5868
|
|
|
5869 /******************** Bits definition for RTC_BKP14R register ***************/
|
|
|
5870 #define RTC_BKP14R ((uint32_t)0xFFFFFFFFU)
|
|
|
5871
|
|
|
5872 /******************** Bits definition for RTC_BKP15R register ***************/
|
|
|
5873 #define RTC_BKP15R ((uint32_t)0xFFFFFFFFU)
|
|
|
5874
|
|
|
5875 /******************** Bits definition for RTC_BKP16R register ***************/
|
|
|
5876 #define RTC_BKP16R ((uint32_t)0xFFFFFFFFU)
|
|
|
5877
|
|
|
5878 /******************** Bits definition for RTC_BKP17R register ***************/
|
|
|
5879 #define RTC_BKP17R ((uint32_t)0xFFFFFFFFU)
|
|
|
5880
|
|
|
5881 /******************** Bits definition for RTC_BKP18R register ***************/
|
|
|
5882 #define RTC_BKP18R ((uint32_t)0xFFFFFFFFU)
|
|
|
5883
|
|
|
5884 /******************** Bits definition for RTC_BKP19R register ***************/
|
|
|
5885 #define RTC_BKP19R ((uint32_t)0xFFFFFFFFU)
|
|
|
5886
|
|
|
5887 /******************** Bits definition for RTC_BKP20R register ***************/
|
|
|
5888 #define RTC_BKP20R ((uint32_t)0xFFFFFFFFU)
|
|
|
5889
|
|
|
5890 /******************** Bits definition for RTC_BKP21R register ***************/
|
|
|
5891 #define RTC_BKP21R ((uint32_t)0xFFFFFFFFU)
|
|
|
5892
|
|
|
5893 /******************** Bits definition for RTC_BKP22R register ***************/
|
|
|
5894 #define RTC_BKP22R ((uint32_t)0xFFFFFFFFU)
|
|
|
5895
|
|
|
5896 /******************** Bits definition for RTC_BKP23R register ***************/
|
|
|
5897 #define RTC_BKP23R ((uint32_t)0xFFFFFFFFU)
|
|
|
5898
|
|
|
5899 /******************** Bits definition for RTC_BKP24R register ***************/
|
|
|
5900 #define RTC_BKP24R ((uint32_t)0xFFFFFFFFU)
|
|
|
5901
|
|
|
5902 /******************** Bits definition for RTC_BKP25R register ***************/
|
|
|
5903 #define RTC_BKP25R ((uint32_t)0xFFFFFFFFU)
|
|
|
5904
|
|
|
5905 /******************** Bits definition for RTC_BKP26R register ***************/
|
|
|
5906 #define RTC_BKP26R ((uint32_t)0xFFFFFFFFU)
|
|
|
5907
|
|
|
5908 /******************** Bits definition for RTC_BKP27R register ***************/
|
|
|
5909 #define RTC_BKP27R ((uint32_t)0xFFFFFFFFU)
|
|
|
5910
|
|
|
5911 /******************** Bits definition for RTC_BKP28R register ***************/
|
|
|
5912 #define RTC_BKP28R ((uint32_t)0xFFFFFFFFU)
|
|
|
5913
|
|
|
5914 /******************** Bits definition for RTC_BKP29R register ***************/
|
|
|
5915 #define RTC_BKP29R ((uint32_t)0xFFFFFFFFU)
|
|
|
5916
|
|
|
5917 /******************** Bits definition for RTC_BKP30R register ***************/
|
|
|
5918 #define RTC_BKP30R ((uint32_t)0xFFFFFFFFU)
|
|
|
5919
|
|
|
5920 /******************** Bits definition for RTC_BKP31R register ***************/
|
|
|
5921 #define RTC_BKP31R ((uint32_t)0xFFFFFFFFU)
|
|
|
5922
|
|
|
5923 /******************** Number of backup registers ******************************/
|
|
|
5924 #define RTC_BKP_NUMBER 32U
|
|
|
5925
|
|
|
5926 /******************************************************************************/
|
|
|
5927 /* */
|
|
|
5928 /* Serial Audio Interface */
|
|
|
5929 /* */
|
|
|
5930 /******************************************************************************/
|
|
|
5931 /******************** Bit definition for SAI_GCR register *******************/
|
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|
5932 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003U) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
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|
5933 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
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5934 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
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5935
|
|
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5936 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030U) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
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5937 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
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|
|
5938 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
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|
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5939
|
|
|
5940 /******************* Bit definition for SAI_xCR1 register *******************/
|
|
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5941 #define SAI_xCR1_MODE ((uint32_t)0x00000003U) /*!<MODE[1:0] bits (Audio Block Mode) */
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5942 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
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|
5943 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
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5944
|
|
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5945 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000CU) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
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5946 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
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5947 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
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|
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5948
|
|
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5949 #define SAI_xCR1_DS ((uint32_t)0x000000E0U) /*!<DS[1:0] bits (Data Size) */
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5950 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
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5951 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
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5952 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
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5953
|
|
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5954 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100U) /*!<LSB First Configuration */
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5955 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200U) /*!<ClocK STRobing edge */
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5956
|
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5957 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00U) /*!<SYNCEN[1:0](SYNChronization ENable) */
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5958 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
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5959 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
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5960
|
|
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5961 #define SAI_xCR1_MONO ((uint32_t)0x00001000U) /*!<Mono mode */
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5962 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000U) /*!<Output Drive */
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5963 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000U) /*!<Audio Block enable */
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|
5964 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000U) /*!<DMA enable */
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5965 #define SAI_xCR1_NODIV ((uint32_t)0x00080000U) /*!<No Divider Configuration */
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|
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5966
|
|
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5967 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000U) /*!<MCKDIV[3:0] (Master ClocK Divider) */
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|
|
5968 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
|
|
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5969 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
|
|
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5970 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
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|
|
5971 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000U) /*!<Bit 3 */
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|
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5972
|
|
|
5973 /******************* Bit definition for SAI_xCR2 register *******************/
|
|
|
5974 #define SAI_xCR2_FTH ((uint32_t)0x00000007U) /*!<FTH[2:0](Fifo THreshold) */
|
|
|
5975 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
5976 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
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|
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5977 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
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5978
|
|
|
5979 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008U) /*!<Fifo FLUSH */
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|
|
5980 #define SAI_xCR2_TRIS ((uint32_t)0x00000010U) /*!<TRIState Management on data line */
|
|
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5981 #define SAI_xCR2_MUTE ((uint32_t)0x00000020U) /*!<Mute mode */
|
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|
5982 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040U) /*!<Muate value */
|
|
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5983
|
|
|
5984
|
|
|
5985 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80U) /*!<MUTECNT[5:0] (MUTE counter) */
|
|
|
5986 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
|
|
|
5987 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
|
|
|
5988 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200U) /*!<Bit 2 */
|
|
|
5989 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400U) /*!<Bit 3 */
|
|
|
5990 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800U) /*!<Bit 4 */
|
|
|
5991 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000U) /*!<Bit 5 */
|
|
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5992
|
|
|
5993 #define SAI_xCR2_CPL ((uint32_t)0x00002000U) /*!<CPL mode */
|
|
|
5994 #define SAI_xCR2_COMP ((uint32_t)0x0000C000U) /*!<COMP[1:0] (Companding mode) */
|
|
|
5995 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
|
|
|
5996 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
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|
|
5997
|
|
|
5998
|
|
|
5999 /****************** Bit definition for SAI_xFRCR register *******************/
|
|
|
6000 #define SAI_xFRCR_FRL ((uint32_t)0x000000FFU) /*!<FRL[7:0](Frame length) */
|
|
|
6001 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6002 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6003 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
6004 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
6005 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
6006 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
6007 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
6008 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
|
|
|
6009
|
|
|
6010 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00U) /*!<FRL[6:0] (Frame synchronization active level length) */
|
|
|
6011 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
6012 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6013 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
6014 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
6015 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
6016 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
|
|
|
6017 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
|
|
|
6018
|
|
|
6019 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000U) /*!< Frame Synchronization Definition */
|
|
|
6020 #define SAI_xFRCR_FSPOL ((uint32_t)0x00020000U) /*!<Frame Synchronization POLarity */
|
|
|
6021 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000U) /*!<Frame Synchronization OFFset */
|
|
|
6022
|
|
|
6023 /****************** Bit definition for SAI_xSLOTR register *******************/
|
|
|
6024 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001FU) /*!<FRL[4:0](First Bit Offset) */
|
|
|
6025 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6026 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6027 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
6028 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
6029 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
6030
|
|
|
6031 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0U) /*!<SLOTSZ[1:0] (Slot size) */
|
|
|
6032 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
|
|
|
6033 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
|
|
|
6034
|
|
|
6035 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00U) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
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|
|
6036 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
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|
|
6037 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6038 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
6039 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
6040
|
|
|
6041 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000U) /*!<SLOTEN[15:0] (Slot Enable) */
|
|
|
6042
|
|
|
6043 /******************* Bit definition for SAI_xIMR register *******************/
|
|
|
6044 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001U) /*!<Overrun underrun interrupt enable */
|
|
|
6045 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002U) /*!<Mute detection interrupt enable */
|
|
|
6046 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004U) /*!<Wrong Clock Configuration interrupt enable */
|
|
|
6047 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008U) /*!<FIFO request interrupt enable */
|
|
|
6048 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010U) /*!<Codec not ready interrupt enable */
|
|
|
6049 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020U) /*!<Anticipated frame synchronization detection interrupt enable */
|
|
|
6050 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040U) /*!<Late frame synchronization detection interrupt enable */
|
|
|
6051
|
|
|
6052 /******************** Bit definition for SAI_xSR register *******************/
|
|
|
6053 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001U) /*!<Overrun underrun */
|
|
|
6054 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002U) /*!<Mute detection */
|
|
|
6055 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004U) /*!<Wrong Clock Configuration */
|
|
|
6056 #define SAI_xSR_FREQ ((uint32_t)0x00000008U) /*!<FIFO request */
|
|
|
6057 #define SAI_xSR_CNRDY ((uint32_t)0x00000010U) /*!<Codec not ready */
|
|
|
6058 #define SAI_xSR_AFSDET ((uint32_t)0x00000020U) /*!<Anticipated frame synchronization detection */
|
|
|
6059 #define SAI_xSR_LFSDET ((uint32_t)0x00000040U) /*!<Late frame synchronization detection */
|
|
|
6060
|
|
|
6061 #define SAI_xSR_FLVL ((uint32_t)0x00070000U) /*!<FLVL[2:0] (FIFO Level Threshold) */
|
|
|
6062 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
6063 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
6064 #define SAI_xSR_FLVL_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
6065
|
|
|
6066 /****************** Bit definition for SAI_xCLRFR register ******************/
|
|
|
6067 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001U) /*!<Clear Overrun underrun */
|
|
|
6068 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002U) /*!<Clear Mute detection */
|
|
|
6069 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004U) /*!<Clear Wrong Clock Configuration */
|
|
|
6070 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008U) /*!<Clear FIFO request */
|
|
|
6071 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010U) /*!<Clear Codec not ready */
|
|
|
6072 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020U) /*!<Clear Anticipated frame synchronization detection */
|
|
|
6073 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040U) /*!<Clear Late frame synchronization detection */
|
|
|
6074
|
|
|
6075 /****************** Bit definition for SAI_xDR register ******************/
|
|
|
6076 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFFU)
|
|
|
6077
|
|
|
6078 /******************************************************************************/
|
|
|
6079 /* */
|
|
|
6080 /* SDMMC Interface */
|
|
|
6081 /* */
|
|
|
6082 /******************************************************************************/
|
|
|
6083 /****************** Bit definition for SDMMC_POWER register ******************/
|
|
|
6084 #define SDMMC_POWER_PWRCTRL ((uint8_t)0x03U) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
|
|
|
6085 #define SDMMC_POWER_PWRCTRL_0 ((uint8_t)0x01U) /*!<Bit 0 */
|
|
|
6086 #define SDMMC_POWER_PWRCTRL_1 ((uint8_t)0x02U) /*!<Bit 1 */
|
|
|
6087
|
|
|
6088 /****************** Bit definition for SDMMC_CLKCR register ******************/
|
|
|
6089 #define SDMMC_CLKCR_CLKDIV ((uint16_t)0x00FFU) /*!<Clock divide factor */
|
|
|
6090 #define SDMMC_CLKCR_CLKEN ((uint16_t)0x0100U) /*!<Clock enable bit */
|
|
|
6091 #define SDMMC_CLKCR_PWRSAV ((uint16_t)0x0200U) /*!<Power saving configuration bit */
|
|
|
6092 #define SDMMC_CLKCR_BYPASS ((uint16_t)0x0400U) /*!<Clock divider bypass enable bit */
|
|
|
6093
|
|
|
6094 #define SDMMC_CLKCR_WIDBUS ((uint16_t)0x1800U) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
|
|
|
6095 #define SDMMC_CLKCR_WIDBUS_0 ((uint16_t)0x0800U) /*!<Bit 0 */
|
|
|
6096 #define SDMMC_CLKCR_WIDBUS_1 ((uint16_t)0x1000U) /*!<Bit 1 */
|
|
|
6097
|
|
|
6098 #define SDMMC_CLKCR_NEGEDGE ((uint16_t)0x2000U) /*!<SDMMC_CK dephasing selection bit */
|
|
|
6099 #define SDMMC_CLKCR_HWFC_EN ((uint16_t)0x4000U) /*!<HW Flow Control enable */
|
|
|
6100
|
|
|
6101 /******************* Bit definition for SDMMC_ARG register *******************/
|
|
|
6102 #define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFFU) /*!<Command argument */
|
|
|
6103
|
|
|
6104 /******************* Bit definition for SDMMC_CMD register *******************/
|
|
|
6105 #define SDMMC_CMD_CMDINDEX ((uint16_t)0x003FU) /*!<Command Index */
|
|
|
6106
|
|
|
6107 #define SDMMC_CMD_WAITRESP ((uint16_t)0x00C0U) /*!<WAITRESP[1:0] bits (Wait for response bits) */
|
|
|
6108 #define SDMMC_CMD_WAITRESP_0 ((uint16_t)0x0040U) /*!< Bit 0 */
|
|
|
6109 #define SDMMC_CMD_WAITRESP_1 ((uint16_t)0x0080U) /*!< Bit 1 */
|
|
|
6110
|
|
|
6111 #define SDMMC_CMD_WAITINT ((uint16_t)0x0100U) /*!<CPSM Waits for Interrupt Request */
|
|
|
6112 #define SDMMC_CMD_WAITPEND ((uint16_t)0x0200U) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
|
|
|
6113 #define SDMMC_CMD_CPSMEN ((uint16_t)0x0400U) /*!<Command path state machine (CPSM) Enable bit */
|
|
|
6114 #define SDMMC_CMD_SDIOSUSPEND ((uint16_t)0x0800U) /*!<SD I/O suspend command */
|
|
|
6115
|
|
|
6116 /***************** Bit definition for SDMMC_RESPCMD register *****************/
|
|
|
6117 #define SDMMC_RESPCMD_RESPCMD ((uint8_t)0x3FU) /*!<Response command index */
|
|
|
6118
|
|
|
6119 /****************** Bit definition for SDMMC_RESP0 register ******************/
|
|
|
6120 #define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
6121
|
|
|
6122 /****************** Bit definition for SDMMC_RESP1 register ******************/
|
|
|
6123 #define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
6124
|
|
|
6125 /****************** Bit definition for SDMMC_RESP2 register ******************/
|
|
|
6126 #define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
6127
|
|
|
6128 /****************** Bit definition for SDMMC_RESP3 register ******************/
|
|
|
6129 #define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
6130
|
|
|
6131 /****************** Bit definition for SDMMC_RESP4 register ******************/
|
|
|
6132 #define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
6133
|
|
|
6134 /****************** Bit definition for SDMMC_DTIMER register *****************/
|
|
|
6135 #define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFFU) /*!<Data timeout period. */
|
|
|
6136
|
|
|
6137 /****************** Bit definition for SDMMC_DLEN register *******************/
|
|
|
6138 #define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFFU) /*!<Data length value */
|
|
|
6139
|
|
|
6140 /****************** Bit definition for SDMMC_DCTRL register ******************/
|
|
|
6141 #define SDMMC_DCTRL_DTEN ((uint16_t)0x0001U) /*!<Data transfer enabled bit */
|
|
|
6142 #define SDMMC_DCTRL_DTDIR ((uint16_t)0x0002U) /*!<Data transfer direction selection */
|
|
|
6143 #define SDMMC_DCTRL_DTMODE ((uint16_t)0x0004U) /*!<Data transfer mode selection */
|
|
|
6144 #define SDMMC_DCTRL_DMAEN ((uint16_t)0x0008U) /*!<DMA enabled bit */
|
|
|
6145
|
|
|
6146 #define SDMMC_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0U) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
|
|
|
6147 #define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010U) /*!<Bit 0 */
|
|
|
6148 #define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020U) /*!<Bit 1 */
|
|
|
6149 #define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040U) /*!<Bit 2 */
|
|
|
6150 #define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080U) /*!<Bit 3 */
|
|
|
6151
|
|
|
6152 #define SDMMC_DCTRL_RWSTART ((uint16_t)0x0100U) /*!<Read wait start */
|
|
|
6153 #define SDMMC_DCTRL_RWSTOP ((uint16_t)0x0200U) /*!<Read wait stop */
|
|
|
6154 #define SDMMC_DCTRL_RWMOD ((uint16_t)0x0400U) /*!<Read wait mode */
|
|
|
6155 #define SDMMC_DCTRL_SDIOEN ((uint16_t)0x0800U) /*!<SD I/O enable functions */
|
|
|
6156
|
|
|
6157 /****************** Bit definition for SDMMC_DCOUNT register *****************/
|
|
|
6158 #define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFFU) /*!<Data count value */
|
|
|
6159
|
|
|
6160 /****************** Bit definition for SDMMC_STA register ********************/
|
|
|
6161 #define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001U) /*!<Command response received (CRC check failed) */
|
|
|
6162 #define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002U) /*!<Data block sent/received (CRC check failed) */
|
|
|
6163 #define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004U) /*!<Command response timeout */
|
|
|
6164 #define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008U) /*!<Data timeout */
|
|
|
6165 #define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010U) /*!<Transmit FIFO underrun error */
|
|
|
6166 #define SDMMC_STA_RXOVERR ((uint32_t)0x00000020U) /*!<Received FIFO overrun error */
|
|
|
6167 #define SDMMC_STA_CMDREND ((uint32_t)0x00000040U) /*!<Command response received (CRC check passed) */
|
|
|
6168 #define SDMMC_STA_CMDSENT ((uint32_t)0x00000080U) /*!<Command sent (no response required) */
|
|
|
6169 #define SDMMC_STA_DATAEND ((uint32_t)0x00000100U) /*!<Data end (data counter, SDIDCOUNT, is zero) */
|
|
|
6170 #define SDMMC_STA_STBITERR ((uint32_t)0x00000200U) /*!<Start bit not detected on all data signals in wide bus mode */
|
|
|
6171 #define SDMMC_STA_DBCKEND ((uint32_t)0x00000400U) /*!<Data block sent/received (CRC check passed) */
|
|
|
6172 #define SDMMC_STA_CMDACT ((uint32_t)0x00000800U) /*!<Command transfer in progress */
|
|
|
6173 #define SDMMC_STA_TXACT ((uint32_t)0x00001000U) /*!<Data transmit in progress */
|
|
|
6174 #define SDMMC_STA_RXACT ((uint32_t)0x00002000U) /*!<Data receive in progress */
|
|
|
6175 #define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000U) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
|
|
|
6176 #define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000U) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
|
|
|
6177 #define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000U) /*!<Transmit FIFO full */
|
|
|
6178 #define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000U) /*!<Receive FIFO full */
|
|
|
6179 #define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000U) /*!<Transmit FIFO empty */
|
|
|
6180 #define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000U) /*!<Receive FIFO empty */
|
|
|
6181 #define SDMMC_STA_TXDAVL ((uint32_t)0x00100000U) /*!<Data available in transmit FIFO */
|
|
|
6182 #define SDMMC_STA_RXDAVL ((uint32_t)0x00200000U) /*!<Data available in receive FIFO */
|
|
|
6183 #define SDMMC_STA_SDIOIT ((uint32_t)0x00400000U) /*!<SDIO interrupt received */
|
|
|
6184
|
|
|
6185 /******************* Bit definition for SDMMC_ICR register *******************/
|
|
|
6186 #define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001U) /*!<CCRCFAIL flag clear bit */
|
|
|
6187 #define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002U) /*!<DCRCFAIL flag clear bit */
|
|
|
6188 #define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004U) /*!<CTIMEOUT flag clear bit */
|
|
|
6189 #define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008U) /*!<DTIMEOUT flag clear bit */
|
|
|
6190 #define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010U) /*!<TXUNDERR flag clear bit */
|
|
|
6191 #define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020U) /*!<RXOVERR flag clear bit */
|
|
|
6192 #define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040U) /*!<CMDREND flag clear bit */
|
|
|
6193 #define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080U) /*!<CMDSENT flag clear bit */
|
|
|
6194 #define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100U) /*!<DATAEND flag clear bit */
|
|
|
6195 #define SDMMC_ICR_STBITERRC ((uint32_t)0x00000200U) /*!<STBITERR flag clear bit */
|
|
|
6196 #define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400U) /*!<DBCKEND flag clear bit */
|
|
|
6197 #define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000U) /*!<SDIOIT flag clear bit */
|
|
|
6198
|
|
|
6199 /****************** Bit definition for SDMMC_MASK register *******************/
|
|
|
6200 #define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001U) /*!<Command CRC Fail Interrupt Enable */
|
|
|
6201 #define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002U) /*!<Data CRC Fail Interrupt Enable */
|
|
|
6202 #define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004U) /*!<Command TimeOut Interrupt Enable */
|
|
|
6203 #define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008U) /*!<Data TimeOut Interrupt Enable */
|
|
|
6204 #define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010U) /*!<Tx FIFO UnderRun Error Interrupt Enable */
|
|
|
6205 #define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020U) /*!<Rx FIFO OverRun Error Interrupt Enable */
|
|
|
6206 #define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040U) /*!<Command Response Received Interrupt Enable */
|
|
|
6207 #define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080U) /*!<Command Sent Interrupt Enable */
|
|
|
6208 #define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100U) /*!<Data End Interrupt Enable */
|
|
|
6209 #define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400U) /*!<Data Block End Interrupt Enable */
|
|
|
6210 #define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800U) /*!<CCommand Acting Interrupt Enable */
|
|
|
6211 #define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000U) /*!<Data Transmit Acting Interrupt Enable */
|
|
|
6212 #define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000U) /*!<Data receive acting interrupt enabled */
|
|
|
6213 #define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000U) /*!<Tx FIFO Half Empty interrupt Enable */
|
|
|
6214 #define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000U) /*!<Rx FIFO Half Full interrupt Enable */
|
|
|
6215 #define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000U) /*!<Tx FIFO Full interrupt Enable */
|
|
|
6216 #define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000U) /*!<Rx FIFO Full interrupt Enable */
|
|
|
6217 #define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000U) /*!<Tx FIFO Empty interrupt Enable */
|
|
|
6218 #define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000U) /*!<Rx FIFO Empty interrupt Enable */
|
|
|
6219 #define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000U) /*!<Data available in Tx FIFO interrupt Enable */
|
|
|
6220 #define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000U) /*!<Data available in Rx FIFO interrupt Enable */
|
|
|
6221 #define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000U) /*!<SDIO Mode Interrupt Received interrupt Enable */
|
|
|
6222
|
|
|
6223 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
|
|
|
6224 #define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFFU) /*!<Remaining number of words to be written to or read from the FIFO */
|
|
|
6225
|
|
|
6226 /****************** Bit definition for SDMMC_FIFO register *******************/
|
|
|
6227 #define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFFU) /*!<Receive and transmit FIFO data */
|
|
|
6228
|
|
|
6229 /******************************************************************************/
|
|
|
6230 /* */
|
|
|
6231 /* Serial Peripheral Interface (SPI) */
|
|
|
6232 /* */
|
|
|
6233 /******************************************************************************/
|
|
|
6234 /******************* Bit definition for SPI_CR1 register ********************/
|
|
|
6235 #define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!<Clock Phase */
|
|
|
6236 #define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!<Clock Polarity */
|
|
|
6237 #define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!<Master Selection */
|
|
|
6238
|
|
|
6239 #define SPI_CR1_BR ((uint32_t)0x00000038U) /*!<BR[2:0] bits (Baud Rate Control) */
|
|
|
6240 #define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
|
|
|
6241 #define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
|
|
|
6242 #define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
|
|
|
6243
|
|
|
6244 #define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!<SPI Enable */
|
|
|
6245 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!<Frame Format */
|
|
|
6246 #define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!<Internal slave select */
|
|
|
6247 #define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!<Software slave management */
|
|
|
6248 #define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!<Receive only */
|
|
|
6249 #define SPI_CR1_CRCL ((uint32_t)0x00000800U) /*!< CRC Length */
|
|
|
6250 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!<Transmit CRC next */
|
|
|
6251 #define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!<Hardware CRC calculation enable */
|
|
|
6252 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!<Output enable in bidirectional mode */
|
|
|
6253 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!<Bidirectional data mode enable */
|
|
|
6254
|
|
|
6255 /******************* Bit definition for SPI_CR2 register ********************/
|
|
|
6256 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
|
|
|
6257 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
|
|
|
6258 #define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
|
|
|
6259 #define SPI_CR2_NSSP ((uint32_t)0x00000008U) /*!< NSS pulse management Enable */
|
|
|
6260 #define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */
|
|
|
6261 #define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
|
|
|
6262 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
|
|
|
6263 #define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
|
|
|
6264 #define SPI_CR2_DS ((uint32_t)0x00000F00U) /*!< DS[3:0] Data Size */
|
|
|
6265 #define SPI_CR2_DS_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
6266 #define SPI_CR2_DS_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
6267 #define SPI_CR2_DS_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
|
|
|
6268 #define SPI_CR2_DS_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
|
|
|
6269 #define SPI_CR2_FRXTH ((uint32_t)0x00001000U) /*!< FIFO reception Threshold */
|
|
|
6270 #define SPI_CR2_LDMARX ((uint32_t)0x00002000U) /*!< Last DMA transfer for reception */
|
|
|
6271 #define SPI_CR2_LDMATX ((uint32_t)0x00004000U) /*!< Last DMA transfer for transmission */
|
|
|
6272
|
|
|
6273 /******************** Bit definition for SPI_SR register ********************/
|
|
|
6274 #define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
|
|
|
6275 #define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
|
|
|
6276 #define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
|
|
|
6277 #define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
|
|
|
6278 #define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
|
|
|
6279 #define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
|
|
|
6280 #define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
|
|
|
6281 #define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
|
|
|
6282 #define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */
|
|
|
6283 #define SPI_SR_FRLVL ((uint32_t)0x00000600U) /*!< FIFO Reception Level */
|
|
|
6284 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
|
|
|
6285 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
|
|
|
6286 #define SPI_SR_FTLVL ((uint32_t)0x00001800U) /*!< FIFO Transmission Level */
|
|
|
6287 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
|
|
|
6288 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
|
|
|
6289
|
|
|
6290 /******************** Bit definition for SPI_DR register ********************/
|
|
|
6291 #define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!<Data Register */
|
|
|
6292
|
|
|
6293 /******************* Bit definition for SPI_CRCPR register ******************/
|
|
|
6294 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!<CRC polynomial register */
|
|
|
6295
|
|
|
6296 /****************** Bit definition for SPI_RXCRCR register ******************/
|
|
|
6297 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!<Rx CRC Register */
|
|
|
6298
|
|
|
6299 /****************** Bit definition for SPI_TXCRCR register ******************/
|
|
|
6300 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!<Tx CRC Register */
|
|
|
6301
|
|
|
6302 /******************************************************************************/
|
|
|
6303 /* */
|
|
|
6304 /* QUADSPI */
|
|
|
6305 /* */
|
|
|
6306 /******************************************************************************/
|
|
|
6307 /***************** Bit definition for QUADSPI_CR register *******************/
|
|
|
6308 #define QUADSPI_CR_EN ((uint32_t)0x00000001U) /*!< Enable */
|
|
|
6309 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002U) /*!< Abort request */
|
|
|
6310 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004U) /*!< DMA Enable */
|
|
|
6311 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008U) /*!< Timeout Counter Enable */
|
|
|
6312 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010U) /*!< Sample Shift */
|
|
|
6313 #define QUADSPI_CR_DFM ((uint32_t)0x00000040U) /*!< Dual-flash mode */
|
|
|
6314 #define QUADSPI_CR_FSEL ((uint32_t)0x00000080U) /*!< Flash memory selection */
|
|
|
6315 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00U) /*!< FTHRES[3:0] FIFO Level */
|
|
|
6316 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000U) /*!< Transfer Error Interrupt Enable */
|
|
|
6317 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000U) /*!< Transfer Complete Interrupt Enable */
|
|
|
6318 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000U) /*!< FIFO Threshold Interrupt Enable */
|
|
|
6319 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000U) /*!< Status Match Interrupt Enable */
|
|
|
6320 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000U) /*!< TimeOut Interrupt Enable */
|
|
|
6321 #define QUADSPI_CR_APMS ((uint32_t)0x00400000U) /*!< Automatic Polling Mode Stop */
|
|
|
6322 #define QUADSPI_CR_PMM ((uint32_t)0x00800000U) /*!< Polling Match Mode */
|
|
|
6323 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000U) /*!< PRESCALER[7:0] Clock prescaler */
|
|
|
6324
|
|
|
6325 /***************** Bit definition for QUADSPI_DCR register ******************/
|
|
|
6326 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001U) /*!< Mode 0 / Mode 3 */
|
|
|
6327 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700U) /*!< CSHT[2:0]: ChipSelect High Time */
|
|
|
6328 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
6329 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
6330 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
|
|
|
6331 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000U) /*!< FSIZE[4:0]: Flash Size */
|
|
|
6332
|
|
|
6333 /****************** Bit definition for QUADSPI_SR register *******************/
|
|
|
6334 #define QUADSPI_SR_TEF ((uint32_t)0x00000001U) /*!< Transfer Error Flag */
|
|
|
6335 #define QUADSPI_SR_TCF ((uint32_t)0x00000002U) /*!< Transfer Complete Flag */
|
|
|
6336 #define QUADSPI_SR_FTF ((uint32_t)0x00000004U) /*!< FIFO Threshlod Flag */
|
|
|
6337 #define QUADSPI_SR_SMF ((uint32_t)0x00000008U) /*!< Status Match Flag */
|
|
|
6338 #define QUADSPI_SR_TOF ((uint32_t)0x00000010U) /*!< Timeout Flag */
|
|
|
6339 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020U) /*!< Busy */
|
|
|
6340 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00U) /*!< FIFO Threshlod Flag */
|
|
|
6341
|
|
|
6342 /****************** Bit definition for QUADSPI_FCR register ******************/
|
|
|
6343 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001U) /*!< Clear Transfer Error Flag */
|
|
|
6344 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002U) /*!< Clear Transfer Complete Flag */
|
|
|
6345 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008U) /*!< Clear Status Match Flag */
|
|
|
6346 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010U) /*!< Clear Timeout Flag */
|
|
|
6347
|
|
|
6348 /****************** Bit definition for QUADSPI_DLR register ******************/
|
|
|
6349 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFFU) /*!< DL[31:0]: Data Length */
|
|
|
6350
|
|
|
6351 /****************** Bit definition for QUADSPI_CCR register ******************/
|
|
|
6352 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FFU) /*!< INSTRUCTION[7:0]: Instruction */
|
|
|
6353 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300U) /*!< IMODE[1:0]: Instruction Mode */
|
|
|
6354 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
6355 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
6356 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00U) /*!< ADMODE[1:0]: Address Mode */
|
|
|
6357 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
|
|
|
6358 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
|
|
|
6359 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000U) /*!< ADSIZE[1:0]: Address Size */
|
|
|
6360 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
|
|
|
6361 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
|
|
|
6362 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000U) /*!< ABMODE[1:0]: Alternate Bytes Mode */
|
|
|
6363 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000U) /*!< Bit 0 */
|
|
|
6364 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000U) /*!< Bit 1 */
|
|
|
6365 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000U) /*!< ABSIZE[1:0]: Instruction Mode */
|
|
|
6366 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
|
|
|
6367 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
|
|
|
6368 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000U) /*!< DCYC[4:0]: Dummy Cycles */
|
|
|
6369 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000U) /*!< DMODE[1:0]: Data Mode */
|
|
|
6370 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
|
|
|
6371 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
|
|
|
6372 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000U) /*!< FMODE[1:0]: Functional Mode */
|
|
|
6373 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
|
|
|
6374 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
|
|
|
6375 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000U) /*!< SIOO: Send Instruction Only Once Mode */
|
|
|
6376 #define QUADSPI_CCR_DHHC ((uint32_t)0x40000000U) /*!< DHHC: DDR hold */
|
|
|
6377 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000U) /*!< DDRM: Double Data Rate Mode */
|
|
|
6378
|
|
|
6379 /****************** Bit definition for QUADSPI_AR register *******************/
|
|
|
6380 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFFU) /*!< ADDRESS[31:0]: Address */
|
|
|
6381
|
|
|
6382 /****************** Bit definition for QUADSPI_ABR register ******************/
|
|
|
6383 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFFU) /*!< ALTERNATE[31:0]: Alternate Bytes */
|
|
|
6384
|
|
|
6385 /****************** Bit definition for QUADSPI_DR register *******************/
|
|
|
6386 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFFU) /*!< DATA[31:0]: Data */
|
|
|
6387
|
|
|
6388 /****************** Bit definition for QUADSPI_PSMKR register ****************/
|
|
|
6389 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFFU) /*!< MASK[31:0]: Status Mask */
|
|
|
6390
|
|
|
6391 /****************** Bit definition for QUADSPI_PSMAR register ****************/
|
|
|
6392 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFFU) /*!< MATCH[31:0]: Status Match */
|
|
|
6393
|
|
|
6394 /****************** Bit definition for QUADSPI_PIR register *****************/
|
|
|
6395 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFFU) /*!< INTERVAL[15:0]: Polling Interval */
|
|
|
6396
|
|
|
6397 /****************** Bit definition for QUADSPI_LPTR register *****************/
|
|
|
6398 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< TIMEOUT[15:0]: Timeout period */
|
|
|
6399
|
|
|
6400 /******************************************************************************/
|
|
|
6401 /* */
|
|
|
6402 /* SYSCFG */
|
|
|
6403 /* */
|
|
|
6404 /******************************************************************************/
|
|
|
6405 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
|
|
|
6406 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
|
|
|
6407 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001U)
|
|
|
6408 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002U)
|
|
|
6409 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004U)
|
|
|
6410
|
|
|
6411
|
|
|
6412
|
|
|
6413 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
|
|
|
6414 #define SYSCFG_CFGR1_FWDIS ((uint32_t)0x00000001U) /*!< FIREWALL access enable*/
|
|
|
6415 #define SYSCFG_CFGR1_BOOSTEN ((uint32_t)0x00000100U) /*!< I/O analog switch voltage booster enable */
|
|
|
6416 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000U) /*!< I2C PB6 Fast mode plus */
|
|
|
6417 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000U) /*!< I2C PB7 Fast mode plus */
|
|
|
6418 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000U) /*!< I2C PB8 Fast mode plus */
|
|
|
6419 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000U) /*!< I2C PB9 Fast mode plus */
|
|
|
6420 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000U) /*!< I2C1 Fast mode plus */
|
|
|
6421 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000U) /*!< I2C2 Fast mode plus */
|
|
|
6422 #define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x00400000U) /*!< I2C3 Fast mode plus */
|
|
|
6423 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000U) /*!< Invalid operation Interrupt enable */
|
|
|
6424 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000U) /*!< Divide-by-zero Interrupt enable */
|
|
|
6425 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000U) /*!< Underflow Interrupt enable */
|
|
|
6426 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000U) /*!< Overflow Interrupt enable */
|
|
|
6427 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000U) /*!< Input denormal Interrupt enable */
|
|
|
6428 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
|
|
|
6429
|
|
|
6430 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
|
|
6431 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x00000007U) /*!<EXTI 0 configuration */
|
|
|
6432 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00000070U) /*!<EXTI 1 configuration */
|
|
|
6433 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000700U) /*!<EXTI 2 configuration */
|
|
|
6434 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x00007000U) /*!<EXTI 3 configuration */
|
|
|
6435 /**
|
|
|
6436 * @brief EXTI0 configuration
|
|
|
6437 */
|
|
|
6438 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!<PA[0] pin */
|
|
|
6439 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!<PB[0] pin */
|
|
|
6440 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!<PC[0] pin */
|
|
|
6441 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003U) /*!<PD[0] pin */
|
|
|
6442 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004U) /*!<PE[0] pin */
|
|
|
6443 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007U) /*!<PH[0] pin */
|
|
|
6444
|
|
|
6445
|
|
|
6446 /**
|
|
|
6447 * @brief EXTI1 configuration
|
|
|
6448 */
|
|
|
6449 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!<PA[1] pin */
|
|
|
6450 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!<PB[1] pin */
|
|
|
6451 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!<PC[1] pin */
|
|
|
6452 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030U) /*!<PD[1] pin */
|
|
|
6453 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040U) /*!<PE[1] pin */
|
|
|
6454 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070U) /*!<PH[1] pin */
|
|
|
6455
|
|
|
6456 /**
|
|
|
6457 * @brief EXTI2 configuration
|
|
|
6458 */
|
|
|
6459 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!<PA[2] pin */
|
|
|
6460 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!<PB[2] pin */
|
|
|
6461 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!<PC[2] pin */
|
|
|
6462 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!<PD[2] pin */
|
|
|
6463 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400U) /*!<PE[2] pin */
|
|
|
6464
|
|
|
6465
|
|
|
6466 /**
|
|
|
6467 * @brief EXTI3 configuration
|
|
|
6468 */
|
|
|
6469 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!<PA[3] pin */
|
|
|
6470 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!<PB[3] pin */
|
|
|
6471 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!<PC[3] pin */
|
|
|
6472 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000U) /*!<PD[3] pin */
|
|
|
6473 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000U) /*!<PE[3] pin */
|
|
|
6474 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00007000U) /*!<PH[3] pin */
|
|
|
6475
|
|
|
6476
|
|
|
6477 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
|
|
6478 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x00000007U) /*!<EXTI 4 configuration */
|
|
|
6479 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00000070U) /*!<EXTI 5 configuration */
|
|
|
6480 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000700U) /*!<EXTI 6 configuration */
|
|
|
6481 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x00007000U) /*!<EXTI 7 configuration */
|
|
|
6482 /**
|
|
|
6483 * @brief EXTI4 configuration
|
|
|
6484 */
|
|
|
6485 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!<PA[4] pin */
|
|
|
6486 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!<PB[4] pin */
|
|
|
6487 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!<PC[4] pin */
|
|
|
6488 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003U) /*!<PD[4] pin */
|
|
|
6489 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004U) /*!<PE[4] pin */
|
|
|
6490
|
|
|
6491 /**
|
|
|
6492 * @brief EXTI5 configuration
|
|
|
6493 */
|
|
|
6494 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!<PA[5] pin */
|
|
|
6495 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!<PB[5] pin */
|
|
|
6496 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!<PC[5] pin */
|
|
|
6497 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030U) /*!<PD[5] pin */
|
|
|
6498 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040U) /*!<PE[5] pin */
|
|
|
6499
|
|
|
6500 /**
|
|
|
6501 * @brief EXTI6 configuration
|
|
|
6502 */
|
|
|
6503 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!<PA[6] pin */
|
|
|
6504 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!<PB[6] pin */
|
|
|
6505 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!<PC[6] pin */
|
|
|
6506 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300U) /*!<PD[6] pin */
|
|
|
6507 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400U) /*!<PE[6] pin */
|
|
|
6508
|
|
|
6509 /**
|
|
|
6510 * @brief EXTI7 configuration
|
|
|
6511 */
|
|
|
6512 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!<PA[7] pin */
|
|
|
6513 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!<PB[7] pin */
|
|
|
6514 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!<PC[7] pin */
|
|
|
6515 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000U) /*!<PD[7] pin */
|
|
|
6516 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000U) /*!<PE[7] pin */
|
|
|
6517
|
|
|
6518
|
|
|
6519 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
|
|
6520 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x00000007U) /*!<EXTI 8 configuration */
|
|
|
6521 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00000070U) /*!<EXTI 9 configuration */
|
|
|
6522 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000700U) /*!<EXTI 10 configuration */
|
|
|
6523 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x00007000U) /*!<EXTI 11 configuration */
|
|
|
6524
|
|
|
6525 /**
|
|
|
6526 * @brief EXTI8 configuration
|
|
|
6527 */
|
|
|
6528 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!<PA[8] pin */
|
|
|
6529 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!<PB[8] pin */
|
|
|
6530 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!<PC[8] pin */
|
|
|
6531 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003U) /*!<PD[8] pin */
|
|
|
6532 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004U) /*!<PE[8] pin */
|
|
|
6533
|
|
|
6534 /**
|
|
|
6535 * @brief EXTI9 configuration
|
|
|
6536 */
|
|
|
6537 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!<PA[9] pin */
|
|
|
6538 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!<PB[9] pin */
|
|
|
6539 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!<PC[9] pin */
|
|
|
6540 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030U) /*!<PD[9] pin */
|
|
|
6541 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040U) /*!<PE[9] pin */
|
|
|
6542
|
|
|
6543 /**
|
|
|
6544 * @brief EXTI10 configuration
|
|
|
6545 */
|
|
|
6546 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!<PA[10] pin */
|
|
|
6547 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!<PB[10] pin */
|
|
|
6548 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!<PC[10] pin */
|
|
|
6549 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300U) /*!<PD[10] pin */
|
|
|
6550 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400U) /*!<PE[10] pin */
|
|
|
6551
|
|
|
6552 /**
|
|
|
6553 * @brief EXTI11 configuration
|
|
|
6554 */
|
|
|
6555 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!<PA[11] pin */
|
|
|
6556 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!<PB[11] pin */
|
|
|
6557 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!<PC[11] pin */
|
|
|
6558 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000U) /*!<PD[11] pin */
|
|
|
6559 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000U) /*!<PE[11] pin */
|
|
|
6560
|
|
|
6561 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
|
|
6562 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x00000007U) /*!<EXTI 12 configuration */
|
|
|
6563 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00000070U) /*!<EXTI 13 configuration */
|
|
|
6564 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000700U) /*!<EXTI 14 configuration */
|
|
|
6565 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x00007000U) /*!<EXTI 15 configuration */
|
|
|
6566 /**
|
|
|
6567 * @brief EXTI12 configuration
|
|
|
6568 */
|
|
|
6569 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!<PA[12] pin */
|
|
|
6570 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!<PB[12] pin */
|
|
|
6571 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!<PC[12] pin */
|
|
|
6572 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003U) /*!<PD[12] pin */
|
|
|
6573 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004U) /*!<PE[12] pin */
|
|
|
6574
|
|
|
6575 /**
|
|
|
6576 * @brief EXTI13 configuration
|
|
|
6577 */
|
|
|
6578 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!<PA[13] pin */
|
|
|
6579 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!<PB[13] pin */
|
|
|
6580 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!<PC[13] pin */
|
|
|
6581 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030U) /*!<PD[13] pin */
|
|
|
6582 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040U) /*!<PE[13] pin */
|
|
|
6583
|
|
|
6584 /**
|
|
|
6585 * @brief EXTI14 configuration
|
|
|
6586 */
|
|
|
6587 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!<PA[14] pin */
|
|
|
6588 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!<PB[14] pin */
|
|
|
6589 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!<PC[14] pin */
|
|
|
6590 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300U) /*!<PD[14] pin */
|
|
|
6591 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400U) /*!<PE[14] pin */
|
|
|
6592
|
|
|
6593 /**
|
|
|
6594 * @brief EXTI15 configuration
|
|
|
6595 */
|
|
|
6596 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!<PA[15] pin */
|
|
|
6597 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!<PB[15] pin */
|
|
|
6598 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!<PC[15] pin */
|
|
|
6599 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000U) /*!<PD[15] pin */
|
|
|
6600 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000U) /*!<PE[15] pin */
|
|
|
6601
|
|
|
6602 /****************** Bit definition for SYSCFG_SCSR register ****************/
|
|
|
6603 #define SYSCFG_SCSR_SRAM2ER ((uint32_t)0x00000001U) /*!< SRAM2 Erase Request */
|
|
|
6604 #define SYSCFG_SCSR_SRAM2BSY ((uint32_t)0x00000002U) /*!< SRAM2 Erase Ongoing */
|
|
|
6605
|
|
|
6606 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
|
|
|
6607 #define SYSCFG_CFGR2_CLL ((uint32_t)0x00000001U) /*!< Core Lockup Lock */
|
|
|
6608 #define SYSCFG_CFGR2_SPL ((uint32_t)0x00000002U) /*!< SRAM Parity Lock*/
|
|
|
6609 #define SYSCFG_CFGR2_PVDL ((uint32_t)0x00000004U) /*!< PVD Lock */
|
|
|
6610 #define SYSCFG_CFGR2_ECCL ((uint32_t)0x00000008U) /*!< ECC Lock*/
|
|
|
6611 #define SYSCFG_CFGR2_SPF ((uint32_t)0x00000100U) /*!< SRAM Parity Flag */
|
|
|
6612
|
|
|
6613 /****************** Bit definition for SYSCFG_SWPR register ****************/
|
|
|
6614 #define SYSCFG_SWPR_PAGE0 ((uint32_t)0x00000001U) /*!< SRAM2 Write protection page 0 */
|
|
|
6615 #define SYSCFG_SWPR_PAGE1 ((uint32_t)0x00000002U) /*!< SRAM2 Write protection page 1 */
|
|
|
6616 #define SYSCFG_SWPR_PAGE2 ((uint32_t)0x00000004U) /*!< SRAM2 Write protection page 2 */
|
|
|
6617 #define SYSCFG_SWPR_PAGE3 ((uint32_t)0x00000008U) /*!< SRAM2 Write protection page 3 */
|
|
|
6618 #define SYSCFG_SWPR_PAGE4 ((uint32_t)0x00000010U) /*!< SRAM2 Write protection page 4 */
|
|
|
6619 #define SYSCFG_SWPR_PAGE5 ((uint32_t)0x00000020U) /*!< SRAM2 Write protection page 5 */
|
|
|
6620 #define SYSCFG_SWPR_PAGE6 ((uint32_t)0x00000040U) /*!< SRAM2 Write protection page 6 */
|
|
|
6621 #define SYSCFG_SWPR_PAGE7 ((uint32_t)0x00000080U) /*!< SRAM2 Write protection page 7 */
|
|
|
6622 #define SYSCFG_SWPR_PAGE8 ((uint32_t)0x00000100U) /*!< SRAM2 Write protection page 8 */
|
|
|
6623 #define SYSCFG_SWPR_PAGE9 ((uint32_t)0x00000200U) /*!< SRAM2 Write protection page 9 */
|
|
|
6624 #define SYSCFG_SWPR_PAGE10 ((uint32_t)0x00000400U) /*!< SRAM2 Write protection page 10*/
|
|
|
6625 #define SYSCFG_SWPR_PAGE11 ((uint32_t)0x00000800U) /*!< SRAM2 Write protection page 11*/
|
|
|
6626 #define SYSCFG_SWPR_PAGE12 ((uint32_t)0x00001000U) /*!< SRAM2 Write protection page 12*/
|
|
|
6627 #define SYSCFG_SWPR_PAGE13 ((uint32_t)0x00002000U) /*!< SRAM2 Write protection page 13*/
|
|
|
6628 #define SYSCFG_SWPR_PAGE14 ((uint32_t)0x00004000U) /*!< SRAM2 Write protection page 14*/
|
|
|
6629 #define SYSCFG_SWPR_PAGE15 ((uint32_t)0x00008000U) /*!< SRAM2 Write protection page 15*/
|
|
|
6630
|
|
|
6631 /****************** Bit definition for SYSCFG_SKR register ****************/
|
|
|
6632 #define SYSCFG_SKR_KEY ((uint32_t)0x000000FFU) /*!< SRAM2 write protection key for software erase */
|
|
|
6633
|
|
|
6634
|
|
|
6635
|
|
|
6636
|
|
|
6637 /******************************************************************************/
|
|
|
6638 /* */
|
|
|
6639 /* TIM */
|
|
|
6640 /* */
|
|
|
6641 /******************************************************************************/
|
|
|
6642 /******************* Bit definition for TIM_CR1 register ********************/
|
|
|
6643 #define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
|
|
|
6644 #define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
|
|
|
6645 #define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
|
|
|
6646 #define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
|
|
|
6647 #define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
|
|
|
6648
|
|
|
6649 #define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
|
|
|
6650 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
|
|
|
6651 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
|
|
|
6652
|
|
|
6653 #define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
|
|
|
6654
|
|
|
6655 #define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
|
|
|
6656 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
6657 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6658
|
|
|
6659 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800U) /*!<Update interrupt flag remap */
|
|
|
6660
|
|
|
6661 /******************* Bit definition for TIM_CR2 register ********************/
|
|
|
6662 #define TIM_CR2_CCPC ((uint32_t)0x00000001U) /*!<Capture/Compare Preloaded Control */
|
|
|
6663 #define TIM_CR2_CCUS ((uint32_t)0x00000004U) /*!<Capture/Compare Control Update Selection */
|
|
|
6664 #define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
|
|
|
6665
|
|
|
6666 #define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
|
|
|
6667 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
6668 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
6669 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
6670
|
|
|
6671 #define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
|
|
|
6672 #define TIM_CR2_OIS1 ((uint32_t)0x00000100U) /*!<Output Idle state 1 (OC1 output) */
|
|
|
6673 #define TIM_CR2_OIS1N ((uint32_t)0x00000200U) /*!<Output Idle state 1 (OC1N output) */
|
|
|
6674 #define TIM_CR2_OIS2 ((uint32_t)0x00000400U) /*!<Output Idle state 2 (OC2 output) */
|
|
|
6675 #define TIM_CR2_OIS2N ((uint32_t)0x00000800U) /*!<Output Idle state 2 (OC2N output) */
|
|
|
6676 #define TIM_CR2_OIS3 ((uint32_t)0x00001000U) /*!<Output Idle state 3 (OC3 output) */
|
|
|
6677 #define TIM_CR2_OIS3N ((uint32_t)0x00002000U) /*!<Output Idle state 3 (OC3N output) */
|
|
|
6678 #define TIM_CR2_OIS4 ((uint32_t)0x00004000U) /*!<Output Idle state 4 (OC4 output) */
|
|
|
6679 #define TIM_CR2_OIS5 ((uint32_t)0x00010000U) /*!<Output Idle state 5 (OC5 output) */
|
|
|
6680 #define TIM_CR2_OIS6 ((uint32_t)0x00040000U) /*!<Output Idle state 6 (OC6 output) */
|
|
|
6681
|
|
|
6682 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000U) /*!<MMS[2:0] bits (Master Mode Selection) */
|
|
|
6683 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
|
|
|
6684 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
|
|
|
6685 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
|
|
|
6686 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000U) /*!<Bit 2 */
|
|
|
6687
|
|
|
6688 /******************* Bit definition for TIM_SMCR register *******************/
|
|
|
6689 #define TIM_SMCR_SMS ((uint32_t)0x00010007U) /*!<SMS[2:0] bits (Slave mode selection) */
|
|
|
6690 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6691 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6692 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
6693 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
6694
|
|
|
6695 #define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
|
|
|
6696
|
|
|
6697 #define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
|
|
|
6698 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
6699 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
6700 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
6701
|
|
|
6702 #define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
|
|
|
6703
|
|
|
6704 #define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
|
|
|
6705 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
6706 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6707 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
6708 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
6709
|
|
|
6710 #define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
|
|
|
6711 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
6712 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
6713
|
|
|
6714 #define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
|
|
|
6715 #define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
|
|
|
6716
|
|
|
6717 /******************* Bit definition for TIM_DIER register *******************/
|
|
|
6718 #define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
|
|
|
6719 #define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
|
|
|
6720 #define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
|
|
|
6721 #define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
|
|
|
6722 #define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
|
|
|
6723 #define TIM_DIER_COMIE ((uint32_t)0x00000020U) /*!<COM interrupt enable */
|
|
|
6724 #define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
|
|
|
6725 #define TIM_DIER_BIE ((uint32_t)0x00000080U) /*!<Break interrupt enable */
|
|
|
6726 #define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
|
|
|
6727 #define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
|
|
|
6728 #define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
|
|
|
6729 #define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
|
|
|
6730 #define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
|
|
|
6731 #define TIM_DIER_COMDE ((uint32_t)0x00002000U) /*!<COM DMA request enable */
|
|
|
6732 #define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
|
|
|
6733
|
|
|
6734 /******************** Bit definition for TIM_SR register ********************/
|
|
|
6735 #define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
|
|
|
6736 #define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
|
|
|
6737 #define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
|
|
|
6738 #define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
|
|
|
6739 #define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
|
|
|
6740 #define TIM_SR_COMIF ((uint32_t)0x00000020U) /*!<COM interrupt Flag */
|
|
|
6741 #define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
|
|
|
6742 #define TIM_SR_BIF ((uint32_t)0x00000080U) /*!<Break interrupt Flag */
|
|
|
6743 #define TIM_SR_B2IF ((uint32_t)0x00000100U) /*!<Break 2 interrupt Flag */
|
|
|
6744 #define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
|
|
|
6745 #define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
|
|
|
6746 #define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
|
|
|
6747 #define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
|
|
|
6748 #define TIM_SR_SBIF ((uint32_t)0x00002000U) /*!<System Break interrupt Flag */
|
|
|
6749 #define TIM_SR_CC5IF ((uint32_t)0x00010000U) /*!<Capture/Compare 5 interrupt Flag */
|
|
|
6750 #define TIM_SR_CC6IF ((uint32_t)0x00020000U) /*!<Capture/Compare 6 interrupt Flag */
|
|
|
6751
|
|
|
6752
|
|
|
6753 /******************* Bit definition for TIM_EGR register ********************/
|
|
|
6754 #define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
|
|
|
6755 #define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
|
|
|
6756 #define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
|
|
|
6757 #define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
|
|
|
6758 #define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
|
|
|
6759 #define TIM_EGR_COMG ((uint32_t)0x00000020U) /*!<Capture/Compare Control Update Generation */
|
|
|
6760 #define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
|
|
|
6761 #define TIM_EGR_BG ((uint32_t)0x00000080U) /*!<Break Generation */
|
|
|
6762 #define TIM_EGR_B2G ((uint32_t)0x00000100U) /*!<Break 2 Generation */
|
|
|
6763
|
|
|
6764
|
|
|
6765 /****************** Bit definition for TIM_CCMR1 register *******************/
|
|
|
6766 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
|
|
|
6767 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6768 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6769
|
|
|
6770 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
|
|
|
6771 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
|
|
|
6772
|
|
|
6773 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
|
|
|
6774 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
6775 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
6776 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
6777 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
6778
|
|
|
6779 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1 Clear Enable */
|
|
|
6780
|
|
|
6781 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
|
|
|
6782 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
6783 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6784
|
|
|
6785 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
|
|
|
6786 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
|
|
|
6787
|
|
|
6788 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
|
|
|
6789 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
6790 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
6791 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
6792 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
|
|
|
6793
|
|
|
6794 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
|
|
|
6795
|
|
|
6796 /*----------------------------------------------------------------------------*/
|
|
|
6797 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
|
|
|
6798 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
6799 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
6800
|
|
|
6801 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
|
|
|
6802 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
6803 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
6804 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
6805 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
|
|
|
6806
|
|
|
6807 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
|
|
|
6808 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
|
|
|
6809 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
|
|
|
6810
|
|
|
6811 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
|
|
|
6812 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
6813 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
6814 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
6815 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
|
|
|
6816
|
|
|
6817 /****************** Bit definition for TIM_CCMR2 register *******************/
|
|
|
6818 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
|
|
|
6819 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6820 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6821
|
|
|
6822 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
|
|
|
6823 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
|
|
|
6824
|
|
|
6825 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
|
|
6826 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
6827 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
6828 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
6829 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
6830
|
|
|
6831 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
|
|
|
6832
|
|
|
6833 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
|
|
|
6834 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
6835 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6836
|
|
|
6837 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
|
|
|
6838 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
|
|
|
6839
|
|
|
6840 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
|
|
6841 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
6842 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
6843 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
6844 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
|
|
|
6845
|
|
|
6846 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
|
|
|
6847
|
|
|
6848 /*----------------------------------------------------------------------------*/
|
|
|
6849 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
|
|
|
6850 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
6851 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
6852
|
|
|
6853 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
|
|
|
6854 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
6855 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
6856 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
6857 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
|
|
|
6858
|
|
|
6859 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
|
|
|
6860 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
|
|
|
6861 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
|
|
|
6862
|
|
|
6863 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
|
|
|
6864 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
6865 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
6866 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
6867 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
|
|
|
6868
|
|
|
6869 /****************** Bit definition for TIM_CCMR3 register *******************/
|
|
|
6870 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004U) /*!<Output Compare 5 Fast enable */
|
|
|
6871 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008U) /*!<Output Compare 5 Preload enable */
|
|
|
6872
|
|
|
6873 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070U) /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
|
|
6874 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
6875 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
6876 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
6877 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
6878
|
|
|
6879 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080U) /*!<Output Compare 5 Clear Enable */
|
|
|
6880
|
|
|
6881 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400U) /*!<Output Compare 6 Fast enable */
|
|
|
6882 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800U) /*!<Output Compare 6 Preload enable */
|
|
|
6883
|
|
|
6884 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000U) /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
|
|
|
6885 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
6886 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
6887 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
6888 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
|
|
|
6889
|
|
|
6890 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000U) /*!<Output Compare 6 Clear Enable */
|
|
|
6891
|
|
|
6892 /******************* Bit definition for TIM_CCER register *******************/
|
|
|
6893 #define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
|
|
|
6894 #define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
|
|
|
6895 #define TIM_CCER_CC1NE ((uint32_t)0x00000004U) /*!<Capture/Compare 1 Complementary output enable */
|
|
|
6896 #define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
|
|
|
6897 #define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
|
|
|
6898 #define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
|
|
|
6899 #define TIM_CCER_CC2NE ((uint32_t)0x00000040U) /*!<Capture/Compare 2 Complementary output enable */
|
|
|
6900 #define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
|
|
|
6901 #define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
|
|
|
6902 #define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
|
|
|
6903 #define TIM_CCER_CC3NE ((uint32_t)0x00000400U) /*!<Capture/Compare 3 Complementary output enable */
|
|
|
6904 #define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
|
|
|
6905 #define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
|
|
|
6906 #define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
|
|
|
6907 #define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
|
|
|
6908 #define TIM_CCER_CC5E ((uint32_t)0x00010000U) /*!<Capture/Compare 5 output enable */
|
|
|
6909 #define TIM_CCER_CC5P ((uint32_t)0x00020000U) /*!<Capture/Compare 5 output Polarity */
|
|
|
6910 #define TIM_CCER_CC6E ((uint32_t)0x00100000U) /*!<Capture/Compare 6 output enable */
|
|
|
6911 #define TIM_CCER_CC6P ((uint32_t)0x00200000U) /*!<Capture/Compare 6 output Polarity */
|
|
|
6912
|
|
|
6913 /******************* Bit definition for TIM_CNT register ********************/
|
|
|
6914 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFFU) /*!<Counter Value */
|
|
|
6915 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000U) /*!<Update interrupt flag copy (if UIFREMAP=1) */
|
|
|
6916
|
|
|
6917 /******************* Bit definition for TIM_PSC register ********************/
|
|
|
6918 #define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
|
|
|
6919
|
|
|
6920 /******************* Bit definition for TIM_ARR register ********************/
|
|
|
6921 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFFU) /*!<Actual auto-reload Value */
|
|
|
6922
|
|
|
6923 /******************* Bit definition for TIM_RCR register ********************/
|
|
|
6924 #define TIM_RCR_REP ((uint32_t)0x0000FFFFU) /*!<Repetition Counter Value */
|
|
|
6925
|
|
|
6926 /******************* Bit definition for TIM_CCR1 register *******************/
|
|
|
6927 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
|
|
|
6928
|
|
|
6929 /******************* Bit definition for TIM_CCR2 register *******************/
|
|
|
6930 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
|
|
|
6931
|
|
|
6932 /******************* Bit definition for TIM_CCR3 register *******************/
|
|
|
6933 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
|
|
|
6934
|
|
|
6935 /******************* Bit definition for TIM_CCR4 register *******************/
|
|
|
6936 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
|
|
|
6937
|
|
|
6938 /******************* Bit definition for TIM_CCR5 register *******************/
|
|
|
6939 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFFU) /*!<Capture/Compare 5 Value */
|
|
|
6940 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000U) /*!<Group Channel 5 and Channel 1 */
|
|
|
6941 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000U) /*!<Group Channel 5 and Channel 2 */
|
|
|
6942 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000U) /*!<Group Channel 5 and Channel 3 */
|
|
|
6943
|
|
|
6944 /******************* Bit definition for TIM_CCR6 register *******************/
|
|
|
6945 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 6 Value */
|
|
|
6946
|
|
|
6947 /******************* Bit definition for TIM_BDTR register *******************/
|
|
|
6948 #define TIM_BDTR_DTG ((uint32_t)0x000000FFU) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
|
|
|
6949 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6950 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6951 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
6952 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
6953 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
6954 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
6955 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
6956 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
|
|
|
6957
|
|
|
6958 #define TIM_BDTR_LOCK ((uint32_t)0x00000300U) /*!<LOCK[1:0] bits (Lock Configuration) */
|
|
|
6959 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
6960 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6961
|
|
|
6962 #define TIM_BDTR_OSSI ((uint32_t)0x00000400U) /*!<Off-State Selection for Idle mode */
|
|
|
6963 #define TIM_BDTR_OSSR ((uint32_t)0x00000800U) /*!<Off-State Selection for Run mode */
|
|
|
6964 #define TIM_BDTR_BKE ((uint32_t)0x00001000U) /*!<Break enable for Break 1 */
|
|
|
6965 #define TIM_BDTR_BKP ((uint32_t)0x00002000U) /*!<Break Polarity for Break 1 */
|
|
|
6966 #define TIM_BDTR_AOE ((uint32_t)0x00004000U) /*!<Automatic Output enable */
|
|
|
6967 #define TIM_BDTR_MOE ((uint32_t)0x00008000U) /*!<Main Output enable */
|
|
|
6968
|
|
|
6969 #define TIM_BDTR_BKF ((uint32_t)0x000F0000U) /*!<Break Filter for Break 1 */
|
|
|
6970 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000U) /*!<Break Filter for Break 2 */
|
|
|
6971
|
|
|
6972 #define TIM_BDTR_BK2E ((uint32_t)0x01000000U) /*!<Break enable for Break 2 */
|
|
|
6973 #define TIM_BDTR_BK2P ((uint32_t)0x02000000U) /*!<Break Polarity for Break 2 */
|
|
|
6974
|
|
|
6975 /******************* Bit definition for TIM_DCR register ********************/
|
|
|
6976 #define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
|
|
|
6977 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6978 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6979 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
6980 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
6981 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
6982
|
|
|
6983 #define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
|
|
|
6984 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
6985 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6986 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
6987 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
6988 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
6989
|
|
|
6990 /******************* Bit definition for TIM_DMAR register *******************/
|
|
|
6991 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
|
|
|
6992
|
|
|
6993 /******************* Bit definition for TIM1_OR1 register *******************/
|
|
|
6994 #define TIM1_OR1_ETR_ADC1_RMP ((uint32_t)0x00000003U) /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
|
|
|
6995 #define TIM1_OR1_ETR_ADC1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6996 #define TIM1_OR1_ETR_ADC1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6997
|
|
|
6998 #define TIM1_OR1_TI1_RMP ((uint32_t)0x00000010U) /*!<TIM1 Input Capture 1 remap */
|
|
|
6999
|
|
|
7000 /******************* Bit definition for TIM1_OR2 register *******************/
|
|
|
7001 #define TIM1_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
|
|
|
7002 #define TIM1_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
|
|
|
7003 #define TIM1_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
|
|
|
7004 #define TIM1_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
|
|
|
7005 #define TIM1_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
|
|
|
7006 #define TIM1_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
|
|
|
7007
|
|
|
7008 #define TIM1_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
|
|
|
7009 #define TIM1_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
|
|
|
7010 #define TIM1_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
|
|
|
7011 #define TIM1_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
|
|
|
7012
|
|
|
7013 /******************* Bit definition for TIM1_OR3 register *******************/
|
|
|
7014 #define TIM1_OR3_BK2INE ((uint32_t)0x00000001U) /*!<BRK2 BKIN2 input enable */
|
|
|
7015 #define TIM1_OR3_BK2CMP1E ((uint32_t)0x00000002U) /*!<BRK2 COMP1 enable */
|
|
|
7016 #define TIM1_OR3_BK2CMP2E ((uint32_t)0x00000004U) /*!<BRK2 COMP2 enable */
|
|
|
7017 #define TIM1_OR3_BK2INP ((uint32_t)0x00000200U) /*!<BRK2 BKIN2 input polarity */
|
|
|
7018 #define TIM1_OR3_BK2CMP1P ((uint32_t)0x00000400U) /*!<BRK2 COMP1 input polarity */
|
|
|
7019 #define TIM1_OR3_BK2CMP2P ((uint32_t)0x00000800U) /*!<BRK2 COMP2 input polarity */
|
|
|
7020
|
|
|
7021
|
|
|
7022 /******************* Bit definition for TIM2_OR1 register *******************/
|
|
|
7023 #define TIM2_OR1_ITR1_RMP ((uint32_t)0x00000001U) /*!<TIM2 Internal trigger 1 remap */
|
|
|
7024 #define TIM2_OR1_ETR1_RMP ((uint32_t)0x00000002U) /*!<TIM2 External trigger 1 remap */
|
|
|
7025
|
|
|
7026 #define TIM2_OR1_TI4_RMP ((uint32_t)0x0000000CU) /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
|
|
|
7027 #define TIM2_OR1_TI4_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
7028 #define TIM2_OR1_TI4_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
7029
|
|
|
7030 /******************* Bit definition for TIM2_OR2 register *******************/
|
|
|
7031 #define TIM2_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
|
|
|
7032 #define TIM2_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
|
|
|
7033 #define TIM2_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
|
|
|
7034 #define TIM2_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
|
|
|
7035
|
|
|
7036
|
|
|
7037 /******************* Bit definition for TIM15_OR1 register ******************/
|
|
|
7038 #define TIM15_OR1_TI1_RMP ((uint32_t)0x00000001U) /*!<TIM15 Input Capture 1 remap */
|
|
|
7039
|
|
|
7040 #define TIM15_OR1_ENCODER_MODE ((uint32_t)0x00000006U) /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
|
|
|
7041 #define TIM15_OR1_ENCODER_MODE_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
|
|
|
7042 #define TIM15_OR1_ENCODER_MODE_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
|
|
|
7043
|
|
|
7044 /******************* Bit definition for TIM15_OR2 register ******************/
|
|
|
7045 #define TIM15_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
|
|
|
7046 #define TIM15_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
|
|
|
7047 #define TIM15_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
|
|
|
7048 #define TIM15_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
|
|
|
7049 #define TIM15_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
|
|
|
7050 #define TIM15_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
|
|
|
7051
|
|
|
7052 /******************* Bit definition for TIM16_OR1 register ******************/
|
|
|
7053 #define TIM16_OR1_TI1_RMP ((uint32_t)0x00000007U) /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
|
|
|
7054 #define TIM16_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
7055 #define TIM16_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
7056 #define TIM16_OR1_TI1_RMP_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
7057
|
|
|
7058 /******************* Bit definition for TIM16_OR2 register ******************/
|
|
|
7059 #define TIM16_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
|
|
|
7060 #define TIM16_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
|
|
|
7061 #define TIM16_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
|
|
|
7062 #define TIM16_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
|
|
|
7063 #define TIM16_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
|
|
|
7064 #define TIM16_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
|
|
|
7065
|
|
|
7066
|
|
|
7067 /******************************************************************************/
|
|
|
7068 /* */
|
|
|
7069 /* Low Power Timer (LPTTIM) */
|
|
|
7070 /* */
|
|
|
7071 /******************************************************************************/
|
|
|
7072 /****************** Bit definition for LPTIM_ISR register *******************/
|
|
|
7073 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */
|
|
|
7074 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */
|
|
|
7075 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */
|
|
|
7076 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */
|
|
|
7077 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */
|
|
|
7078 #define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */
|
|
|
7079 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */
|
|
|
7080
|
|
|
7081 /****************** Bit definition for LPTIM_ICR register *******************/
|
|
|
7082 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */
|
|
|
7083 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */
|
|
|
7084 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */
|
|
|
7085 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */
|
|
|
7086 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */
|
|
|
7087 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */
|
|
|
7088 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */
|
|
|
7089
|
|
|
7090 /****************** Bit definition for LPTIM_IER register ********************/
|
|
|
7091 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */
|
|
|
7092 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */
|
|
|
7093 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */
|
|
|
7094 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */
|
|
|
7095 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */
|
|
|
7096 #define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */
|
|
|
7097 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */
|
|
|
7098
|
|
|
7099 /****************** Bit definition for LPTIM_CFGR register *******************/
|
|
|
7100 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */
|
|
|
7101
|
|
|
7102 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */
|
|
|
7103 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
|
|
|
7104 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
|
|
|
7105
|
|
|
7106 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
|
|
|
7107 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
|
|
|
7108 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
|
|
|
7109
|
|
|
7110 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
|
|
|
7111 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
|
|
|
7112 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
|
|
|
7113
|
|
|
7114 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */
|
|
|
7115 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
|
|
|
7116 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
|
|
|
7117 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
|
|
|
7118
|
|
|
7119 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
|
|
|
7120 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
|
|
|
7121 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
|
|
|
7122 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
|
|
|
7123
|
|
|
7124 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
|
|
|
7125 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
|
|
|
7126 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
|
|
|
7127
|
|
|
7128 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */
|
|
|
7129 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */
|
|
|
7130 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */
|
|
|
7131 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */
|
|
|
7132 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */
|
|
|
7133 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */
|
|
|
7134
|
|
|
7135 /****************** Bit definition for LPTIM_CR register ********************/
|
|
|
7136 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */
|
|
|
7137 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */
|
|
|
7138 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */
|
|
|
7139
|
|
|
7140 /****************** Bit definition for LPTIM_CMP register *******************/
|
|
|
7141 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */
|
|
|
7142
|
|
|
7143 /****************** Bit definition for LPTIM_ARR register *******************/
|
|
|
7144 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */
|
|
|
7145
|
|
|
7146 /****************** Bit definition for LPTIM_CNT register *******************/
|
|
|
7147 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */
|
|
|
7148
|
|
|
7149 /****************** Bit definition for LPTIM_OR register *******************/
|
|
|
7150 #define LPTIM_OR_OR ((uint32_t)0x00000003U) /*!< LPTIMER[1:0] bits (Remap selection) */
|
|
|
7151 #define LPTIM_OR_OR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
|
|
|
7152 #define LPTIM_OR_OR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
|
|
|
7153
|
|
|
7154 /******************************************************************************/
|
|
|
7155 /* */
|
|
|
7156 /* Analog Comparators (COMP) */
|
|
|
7157 /* */
|
|
|
7158 /******************************************************************************/
|
|
|
7159 /********************** Bit definition for COMPx_CSR register ***************/
|
|
|
7160 #define COMP_CSR_EN ((uint32_t)0x00000001U) /*!< COMPx enable */
|
|
|
7161
|
|
|
7162 #define COMP_CSR_PWRMODE ((uint32_t)0x0000000CU) /*!< COMPx power mode */
|
|
|
7163 #define COMP_CSR_PWRMODE_0 ((uint32_t)0x00000004U) /*!< COMPx power mode bit 0 */
|
|
|
7164 #define COMP_CSR_PWRMODE_1 ((uint32_t)0x00000008U) /*!< COMPx power mode bit 1 */
|
|
|
7165
|
|
|
7166 #define COMP_CSR_INMSEL ((uint32_t)0x00000070U) /*!< COMPx inverting input (minus) selection */
|
|
|
7167 #define COMP_CSR_INMSEL_0 ((uint32_t)0x00000010U) /*!< COMPx inverting input (minus) selection bit 0 */
|
|
|
7168 #define COMP_CSR_INMSEL_1 ((uint32_t)0x00000020U) /*!< COMPx inverting input (minus) selection bit 1 */
|
|
|
7169 #define COMP_CSR_INMSEL_2 ((uint32_t)0x00000040U) /*!< COMPx inverting input (minus) selection bit 2 */
|
|
|
7170
|
|
|
7171 #define COMP_CSR_INPSEL ((uint32_t)0x00000180U) /*!< COMPx non inverting input (plus) selection */
|
|
|
7172 #define COMP_CSR_INPSEL_0 ((uint32_t)0x00000080U) /*!< COMPx non inverting input (plus) selection bit 0*/
|
|
|
7173 #define COMP_CSR_INPSEL_1 ((uint32_t)0x00000100U) /*!< COMPx non inverting input (plus) selection bit 1*/
|
|
|
7174
|
|
|
7175 #define COMP_CSR_WINMODE ((uint32_t)0x00000200U) /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
|
|
|
7176 #define COMP_CSR_POLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */
|
|
|
7177
|
|
|
7178 #define COMP_CSR_HYST ((uint32_t)0x00030000U) /*!< COMPx hysteresis */
|
|
|
7179 #define COMP_CSR_HYST_0 ((uint32_t)0x00010000U) /*!< COMPx hysteresis bit 0 */
|
|
|
7180 #define COMP_CSR_HYST_1 ((uint32_t)0x00020000U) /*!< COMPx hysteresis bit 1 */
|
|
|
7181
|
|
|
7182 #define COMP_CSR_BLANKING ((uint32_t)0x001C0000U) /*!< COMPx blanking source */
|
|
|
7183 #define COMP_CSR_BLANKING_0 ((uint32_t)0x00040000U) /*!< COMPx blanking source bit 0 */
|
|
|
7184 #define COMP_CSR_BLANKING_1 ((uint32_t)0x00080000U) /*!< COMPx blanking source bit 1 */
|
|
|
7185 #define COMP_CSR_BLANKING_2 ((uint32_t)0x00100000U) /*!< COMPx blanking source bit 2 */
|
|
|
7186
|
|
|
7187 #define COMP_CSR_BRGEN ((uint32_t)0x00400000U) /*!< COMPx voltage scaler enable */
|
|
|
7188 #define COMP_CSR_SCALEN ((uint32_t)0x00800000U) /*!< COMPx scaler bridge enable */
|
|
|
7189
|
|
|
7190 #define COMP_CSR_INMESEL ((uint32_t)0x06000000U) /*!< COMPx inverting input (minus) extended selection */
|
|
|
7191 #define COMP_CSR_INMESEL_0 ((uint32_t)0x02000000U) /*!< COMPx inverting input (minus) extended selection bit 0*/
|
|
|
7192 #define COMP_CSR_INMESEL_1 ((uint32_t)0x04000000U) /*!< COMPx inverting input (minus) extended selection bit 1*/
|
|
|
7193
|
|
|
7194 #define COMP_CSR_VALUE ((uint32_t)0x40000000U) /*!< COMPx value */
|
|
|
7195 #define COMP_CSR_LOCK ((uint32_t)0x80000000U) /*!< COMPx lock */
|
|
|
7196
|
|
|
7197 /******************************************************************************/
|
|
|
7198 /* */
|
|
|
7199 /* Operational Amplifier (OPAMP) */
|
|
|
7200 /* */
|
|
|
7201 /******************************************************************************/
|
|
|
7202 /********************* Bit definition for OPAMPx_CSR register ***************/
|
|
|
7203 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001U) /*!< OPAMP enable */
|
|
|
7204 #define OPAMP_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier Low Power Mode */
|
|
|
7205
|
|
|
7206 #define OPAMP_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier PGA mode */
|
|
|
7207 #define OPAMP_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
|
|
|
7208 #define OPAMP_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
|
|
|
7209
|
|
|
7210 #define OPAMP_CSR_PGGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier Programmable amplifier gain value */
|
|
|
7211 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
|
|
|
7212 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
|
|
|
7213
|
|
|
7214 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
|
|
|
7215 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
7216 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
7217
|
|
|
7218 #define OPAMP_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
|
|
|
7219 #define OPAMP_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
|
|
|
7220 #define OPAMP_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
|
|
|
7221 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
|
|
|
7222 #define OPAMP_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
|
|
|
7223
|
|
|
7224 /********************* Bit definition for OPAMP1_CSR register ***************/
|
|
|
7225 #define OPAMP1_CSR_OPAEN ((uint32_t)0x00000001U) /*!< Operational amplifier1 Enable */
|
|
|
7226 #define OPAMP1_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier1 Low Power Mode */
|
|
|
7227
|
|
|
7228 #define OPAMP1_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier1 PGA mode */
|
|
|
7229 #define OPAMP1_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
|
|
|
7230 #define OPAMP1_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
|
|
|
7231
|
|
|
7232 #define OPAMP1_CSR_PGAGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier1 Programmable amplifier gain value */
|
|
|
7233 #define OPAMP1_CSR_PGAGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
|
|
|
7234 #define OPAMP1_CSR_PGAGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
|
|
|
7235
|
|
|
7236 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
|
|
|
7237 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
7238 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
7239
|
|
|
7240 #define OPAMP1_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
|
|
|
7241 #define OPAMP1_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
|
|
|
7242 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
|
|
|
7243 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
|
|
|
7244 #define OPAMP1_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
|
|
|
7245 #define OPAMP1_CSR_OPARANGE ((uint32_t)0x80000000U) /*!< Operational amplifiers power supply range for stability */
|
|
|
7246
|
|
|
7247 /******************* Bit definition for OPAMP_OTR register ******************/
|
|
|
7248 #define OPAMP_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
7249 #define OPAMP_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
7250
|
|
|
7251 /******************* Bit definition for OPAMP1_OTR register ******************/
|
|
|
7252 #define OPAMP1_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
7253 #define OPAMP1_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
7254
|
|
|
7255 /******************* Bit definition for OPAMP_LPOTR register ****************/
|
|
|
7256 #define OPAMP_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
7257 #define OPAMP_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
7258
|
|
|
7259 /******************* Bit definition for OPAMP1_LPOTR register ****************/
|
|
|
7260 #define OPAMP1_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
7261 #define OPAMP1_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
7262
|
|
|
7263 /******************************************************************************/
|
|
|
7264 /* */
|
|
|
7265 /* Touch Sensing Controller (TSC) */
|
|
|
7266 /* */
|
|
|
7267 /******************************************************************************/
|
|
|
7268 /******************* Bit definition for TSC_CR register *********************/
|
|
|
7269 #define TSC_CR_TSCE ((uint32_t)0x00000001U) /*!<Touch sensing controller enable */
|
|
|
7270 #define TSC_CR_START ((uint32_t)0x00000002U) /*!<Start acquisition */
|
|
|
7271 #define TSC_CR_AM ((uint32_t)0x00000004U) /*!<Acquisition mode */
|
|
|
7272 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /*!<Synchronization pin polarity */
|
|
|
7273 #define TSC_CR_IODEF ((uint32_t)0x00000010U) /*!<IO default mode */
|
|
|
7274
|
|
|
7275 #define TSC_CR_MCV ((uint32_t)0x000000E0U) /*!<MCV[2:0] bits (Max Count Value) */
|
|
|
7276 #define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
|
|
|
7277 #define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
|
|
|
7278 #define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
|
|
|
7279
|
|
|
7280 #define TSC_CR_PGPSC ((uint32_t)0x00007000U) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
|
|
|
7281 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
7282 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
7283 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
7284
|
|
|
7285 #define TSC_CR_SSPSC ((uint32_t)0x00008000U) /*!<Spread Spectrum Prescaler */
|
|
|
7286 #define TSC_CR_SSE ((uint32_t)0x00010000U) /*!<Spread Spectrum Enable */
|
|
|
7287
|
|
|
7288 #define TSC_CR_SSD ((uint32_t)0x00FE0000U) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
|
|
|
7289 #define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
|
|
|
7290 #define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
|
|
|
7291 #define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
|
|
|
7292 #define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
|
|
|
7293 #define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
|
|
|
7294 #define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
|
|
|
7295 #define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
|
|
|
7296
|
|
|
7297 #define TSC_CR_CTPL ((uint32_t)0x0F000000U) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
|
|
|
7298 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
7299 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
7300 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
7301 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
7302
|
|
|
7303 #define TSC_CR_CTPH ((uint32_t)0xF0000000U) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
|
|
|
7304 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
|
|
|
7305 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
|
|
|
7306 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
|
|
|
7307 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /*!<Bit 3 */
|
|
|
7308
|
|
|
7309 /******************* Bit definition for TSC_IER register ********************/
|
|
|
7310 #define TSC_IER_EOAIE ((uint32_t)0x00000001U) /*!<End of acquisition interrupt enable */
|
|
|
7311 #define TSC_IER_MCEIE ((uint32_t)0x00000002U) /*!<Max count error interrupt enable */
|
|
|
7312
|
|
|
7313 /******************* Bit definition for TSC_ICR register ********************/
|
|
|
7314 #define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /*!<End of acquisition interrupt clear */
|
|
|
7315 #define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /*!<Max count error interrupt clear */
|
|
|
7316
|
|
|
7317 /******************* Bit definition for TSC_ISR register ********************/
|
|
|
7318 #define TSC_ISR_EOAF ((uint32_t)0x00000001U) /*!<End of acquisition flag */
|
|
|
7319 #define TSC_ISR_MCEF ((uint32_t)0x00000002U) /*!<Max count error flag */
|
|
|
7320
|
|
|
7321 /******************* Bit definition for TSC_IOHCR register ******************/
|
|
|
7322 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
|
|
|
7323 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
|
|
|
7324 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
|
|
|
7325 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
|
|
|
7326 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
|
|
|
7327 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
|
|
|
7328 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
|
|
|
7329 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
|
|
|
7330 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
|
|
|
7331 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
|
|
|
7332 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
|
|
|
7333 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
|
|
|
7334 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
|
|
|
7335 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
|
|
|
7336 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
|
|
|
7337 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
|
|
|
7338 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
|
|
|
7339 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
|
|
|
7340 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
|
|
|
7341 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
|
|
|
7342 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
|
|
|
7343 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
|
|
|
7344 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
|
|
|
7345 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
|
|
|
7346 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
|
|
|
7347 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
|
|
|
7348 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
|
|
|
7349 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
|
|
|
7350
|
|
|
7351 /******************* Bit definition for TSC_IOASCR register *****************/
|
|
|
7352 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 analog switch enable */
|
|
|
7353 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 analog switch enable */
|
|
|
7354 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 analog switch enable */
|
|
|
7355 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 analog switch enable */
|
|
|
7356 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 analog switch enable */
|
|
|
7357 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 analog switch enable */
|
|
|
7358 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 analog switch enable */
|
|
|
7359 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 analog switch enable */
|
|
|
7360 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 analog switch enable */
|
|
|
7361 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 analog switch enable */
|
|
|
7362 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 analog switch enable */
|
|
|
7363 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 analog switch enable */
|
|
|
7364 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 analog switch enable */
|
|
|
7365 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 analog switch enable */
|
|
|
7366 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 analog switch enable */
|
|
|
7367 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 analog switch enable */
|
|
|
7368 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 analog switch enable */
|
|
|
7369 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 analog switch enable */
|
|
|
7370 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 analog switch enable */
|
|
|
7371 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 analog switch enable */
|
|
|
7372 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 analog switch enable */
|
|
|
7373 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 analog switch enable */
|
|
|
7374 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 analog switch enable */
|
|
|
7375 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 analog switch enable */
|
|
|
7376 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 analog switch enable */
|
|
|
7377 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 analog switch enable */
|
|
|
7378 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 analog switch enable */
|
|
|
7379 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 analog switch enable */
|
|
|
7380
|
|
|
7381 /******************* Bit definition for TSC_IOSCR register ******************/
|
|
|
7382 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 sampling mode */
|
|
|
7383 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 sampling mode */
|
|
|
7384 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 sampling mode */
|
|
|
7385 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 sampling mode */
|
|
|
7386 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 sampling mode */
|
|
|
7387 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 sampling mode */
|
|
|
7388 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 sampling mode */
|
|
|
7389 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 sampling mode */
|
|
|
7390 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 sampling mode */
|
|
|
7391 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 sampling mode */
|
|
|
7392 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 sampling mode */
|
|
|
7393 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 sampling mode */
|
|
|
7394 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 sampling mode */
|
|
|
7395 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 sampling mode */
|
|
|
7396 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 sampling mode */
|
|
|
7397 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 sampling mode */
|
|
|
7398 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 sampling mode */
|
|
|
7399 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 sampling mode */
|
|
|
7400 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 sampling mode */
|
|
|
7401 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 sampling mode */
|
|
|
7402 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 sampling mode */
|
|
|
7403 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 sampling mode */
|
|
|
7404 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 sampling mode */
|
|
|
7405 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 sampling mode */
|
|
|
7406 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 sampling mode */
|
|
|
7407 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 sampling mode */
|
|
|
7408 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 sampling mode */
|
|
|
7409 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 sampling mode */
|
|
|
7410
|
|
|
7411 /******************* Bit definition for TSC_IOCCR register ******************/
|
|
|
7412 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 channel mode */
|
|
|
7413 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 channel mode */
|
|
|
7414 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 channel mode */
|
|
|
7415 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 channel mode */
|
|
|
7416 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 channel mode */
|
|
|
7417 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 channel mode */
|
|
|
7418 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 channel mode */
|
|
|
7419 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 channel mode */
|
|
|
7420 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 channel mode */
|
|
|
7421 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 channel mode */
|
|
|
7422 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 channel mode */
|
|
|
7423 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 channel mode */
|
|
|
7424 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 channel mode */
|
|
|
7425 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 channel mode */
|
|
|
7426 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 channel mode */
|
|
|
7427 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 channel mode */
|
|
|
7428 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 channel mode */
|
|
|
7429 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 channel mode */
|
|
|
7430 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 channel mode */
|
|
|
7431 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 channel mode */
|
|
|
7432 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 channel mode */
|
|
|
7433 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 channel mode */
|
|
|
7434 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 channel mode */
|
|
|
7435 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 channel mode */
|
|
|
7436 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 channel mode */
|
|
|
7437 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 channel mode */
|
|
|
7438 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 channel mode */
|
|
|
7439 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 channel mode */
|
|
|
7440
|
|
|
7441 /******************* Bit definition for TSC_IOGCSR register *****************/
|
|
|
7442 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /*!<Analog IO GROUP1 enable */
|
|
|
7443 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /*!<Analog IO GROUP2 enable */
|
|
|
7444 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /*!<Analog IO GROUP3 enable */
|
|
|
7445 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /*!<Analog IO GROUP4 enable */
|
|
|
7446 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /*!<Analog IO GROUP5 enable */
|
|
|
7447 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /*!<Analog IO GROUP6 enable */
|
|
|
7448 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /*!<Analog IO GROUP7 enable */
|
|
|
7449 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /*!<Analog IO GROUP1 status */
|
|
|
7450 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /*!<Analog IO GROUP2 status */
|
|
|
7451 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /*!<Analog IO GROUP3 status */
|
|
|
7452 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /*!<Analog IO GROUP4 status */
|
|
|
7453 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /*!<Analog IO GROUP5 status */
|
|
|
7454 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /*!<Analog IO GROUP6 status */
|
|
|
7455 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /*!<Analog IO GROUP7 status */
|
|
|
7456
|
|
|
7457 /******************* Bit definition for TSC_IOGXCR register *****************/
|
|
|
7458 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /*!<CNT[13:0] bits (Counter value) */
|
|
|
7459
|
|
|
7460 /******************************************************************************/
|
|
|
7461 /* */
|
|
|
7462 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
|
|
7463 /* */
|
|
|
7464 /******************************************************************************/
|
|
|
7465
|
|
|
7466 /*
|
|
|
7467 * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
|
|
|
7468 */
|
|
|
7469
|
|
|
7470 /* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
|
|
|
7471 #define USART_TCBGT_SUPPORT
|
|
|
7472
|
|
|
7473 /****************** Bit definition for USART_CR1 register *******************/
|
|
|
7474 #define USART_CR1_UE ((uint32_t)0x00000001U) /*!< USART Enable */
|
|
|
7475 #define USART_CR1_UESM ((uint32_t)0x00000002U) /*!< USART Enable in STOP Mode */
|
|
|
7476 #define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
|
|
|
7477 #define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
|
|
|
7478 #define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
|
|
|
7479 #define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
|
|
|
7480 #define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
|
|
|
7481 #define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< TXE Interrupt Enable */
|
|
|
7482 #define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
|
|
|
7483 #define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
|
|
|
7484 #define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
|
|
|
7485 #define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Receiver Wakeup method */
|
|
|
7486 #define USART_CR1_M ((uint32_t)0x10001000U) /*!< Word length */
|
|
|
7487 #define USART_CR1_M0 ((uint32_t)0x00001000U) /*!< Word length - Bit 0 */
|
|
|
7488 #define USART_CR1_MME ((uint32_t)0x00002000U) /*!< Mute Mode Enable */
|
|
|
7489 #define USART_CR1_CMIE ((uint32_t)0x00004000U) /*!< Character match interrupt enable */
|
|
|
7490 #define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit or 16-bit mode */
|
|
|
7491 #define USART_CR1_DEDT ((uint32_t)0x001F0000U) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
|
|
|
7492 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
|
|
|
7493 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
|
|
|
7494 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
|
|
|
7495 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
|
|
|
7496 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
|
|
|
7497 #define USART_CR1_DEAT ((uint32_t)0x03E00000U) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
|
|
|
7498 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
|
|
|
7499 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
|
|
|
7500 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
|
|
|
7501 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /*!< Bit 3 */
|
|
|
7502 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /*!< Bit 4 */
|
|
|
7503 #define USART_CR1_RTOIE ((uint32_t)0x04000000U) /*!< Receive Time Out interrupt enable */
|
|
|
7504 #define USART_CR1_EOBIE ((uint32_t)0x08000000U) /*!< End of Block interrupt enable */
|
|
|
7505 #define USART_CR1_M1 ((uint32_t)0x10000000U) /*!< Word length - Bit 1 */
|
|
|
7506
|
|
|
7507 /****************** Bit definition for USART_CR2 register *******************/
|
|
|
7508 #define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /*!< 7-bit or 4-bit Address Detection */
|
|
|
7509 #define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
|
|
|
7510 #define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
|
|
|
7511 #define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
|
|
|
7512 #define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
|
|
|
7513 #define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
|
|
|
7514 #define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
|
|
|
7515 #define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
|
|
|
7516 #define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
|
|
|
7517 #define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
|
|
|
7518 #define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
|
|
|
7519 #define USART_CR2_SWAP ((uint32_t)0x00008000U) /*!< SWAP TX/RX pins */
|
|
|
7520 #define USART_CR2_RXINV ((uint32_t)0x00010000U) /*!< RX pin active level inversion */
|
|
|
7521 #define USART_CR2_TXINV ((uint32_t)0x00020000U) /*!< TX pin active level inversion */
|
|
|
7522 #define USART_CR2_DATAINV ((uint32_t)0x00040000U) /*!< Binary data inversion */
|
|
|
7523 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /*!< Most Significant Bit First */
|
|
|
7524 #define USART_CR2_ABREN ((uint32_t)0x00100000U) /*!< Auto Baud-Rate Enable*/
|
|
|
7525 #define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
|
|
|
7526 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
|
|
|
7527 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
|
|
|
7528 #define USART_CR2_RTOEN ((uint32_t)0x00800000U) /*!< Receiver Time-Out enable */
|
|
|
7529 #define USART_CR2_ADD ((uint32_t)0xFF000000U) /*!< Address of the USART node */
|
|
|
7530
|
|
|
7531 /****************** Bit definition for USART_CR3 register *******************/
|
|
|
7532 #define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
|
|
|
7533 #define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
|
|
|
7534 #define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
|
|
|
7535 #define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
|
|
|
7536 #define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< SmartCard NACK enable */
|
|
|
7537 #define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< SmartCard mode enable */
|
|
|
7538 #define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
|
|
|
7539 #define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
|
|
|
7540 #define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
|
|
|
7541 #define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
|
|
|
7542 #define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
|
|
|
7543 #define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
|
|
|
7544 #define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /*!< Overrun Disable */
|
|
|
7545 #define USART_CR3_DDRE ((uint32_t)0x00002000U) /*!< DMA Disable on Reception Error */
|
|
|
7546 #define USART_CR3_DEM ((uint32_t)0x00004000U) /*!< Driver Enable Mode */
|
|
|
7547 #define USART_CR3_DEP ((uint32_t)0x00008000U) /*!< Driver Enable Polarity Selection */
|
|
|
7548 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
|
|
|
7549 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
|
|
|
7550 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
|
|
|
7551 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /*!< Bit 2 */
|
|
|
7552 #define USART_CR3_WUS ((uint32_t)0x00300000U) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
|
|
|
7553 #define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
|
|
|
7554 #define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
|
|
|
7555 #define USART_CR3_WUFIE ((uint32_t)0x00400000U) /*!< Wake Up Interrupt Enable */
|
|
|
7556 #define USART_CR3_TCBGTIE ((uint32_t)0x01000000U) /*!< Transmission Complete Before Guard Time Interrupt Enable */
|
|
|
7557
|
|
|
7558 /****************** Bit definition for USART_BRR register *******************/
|
|
|
7559 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000FU) /*!< Fraction of USARTDIV */
|
|
|
7560 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0U) /*!< Mantissa of USARTDIV */
|
|
|
7561
|
|
|
7562 /****************** Bit definition for USART_GTPR register ******************/
|
|
|
7563 #define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
|
|
|
7564 #define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< GT[7:0] bits (Guard time value) */
|
|
|
7565
|
|
|
7566
|
|
|
7567 /******************* Bit definition for USART_RTOR register *****************/
|
|
|
7568 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /*!< Receiver Time Out Value */
|
|
|
7569 #define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /*!< Block Length */
|
|
|
7570
|
|
|
7571 /******************* Bit definition for USART_RQR register ******************/
|
|
|
7572 #define USART_RQR_ABRRQ ((uint16_t)0x0001U) /*!< Auto-Baud Rate Request */
|
|
|
7573 #define USART_RQR_SBKRQ ((uint16_t)0x0002U) /*!< Send Break Request */
|
|
|
7574 #define USART_RQR_MMRQ ((uint16_t)0x0004U) /*!< Mute Mode Request */
|
|
|
7575 #define USART_RQR_RXFRQ ((uint16_t)0x0008U) /*!< Receive Data flush Request */
|
|
|
7576 #define USART_RQR_TXFRQ ((uint16_t)0x0010U) /*!< Transmit data flush Request */
|
|
|
7577
|
|
|
7578 /******************* Bit definition for USART_ISR register ******************/
|
|
|
7579 #define USART_ISR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
|
|
|
7580 #define USART_ISR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
|
|
|
7581 #define USART_ISR_NE ((uint32_t)0x00000004U) /*!< Noise detected Flag */
|
|
|
7582 #define USART_ISR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
|
|
|
7583 #define USART_ISR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
|
|
|
7584 #define USART_ISR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
|
|
|
7585 #define USART_ISR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
|
|
|
7586 #define USART_ISR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
|
|
|
7587 #define USART_ISR_LBDF ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
|
|
|
7588 #define USART_ISR_CTSIF ((uint32_t)0x00000200U) /*!< CTS interrupt flag */
|
|
|
7589 #define USART_ISR_CTS ((uint32_t)0x00000400U) /*!< CTS flag */
|
|
|
7590 #define USART_ISR_RTOF ((uint32_t)0x00000800U) /*!< Receiver Time Out */
|
|
|
7591 #define USART_ISR_EOBF ((uint32_t)0x00001000U) /*!< End Of Block Flag */
|
|
|
7592 #define USART_ISR_ABRE ((uint32_t)0x00004000U) /*!< Auto-Baud Rate Error */
|
|
|
7593 #define USART_ISR_ABRF ((uint32_t)0x00008000U) /*!< Auto-Baud Rate Flag */
|
|
|
7594 #define USART_ISR_BUSY ((uint32_t)0x00010000U) /*!< Busy Flag */
|
|
|
7595 #define USART_ISR_CMF ((uint32_t)0x00020000U) /*!< Character Match Flag */
|
|
|
7596 #define USART_ISR_SBKF ((uint32_t)0x00040000U) /*!< Send Break Flag */
|
|
|
7597 #define USART_ISR_RWU ((uint32_t)0x00080000U) /*!< Receive Wake Up from mute mode Flag */
|
|
|
7598 #define USART_ISR_WUF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Flag */
|
|
|
7599 #define USART_ISR_TEACK ((uint32_t)0x00200000U) /*!< Transmit Enable Acknowledge Flag */
|
|
|
7600 #define USART_ISR_REACK ((uint32_t)0x00400000U) /*!< Receive Enable Acknowledge Flag */
|
|
|
7601 #define USART_ISR_TCBGT ((uint32_t)0x02000000U) /*!< Transmission Complete Before Guard Time Completion Flag */
|
|
|
7602
|
|
|
7603 /******************* Bit definition for USART_ICR register ******************/
|
|
|
7604 #define USART_ICR_PECF ((uint32_t)0x00000001U) /*!< Parity Error Clear Flag */
|
|
|
7605 #define USART_ICR_FECF ((uint32_t)0x00000002U) /*!< Framing Error Clear Flag */
|
|
|
7606 #define USART_ICR_NCF ((uint32_t)0x00000004U) /*!< Noise detected Clear Flag */
|
|
|
7607 #define USART_ICR_ORECF ((uint32_t)0x00000008U) /*!< OverRun Error Clear Flag */
|
|
|
7608 #define USART_ICR_IDLECF ((uint32_t)0x00000010U) /*!< IDLE line detected Clear Flag */
|
|
|
7609 #define USART_ICR_TCCF ((uint32_t)0x00000040U) /*!< Transmission Complete Clear Flag */
|
|
|
7610 #define USART_ICR_TCBGTCF ((uint32_t)0x00000080U) /*!< Transmission Complete Before Guard Time Clear Flag */
|
|
|
7611 #define USART_ICR_LBDCF ((uint32_t)0x00000100U) /*!< LIN Break Detection Clear Flag */
|
|
|
7612 #define USART_ICR_CTSCF ((uint32_t)0x00000200U) /*!< CTS Interrupt Clear Flag */
|
|
|
7613 #define USART_ICR_RTOCF ((uint32_t)0x00000800U) /*!< Receiver Time Out Clear Flag */
|
|
|
7614 #define USART_ICR_EOBCF ((uint32_t)0x00001000U) /*!< End Of Block Clear Flag */
|
|
|
7615 #define USART_ICR_CMCF ((uint32_t)0x00020000U) /*!< Character Match Clear Flag */
|
|
|
7616 #define USART_ICR_WUCF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Clear Flag */
|
|
|
7617
|
|
|
7618 /******************* Bit definition for USART_RDR register ******************/
|
|
|
7619 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
|
|
|
7620
|
|
|
7621 /******************* Bit definition for USART_TDR register ******************/
|
|
|
7622 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
|
|
|
7623
|
|
|
7624 /******************************************************************************/
|
|
|
7625 /* */
|
|
|
7626 /* Single Wire Protocol Master Interface (SWPMI) */
|
|
|
7627 /* */
|
|
|
7628 /******************************************************************************/
|
|
|
7629
|
|
|
7630 /******************* Bit definition for SWPMI_CR register ********************/
|
|
|
7631 #define SWPMI_CR_RXDMA ((uint32_t)0x00000001U) /*!<Reception DMA enable */
|
|
|
7632 #define SWPMI_CR_TXDMA ((uint32_t)0x00000002U) /*!<Transmission DMA enable */
|
|
|
7633 #define SWPMI_CR_RXMODE ((uint32_t)0x00000004U) /*!<Reception buffering mode */
|
|
|
7634 #define SWPMI_CR_TXMODE ((uint32_t)0x00000008U) /*!<Transmission buffering mode */
|
|
|
7635 #define SWPMI_CR_LPBK ((uint32_t)0x00000010U) /*!<Loopback mode enable */
|
|
|
7636 #define SWPMI_CR_SWPACT ((uint32_t)0x00000020U) /*!<Single wire protocol master interface activate */
|
|
|
7637 #define SWPMI_CR_DEACT ((uint32_t)0x00000400U) /*!<Single wire protocol master interface deactivate */
|
|
|
7638
|
|
|
7639 /******************* Bit definition for SWPMI_BRR register ********************/
|
|
|
7640 #define SWPMI_BRR_BR ((uint32_t)0x0000003FU) /*!<BR[5:0] bits (Bitrate prescaler) */
|
|
|
7641
|
|
|
7642 /******************* Bit definition for SWPMI_ISR register ********************/
|
|
|
7643 #define SWPMI_ISR_RXBFF ((uint32_t)0x00000001U) /*!<Receive buffer full flag */
|
|
|
7644 #define SWPMI_ISR_TXBEF ((uint32_t)0x00000002U) /*!<Transmit buffer empty flag */
|
|
|
7645 #define SWPMI_ISR_RXBERF ((uint32_t)0x00000004U) /*!<Receive CRC error flag */
|
|
|
7646 #define SWPMI_ISR_RXOVRF ((uint32_t)0x00000008U) /*!<Receive overrun error flag */
|
|
|
7647 #define SWPMI_ISR_TXUNRF ((uint32_t)0x00000010U) /*!<Transmit underrun error flag */
|
|
|
7648 #define SWPMI_ISR_RXNE ((uint32_t)0x00000020U) /*!<Receive data register not empty */
|
|
|
7649 #define SWPMI_ISR_TXE ((uint32_t)0x00000040U) /*!<Transmit data register empty */
|
|
|
7650 #define SWPMI_ISR_TCF ((uint32_t)0x00000080U) /*!<Transfer complete flag */
|
|
|
7651 #define SWPMI_ISR_SRF ((uint32_t)0x00000100U) /*!<Slave resume flag */
|
|
|
7652 #define SWPMI_ISR_SUSP ((uint32_t)0x00000200U) /*!<SUSPEND flag */
|
|
|
7653 #define SWPMI_ISR_DEACTF ((uint32_t)0x00000400U) /*!<DEACTIVATED flag */
|
|
|
7654
|
|
|
7655 /******************* Bit definition for SWPMI_ICR register ********************/
|
|
|
7656 #define SWPMI_ICR_CRXBFF ((uint32_t)0x00000001U) /*!<Clear receive buffer full flag */
|
|
|
7657 #define SWPMI_ICR_CTXBEF ((uint32_t)0x00000002U) /*!<Clear transmit buffer empty flag */
|
|
|
7658 #define SWPMI_ICR_CRXBERF ((uint32_t)0x00000004U) /*!<Clear receive CRC error flag */
|
|
|
7659 #define SWPMI_ICR_CRXOVRF ((uint32_t)0x00000008U) /*!<Clear receive overrun error flag */
|
|
|
7660 #define SWPMI_ICR_CTXUNRF ((uint32_t)0x00000010U) /*!<Clear transmit underrun error flag */
|
|
|
7661 #define SWPMI_ICR_CTCF ((uint32_t)0x00000080U) /*!<Clear transfer complete flag */
|
|
|
7662 #define SWPMI_ICR_CSRF ((uint32_t)0x00000100U) /*!<Clear slave resume flag */
|
|
|
7663
|
|
|
7664 /******************* Bit definition for SWPMI_IER register ********************/
|
|
|
7665 #define SWPMI_IER_SRIE ((uint32_t)0x00000100U) /*!<Slave resume interrupt enable */
|
|
|
7666 #define SWPMI_IER_TCIE ((uint32_t)0x00000080U) /*!<Transmit complete interrupt enable */
|
|
|
7667 #define SWPMI_IER_TIE ((uint32_t)0x00000040U) /*!<Transmit interrupt enable */
|
|
|
7668 #define SWPMI_IER_RIE ((uint32_t)0x00000020U) /*!<Receive interrupt enable */
|
|
|
7669 #define SWPMI_IER_TXUNRIE ((uint32_t)0x00000010U) /*!<Transmit underrun error interrupt enable */
|
|
|
7670 #define SWPMI_IER_RXOVRIE ((uint32_t)0x00000008U) /*!<Receive overrun error interrupt enable */
|
|
|
7671 #define SWPMI_IER_RXBERIE ((uint32_t)0x00000004U) /*!<Receive CRC error interrupt enable */
|
|
|
7672 #define SWPMI_IER_TXBEIE ((uint32_t)0x00000002U) /*!<Transmit buffer empty interrupt enable */
|
|
|
7673 #define SWPMI_IER_RXBFIE ((uint32_t)0x00000001U) /*!<Receive buffer full interrupt enable */
|
|
|
7674
|
|
|
7675 /******************* Bit definition for SWPMI_RFL register ********************/
|
|
|
7676 #define SWPMI_RFL_RFL ((uint32_t)0x0000001FU) /*!<RFL[4:0] bits (Receive Frame length) */
|
|
|
7677 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
|
|
7678
|
|
|
7679 /******************* Bit definition for SWPMI_TDR register ********************/
|
|
|
7680 #define SWPMI_TDR_TD ((uint32_t)0xFFFFFFFFU) /*!<Transmit Data Register */
|
|
|
7681
|
|
|
7682 /******************* Bit definition for SWPMI_RDR register ********************/
|
|
|
7683 #define SWPMI_RDR_RD ((uint32_t)0xFFFFFFFFU) /*!<Receive Data Register */
|
|
|
7684
|
|
|
7685 /******************* Bit definition for SWPMI_OR register ********************/
|
|
|
7686 #define SWPMI_OR_TBYP ((uint32_t)0x00000001U) /*!<SWP Transceiver Bypass */
|
|
|
7687 #define SWPMI_OR_CLASS ((uint32_t)0x00000002U) /*!<SWP Voltage Class selection */
|
|
|
7688
|
|
|
7689 /******************************************************************************/
|
|
|
7690 /* */
|
|
|
7691 /* VREFBUF */
|
|
|
7692 /* */
|
|
|
7693 /******************************************************************************/
|
|
|
7694 /******************* Bit definition for VREFBUF_CSR register ****************/
|
|
|
7695 #define VREFBUF_CSR_ENVR ((uint32_t)0x00000001U) /*!<Voltage reference buffer enable */
|
|
|
7696 #define VREFBUF_CSR_HIZ ((uint32_t)0x00000002U) /*!<High impedance mode */
|
|
|
7697 #define VREFBUF_CSR_VRS ((uint32_t)0x00000004U) /*!<Voltage reference scale */
|
|
|
7698 #define VREFBUF_CSR_VRR ((uint32_t)0x00000008U) /*!<Voltage reference buffer ready */
|
|
|
7699
|
|
|
7700 /******************* Bit definition for VREFBUF_CCR register ******************/
|
|
|
7701 #define VREFBUF_CCR_TRIM ((uint32_t)0x0000003FU) /*!<TRIM[5:0] bits (Trimming code) */
|
|
|
7702
|
|
|
7703 /******************************************************************************/
|
|
|
7704 /* */
|
|
|
7705 /* Window WATCHDOG */
|
|
|
7706 /* */
|
|
|
7707 /******************************************************************************/
|
|
|
7708 /******************* Bit definition for WWDG_CR register ********************/
|
|
|
7709 #define WWDG_CR_T ((uint32_t)0x0000007FU) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
|
|
7710 #define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
7711 #define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
7712 #define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
7713 #define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
7714 #define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
7715 #define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
7716 #define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
7717
|
|
|
7718 #define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!<Activation bit */
|
|
|
7719
|
|
|
7720 /******************* Bit definition for WWDG_CFR register *******************/
|
|
|
7721 #define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!<W[6:0] bits (7-bit window value) */
|
|
|
7722 #define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
7723 #define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
7724 #define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
7725 #define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
7726 #define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
7727 #define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
7728 #define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
7729
|
|
|
7730 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!<WDGTB[1:0] bits (Timer Base) */
|
|
|
7731 #define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
|
|
|
7732 #define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
|
|
|
7733
|
|
|
7734 #define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!<Early Wakeup Interrupt */
|
|
|
7735
|
|
|
7736 /******************* Bit definition for WWDG_SR register ********************/
|
|
|
7737 #define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!<Early Wakeup Interrupt Flag */
|
|
|
7738
|
|
|
7739
|
|
|
7740 /******************************************************************************/
|
|
|
7741 /* */
|
|
|
7742 /* Debug MCU */
|
|
|
7743 /* */
|
|
|
7744 /******************************************************************************/
|
|
|
7745 /******************** Bit definition for DBGMCU_IDCODE register *************/
|
|
|
7746 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU)
|
|
|
7747 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U)
|
|
|
7748
|
|
|
7749 /******************** Bit definition for DBGMCU_CR register *****************/
|
|
|
7750 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U)
|
|
|
7751 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U)
|
|
|
7752 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U)
|
|
|
7753 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020U)
|
|
|
7754
|
|
|
7755 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0U)
|
|
|
7756 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040U)/*!<Bit 0 */
|
|
|
7757 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080U)/*!<Bit 1 */
|
|
|
7758
|
|
|
7759 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
|
|
|
7760 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP ((uint32_t)0x00000001U)
|
|
|
7761 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP ((uint32_t)0x00000010U)
|
|
|
7762 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP ((uint32_t)0x00000020U)
|
|
|
7763 #define DBGMCU_APB1FZR1_DBG_RTC_STOP ((uint32_t)0x00000400U)
|
|
|
7764 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP ((uint32_t)0x00000800U)
|
|
|
7765 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP ((uint32_t)0x00001000U)
|
|
|
7766 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP ((uint32_t)0x00200000U)
|
|
|
7767 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP ((uint32_t)0x00400000U)
|
|
|
7768 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP ((uint32_t)0x00800000U)
|
|
|
7769 #define DBGMCU_APB1FZR1_DBG_CAN_STOP ((uint32_t)0x02000000U)
|
|
|
7770 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP ((uint32_t)0x80000000U)
|
|
|
7771
|
|
|
7772 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
|
|
|
7773 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP ((uint32_t)0x00000020U)
|
|
|
7774
|
|
|
7775 /******************** Bit definition for DBGMCU_APB2FZ register ************/
|
|
|
7776 #define DBGMCU_APB2FZ_DBG_TIM1_STOP ((uint32_t)0x00000800U)
|
|
|
7777 #define DBGMCU_APB2FZ_DBG_TIM15_STOP ((uint32_t)0x00010000U)
|
|
|
7778 #define DBGMCU_APB2FZ_DBG_TIM16_STOP ((uint32_t)0x00020000U)
|
|
|
7779
|
|
|
7780
|
|
|
7781 /**
|
|
|
7782 * @}
|
|
|
7783 */
|
|
|
7784
|
|
|
7785 /**
|
|
|
7786 * @}
|
|
|
7787 */
|
|
|
7788
|
|
|
7789 /** @addtogroup Exported_macros
|
|
|
7790 * @{
|
|
|
7791 */
|
|
|
7792
|
|
|
7793 /******************************* ADC Instances ********************************/
|
|
|
7794 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
|
|
|
7795
|
|
|
7796 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
|
|
|
7797
|
|
|
7798 /******************************** CAN Instances ******************************/
|
|
|
7799 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
|
|
|
7800
|
|
|
7801 /******************************** COMP Instances ******************************/
|
|
|
7802 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
|
|
|
7803 ((INSTANCE) == COMP2))
|
|
|
7804
|
|
|
7805 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
|
|
|
7806
|
|
|
7807 /******************** COMP Instances with window mode capability **************/
|
|
|
7808 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
|
|
|
7809
|
|
|
7810 /******************************* CRC Instances ********************************/
|
|
|
7811 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
|
|
|
7812
|
|
|
7813 /******************************* DAC Instances ********************************/
|
|
|
7814 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
|
|
|
7815
|
|
|
7816 /******************************** DMA Instances *******************************/
|
|
|
7817 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
|
|
|
7818 ((INSTANCE) == DMA1_Channel2) || \
|
|
|
7819 ((INSTANCE) == DMA1_Channel3) || \
|
|
|
7820 ((INSTANCE) == DMA1_Channel4) || \
|
|
|
7821 ((INSTANCE) == DMA1_Channel5) || \
|
|
|
7822 ((INSTANCE) == DMA1_Channel6) || \
|
|
|
7823 ((INSTANCE) == DMA1_Channel7) || \
|
|
|
7824 ((INSTANCE) == DMA2_Channel1) || \
|
|
|
7825 ((INSTANCE) == DMA2_Channel2) || \
|
|
|
7826 ((INSTANCE) == DMA2_Channel3) || \
|
|
|
7827 ((INSTANCE) == DMA2_Channel4) || \
|
|
|
7828 ((INSTANCE) == DMA2_Channel5) || \
|
|
|
7829 ((INSTANCE) == DMA2_Channel6) || \
|
|
|
7830 ((INSTANCE) == DMA2_Channel7))
|
|
|
7831
|
|
|
7832 /******************************* GPIO Instances *******************************/
|
|
|
7833 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
|
|
7834 ((INSTANCE) == GPIOB) || \
|
|
|
7835 ((INSTANCE) == GPIOC) || \
|
|
|
7836 ((INSTANCE) == GPIOD) || \
|
|
|
7837 ((INSTANCE) == GPIOE) || \
|
|
|
7838 ((INSTANCE) == GPIOH))
|
|
|
7839
|
|
|
7840 /******************************* GPIO AF Instances ****************************/
|
|
|
7841 /* On L4, all GPIO Bank support AF */
|
|
|
7842 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
|
|
|
7843
|
|
|
7844 /**************************** GPIO Lock Instances *****************************/
|
|
|
7845 /* On L4, all GPIO Bank support the Lock mechanism */
|
|
|
7846 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
|
|
|
7847
|
|
|
7848 /******************************** I2C Instances *******************************/
|
|
|
7849 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
|
|
7850 ((INSTANCE) == I2C2) || \
|
|
|
7851 ((INSTANCE) == I2C3))
|
|
|
7852
|
|
|
7853 /****************** I2C Instances : wakeup capability from stop modes *********/
|
|
|
7854 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
|
|
|
7855
|
|
|
7856 /****************************** OPAMP Instances *******************************/
|
|
|
7857 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
|
|
|
7858
|
|
|
7859 #define IS_OPAMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1_COMMON)
|
|
|
7860
|
|
|
7861 /******************************* QSPI Instances *******************************/
|
|
|
7862 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
|
|
|
7863
|
|
|
7864 /******************************* RNG Instances ********************************/
|
|
|
7865 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
|
|
|
7866
|
|
|
7867 /****************************** RTC Instances *********************************/
|
|
|
7868 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
|
|
7869
|
|
|
7870 /******************************** SAI Instances *******************************/
|
|
|
7871 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
|
|
|
7872 ((INSTANCE) == SAI1_Block_B))
|
|
|
7873
|
|
|
7874 /****************************** SDMMC Instances *******************************/
|
|
|
7875 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
|
|
|
7876
|
|
|
7877 /****************************** SMBUS Instances *******************************/
|
|
|
7878 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
|
|
7879 ((INSTANCE) == I2C2) || \
|
|
|
7880 ((INSTANCE) == I2C3))
|
|
|
7881
|
|
|
7882 /******************************** SPI Instances *******************************/
|
|
|
7883 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
|
|
7884 ((INSTANCE) == SPI2) || \
|
|
|
7885 ((INSTANCE) == SPI3))
|
|
|
7886
|
|
|
7887 /******************************** SWPMI Instances *****************************/
|
|
|
7888 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
|
|
|
7889
|
|
|
7890 /****************** LPTIM Instances : All supported instances *****************/
|
|
|
7891 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
|
|
|
7892 ((INSTANCE) == LPTIM2))
|
|
|
7893
|
|
|
7894 /****************** TIM Instances : All supported instances *******************/
|
|
|
7895 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7896 ((INSTANCE) == TIM2) || \
|
|
|
7897 ((INSTANCE) == TIM6) || \
|
|
|
7898 ((INSTANCE) == TIM7) || \
|
|
|
7899 ((INSTANCE) == TIM15) || \
|
|
|
7900 ((INSTANCE) == TIM16))
|
|
|
7901
|
|
|
7902 /****************** TIM Instances : supporting 32 bits counter ****************/
|
|
|
7903 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
|
|
|
7904
|
|
|
7905 /****************** TIM Instances : supporting the break function *************/
|
|
|
7906 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7907 ((INSTANCE) == TIM15) || \
|
|
|
7908 ((INSTANCE) == TIM16))
|
|
|
7909
|
|
|
7910 /************** TIM Instances : supporting Break source selection *************/
|
|
|
7911 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7912 ((INSTANCE) == TIM15) || \
|
|
|
7913 ((INSTANCE) == TIM16))
|
|
|
7914
|
|
|
7915 /****************** TIM Instances : supporting 2 break inputs *****************/
|
|
|
7916 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
|
|
|
7917
|
|
|
7918 /************* TIM Instances : at least 1 capture/compare channel *************/
|
|
|
7919 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7920 ((INSTANCE) == TIM2) || \
|
|
|
7921 ((INSTANCE) == TIM15) || \
|
|
|
7922 ((INSTANCE) == TIM16))
|
|
|
7923
|
|
|
7924 /************ TIM Instances : at least 2 capture/compare channels *************/
|
|
|
7925 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7926 ((INSTANCE) == TIM2) || \
|
|
|
7927 ((INSTANCE) == TIM15))
|
|
|
7928
|
|
|
7929 /************ TIM Instances : at least 3 capture/compare channels *************/
|
|
|
7930 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7931 ((INSTANCE) == TIM2))
|
|
|
7932
|
|
|
7933 /************ TIM Instances : at least 4 capture/compare channels *************/
|
|
|
7934 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7935 ((INSTANCE) == TIM2))
|
|
|
7936
|
|
|
7937 /****************** TIM Instances : at least 5 capture/compare channels *******/
|
|
|
7938 #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
|
|
|
7939
|
|
|
7940 /****************** TIM Instances : at least 6 capture/compare channels *******/
|
|
|
7941 #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
|
|
|
7942
|
|
|
7943 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
|
|
|
7944 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7945 ((INSTANCE) == TIM15) || \
|
|
|
7946 ((INSTANCE) == TIM16))
|
|
|
7947
|
|
|
7948 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
|
|
|
7949 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7950 ((INSTANCE) == TIM2) || \
|
|
|
7951 ((INSTANCE) == TIM6) || \
|
|
|
7952 ((INSTANCE) == TIM7) || \
|
|
|
7953 ((INSTANCE) == TIM15) || \
|
|
|
7954 ((INSTANCE) == TIM16))
|
|
|
7955
|
|
|
7956 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
|
|
|
7957 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7958 ((INSTANCE) == TIM2) || \
|
|
|
7959 ((INSTANCE) == TIM15) || \
|
|
|
7960 ((INSTANCE) == TIM16))
|
|
|
7961
|
|
|
7962 /******************** TIM Instances : DMA burst feature ***********************/
|
|
|
7963 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7964 ((INSTANCE) == TIM2) || \
|
|
|
7965 ((INSTANCE) == TIM15) || \
|
|
|
7966 ((INSTANCE) == TIM16))
|
|
|
7967
|
|
|
7968 /******************* TIM Instances : output(s) available **********************/
|
|
|
7969 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
|
|
|
7970 ((((INSTANCE) == TIM1) && \
|
|
|
7971 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7972 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7973 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
7974 ((CHANNEL) == TIM_CHANNEL_4) || \
|
|
|
7975 ((CHANNEL) == TIM_CHANNEL_5) || \
|
|
|
7976 ((CHANNEL) == TIM_CHANNEL_6))) \
|
|
|
7977 || \
|
|
|
7978 (((INSTANCE) == TIM2) && \
|
|
|
7979 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7980 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7981 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
7982 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
7983 || \
|
|
|
7984 (((INSTANCE) == TIM15) && \
|
|
|
7985 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7986 ((CHANNEL) == TIM_CHANNEL_2))) \
|
|
|
7987 || \
|
|
|
7988 (((INSTANCE) == TIM16) && \
|
|
|
7989 (((CHANNEL) == TIM_CHANNEL_1))))
|
|
|
7990
|
|
|
7991 /****************** TIM Instances : supporting complementary output(s) ********/
|
|
|
7992 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
|
|
|
7993 ((((INSTANCE) == TIM1) && \
|
|
|
7994 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7995 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7996 ((CHANNEL) == TIM_CHANNEL_3))) \
|
|
|
7997 || \
|
|
|
7998 (((INSTANCE) == TIM15) && \
|
|
|
7999 ((CHANNEL) == TIM_CHANNEL_1)) \
|
|
|
8000 || \
|
|
|
8001 (((INSTANCE) == TIM16) && \
|
|
|
8002 ((CHANNEL) == TIM_CHANNEL_1)))
|
|
|
8003
|
|
|
8004 /****************** TIM Instances : supporting clock division *****************/
|
|
|
8005 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8006 ((INSTANCE) == TIM2) || \
|
|
|
8007 ((INSTANCE) == TIM15) || \
|
|
|
8008 ((INSTANCE) == TIM16))
|
|
|
8009
|
|
|
8010 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
|
|
|
8011 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8012 ((INSTANCE) == TIM2) || \
|
|
|
8013 ((INSTANCE) == TIM15))
|
|
|
8014
|
|
|
8015 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
|
|
|
8016 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8017 ((INSTANCE) == TIM2))
|
|
|
8018
|
|
|
8019 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
|
|
|
8020 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8021 ((INSTANCE) == TIM2) || \
|
|
|
8022 ((INSTANCE) == TIM15))
|
|
|
8023
|
|
|
8024 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
|
|
8025 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8026 ((INSTANCE) == TIM2) || \
|
|
|
8027 ((INSTANCE) == TIM15))
|
|
|
8028
|
|
|
8029 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
|
|
|
8030 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
|
|
|
8031
|
|
|
8032 /****************** TIM Instances : supporting commutation event generation ***/
|
|
|
8033 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8034 ((INSTANCE) == TIM15) || \
|
|
|
8035 ((INSTANCE) == TIM16))
|
|
|
8036
|
|
|
8037 /****************** TIM Instances : supporting counting mode selection ********/
|
|
|
8038 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8039 ((INSTANCE) == TIM2))
|
|
|
8040
|
|
|
8041 /****************** TIM Instances : supporting encoder interface **************/
|
|
|
8042 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8043 ((INSTANCE) == TIM2))
|
|
|
8044
|
|
|
8045 /****************** TIM Instances : supporting Hall sensor interface **********/
|
|
|
8046 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8047 ((INSTANCE) == TIM2))
|
|
|
8048
|
|
|
8049 /**************** TIM Instances : external trigger input available ************/
|
|
|
8050 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8051 ((INSTANCE) == TIM2))
|
|
|
8052
|
|
|
8053 /************* TIM Instances : supporting ETR source selection ***************/
|
|
|
8054 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8055 ((INSTANCE) == TIM2))
|
|
|
8056
|
|
|
8057 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
|
|
|
8058 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8059 ((INSTANCE) == TIM2) || \
|
|
|
8060 ((INSTANCE) == TIM6) || \
|
|
|
8061 ((INSTANCE) == TIM7) || \
|
|
|
8062 ((INSTANCE) == TIM15))
|
|
|
8063
|
|
|
8064 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
|
|
|
8065 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8066 ((INSTANCE) == TIM2) || \
|
|
|
8067 ((INSTANCE) == TIM15))
|
|
|
8068
|
|
|
8069 /****************** TIM Instances : supporting OCxREF clear *******************/
|
|
|
8070 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8071 ((INSTANCE) == TIM2))
|
|
|
8072
|
|
|
8073 /****************** TIM Instances : remapping capability **********************/
|
|
|
8074 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8075 ((INSTANCE) == TIM2) || \
|
|
|
8076 ((INSTANCE) == TIM15) || \
|
|
|
8077 ((INSTANCE) == TIM16))
|
|
|
8078
|
|
|
8079 /****************** TIM Instances : supporting repetition counter *************/
|
|
|
8080 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8081 ((INSTANCE) == TIM15) || \
|
|
|
8082 ((INSTANCE) == TIM16))
|
|
|
8083
|
|
|
8084 /****************** TIM Instances : supporting synchronization ****************/
|
|
|
8085 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
|
|
8086
|
|
|
8087 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
|
|
8088 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
|
|
|
8089
|
|
|
8090 /******************* TIM Instances : Timer input XOR function *****************/
|
|
|
8091 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
8092 ((INSTANCE) == TIM2) || \
|
|
|
8093 ((INSTANCE) == TIM15))
|
|
|
8094
|
|
|
8095 /****************************** TSC Instances *********************************/
|
|
|
8096 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
|
|
|
8097
|
|
|
8098 /******************** USART Instances : Synchronous mode **********************/
|
|
|
8099 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8100 ((INSTANCE) == USART2) || \
|
|
|
8101 ((INSTANCE) == USART3))
|
|
|
8102
|
|
|
8103 /******************** UART Instances : Asynchronous mode **********************/
|
|
|
8104 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8105 ((INSTANCE) == USART2) || \
|
|
|
8106 ((INSTANCE) == USART3))
|
|
|
8107
|
|
|
8108 /****************** UART Instances : Auto Baud Rate detection ****************/
|
|
|
8109 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8110 ((INSTANCE) == USART2) || \
|
|
|
8111 ((INSTANCE) == USART3))
|
|
|
8112
|
|
|
8113 /****************** UART Instances : Driver Enable *****************/
|
|
|
8114 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8115 ((INSTANCE) == USART2) || \
|
|
|
8116 ((INSTANCE) == USART3) || \
|
|
|
8117 ((INSTANCE) == LPUART1))
|
|
|
8118
|
|
|
8119 /******************** UART Instances : Half-Duplex mode **********************/
|
|
|
8120 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8121 ((INSTANCE) == USART2) || \
|
|
|
8122 ((INSTANCE) == USART3) || \
|
|
|
8123 ((INSTANCE) == LPUART1))
|
|
|
8124
|
|
|
8125 /****************** UART Instances : Hardware Flow control ********************/
|
|
|
8126 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8127 ((INSTANCE) == USART2) || \
|
|
|
8128 ((INSTANCE) == USART3) || \
|
|
|
8129 ((INSTANCE) == LPUART1))
|
|
|
8130
|
|
|
8131 /******************** UART Instances : LIN mode **********************/
|
|
|
8132 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8133 ((INSTANCE) == USART2) || \
|
|
|
8134 ((INSTANCE) == USART3))
|
|
|
8135
|
|
|
8136 /******************** UART Instances : Wake-up from Stop mode **********************/
|
|
|
8137 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8138 ((INSTANCE) == USART2) || \
|
|
|
8139 ((INSTANCE) == USART3) || \
|
|
|
8140 ((INSTANCE) == LPUART1))
|
|
|
8141
|
|
|
8142 /*********************** UART Instances : IRDA mode ***************************/
|
|
|
8143 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8144 ((INSTANCE) == USART2) || \
|
|
|
8145 ((INSTANCE) == USART3))
|
|
|
8146
|
|
|
8147 /********************* USART Instances : Smard card mode ***********************/
|
|
|
8148 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
8149 ((INSTANCE) == USART2) || \
|
|
|
8150 ((INSTANCE) == USART3))
|
|
|
8151
|
|
|
8152 /******************** LPUART Instance *****************************************/
|
|
|
8153 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
|
|
|
8154
|
|
|
8155 /****************************** IWDG Instances ********************************/
|
|
|
8156 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
|
|
8157
|
|
|
8158 /****************************** WWDG Instances ********************************/
|
|
|
8159 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
|
|
8160
|
|
|
8161 /**
|
|
|
8162 * @}
|
|
|
8163 */
|
|
|
8164
|
|
|
8165
|
|
|
8166 /******************************************************************************/
|
|
|
8167 /* For a painless codes migration between the STM32L4xx device product */
|
|
|
8168 /* lines, the aliases defined below are put in place to overcome the */
|
|
|
8169 /* differences in the interrupt handlers and IRQn definitions. */
|
|
|
8170 /* No need to update developed interrupt code when moving across */
|
|
|
8171 /* product lines within the same STM32L4 Family */
|
|
|
8172 /******************************************************************************/
|
|
|
8173
|
|
|
8174 /* Aliases for __IRQn */
|
|
|
8175 #define ADC1_2_IRQn ADC1_IRQn
|
|
|
8176 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
|
|
|
8177
|
|
|
8178 /* Aliases for __IRQHandler */
|
|
|
8179 #define ADC1_2_IRQHandler ADC1_IRQHandler
|
|
|
8180 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
|
|
|
8181
|
|
|
8182 #ifdef __cplusplus
|
|
|
8183 }
|
|
|
8184 #endif /* __cplusplus */
|
|
|
8185
|
|
|
8186 #endif /* __STM32L431xx_H */
|
|
|
8187
|
|
|
8188 /**
|
|
|
8189 * @}
|
|
|
8190 */
|
|
|
8191
|
|
|
8192 /**
|
|
|
8193 * @}
|
|
|
8194 */
|
|
|
8195
|
|
|
8196 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
