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1 /**
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2 ******************************************************************************
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3 * @file stm32l4xx_hal.h
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4 * @author MCD Application Team
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5 * @version V1.6.0
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6 * @date 28-October-2016
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7 * @brief This file contains all the functions prototypes for the HAL
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8 * module driver.
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9 ******************************************************************************
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10 * @attention
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11 *
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12 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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13 *
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14 * Redistribution and use in source and binary forms, with or without modification,
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15 * are permitted provided that the following conditions are met:
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16 * 1. Redistributions of source code must retain the above copyright notice,
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17 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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22 * may be used to endorse or promote products derived from this software
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23 * without specific prior written permission.
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24 *
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25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 *
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36 ******************************************************************************
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37 */
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38
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39 /* Define to prevent recursive inclusion -------------------------------------*/
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40 #ifndef __STM32L4xx_HAL_H
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41 #define __STM32L4xx_HAL_H
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42
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43 #ifdef __cplusplus
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44 extern "C" {
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45 #endif
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46
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47 /* Includes ------------------------------------------------------------------*/
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48 #include "stm32l4xx_hal_conf.h"
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49
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50 /** @addtogroup STM32L4xx_HAL_Driver
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51 * @{
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52 */
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53
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54 /** @addtogroup HAL
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55 * @{
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56 */
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57
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58 /* Exported types ------------------------------------------------------------*/
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59 /* Exported constants --------------------------------------------------------*/
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60 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
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61 * @{
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62 */
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63
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64 /** @defgroup SYSCFG_BootMode Boot Mode
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65 * @{
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66 */
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67 #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
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68 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
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69
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70 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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71 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1
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72 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
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73
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74 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
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75
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76 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
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77
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78 /**
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79 * @}
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80 */
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81
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82 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
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83 * @{
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84 */
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85 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
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86 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
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87 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
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88 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
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89 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
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90 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
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91
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92 /**
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93 * @}
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94 */
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95
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96 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection
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97 * @{
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98 */
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99 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
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100 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
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101 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
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102 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
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103 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
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104 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
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105 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
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106 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
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107 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
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108 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
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109 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
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110 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
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111 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
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112 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
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113 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
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114 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
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115 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
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116 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
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117 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
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118 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
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119 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
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120 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
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121 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
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122 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
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123 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
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124 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
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125 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
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126 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
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127 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
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128 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
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129 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
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130 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
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131
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132 /**
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133 * @}
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134 */
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135
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136 #if defined(VREFBUF)
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137 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
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138 * @{
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139 */
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140 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
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141 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
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142
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143 /**
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144 * @}
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145 */
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146
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147 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
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148 * @{
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149 */
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150 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
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151 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
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152
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153 /**
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154 * @}
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155 */
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156 #endif /* VREFBUF */
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157
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158 /** @defgroup SYSCFG_flags_definition Flags
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159 * @{
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160 */
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161
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162 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */
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163 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */
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164
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165 /**
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166 * @}
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167 */
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168
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169 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
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170 * @{
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171 */
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172
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173 /** @brief Fast-mode Plus driving capability on a specific GPIO
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174 */
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175 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
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176 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
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177 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
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178 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
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179 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
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180 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
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181 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
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182 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
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183
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184 /**
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185 * @}
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186 */
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187
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188 /**
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189 * @}
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190 */
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191
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192 /* Exported macros -----------------------------------------------------------*/
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193
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194 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
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195 * @{
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196 */
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197
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198 /** @brief Freeze/Unfreeze Peripherals in Debug mode
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199 */
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200 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
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201 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
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202 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
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203 #endif
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204
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205 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
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206 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
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207 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
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208 #endif
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209
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210 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
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211 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
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212 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
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213 #endif
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214
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215 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
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216 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
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217 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
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218 #endif
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219
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220 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
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221 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
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222 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
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223 #endif
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224
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225 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
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226 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
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227 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
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228 #endif
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229
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230 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
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231 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
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232 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
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233 #endif
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234
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235 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
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236 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
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237 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
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238 #endif
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239
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240 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
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241 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
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242 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
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243 #endif
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244
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245 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
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246 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
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247 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
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248 #endif
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249
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250 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
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251 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
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252 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
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253 #endif
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254
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255 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
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256 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
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257 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
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258 #endif
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259
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260 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
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261 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
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262 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
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263 #endif
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264
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265 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
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266 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
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267 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
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268 #endif
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269
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270 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
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271 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
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272 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
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273 #endif
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274
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275 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
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276 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
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277 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
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278 #endif
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279
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280 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
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281 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
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282 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
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283 #endif
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284
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285 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
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286 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
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287 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
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288 #endif
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289
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290 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
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291 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
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292 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
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293 #endif
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294
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295 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
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296 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
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297 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
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298 #endif
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299
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300 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
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301 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
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302 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
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303 #endif
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304
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305 /**
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306 * @}
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307 */
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308
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309 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
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310 * @{
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311 */
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312
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313 /** @brief Main Flash memory mapped at 0x00000000.
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314 */
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315 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
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316
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317 /** @brief System Flash memory mapped at 0x00000000.
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318 */
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319 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
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320
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321 /** @brief Embedded SRAM mapped at 0x00000000.
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322 */
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323 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
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324
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325 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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326
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327 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
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328 */
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329 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
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330
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331 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
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332
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333 /** @brief QUADSPI mapped at 0x00000000.
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334 */
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335 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
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336
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337 /**
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338 * @brief Return the boot mode as configured by user.
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339 * @retval The boot mode as configured by user. The returned value can be one
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340 * of the following values:
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341 * @arg @ref SYSCFG_BOOT_MAINFLASH
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342 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH
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343 @if STM32L486xx
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344 * @arg @ref SYSCFG_BOOT_FMC
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345 @endif
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346 * @arg @ref SYSCFG_BOOT_SRAM
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347 * @arg @ref SYSCFG_BOOT_QUADSPI
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348 */
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349 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
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350
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351 /** @brief SRAM2 page write protection enable macro
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352 * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP
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353 * @note write protection can only be disabled by a system reset
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354 */
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355 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
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356 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
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357 }while(0)
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358
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359 /** @brief SRAM2 page write protection unlock prior to erase
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360 * @note Writing a wrong key reactivates the write protection
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361 */
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362 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\
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363 SYSCFG->SKR = 0x53;\
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364 }while(0)
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365
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366 /** @brief SRAM2 erase
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367 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
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368 */
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369 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
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370
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371 /** @brief Floating Point Unit interrupt enable/disable macros
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372 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
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373 */
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374 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
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375 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
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376 }while(0)
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377
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378 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
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379 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
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380 }while(0)
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381
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382 /** @brief SYSCFG Break ECC lock.
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383 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
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384 * @note The selected configuration is locked and can be unlocked only by system reset.
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385 */
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386 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
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387
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388 /** @brief SYSCFG Break Cortex-M4 Lockup lock.
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389 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
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390 * @note The selected configuration is locked and can be unlocked only by system reset.
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391 */
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392 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
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393
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394 /** @brief SYSCFG Break PVD lock.
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395 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
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396 * @note The selected configuration is locked and can be unlocked only by system reset.
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397 */
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398 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
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399
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400 /** @brief SYSCFG Break SRAM2 parity lock.
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401 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
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402 * @note The selected configuration is locked and can be unlocked by system reset.
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403 */
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404 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
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405
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406 /** @brief Check SYSCFG flag is set or not.
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407 * @param __FLAG__: specifies the flag to check.
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408 * This parameter can be one of the following values:
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409 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
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410 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
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411 * @retval The new state of __FLAG__ (TRUE or FALSE).
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412 */
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413 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
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414
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415 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
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416 */
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417 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
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418
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419 /** @brief Fast-mode Plus driving capability enable/disable macros
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420 * @param __FASTMODEPLUS__: This parameter can be a value of :
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421 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
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422 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
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423 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
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424 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
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425 */
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426 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
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427 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
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428 }while(0)
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429
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430 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
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431 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
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432 }while(0)
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433
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434 /**
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435 * @}
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436 */
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437
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438 /* Private macros ------------------------------------------------------------*/
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439 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
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440 * @{
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441 */
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442
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443 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
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444 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
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445 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
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446 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
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447 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
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448 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
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449
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450 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
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451 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \
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452 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
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453 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
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454
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455 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
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456
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457 #if defined(VREFBUF)
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458 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
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459 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
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460
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461 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
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462 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
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463
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464 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
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465 #endif /* VREFBUF */
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466
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467 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
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468 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
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469 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
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470 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
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471 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
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472 #elif defined(SYSCFG_FASTMODEPLUS_PB8)
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473 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
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474 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
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475 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
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476 #elif defined(SYSCFG_FASTMODEPLUS_PB9)
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477 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
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478 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
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479 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
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480 #else
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481 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
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482 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
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483 #endif
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|
484 /**
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485 * @}
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486 */
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487
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|
|
488 /* Exported functions --------------------------------------------------------*/
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489
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490 /** @addtogroup HAL_Exported_Functions
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491 * @{
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492 */
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493
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494 /** @addtogroup HAL_Exported_Functions_Group1
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495 * @{
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|
496 */
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|
|
497
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|
|
498 /* Initialization and de-initialization functions ******************************/
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|
499 HAL_StatusTypeDef HAL_Init(void);
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|
|
500 HAL_StatusTypeDef HAL_DeInit(void);
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501 void HAL_MspInit(void);
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|
502 void HAL_MspDeInit(void);
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|
503 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
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504
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|
505 /**
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506 * @}
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507 */
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508
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|
|
509 /** @addtogroup HAL_Exported_Functions_Group2
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510 * @{
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511 */
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512
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|
513 /* Peripheral Control functions ************************************************/
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|
514 void HAL_IncTick(void);
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|
515 void HAL_Delay(uint32_t Delay);
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|
516 uint32_t HAL_GetTick(void);
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|
517 void HAL_SuspendTick(void);
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|
|
518 void HAL_ResumeTick(void);
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|
519 uint32_t HAL_GetHalVersion(void);
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520 uint32_t HAL_GetREVID(void);
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|
|
521 uint32_t HAL_GetDEVID(void);
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522
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|
523 /**
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|
|
524 * @}
|
|
|
525 */
|
|
|
526
|
|
|
527 /** @addtogroup HAL_Exported_Functions_Group3
|
|
|
528 * @{
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|
|
529 */
|
|
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530
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|
|
531 /* DBGMCU Peripheral Control functions *****************************************/
|
|
|
532 void HAL_DBGMCU_EnableDBGSleepMode(void);
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|
|
533 void HAL_DBGMCU_DisableDBGSleepMode(void);
|
|
|
534 void HAL_DBGMCU_EnableDBGStopMode(void);
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|
|
535 void HAL_DBGMCU_DisableDBGStopMode(void);
|
|
|
536 void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
|
|
537 void HAL_DBGMCU_DisableDBGStandbyMode(void);
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|
538
|
|
|
539 /**
|
|
|
540 * @}
|
|
|
541 */
|
|
|
542
|
|
|
543 /** @addtogroup HAL_Exported_Functions_Group4
|
|
|
544 * @{
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|
|
545 */
|
|
|
546
|
|
|
547 /* SYSCFG Control functions ****************************************************/
|
|
|
548 void HAL_SYSCFG_SRAM2Erase(void);
|
|
|
549 void HAL_SYSCFG_EnableMemorySwappingBank(void);
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|
|
550 void HAL_SYSCFG_DisableMemorySwappingBank(void);
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|
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551
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|
|
552 #if defined(VREFBUF)
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|
|
553 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
|
|
|
554 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
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|
|
555 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
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|
|
556 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
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|
|
557 void HAL_SYSCFG_DisableVREFBUF(void);
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|
|
558 #endif /* VREFBUF */
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559
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|
|
560 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
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|
|
561 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
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562
|
|
|
563 /**
|
|
|
564 * @}
|
|
|
565 */
|
|
|
566
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|
|
567 /**
|
|
|
568 * @}
|
|
|
569 */
|
|
|
570
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|
|
571 /**
|
|
|
572 * @}
|
|
|
573 */
|
|
|
574
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575 /**
|
|
|
576 * @}
|
|
|
577 */
|
|
|
578
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|
|
579 #ifdef __cplusplus
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|
|
580 }
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|
|
581 #endif
|
|
|
582
|
|
|
583 #endif /* __STM32L4xx_HAL_H */
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|
|
584
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585 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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