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1 /**
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2 ******************************************************************************
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3 * @file stm32l4xx_hal_pwr_ex.h
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4 * @author MCD Application Team
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5 * @version V1.6.0
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6 * @date 28-October-2016
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7 * @brief Header file of PWR HAL Extended module.
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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12 *
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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23 *
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 *
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35 ******************************************************************************
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36 */
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37
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32L4xx_HAL_PWR_EX_H
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40 #define __STM32L4xx_HAL_PWR_EX_H
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41
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42 #ifdef __cplusplus
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43 extern "C" {
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44 #endif
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32l4xx_hal_def.h"
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48
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49 /** @addtogroup STM32L4xx_HAL_Driver
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50 * @{
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51 */
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52
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53 /** @addtogroup PWREx
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54 * @{
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55 */
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56
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57
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58 /* Exported types ------------------------------------------------------------*/
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59
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60 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
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61 * @{
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62 */
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63
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64
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65 /**
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66 * @brief PWR PVM configuration structure definition
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67 */
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68 typedef struct
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69 {
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70 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
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71 This parameter can be a value of @ref PWREx_PVM_Type.
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72 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
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73 @if STM32L486xx
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74 @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
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75 @endif
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76 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
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77 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
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78
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79 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
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80 This parameter can be a value of @ref PWREx_PVM_Mode. */
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81 }PWR_PVMTypeDef;
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82
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83 /**
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84 * @}
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85 */
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86
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87 /* Exported constants --------------------------------------------------------*/
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88
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89 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
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90 * @{
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91 */
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92
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93 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
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94 * @{
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95 */
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96 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */
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97 /**
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98 * @}
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99 */
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100
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101
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102 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
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103 * @{
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104 */
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105 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
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106 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
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107 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
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108 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
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109 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
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110 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
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111 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
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112 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
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113 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
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114 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
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115 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
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116 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
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117 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
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118 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
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119 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
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120 /**
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121 * @}
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122 */
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123
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124 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
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125 * @{
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126 */
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127 #if defined(PWR_CR2_PVME1)
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128 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
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129 #endif /* PWR_CR2_PVME1 */
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130 #if defined(PWR_CR2_PVME2)
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131 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
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132 #endif /* PWR_CR2_PVME2 */
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133 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
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134 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */
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135 /**
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136 * @}
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137 */
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138
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139 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
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140 * @{
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141 */
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142 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
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143 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
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144 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
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145 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
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146 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
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147 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
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148 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
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149 /**
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150 * @}
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151 */
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152
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153
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154
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155 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
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156 * @{
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157 */
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158 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */
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159 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
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160 /**
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161 * @}
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162 */
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163
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164
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165 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
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166 * @{
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167 */
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168 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */
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169 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
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170 /**
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171 * @}
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172 */
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173
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174 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
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175 * @{
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176 */
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177 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)
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178 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
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179 /**
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180 * @}
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181 */
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182
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183 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
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184 * @{
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185 */
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186 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
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187 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
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188 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
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189 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
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190 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
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191 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
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192 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
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193 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
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194 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
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195 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
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196 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
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197 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
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198 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
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199 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
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200 #define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
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201 #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
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202 /**
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203 * @}
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204 */
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205
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206 /** @defgroup PWREx_GPIO GPIO port
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207 * @{
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208 */
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209 #define PWR_GPIO_A 0x00000000 /*!< GPIO port A */
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210 #define PWR_GPIO_B 0x00000001 /*!< GPIO port B */
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211 #define PWR_GPIO_C 0x00000002 /*!< GPIO port C */
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212 #if defined(GPIOD_BASE)
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213 #define PWR_GPIO_D 0x00000003 /*!< GPIO port D */
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214 #endif
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215 #if defined(GPIOE_BASE)
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216 #define PWR_GPIO_E 0x00000004 /*!< GPIO port E */
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217 #endif
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218 #if defined(GPIOF_BASE)
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219 #define PWR_GPIO_F 0x00000005 /*!< GPIO port F */
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220 #endif
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221 #if defined(GPIOG_BASE)
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222 #define PWR_GPIO_G 0x00000006 /*!< GPIO port G */
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223 #endif
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224 #define PWR_GPIO_H 0x00000007 /*!< GPIO port H */
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225 /**
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226 * @}
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227 */
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228
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229 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
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230 * @{
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231 */
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232 #if defined(PWR_CR2_PVME1)
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233 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */
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234 #endif /* PWR_CR2_PVME1 */
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235 #if defined(PWR_CR2_PVME2)
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236 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */
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237 #endif /* PWR_CR2_PVME2 */
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238 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */
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239 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */
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240 /**
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241 * @}
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242 */
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243
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244 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
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245 * @{
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246 */
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247 #if defined(PWR_CR2_PVME1)
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248 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */
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249 #endif /* PWR_CR2_PVME1 */
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250 #if defined(PWR_CR2_PVME2)
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251 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */
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252 #endif /* PWR_CR2_PVME2 */
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253 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */
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254 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */
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255 /**
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256 * @}
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257 */
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258
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259 /** @defgroup PWREx_Flag PWR Status Flags
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260 * Elements values convention: 0000 0000 0XXY YYYYb
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261 * - Y YYYY : Flag position in the XX register (5 bits)
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262 * - XX : Status register (2 bits)
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263 * - 01: SR1 register
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264 * - 10: SR2 register
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265 * The only exception is PWR_FLAG_WU, encompassing all
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266 * wake-up flags and set to PWR_SR1_WUF.
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267 * @{
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268 */
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269 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */
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270 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */
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271 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */
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272 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */
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273 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */
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274 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
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275 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */
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276 #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */
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277
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278 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */
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279 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */
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280 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */
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281 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */
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282 #if defined(PWR_CR2_PVME1)
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283 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */
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284 #endif /* PWR_CR2_PVME1 */
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285 #if defined(PWR_CR2_PVME2)
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286 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */
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287 #endif /* PWR_CR2_PVME2 */
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288 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */
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289 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */
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290 /**
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291 * @}
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292 */
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293
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294 /**
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295 * @}
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296 */
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297
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298 /* Exported macros -----------------------------------------------------------*/
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299 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
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300 * @{
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301 */
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302
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303 #if defined(PWR_CR2_PVME1)
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304 /**
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305 * @brief Enable the PVM1 Extended Interrupt Line.
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306 * @retval None
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307 */
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308 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
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309
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310 /**
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311 * @brief Disable the PVM1 Extended Interrupt Line.
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312 * @retval None
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313 */
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314 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
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315
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316 /**
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317 * @brief Enable the PVM1 Event Line.
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318 * @retval None
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319 */
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320 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
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321
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322 /**
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323 * @brief Disable the PVM1 Event Line.
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324 * @retval None
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325 */
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326 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
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327
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328 /**
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329 * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
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330 * @retval None
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331 */
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332 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
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333
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334 /**
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335 * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
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336 * @retval None
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337 */
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338 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
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339
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340 /**
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341 * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
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342 * @retval None
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343 */
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344 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
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345
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346
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347 /**
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348 * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
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349 * @retval None
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350 */
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351 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
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352
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353
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354 /**
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355 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
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356 * @retval None
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357 */
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358 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
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359 do { \
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360 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
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361 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
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362 } while(0)
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363
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364 /**
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365 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
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366 * @retval None
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367 */
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368 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
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369 do { \
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370 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
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371 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
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372 } while(0)
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373
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374 /**
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375 * @brief Generate a Software interrupt on selected EXTI line.
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376 * @retval None
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377 */
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378 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
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379
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380 /**
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381 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
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382 * @retval EXTI PVM1 Line Status.
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383 */
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384 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
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385
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386 /**
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387 * @brief Clear the PVM1 EXTI flag.
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388 * @retval None
|
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389 */
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390 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
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391
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392 #endif /* PWR_CR2_PVME1 */
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393
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394
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395 #if defined(PWR_CR2_PVME2)
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396 /**
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397 * @brief Enable the PVM2 Extended Interrupt Line.
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398 * @retval None
|
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399 */
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400 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
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401
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402 /**
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403 * @brief Disable the PVM2 Extended Interrupt Line.
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404 * @retval None
|
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405 */
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406 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
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407
|
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408 /**
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409 * @brief Enable the PVM2 Event Line.
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410 * @retval None
|
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411 */
|
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412 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
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413
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414 /**
|
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415 * @brief Disable the PVM2 Event Line.
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416 * @retval None
|
|
|
417 */
|
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418 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
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419
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420 /**
|
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421 * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
|
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422 * @retval None
|
|
|
423 */
|
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424 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
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425
|
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|
426 /**
|
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427 * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
|
|
|
428 * @retval None
|
|
|
429 */
|
|
|
430 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
|
|
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431
|
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432 /**
|
|
|
433 * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
|
|
|
434 * @retval None
|
|
|
435 */
|
|
|
436 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
|
|
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437
|
|
|
438
|
|
|
439 /**
|
|
|
440 * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
|
|
|
441 * @retval None
|
|
|
442 */
|
|
|
443 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
|
|
|
444
|
|
|
445
|
|
|
446 /**
|
|
|
447 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
|
|
|
448 * @retval None
|
|
|
449 */
|
|
|
450 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
|
|
451 do { \
|
|
|
452 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
|
|
|
453 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
|
|
|
454 } while(0)
|
|
|
455
|
|
|
456 /**
|
|
|
457 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
|
|
|
458 * @retval None
|
|
|
459 */
|
|
|
460 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
|
|
461 do { \
|
|
|
462 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
|
|
|
463 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
|
|
|
464 } while(0)
|
|
|
465
|
|
|
466 /**
|
|
|
467 * @brief Generate a Software interrupt on selected EXTI line.
|
|
|
468 * @retval None
|
|
|
469 */
|
|
|
470 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
|
|
|
471
|
|
|
472 /**
|
|
|
473 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
|
|
|
474 * @retval EXTI PVM2 Line Status.
|
|
|
475 */
|
|
|
476 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
|
|
|
477
|
|
|
478 /**
|
|
|
479 * @brief Clear the PVM2 EXTI flag.
|
|
|
480 * @retval None
|
|
|
481 */
|
|
|
482 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
|
|
|
483
|
|
|
484 #endif /* PWR_CR2_PVME2 */
|
|
|
485
|
|
|
486
|
|
|
487 /**
|
|
|
488 * @brief Enable the PVM3 Extended Interrupt Line.
|
|
|
489 * @retval None
|
|
|
490 */
|
|
|
491 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
|
|
|
492
|
|
|
493 /**
|
|
|
494 * @brief Disable the PVM3 Extended Interrupt Line.
|
|
|
495 * @retval None
|
|
|
496 */
|
|
|
497 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
|
|
|
498
|
|
|
499 /**
|
|
|
500 * @brief Enable the PVM3 Event Line.
|
|
|
501 * @retval None
|
|
|
502 */
|
|
|
503 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
|
|
|
504
|
|
|
505 /**
|
|
|
506 * @brief Disable the PVM3 Event Line.
|
|
|
507 * @retval None
|
|
|
508 */
|
|
|
509 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
|
|
|
510
|
|
|
511 /**
|
|
|
512 * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
|
|
|
513 * @retval None
|
|
|
514 */
|
|
|
515 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
|
|
|
516
|
|
|
517 /**
|
|
|
518 * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
|
|
|
519 * @retval None
|
|
|
520 */
|
|
|
521 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
|
|
|
522
|
|
|
523 /**
|
|
|
524 * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
|
|
|
525 * @retval None
|
|
|
526 */
|
|
|
527 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
|
|
|
528
|
|
|
529
|
|
|
530 /**
|
|
|
531 * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
|
|
|
532 * @retval None
|
|
|
533 */
|
|
|
534 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
|
|
|
535
|
|
|
536
|
|
|
537 /**
|
|
|
538 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
|
|
|
539 * @retval None
|
|
|
540 */
|
|
|
541 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
|
|
542 do { \
|
|
|
543 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
|
|
|
544 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
|
|
|
545 } while(0)
|
|
|
546
|
|
|
547 /**
|
|
|
548 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
|
|
|
549 * @retval None
|
|
|
550 */
|
|
|
551 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
|
|
552 do { \
|
|
|
553 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
|
|
|
554 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
|
|
|
555 } while(0)
|
|
|
556
|
|
|
557 /**
|
|
|
558 * @brief Generate a Software interrupt on selected EXTI line.
|
|
|
559 * @retval None
|
|
|
560 */
|
|
|
561 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
|
|
|
562
|
|
|
563 /**
|
|
|
564 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
|
|
|
565 * @retval EXTI PVM3 Line Status.
|
|
|
566 */
|
|
|
567 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
|
|
|
568
|
|
|
569 /**
|
|
|
570 * @brief Clear the PVM3 EXTI flag.
|
|
|
571 * @retval None
|
|
|
572 */
|
|
|
573 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
|
|
|
574
|
|
|
575
|
|
|
576
|
|
|
577
|
|
|
578 /**
|
|
|
579 * @brief Enable the PVM4 Extended Interrupt Line.
|
|
|
580 * @retval None
|
|
|
581 */
|
|
|
582 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
|
|
|
583
|
|
|
584 /**
|
|
|
585 * @brief Disable the PVM4 Extended Interrupt Line.
|
|
|
586 * @retval None
|
|
|
587 */
|
|
|
588 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
|
|
|
589
|
|
|
590 /**
|
|
|
591 * @brief Enable the PVM4 Event Line.
|
|
|
592 * @retval None
|
|
|
593 */
|
|
|
594 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
|
|
|
595
|
|
|
596 /**
|
|
|
597 * @brief Disable the PVM4 Event Line.
|
|
|
598 * @retval None
|
|
|
599 */
|
|
|
600 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
|
|
|
601
|
|
|
602 /**
|
|
|
603 * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
|
|
|
604 * @retval None
|
|
|
605 */
|
|
|
606 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
|
|
|
607
|
|
|
608 /**
|
|
|
609 * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
|
|
|
610 * @retval None
|
|
|
611 */
|
|
|
612 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
|
|
|
613
|
|
|
614 /**
|
|
|
615 * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
|
|
|
616 * @retval None
|
|
|
617 */
|
|
|
618 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
|
|
|
619
|
|
|
620
|
|
|
621 /**
|
|
|
622 * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
|
|
|
623 * @retval None
|
|
|
624 */
|
|
|
625 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
|
|
|
626
|
|
|
627
|
|
|
628 /**
|
|
|
629 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
|
|
|
630 * @retval None
|
|
|
631 */
|
|
|
632 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
|
|
633 do { \
|
|
|
634 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
|
|
|
635 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
|
|
|
636 } while(0)
|
|
|
637
|
|
|
638 /**
|
|
|
639 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
|
|
|
640 * @retval None
|
|
|
641 */
|
|
|
642 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
|
|
643 do { \
|
|
|
644 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
|
|
|
645 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
|
|
|
646 } while(0)
|
|
|
647
|
|
|
648 /**
|
|
|
649 * @brief Generate a Software interrupt on selected EXTI line.
|
|
|
650 * @retval None
|
|
|
651 */
|
|
|
652 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
|
|
|
653
|
|
|
654 /**
|
|
|
655 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
|
|
|
656 * @retval EXTI PVM4 Line Status.
|
|
|
657 */
|
|
|
658 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
|
|
|
659
|
|
|
660 /**
|
|
|
661 * @brief Clear the PVM4 EXTI flag.
|
|
|
662 * @retval None
|
|
|
663 */
|
|
|
664 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
|
|
|
665
|
|
|
666
|
|
|
667 /**
|
|
|
668 * @brief Configure the main internal regulator output voltage.
|
|
|
669 * @param __REGULATOR__: specifies the regulator output voltage to achieve
|
|
|
670 * a tradeoff between performance and power consumption.
|
|
|
671 * This parameter can be one of the following values:
|
|
|
672 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
|
|
|
673 * typical output voltage at 1.2 V,
|
|
|
674 * system frequency up to 80 MHz.
|
|
|
675 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
|
|
|
676 * typical output voltage at 1.0 V,
|
|
|
677 * system frequency up to 26 MHz.
|
|
|
678 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
|
|
|
679 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User
|
|
|
680 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
|
|
|
681 * @retval None
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682 */
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683 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
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684 __IO uint32_t tmpreg; \
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685 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
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686 /* Delay after an RCC peripheral clock enabling */ \
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687 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
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688 UNUSED(tmpreg); \
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689 } while(0)
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690
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691 /**
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692 * @}
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693 */
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694
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695 /* Private macros --------------------------------------------------------*/
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696 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
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697 * @{
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698 */
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699
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700 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
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701 ((PIN) == PWR_WAKEUP_PIN2) || \
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702 ((PIN) == PWR_WAKEUP_PIN3) || \
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703 ((PIN) == PWR_WAKEUP_PIN4) || \
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704 ((PIN) == PWR_WAKEUP_PIN5) || \
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705 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
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706 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
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707 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
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708 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
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709 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
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710 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
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711 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
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712 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
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713 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
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714 ((PIN) == PWR_WAKEUP_PIN5_LOW))
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715
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716 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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717 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
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718 ((TYPE) == PWR_PVM_2) ||\
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719 ((TYPE) == PWR_PVM_3) ||\
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720 ((TYPE) == PWR_PVM_4))
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|
|
721 #elif defined (STM32L471xx)
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722 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
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723 ((TYPE) == PWR_PVM_3) ||\
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724 ((TYPE) == PWR_PVM_4))
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725 #endif
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726
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727 #if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)
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728 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
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729 ((TYPE) == PWR_PVM_3) ||\
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730 ((TYPE) == PWR_PVM_4))
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731 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)
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732 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
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733 ((TYPE) == PWR_PVM_4))
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734 #endif
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735
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736 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
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737 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\
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738 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
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|
739 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
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740 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
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|
|
741 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
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742 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
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743
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744 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
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745 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
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746
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747 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
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748 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
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|
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749
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|
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750 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
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|
|
751 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
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|
752
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753 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
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|
754
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|
|
755
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756 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
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|
757 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
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|
758 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
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759 ((GPIO) == PWR_GPIO_B) ||\
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760 ((GPIO) == PWR_GPIO_C) ||\
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761 ((GPIO) == PWR_GPIO_D) ||\
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762 ((GPIO) == PWR_GPIO_E) ||\
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763 ((GPIO) == PWR_GPIO_H))
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|
|
764 #elif defined (STM32L432xx) || defined (STM32L442xx)
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765 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
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|
|
766 ((GPIO) == PWR_GPIO_B) ||\
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767 ((GPIO) == PWR_GPIO_C) ||\
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|
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768 ((GPIO) == PWR_GPIO_H))
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|
|
769 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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770 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
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|
771 ((GPIO) == PWR_GPIO_B) ||\
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772 ((GPIO) == PWR_GPIO_C) ||\
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773 ((GPIO) == PWR_GPIO_D) ||\
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774 ((GPIO) == PWR_GPIO_E) ||\
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|
775 ((GPIO) == PWR_GPIO_F) ||\
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|
776 ((GPIO) == PWR_GPIO_G) ||\
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|
|
777 ((GPIO) == PWR_GPIO_H))
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|
778 #endif
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779
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780
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781 /**
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|
782 * @}
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|
|
783 */
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|
|
784
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|
|
785
|
|
|
786 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
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|
|
787 * @{
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|
|
788 */
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|
|
789
|
|
|
790 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
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|
791 * @{
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|
792 */
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|
793
|
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|
794
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|
|
795 /* Peripheral Control functions **********************************************/
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|
|
796 uint32_t HAL_PWREx_GetVoltageRange(void);
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|
797 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
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|
|
798 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
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|
|
799 void HAL_PWREx_DisableBatteryCharging(void);
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|
|
800 #if defined(PWR_CR2_USV)
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|
|
801 void HAL_PWREx_EnableVddUSB(void);
|
|
|
802 void HAL_PWREx_DisableVddUSB(void);
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|
803 #endif /* PWR_CR2_USV */
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|
|
804 #if defined(PWR_CR2_IOSV)
|
|
|
805 void HAL_PWREx_EnableVddIO2(void);
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|
|
806 void HAL_PWREx_DisableVddIO2(void);
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|
|
807 #endif /* PWR_CR2_IOSV */
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|
808 void HAL_PWREx_EnableInternalWakeUpLine(void);
|
|
|
809 void HAL_PWREx_DisableInternalWakeUpLine(void);
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|
|
810 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
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|
|
811 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
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|
|
812 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
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|
|
813 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
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|
|
814 void HAL_PWREx_EnablePullUpPullDownConfig(void);
|
|
|
815 void HAL_PWREx_DisablePullUpPullDownConfig(void);
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|
|
816 void HAL_PWREx_EnableSRAM2ContentRetention(void);
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|
|
817 void HAL_PWREx_DisableSRAM2ContentRetention(void);
|
|
|
818 #if defined(PWR_CR2_PVME1)
|
|
|
819 void HAL_PWREx_EnablePVM1(void);
|
|
|
820 void HAL_PWREx_DisablePVM1(void);
|
|
|
821 #endif /* PWR_CR2_PVME1 */
|
|
|
822 #if defined(PWR_CR2_PVME2)
|
|
|
823 void HAL_PWREx_EnablePVM2(void);
|
|
|
824 void HAL_PWREx_DisablePVM2(void);
|
|
|
825 #endif /* PWR_CR2_PVME2 */
|
|
|
826 void HAL_PWREx_EnablePVM3(void);
|
|
|
827 void HAL_PWREx_DisablePVM3(void);
|
|
|
828 void HAL_PWREx_EnablePVM4(void);
|
|
|
829 void HAL_PWREx_DisablePVM4(void);
|
|
|
830 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
|
|
|
831
|
|
|
832
|
|
|
833 /* Low Power modes configuration functions ************************************/
|
|
|
834 void HAL_PWREx_EnableLowPowerRunMode(void);
|
|
|
835 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
|
|
|
836 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
|
|
|
837 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
|
|
|
838 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
|
|
|
839 void HAL_PWREx_EnterSHUTDOWNMode(void);
|
|
|
840
|
|
|
841 void HAL_PWREx_PVD_PVM_IRQHandler(void);
|
|
|
842 #if defined(PWR_CR2_PVME1)
|
|
|
843 void HAL_PWREx_PVM1Callback(void);
|
|
|
844 #endif /* PWR_CR2_PVME1 */
|
|
|
845 #if defined(PWR_CR2_PVME2)
|
|
|
846 void HAL_PWREx_PVM2Callback(void);
|
|
|
847 #endif /* PWR_CR2_PVME2 */
|
|
|
848 void HAL_PWREx_PVM3Callback(void);
|
|
|
849 void HAL_PWREx_PVM4Callback(void);
|
|
|
850
|
|
|
851 /**
|
|
|
852 * @}
|
|
|
853 */
|
|
|
854
|
|
|
855 /**
|
|
|
856 * @}
|
|
|
857 */
|
|
|
858
|
|
|
859 /**
|
|
|
860 * @}
|
|
|
861 */
|
|
|
862
|
|
|
863 /**
|
|
|
864 * @}
|
|
|
865 */
|
|
|
866
|
|
|
867 #ifdef __cplusplus
|
|
|
868 }
|
|
|
869 #endif
|
|
|
870
|
|
|
871
|
|
|
872 #endif /* __STM32L4xx_HAL_PWR_EX_H */
|
|
|
873
|
|
|
874 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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