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1 /**
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2 ******************************************************************************
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3 * @file stm32l4xx_hal_rcc_ex.h
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4 * @author MCD Application Team
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5 * @version V1.6.0
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6 * @date 28-October-2016
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7 * @brief Header file of RCC HAL Extended module.
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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12 *
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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23 *
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 *
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35 ******************************************************************************
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36 */
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37
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32L4xx_HAL_RCC_EX_H
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40 #define __STM32L4xx_HAL_RCC_EX_H
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41
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42 #ifdef __cplusplus
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43 extern "C" {
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44 #endif
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32l4xx_hal_def.h"
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48
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49 /** @addtogroup STM32L4xx_HAL_Driver
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50 * @{
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51 */
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52
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53 /** @addtogroup RCCEx
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54 * @{
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55 */
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56
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57 /* Exported types ------------------------------------------------------------*/
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58
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59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
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60 * @{
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61 */
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62
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63 /**
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64 * @brief PLLSAI1 Clock structure definition
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65 */
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66 typedef struct
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67 {
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68
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69 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source.
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70 This parameter must be a value of @ref RCC_PLL_Clock_Source */
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71
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72 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
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73 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
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74
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75 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
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76 This parameter must be a number between 8 and 86 or 127 depending on devices. */
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77
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78 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock.
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79 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
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80
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81 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
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82 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
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83
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84 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock.
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85 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
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86
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87 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
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88 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
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89 }RCC_PLLSAI1InitTypeDef;
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90
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91 #if defined(RCC_PLLSAI2_SUPPORT)
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92
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93 /**
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94 * @brief PLLSAI2 Clock structure definition
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95 */
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96 typedef struct
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97 {
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98
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99 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source.
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100 This parameter must be a value of @ref RCC_PLL_Clock_Source */
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101
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102 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
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103 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
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104
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105 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
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106 This parameter must be a number between 8 and 86 or 127 depending on devices. */
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107
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108 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock.
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109 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
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110
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111 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
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112 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
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113
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114 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
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115 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
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116 }RCC_PLLSAI2InitTypeDef;
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117
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118 #endif /* RCC_PLLSAI2_SUPPORT */
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119
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120 /**
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121 * @brief RCC extended clocks structure definition
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122 */
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123 typedef struct
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124 {
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125 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
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126 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
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127
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128 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
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129 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
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130
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131 #if defined(RCC_PLLSAI2_SUPPORT)
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132
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133 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters.
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134 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
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135
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136 #endif /* RCC_PLLSAI2_SUPPORT */
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137
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138 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
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139 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
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140
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141 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
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142 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
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143
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144 #if defined(USART3)
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145
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146 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
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147 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
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148
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149 #endif /* USART3 */
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150
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151 #if defined(UART4)
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152
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153 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
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154 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
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155
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156 #endif /* UART4 */
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157
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158 #if defined(UART5)
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159
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160 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
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161 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
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162
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163 #endif /* UART5 */
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164
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165 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
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166 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
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167
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168 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
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169 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
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170
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171 #if defined(I2C2)
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172
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173 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
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174 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
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175
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176 #endif /* I2C2 */
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177
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178 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
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179 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
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180
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181 #if defined(I2C4)
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182
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183 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
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184 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
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185
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186 #endif /* I2C4 */
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187
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188 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
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189 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
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190
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191 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
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192 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
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193
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194 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
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195 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
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196
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197 #if defined(SAI2)
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198
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199 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
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200 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
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201
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202 #endif /* SAI2 */
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203
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204 #if defined(USB_OTG_FS) || defined(USB)
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205
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206 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
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207 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
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208
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209 #endif /* USB_OTG_FS || USB */
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210
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211 #if defined(SDMMC1)
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212
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213 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
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214 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
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215
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216 #endif /* SDMMC1 */
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217
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218 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
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219 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
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220
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221 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
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222 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
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223
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224 #if defined(SWPMI1)
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225
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226 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source.
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227 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
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228
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229 #endif /* SWPMI1 */
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230
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231 #if defined(DFSDM1_Filter0)
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232
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233 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source.
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234 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
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235
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236 #endif /* DFSDM1_Filter0 */
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237
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238 uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
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239 This parameter can be a value of @ref RCC_RTC_Clock_Source */
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240 }RCC_PeriphCLKInitTypeDef;
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241
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242 #if defined(CRS)
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243
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244 /**
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245 * @brief RCC_CRS Init structure definition
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246 */
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247 typedef struct
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248 {
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249 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
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250 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
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251
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252 uint32_t Source; /*!< Specifies the SYNC signal source.
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253 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
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254
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255 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
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256 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
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257
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258 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
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259 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
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260 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
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261
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262 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
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263 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
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264
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265 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
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266 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
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267
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268 }RCC_CRSInitTypeDef;
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269
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270 /**
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271 * @brief RCC_CRS Synchronization structure definition
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272 */
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273 typedef struct
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274 {
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275 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
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276 This parameter must be a number between 0 and 0xFFFF */
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277
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278 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
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279 This parameter must be a number between 0 and 0x3F */
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280
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281 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
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282 value latched in the time of the last SYNC event.
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283 This parameter must be a number between 0 and 0xFFFF */
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284
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285 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
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286 frequency error counter latched in the time of the last SYNC event.
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287 It shows whether the actual frequency is below or above the target.
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288 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
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289
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290 }RCC_CRSSynchroInfoTypeDef;
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291
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292 #endif /* CRS */
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293 /**
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294 * @}
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295 */
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296
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297 /* Exported constants --------------------------------------------------------*/
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298 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
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299 * @{
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300 */
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301
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302 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
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303 * @{
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304 */
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305 #define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */
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306 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
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307 /**
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308 * @}
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309 */
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310
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311 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
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312 * @{
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313 */
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314 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
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315 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
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316 #if defined(USART3)
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317 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U)
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318 #endif
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319 #if defined(UART4)
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320 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U)
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321 #endif
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322 #if defined(UART5)
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323 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U)
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324 #endif
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325 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U)
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326 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U)
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327 #if defined(I2C2)
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328 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U)
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329 #endif
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330 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
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331 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U)
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332 #define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U)
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333 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U)
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334 #if defined(SAI2)
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335 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U)
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336 #endif
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337 #if defined(USB_OTG_FS) || defined(USB)
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338 #define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U)
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339 #endif
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340 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U)
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341 #if defined(SWPMI1)
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342 #define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U)
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343 #endif
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344 #if defined(DFSDM1_Filter0)
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345 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U)
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346 #endif
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347 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U)
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348 #define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U)
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349 #if defined(SDMMC1)
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350 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U)
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351 #endif
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352 #if defined(I2C4)
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353 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00100000U)
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354 #endif
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355 /**
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356 * @}
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357 */
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358
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359
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360 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
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361 * @{
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362 */
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363 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
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364 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
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365 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
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366 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
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367 /**
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368 * @}
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369 */
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370
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371 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
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372 * @{
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373 */
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374 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
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375 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
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376 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
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377 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
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378 /**
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379 * @}
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380 */
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381
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382 #if defined(USART3)
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383 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
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384 * @{
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385 */
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386 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
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387 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
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388 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
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389 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
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390 /**
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391 * @}
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392 */
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393 #endif /* USART3 */
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394
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395 #if defined(UART4)
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396 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
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397 * @{
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398 */
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399 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
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400 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
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401 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
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402 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
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403 /**
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404 * @}
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405 */
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406 #endif /* UART4 */
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407
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408 #if defined(UART5)
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409 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
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410 * @{
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411 */
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412 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
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413 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
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414 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
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415 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
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416 /**
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417 * @}
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418 */
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419 #endif /* UART5 */
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420
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421 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
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422 * @{
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423 */
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424 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
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425 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
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426 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
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427 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
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428 /**
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429 * @}
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430 */
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431
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432 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
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433 * @{
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434 */
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435 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
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436 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
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437 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
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438 /**
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439 * @}
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440 */
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441
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442 #if defined(I2C2)
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443 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
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444 * @{
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445 */
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446 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
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447 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
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448 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
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449 /**
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450 * @}
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451 */
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452 #endif /* I2C2 */
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453
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454 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
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455 * @{
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456 */
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457 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
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458 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
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459 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
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460 /**
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461 * @}
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462 */
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463
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464 #if defined(I2C4)
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465 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
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466 * @{
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467 */
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468 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
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469 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
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470 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
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471 /**
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472 * @}
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473 */
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474 #endif /* I2C4 */
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475
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476 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
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477 * @{
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478 */
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479 #define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
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480 #if defined(RCC_PLLSAI2_SUPPORT)
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481 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
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482 #endif /* RCC_PLLSAI2_SUPPORT */
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483 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
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484 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
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485 /**
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486 * @}
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487 */
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488
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489 #if defined(SAI2)
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490 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
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491 * @{
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492 */
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493 #define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
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494 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
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495 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
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496 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
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497 /**
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|
498 * @}
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499 */
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500 #endif /* SAI2 */
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501
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502 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
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503 * @{
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504 */
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505 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
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|
506 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
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507 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
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508 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
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509 /**
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|
510 * @}
|
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|
511 */
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|
512
|
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|
513 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
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514 * @{
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515 */
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516 #define RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000U)
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517 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
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518 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
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|
519 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
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520 /**
|
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521 * @}
|
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|
522 */
|
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523
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524 #if defined(SDMMC1)
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|
525 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
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526 * @{
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|
|
527 */
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|
528 #if defined(RCC_HSI48_SUPPORT)
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|
529 #define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U)
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|
530 #else
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|
|
531 #define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U)
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|
532 #endif /* RCC_HSI48_SUPPORT */
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|
533 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
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|
534 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
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|
535 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
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|
536 /**
|
|
|
537 * @}
|
|
|
538 */
|
|
|
539 #endif /* SDMMC1 */
|
|
|
540
|
|
|
541 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
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|
|
542 * @{
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|
|
543 */
|
|
|
544 #if defined(RCC_HSI48_SUPPORT)
|
|
|
545 #define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
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|
546 #else
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|
547 #define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U)
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|
548 #endif /* RCC_HSI48_SUPPORT */
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|
|
549 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
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|
|
550 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
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|
551 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
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|
|
552 /**
|
|
|
553 * @}
|
|
|
554 */
|
|
|
555
|
|
|
556 #if defined(USB_OTG_FS) || defined(USB)
|
|
|
557 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
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|
|
558 * @{
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|
|
559 */
|
|
|
560 #if defined(RCC_HSI48_SUPPORT)
|
|
|
561 #define RCC_USBCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
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|
|
562 #else
|
|
|
563 #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U)
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|
|
564 #endif /* RCC_HSI48_SUPPORT */
|
|
|
565 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
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|
|
566 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
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|
|
567 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
|
|
|
568 /**
|
|
|
569 * @}
|
|
|
570 */
|
|
|
571 #endif /* USB_OTG_FS || USB */
|
|
|
572
|
|
|
573 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
|
|
|
574 * @{
|
|
|
575 */
|
|
|
576 #define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U)
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|
|
577 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
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|
|
578 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
|
579 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
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|
|
580 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
581 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
|
|
|
582 /**
|
|
|
583 * @}
|
|
|
584 */
|
|
|
585
|
|
|
586 #if defined(SWPMI1)
|
|
|
587 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
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|
|
588 * @{
|
|
|
589 */
|
|
|
590 #define RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
|
|
|
591 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
|
|
|
592 /**
|
|
|
593 * @}
|
|
|
594 */
|
|
|
595 #endif /* SWPMI1 */
|
|
|
596
|
|
|
597 #if defined(DFSDM1_Filter0)
|
|
|
598 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
|
|
|
599 * @{
|
|
|
600 */
|
|
|
601 #define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
|
|
|
602 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
|
|
|
603 /**
|
|
|
604 * @}
|
|
|
605 */
|
|
|
606 #endif /* DFSDM1_Filter0 */
|
|
|
607
|
|
|
608 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
|
|
|
609 * @{
|
|
|
610 */
|
|
|
611 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
|
|
|
612 /**
|
|
|
613 * @}
|
|
|
614 */
|
|
|
615
|
|
|
616 #if defined(CRS)
|
|
|
617
|
|
|
618 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
|
|
|
619 * @{
|
|
|
620 */
|
|
|
621 #define RCC_CRS_NONE ((uint32_t)0x00000000U)
|
|
|
622 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U)
|
|
|
623 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002U)
|
|
|
624 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U)
|
|
|
625 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008U)
|
|
|
626 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U)
|
|
|
627 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U)
|
|
|
628 /**
|
|
|
629 * @}
|
|
|
630 */
|
|
|
631
|
|
|
632 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
|
|
|
633 * @{
|
|
|
634 */
|
|
|
635 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
|
|
|
636 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
|
|
|
637 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
|
|
|
638 /**
|
|
|
639 * @}
|
|
|
640 */
|
|
|
641
|
|
|
642 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
|
|
|
643 * @{
|
|
|
644 */
|
|
|
645 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */
|
|
|
646 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
|
|
|
647 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
|
|
|
648 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
|
|
|
649 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
|
|
|
650 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
|
|
|
651 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
|
|
|
652 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
|
|
|
653 /**
|
|
|
654 * @}
|
|
|
655 */
|
|
|
656
|
|
|
657 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
|
|
|
658 * @{
|
|
|
659 */
|
|
|
660 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
|
|
|
661 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
|
|
|
662 /**
|
|
|
663 * @}
|
|
|
664 */
|
|
|
665
|
|
|
666 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
|
|
|
667 * @{
|
|
|
668 */
|
|
|
669 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
|
|
|
670 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
|
|
|
671 /**
|
|
|
672 * @}
|
|
|
673 */
|
|
|
674
|
|
|
675 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
|
|
|
676 * @{
|
|
|
677 */
|
|
|
678 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
|
|
|
679 /**
|
|
|
680 * @}
|
|
|
681 */
|
|
|
682
|
|
|
683 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
|
|
|
684 * @{
|
|
|
685 */
|
|
|
686 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
|
|
|
687 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
|
|
|
688 corresponds to a higher output frequency */
|
|
|
689 /**
|
|
|
690 * @}
|
|
|
691 */
|
|
|
692
|
|
|
693 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
|
|
|
694 * @{
|
|
|
695 */
|
|
|
696 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */
|
|
|
697 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
|
|
|
698 /**
|
|
|
699 * @}
|
|
|
700 */
|
|
|
701
|
|
|
702 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
|
|
|
703 * @{
|
|
|
704 */
|
|
|
705 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
|
|
|
706 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
|
|
|
707 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
|
|
|
708 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
|
|
|
709 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
|
|
|
710 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
|
|
|
711 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
|
|
|
712
|
|
|
713 /**
|
|
|
714 * @}
|
|
|
715 */
|
|
|
716
|
|
|
717 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
|
|
|
718 * @{
|
|
|
719 */
|
|
|
720 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
|
|
|
721 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
|
|
|
722 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
|
|
|
723 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
|
|
|
724 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
|
|
|
725 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
|
|
|
726 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
|
|
|
727
|
|
|
728 /**
|
|
|
729 * @}
|
|
|
730 */
|
|
|
731
|
|
|
732 #endif /* CRS */
|
|
|
733
|
|
|
734 /**
|
|
|
735 * @}
|
|
|
736 */
|
|
|
737
|
|
|
738 /* Exported macros -----------------------------------------------------------*/
|
|
|
739 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
|
|
|
740 * @{
|
|
|
741 */
|
|
|
742
|
|
|
743
|
|
|
744 /**
|
|
|
745 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
|
|
|
746 *
|
|
|
747 * @note This function must be used only when the PLLSAI1 is disabled.
|
|
|
748 * @note PLLSAI1 clock source is common with the main PLL (configured through
|
|
|
749 * __HAL_RCC_PLL_CONFIG() macro)
|
|
|
750 *
|
|
|
751 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
|
|
|
752 * This parameter must be a number between 8 and 86.
|
|
|
753 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
|
|
|
754 * output frequency is between 64 and 344 MHz.
|
|
|
755 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
|
|
|
756 *
|
|
|
757 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
|
|
|
758 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
|
|
|
759 * else (2 to 31).
|
|
|
760 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
|
|
|
761 *
|
|
|
762 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
|
|
|
763 * This parameter must be in the range (2, 4, 6 or 8).
|
|
|
764 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
|
|
|
765 *
|
|
|
766 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock.
|
|
|
767 * This parameter must be in the range (2, 4, 6 or 8).
|
|
|
768 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R
|
|
|
769 *
|
|
|
770 * @retval None
|
|
|
771 */
|
|
|
772 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
|
|
|
773
|
|
|
774 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
|
|
|
775 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
|
|
|
776 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
|
|
|
777 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
|
|
|
778 ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
|
|
|
779
|
|
|
780 #else
|
|
|
781
|
|
|
782 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
|
|
|
783 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
|
|
|
784 (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
|
|
|
785 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
|
|
|
786 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
|
|
|
787
|
|
|
788 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
789
|
|
|
790 /**
|
|
|
791 * @brief Macro to configure the PLLSAI1 clock multiplication factor N.
|
|
|
792 *
|
|
|
793 * @note This function must be used only when the PLLSAI1 is disabled.
|
|
|
794 * @note PLLSAI1 clock source is common with the main PLL (configured through
|
|
|
795 * __HAL_RCC_PLL_CONFIG() macro)
|
|
|
796 *
|
|
|
797 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
|
|
|
798 * This parameter must be a number between 8 and 86.
|
|
|
799 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
|
|
|
800 * output frequency is between 64 and 344 MHz.
|
|
|
801 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
|
|
|
802 *
|
|
|
803 * @retval None
|
|
|
804 */
|
|
|
805 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
|
|
|
806 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
|
|
|
807
|
|
|
808 /** @brief Macro to configure the PLLSAI1 clock division factor P.
|
|
|
809 *
|
|
|
810 * @note This function must be used only when the PLLSAI1 is disabled.
|
|
|
811 * @note PLLSAI1 clock source is common with the main PLL (configured through
|
|
|
812 * __HAL_RCC_PLL_CONFIG() macro)
|
|
|
813 *
|
|
|
814 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
|
|
|
815 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
|
|
|
816 * else (2 to 31).
|
|
|
817 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
|
|
|
818 *
|
|
|
819 * @retval None
|
|
|
820 */
|
|
|
821 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
|
|
|
822
|
|
|
823 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
|
|
|
824 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
|
|
|
825
|
|
|
826 #else
|
|
|
827
|
|
|
828 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
|
|
|
829 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
|
|
|
830
|
|
|
831 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
832
|
|
|
833 /** @brief Macro to configure the PLLSAI1 clock division factor Q.
|
|
|
834 *
|
|
|
835 * @note This function must be used only when the PLLSAI1 is disabled.
|
|
|
836 * @note PLLSAI1 clock source is common with the main PLL (configured through
|
|
|
837 * __HAL_RCC_PLL_CONFIG() macro)
|
|
|
838 *
|
|
|
839 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
|
|
|
840 * This parameter must be in the range (2, 4, 6 or 8).
|
|
|
841 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
|
|
|
842 *
|
|
|
843 * @retval None
|
|
|
844 */
|
|
|
845 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
|
|
|
846 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
|
|
|
847
|
|
|
848 /** @brief Macro to configure the PLLSAI1 clock division factor R.
|
|
|
849 *
|
|
|
850 * @note This function must be used only when the PLLSAI1 is disabled.
|
|
|
851 * @note PLLSAI1 clock source is common with the main PLL (configured through
|
|
|
852 * __HAL_RCC_PLL_CONFIG() macro)
|
|
|
853 *
|
|
|
854 * @param __PLLSAI1R__ specifies the division factor for ADC clock.
|
|
|
855 * This parameter must be in the range (2, 4, 6 or 8)
|
|
|
856 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
|
|
|
857 *
|
|
|
858 * @retval None
|
|
|
859 */
|
|
|
860 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
|
|
|
861 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
|
|
|
862
|
|
|
863 /**
|
|
|
864 * @brief Macros to enable or disable the PLLSAI1.
|
|
|
865 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
|
|
|
866 * @retval None
|
|
|
867 */
|
|
|
868
|
|
|
869 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
|
|
|
870
|
|
|
871 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
|
|
|
872
|
|
|
873 /**
|
|
|
874 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
|
|
|
875 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
|
|
|
876 * This is mainly used to save Power.
|
|
|
877 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
|
|
|
878 * This parameter can be one or a combination of the following values:
|
|
|
879 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
|
|
|
880 * high-quality audio performance on SAI interface in case.
|
|
|
881 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
|
|
|
882 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
|
|
|
883 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
|
|
|
884 * @retval None
|
|
|
885 */
|
|
|
886
|
|
|
887 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
|
|
|
888
|
|
|
889 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
|
|
|
890
|
|
|
891 /**
|
|
|
892 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
|
|
|
893 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
|
|
|
894 * This parameter can be one of the following values:
|
|
|
895 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
|
|
|
896 * high-quality audio performance on SAI interface in case.
|
|
|
897 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
|
|
|
898 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
|
|
|
899 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
|
|
|
900 * @retval SET / RESET
|
|
|
901 */
|
|
|
902 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
|
|
|
903
|
|
|
904 #if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
905
|
|
|
906 /**
|
|
|
907 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors.
|
|
|
908 *
|
|
|
909 * @note This function must be used only when the PLLSAI2 is disabled.
|
|
|
910 * @note PLLSAI2 clock source is common with the main PLL (configured through
|
|
|
911 * __HAL_RCC_PLL_CONFIG() macro)
|
|
|
912 *
|
|
|
913 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
|
|
|
914 * This parameter must be a number between 8 and 86.
|
|
|
915 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
|
|
|
916 * output frequency is between 64 and 344 MHz.
|
|
|
917 *
|
|
|
918 * @param __PLLSAI2P__ specifies the division factor for SAI clock.
|
|
|
919 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
|
|
|
920 * else (2 to 31).
|
|
|
921 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
|
|
|
922 *
|
|
|
923 * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock.
|
|
|
924 * This parameter must be in the range (2, 4, 6 or 8).
|
|
|
925 *
|
|
|
926 * @retval None
|
|
|
927 */
|
|
|
928
|
|
|
929 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
|
|
|
930
|
|
|
931 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
|
|
|
932 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
|
|
|
933 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
|
|
|
934 ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
|
|
|
935
|
|
|
936 #else
|
|
|
937
|
|
|
938 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
|
|
|
939 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
|
|
|
940 (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
|
|
|
941 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
|
|
|
942
|
|
|
943 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
|
|
|
944
|
|
|
945
|
|
|
946 /**
|
|
|
947 * @brief Macro to configure the PLLSAI2 clock multiplication factor N.
|
|
|
948 *
|
|
|
949 * @note This function must be used only when the PLLSAI2 is disabled.
|
|
|
950 * @note PLLSAI2 clock source is common with the main PLL (configured through
|
|
|
951 * __HAL_RCC_PLL_CONFIG() macro)
|
|
|
952 *
|
|
|
953 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
|
|
|
954 * This parameter must be a number between 8 and 86.
|
|
|
955 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
|
|
|
956 * output frequency is between 64 and 344 MHz.
|
|
|
957 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
|
|
|
958 *
|
|
|
959 * @retval None
|
|
|
960 */
|
|
|
961 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
|
|
|
962 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
|
|
|
963
|
|
|
964 /** @brief Macro to configure the PLLSAI2 clock division factor P.
|
|
|
965 *
|
|
|
966 * @note This function must be used only when the PLLSAI2 is disabled.
|
|
|
967 * @note PLLSAI2 clock source is common with the main PLL (configured through
|
|
|
968 * __HAL_RCC_PLL_CONFIG() macro)
|
|
|
969 *
|
|
|
970 * @param __PLLSAI2P__ specifies the division factor.
|
|
|
971 * This parameter must be a number in the range (7 or 17).
|
|
|
972 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
|
|
|
973 *
|
|
|
974 * @retval None
|
|
|
975 */
|
|
|
976 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
|
|
|
977 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
|
|
|
978
|
|
|
979 /** @brief Macro to configure the PLLSAI2 clock division factor R.
|
|
|
980 *
|
|
|
981 * @note This function must be used only when the PLLSAI2 is disabled.
|
|
|
982 * @note PLLSAI2 clock source is common with the main PLL (configured through
|
|
|
983 * __HAL_RCC_PLL_CONFIG() macro)
|
|
|
984 *
|
|
|
985 * @param __PLLSAI2R__ specifies the division factor.
|
|
|
986 * This parameter must be in the range (2, 4, 6 or 8).
|
|
|
987 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
|
|
|
988 *
|
|
|
989 * @retval None
|
|
|
990 */
|
|
|
991 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
|
|
|
992 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
|
|
|
993
|
|
|
994 /**
|
|
|
995 * @brief Macros to enable or disable the PLLSAI2.
|
|
|
996 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
|
|
|
997 * @retval None
|
|
|
998 */
|
|
|
999
|
|
|
1000 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
|
|
|
1001
|
|
|
1002 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
|
|
|
1003
|
|
|
1004 /**
|
|
|
1005 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
|
|
|
1006 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
|
|
|
1007 * This is mainly used to save Power.
|
|
|
1008 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
|
|
|
1009 * This parameter can be one or a combination of the following values:
|
|
|
1010 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
|
|
|
1011 * high-quality audio performance on SAI interface in case.
|
|
|
1012 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
|
|
|
1013 * @retval None
|
|
|
1014 */
|
|
|
1015
|
|
|
1016 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
|
|
|
1017
|
|
|
1018 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
|
|
|
1019
|
|
|
1020 /**
|
|
|
1021 * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
|
|
|
1022 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
|
|
|
1023 * This parameter can be one of the following values:
|
|
|
1024 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
|
|
|
1025 * high-quality audio performance on SAI interface in case.
|
|
|
1026 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
|
|
|
1027 * @retval SET / RESET
|
|
|
1028 */
|
|
|
1029 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
|
|
|
1030
|
|
|
1031 #endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
1032
|
|
|
1033 /**
|
|
|
1034 * @brief Macro to configure the SAI1 clock source.
|
|
|
1035 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
|
|
|
1036 * from the PLLSAI1, system PLL or external clock (through a dedicated pin).
|
|
|
1037 * This parameter can be one of the following values:
|
|
|
1038 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
|
|
|
1039 @if STM32L486xx
|
|
|
1040 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
|
|
|
1041 @endif
|
|
|
1042 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
|
|
|
1043 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
|
|
|
1044 *
|
|
|
1045 @if STM32L443xx
|
|
|
1046 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
|
|
|
1047 @endif
|
|
|
1048 @if STM32L462xx
|
|
|
1049 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
|
|
|
1050 @endif
|
|
|
1051 *
|
|
|
1052 * @retval None
|
|
|
1053 */
|
|
|
1054 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
|
|
|
1055 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
|
|
|
1056
|
|
|
1057 /** @brief Macro to get the SAI1 clock source.
|
|
|
1058 * @retval The clock source can be one of the following values:
|
|
|
1059 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
|
|
|
1060 @if STM32L486xx
|
|
|
1061 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
|
|
|
1062 @endif
|
|
|
1063 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
|
|
|
1064 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
|
|
|
1065 *
|
|
|
1066 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
|
|
|
1067 * clock source when PLLs are disabled for devices without PLLSAI2.
|
|
|
1068 *
|
|
|
1069 */
|
|
|
1070 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
|
|
|
1071
|
|
|
1072 #if defined(SAI2)
|
|
|
1073
|
|
|
1074 /**
|
|
|
1075 * @brief Macro to configure the SAI2 clock source.
|
|
|
1076 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
|
|
|
1077 * from the PLLSAI2, system PLL or external clock (through a dedicated pin).
|
|
|
1078 * This parameter can be one of the following values:
|
|
|
1079 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
|
|
|
1080 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
|
|
|
1081 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
|
|
|
1082 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
|
|
|
1083 *
|
|
|
1084 * @retval None
|
|
|
1085 */
|
|
|
1086 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
|
|
|
1087 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
|
|
|
1088
|
|
|
1089 /** @brief Macro to get the SAI2 clock source.
|
|
|
1090 * @retval The clock source can be one of the following values:
|
|
|
1091 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
|
|
|
1092 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
|
|
|
1093 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
|
|
|
1094 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
|
|
|
1095 */
|
|
|
1096 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
|
|
|
1097
|
|
|
1098 #endif /* SAI2 */
|
|
|
1099
|
|
|
1100 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
|
|
|
1101 *
|
|
|
1102 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
|
|
|
1103 * This parameter can be one of the following values:
|
|
|
1104 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
|
|
|
1105 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
|
|
|
1106 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
|
|
|
1107 * @retval None
|
|
|
1108 */
|
|
|
1109 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
|
|
|
1110 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
|
|
|
1111
|
|
|
1112 /** @brief Macro to get the I2C1 clock source.
|
|
|
1113 * @retval The clock source can be one of the following values:
|
|
|
1114 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
|
|
|
1115 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
|
|
|
1116 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
|
|
|
1117 */
|
|
|
1118 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
|
|
|
1119
|
|
|
1120 #if defined(I2C2)
|
|
|
1121
|
|
|
1122 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
|
|
|
1123 *
|
|
|
1124 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
|
|
|
1125 * This parameter can be one of the following values:
|
|
|
1126 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
|
|
|
1127 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
|
|
|
1128 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
|
|
|
1129 * @retval None
|
|
|
1130 */
|
|
|
1131 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
|
|
|
1132 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
|
|
|
1133
|
|
|
1134 /** @brief Macro to get the I2C2 clock source.
|
|
|
1135 * @retval The clock source can be one of the following values:
|
|
|
1136 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
|
|
|
1137 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
|
|
|
1138 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
|
|
|
1139 */
|
|
|
1140 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
|
|
|
1141
|
|
|
1142 #endif /* I2C2 */
|
|
|
1143
|
|
|
1144 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
|
|
|
1145 *
|
|
|
1146 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
|
|
|
1147 * This parameter can be one of the following values:
|
|
|
1148 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
|
|
|
1149 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
|
|
|
1150 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
|
|
|
1151 * @retval None
|
|
|
1152 */
|
|
|
1153 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
|
|
|
1154 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
|
|
|
1155
|
|
|
1156 /** @brief Macro to get the I2C3 clock source.
|
|
|
1157 * @retval The clock source can be one of the following values:
|
|
|
1158 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
|
|
|
1159 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
|
|
|
1160 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
|
|
|
1161 */
|
|
|
1162 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
|
|
|
1163
|
|
|
1164 #if defined(I2C4)
|
|
|
1165
|
|
|
1166 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
|
|
|
1167 *
|
|
|
1168 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
|
|
|
1169 * This parameter can be one of the following values:
|
|
|
1170 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
|
|
|
1171 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
|
|
|
1172 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
|
|
|
1173 * @retval None
|
|
|
1174 */
|
|
|
1175 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
|
|
|
1176 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
|
|
|
1177
|
|
|
1178 /** @brief Macro to get the I2C4 clock source.
|
|
|
1179 * @retval The clock source can be one of the following values:
|
|
|
1180 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
|
|
|
1181 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
|
|
|
1182 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
|
|
|
1183 */
|
|
|
1184 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)))
|
|
|
1185
|
|
|
1186 #endif /* I2C4 */
|
|
|
1187
|
|
|
1188
|
|
|
1189 /** @brief Macro to configure the USART1 clock (USART1CLK).
|
|
|
1190 *
|
|
|
1191 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
|
|
|
1192 * This parameter can be one of the following values:
|
|
|
1193 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
|
|
|
1194 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
|
|
|
1195 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
|
|
|
1196 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock
|
|
|
1197 * @retval None
|
|
|
1198 */
|
|
|
1199 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
|
|
|
1200 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
|
|
|
1201
|
|
|
1202 /** @brief Macro to get the USART1 clock source.
|
|
|
1203 * @retval The clock source can be one of the following values:
|
|
|
1204 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
|
|
|
1205 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
|
|
|
1206 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
|
|
|
1207 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
|
|
|
1208 */
|
|
|
1209 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
|
|
|
1210
|
|
|
1211 /** @brief Macro to configure the USART2 clock (USART2CLK).
|
|
|
1212 *
|
|
|
1213 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
|
|
|
1214 * This parameter can be one of the following values:
|
|
|
1215 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
|
|
|
1216 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
|
|
|
1217 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
|
|
|
1218 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
|
|
|
1219 * @retval None
|
|
|
1220 */
|
|
|
1221 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
|
|
|
1222 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
|
|
|
1223
|
|
|
1224 /** @brief Macro to get the USART2 clock source.
|
|
|
1225 * @retval The clock source can be one of the following values:
|
|
|
1226 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
|
|
|
1227 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
|
|
|
1228 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
|
|
|
1229 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
|
|
|
1230 */
|
|
|
1231 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
|
|
|
1232
|
|
|
1233 #if defined(USART3)
|
|
|
1234
|
|
|
1235 /** @brief Macro to configure the USART3 clock (USART3CLK).
|
|
|
1236 *
|
|
|
1237 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
|
|
|
1238 * This parameter can be one of the following values:
|
|
|
1239 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
|
|
|
1240 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
|
|
|
1241 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
|
|
|
1242 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
|
|
|
1243 * @retval None
|
|
|
1244 */
|
|
|
1245 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
|
|
|
1246 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
|
|
|
1247
|
|
|
1248 /** @brief Macro to get the USART3 clock source.
|
|
|
1249 * @retval The clock source can be one of the following values:
|
|
|
1250 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
|
|
|
1251 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
|
|
|
1252 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
|
|
|
1253 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
|
|
|
1254 */
|
|
|
1255 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
|
|
|
1256
|
|
|
1257 #endif /* USART3 */
|
|
|
1258
|
|
|
1259 #if defined(UART4)
|
|
|
1260
|
|
|
1261 /** @brief Macro to configure the UART4 clock (UART4CLK).
|
|
|
1262 *
|
|
|
1263 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
|
|
|
1264 * This parameter can be one of the following values:
|
|
|
1265 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
|
|
|
1266 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
|
|
|
1267 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
|
|
|
1268 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
|
|
|
1269 * @retval None
|
|
|
1270 */
|
|
|
1271 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
|
|
|
1272 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
|
|
|
1273
|
|
|
1274 /** @brief Macro to get the UART4 clock source.
|
|
|
1275 * @retval The clock source can be one of the following values:
|
|
|
1276 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
|
|
|
1277 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
|
|
|
1278 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
|
|
|
1279 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
|
|
|
1280 */
|
|
|
1281 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
|
|
|
1282
|
|
|
1283 #endif /* UART4 */
|
|
|
1284
|
|
|
1285 #if defined(UART5)
|
|
|
1286
|
|
|
1287 /** @brief Macro to configure the UART5 clock (UART5CLK).
|
|
|
1288 *
|
|
|
1289 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
|
|
|
1290 * This parameter can be one of the following values:
|
|
|
1291 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
|
|
|
1292 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
|
|
|
1293 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
|
|
|
1294 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
|
|
|
1295 * @retval None
|
|
|
1296 */
|
|
|
1297 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
|
|
|
1298 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
|
|
|
1299
|
|
|
1300 /** @brief Macro to get the UART5 clock source.
|
|
|
1301 * @retval The clock source can be one of the following values:
|
|
|
1302 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
|
|
|
1303 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
|
|
|
1304 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
|
|
|
1305 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
|
|
|
1306 */
|
|
|
1307 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
|
|
|
1308
|
|
|
1309 #endif /* UART5 */
|
|
|
1310
|
|
|
1311 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
|
|
|
1312 *
|
|
|
1313 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
|
|
|
1314 * This parameter can be one of the following values:
|
|
|
1315 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
|
|
|
1316 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
|
|
|
1317 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
|
|
|
1318 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
|
|
|
1319 * @retval None
|
|
|
1320 */
|
|
|
1321 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
|
|
|
1322 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
|
|
|
1323
|
|
|
1324 /** @brief Macro to get the LPUART1 clock source.
|
|
|
1325 * @retval The clock source can be one of the following values:
|
|
|
1326 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
|
|
|
1327 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
|
|
|
1328 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
|
|
|
1329 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
|
|
|
1330 */
|
|
|
1331 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
|
|
|
1332
|
|
|
1333 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
|
|
|
1334 *
|
|
|
1335 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
|
|
|
1336 * This parameter can be one of the following values:
|
|
|
1337 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPTIM1 clock
|
|
|
1338 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
|
|
|
1339 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
|
|
|
1340 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
|
|
|
1341 * @retval None
|
|
|
1342 */
|
|
|
1343 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
|
|
|
1344 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
|
|
|
1345
|
|
|
1346 /** @brief Macro to get the LPTIM1 clock source.
|
|
|
1347 * @retval The clock source can be one of the following values:
|
|
|
1348 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPUART1 clock
|
|
|
1349 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
|
|
|
1350 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
|
|
|
1351 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
|
|
|
1352 */
|
|
|
1353 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
|
|
|
1354
|
|
|
1355 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
|
|
|
1356 *
|
|
|
1357 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
|
|
|
1358 * This parameter can be one of the following values:
|
|
|
1359 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPTIM2 clock
|
|
|
1360 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
|
|
|
1361 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
|
|
|
1362 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
|
|
|
1363 * @retval None
|
|
|
1364 */
|
|
|
1365 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
|
|
|
1366 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
|
|
|
1367
|
|
|
1368 /** @brief Macro to get the LPTIM2 clock source.
|
|
|
1369 * @retval The clock source can be one of the following values:
|
|
|
1370 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPUART1 clock
|
|
|
1371 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock
|
|
|
1372 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
|
|
|
1373 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock
|
|
|
1374 */
|
|
|
1375 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
|
|
|
1376
|
|
|
1377 #if defined(SDMMC1)
|
|
|
1378
|
|
|
1379 /** @brief Macro to configure the SDMMC1 clock.
|
|
|
1380 *
|
|
|
1381 @if STM32L443xx
|
|
|
1382 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
|
|
|
1383 @endif
|
|
|
1384 @if STM32L462xx
|
|
|
1385 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
|
|
|
1386 @endif
|
|
|
1387 @if STM32L486xx
|
|
|
1388 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
|
|
|
1389 @endif
|
|
|
1390 *
|
|
|
1391 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
|
|
|
1392 * This parameter can be one of the following values:
|
|
|
1393 @if STM32L443xx
|
|
|
1394 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
|
|
|
1395 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
|
|
|
1396 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
|
|
|
1397 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
|
|
|
1398 @endif
|
|
|
1399 @if STM32L462xx
|
|
|
1400 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
|
|
|
1401 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
|
|
|
1402 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
|
|
|
1403 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
|
|
|
1404 @endif
|
|
|
1405 @if STM32L486xx
|
|
|
1406 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
|
|
|
1407 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
|
|
|
1408 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
|
|
|
1409 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
|
|
|
1410 @endif
|
|
|
1411 * @retval None
|
|
|
1412 */
|
|
|
1413 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
|
|
|
1414 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
|
|
|
1415
|
|
|
1416 /** @brief Macro to get the SDMMC1 clock.
|
|
|
1417 * @retval The clock source can be one of the following values:
|
|
|
1418 @if STM32L443xx
|
|
|
1419 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
|
|
|
1420 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
|
|
|
1421 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
|
|
|
1422 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
|
|
|
1423 @endif
|
|
|
1424 @if STM32L462xx
|
|
|
1425 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
|
|
|
1426 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
|
|
|
1427 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
|
|
|
1428 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
|
|
|
1429 @endif
|
|
|
1430 @if STM32L486xx
|
|
|
1431 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
|
|
|
1432 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
|
|
|
1433 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
|
|
|
1434 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
|
|
|
1435 @endif
|
|
|
1436 */
|
|
|
1437 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
|
|
|
1438
|
|
|
1439 #endif /* SDMMC1 */
|
|
|
1440
|
|
|
1441 /** @brief Macro to configure the RNG clock.
|
|
|
1442 *
|
|
|
1443 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
|
|
|
1444 *
|
|
|
1445 * @param __RNG_CLKSOURCE__ specifies the RNG clock source.
|
|
|
1446 * This parameter can be one of the following values:
|
|
|
1447 @if STM32L443xx
|
|
|
1448 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
|
|
|
1449 @endif
|
|
|
1450 @if STM32L462xx
|
|
|
1451 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
|
|
|
1452 @endif
|
|
|
1453 @if STM32L486xx
|
|
|
1454 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
|
|
|
1455 @endif
|
|
|
1456 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
|
|
|
1457 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
|
|
|
1458 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
|
|
|
1459 * @retval None
|
|
|
1460 */
|
|
|
1461 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
|
|
|
1462 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
|
|
|
1463
|
|
|
1464 /** @brief Macro to get the RNG clock.
|
|
|
1465 * @retval The clock source can be one of the following values:
|
|
|
1466 @if STM32L443xx
|
|
|
1467 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
|
|
|
1468 @endif
|
|
|
1469 @if STM32L462xx
|
|
|
1470 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
|
|
|
1471 @endif
|
|
|
1472 @if STM32L486xx
|
|
|
1473 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
|
|
|
1474 @endif
|
|
|
1475 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
|
|
|
1476 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
|
|
|
1477 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock
|
|
|
1478 */
|
|
|
1479 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
|
|
|
1480
|
|
|
1481 #if defined(USB_OTG_FS) || defined(USB)
|
|
|
1482
|
|
|
1483 /** @brief Macro to configure the USB clock (USBCLK).
|
|
|
1484 *
|
|
|
1485 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
|
|
|
1486 *
|
|
|
1487 * @param __USB_CLKSOURCE__ specifies the USB clock source.
|
|
|
1488 * This parameter can be one of the following values:
|
|
|
1489 @if STM32L443xx
|
|
|
1490 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
|
|
|
1491 @endif
|
|
|
1492 @if STM32L462xx
|
|
|
1493 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
|
|
|
1494 @endif
|
|
|
1495 @if STM32L486xx
|
|
|
1496 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
|
|
|
1497 @endif
|
|
|
1498 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
|
|
|
1499 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
|
|
|
1500 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
|
|
|
1501 * @retval None
|
|
|
1502 */
|
|
|
1503 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
|
|
|
1504 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
|
|
|
1505
|
|
|
1506 /** @brief Macro to get the USB clock source.
|
|
|
1507 * @retval The clock source can be one of the following values:
|
|
|
1508 @if STM32L443xx
|
|
|
1509 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
|
|
|
1510 @endif
|
|
|
1511 @if STM32L462xx
|
|
|
1512 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
|
|
|
1513 @endif
|
|
|
1514 @if STM32L486xx
|
|
|
1515 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
|
|
|
1516 @endif
|
|
|
1517 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
|
|
|
1518 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
|
|
|
1519 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
|
|
|
1520 */
|
|
|
1521 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
|
|
|
1522
|
|
|
1523 #endif /* USB_OTG_FS || USB */
|
|
|
1524
|
|
|
1525 /** @brief Macro to configure the ADC interface clock.
|
|
|
1526 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
|
|
|
1527 * This parameter can be one of the following values:
|
|
|
1528 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
|
|
|
1529 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
|
|
|
1530 @if STM32L486xx
|
|
|
1531 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x devices
|
|
|
1532 @endif
|
|
|
1533 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
|
|
|
1534 * @retval None
|
|
|
1535 */
|
|
|
1536 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
|
|
|
1537 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
|
|
|
1538
|
|
|
1539 /** @brief Macro to get the ADC clock source.
|
|
|
1540 * @retval The clock source can be one of the following values:
|
|
|
1541 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
|
|
|
1542 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
|
|
|
1543 @if STM32L486xx
|
|
|
1544 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x devices
|
|
|
1545 @endif
|
|
|
1546 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
|
|
|
1547 */
|
|
|
1548 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
|
|
|
1549
|
|
|
1550 #if defined(SWPMI1)
|
|
|
1551
|
|
|
1552 /** @brief Macro to configure the SWPMI1 clock.
|
|
|
1553 * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
|
|
|
1554 * This parameter can be one of the following values:
|
|
|
1555 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
|
|
|
1556 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
|
|
|
1557 * @retval None
|
|
|
1558 */
|
|
|
1559 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
|
|
|
1560 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
|
|
|
1561
|
|
|
1562 /** @brief Macro to get the SWPMI1 clock source.
|
|
|
1563 * @retval The clock source can be one of the following values:
|
|
|
1564 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
|
|
|
1565 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
|
|
|
1566 */
|
|
|
1567 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
|
|
|
1568
|
|
|
1569 #endif /* SWPMI1 */
|
|
|
1570
|
|
|
1571 #if defined(DFSDM1_Filter0)
|
|
|
1572 /** @brief Macro to configure the DFSDM1 clock.
|
|
|
1573 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
|
|
|
1574 * This parameter can be one of the following values:
|
|
|
1575 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK PCLK Clock selected as DFSDM1 clock
|
|
|
1576 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
|
|
|
1577 * @retval None
|
|
|
1578 */
|
|
|
1579 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
|
|
|
1580 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
|
|
|
1581
|
|
|
1582 /** @brief Macro to get the DFSDM1 clock source.
|
|
|
1583 * @retval The clock source can be one of the following values:
|
|
|
1584 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK PCLK Clock selected as DFSDM1 clock
|
|
|
1585 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
|
|
|
1586 */
|
|
|
1587 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
|
|
|
1588
|
|
|
1589 #endif /* DFSDM1_Filter0 */
|
|
|
1590
|
|
|
1591 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
|
|
|
1592 * @brief macros to manage the specified RCC Flags and interrupts.
|
|
|
1593 * @{
|
|
|
1594 */
|
|
|
1595
|
|
|
1596 /** @brief Enable PLLSAI1RDY interrupt.
|
|
|
1597 * @retval None
|
|
|
1598 */
|
|
|
1599 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
|
|
|
1600
|
|
|
1601 /** @brief Disable PLLSAI1RDY interrupt.
|
|
|
1602 * @retval None
|
|
|
1603 */
|
|
|
1604 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
|
|
|
1605
|
|
|
1606 /** @brief Clear the PLLSAI1RDY interrupt pending bit.
|
|
|
1607 * @retval None
|
|
|
1608 */
|
|
|
1609 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
|
|
|
1610
|
|
|
1611 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
|
|
|
1612 * @retval TRUE or FALSE.
|
|
|
1613 */
|
|
|
1614 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
|
|
|
1615
|
|
|
1616 /** @brief Check whether the PLLSAI1RDY flag is set or not.
|
|
|
1617 * @retval TRUE or FALSE.
|
|
|
1618 */
|
|
|
1619 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
|
|
|
1620
|
|
|
1621 #if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
1622
|
|
|
1623 /** @brief Enable PLLSAI2RDY interrupt.
|
|
|
1624 * @retval None
|
|
|
1625 */
|
|
|
1626 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
|
|
|
1627
|
|
|
1628 /** @brief Disable PLLSAI2RDY interrupt.
|
|
|
1629 * @retval None
|
|
|
1630 */
|
|
|
1631 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
|
|
|
1632
|
|
|
1633 /** @brief Clear the PLLSAI2RDY interrupt pending bit.
|
|
|
1634 * @retval None
|
|
|
1635 */
|
|
|
1636 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
|
|
|
1637
|
|
|
1638 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
|
|
|
1639 * @retval TRUE or FALSE.
|
|
|
1640 */
|
|
|
1641 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
|
|
|
1642
|
|
|
1643 /** @brief Check whether the PLLSAI2RDY flag is set or not.
|
|
|
1644 * @retval TRUE or FALSE.
|
|
|
1645 */
|
|
|
1646 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
|
|
|
1647
|
|
|
1648 #endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
1649
|
|
|
1650
|
|
|
1651 /**
|
|
|
1652 * @brief Enable the RCC LSE CSS Extended Interrupt Line.
|
|
|
1653 * @retval None
|
|
|
1654 */
|
|
|
1655 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
|
|
|
1656
|
|
|
1657 /**
|
|
|
1658 * @brief Disable the RCC LSE CSS Extended Interrupt Line.
|
|
|
1659 * @retval None
|
|
|
1660 */
|
|
|
1661 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
|
|
|
1662
|
|
|
1663 /**
|
|
|
1664 * @brief Enable the RCC LSE CSS Event Line.
|
|
|
1665 * @retval None.
|
|
|
1666 */
|
|
|
1667 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
|
|
|
1668
|
|
|
1669 /**
|
|
|
1670 * @brief Disable the RCC LSE CSS Event Line.
|
|
|
1671 * @retval None.
|
|
|
1672 */
|
|
|
1673 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
|
|
|
1674
|
|
|
1675
|
|
|
1676 /**
|
|
|
1677 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
|
|
|
1678 * @retval None.
|
|
|
1679 */
|
|
|
1680 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
|
|
|
1681
|
|
|
1682
|
|
|
1683 /**
|
|
|
1684 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
|
|
|
1685 * @retval None.
|
|
|
1686 */
|
|
|
1687 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
|
|
|
1688
|
|
|
1689
|
|
|
1690 /**
|
|
|
1691 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
|
|
|
1692 * @retval None.
|
|
|
1693 */
|
|
|
1694 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
|
|
|
1695
|
|
|
1696 /**
|
|
|
1697 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
|
|
|
1698 * @retval None.
|
|
|
1699 */
|
|
|
1700 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
|
|
|
1701
|
|
|
1702 /**
|
|
|
1703 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
|
|
|
1704 * @retval None.
|
|
|
1705 */
|
|
|
1706 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
|
|
1707 do { \
|
|
|
1708 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
|
|
|
1709 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
|
|
|
1710 } while(0)
|
|
|
1711
|
|
|
1712 /**
|
|
|
1713 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
|
|
|
1714 * @retval None.
|
|
|
1715 */
|
|
|
1716 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
|
|
1717 do { \
|
|
|
1718 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
|
|
|
1719 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
|
|
|
1720 } while(0)
|
|
|
1721
|
|
|
1722 /**
|
|
|
1723 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
|
|
|
1724 * @retval EXTI RCC LSE CSS Line Status.
|
|
|
1725 */
|
|
|
1726 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
|
|
|
1727
|
|
|
1728 /**
|
|
|
1729 * @brief Clear the RCC LSE CSS EXTI flag.
|
|
|
1730 * @retval None.
|
|
|
1731 */
|
|
|
1732 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
|
|
|
1733
|
|
|
1734 /**
|
|
|
1735 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
|
|
|
1736 * @retval None.
|
|
|
1737 */
|
|
|
1738 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
|
|
|
1739
|
|
|
1740
|
|
|
1741 #if defined(CRS)
|
|
|
1742
|
|
|
1743 /**
|
|
|
1744 * @brief Enable the specified CRS interrupts.
|
|
|
1745 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
|
|
|
1746 * This parameter can be any combination of the following values:
|
|
|
1747 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
|
|
|
1748 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
|
|
|
1749 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
|
|
|
1750 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
|
|
|
1751 * @retval None
|
|
|
1752 */
|
|
|
1753 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
|
|
|
1754
|
|
|
1755 /**
|
|
|
1756 * @brief Disable the specified CRS interrupts.
|
|
|
1757 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
|
|
|
1758 * This parameter can be any combination of the following values:
|
|
|
1759 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
|
|
|
1760 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
|
|
|
1761 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
|
|
|
1762 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
|
|
|
1763 * @retval None
|
|
|
1764 */
|
|
|
1765 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
|
|
|
1766
|
|
|
1767 /** @brief Check whether the CRS interrupt has occurred or not.
|
|
|
1768 * @param __INTERRUPT__ specifies the CRS interrupt source to check.
|
|
|
1769 * This parameter can be one of the following values:
|
|
|
1770 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
|
|
|
1771 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
|
|
|
1772 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
|
|
|
1773 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
|
|
|
1774 * @retval The new state of __INTERRUPT__ (SET or RESET).
|
|
|
1775 */
|
|
|
1776 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
|
|
|
1777
|
|
|
1778 /** @brief Clear the CRS interrupt pending bits
|
|
|
1779 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
|
|
1780 * This parameter can be any combination of the following values:
|
|
|
1781 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
|
|
|
1782 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
|
|
|
1783 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
|
|
|
1784 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
|
|
|
1785 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
|
|
|
1786 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
|
|
|
1787 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
|
|
|
1788 */
|
|
|
1789 /* CRS IT Error Mask */
|
|
|
1790 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
|
|
|
1791
|
|
|
1792 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
|
|
|
1793 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
|
|
|
1794 { \
|
|
|
1795 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
|
|
|
1796 } \
|
|
|
1797 else \
|
|
|
1798 { \
|
|
|
1799 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
|
|
|
1800 } \
|
|
|
1801 } while(0)
|
|
|
1802
|
|
|
1803 /**
|
|
|
1804 * @brief Check whether the specified CRS flag is set or not.
|
|
|
1805 * @param __FLAG__ specifies the flag to check.
|
|
|
1806 * This parameter can be one of the following values:
|
|
|
1807 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
|
|
|
1808 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
|
|
|
1809 * @arg @ref RCC_CRS_FLAG_ERR Error
|
|
|
1810 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
|
|
|
1811 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
|
|
|
1812 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
|
|
|
1813 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
|
|
|
1814 * @retval The new state of _FLAG_ (TRUE or FALSE).
|
|
|
1815 */
|
|
|
1816 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
|
|
|
1817
|
|
|
1818 /**
|
|
|
1819 * @brief Clear the CRS specified FLAG.
|
|
|
1820 * @param __FLAG__ specifies the flag to clear.
|
|
|
1821 * This parameter can be one of the following values:
|
|
|
1822 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
|
|
|
1823 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
|
|
|
1824 * @arg @ref RCC_CRS_FLAG_ERR Error
|
|
|
1825 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
|
|
|
1826 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
|
|
|
1827 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
|
|
|
1828 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
|
|
|
1829 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
|
|
|
1830 * @retval None
|
|
|
1831 */
|
|
|
1832
|
|
|
1833 /* CRS Flag Error Mask */
|
|
|
1834 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
|
|
|
1835
|
|
|
1836 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
|
|
|
1837 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
|
|
|
1838 { \
|
|
|
1839 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
|
|
|
1840 } \
|
|
|
1841 else \
|
|
|
1842 { \
|
|
|
1843 WRITE_REG(CRS->ICR, (__FLAG__)); \
|
|
|
1844 } \
|
|
|
1845 } while(0)
|
|
|
1846
|
|
|
1847 #endif /* CRS */
|
|
|
1848
|
|
|
1849 /**
|
|
|
1850 * @}
|
|
|
1851 */
|
|
|
1852
|
|
|
1853 #if defined(CRS)
|
|
|
1854
|
|
|
1855 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
|
|
|
1856 * @{
|
|
|
1857 */
|
|
|
1858 /**
|
|
|
1859 * @brief Enable the oscillator clock for frequency error counter.
|
|
|
1860 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
|
|
|
1861 * @retval None
|
|
|
1862 */
|
|
|
1863 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
|
|
|
1864
|
|
|
1865 /**
|
|
|
1866 * @brief Disable the oscillator clock for frequency error counter.
|
|
|
1867 * @retval None
|
|
|
1868 */
|
|
|
1869 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
|
|
|
1870
|
|
|
1871 /**
|
|
|
1872 * @brief Enable the automatic hardware adjustement of TRIM bits.
|
|
|
1873 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
|
|
|
1874 * @retval None
|
|
|
1875 */
|
|
|
1876 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
|
|
|
1877
|
|
|
1878 /**
|
|
|
1879 * @brief Enable or disable the automatic hardware adjustement of TRIM bits.
|
|
|
1880 * @retval None
|
|
|
1881 */
|
|
|
1882 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
|
|
|
1883
|
|
|
1884 /**
|
|
|
1885 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
|
|
|
1886 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
|
|
|
1887 * of the synchronization source after prescaling. It is then decreased by one in order to
|
|
|
1888 * reach the expected synchronization on the zero value. The formula is the following:
|
|
|
1889 * RELOAD = (fTARGET / fSYNC) -1
|
|
|
1890 * @param __FTARGET__ Target frequency (value in Hz)
|
|
|
1891 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
|
|
|
1892 * @retval None
|
|
|
1893 */
|
|
|
1894 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
|
|
|
1895
|
|
|
1896 /**
|
|
|
1897 * @}
|
|
|
1898 */
|
|
|
1899
|
|
|
1900 #endif /* CRS */
|
|
|
1901
|
|
|
1902 /**
|
|
|
1903 * @}
|
|
|
1904 */
|
|
|
1905
|
|
|
1906 /* Exported functions --------------------------------------------------------*/
|
|
|
1907 /** @addtogroup RCCEx_Exported_Functions
|
|
|
1908 * @{
|
|
|
1909 */
|
|
|
1910
|
|
|
1911 /** @addtogroup RCCEx_Exported_Functions_Group1
|
|
|
1912 * @{
|
|
|
1913 */
|
|
|
1914
|
|
|
1915 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
|
|
1916 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
|
|
1917 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
|
|
|
1918
|
|
|
1919 /**
|
|
|
1920 * @}
|
|
|
1921 */
|
|
|
1922
|
|
|
1923 /** @addtogroup RCCEx_Exported_Functions_Group2
|
|
|
1924 * @{
|
|
|
1925 */
|
|
|
1926
|
|
|
1927 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
|
|
|
1928 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
|
|
|
1929
|
|
|
1930 #if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
1931
|
|
|
1932 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
|
|
|
1933 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
|
|
|
1934
|
|
|
1935 #endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
1936
|
|
|
1937 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
|
|
|
1938 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
|
|
|
1939 void HAL_RCCEx_EnableLSECSS(void);
|
|
|
1940 void HAL_RCCEx_DisableLSECSS(void);
|
|
|
1941 void HAL_RCCEx_EnableLSECSS_IT(void);
|
|
|
1942 void HAL_RCCEx_LSECSS_IRQHandler(void);
|
|
|
1943 void HAL_RCCEx_LSECSS_Callback(void);
|
|
|
1944 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
|
|
|
1945 void HAL_RCCEx_DisableLSCO(void);
|
|
|
1946 void HAL_RCCEx_EnableMSIPLLMode(void);
|
|
|
1947 void HAL_RCCEx_DisableMSIPLLMode(void);
|
|
|
1948
|
|
|
1949 /**
|
|
|
1950 * @}
|
|
|
1951 */
|
|
|
1952
|
|
|
1953 #if defined(CRS)
|
|
|
1954
|
|
|
1955 /** @addtogroup RCCEx_Exported_Functions_Group3
|
|
|
1956 * @{
|
|
|
1957 */
|
|
|
1958
|
|
|
1959 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
|
|
|
1960 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
|
|
|
1961 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
|
|
|
1962 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
|
|
|
1963 void HAL_RCCEx_CRS_IRQHandler(void);
|
|
|
1964 void HAL_RCCEx_CRS_SyncOkCallback(void);
|
|
|
1965 void HAL_RCCEx_CRS_SyncWarnCallback(void);
|
|
|
1966 void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
|
|
|
1967 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
|
|
|
1968
|
|
|
1969 /**
|
|
|
1970 * @}
|
|
|
1971 */
|
|
|
1972
|
|
|
1973 #endif /* CRS */
|
|
|
1974
|
|
|
1975 /**
|
|
|
1976 * @}
|
|
|
1977 */
|
|
|
1978
|
|
|
1979 /* Private macros ------------------------------------------------------------*/
|
|
|
1980 /** @addtogroup RCCEx_Private_Macros
|
|
|
1981 * @{
|
|
|
1982 */
|
|
|
1983
|
|
|
1984 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
|
|
|
1985 ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
|
|
|
1986
|
|
|
1987 #if defined(STM32L431xx)
|
|
|
1988
|
|
|
1989 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
|
|
1990 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
|
|
1991 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
|
|
1992 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
|
|
1993 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
|
|
1994 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
|
|
1995 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
|
|
1996 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
|
|
1997 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
|
|
1998 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
|
|
1999 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
|
|
2000 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
|
|
2001 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
|
|
|
2002 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
|
|
2003 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
|
|
2004 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
|
|
|
2005
|
|
|
2006 #elif defined(STM32L432xx) || defined(STM32L442xx)
|
|
|
2007
|
|
|
2008 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
|
|
2009 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
|
|
2010 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
|
|
2011 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
|
|
2012 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
|
|
2013 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
|
|
2014 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
|
|
2015 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
|
|
2016 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
|
|
2017 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
|
|
2018 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
|
|
2019 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
|
|
|
2020 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
|
|
2021 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
|
|
|
2022
|
|
|
2023 #elif defined(STM32L433xx) || defined(STM32L443xx)
|
|
|
2024
|
|
|
2025 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
|
|
2026 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
|
|
2027 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
|
|
2028 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
|
|
2029 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
|
|
2030 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
|
|
2031 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
|
|
2032 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
|
|
2033 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
|
|
2034 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
|
|
2035 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
|
|
2036 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
|
|
2037 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
|
|
2038 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
|
|
|
2039 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
|
|
2040 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
|
|
2041 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
|
|
|
2042
|
|
|
2043 #elif defined(STM32L451xx)
|
|
|
2044
|
|
|
2045 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
|
|
2046 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
|
|
2047 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
|
|
2048 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
|
|
2049 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
|
|
2050 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
|
|
2051 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
|
|
2052 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
|
|
2053 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
|
|
2054 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
|
|
|
2055 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
|
|
2056 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
|
|
2057 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
|
|
2058 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
|
|
2059 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
|
|
|
2060 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
|
|
2061 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
|
|
2062 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
|
|
|
2063
|
|
|
2064 #elif defined(STM32L452xx) || defined(STM32L462xx)
|
|
|
2065
|
|
|
2066 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
|
|
2067 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
|
|
2068 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
|
|
2069 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
|
|
2070 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
|
|
2071 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
|
|
2072 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
|
|
2073 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
|
|
2074 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
|
|
2075 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
|
|
|
2076 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
|
|
2077 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
|
|
2078 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
|
|
2079 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
|
|
2080 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
|
|
2081 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
|
|
|
2082 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
|
|
2083 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
|
|
2084 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
|
|
|
2085
|
|
|
2086 #elif defined(STM32L471xx)
|
|
|
2087
|
|
|
2088 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
|
|
2089 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
|
|
2090 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
|
|
2091 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
|
|
2092 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
|
|
2093 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
|
|
|
2094 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
|
|
2095 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
|
|
2096 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
|
|
2097 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
|
|
2098 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
|
|
2099 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
|
|
2100 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
|
|
2101 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
|
|
|
2102 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
|
|
2103 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
|
|
|
2104 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
|
|
|
2105 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
|
|
2106 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
|
|
2107 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
|
|
|
2108
|
|
|
2109 #else
|
|
|
2110
|
|
|
2111 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
|
|
2112 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
|
|
2113 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
|
|
2114 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
|
|
2115 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
|
|
2116 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
|
|
|
2117 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
|
|
2118 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
|
|
2119 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
|
|
2120 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
|
|
2121 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
|
|
2122 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
|
|
|
2123 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
|
|
2124 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
|
|
|
2125 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
|
|
2126 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
|
|
|
2127 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
|
|
|
2128 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
|
|
|
2129 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
|
|
|
2130 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
|
|
2131 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
|
|
|
2132
|
|
|
2133 #endif /* STM32L431xx */
|
|
|
2134
|
|
|
2135 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
|
|
|
2136 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
|
|
|
2137 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
|
|
|
2138 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
|
|
|
2139 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
|
|
|
2140
|
|
|
2141 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
|
|
|
2142 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
|
|
|
2143 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
|
|
|
2144 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
|
|
|
2145 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
|
|
|
2146
|
|
|
2147 #if defined(USART3)
|
|
|
2148
|
|
|
2149 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
|
|
|
2150 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
|
|
|
2151 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
|
|
|
2152 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
|
|
|
2153 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
|
|
|
2154
|
|
|
2155 #endif /* USART3 */
|
|
|
2156
|
|
|
2157 #if defined(UART4)
|
|
|
2158
|
|
|
2159 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
|
|
|
2160 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
|
|
|
2161 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
|
|
|
2162 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
|
|
|
2163 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
|
|
|
2164
|
|
|
2165 #endif /* UART4 */
|
|
|
2166
|
|
|
2167 #if defined(UART5)
|
|
|
2168
|
|
|
2169 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
|
|
|
2170 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
|
|
|
2171 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
|
|
|
2172 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
|
|
|
2173 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
|
|
|
2174
|
|
|
2175 #endif /* UART5 */
|
|
|
2176
|
|
|
2177 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
|
|
|
2178 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
|
|
|
2179 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
|
|
|
2180 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
|
|
|
2181 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
|
|
|
2182
|
|
|
2183 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
|
|
|
2184 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
|
|
|
2185 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
|
|
|
2186 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
|
|
|
2187
|
|
|
2188 #if defined(I2C2)
|
|
|
2189
|
|
|
2190 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
|
|
|
2191 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
|
|
|
2192 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
|
|
|
2193 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
|
|
|
2194
|
|
|
2195 #endif /* I2C2 */
|
|
|
2196
|
|
|
2197 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
|
|
|
2198 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
|
|
|
2199 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
|
|
|
2200 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
|
|
|
2201
|
|
|
2202 #if defined(I2C4)
|
|
|
2203
|
|
|
2204 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
|
|
|
2205 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
|
|
|
2206 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
|
|
|
2207 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
|
|
|
2208
|
|
|
2209 #endif /* I2C4 */
|
|
|
2210
|
|
|
2211 #if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
2212
|
|
|
2213 #define IS_RCC_SAI1CLK(__SOURCE__) \
|
|
|
2214 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
|
|
|
2215 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
|
|
|
2216 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
|
|
|
2217 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
|
|
|
2218
|
|
|
2219 #else
|
|
|
2220
|
|
|
2221 #define IS_RCC_SAI1CLK(__SOURCE__) \
|
|
|
2222 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
|
|
|
2223 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
|
|
|
2224 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
|
|
|
2225
|
|
|
2226 #endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
2227
|
|
|
2228 #if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
2229
|
|
|
2230 #define IS_RCC_SAI2CLK(__SOURCE__) \
|
|
|
2231 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
|
|
|
2232 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
|
|
|
2233 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
|
|
|
2234 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
|
|
|
2235
|
|
|
2236 #endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
2237
|
|
|
2238 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
|
|
|
2239 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \
|
|
|
2240 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
|
|
|
2241 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
|
|
2242 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
|
|
|
2243
|
|
|
2244 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
|
|
|
2245 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \
|
|
|
2246 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
|
|
|
2247 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
|
|
|
2248 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
|
|
|
2249
|
|
|
2250 #if defined(SDMMC1)
|
|
|
2251 #if defined(RCC_HSI48_SUPPORT)
|
|
|
2252
|
|
|
2253 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
|
|
|
2254 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
|
|
|
2255 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
|
|
|
2256 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
|
|
|
2257 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
|
|
|
2258
|
|
|
2259 #else
|
|
|
2260
|
|
|
2261 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
|
|
|
2262 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \
|
|
|
2263 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
|
|
|
2264 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
|
|
|
2265 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
|
|
|
2266
|
|
|
2267 #endif /* RCC_HSI48_SUPPORT */
|
|
|
2268 #endif /* SDMMC1 */
|
|
|
2269
|
|
|
2270 #if defined(RCC_HSI48_SUPPORT)
|
|
|
2271
|
|
|
2272 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
|
|
|
2273 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
|
|
|
2274 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
|
|
|
2275 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
|
|
|
2276 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
|
|
|
2277
|
|
|
2278 #else
|
|
|
2279
|
|
|
2280 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
|
|
|
2281 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
|
|
|
2282 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
|
|
|
2283 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
|
|
|
2284 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
|
|
|
2285
|
|
|
2286 #endif /* RCC_HSI48_SUPPORT */
|
|
|
2287
|
|
|
2288 #if defined(USB_OTG_FS) || defined(USB)
|
|
|
2289 #if defined(RCC_HSI48_SUPPORT)
|
|
|
2290
|
|
|
2291 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
|
|
|
2292 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
|
|
|
2293 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
|
|
|
2294 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
|
|
|
2295 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
|
|
|
2296
|
|
|
2297 #else
|
|
|
2298
|
|
|
2299 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
|
|
|
2300 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \
|
|
|
2301 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
|
|
|
2302 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
|
|
|
2303 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
|
|
|
2304
|
|
|
2305 #endif /* RCC_HSI48_SUPPORT */
|
|
|
2306 #endif /* USB_OTG_FS || USB */
|
|
|
2307
|
|
|
2308 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
|
2309
|
|
|
2310 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
|
|
|
2311 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
|
|
|
2312 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
|
|
|
2313 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
|
|
|
2314 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
|
|
|
2315
|
|
|
2316 #else
|
|
|
2317
|
|
|
2318 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
|
|
|
2319 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
|
|
|
2320 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
|
|
|
2321 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
|
|
|
2322
|
|
|
2323 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
2324
|
|
|
2325 #if defined(SWPMI1)
|
|
|
2326
|
|
|
2327 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
|
|
|
2328 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \
|
|
|
2329 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
|
|
|
2330
|
|
|
2331 #endif /* SWPMI1 */
|
|
|
2332
|
|
|
2333 #if defined(DFSDM1_Filter0)
|
|
|
2334
|
|
|
2335 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \
|
|
|
2336 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK) || \
|
|
|
2337 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
|
|
|
2338
|
|
|
2339 #endif /* DFSDM1_Filter0 */
|
|
|
2340
|
|
|
2341 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
|
|
|
2342
|
|
|
2343 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
|
|
|
2344
|
|
|
2345 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
|
|
|
2346
|
|
|
2347 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
|
|
|
2348 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
|
|
|
2349 #else
|
|
|
2350 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
|
|
|
2351 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
2352
|
|
|
2353 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
|
|
|
2354 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
|
|
|
2355
|
|
|
2356 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
|
|
|
2357 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
|
|
|
2358
|
|
|
2359 #if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
2360
|
|
|
2361 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
|
|
|
2362
|
|
|
2363 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
|
|
|
2364
|
|
|
2365 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
|
|
|
2366
|
|
|
2367 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
|
|
|
2368 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
|
|
|
2369 #else
|
|
|
2370 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
|
|
|
2371 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
|
|
|
2372
|
|
|
2373 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
|
|
|
2374 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
|
|
|
2375
|
|
|
2376 #endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
2377
|
|
|
2378 #if defined(CRS)
|
|
|
2379
|
|
|
2380 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
|
|
|
2381 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
|
|
|
2382 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
|
|
|
2383
|
|
|
2384 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
|
|
|
2385 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
|
|
|
2386 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
|
|
|
2387 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
|
|
|
2388
|
|
|
2389 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
|
|
|
2390 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
|
|
|
2391
|
|
|
2392 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
|
|
|
2393
|
|
|
2394 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
|
|
|
2395
|
|
|
2396 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
|
|
|
2397
|
|
|
2398 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
|
|
|
2399 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
|
|
|
2400
|
|
|
2401 #endif /* CRS */
|
|
|
2402
|
|
|
2403 /**
|
|
|
2404 * @}
|
|
|
2405 */
|
|
|
2406
|
|
|
2407 /**
|
|
|
2408 * @}
|
|
|
2409 */
|
|
|
2410
|
|
|
2411 /**
|
|
|
2412 * @}
|
|
|
2413 */
|
|
|
2414
|
|
|
2415 #ifdef __cplusplus
|
|
|
2416 }
|
|
|
2417 #endif
|
|
|
2418
|
|
|
2419 #endif /* __STM32L4xx_HAL_RCC_EX_H */
|
|
|
2420
|
|
|
2421 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
