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1 /**
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2 ******************************************************************************
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3 * @file stm32l4xx_hal_pwr_ex.c
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4 * @author MCD Application Team
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5 * @version V1.6.0
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6 * @date 28-October-2016
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7 * @brief Extended PWR HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the Power Controller (PWR) peripheral:
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10 * + Extended Initialization and de-initialization functions
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11 * + Extended Peripheral Control functions
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12 *
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13 ******************************************************************************
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14 * @attention
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15 *
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16 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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17 *
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18 * Redistribution and use in source and binary forms, with or without modification,
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19 * are permitted provided that the following conditions are met:
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20 * 1. Redistributions of source code must retain the above copyright notice,
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21 * this list of conditions and the following disclaimer.
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22 * 2. Redistributions in binary form must reproduce the above copyright notice,
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23 * this list of conditions and the following disclaimer in the documentation
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24 * and/or other materials provided with the distribution.
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25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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26 * may be used to endorse or promote products derived from this software
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27 * without specific prior written permission.
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28 *
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29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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39 *
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40 ******************************************************************************
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41 */
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42
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43 /* Includes ------------------------------------------------------------------*/
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44 #include "stm32l4xx_hal.h"
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45
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46 /** @addtogroup STM32L4xx_HAL_Driver
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47 * @{
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48 */
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49
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50 /** @defgroup PWREx PWREx
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51 * @brief PWR Extended HAL module driver
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52 * @{
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53 */
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54
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55 #ifdef HAL_PWR_MODULE_ENABLED
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56
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57 /* Private typedef -----------------------------------------------------------*/
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58 /* Private define ------------------------------------------------------------*/
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59
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60 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
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61 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
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62 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
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63 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
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64 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
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65 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */
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66 #endif
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67
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68 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
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69 * @{
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70 */
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71
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72 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
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73 * @{
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74 */
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75 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
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76 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
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77 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
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78 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
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79 /**
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80 * @}
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81 */
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82
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83 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
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84 * @{
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85 */
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86 #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */
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87 /**
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88 * @}
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89 */
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90
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91
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92
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93 /**
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94 * @}
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95 */
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96
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97
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98
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99 /* Private macro -------------------------------------------------------------*/
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100 /* Private variables ---------------------------------------------------------*/
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101 /* Private function prototypes -----------------------------------------------*/
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102 /* Exported functions --------------------------------------------------------*/
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103
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104 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
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105 * @{
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106 */
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107
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108 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
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109 * @brief Extended Peripheral Control functions
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110 *
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111 @verbatim
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112 ===============================================================================
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113 ##### Extended Peripheral Initialization and de-initialization functions #####
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114 ===============================================================================
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115 [..]
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116
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117 @endverbatim
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118 * @{
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119 */
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120
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121
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122 /**
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123 * @brief Return Voltage Scaling Range.
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124 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
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125 */
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126 uint32_t HAL_PWREx_GetVoltageRange(void)
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127 {
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128 return (PWR->CR1 & PWR_CR1_VOS);
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129 }
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130
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131
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132
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133 /**
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134 * @brief Configure the main internal regulator output voltage.
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135 * @param VoltageScaling: specifies the regulator output voltage to achieve
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136 * a tradeoff between performance and power consumption.
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137 * This parameter can be one of the following values:
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138 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
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139 * typical output voltage at 1.2 V,
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140 * system frequency up to 80 MHz.
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141 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
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142 * typical output voltage at 1.0 V,
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143 * system frequency up to 26 MHz.
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144 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
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145 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
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146 * When moving from Range 2 to Range 1, the system frequency can be increased to
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147 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
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148 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
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149 * cleared before returning the status. If the flag is not cleared within
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150 * 50 microseconds, HAL_TIMEOUT status is reported.
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151 * @retval HAL Status
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152 */
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153 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
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154 {
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155 uint32_t wait_loop_index = 0;
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156
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157 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
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158
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159 /* If Set Range 1 */
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160 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
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161 {
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162 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
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163 {
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164 /* Set Range 1 */
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165 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
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166
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167 /* Wait until VOSF is cleared */
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168 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
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169 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)))
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170 {
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171 wait_loop_index--;
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172 }
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173 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
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174 {
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175 return HAL_TIMEOUT;
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176 }
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177 }
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178 }
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179 else
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180 {
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181 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
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182 {
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183 /* Set Range 2 */
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184 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
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185 /* No need to wait for VOSF to be cleared for this transition */
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186 }
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187 }
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188
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189 return HAL_OK;
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190 }
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191
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192
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193 /**
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194 * @brief Enable battery charging.
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195 * When VDD is present, charge the external battery on VBAT thru an internal resistor.
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196 * @param ResistorSelection: specifies the resistor impedance.
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197 * This parameter can be one of the following values:
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198 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
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199 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
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200 * @retval None
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201 */
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202 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
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203 {
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204 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
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205
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206 /* Specify resistor selection */
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207 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
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208
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209 /* Enable battery charging */
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210 SET_BIT(PWR->CR4, PWR_CR4_VBE);
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211 }
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212
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213
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214 /**
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215 * @brief Disable battery charging.
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216 * @retval None
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217 */
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218 void HAL_PWREx_DisableBatteryCharging(void)
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219 {
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220 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
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221 }
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222
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223
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224 #if defined(PWR_CR2_USV)
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225 /**
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226 * @brief Enable VDDUSB supply.
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227 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
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228 * @retval None
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229 */
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230 void HAL_PWREx_EnableVddUSB(void)
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231 {
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232 SET_BIT(PWR->CR2, PWR_CR2_USV);
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233 }
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234
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235
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236 /**
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237 * @brief Disable VDDUSB supply.
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238 * @retval None
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239 */
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240 void HAL_PWREx_DisableVddUSB(void)
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241 {
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242 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
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243 }
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244 #endif /* PWR_CR2_USV */
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245
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246 #if defined(PWR_CR2_IOSV)
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247 /**
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248 * @brief Enable VDDIO2 supply.
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249 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
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250 * @retval None
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251 */
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252 void HAL_PWREx_EnableVddIO2(void)
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253 {
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254 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
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255 }
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256
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257
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258 /**
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259 * @brief Disable VDDIO2 supply.
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260 * @retval None
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261 */
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262 void HAL_PWREx_DisableVddIO2(void)
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263 {
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264 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
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265 }
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266 #endif /* PWR_CR2_IOSV */
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267
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268
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269 /**
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270 * @brief Enable Internal Wake-up Line.
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271 * @retval None
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272 */
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273 void HAL_PWREx_EnableInternalWakeUpLine(void)
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274 {
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275 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
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276 }
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277
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278
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279 /**
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280 * @brief Disable Internal Wake-up Line.
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281 * @retval None
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282 */
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283 void HAL_PWREx_DisableInternalWakeUpLine(void)
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284 {
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285 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
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286 }
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287
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288
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289
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290 /**
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291 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
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292 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
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293 * pull-up state in Standby and Shutdown modes.
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294 * @note This state is effective in Standby and Shutdown modes only if APC bit
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295 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
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296 * @note The configuration is lost when exiting the Shutdown mode due to the
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297 * power-on reset, maintained when exiting the Standby mode.
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298 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
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299 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
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300 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
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301 * parameter at the same time are set.
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302 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
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303 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
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304 * @param GPIONumber: Specify the I/O pins numbers.
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305 * This parameter can be one of the following values:
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306 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
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307 * I/O pins are available) or the logical OR of several of them to set
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308 * several bits for a given port in a single API call.
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309 * @retval HAL Status
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310 */
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311 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
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312 {
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313 assert_param(IS_PWR_GPIO(GPIO));
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314 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
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315
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316 switch (GPIO)
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317 {
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318 case PWR_GPIO_A:
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319 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
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320 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
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321 break;
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322 case PWR_GPIO_B:
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323 SET_BIT(PWR->PUCRB, GPIONumber);
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324 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
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325 break;
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326 case PWR_GPIO_C:
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327 SET_BIT(PWR->PUCRC, GPIONumber);
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328 CLEAR_BIT(PWR->PDCRC, GPIONumber);
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329 break;
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330 #if defined(GPIOD)
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331 case PWR_GPIO_D:
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332 SET_BIT(PWR->PUCRD, GPIONumber);
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333 CLEAR_BIT(PWR->PDCRD, GPIONumber);
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334 break;
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335 #endif
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336 #if defined(GPIOE)
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337 case PWR_GPIO_E:
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338 SET_BIT(PWR->PUCRE, GPIONumber);
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339 CLEAR_BIT(PWR->PDCRE, GPIONumber);
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340 break;
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341 #endif
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342 #if defined(GPIOF)
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343 case PWR_GPIO_F:
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344 SET_BIT(PWR->PUCRF, GPIONumber);
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345 CLEAR_BIT(PWR->PDCRF, GPIONumber);
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346 break;
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347 #endif
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348 #if defined(GPIOG)
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349 case PWR_GPIO_G:
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350 SET_BIT(PWR->PUCRG, GPIONumber);
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351 CLEAR_BIT(PWR->PDCRG, GPIONumber);
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352 break;
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353 #endif
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354 case PWR_GPIO_H:
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355 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
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356 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
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357 break;
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358 default:
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359 return HAL_ERROR;
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360 }
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361
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362 return HAL_OK;
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363 }
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364
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365
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366 /**
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367 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
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368 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
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369 * in pull-up state in Standby and Shutdown modes.
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370 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
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371 * parameter at the same time are reset.
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372 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
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373 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
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374 * @param GPIONumber: Specify the I/O pins numbers.
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375 * This parameter can be one of the following values:
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376 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
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377 * I/O pins are available) or the logical OR of several of them to reset
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378 * several bits for a given port in a single API call.
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379 * @retval HAL Status
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380 */
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381 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
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382 {
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383 assert_param(IS_PWR_GPIO(GPIO));
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384 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
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385
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386 switch (GPIO)
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387 {
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388 case PWR_GPIO_A:
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389 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
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390 break;
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391 case PWR_GPIO_B:
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392 CLEAR_BIT(PWR->PUCRB, GPIONumber);
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393 break;
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394 case PWR_GPIO_C:
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395 CLEAR_BIT(PWR->PUCRC, GPIONumber);
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396 break;
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397 #if defined(GPIOD)
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398 case PWR_GPIO_D:
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399 CLEAR_BIT(PWR->PUCRD, GPIONumber);
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400 break;
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401 #endif
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402 #if defined(GPIOE)
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403 case PWR_GPIO_E:
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404 CLEAR_BIT(PWR->PUCRE, GPIONumber);
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405 break;
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406 #endif
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407 #if defined(GPIOF)
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408 case PWR_GPIO_F:
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409 CLEAR_BIT(PWR->PUCRF, GPIONumber);
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410 break;
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411 #endif
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412 #if defined(GPIOG)
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413 case PWR_GPIO_G:
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414 CLEAR_BIT(PWR->PUCRG, GPIONumber);
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415 break;
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416 #endif
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417 case PWR_GPIO_H:
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418 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
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419 break;
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420 default:
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421 return HAL_ERROR;
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422 }
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423
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424 return HAL_OK;
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425 }
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426
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427
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428
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429 /**
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430 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
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431 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
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432 * pull-down state in Standby and Shutdown modes.
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433 * @note This state is effective in Standby and Shutdown modes only if APC bit
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434 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
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435 * @note The configuration is lost when exiting the Shutdown mode due to the
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436 * power-on reset, maintained when exiting the Standby mode.
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437 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
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438 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
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439 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
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440 * parameter at the same time are set.
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441 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
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442 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
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443 * @param GPIONumber: Specify the I/O pins numbers.
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444 * This parameter can be one of the following values:
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445 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
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446 * I/O pins are available) or the logical OR of several of them to set
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447 * several bits for a given port in a single API call.
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448 * @retval HAL Status
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449 */
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450 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
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451 {
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452 assert_param(IS_PWR_GPIO(GPIO));
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453 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
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454
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455 switch (GPIO)
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456 {
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457 case PWR_GPIO_A:
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458 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
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459 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
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460 break;
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461 case PWR_GPIO_B:
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462 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
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463 CLEAR_BIT(PWR->PUCRB, GPIONumber);
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464 break;
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465 case PWR_GPIO_C:
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466 SET_BIT(PWR->PDCRC, GPIONumber);
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467 CLEAR_BIT(PWR->PUCRC, GPIONumber);
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468 break;
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469 #if defined(GPIOD)
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470 case PWR_GPIO_D:
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471 SET_BIT(PWR->PDCRD, GPIONumber);
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472 CLEAR_BIT(PWR->PUCRD, GPIONumber);
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473 break;
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474 #endif
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475 #if defined(GPIOE)
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476 case PWR_GPIO_E:
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477 SET_BIT(PWR->PDCRE, GPIONumber);
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478 CLEAR_BIT(PWR->PUCRE, GPIONumber);
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479 break;
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480 #endif
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481 #if defined(GPIOF)
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482 case PWR_GPIO_F:
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483 SET_BIT(PWR->PDCRF, GPIONumber);
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484 CLEAR_BIT(PWR->PUCRF, GPIONumber);
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485 break;
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486 #endif
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487 #if defined(GPIOG)
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488 case PWR_GPIO_G:
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489 SET_BIT(PWR->PDCRG, GPIONumber);
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490 CLEAR_BIT(PWR->PUCRG, GPIONumber);
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491 break;
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492 #endif
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493 case PWR_GPIO_H:
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494 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
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495 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
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496 break;
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497 default:
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498 return HAL_ERROR;
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499 }
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500
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501 return HAL_OK;
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502 }
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503
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504
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505 /**
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506 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
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507 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
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508 * in pull-down state in Standby and Shutdown modes.
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509 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
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510 * parameter at the same time are reset.
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511 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
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512 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
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513 * @param GPIONumber: Specify the I/O pins numbers.
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514 * This parameter can be one of the following values:
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515 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
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516 * I/O pins are available) or the logical OR of several of them to reset
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517 * several bits for a given port in a single API call.
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518 * @retval HAL Status
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519 */
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520 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
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521 {
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522 assert_param(IS_PWR_GPIO(GPIO));
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523 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
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524
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525 switch (GPIO)
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526 {
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527 case PWR_GPIO_A:
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528 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
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529 break;
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530 case PWR_GPIO_B:
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531 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
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532 break;
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533 case PWR_GPIO_C:
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534 CLEAR_BIT(PWR->PDCRC, GPIONumber);
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535 break;
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536 #if defined(GPIOD)
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537 case PWR_GPIO_D:
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538 CLEAR_BIT(PWR->PDCRD, GPIONumber);
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539 break;
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540 #endif
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541 #if defined(GPIOE)
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542 case PWR_GPIO_E:
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543 CLEAR_BIT(PWR->PDCRE, GPIONumber);
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544 break;
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545 #endif
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546 #if defined(GPIOF)
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547 case PWR_GPIO_F:
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548 CLEAR_BIT(PWR->PDCRF, GPIONumber);
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549 break;
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550 #endif
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551 #if defined(GPIOG)
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552 case PWR_GPIO_G:
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553 CLEAR_BIT(PWR->PDCRG, GPIONumber);
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554 break;
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555 #endif
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556 case PWR_GPIO_H:
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557 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
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558 break;
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559 default:
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560 return HAL_ERROR;
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561 }
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562
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563 return HAL_OK;
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564 }
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565
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566
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567
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568 /**
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569 * @brief Enable pull-up and pull-down configuration.
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570 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
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571 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
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572 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
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573 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
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574 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
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575 * is no conflict when setting PUy or PDy bit.
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576 * @retval None
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577 */
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578 void HAL_PWREx_EnablePullUpPullDownConfig(void)
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579 {
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580 SET_BIT(PWR->CR3, PWR_CR3_APC);
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581 }
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582
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583
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584 /**
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585 * @brief Disable pull-up and pull-down configuration.
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|
586 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
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587 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
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588 * @retval None
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589 */
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590 void HAL_PWREx_DisablePullUpPullDownConfig(void)
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591 {
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592 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
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593 }
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594
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595
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596
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597 /**
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598 * @brief Enable SRAM2 content retention in Standby mode.
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599 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
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600 * Standby mode and its content is kept.
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601 * @retval None
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602 */
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603 void HAL_PWREx_EnableSRAM2ContentRetention(void)
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604 {
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605 SET_BIT(PWR->CR3, PWR_CR3_RRS);
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606 }
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607
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608
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609 /**
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610 * @brief Disable SRAM2 content retention in Standby mode.
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|
611 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
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|
612 * and its content is lost.
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613 * @retval None
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614 */
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615 void HAL_PWREx_DisableSRAM2ContentRetention(void)
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616 {
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617 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
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618 }
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619
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620
|
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621
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622
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|
623 #if defined(PWR_CR2_PVME1)
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624 /**
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625 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
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|
626 * @retval None
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|
627 */
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628 void HAL_PWREx_EnablePVM1(void)
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629 {
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|
|
630 SET_BIT(PWR->CR2, PWR_PVM_1);
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|
631 }
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632
|
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633 /**
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634 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
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|
635 * @retval None
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|
636 */
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637 void HAL_PWREx_DisablePVM1(void)
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|
638 {
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|
639 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
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|
640 }
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|
|
641 #endif /* PWR_CR2_PVME1 */
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|
642
|
|
|
643
|
|
|
644 #if defined(PWR_CR2_PVME2)
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|
|
645 /**
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|
|
646 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
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|
|
647 * @retval None
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|
648 */
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|
|
649 void HAL_PWREx_EnablePVM2(void)
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|
650 {
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|
|
651 SET_BIT(PWR->CR2, PWR_PVM_2);
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|
|
652 }
|
|
|
653
|
|
|
654 /**
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|
|
655 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
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|
|
656 * @retval None
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|
|
657 */
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|
|
658 void HAL_PWREx_DisablePVM2(void)
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|
|
659 {
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|
|
660 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
|
|
|
661 }
|
|
|
662 #endif /* PWR_CR2_PVME2 */
|
|
|
663
|
|
|
664
|
|
|
665 /**
|
|
|
666 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
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|
|
667 * @retval None
|
|
|
668 */
|
|
|
669 void HAL_PWREx_EnablePVM3(void)
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|
|
670 {
|
|
|
671 SET_BIT(PWR->CR2, PWR_PVM_3);
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|
|
672 }
|
|
|
673
|
|
|
674 /**
|
|
|
675 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
|
|
|
676 * @retval None
|
|
|
677 */
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|
|
678 void HAL_PWREx_DisablePVM3(void)
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|
|
679 {
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|
|
680 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
|
|
|
681 }
|
|
|
682
|
|
|
683
|
|
|
684 /**
|
|
|
685 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
|
|
|
686 * @retval None
|
|
|
687 */
|
|
|
688 void HAL_PWREx_EnablePVM4(void)
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|
|
689 {
|
|
|
690 SET_BIT(PWR->CR2, PWR_PVM_4);
|
|
|
691 }
|
|
|
692
|
|
|
693 /**
|
|
|
694 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
|
|
|
695 * @retval None
|
|
|
696 */
|
|
|
697 void HAL_PWREx_DisablePVM4(void)
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|
|
698 {
|
|
|
699 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
|
|
|
700 }
|
|
|
701
|
|
|
702
|
|
|
703
|
|
|
704
|
|
|
705 /**
|
|
|
706 * @brief Configure the Peripheral Voltage Monitoring (PVM).
|
|
|
707 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
|
|
|
708 * PVM configuration information.
|
|
|
709 * @note The API configures a single PVM according to the information contained
|
|
|
710 * in the input structure. To configure several PVMs, the API must be singly
|
|
|
711 * called for each PVM used.
|
|
|
712 * @note Refer to the electrical characteristics of your device datasheet for
|
|
|
713 * more details about the voltage thresholds corresponding to each
|
|
|
714 * detection level and to each monitored supply.
|
|
|
715 * @retval HAL status
|
|
|
716 */
|
|
|
717 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
|
|
|
718 {
|
|
|
719 /* Check the parameters */
|
|
|
720 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
|
|
|
721 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
|
|
|
722
|
|
|
723
|
|
|
724 /* Configure EXTI 35 to 38 interrupts if so required:
|
|
|
725 scan thru PVMType to detect which PVMx is set and
|
|
|
726 configure the corresponding EXTI line accordingly. */
|
|
|
727 switch (sConfigPVM->PVMType)
|
|
|
728 {
|
|
|
729 #if defined(PWR_CR2_PVME1)
|
|
|
730 case PWR_PVM_1:
|
|
|
731 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
|
|
732 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
|
|
|
733 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
|
|
|
734 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
|
|
|
735 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
|
|
|
736
|
|
|
737 /* Configure interrupt mode */
|
|
|
738 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
|
|
|
739 {
|
|
|
740 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
|
|
|
741 }
|
|
|
742
|
|
|
743 /* Configure event mode */
|
|
|
744 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
|
|
|
745 {
|
|
|
746 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
|
|
|
747 }
|
|
|
748
|
|
|
749 /* Configure the edge */
|
|
|
750 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
|
|
|
751 {
|
|
|
752 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
|
|
|
753 }
|
|
|
754
|
|
|
755 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
|
|
|
756 {
|
|
|
757 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
|
|
|
758 }
|
|
|
759 break;
|
|
|
760 #endif /* PWR_CR2_PVME1 */
|
|
|
761
|
|
|
762 #if defined(PWR_CR2_PVME2)
|
|
|
763 case PWR_PVM_2:
|
|
|
764 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
|
|
765 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
|
|
|
766 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
|
|
|
767 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
|
|
|
768 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
|
|
|
769
|
|
|
770 /* Configure interrupt mode */
|
|
|
771 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
|
|
|
772 {
|
|
|
773 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
|
|
|
774 }
|
|
|
775
|
|
|
776 /* Configure event mode */
|
|
|
777 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
|
|
|
778 {
|
|
|
779 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
|
|
|
780 }
|
|
|
781
|
|
|
782 /* Configure the edge */
|
|
|
783 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
|
|
|
784 {
|
|
|
785 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
|
|
|
786 }
|
|
|
787
|
|
|
788 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
|
|
|
789 {
|
|
|
790 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
|
|
|
791 }
|
|
|
792 break;
|
|
|
793 #endif /* PWR_CR2_PVME2 */
|
|
|
794
|
|
|
795 case PWR_PVM_3:
|
|
|
796 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
|
|
797 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
|
|
|
798 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
|
|
|
799 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
|
|
|
800 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
|
|
|
801
|
|
|
802 /* Configure interrupt mode */
|
|
|
803 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
|
|
|
804 {
|
|
|
805 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
|
|
|
806 }
|
|
|
807
|
|
|
808 /* Configure event mode */
|
|
|
809 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
|
|
|
810 {
|
|
|
811 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
|
|
|
812 }
|
|
|
813
|
|
|
814 /* Configure the edge */
|
|
|
815 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
|
|
|
816 {
|
|
|
817 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
|
|
|
818 }
|
|
|
819
|
|
|
820 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
|
|
|
821 {
|
|
|
822 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
|
|
|
823 }
|
|
|
824 break;
|
|
|
825
|
|
|
826 case PWR_PVM_4:
|
|
|
827 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
|
|
828 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
|
|
|
829 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
|
|
|
830 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
|
|
|
831 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
|
|
|
832
|
|
|
833 /* Configure interrupt mode */
|
|
|
834 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
|
|
|
835 {
|
|
|
836 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
|
|
|
837 }
|
|
|
838
|
|
|
839 /* Configure event mode */
|
|
|
840 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
|
|
|
841 {
|
|
|
842 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
|
|
|
843 }
|
|
|
844
|
|
|
845 /* Configure the edge */
|
|
|
846 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
|
|
|
847 {
|
|
|
848 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
|
|
|
849 }
|
|
|
850
|
|
|
851 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
|
|
|
852 {
|
|
|
853 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
|
|
|
854 }
|
|
|
855 break;
|
|
|
856
|
|
|
857 default:
|
|
|
858 return HAL_ERROR;
|
|
|
859
|
|
|
860 }
|
|
|
861
|
|
|
862
|
|
|
863 return HAL_OK;
|
|
|
864 }
|
|
|
865
|
|
|
866
|
|
|
867
|
|
|
868 /**
|
|
|
869 * @brief Enter Low-power Run mode
|
|
|
870 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
|
|
|
871 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
|
|
|
872 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
|
|
|
873 * Additionally, the clock frequency must be reduced below 2 MHz.
|
|
|
874 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
|
|
|
875 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
|
|
|
876 * @retval None
|
|
|
877 */
|
|
|
878 void HAL_PWREx_EnableLowPowerRunMode(void)
|
|
|
879 {
|
|
|
880 /* Set Regulator parameter */
|
|
|
881 SET_BIT(PWR->CR1, PWR_CR1_LPR);
|
|
|
882 }
|
|
|
883
|
|
|
884
|
|
|
885 /**
|
|
|
886 * @brief Exit Low-power Run mode.
|
|
|
887 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
|
|
|
888 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
|
|
|
889 * returns HAL_TIMEOUT status). The system clock frequency can then be
|
|
|
890 * increased above 2 MHz.
|
|
|
891 * @retval HAL Status
|
|
|
892 */
|
|
|
893 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
|
|
|
894 {
|
|
|
895 uint32_t wait_loop_index = 0;
|
|
|
896
|
|
|
897 /* Clear LPR bit */
|
|
|
898 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
|
|
|
899
|
|
|
900 /* Wait until REGLPF is reset */
|
|
|
901 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
|
|
|
902 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)))
|
|
|
903 {
|
|
|
904 wait_loop_index--;
|
|
|
905 }
|
|
|
906 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
|
|
|
907 {
|
|
|
908 return HAL_TIMEOUT;
|
|
|
909 }
|
|
|
910
|
|
|
911 return HAL_OK;
|
|
|
912 }
|
|
|
913
|
|
|
914
|
|
|
915 /**
|
|
|
916 * @brief Enter Stop 0 mode.
|
|
|
917 * @note In Stop 0 mode, main and low voltage regulators are ON.
|
|
|
918 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
|
|
|
919 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
|
|
|
920 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
|
|
|
921 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
|
|
|
922 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
|
|
|
923 * only to the peripheral requesting it.
|
|
|
924 * SRAM1, SRAM2 and register contents are preserved.
|
|
|
925 * The BOR is available.
|
|
|
926 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
|
|
|
927 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
|
|
|
928 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
|
|
|
929 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
|
|
|
930 * is higher although the startup time is reduced.
|
|
|
931 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
|
|
|
932 * This parameter can be one of the following values:
|
|
|
933 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
|
|
|
934 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
|
|
|
935 * @retval None
|
|
|
936 */
|
|
|
937 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
|
|
|
938 {
|
|
|
939 /* Check the parameters */
|
|
|
940 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
|
|
941
|
|
|
942 /* Stop 0 mode with Main Regulator */
|
|
|
943 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
|
|
|
944
|
|
|
945 /* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
|
946 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
|
947
|
|
|
948 /* Select Stop mode entry --------------------------------------------------*/
|
|
|
949 if(STOPEntry == PWR_STOPENTRY_WFI)
|
|
|
950 {
|
|
|
951 /* Request Wait For Interrupt */
|
|
|
952 __WFI();
|
|
|
953 }
|
|
|
954 else
|
|
|
955 {
|
|
|
956 /* Request Wait For Event */
|
|
|
957 __SEV();
|
|
|
958 __WFE();
|
|
|
959 __WFE();
|
|
|
960 }
|
|
|
961
|
|
|
962 /* Reset SLEEPDEEP bit of Cortex System Control Register */
|
|
|
963 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
|
964 }
|
|
|
965
|
|
|
966
|
|
|
967 /**
|
|
|
968 * @brief Enter Stop 1 mode.
|
|
|
969 * @note In Stop 1 mode, only low power voltage regulator is ON.
|
|
|
970 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
|
|
|
971 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
|
|
|
972 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
|
|
|
973 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
|
|
|
974 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
|
|
|
975 * only to the peripheral requesting it.
|
|
|
976 * SRAM1, SRAM2 and register contents are preserved.
|
|
|
977 * The BOR is available.
|
|
|
978 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
|
|
|
979 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
|
|
|
980 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
|
|
|
981 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
|
|
|
982 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
|
|
|
983 * This parameter can be one of the following values:
|
|
|
984 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
|
|
|
985 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
|
|
|
986 * @retval None
|
|
|
987 */
|
|
|
988 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
|
|
|
989 {
|
|
|
990 /* Check the parameters */
|
|
|
991 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
|
|
992
|
|
|
993 /* Stop 1 mode with Low-Power Regulator */
|
|
|
994 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
|
|
|
995
|
|
|
996 /* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
|
997 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
|
998
|
|
|
999 /* Select Stop mode entry --------------------------------------------------*/
|
|
|
1000 if(STOPEntry == PWR_STOPENTRY_WFI)
|
|
|
1001 {
|
|
|
1002 /* Request Wait For Interrupt */
|
|
|
1003 __WFI();
|
|
|
1004 }
|
|
|
1005 else
|
|
|
1006 {
|
|
|
1007 /* Request Wait For Event */
|
|
|
1008 __SEV();
|
|
|
1009 __WFE();
|
|
|
1010 __WFE();
|
|
|
1011 }
|
|
|
1012
|
|
|
1013 /* Reset SLEEPDEEP bit of Cortex System Control Register */
|
|
|
1014 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
|
1015 }
|
|
|
1016
|
|
|
1017
|
|
|
1018 /**
|
|
|
1019 * @brief Enter Stop 2 mode.
|
|
|
1020 * @note In Stop 2 mode, only low power voltage regulator is ON.
|
|
|
1021 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
|
|
|
1022 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
|
|
|
1023 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
|
|
|
1024 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
|
|
|
1025 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
|
|
|
1026 * to the peripheral requesting it.
|
|
|
1027 * SRAM1, SRAM2 and register contents are preserved.
|
|
|
1028 * The BOR is available.
|
|
|
1029 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
|
|
|
1030 * Otherwise, Stop 1 mode is entered.
|
|
|
1031 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
|
|
|
1032 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
|
|
|
1033 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
|
|
|
1034 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
|
|
|
1035 * This parameter can be one of the following values:
|
|
|
1036 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
|
|
|
1037 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
|
|
|
1038 * @retval None
|
|
|
1039 */
|
|
|
1040 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
|
|
|
1041 {
|
|
|
1042 /* Check the parameter */
|
|
|
1043 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
|
|
1044
|
|
|
1045 /* Set Stop mode 2 */
|
|
|
1046 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
|
|
|
1047
|
|
|
1048 /* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
|
1049 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
|
1050
|
|
|
1051 /* Select Stop mode entry --------------------------------------------------*/
|
|
|
1052 if(STOPEntry == PWR_STOPENTRY_WFI)
|
|
|
1053 {
|
|
|
1054 /* Request Wait For Interrupt */
|
|
|
1055 __WFI();
|
|
|
1056 }
|
|
|
1057 else
|
|
|
1058 {
|
|
|
1059 /* Request Wait For Event */
|
|
|
1060 __SEV();
|
|
|
1061 __WFE();
|
|
|
1062 __WFE();
|
|
|
1063 }
|
|
|
1064
|
|
|
1065 /* Reset SLEEPDEEP bit of Cortex System Control Register */
|
|
|
1066 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
|
1067 }
|
|
|
1068
|
|
|
1069
|
|
|
1070
|
|
|
1071
|
|
|
1072
|
|
|
1073 /**
|
|
|
1074 * @brief Enter Shutdown mode.
|
|
|
1075 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
|
|
|
1076 * off. The voltage regulator is disabled and Vcore domain is powered off.
|
|
|
1077 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
|
|
|
1078 * The BOR is not available.
|
|
|
1079 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
|
|
|
1080 * @retval None
|
|
|
1081 */
|
|
|
1082 void HAL_PWREx_EnterSHUTDOWNMode(void)
|
|
|
1083 {
|
|
|
1084
|
|
|
1085 /* Set Shutdown mode */
|
|
|
1086 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
|
|
|
1087
|
|
|
1088 /* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
|
1089 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
|
1090
|
|
|
1091 /* This option is used to ensure that store operations are completed */
|
|
|
1092 #if defined ( __CC_ARM)
|
|
|
1093 __force_stores();
|
|
|
1094 #endif
|
|
|
1095 /* Request Wait For Interrupt */
|
|
|
1096 __WFI();
|
|
|
1097 }
|
|
|
1098
|
|
|
1099
|
|
|
1100
|
|
|
1101
|
|
|
1102 /**
|
|
|
1103 * @brief This function handles the PWR PVD/PVMx interrupt request.
|
|
|
1104 * @note This API should be called under the PVD_PVM_IRQHandler().
|
|
|
1105 * @retval None
|
|
|
1106 */
|
|
|
1107 void HAL_PWREx_PVD_PVM_IRQHandler(void)
|
|
|
1108 {
|
|
|
1109 /* Check PWR exti flag */
|
|
|
1110 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
|
|
1111 {
|
|
|
1112 /* PWR PVD interrupt user callback */
|
|
|
1113 HAL_PWR_PVDCallback();
|
|
|
1114
|
|
|
1115 /* Clear PVD exti pending bit */
|
|
|
1116 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
|
|
1117 }
|
|
|
1118 /* Next, successively check PVMx exti flags */
|
|
|
1119 #if defined(PWR_CR2_PVME1)
|
|
|
1120 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET)
|
|
|
1121 {
|
|
|
1122 /* PWR PVM1 interrupt user callback */
|
|
|
1123 HAL_PWREx_PVM1Callback();
|
|
|
1124
|
|
|
1125 /* Clear PVM1 exti pending bit */
|
|
|
1126 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
|
|
|
1127 }
|
|
|
1128 #endif /* PWR_CR2_PVME1 */
|
|
|
1129 #if defined(PWR_CR2_PVME2)
|
|
|
1130 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET)
|
|
|
1131 {
|
|
|
1132 /* PWR PVM2 interrupt user callback */
|
|
|
1133 HAL_PWREx_PVM2Callback();
|
|
|
1134
|
|
|
1135 /* Clear PVM2 exti pending bit */
|
|
|
1136 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
|
|
|
1137 }
|
|
|
1138 #endif /* PWR_CR2_PVME2 */
|
|
|
1139 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET)
|
|
|
1140 {
|
|
|
1141 /* PWR PVM3 interrupt user callback */
|
|
|
1142 HAL_PWREx_PVM3Callback();
|
|
|
1143
|
|
|
1144 /* Clear PVM3 exti pending bit */
|
|
|
1145 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
|
|
|
1146 }
|
|
|
1147 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET)
|
|
|
1148 {
|
|
|
1149 /* PWR PVM4 interrupt user callback */
|
|
|
1150 HAL_PWREx_PVM4Callback();
|
|
|
1151
|
|
|
1152 /* Clear PVM4 exti pending bit */
|
|
|
1153 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
|
|
|
1154 }
|
|
|
1155 }
|
|
|
1156
|
|
|
1157
|
|
|
1158 #if defined(PWR_CR2_PVME1)
|
|
|
1159 /**
|
|
|
1160 * @brief PWR PVM1 interrupt callback
|
|
|
1161 * @retval None
|
|
|
1162 */
|
|
|
1163 __weak void HAL_PWREx_PVM1Callback(void)
|
|
|
1164 {
|
|
|
1165 /* NOTE : This function should not be modified; when the callback is needed,
|
|
|
1166 HAL_PWREx_PVM1Callback() API can be implemented in the user file
|
|
|
1167 */
|
|
|
1168 }
|
|
|
1169 #endif /* PWR_CR2_PVME1 */
|
|
|
1170
|
|
|
1171 #if defined(PWR_CR2_PVME2)
|
|
|
1172 /**
|
|
|
1173 * @brief PWR PVM2 interrupt callback
|
|
|
1174 * @retval None
|
|
|
1175 */
|
|
|
1176 __weak void HAL_PWREx_PVM2Callback(void)
|
|
|
1177 {
|
|
|
1178 /* NOTE : This function should not be modified; when the callback is needed,
|
|
|
1179 HAL_PWREx_PVM2Callback() API can be implemented in the user file
|
|
|
1180 */
|
|
|
1181 }
|
|
|
1182 #endif /* PWR_CR2_PVME2 */
|
|
|
1183
|
|
|
1184 /**
|
|
|
1185 * @brief PWR PVM3 interrupt callback
|
|
|
1186 * @retval None
|
|
|
1187 */
|
|
|
1188 __weak void HAL_PWREx_PVM3Callback(void)
|
|
|
1189 {
|
|
|
1190 /* NOTE : This function should not be modified; when the callback is needed,
|
|
|
1191 HAL_PWREx_PVM3Callback() API can be implemented in the user file
|
|
|
1192 */
|
|
|
1193 }
|
|
|
1194
|
|
|
1195 /**
|
|
|
1196 * @brief PWR PVM4 interrupt callback
|
|
|
1197 * @retval None
|
|
|
1198 */
|
|
|
1199 __weak void HAL_PWREx_PVM4Callback(void)
|
|
|
1200 {
|
|
|
1201 /* NOTE : This function should not be modified; when the callback is needed,
|
|
|
1202 HAL_PWREx_PVM4Callback() API can be implemented in the user file
|
|
|
1203 */
|
|
|
1204 }
|
|
|
1205
|
|
|
1206
|
|
|
1207 /**
|
|
|
1208 * @}
|
|
|
1209 */
|
|
|
1210
|
|
|
1211 /**
|
|
|
1212 * @}
|
|
|
1213 */
|
|
|
1214
|
|
|
1215 #endif /* HAL_PWR_MODULE_ENABLED */
|
|
|
1216 /**
|
|
|
1217 * @}
|
|
|
1218 */
|
|
|
1219
|
|
|
1220 /**
|
|
|
1221 * @}
|
|
|
1222 */
|
|
|
1223
|
|
|
1224 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
