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1 /**
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2 ******************************************************************************
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3 * @file stm32l4xx_hal_tim.c
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4 * @author MCD Application Team
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5 * @version V1.6.0
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6 * @date 28-October-2016
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7 * @brief TIM HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the Timer (TIM) peripheral:
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10 * + Time Base Initialization
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11 * + Time Base Start
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12 * + Time Base Start Interruption
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13 * + Time Base Start DMA
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14 * + Time Output Compare/PWM Initialization
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15 * + Time Output Compare/PWM Channel Configuration
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16 * + Time Output Compare/PWM Start
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17 * + Time Output Compare/PWM Start Interruption
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18 * + Time Output Compare/PWM Start DMA
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19 * + Time Input Capture Initialization
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20 * + Time Input Capture Channel Configuration
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21 * + Time Input Capture Start
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22 * + Time Input Capture Start Interruption
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23 * + Time Input Capture Start DMA
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24 * + Time One Pulse Initialization
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25 * + Time One Pulse Channel Configuration
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26 * + Time One Pulse Start
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27 * + Time Encoder Interface Initialization
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28 * + Time Encoder Interface Start
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29 * + Time Encoder Interface Start Interruption
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30 * + Time Encoder Interface Start DMA
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31 * + Commutation Event configuration with Interruption and DMA
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32 * + Time OCRef clear configuration
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33 * + Time External Clock configuration
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34 @verbatim
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35 ==============================================================================
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36 ##### TIMER Generic features #####
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37 ==============================================================================
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38 [..] The Timer features include:
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39 (#) 16-bit up, down, up/down auto-reload counter.
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40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
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41 counter clock frequency either by any factor between 1 and 65536.
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42 (#) Up to 4 independent channels for:
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43 (++) Input Capture
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44 (++) Output Compare
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45 (++) PWM generation (Edge and Center-aligned Mode)
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46 (++) One-pulse mode output
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47
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48 ##### How to use this driver #####
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49 ==============================================================================
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50 [..]
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51 (#) Initialize the TIM low level resources by implementing the following functions
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52 depending on the selected feature:
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53 (++) Time Base : HAL_TIM_Base_MspInit()
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54 (++) Input Capture : HAL_TIM_IC_MspInit()
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55 (++) Output Compare : HAL_TIM_OC_MspInit()
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56 (++) PWM generation : HAL_TIM_PWM_MspInit()
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57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
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58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
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59
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60 (#) Initialize the TIM low level resources :
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61 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
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62 (##) TIM pins configuration
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63 (+++) Enable the clock for the TIM GPIOs using the following function:
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64 __HAL_RCC_GPIOx_CLK_ENABLE();
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65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
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66
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67 (#) The external Clock can be configured, if needed (the default clock is the
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68 internal clock from the APBx), using the following function:
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69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
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70 any start function.
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71
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72 (#) Configure the TIM in the desired functioning mode using one of the
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73 Initialization function of this driver:
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74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
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75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
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76 Output Compare signal.
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77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
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78 PWM signal.
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79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
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80 external signal.
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81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
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82 in One Pulse Mode.
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83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
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84
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85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
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86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
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87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
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88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
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89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
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90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
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91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
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92
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93 (#) The DMA Burst is managed with the two following functions:
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94 HAL_TIM_DMABurst_WriteStart()
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95 HAL_TIM_DMABurst_ReadStart()
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96
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97 @endverbatim
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98 ******************************************************************************
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99 * @attention
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100 *
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101 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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102 *
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103 * Redistribution and use in source and binary forms, with or without modification,
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104 * are permitted provided that the following conditions are met:
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105 * 1. Redistributions of source code must retain the above copyright notice,
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106 * this list of conditions and the following disclaimer.
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107 * 2. Redistributions in binary form must reproduce the above copyright notice,
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108 * this list of conditions and the following disclaimer in the documentation
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109 * and/or other materials provided with the distribution.
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110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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111 * may be used to endorse or promote products derived from this software
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112 * without specific prior written permission.
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113 *
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114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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124 *
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125 ******************************************************************************
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126 */
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127
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128 /* Includes ------------------------------------------------------------------*/
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129 #include "stm32l4xx_hal.h"
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130
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131 /** @addtogroup STM32L4xx_HAL_Driver
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132 * @{
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133 */
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134
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135 /** @defgroup TIM TIM
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136 * @brief TIM HAL module driver
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137 * @{
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138 */
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139
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140 #ifdef HAL_TIM_MODULE_ENABLED
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141
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142 /* Private typedef -----------------------------------------------------------*/
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143 /* Private define ------------------------------------------------------------*/
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144 /* Private macro -------------------------------------------------------------*/
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145 /* Private variables ---------------------------------------------------------*/
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146 /* Private function prototypes -----------------------------------------------*/
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147 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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148 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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149 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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150 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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151 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
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152 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
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153 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
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154 uint32_t TIM_ICFilter);
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155 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
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156 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
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157 uint32_t TIM_ICFilter);
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158 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
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159 uint32_t TIM_ICFilter);
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160 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
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161 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
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162 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
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163 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
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164 TIM_SlaveConfigTypeDef * sSlaveConfig);
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165 /* Exported functions --------------------------------------------------------*/
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166
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167 /** @defgroup TIM_Exported_Functions TIM Exported Functions
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168 * @{
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169 */
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170
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171 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
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172 * @brief Time Base functions
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173 *
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174 @verbatim
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175 ==============================================================================
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176 ##### Time Base functions #####
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177 ==============================================================================
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178 [..]
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179 This section provides functions allowing to:
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180 (+) Initialize and configure the TIM base.
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181 (+) De-initialize the TIM base.
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182 (+) Start the Time Base.
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183 (+) Stop the Time Base.
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184 (+) Start the Time Base and enable interrupt.
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185 (+) Stop the Time Base and disable interrupt.
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186 (+) Start the Time Base and enable DMA transfer.
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187 (+) Stop the Time Base and disable DMA transfer.
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188
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189 @endverbatim
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190 * @{
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191 */
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192 /**
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193 * @brief Initializes the TIM Time base Unit according to the specified
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194 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
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195 * @param htim: TIM Base handle
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196 * @retval HAL status
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197 */
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198 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
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199 {
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200 /* Check the TIM handle allocation */
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201 if(htim == NULL)
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202 {
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203 return HAL_ERROR;
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204 }
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205
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206 /* Check the parameters */
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207 assert_param(IS_TIM_INSTANCE(htim->Instance));
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208 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
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209 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
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210
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211 if(htim->State == HAL_TIM_STATE_RESET)
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212 {
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213 /* Allocate lock resource and initialize it */
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214 htim->Lock = HAL_UNLOCKED;
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215
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216 /* Init the low level hardware : GPIO, CLOCK, NVIC */
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217 HAL_TIM_Base_MspInit(htim);
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218 }
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219
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220 /* Set the TIM state */
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221 htim->State= HAL_TIM_STATE_BUSY;
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222
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223 /* Set the Time Base configuration */
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224 TIM_Base_SetConfig(htim->Instance, &htim->Init);
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225
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226 /* Initialize the TIM state*/
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227 htim->State= HAL_TIM_STATE_READY;
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228
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229 return HAL_OK;
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230 }
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231
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232 /**
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233 * @brief DeInitialize the TIM Base peripheral
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234 * @param htim: TIM Base handle
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235 * @retval HAL status
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236 */
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237 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
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238 {
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239 /* Check the parameters */
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240 assert_param(IS_TIM_INSTANCE(htim->Instance));
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241
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242 htim->State = HAL_TIM_STATE_BUSY;
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243
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244 /* Disable the TIM Peripheral Clock */
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245 __HAL_TIM_DISABLE(htim);
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246
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247 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
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248 HAL_TIM_Base_MspDeInit(htim);
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249
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250 /* Change TIM state */
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251 htim->State = HAL_TIM_STATE_RESET;
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252
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253 /* Release Lock */
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254 __HAL_UNLOCK(htim);
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255
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256 return HAL_OK;
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257 }
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258
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259 /**
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260 * @brief Initializes the TIM Base MSP.
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261 * @param htim: TIM handle
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262 * @retval None
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263 */
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264 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
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265 {
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266 /* Prevent unused argument(s) compilation warning */
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267 UNUSED(htim);
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268
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269 /* NOTE : This function should not be modified, when the callback is needed,
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270 the HAL_TIM_Base_MspInit could be implemented in the user file
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271 */
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272 }
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273
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274 /**
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275 * @brief DeInitialize TIM Base MSP.
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276 * @param htim: TIM handle
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277 * @retval None
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278 */
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279 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
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280 {
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281 /* Prevent unused argument(s) compilation warning */
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282 UNUSED(htim);
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283
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284 /* NOTE : This function should not be modified, when the callback is needed,
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285 the HAL_TIM_Base_MspDeInit could be implemented in the user file
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286 */
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287 }
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288
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289
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290 /**
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291 * @brief Starts the TIM Base generation.
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292 * @param htim : TIM handle
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293 * @retval HAL status
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294 */
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295 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
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296 {
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297 /* Check the parameters */
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298 assert_param(IS_TIM_INSTANCE(htim->Instance));
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299
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300 /* Set the TIM state */
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301 htim->State= HAL_TIM_STATE_BUSY;
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302
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303 /* Enable the Peripheral */
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304 __HAL_TIM_ENABLE(htim);
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305
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306 /* Change the TIM state*/
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307 htim->State= HAL_TIM_STATE_READY;
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308
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309 /* Return function status */
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310 return HAL_OK;
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311 }
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312
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313 /**
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314 * @brief Stops the TIM Base generation.
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315 * @param htim : TIM handle
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316 * @retval HAL status
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317 */
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318 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
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319 {
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320 /* Check the parameters */
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321 assert_param(IS_TIM_INSTANCE(htim->Instance));
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322
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323 /* Set the TIM state */
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324 htim->State= HAL_TIM_STATE_BUSY;
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325
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326 /* Disable the Peripheral */
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327 __HAL_TIM_DISABLE(htim);
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328
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329 /* Change the TIM state*/
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330 htim->State= HAL_TIM_STATE_READY;
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331
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332 /* Return function status */
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333 return HAL_OK;
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334 }
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335
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336 /**
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337 * @brief Starts the TIM Base generation in interrupt mode.
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338 * @param htim : TIM handle
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339 * @retval HAL status
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340 */
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341 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
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342 {
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343 /* Check the parameters */
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344 assert_param(IS_TIM_INSTANCE(htim->Instance));
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345
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346 /* Enable the TIM Update interrupt */
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347 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
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348
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349 /* Enable the Peripheral */
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350 __HAL_TIM_ENABLE(htim);
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351
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352 /* Return function status */
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353 return HAL_OK;
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354 }
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355
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356 /**
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357 * @brief Stops the TIM Base generation in interrupt mode.
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358 * @param htim : TIM handle
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359 * @retval HAL status
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360 */
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361 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
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362 {
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363 /* Check the parameters */
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364 assert_param(IS_TIM_INSTANCE(htim->Instance));
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365 /* Disable the TIM Update interrupt */
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366 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
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367
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368 /* Disable the Peripheral */
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369 __HAL_TIM_DISABLE(htim);
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370
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371 /* Return function status */
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372 return HAL_OK;
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373 }
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374
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375 /**
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376 * @brief Starts the TIM Base generation in DMA mode.
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377 * @param htim : TIM handle
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378 * @param pData: The source Buffer address.
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379 * @param Length: The length of data to be transferred from memory to peripheral.
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380 * @retval HAL status
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381 */
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382 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
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383 {
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384 /* Check the parameters */
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385 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
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386
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387 if((htim->State == HAL_TIM_STATE_BUSY))
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388 {
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389 return HAL_BUSY;
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390 }
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391 else if((htim->State == HAL_TIM_STATE_READY))
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392 {
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393 if((pData == 0 ) && (Length > 0))
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394 {
|
|
|
395 return HAL_ERROR;
|
|
|
396 }
|
|
|
397 else
|
|
|
398 {
|
|
|
399 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
400 }
|
|
|
401 }
|
|
|
402 /* Set the DMA Period elapsed callback */
|
|
|
403 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
|
|
|
404
|
|
|
405 /* Set the DMA error callback */
|
|
|
406 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
|
|
|
407
|
|
|
408 /* Enable the DMA channel */
|
|
|
409 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
|
|
|
410
|
|
|
411 /* Enable the TIM Update DMA request */
|
|
|
412 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
|
|
|
413
|
|
|
414 /* Enable the Peripheral */
|
|
|
415 __HAL_TIM_ENABLE(htim);
|
|
|
416
|
|
|
417 /* Return function status */
|
|
|
418 return HAL_OK;
|
|
|
419 }
|
|
|
420
|
|
|
421 /**
|
|
|
422 * @brief Stops the TIM Base generation in DMA mode.
|
|
|
423 * @param htim : TIM handle
|
|
|
424 * @retval HAL status
|
|
|
425 */
|
|
|
426 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
|
|
|
427 {
|
|
|
428 /* Check the parameters */
|
|
|
429 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
|
|
|
430
|
|
|
431 /* Disable the TIM Update DMA request */
|
|
|
432 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
|
|
|
433
|
|
|
434 /* Disable the Peripheral */
|
|
|
435 __HAL_TIM_DISABLE(htim);
|
|
|
436
|
|
|
437 /* Change the htim state */
|
|
|
438 htim->State = HAL_TIM_STATE_READY;
|
|
|
439
|
|
|
440 /* Return function status */
|
|
|
441 return HAL_OK;
|
|
|
442 }
|
|
|
443
|
|
|
444 /**
|
|
|
445 * @}
|
|
|
446 */
|
|
|
447
|
|
|
448 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
|
|
|
449 * @brief Time Output Compare functions
|
|
|
450 *
|
|
|
451 @verbatim
|
|
|
452 ==============================================================================
|
|
|
453 ##### Time Output Compare functions #####
|
|
|
454 ==============================================================================
|
|
|
455 [..]
|
|
|
456 This section provides functions allowing to:
|
|
|
457 (+) Initialize and configure the TIM Output Compare.
|
|
|
458 (+) De-initialize the TIM Output Compare.
|
|
|
459 (+) Start the Time Output Compare.
|
|
|
460 (+) Stop the Time Output Compare.
|
|
|
461 (+) Start the Time Output Compare and enable interrupt.
|
|
|
462 (+) Stop the Time Output Compare and disable interrupt.
|
|
|
463 (+) Start the Time Output Compare and enable DMA transfer.
|
|
|
464 (+) Stop the Time Output Compare and disable DMA transfer.
|
|
|
465
|
|
|
466 @endverbatim
|
|
|
467 * @{
|
|
|
468 */
|
|
|
469 /**
|
|
|
470 * @brief Initializes the TIM Output Compare according to the specified
|
|
|
471 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
|
|
|
472 * @param htim: TIM Output Compare handle
|
|
|
473 * @retval HAL status
|
|
|
474 */
|
|
|
475 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
|
|
|
476 {
|
|
|
477 /* Check the TIM handle allocation */
|
|
|
478 if(htim == NULL)
|
|
|
479 {
|
|
|
480 return HAL_ERROR;
|
|
|
481 }
|
|
|
482
|
|
|
483 /* Check the parameters */
|
|
|
484 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
485 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
|
486 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
|
487
|
|
|
488 if(htim->State == HAL_TIM_STATE_RESET)
|
|
|
489 {
|
|
|
490 /* Allocate lock resource and initialize it */
|
|
|
491 htim->Lock = HAL_UNLOCKED;
|
|
|
492
|
|
|
493 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
|
494 HAL_TIM_OC_MspInit(htim);
|
|
|
495 }
|
|
|
496
|
|
|
497 /* Set the TIM state */
|
|
|
498 htim->State= HAL_TIM_STATE_BUSY;
|
|
|
499
|
|
|
500 /* Init the base time for the Output Compare */
|
|
|
501 TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
|
502
|
|
|
503 /* Initialize the TIM state*/
|
|
|
504 htim->State= HAL_TIM_STATE_READY;
|
|
|
505
|
|
|
506 return HAL_OK;
|
|
|
507 }
|
|
|
508
|
|
|
509 /**
|
|
|
510 * @brief DeInitialize the TIM peripheral
|
|
|
511 * @param htim: TIM Output Compare handle
|
|
|
512 * @retval HAL status
|
|
|
513 */
|
|
|
514 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
|
|
|
515 {
|
|
|
516 /* Check the parameters */
|
|
|
517 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
518
|
|
|
519 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
520
|
|
|
521 /* Disable the TIM Peripheral Clock */
|
|
|
522 __HAL_TIM_DISABLE(htim);
|
|
|
523
|
|
|
524 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
|
|
|
525 HAL_TIM_OC_MspDeInit(htim);
|
|
|
526
|
|
|
527 /* Change TIM state */
|
|
|
528 htim->State = HAL_TIM_STATE_RESET;
|
|
|
529
|
|
|
530 /* Release Lock */
|
|
|
531 __HAL_UNLOCK(htim);
|
|
|
532
|
|
|
533 return HAL_OK;
|
|
|
534 }
|
|
|
535
|
|
|
536 /**
|
|
|
537 * @brief Initializes the TIM Output Compare MSP.
|
|
|
538 * @param htim: TIM handle
|
|
|
539 * @retval None
|
|
|
540 */
|
|
|
541 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
|
|
|
542 {
|
|
|
543 /* Prevent unused argument(s) compilation warning */
|
|
|
544 UNUSED(htim);
|
|
|
545
|
|
|
546 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
547 the HAL_TIM_OC_MspInit could be implemented in the user file
|
|
|
548 */
|
|
|
549 }
|
|
|
550
|
|
|
551 /**
|
|
|
552 * @brief DeInitialize TIM Output Compare MSP.
|
|
|
553 * @param htim: TIM handle
|
|
|
554 * @retval None
|
|
|
555 */
|
|
|
556 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
|
|
|
557 {
|
|
|
558 /* Prevent unused argument(s) compilation warning */
|
|
|
559 UNUSED(htim);
|
|
|
560
|
|
|
561 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
562 the HAL_TIM_OC_MspDeInit could be implemented in the user file
|
|
|
563 */
|
|
|
564 }
|
|
|
565
|
|
|
566 /**
|
|
|
567 * @brief Starts the TIM Output Compare signal generation.
|
|
|
568 * @param htim : TIM Output Compare handle
|
|
|
569 * @param Channel : TIM Channel to be enabled
|
|
|
570 * This parameter can be one of the following values:
|
|
|
571 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
572 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
573 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
574 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
575 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
576 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
577 * @retval HAL status
|
|
|
578 */
|
|
|
579 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
580 {
|
|
|
581 /* Check the parameters */
|
|
|
582 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
583
|
|
|
584 /* Enable the Output compare channel */
|
|
|
585 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
|
586
|
|
|
587 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
588 {
|
|
|
589 /* Enable the main output */
|
|
|
590 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
591 }
|
|
|
592
|
|
|
593 /* Enable the Peripheral */
|
|
|
594 __HAL_TIM_ENABLE(htim);
|
|
|
595
|
|
|
596 /* Return function status */
|
|
|
597 return HAL_OK;
|
|
|
598 }
|
|
|
599
|
|
|
600 /**
|
|
|
601 * @brief Stops the TIM Output Compare signal generation.
|
|
|
602 * @param htim : TIM handle
|
|
|
603 * @param Channel : TIM Channel to be disabled
|
|
|
604 * This parameter can be one of the following values:
|
|
|
605 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
606 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
607 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
608 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
609 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
610 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
611 * @retval HAL status
|
|
|
612 */
|
|
|
613 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
614 {
|
|
|
615 /* Check the parameters */
|
|
|
616 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
617
|
|
|
618 /* Disable the Output compare channel */
|
|
|
619 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
|
620
|
|
|
621 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
622 {
|
|
|
623 /* Disable the Main Ouput */
|
|
|
624 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
625 }
|
|
|
626
|
|
|
627 /* Disable the Peripheral */
|
|
|
628 __HAL_TIM_DISABLE(htim);
|
|
|
629
|
|
|
630 /* Return function status */
|
|
|
631 return HAL_OK;
|
|
|
632 }
|
|
|
633
|
|
|
634 /**
|
|
|
635 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
|
|
|
636 * @param htim : TIM OC handle
|
|
|
637 * @param Channel : TIM Channel to be enabled
|
|
|
638 * This parameter can be one of the following values:
|
|
|
639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
643 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
644 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
645 * @retval HAL status
|
|
|
646 */
|
|
|
647 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
648 {
|
|
|
649 /* Check the parameters */
|
|
|
650 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
651
|
|
|
652 switch (Channel)
|
|
|
653 {
|
|
|
654 case TIM_CHANNEL_1:
|
|
|
655 {
|
|
|
656 /* Enable the TIM Capture/Compare 1 interrupt */
|
|
|
657 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
658 }
|
|
|
659 break;
|
|
|
660
|
|
|
661 case TIM_CHANNEL_2:
|
|
|
662 {
|
|
|
663 /* Enable the TIM Capture/Compare 2 interrupt */
|
|
|
664 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
665 }
|
|
|
666 break;
|
|
|
667
|
|
|
668 case TIM_CHANNEL_3:
|
|
|
669 {
|
|
|
670 /* Enable the TIM Capture/Compare 3 interrupt */
|
|
|
671 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
|
|
672 }
|
|
|
673 break;
|
|
|
674
|
|
|
675 case TIM_CHANNEL_4:
|
|
|
676 {
|
|
|
677 /* Enable the TIM Capture/Compare 4 interrupt */
|
|
|
678 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
|
|
679 }
|
|
|
680 break;
|
|
|
681
|
|
|
682 default:
|
|
|
683 break;
|
|
|
684 }
|
|
|
685
|
|
|
686 /* Enable the Output compare channel */
|
|
|
687 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
|
688
|
|
|
689 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
690 {
|
|
|
691 /* Enable the main output */
|
|
|
692 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
693 }
|
|
|
694
|
|
|
695 /* Enable the Peripheral */
|
|
|
696 __HAL_TIM_ENABLE(htim);
|
|
|
697
|
|
|
698 /* Return function status */
|
|
|
699 return HAL_OK;
|
|
|
700 }
|
|
|
701
|
|
|
702 /**
|
|
|
703 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
|
|
|
704 * @param htim : TIM Output Compare handle
|
|
|
705 * @param Channel : TIM Channel to be disabled
|
|
|
706 * This parameter can be one of the following values:
|
|
|
707 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
708 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
709 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
710 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
711 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
712 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
713 * @retval HAL status
|
|
|
714 */
|
|
|
715 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
716 {
|
|
|
717 /* Check the parameters */
|
|
|
718 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
719
|
|
|
720 switch (Channel)
|
|
|
721 {
|
|
|
722 case TIM_CHANNEL_1:
|
|
|
723 {
|
|
|
724 /* Disable the TIM Capture/Compare 1 interrupt */
|
|
|
725 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
726 }
|
|
|
727 break;
|
|
|
728
|
|
|
729 case TIM_CHANNEL_2:
|
|
|
730 {
|
|
|
731 /* Disable the TIM Capture/Compare 2 interrupt */
|
|
|
732 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
733 }
|
|
|
734 break;
|
|
|
735
|
|
|
736 case TIM_CHANNEL_3:
|
|
|
737 {
|
|
|
738 /* Disable the TIM Capture/Compare 3 interrupt */
|
|
|
739 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
|
|
740 }
|
|
|
741 break;
|
|
|
742
|
|
|
743 case TIM_CHANNEL_4:
|
|
|
744 {
|
|
|
745 /* Disable the TIM Capture/Compare 4 interrupt */
|
|
|
746 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
|
|
747 }
|
|
|
748 break;
|
|
|
749
|
|
|
750 default:
|
|
|
751 break;
|
|
|
752 }
|
|
|
753
|
|
|
754 /* Disable the Output compare channel */
|
|
|
755 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
|
756
|
|
|
757 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
758 {
|
|
|
759 /* Disable the Main Ouput */
|
|
|
760 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
761 }
|
|
|
762
|
|
|
763 /* Disable the Peripheral */
|
|
|
764 __HAL_TIM_DISABLE(htim);
|
|
|
765
|
|
|
766 /* Return function status */
|
|
|
767 return HAL_OK;
|
|
|
768 }
|
|
|
769
|
|
|
770 /**
|
|
|
771 * @brief Starts the TIM Output Compare signal generation in DMA mode.
|
|
|
772 * @param htim : TIM Output Compare handle
|
|
|
773 * @param Channel : TIM Channel to be enabled
|
|
|
774 * This parameter can be one of the following values:
|
|
|
775 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
776 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
777 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
778 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
779 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
780 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
781 * @param pData: The source Buffer address.
|
|
|
782 * @param Length: The length of data to be transferred from memory to TIM peripheral
|
|
|
783 * @retval HAL status
|
|
|
784 */
|
|
|
785 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
|
|
786 {
|
|
|
787 /* Check the parameters */
|
|
|
788 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
789
|
|
|
790 if((htim->State == HAL_TIM_STATE_BUSY))
|
|
|
791 {
|
|
|
792 return HAL_BUSY;
|
|
|
793 }
|
|
|
794 else if((htim->State == HAL_TIM_STATE_READY))
|
|
|
795 {
|
|
|
796 if(((uint32_t)pData == 0 ) && (Length > 0))
|
|
|
797 {
|
|
|
798 return HAL_ERROR;
|
|
|
799 }
|
|
|
800 else
|
|
|
801 {
|
|
|
802 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
803 }
|
|
|
804 }
|
|
|
805 switch (Channel)
|
|
|
806 {
|
|
|
807 case TIM_CHANNEL_1:
|
|
|
808 {
|
|
|
809 /* Set the DMA Period elapsed callback */
|
|
|
810 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
811
|
|
|
812 /* Set the DMA error callback */
|
|
|
813 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
814
|
|
|
815 /* Enable the DMA channel */
|
|
|
816 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
|
|
|
817
|
|
|
818 /* Enable the TIM Capture/Compare 1 DMA request */
|
|
|
819 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
820 }
|
|
|
821 break;
|
|
|
822
|
|
|
823 case TIM_CHANNEL_2:
|
|
|
824 {
|
|
|
825 /* Set the DMA Period elapsed callback */
|
|
|
826 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
827
|
|
|
828 /* Set the DMA error callback */
|
|
|
829 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
830
|
|
|
831 /* Enable the DMA channel */
|
|
|
832 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
|
|
|
833
|
|
|
834 /* Enable the TIM Capture/Compare 2 DMA request */
|
|
|
835 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
836 }
|
|
|
837 break;
|
|
|
838
|
|
|
839 case TIM_CHANNEL_3:
|
|
|
840 {
|
|
|
841 /* Set the DMA Period elapsed callback */
|
|
|
842 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
843
|
|
|
844 /* Set the DMA error callback */
|
|
|
845 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
|
|
846
|
|
|
847 /* Enable the DMA channel */
|
|
|
848 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
|
|
|
849
|
|
|
850 /* Enable the TIM Capture/Compare 3 DMA request */
|
|
|
851 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
852 }
|
|
|
853 break;
|
|
|
854
|
|
|
855 case TIM_CHANNEL_4:
|
|
|
856 {
|
|
|
857 /* Set the DMA Period elapsed callback */
|
|
|
858 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
859
|
|
|
860 /* Set the DMA error callback */
|
|
|
861 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
|
|
862
|
|
|
863 /* Enable the DMA channel */
|
|
|
864 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
|
|
|
865
|
|
|
866 /* Enable the TIM Capture/Compare 4 DMA request */
|
|
|
867 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
868 }
|
|
|
869 break;
|
|
|
870
|
|
|
871 default:
|
|
|
872 break;
|
|
|
873 }
|
|
|
874
|
|
|
875 /* Enable the Output compare channel */
|
|
|
876 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
|
877
|
|
|
878 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
879 {
|
|
|
880 /* Enable the main output */
|
|
|
881 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
882 }
|
|
|
883
|
|
|
884 /* Enable the Peripheral */
|
|
|
885 __HAL_TIM_ENABLE(htim);
|
|
|
886
|
|
|
887 /* Return function status */
|
|
|
888 return HAL_OK;
|
|
|
889 }
|
|
|
890
|
|
|
891 /**
|
|
|
892 * @brief Stops the TIM Output Compare signal generation in DMA mode.
|
|
|
893 * @param htim : TIM Output Compare handle
|
|
|
894 * @param Channel : TIM Channel to be disabled
|
|
|
895 * This parameter can be one of the following values:
|
|
|
896 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
897 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
898 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
899 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
900 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
901 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
902 * @retval HAL status
|
|
|
903 */
|
|
|
904 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
905 {
|
|
|
906 /* Check the parameters */
|
|
|
907 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
908
|
|
|
909 switch (Channel)
|
|
|
910 {
|
|
|
911 case TIM_CHANNEL_1:
|
|
|
912 {
|
|
|
913 /* Disable the TIM Capture/Compare 1 DMA request */
|
|
|
914 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
915 }
|
|
|
916 break;
|
|
|
917
|
|
|
918 case TIM_CHANNEL_2:
|
|
|
919 {
|
|
|
920 /* Disable the TIM Capture/Compare 2 DMA request */
|
|
|
921 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
922 }
|
|
|
923 break;
|
|
|
924
|
|
|
925 case TIM_CHANNEL_3:
|
|
|
926 {
|
|
|
927 /* Disable the TIM Capture/Compare 3 DMA request */
|
|
|
928 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
929 }
|
|
|
930 break;
|
|
|
931
|
|
|
932 case TIM_CHANNEL_4:
|
|
|
933 {
|
|
|
934 /* Disable the TIM Capture/Compare 4 interrupt */
|
|
|
935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
936 }
|
|
|
937 break;
|
|
|
938
|
|
|
939 default:
|
|
|
940 break;
|
|
|
941 }
|
|
|
942
|
|
|
943 /* Disable the Output compare channel */
|
|
|
944 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
|
945
|
|
|
946 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
947 {
|
|
|
948 /* Disable the Main Ouput */
|
|
|
949 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
950 }
|
|
|
951
|
|
|
952 /* Disable the Peripheral */
|
|
|
953 __HAL_TIM_DISABLE(htim);
|
|
|
954
|
|
|
955 /* Change the htim state */
|
|
|
956 htim->State = HAL_TIM_STATE_READY;
|
|
|
957
|
|
|
958 /* Return function status */
|
|
|
959 return HAL_OK;
|
|
|
960 }
|
|
|
961
|
|
|
962 /**
|
|
|
963 * @}
|
|
|
964 */
|
|
|
965
|
|
|
966 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
|
|
|
967 * @brief Time PWM functions
|
|
|
968 *
|
|
|
969 @verbatim
|
|
|
970 ==============================================================================
|
|
|
971 ##### Time PWM functions #####
|
|
|
972 ==============================================================================
|
|
|
973 [..]
|
|
|
974 This section provides functions allowing to:
|
|
|
975 (+) Initialize and configure the TIM OPWM.
|
|
|
976 (+) De-initialize the TIM PWM.
|
|
|
977 (+) Start the Time PWM.
|
|
|
978 (+) Stop the Time PWM.
|
|
|
979 (+) Start the Time PWM and enable interrupt.
|
|
|
980 (+) Stop the Time PWM and disable interrupt.
|
|
|
981 (+) Start the Time PWM and enable DMA transfer.
|
|
|
982 (+) Stop the Time PWM and disable DMA transfer.
|
|
|
983
|
|
|
984 @endverbatim
|
|
|
985 * @{
|
|
|
986 */
|
|
|
987 /**
|
|
|
988 * @brief Initializes the TIM PWM Time Base according to the specified
|
|
|
989 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
|
|
|
990 * @param htim: TIM handle
|
|
|
991 * @retval HAL status
|
|
|
992 */
|
|
|
993 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
|
994 {
|
|
|
995 /* Check the TIM handle allocation */
|
|
|
996 if(htim == NULL)
|
|
|
997 {
|
|
|
998 return HAL_ERROR;
|
|
|
999 }
|
|
|
1000
|
|
|
1001 /* Check the parameters */
|
|
|
1002 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
1003 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
|
1004 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
|
1005
|
|
|
1006 if(htim->State == HAL_TIM_STATE_RESET)
|
|
|
1007 {
|
|
|
1008 /* Allocate lock resource and initialize it */
|
|
|
1009 htim->Lock = HAL_UNLOCKED;
|
|
|
1010
|
|
|
1011 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
|
1012 HAL_TIM_PWM_MspInit(htim);
|
|
|
1013 }
|
|
|
1014
|
|
|
1015 /* Set the TIM state */
|
|
|
1016 htim->State= HAL_TIM_STATE_BUSY;
|
|
|
1017
|
|
|
1018 /* Init the base time for the PWM */
|
|
|
1019 TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
|
1020
|
|
|
1021 /* Initialize the TIM state*/
|
|
|
1022 htim->State= HAL_TIM_STATE_READY;
|
|
|
1023
|
|
|
1024 return HAL_OK;
|
|
|
1025 }
|
|
|
1026
|
|
|
1027 /**
|
|
|
1028 * @brief DeInitialize the TIM peripheral
|
|
|
1029 * @param htim: TIM handle
|
|
|
1030 * @retval HAL status
|
|
|
1031 */
|
|
|
1032 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
|
|
|
1033 {
|
|
|
1034 /* Check the parameters */
|
|
|
1035 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
1036
|
|
|
1037 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
1038
|
|
|
1039 /* Disable the TIM Peripheral Clock */
|
|
|
1040 __HAL_TIM_DISABLE(htim);
|
|
|
1041
|
|
|
1042 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
|
|
|
1043 HAL_TIM_PWM_MspDeInit(htim);
|
|
|
1044
|
|
|
1045 /* Change TIM state */
|
|
|
1046 htim->State = HAL_TIM_STATE_RESET;
|
|
|
1047
|
|
|
1048 /* Release Lock */
|
|
|
1049 __HAL_UNLOCK(htim);
|
|
|
1050
|
|
|
1051 return HAL_OK;
|
|
|
1052 }
|
|
|
1053
|
|
|
1054 /**
|
|
|
1055 * @brief Initializes the TIM PWM MSP.
|
|
|
1056 * @param htim: TIM handle
|
|
|
1057 * @retval None
|
|
|
1058 */
|
|
|
1059 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
|
|
|
1060 {
|
|
|
1061 /* Prevent unused argument(s) compilation warning */
|
|
|
1062 UNUSED(htim);
|
|
|
1063
|
|
|
1064 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
1065 the HAL_TIM_PWM_MspInit could be implemented in the user file
|
|
|
1066 */
|
|
|
1067 }
|
|
|
1068
|
|
|
1069 /**
|
|
|
1070 * @brief DeInitialize TIM PWM MSP.
|
|
|
1071 * @param htim: TIM handle
|
|
|
1072 * @retval None
|
|
|
1073 */
|
|
|
1074 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
|
|
|
1075 {
|
|
|
1076 /* Prevent unused argument(s) compilation warning */
|
|
|
1077 UNUSED(htim);
|
|
|
1078
|
|
|
1079 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
1080 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
|
|
|
1081 */
|
|
|
1082 }
|
|
|
1083
|
|
|
1084 /**
|
|
|
1085 * @brief Starts the PWM signal generation.
|
|
|
1086 * @param htim : TIM handle
|
|
|
1087 * @param Channel : TIM Channels to be enabled
|
|
|
1088 * This parameter can be one of the following values:
|
|
|
1089 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1090 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1091 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1092 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1093 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
1094 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
1095 * @retval HAL status
|
|
|
1096 */
|
|
|
1097 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1098 {
|
|
|
1099 /* Check the parameters */
|
|
|
1100 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1101
|
|
|
1102 /* Enable the Capture compare channel */
|
|
|
1103 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
|
1104
|
|
|
1105 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
1106 {
|
|
|
1107 /* Enable the main output */
|
|
|
1108 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
1109 }
|
|
|
1110
|
|
|
1111 /* Enable the Peripheral */
|
|
|
1112 __HAL_TIM_ENABLE(htim);
|
|
|
1113
|
|
|
1114 /* Return function status */
|
|
|
1115 return HAL_OK;
|
|
|
1116 }
|
|
|
1117
|
|
|
1118 /**
|
|
|
1119 * @brief Stops the PWM signal generation.
|
|
|
1120 * @param htim : TIM handle
|
|
|
1121 * @param Channel : TIM Channels to be disabled
|
|
|
1122 * This parameter can be one of the following values:
|
|
|
1123 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1124 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1125 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1126 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1127 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
1128 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
1129 * @retval HAL status
|
|
|
1130 */
|
|
|
1131 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1132 {
|
|
|
1133 /* Check the parameters */
|
|
|
1134 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1135
|
|
|
1136 /* Disable the Capture compare channel */
|
|
|
1137 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
|
1138
|
|
|
1139 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
1140 {
|
|
|
1141 /* Disable the Main Ouput */
|
|
|
1142 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
1143 }
|
|
|
1144
|
|
|
1145 /* Disable the Peripheral */
|
|
|
1146 __HAL_TIM_DISABLE(htim);
|
|
|
1147
|
|
|
1148 /* Change the htim state */
|
|
|
1149 htim->State = HAL_TIM_STATE_READY;
|
|
|
1150
|
|
|
1151 /* Return function status */
|
|
|
1152 return HAL_OK;
|
|
|
1153 }
|
|
|
1154
|
|
|
1155 /**
|
|
|
1156 * @brief Starts the PWM signal generation in interrupt mode.
|
|
|
1157 * @param htim : TIM handle
|
|
|
1158 * @param Channel : TIM Channel to be enabled
|
|
|
1159 * This parameter can be one of the following values:
|
|
|
1160 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1161 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1162 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1163 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1164 * @retval HAL status
|
|
|
1165 */
|
|
|
1166 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1167 {
|
|
|
1168 /* Check the parameters */
|
|
|
1169 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1170
|
|
|
1171 switch (Channel)
|
|
|
1172 {
|
|
|
1173 case TIM_CHANNEL_1:
|
|
|
1174 {
|
|
|
1175 /* Enable the TIM Capture/Compare 1 interrupt */
|
|
|
1176 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
1177 }
|
|
|
1178 break;
|
|
|
1179
|
|
|
1180 case TIM_CHANNEL_2:
|
|
|
1181 {
|
|
|
1182 /* Enable the TIM Capture/Compare 2 interrupt */
|
|
|
1183 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
1184 }
|
|
|
1185 break;
|
|
|
1186
|
|
|
1187 case TIM_CHANNEL_3:
|
|
|
1188 {
|
|
|
1189 /* Enable the TIM Capture/Compare 3 interrupt */
|
|
|
1190 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
|
|
1191 }
|
|
|
1192 break;
|
|
|
1193
|
|
|
1194 case TIM_CHANNEL_4:
|
|
|
1195 {
|
|
|
1196 /* Enable the TIM Capture/Compare 4 interrupt */
|
|
|
1197 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
|
|
1198 }
|
|
|
1199 break;
|
|
|
1200
|
|
|
1201 default:
|
|
|
1202 break;
|
|
|
1203 }
|
|
|
1204
|
|
|
1205 /* Enable the Capture compare channel */
|
|
|
1206 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
|
1207
|
|
|
1208 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
1209 {
|
|
|
1210 /* Enable the main output */
|
|
|
1211 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
1212 }
|
|
|
1213
|
|
|
1214 /* Enable the Peripheral */
|
|
|
1215 __HAL_TIM_ENABLE(htim);
|
|
|
1216
|
|
|
1217 /* Return function status */
|
|
|
1218 return HAL_OK;
|
|
|
1219 }
|
|
|
1220
|
|
|
1221 /**
|
|
|
1222 * @brief Stops the PWM signal generation in interrupt mode.
|
|
|
1223 * @param htim : TIM handle
|
|
|
1224 * @param Channel : TIM Channels to be disabled
|
|
|
1225 * This parameter can be one of the following values:
|
|
|
1226 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1227 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1228 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1229 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1230 * @retval HAL status
|
|
|
1231 */
|
|
|
1232 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1233 {
|
|
|
1234 /* Check the parameters */
|
|
|
1235 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1236
|
|
|
1237 switch (Channel)
|
|
|
1238 {
|
|
|
1239 case TIM_CHANNEL_1:
|
|
|
1240 {
|
|
|
1241 /* Disable the TIM Capture/Compare 1 interrupt */
|
|
|
1242 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
1243 }
|
|
|
1244 break;
|
|
|
1245
|
|
|
1246 case TIM_CHANNEL_2:
|
|
|
1247 {
|
|
|
1248 /* Disable the TIM Capture/Compare 2 interrupt */
|
|
|
1249 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
1250 }
|
|
|
1251 break;
|
|
|
1252
|
|
|
1253 case TIM_CHANNEL_3:
|
|
|
1254 {
|
|
|
1255 /* Disable the TIM Capture/Compare 3 interrupt */
|
|
|
1256 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
|
|
1257 }
|
|
|
1258 break;
|
|
|
1259
|
|
|
1260 case TIM_CHANNEL_4:
|
|
|
1261 {
|
|
|
1262 /* Disable the TIM Capture/Compare 4 interrupt */
|
|
|
1263 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
|
|
1264 }
|
|
|
1265 break;
|
|
|
1266
|
|
|
1267 default:
|
|
|
1268 break;
|
|
|
1269 }
|
|
|
1270
|
|
|
1271 /* Disable the Capture compare channel */
|
|
|
1272 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
|
1273
|
|
|
1274 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
1275 {
|
|
|
1276 /* Disable the Main Ouput */
|
|
|
1277 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
1278 }
|
|
|
1279
|
|
|
1280 /* Disable the Peripheral */
|
|
|
1281 __HAL_TIM_DISABLE(htim);
|
|
|
1282
|
|
|
1283 /* Return function status */
|
|
|
1284 return HAL_OK;
|
|
|
1285 }
|
|
|
1286
|
|
|
1287 /**
|
|
|
1288 * @brief Starts the TIM PWM signal generation in DMA mode.
|
|
|
1289 * @param htim : TIM handle
|
|
|
1290 * @param Channel : TIM Channels to be enabled
|
|
|
1291 * This parameter can be one of the following values:
|
|
|
1292 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1293 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1294 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1295 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1296 * @param pData: The source Buffer address.
|
|
|
1297 * @param Length: The length of data to be transferred from memory to TIM peripheral
|
|
|
1298 * @retval HAL status
|
|
|
1299 */
|
|
|
1300 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
|
|
1301 {
|
|
|
1302 /* Check the parameters */
|
|
|
1303 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1304
|
|
|
1305 if((htim->State == HAL_TIM_STATE_BUSY))
|
|
|
1306 {
|
|
|
1307 return HAL_BUSY;
|
|
|
1308 }
|
|
|
1309 else if((htim->State == HAL_TIM_STATE_READY))
|
|
|
1310 {
|
|
|
1311 if(((uint32_t)pData == 0 ) && (Length > 0))
|
|
|
1312 {
|
|
|
1313 return HAL_ERROR;
|
|
|
1314 }
|
|
|
1315 else
|
|
|
1316 {
|
|
|
1317 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
1318 }
|
|
|
1319 }
|
|
|
1320 switch (Channel)
|
|
|
1321 {
|
|
|
1322 case TIM_CHANNEL_1:
|
|
|
1323 {
|
|
|
1324 /* Set the DMA Period elapsed callback */
|
|
|
1325 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
1326
|
|
|
1327 /* Set the DMA error callback */
|
|
|
1328 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
1329
|
|
|
1330 /* Enable the DMA channel */
|
|
|
1331 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
|
|
|
1332
|
|
|
1333 /* Enable the TIM Capture/Compare 1 DMA request */
|
|
|
1334 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
1335 }
|
|
|
1336 break;
|
|
|
1337
|
|
|
1338 case TIM_CHANNEL_2:
|
|
|
1339 {
|
|
|
1340 /* Set the DMA Period elapsed callback */
|
|
|
1341 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
1342
|
|
|
1343 /* Set the DMA error callback */
|
|
|
1344 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
1345
|
|
|
1346 /* Enable the DMA channel */
|
|
|
1347 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
|
|
|
1348
|
|
|
1349 /* Enable the TIM Capture/Compare 2 DMA request */
|
|
|
1350 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
1351 }
|
|
|
1352 break;
|
|
|
1353
|
|
|
1354 case TIM_CHANNEL_3:
|
|
|
1355 {
|
|
|
1356 /* Set the DMA Period elapsed callback */
|
|
|
1357 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
1358
|
|
|
1359 /* Set the DMA error callback */
|
|
|
1360 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
|
|
1361
|
|
|
1362 /* Enable the DMA channel */
|
|
|
1363 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
|
|
|
1364
|
|
|
1365 /* Enable the TIM Output Capture/Compare 3 request */
|
|
|
1366 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
1367 }
|
|
|
1368 break;
|
|
|
1369
|
|
|
1370 case TIM_CHANNEL_4:
|
|
|
1371 {
|
|
|
1372 /* Set the DMA Period elapsed callback */
|
|
|
1373 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
1374
|
|
|
1375 /* Set the DMA error callback */
|
|
|
1376 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
|
|
1377
|
|
|
1378 /* Enable the DMA channel */
|
|
|
1379 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
|
|
|
1380
|
|
|
1381 /* Enable the TIM Capture/Compare 4 DMA request */
|
|
|
1382 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
1383 }
|
|
|
1384 break;
|
|
|
1385
|
|
|
1386 default:
|
|
|
1387 break;
|
|
|
1388 }
|
|
|
1389
|
|
|
1390 /* Enable the Capture compare channel */
|
|
|
1391 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
|
1392
|
|
|
1393 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
1394 {
|
|
|
1395 /* Enable the main output */
|
|
|
1396 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
1397 }
|
|
|
1398
|
|
|
1399 /* Enable the Peripheral */
|
|
|
1400 __HAL_TIM_ENABLE(htim);
|
|
|
1401
|
|
|
1402 /* Return function status */
|
|
|
1403 return HAL_OK;
|
|
|
1404 }
|
|
|
1405
|
|
|
1406 /**
|
|
|
1407 * @brief Stops the TIM PWM signal generation in DMA mode.
|
|
|
1408 * @param htim : TIM handle
|
|
|
1409 * @param Channel : TIM Channels to be disabled
|
|
|
1410 * This parameter can be one of the following values:
|
|
|
1411 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1412 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1413 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1414 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1415 * @retval HAL status
|
|
|
1416 */
|
|
|
1417 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1418 {
|
|
|
1419 /* Check the parameters */
|
|
|
1420 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1421
|
|
|
1422 switch (Channel)
|
|
|
1423 {
|
|
|
1424 case TIM_CHANNEL_1:
|
|
|
1425 {
|
|
|
1426 /* Disable the TIM Capture/Compare 1 DMA request */
|
|
|
1427 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
1428 }
|
|
|
1429 break;
|
|
|
1430
|
|
|
1431 case TIM_CHANNEL_2:
|
|
|
1432 {
|
|
|
1433 /* Disable the TIM Capture/Compare 2 DMA request */
|
|
|
1434 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
1435 }
|
|
|
1436 break;
|
|
|
1437
|
|
|
1438 case TIM_CHANNEL_3:
|
|
|
1439 {
|
|
|
1440 /* Disable the TIM Capture/Compare 3 DMA request */
|
|
|
1441 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
1442 }
|
|
|
1443 break;
|
|
|
1444
|
|
|
1445 case TIM_CHANNEL_4:
|
|
|
1446 {
|
|
|
1447 /* Disable the TIM Capture/Compare 4 interrupt */
|
|
|
1448 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
1449 }
|
|
|
1450 break;
|
|
|
1451
|
|
|
1452 default:
|
|
|
1453 break;
|
|
|
1454 }
|
|
|
1455
|
|
|
1456 /* Disable the Capture compare channel */
|
|
|
1457 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
|
1458
|
|
|
1459 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
1460 {
|
|
|
1461 /* Disable the Main Ouput */
|
|
|
1462 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
1463 }
|
|
|
1464
|
|
|
1465 /* Disable the Peripheral */
|
|
|
1466 __HAL_TIM_DISABLE(htim);
|
|
|
1467
|
|
|
1468 /* Change the htim state */
|
|
|
1469 htim->State = HAL_TIM_STATE_READY;
|
|
|
1470
|
|
|
1471 /* Return function status */
|
|
|
1472 return HAL_OK;
|
|
|
1473 }
|
|
|
1474
|
|
|
1475 /**
|
|
|
1476 * @}
|
|
|
1477 */
|
|
|
1478
|
|
|
1479 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
|
|
|
1480 * @brief Time Input Capture functions
|
|
|
1481 *
|
|
|
1482 @verbatim
|
|
|
1483 ==============================================================================
|
|
|
1484 ##### Time Input Capture functions #####
|
|
|
1485 ==============================================================================
|
|
|
1486 [..]
|
|
|
1487 This section provides functions allowing to:
|
|
|
1488 (+) Initialize and configure the TIM Input Capture.
|
|
|
1489 (+) De-initialize the TIM Input Capture.
|
|
|
1490 (+) Start the Time Input Capture.
|
|
|
1491 (+) Stop the Time Input Capture.
|
|
|
1492 (+) Start the Time Input Capture and enable interrupt.
|
|
|
1493 (+) Stop the Time Input Capture and disable interrupt.
|
|
|
1494 (+) Start the Time Input Capture and enable DMA transfer.
|
|
|
1495 (+) Stop the Time Input Capture and disable DMA transfer.
|
|
|
1496
|
|
|
1497 @endverbatim
|
|
|
1498 * @{
|
|
|
1499 */
|
|
|
1500 /**
|
|
|
1501 * @brief Initializes the TIM Input Capture Time base according to the specified
|
|
|
1502 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
|
|
|
1503 * @param htim: TIM Input Capture handle
|
|
|
1504 * @retval HAL status
|
|
|
1505 */
|
|
|
1506 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
|
|
|
1507 {
|
|
|
1508 /* Check the TIM handle allocation */
|
|
|
1509 if(htim == NULL)
|
|
|
1510 {
|
|
|
1511 return HAL_ERROR;
|
|
|
1512 }
|
|
|
1513
|
|
|
1514 /* Check the parameters */
|
|
|
1515 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
1516 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
|
1517 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
|
1518
|
|
|
1519 if(htim->State == HAL_TIM_STATE_RESET)
|
|
|
1520 {
|
|
|
1521 /* Allocate lock resource and initialize it */
|
|
|
1522 htim->Lock = HAL_UNLOCKED;
|
|
|
1523
|
|
|
1524 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
|
1525 HAL_TIM_IC_MspInit(htim);
|
|
|
1526 }
|
|
|
1527
|
|
|
1528 /* Set the TIM state */
|
|
|
1529 htim->State= HAL_TIM_STATE_BUSY;
|
|
|
1530
|
|
|
1531 /* Init the base time for the input capture */
|
|
|
1532 TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
|
1533
|
|
|
1534 /* Initialize the TIM state*/
|
|
|
1535 htim->State= HAL_TIM_STATE_READY;
|
|
|
1536
|
|
|
1537 return HAL_OK;
|
|
|
1538 }
|
|
|
1539
|
|
|
1540 /**
|
|
|
1541 * @brief DeInitialize the TIM peripheral
|
|
|
1542 * @param htim: TIM Input Capture handle
|
|
|
1543 * @retval HAL status
|
|
|
1544 */
|
|
|
1545 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
|
|
|
1546 {
|
|
|
1547 /* Check the parameters */
|
|
|
1548 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
1549
|
|
|
1550 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
1551
|
|
|
1552 /* Disable the TIM Peripheral Clock */
|
|
|
1553 __HAL_TIM_DISABLE(htim);
|
|
|
1554
|
|
|
1555 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
|
|
|
1556 HAL_TIM_IC_MspDeInit(htim);
|
|
|
1557
|
|
|
1558 /* Change TIM state */
|
|
|
1559 htim->State = HAL_TIM_STATE_RESET;
|
|
|
1560
|
|
|
1561 /* Release Lock */
|
|
|
1562 __HAL_UNLOCK(htim);
|
|
|
1563
|
|
|
1564 return HAL_OK;
|
|
|
1565 }
|
|
|
1566
|
|
|
1567 /**
|
|
|
1568 * @brief Initializes the TIM INput Capture MSP.
|
|
|
1569 * @param htim: TIM handle
|
|
|
1570 * @retval None
|
|
|
1571 */
|
|
|
1572 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
|
|
|
1573 {
|
|
|
1574 /* Prevent unused argument(s) compilation warning */
|
|
|
1575 UNUSED(htim);
|
|
|
1576
|
|
|
1577 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
1578 the HAL_TIM_IC_MspInit could be implemented in the user file
|
|
|
1579 */
|
|
|
1580 }
|
|
|
1581
|
|
|
1582 /**
|
|
|
1583 * @brief DeInitialize TIM Input Capture MSP.
|
|
|
1584 * @param htim: TIM handle
|
|
|
1585 * @retval None
|
|
|
1586 */
|
|
|
1587 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
|
|
|
1588 {
|
|
|
1589 /* Prevent unused argument(s) compilation warning */
|
|
|
1590 UNUSED(htim);
|
|
|
1591
|
|
|
1592 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
1593 the HAL_TIM_IC_MspDeInit could be implemented in the user file
|
|
|
1594 */
|
|
|
1595 }
|
|
|
1596
|
|
|
1597 /**
|
|
|
1598 * @brief Starts the TIM Input Capture measurement.
|
|
|
1599 * @param htim : TIM Input Capture handle
|
|
|
1600 * @param Channel : TIM Channels to be enabled
|
|
|
1601 * This parameter can be one of the following values:
|
|
|
1602 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1603 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1604 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1605 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1606 * @retval HAL status
|
|
|
1607 */
|
|
|
1608 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1609 {
|
|
|
1610 /* Check the parameters */
|
|
|
1611 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1612
|
|
|
1613 /* Enable the Input Capture channel */
|
|
|
1614 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
|
1615
|
|
|
1616 /* Enable the Peripheral */
|
|
|
1617 __HAL_TIM_ENABLE(htim);
|
|
|
1618
|
|
|
1619 /* Return function status */
|
|
|
1620 return HAL_OK;
|
|
|
1621 }
|
|
|
1622
|
|
|
1623 /**
|
|
|
1624 * @brief Stops the TIM Input Capture measurement.
|
|
|
1625 * @param htim : TIM handle
|
|
|
1626 * @param Channel : TIM Channels to be disabled
|
|
|
1627 * This parameter can be one of the following values:
|
|
|
1628 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1629 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1630 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1631 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1632 * @retval HAL status
|
|
|
1633 */
|
|
|
1634 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1635 {
|
|
|
1636 /* Check the parameters */
|
|
|
1637 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1638
|
|
|
1639 /* Disable the Input Capture channel */
|
|
|
1640 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
|
1641
|
|
|
1642 /* Disable the Peripheral */
|
|
|
1643 __HAL_TIM_DISABLE(htim);
|
|
|
1644
|
|
|
1645 /* Return function status */
|
|
|
1646 return HAL_OK;
|
|
|
1647 }
|
|
|
1648
|
|
|
1649 /**
|
|
|
1650 * @brief Starts the TIM Input Capture measurement in interrupt mode.
|
|
|
1651 * @param htim : TIM Input Capture handle
|
|
|
1652 * @param Channel : TIM Channels to be enabled
|
|
|
1653 * This parameter can be one of the following values:
|
|
|
1654 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1655 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1656 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1657 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1658 * @retval HAL status
|
|
|
1659 */
|
|
|
1660 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1661 {
|
|
|
1662 /* Check the parameters */
|
|
|
1663 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1664
|
|
|
1665 switch (Channel)
|
|
|
1666 {
|
|
|
1667 case TIM_CHANNEL_1:
|
|
|
1668 {
|
|
|
1669 /* Enable the TIM Capture/Compare 1 interrupt */
|
|
|
1670 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
1671 }
|
|
|
1672 break;
|
|
|
1673
|
|
|
1674 case TIM_CHANNEL_2:
|
|
|
1675 {
|
|
|
1676 /* Enable the TIM Capture/Compare 2 interrupt */
|
|
|
1677 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
1678 }
|
|
|
1679 break;
|
|
|
1680
|
|
|
1681 case TIM_CHANNEL_3:
|
|
|
1682 {
|
|
|
1683 /* Enable the TIM Capture/Compare 3 interrupt */
|
|
|
1684 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
|
|
1685 }
|
|
|
1686 break;
|
|
|
1687
|
|
|
1688 case TIM_CHANNEL_4:
|
|
|
1689 {
|
|
|
1690 /* Enable the TIM Capture/Compare 4 interrupt */
|
|
|
1691 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
|
|
1692 }
|
|
|
1693 break;
|
|
|
1694
|
|
|
1695 default:
|
|
|
1696 break;
|
|
|
1697 }
|
|
|
1698 /* Enable the Input Capture channel */
|
|
|
1699 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
|
1700
|
|
|
1701 /* Enable the Peripheral */
|
|
|
1702 __HAL_TIM_ENABLE(htim);
|
|
|
1703
|
|
|
1704 /* Return function status */
|
|
|
1705 return HAL_OK;
|
|
|
1706 }
|
|
|
1707
|
|
|
1708 /**
|
|
|
1709 * @brief Stops the TIM Input Capture measurement in interrupt mode.
|
|
|
1710 * @param htim : TIM handle
|
|
|
1711 * @param Channel : TIM Channels to be disabled
|
|
|
1712 * This parameter can be one of the following values:
|
|
|
1713 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1714 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1715 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1716 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1717 * @retval HAL status
|
|
|
1718 */
|
|
|
1719 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1720 {
|
|
|
1721 /* Check the parameters */
|
|
|
1722 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1723
|
|
|
1724 switch (Channel)
|
|
|
1725 {
|
|
|
1726 case TIM_CHANNEL_1:
|
|
|
1727 {
|
|
|
1728 /* Disable the TIM Capture/Compare 1 interrupt */
|
|
|
1729 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
1730 }
|
|
|
1731 break;
|
|
|
1732
|
|
|
1733 case TIM_CHANNEL_2:
|
|
|
1734 {
|
|
|
1735 /* Disable the TIM Capture/Compare 2 interrupt */
|
|
|
1736 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
1737 }
|
|
|
1738 break;
|
|
|
1739
|
|
|
1740 case TIM_CHANNEL_3:
|
|
|
1741 {
|
|
|
1742 /* Disable the TIM Capture/Compare 3 interrupt */
|
|
|
1743 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
|
|
1744 }
|
|
|
1745 break;
|
|
|
1746
|
|
|
1747 case TIM_CHANNEL_4:
|
|
|
1748 {
|
|
|
1749 /* Disable the TIM Capture/Compare 4 interrupt */
|
|
|
1750 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
|
|
1751 }
|
|
|
1752 break;
|
|
|
1753
|
|
|
1754 default:
|
|
|
1755 break;
|
|
|
1756 }
|
|
|
1757
|
|
|
1758 /* Disable the Input Capture channel */
|
|
|
1759 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
|
1760
|
|
|
1761 /* Disable the Peripheral */
|
|
|
1762 __HAL_TIM_DISABLE(htim);
|
|
|
1763
|
|
|
1764 /* Return function status */
|
|
|
1765 return HAL_OK;
|
|
|
1766 }
|
|
|
1767
|
|
|
1768 /**
|
|
|
1769 * @brief Starts the TIM Input Capture measurement on in DMA mode.
|
|
|
1770 * @param htim : TIM Input Capture handle
|
|
|
1771 * @param Channel : TIM Channels to be enabled
|
|
|
1772 * This parameter can be one of the following values:
|
|
|
1773 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1774 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1775 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1776 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1777 * @param pData: The destination Buffer address.
|
|
|
1778 * @param Length: The length of data to be transferred from TIM peripheral to memory.
|
|
|
1779 * @retval HAL status
|
|
|
1780 */
|
|
|
1781 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
|
|
1782 {
|
|
|
1783 /* Check the parameters */
|
|
|
1784 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1785 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
|
|
1786
|
|
|
1787 if((htim->State == HAL_TIM_STATE_BUSY))
|
|
|
1788 {
|
|
|
1789 return HAL_BUSY;
|
|
|
1790 }
|
|
|
1791 else if((htim->State == HAL_TIM_STATE_READY))
|
|
|
1792 {
|
|
|
1793 if((pData == 0 ) && (Length > 0))
|
|
|
1794 {
|
|
|
1795 return HAL_ERROR;
|
|
|
1796 }
|
|
|
1797 else
|
|
|
1798 {
|
|
|
1799 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
1800 }
|
|
|
1801 }
|
|
|
1802
|
|
|
1803 switch (Channel)
|
|
|
1804 {
|
|
|
1805 case TIM_CHANNEL_1:
|
|
|
1806 {
|
|
|
1807 /* Set the DMA Period elapsed callback */
|
|
|
1808 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
1809
|
|
|
1810 /* Set the DMA error callback */
|
|
|
1811 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
1812
|
|
|
1813 /* Enable the DMA channel */
|
|
|
1814 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
|
|
|
1815
|
|
|
1816 /* Enable the TIM Capture/Compare 1 DMA request */
|
|
|
1817 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
1818 }
|
|
|
1819 break;
|
|
|
1820
|
|
|
1821 case TIM_CHANNEL_2:
|
|
|
1822 {
|
|
|
1823 /* Set the DMA Period elapsed callback */
|
|
|
1824 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
1825
|
|
|
1826 /* Set the DMA error callback */
|
|
|
1827 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
1828
|
|
|
1829 /* Enable the DMA channel */
|
|
|
1830 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
|
|
|
1831
|
|
|
1832 /* Enable the TIM Capture/Compare 2 DMA request */
|
|
|
1833 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
1834 }
|
|
|
1835 break;
|
|
|
1836
|
|
|
1837 case TIM_CHANNEL_3:
|
|
|
1838 {
|
|
|
1839 /* Set the DMA Period elapsed callback */
|
|
|
1840 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
1841
|
|
|
1842 /* Set the DMA error callback */
|
|
|
1843 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
|
|
1844
|
|
|
1845 /* Enable the DMA channel */
|
|
|
1846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
|
|
|
1847
|
|
|
1848 /* Enable the TIM Capture/Compare 3 DMA request */
|
|
|
1849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
1850 }
|
|
|
1851 break;
|
|
|
1852
|
|
|
1853 case TIM_CHANNEL_4:
|
|
|
1854 {
|
|
|
1855 /* Set the DMA Period elapsed callback */
|
|
|
1856 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
1857
|
|
|
1858 /* Set the DMA error callback */
|
|
|
1859 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
|
|
1860
|
|
|
1861 /* Enable the DMA channel */
|
|
|
1862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
|
|
|
1863
|
|
|
1864 /* Enable the TIM Capture/Compare 4 DMA request */
|
|
|
1865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
1866 }
|
|
|
1867 break;
|
|
|
1868
|
|
|
1869 default:
|
|
|
1870 break;
|
|
|
1871 }
|
|
|
1872
|
|
|
1873 /* Enable the Input Capture channel */
|
|
|
1874 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
|
1875
|
|
|
1876 /* Enable the Peripheral */
|
|
|
1877 __HAL_TIM_ENABLE(htim);
|
|
|
1878
|
|
|
1879 /* Return function status */
|
|
|
1880 return HAL_OK;
|
|
|
1881 }
|
|
|
1882
|
|
|
1883 /**
|
|
|
1884 * @brief Stops the TIM Input Capture measurement on in DMA mode.
|
|
|
1885 * @param htim : TIM Input Capture handle
|
|
|
1886 * @param Channel : TIM Channels to be disabled
|
|
|
1887 * This parameter can be one of the following values:
|
|
|
1888 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1889 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1890 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1891 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1892 * @retval HAL status
|
|
|
1893 */
|
|
|
1894 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1895 {
|
|
|
1896 /* Check the parameters */
|
|
|
1897 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
1898 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
|
|
1899
|
|
|
1900 switch (Channel)
|
|
|
1901 {
|
|
|
1902 case TIM_CHANNEL_1:
|
|
|
1903 {
|
|
|
1904 /* Disable the TIM Capture/Compare 1 DMA request */
|
|
|
1905 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
1906 }
|
|
|
1907 break;
|
|
|
1908
|
|
|
1909 case TIM_CHANNEL_2:
|
|
|
1910 {
|
|
|
1911 /* Disable the TIM Capture/Compare 2 DMA request */
|
|
|
1912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
1913 }
|
|
|
1914 break;
|
|
|
1915
|
|
|
1916 case TIM_CHANNEL_3:
|
|
|
1917 {
|
|
|
1918 /* Disable the TIM Capture/Compare 3 DMA request */
|
|
|
1919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
1920 }
|
|
|
1921 break;
|
|
|
1922
|
|
|
1923 case TIM_CHANNEL_4:
|
|
|
1924 {
|
|
|
1925 /* Disable the TIM Capture/Compare 4 DMA request */
|
|
|
1926 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
1927 }
|
|
|
1928 break;
|
|
|
1929
|
|
|
1930 default:
|
|
|
1931 break;
|
|
|
1932 }
|
|
|
1933
|
|
|
1934 /* Disable the Input Capture channel */
|
|
|
1935 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
|
|
1936
|
|
|
1937 /* Disable the Peripheral */
|
|
|
1938 __HAL_TIM_DISABLE(htim);
|
|
|
1939
|
|
|
1940 /* Change the htim state */
|
|
|
1941 htim->State = HAL_TIM_STATE_READY;
|
|
|
1942
|
|
|
1943 /* Return function status */
|
|
|
1944 return HAL_OK;
|
|
|
1945 }
|
|
|
1946 /**
|
|
|
1947 * @}
|
|
|
1948 */
|
|
|
1949
|
|
|
1950 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
|
|
|
1951 * @brief Time One Pulse functions
|
|
|
1952 *
|
|
|
1953 @verbatim
|
|
|
1954 ==============================================================================
|
|
|
1955 ##### Time One Pulse functions #####
|
|
|
1956 ==============================================================================
|
|
|
1957 [..]
|
|
|
1958 This section provides functions allowing to:
|
|
|
1959 (+) Initialize and configure the TIM One Pulse.
|
|
|
1960 (+) De-initialize the TIM One Pulse.
|
|
|
1961 (+) Start the Time One Pulse.
|
|
|
1962 (+) Stop the Time One Pulse.
|
|
|
1963 (+) Start the Time One Pulse and enable interrupt.
|
|
|
1964 (+) Stop the Time One Pulse and disable interrupt.
|
|
|
1965 (+) Start the Time One Pulse and enable DMA transfer.
|
|
|
1966 (+) Stop the Time One Pulse and disable DMA transfer.
|
|
|
1967
|
|
|
1968 @endverbatim
|
|
|
1969 * @{
|
|
|
1970 */
|
|
|
1971 /**
|
|
|
1972 * @brief Initializes the TIM One Pulse Time Base according to the specified
|
|
|
1973 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
|
|
|
1974 * @param htim: TIM OnePulse handle
|
|
|
1975 * @param OnePulseMode: Select the One pulse mode.
|
|
|
1976 * This parameter can be one of the following values:
|
|
|
1977 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
|
|
|
1978 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
|
|
|
1979 * @retval HAL status
|
|
|
1980 */
|
|
|
1981 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
|
|
|
1982 {
|
|
|
1983 /* Check the TIM handle allocation */
|
|
|
1984 if(htim == NULL)
|
|
|
1985 {
|
|
|
1986 return HAL_ERROR;
|
|
|
1987 }
|
|
|
1988
|
|
|
1989 /* Check the parameters */
|
|
|
1990 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
1991 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
|
1992 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
|
1993 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
|
|
|
1994
|
|
|
1995 if(htim->State == HAL_TIM_STATE_RESET)
|
|
|
1996 {
|
|
|
1997 /* Allocate lock resource and initialize it */
|
|
|
1998 htim->Lock = HAL_UNLOCKED;
|
|
|
1999
|
|
|
2000 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
|
2001 HAL_TIM_OnePulse_MspInit(htim);
|
|
|
2002 }
|
|
|
2003
|
|
|
2004 /* Set the TIM state */
|
|
|
2005 htim->State= HAL_TIM_STATE_BUSY;
|
|
|
2006
|
|
|
2007 /* Configure the Time base in the One Pulse Mode */
|
|
|
2008 TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
|
2009
|
|
|
2010 /* Reset the OPM Bit */
|
|
|
2011 htim->Instance->CR1 &= ~TIM_CR1_OPM;
|
|
|
2012
|
|
|
2013 /* Configure the OPM Mode */
|
|
|
2014 htim->Instance->CR1 |= OnePulseMode;
|
|
|
2015
|
|
|
2016 /* Initialize the TIM state*/
|
|
|
2017 htim->State= HAL_TIM_STATE_READY;
|
|
|
2018
|
|
|
2019 return HAL_OK;
|
|
|
2020 }
|
|
|
2021
|
|
|
2022 /**
|
|
|
2023 * @brief DeInitialize the TIM One Pulse
|
|
|
2024 * @param htim: TIM One Pulse handle
|
|
|
2025 * @retval HAL status
|
|
|
2026 */
|
|
|
2027 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
|
|
|
2028 {
|
|
|
2029 /* Check the parameters */
|
|
|
2030 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
2031
|
|
|
2032 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
2033
|
|
|
2034 /* Disable the TIM Peripheral Clock */
|
|
|
2035 __HAL_TIM_DISABLE(htim);
|
|
|
2036
|
|
|
2037 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
|
|
2038 HAL_TIM_OnePulse_MspDeInit(htim);
|
|
|
2039
|
|
|
2040 /* Change TIM state */
|
|
|
2041 htim->State = HAL_TIM_STATE_RESET;
|
|
|
2042
|
|
|
2043 /* Release Lock */
|
|
|
2044 __HAL_UNLOCK(htim);
|
|
|
2045
|
|
|
2046 return HAL_OK;
|
|
|
2047 }
|
|
|
2048
|
|
|
2049 /**
|
|
|
2050 * @brief Initializes the TIM One Pulse MSP.
|
|
|
2051 * @param htim: TIM handle
|
|
|
2052 * @retval None
|
|
|
2053 */
|
|
|
2054 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
|
|
|
2055 {
|
|
|
2056 /* Prevent unused argument(s) compilation warning */
|
|
|
2057 UNUSED(htim);
|
|
|
2058
|
|
|
2059 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
2060 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
|
|
|
2061 */
|
|
|
2062 }
|
|
|
2063
|
|
|
2064 /**
|
|
|
2065 * @brief DeInitialize TIM One Pulse MSP.
|
|
|
2066 * @param htim: TIM handle
|
|
|
2067 * @retval None
|
|
|
2068 */
|
|
|
2069 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
|
|
|
2070 {
|
|
|
2071 /* Prevent unused argument(s) compilation warning */
|
|
|
2072 UNUSED(htim);
|
|
|
2073
|
|
|
2074 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
2075 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
|
|
|
2076 */
|
|
|
2077 }
|
|
|
2078
|
|
|
2079 /**
|
|
|
2080 * @brief Starts the TIM One Pulse signal generation.
|
|
|
2081 * @param htim : TIM One Pulse handle
|
|
|
2082 * @param OutputChannel : TIM Channels to be enabled
|
|
|
2083 * This parameter can be one of the following values:
|
|
|
2084 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2085 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2086 * @retval HAL status
|
|
|
2087 */
|
|
|
2088 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
|
2089 {
|
|
|
2090 /* Prevent unused argument(s) compilation warning */
|
|
|
2091 UNUSED(OutputChannel);
|
|
|
2092
|
|
|
2093 /* Enable the Capture compare and the Input Capture channels
|
|
|
2094 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
|
|
2095 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
|
|
2096 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
|
|
2097 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
|
|
|
2098
|
|
|
2099 No need to enable the counter, it's enabled automatically by hardware
|
|
|
2100 (the counter starts in response to a stimulus and generate a pulse */
|
|
|
2101
|
|
|
2102 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
2103 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
|
2104
|
|
|
2105 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
2106 {
|
|
|
2107 /* Enable the main output */
|
|
|
2108 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
2109 }
|
|
|
2110
|
|
|
2111 /* Return function status */
|
|
|
2112 return HAL_OK;
|
|
|
2113 }
|
|
|
2114
|
|
|
2115 /**
|
|
|
2116 * @brief Stops the TIM One Pulse signal generation.
|
|
|
2117 * @param htim : TIM One Pulse handle
|
|
|
2118 * @param OutputChannel : TIM Channels to be disable
|
|
|
2119 * This parameter can be one of the following values:
|
|
|
2120 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2121 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2122 * @retval HAL status
|
|
|
2123 */
|
|
|
2124 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
|
2125 {
|
|
|
2126 /* Prevent unused argument(s) compilation warning */
|
|
|
2127 UNUSED(OutputChannel);
|
|
|
2128
|
|
|
2129 /* Disable the Capture compare and the Input Capture channels
|
|
|
2130 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
|
|
2131 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
|
|
2132 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
|
|
2133 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
|
|
|
2134
|
|
|
2135 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
2136 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
|
|
2137
|
|
|
2138 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
2139 {
|
|
|
2140 /* Disable the Main Ouput */
|
|
|
2141 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
2142 }
|
|
|
2143
|
|
|
2144 /* Disable the Peripheral */
|
|
|
2145 __HAL_TIM_DISABLE(htim);
|
|
|
2146
|
|
|
2147 /* Return function status */
|
|
|
2148 return HAL_OK;
|
|
|
2149 }
|
|
|
2150
|
|
|
2151 /**
|
|
|
2152 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
|
|
|
2153 * @param htim : TIM One Pulse handle
|
|
|
2154 * @param OutputChannel : TIM Channels to be enabled
|
|
|
2155 * This parameter can be one of the following values:
|
|
|
2156 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2157 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2158 * @retval HAL status
|
|
|
2159 */
|
|
|
2160 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
|
2161 {
|
|
|
2162 /* Prevent unused argument(s) compilation warning */
|
|
|
2163 UNUSED(OutputChannel);
|
|
|
2164
|
|
|
2165 /* Enable the Capture compare and the Input Capture channels
|
|
|
2166 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
|
|
2167 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
|
|
2168 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
|
|
2169 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
|
|
|
2170
|
|
|
2171 No need to enable the counter, it's enabled automatically by hardware
|
|
|
2172 (the counter starts in response to a stimulus and generate a pulse */
|
|
|
2173
|
|
|
2174 /* Enable the TIM Capture/Compare 1 interrupt */
|
|
|
2175 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
2176
|
|
|
2177 /* Enable the TIM Capture/Compare 2 interrupt */
|
|
|
2178 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
2179
|
|
|
2180 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
2181 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
|
2182
|
|
|
2183 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
2184 {
|
|
|
2185 /* Enable the main output */
|
|
|
2186 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
2187 }
|
|
|
2188
|
|
|
2189 /* Return function status */
|
|
|
2190 return HAL_OK;
|
|
|
2191 }
|
|
|
2192
|
|
|
2193 /**
|
|
|
2194 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
|
|
|
2195 * @param htim : TIM One Pulse handle
|
|
|
2196 * @param OutputChannel : TIM Channels to be enabled
|
|
|
2197 * This parameter can be one of the following values:
|
|
|
2198 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2199 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2200 * @retval HAL status
|
|
|
2201 */
|
|
|
2202 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
|
2203 {
|
|
|
2204 /* Prevent unused argument(s) compilation warning */
|
|
|
2205 UNUSED(OutputChannel);
|
|
|
2206
|
|
|
2207 /* Disable the TIM Capture/Compare 1 interrupt */
|
|
|
2208 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
2209
|
|
|
2210 /* Disable the TIM Capture/Compare 2 interrupt */
|
|
|
2211 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
2212
|
|
|
2213 /* Disable the Capture compare and the Input Capture channels
|
|
|
2214 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
|
|
|
2215 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
|
|
|
2216 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
|
|
|
2217 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
|
|
|
2218 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
2219 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
|
|
2220
|
|
|
2221 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
|
2222 {
|
|
|
2223 /* Disable the Main Ouput */
|
|
|
2224 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
2225 }
|
|
|
2226
|
|
|
2227 /* Disable the Peripheral */
|
|
|
2228 __HAL_TIM_DISABLE(htim);
|
|
|
2229
|
|
|
2230 /* Return function status */
|
|
|
2231 return HAL_OK;
|
|
|
2232 }
|
|
|
2233
|
|
|
2234 /**
|
|
|
2235 * @}
|
|
|
2236 */
|
|
|
2237
|
|
|
2238 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
|
|
|
2239 * @brief Time Encoder functions
|
|
|
2240 *
|
|
|
2241 @verbatim
|
|
|
2242 ==============================================================================
|
|
|
2243 ##### Time Encoder functions #####
|
|
|
2244 ==============================================================================
|
|
|
2245 [..]
|
|
|
2246 This section provides functions allowing to:
|
|
|
2247 (+) Initialize and configure the TIM Encoder.
|
|
|
2248 (+) De-initialize the TIM Encoder.
|
|
|
2249 (+) Start the Time Encoder.
|
|
|
2250 (+) Stop the Time Encoder.
|
|
|
2251 (+) Start the Time Encoder and enable interrupt.
|
|
|
2252 (+) Stop the Time Encoder and disable interrupt.
|
|
|
2253 (+) Start the Time Encoder and enable DMA transfer.
|
|
|
2254 (+) Stop the Time Encoder and disable DMA transfer.
|
|
|
2255
|
|
|
2256 @endverbatim
|
|
|
2257 * @{
|
|
|
2258 */
|
|
|
2259 /**
|
|
|
2260 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
|
|
|
2261 * @param htim: TIM Encoder Interface handle
|
|
|
2262 * @param sConfig: TIM Encoder Interface configuration structure
|
|
|
2263 * @retval HAL status
|
|
|
2264 */
|
|
|
2265 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
|
|
|
2266 {
|
|
|
2267 uint32_t tmpsmcr = 0;
|
|
|
2268 uint32_t tmpccmr1 = 0;
|
|
|
2269 uint32_t tmpccer = 0;
|
|
|
2270
|
|
|
2271 /* Check the TIM handle allocation */
|
|
|
2272 if(htim == NULL)
|
|
|
2273 {
|
|
|
2274 return HAL_ERROR;
|
|
|
2275 }
|
|
|
2276
|
|
|
2277 /* Check the parameters */
|
|
|
2278 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
2279 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
|
|
|
2280 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
|
|
|
2281 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
|
|
|
2282 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
|
|
|
2283 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
|
|
|
2284 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
|
|
|
2285 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
|
|
|
2286 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
|
|
|
2287 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
|
|
|
2288
|
|
|
2289 if(htim->State == HAL_TIM_STATE_RESET)
|
|
|
2290 {
|
|
|
2291 /* Allocate lock resource and initialize it */
|
|
|
2292 htim->Lock = HAL_UNLOCKED;
|
|
|
2293
|
|
|
2294 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
|
2295 HAL_TIM_Encoder_MspInit(htim);
|
|
|
2296 }
|
|
|
2297
|
|
|
2298 /* Set the TIM state */
|
|
|
2299 htim->State= HAL_TIM_STATE_BUSY;
|
|
|
2300
|
|
|
2301 /* Reset the SMS bits */
|
|
|
2302 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
|
|
|
2303
|
|
|
2304 /* Configure the Time base in the Encoder Mode */
|
|
|
2305 TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
|
2306
|
|
|
2307 /* Get the TIMx SMCR register value */
|
|
|
2308 tmpsmcr = htim->Instance->SMCR;
|
|
|
2309
|
|
|
2310 /* Get the TIMx CCMR1 register value */
|
|
|
2311 tmpccmr1 = htim->Instance->CCMR1;
|
|
|
2312
|
|
|
2313 /* Get the TIMx CCER register value */
|
|
|
2314 tmpccer = htim->Instance->CCER;
|
|
|
2315
|
|
|
2316 /* Set the encoder Mode */
|
|
|
2317 tmpsmcr |= sConfig->EncoderMode;
|
|
|
2318
|
|
|
2319 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
|
|
2320 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
|
|
2321 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
|
|
|
2322
|
|
|
2323 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
|
|
|
2324 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
|
|
|
2325 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
|
|
2326 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
|
|
|
2327 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
|
|
|
2328
|
|
|
2329 /* Set the TI1 and the TI2 Polarities */
|
|
|
2330 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
|
|
|
2331 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
|
|
|
2332 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
|
|
|
2333
|
|
|
2334 /* Write to TIMx SMCR */
|
|
|
2335 htim->Instance->SMCR = tmpsmcr;
|
|
|
2336
|
|
|
2337 /* Write to TIMx CCMR1 */
|
|
|
2338 htim->Instance->CCMR1 = tmpccmr1;
|
|
|
2339
|
|
|
2340 /* Write to TIMx CCER */
|
|
|
2341 htim->Instance->CCER = tmpccer;
|
|
|
2342
|
|
|
2343 /* Initialize the TIM state*/
|
|
|
2344 htim->State= HAL_TIM_STATE_READY;
|
|
|
2345
|
|
|
2346 return HAL_OK;
|
|
|
2347 }
|
|
|
2348
|
|
|
2349
|
|
|
2350 /**
|
|
|
2351 * @brief DeInitialize the TIM Encoder interface
|
|
|
2352 * @param htim: TIM Encoder handle
|
|
|
2353 * @retval HAL status
|
|
|
2354 */
|
|
|
2355 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
|
|
|
2356 {
|
|
|
2357 /* Check the parameters */
|
|
|
2358 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
2359
|
|
|
2360 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
2361
|
|
|
2362 /* Disable the TIM Peripheral Clock */
|
|
|
2363 __HAL_TIM_DISABLE(htim);
|
|
|
2364
|
|
|
2365 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
|
|
2366 HAL_TIM_Encoder_MspDeInit(htim);
|
|
|
2367
|
|
|
2368 /* Change TIM state */
|
|
|
2369 htim->State = HAL_TIM_STATE_RESET;
|
|
|
2370
|
|
|
2371 /* Release Lock */
|
|
|
2372 __HAL_UNLOCK(htim);
|
|
|
2373
|
|
|
2374 return HAL_OK;
|
|
|
2375 }
|
|
|
2376
|
|
|
2377 /**
|
|
|
2378 * @brief Initializes the TIM Encoder Interface MSP.
|
|
|
2379 * @param htim: TIM handle
|
|
|
2380 * @retval None
|
|
|
2381 */
|
|
|
2382 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
|
|
|
2383 {
|
|
|
2384 /* Prevent unused argument(s) compilation warning */
|
|
|
2385 UNUSED(htim);
|
|
|
2386
|
|
|
2387 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
2388 the HAL_TIM_Encoder_MspInit could be implemented in the user file
|
|
|
2389 */
|
|
|
2390 }
|
|
|
2391
|
|
|
2392 /**
|
|
|
2393 * @brief DeInitialize TIM Encoder Interface MSP.
|
|
|
2394 * @param htim: TIM handle
|
|
|
2395 * @retval None
|
|
|
2396 */
|
|
|
2397 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
|
|
|
2398 {
|
|
|
2399 /* Prevent unused argument(s) compilation warning */
|
|
|
2400 UNUSED(htim);
|
|
|
2401
|
|
|
2402 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
2403 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
|
|
|
2404 */
|
|
|
2405 }
|
|
|
2406
|
|
|
2407 /**
|
|
|
2408 * @brief Starts the TIM Encoder Interface.
|
|
|
2409 * @param htim : TIM Encoder Interface handle
|
|
|
2410 * @param Channel : TIM Channels to be enabled
|
|
|
2411 * This parameter can be one of the following values:
|
|
|
2412 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2413 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2414 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
|
|
2415 * @retval HAL status
|
|
|
2416 */
|
|
|
2417 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
2418 {
|
|
|
2419 /* Check the parameters */
|
|
|
2420 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
2421
|
|
|
2422 /* Enable the encoder interface channels */
|
|
|
2423 switch (Channel)
|
|
|
2424 {
|
|
|
2425 case TIM_CHANNEL_1:
|
|
|
2426 {
|
|
|
2427 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
2428 }
|
|
|
2429 break;
|
|
|
2430
|
|
|
2431 case TIM_CHANNEL_2:
|
|
|
2432 {
|
|
|
2433 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
|
2434 }
|
|
|
2435 break;
|
|
|
2436
|
|
|
2437 default :
|
|
|
2438 {
|
|
|
2439 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
2440 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
|
2441 }
|
|
|
2442 break;
|
|
|
2443 }
|
|
|
2444 /* Enable the Peripheral */
|
|
|
2445 __HAL_TIM_ENABLE(htim);
|
|
|
2446
|
|
|
2447 /* Return function status */
|
|
|
2448 return HAL_OK;
|
|
|
2449 }
|
|
|
2450
|
|
|
2451 /**
|
|
|
2452 * @brief Stops the TIM Encoder Interface.
|
|
|
2453 * @param htim : TIM Encoder Interface handle
|
|
|
2454 * @param Channel : TIM Channels to be disabled
|
|
|
2455 * This parameter can be one of the following values:
|
|
|
2456 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2457 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2458 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
|
|
2459 * @retval HAL status
|
|
|
2460 */
|
|
|
2461 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
2462 {
|
|
|
2463 /* Check the parameters */
|
|
|
2464 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
2465
|
|
|
2466 /* Disable the Input Capture channels 1 and 2
|
|
|
2467 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
|
|
|
2468 switch (Channel)
|
|
|
2469 {
|
|
|
2470 case TIM_CHANNEL_1:
|
|
|
2471 {
|
|
|
2472 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
2473 }
|
|
|
2474 break;
|
|
|
2475
|
|
|
2476 case TIM_CHANNEL_2:
|
|
|
2477 {
|
|
|
2478 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
|
|
2479 }
|
|
|
2480 break;
|
|
|
2481
|
|
|
2482 default :
|
|
|
2483 {
|
|
|
2484 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
2485 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
|
|
2486 }
|
|
|
2487 break;
|
|
|
2488 }
|
|
|
2489
|
|
|
2490 /* Disable the Peripheral */
|
|
|
2491 __HAL_TIM_DISABLE(htim);
|
|
|
2492
|
|
|
2493 /* Return function status */
|
|
|
2494 return HAL_OK;
|
|
|
2495 }
|
|
|
2496
|
|
|
2497 /**
|
|
|
2498 * @brief Starts the TIM Encoder Interface in interrupt mode.
|
|
|
2499 * @param htim : TIM Encoder Interface handle
|
|
|
2500 * @param Channel : TIM Channels to be enabled
|
|
|
2501 * This parameter can be one of the following values:
|
|
|
2502 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2503 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2504 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
|
|
2505 * @retval HAL status
|
|
|
2506 */
|
|
|
2507 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
2508 {
|
|
|
2509 /* Check the parameters */
|
|
|
2510 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
2511
|
|
|
2512 /* Enable the encoder interface channels */
|
|
|
2513 /* Enable the capture compare Interrupts 1 and/or 2 */
|
|
|
2514 switch (Channel)
|
|
|
2515 {
|
|
|
2516 case TIM_CHANNEL_1:
|
|
|
2517 {
|
|
|
2518 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
2519 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
2520 }
|
|
|
2521 break;
|
|
|
2522
|
|
|
2523 case TIM_CHANNEL_2:
|
|
|
2524 {
|
|
|
2525 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
|
2526 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
2527 }
|
|
|
2528 break;
|
|
|
2529
|
|
|
2530 default :
|
|
|
2531 {
|
|
|
2532 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
2533 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
|
2534 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
2535 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
2536 }
|
|
|
2537 break;
|
|
|
2538 }
|
|
|
2539
|
|
|
2540 /* Enable the Peripheral */
|
|
|
2541 __HAL_TIM_ENABLE(htim);
|
|
|
2542
|
|
|
2543 /* Return function status */
|
|
|
2544 return HAL_OK;
|
|
|
2545 }
|
|
|
2546
|
|
|
2547 /**
|
|
|
2548 * @brief Stops the TIM Encoder Interface in interrupt mode.
|
|
|
2549 * @param htim : TIM Encoder Interface handle
|
|
|
2550 * @param Channel : TIM Channels to be disabled
|
|
|
2551 * This parameter can be one of the following values:
|
|
|
2552 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2553 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2554 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
|
|
2555 * @retval HAL status
|
|
|
2556 */
|
|
|
2557 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
2558 {
|
|
|
2559 /* Check the parameters */
|
|
|
2560 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
2561
|
|
|
2562 /* Disable the Input Capture channels 1 and 2
|
|
|
2563 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
|
|
|
2564 if(Channel == TIM_CHANNEL_1)
|
|
|
2565 {
|
|
|
2566 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
2567
|
|
|
2568 /* Disable the capture compare Interrupts 1 */
|
|
|
2569 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
2570 }
|
|
|
2571 else if(Channel == TIM_CHANNEL_2)
|
|
|
2572 {
|
|
|
2573 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
|
|
2574
|
|
|
2575 /* Disable the capture compare Interrupts 2 */
|
|
|
2576 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
2577 }
|
|
|
2578 else
|
|
|
2579 {
|
|
|
2580 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
2581 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
|
|
2582
|
|
|
2583 /* Disable the capture compare Interrupts 1 and 2 */
|
|
|
2584 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
2585 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
2586 }
|
|
|
2587
|
|
|
2588 /* Disable the Peripheral */
|
|
|
2589 __HAL_TIM_DISABLE(htim);
|
|
|
2590
|
|
|
2591 /* Change the htim state */
|
|
|
2592 htim->State = HAL_TIM_STATE_READY;
|
|
|
2593
|
|
|
2594 /* Return function status */
|
|
|
2595 return HAL_OK;
|
|
|
2596 }
|
|
|
2597
|
|
|
2598 /**
|
|
|
2599 * @brief Starts the TIM Encoder Interface in DMA mode.
|
|
|
2600 * @param htim : TIM Encoder Interface handle
|
|
|
2601 * @param Channel : TIM Channels to be enabled
|
|
|
2602 * This parameter can be one of the following values:
|
|
|
2603 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2604 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2605 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
|
|
2606 * @param pData1: The destination Buffer address for IC1.
|
|
|
2607 * @param pData2: The destination Buffer address for IC2.
|
|
|
2608 * @param Length: The length of data to be transferred from TIM peripheral to memory.
|
|
|
2609 * @retval HAL status
|
|
|
2610 */
|
|
|
2611 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
|
|
|
2612 {
|
|
|
2613 /* Check the parameters */
|
|
|
2614 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
|
|
2615
|
|
|
2616 if((htim->State == HAL_TIM_STATE_BUSY))
|
|
|
2617 {
|
|
|
2618 return HAL_BUSY;
|
|
|
2619 }
|
|
|
2620 else if((htim->State == HAL_TIM_STATE_READY))
|
|
|
2621 {
|
|
|
2622 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
|
|
|
2623 {
|
|
|
2624 return HAL_ERROR;
|
|
|
2625 }
|
|
|
2626 else
|
|
|
2627 {
|
|
|
2628 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
2629 }
|
|
|
2630 }
|
|
|
2631
|
|
|
2632 switch (Channel)
|
|
|
2633 {
|
|
|
2634 case TIM_CHANNEL_1:
|
|
|
2635 {
|
|
|
2636 /* Set the DMA Period elapsed callback */
|
|
|
2637 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
2638
|
|
|
2639 /* Set the DMA error callback */
|
|
|
2640 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
2641
|
|
|
2642 /* Enable the DMA channel */
|
|
|
2643 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
|
|
|
2644
|
|
|
2645 /* Enable the TIM Input Capture DMA request */
|
|
|
2646 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
2647
|
|
|
2648 /* Enable the Peripheral */
|
|
|
2649 __HAL_TIM_ENABLE(htim);
|
|
|
2650
|
|
|
2651 /* Enable the Capture compare channel */
|
|
|
2652 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
2653 }
|
|
|
2654 break;
|
|
|
2655
|
|
|
2656 case TIM_CHANNEL_2:
|
|
|
2657 {
|
|
|
2658 /* Set the DMA Period elapsed callback */
|
|
|
2659 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
2660
|
|
|
2661 /* Set the DMA error callback */
|
|
|
2662 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
|
|
|
2663 /* Enable the DMA channel */
|
|
|
2664 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
|
|
|
2665
|
|
|
2666 /* Enable the TIM Input Capture DMA request */
|
|
|
2667 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
2668
|
|
|
2669 /* Enable the Peripheral */
|
|
|
2670 __HAL_TIM_ENABLE(htim);
|
|
|
2671
|
|
|
2672 /* Enable the Capture compare channel */
|
|
|
2673 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
|
2674 }
|
|
|
2675 break;
|
|
|
2676
|
|
|
2677 case TIM_CHANNEL_ALL:
|
|
|
2678 {
|
|
|
2679 /* Set the DMA Period elapsed callback */
|
|
|
2680 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
2681
|
|
|
2682 /* Set the DMA error callback */
|
|
|
2683 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
2684
|
|
|
2685 /* Enable the DMA channel */
|
|
|
2686 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
|
|
|
2687
|
|
|
2688 /* Set the DMA Period elapsed callback */
|
|
|
2689 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
2690
|
|
|
2691 /* Set the DMA error callback */
|
|
|
2692 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
2693
|
|
|
2694 /* Enable the DMA channel */
|
|
|
2695 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
|
|
|
2696
|
|
|
2697 /* Enable the Peripheral */
|
|
|
2698 __HAL_TIM_ENABLE(htim);
|
|
|
2699
|
|
|
2700 /* Enable the Capture compare channel */
|
|
|
2701 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
2702 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
|
2703
|
|
|
2704 /* Enable the TIM Input Capture DMA request */
|
|
|
2705 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
2706 /* Enable the TIM Input Capture DMA request */
|
|
|
2707 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
2708 }
|
|
|
2709 break;
|
|
|
2710
|
|
|
2711 default:
|
|
|
2712 break;
|
|
|
2713 }
|
|
|
2714 /* Return function status */
|
|
|
2715 return HAL_OK;
|
|
|
2716 }
|
|
|
2717
|
|
|
2718 /**
|
|
|
2719 * @brief Stops the TIM Encoder Interface in DMA mode.
|
|
|
2720 * @param htim : TIM Encoder Interface handle
|
|
|
2721 * @param Channel : TIM Channels to be enabled
|
|
|
2722 * This parameter can be one of the following values:
|
|
|
2723 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2724 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2725 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
|
|
2726 * @retval HAL status
|
|
|
2727 */
|
|
|
2728 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
2729 {
|
|
|
2730 /* Check the parameters */
|
|
|
2731 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
|
|
2732
|
|
|
2733 /* Disable the Input Capture channels 1 and 2
|
|
|
2734 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
|
|
|
2735 if(Channel == TIM_CHANNEL_1)
|
|
|
2736 {
|
|
|
2737 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
2738
|
|
|
2739 /* Disable the capture compare DMA Request 1 */
|
|
|
2740 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
2741 }
|
|
|
2742 else if(Channel == TIM_CHANNEL_2)
|
|
|
2743 {
|
|
|
2744 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
|
|
2745
|
|
|
2746 /* Disable the capture compare DMA Request 2 */
|
|
|
2747 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
2748 }
|
|
|
2749 else
|
|
|
2750 {
|
|
|
2751 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
2752 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
|
|
|
2753
|
|
|
2754 /* Disable the capture compare DMA Request 1 and 2 */
|
|
|
2755 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
2756 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
2757 }
|
|
|
2758
|
|
|
2759 /* Disable the Peripheral */
|
|
|
2760 __HAL_TIM_DISABLE(htim);
|
|
|
2761
|
|
|
2762 /* Change the htim state */
|
|
|
2763 htim->State = HAL_TIM_STATE_READY;
|
|
|
2764
|
|
|
2765 /* Return function status */
|
|
|
2766 return HAL_OK;
|
|
|
2767 }
|
|
|
2768
|
|
|
2769 /**
|
|
|
2770 * @}
|
|
|
2771 */
|
|
|
2772 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
|
|
|
2773 * @brief IRQ handler management
|
|
|
2774 *
|
|
|
2775 @verbatim
|
|
|
2776 ==============================================================================
|
|
|
2777 ##### IRQ handler management #####
|
|
|
2778 ==============================================================================
|
|
|
2779 [..]
|
|
|
2780 This section provides Timer IRQ handler function.
|
|
|
2781
|
|
|
2782 @endverbatim
|
|
|
2783 * @{
|
|
|
2784 */
|
|
|
2785 /**
|
|
|
2786 * @brief This function handles TIM interrupts requests.
|
|
|
2787 * @param htim: TIM handle
|
|
|
2788 * @retval None
|
|
|
2789 */
|
|
|
2790 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
|
2791 {
|
|
|
2792 /* Capture compare 1 event */
|
|
|
2793 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
|
|
|
2794 {
|
|
|
2795 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
|
|
|
2796 {
|
|
|
2797 {
|
|
|
2798 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
|
|
|
2799 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
|
2800
|
|
|
2801 /* Input capture event */
|
|
|
2802 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
|
|
|
2803 {
|
|
|
2804 HAL_TIM_IC_CaptureCallback(htim);
|
|
|
2805 }
|
|
|
2806 /* Output compare event */
|
|
|
2807 else
|
|
|
2808 {
|
|
|
2809 HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
|
2810 HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
|
2811 }
|
|
|
2812 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
|
2813 }
|
|
|
2814 }
|
|
|
2815 }
|
|
|
2816 /* Capture compare 2 event */
|
|
|
2817 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
|
|
|
2818 {
|
|
|
2819 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
|
|
|
2820 {
|
|
|
2821 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
|
|
|
2822 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
|
2823 /* Input capture event */
|
|
|
2824 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
|
|
|
2825 {
|
|
|
2826 HAL_TIM_IC_CaptureCallback(htim);
|
|
|
2827 }
|
|
|
2828 /* Output compare event */
|
|
|
2829 else
|
|
|
2830 {
|
|
|
2831 HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
|
2832 HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
|
2833 }
|
|
|
2834 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
|
2835 }
|
|
|
2836 }
|
|
|
2837 /* Capture compare 3 event */
|
|
|
2838 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
|
|
|
2839 {
|
|
|
2840 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
|
|
|
2841 {
|
|
|
2842 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
|
|
|
2843 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
|
2844 /* Input capture event */
|
|
|
2845 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
|
|
|
2846 {
|
|
|
2847 HAL_TIM_IC_CaptureCallback(htim);
|
|
|
2848 }
|
|
|
2849 /* Output compare event */
|
|
|
2850 else
|
|
|
2851 {
|
|
|
2852 HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
|
2853 HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
|
2854 }
|
|
|
2855 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
|
2856 }
|
|
|
2857 }
|
|
|
2858 /* Capture compare 4 event */
|
|
|
2859 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
|
|
|
2860 {
|
|
|
2861 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
|
|
|
2862 {
|
|
|
2863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
|
|
|
2864 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
|
2865 /* Input capture event */
|
|
|
2866 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
|
|
|
2867 {
|
|
|
2868 HAL_TIM_IC_CaptureCallback(htim);
|
|
|
2869 }
|
|
|
2870 /* Output compare event */
|
|
|
2871 else
|
|
|
2872 {
|
|
|
2873 HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
|
2874 HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
|
2875 }
|
|
|
2876 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
|
2877 }
|
|
|
2878 }
|
|
|
2879 /* TIM Update event */
|
|
|
2880 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
|
|
|
2881 {
|
|
|
2882 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
|
|
|
2883 {
|
|
|
2884 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
|
|
|
2885 HAL_TIM_PeriodElapsedCallback(htim);
|
|
|
2886 }
|
|
|
2887 }
|
|
|
2888 /* TIM Break input event */
|
|
|
2889 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
|
|
|
2890 {
|
|
|
2891 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
|
|
|
2892 {
|
|
|
2893 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
|
|
|
2894 HAL_TIMEx_BreakCallback(htim);
|
|
|
2895 }
|
|
|
2896 }
|
|
|
2897 /* TIM Trigger detection event */
|
|
|
2898 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
|
|
|
2899 {
|
|
|
2900 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
|
|
|
2901 {
|
|
|
2902 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
|
|
|
2903 HAL_TIM_TriggerCallback(htim);
|
|
|
2904 }
|
|
|
2905 }
|
|
|
2906 /* TIM commutation event */
|
|
|
2907 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
|
|
|
2908 {
|
|
|
2909 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
|
|
|
2910 {
|
|
|
2911 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
|
|
|
2912 HAL_TIMEx_CommutationCallback(htim);
|
|
|
2913 }
|
|
|
2914 }
|
|
|
2915 }
|
|
|
2916
|
|
|
2917 /**
|
|
|
2918 * @}
|
|
|
2919 */
|
|
|
2920
|
|
|
2921 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
|
|
|
2922 * @brief Peripheral Control functions
|
|
|
2923 *
|
|
|
2924 @verbatim
|
|
|
2925 ==============================================================================
|
|
|
2926 ##### Peripheral Control functions #####
|
|
|
2927 ==============================================================================
|
|
|
2928 [..]
|
|
|
2929 This section provides functions allowing to:
|
|
|
2930 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
|
|
|
2931 (+) Configure External Clock source.
|
|
|
2932 (+) Configure Complementary channels, break features and dead time.
|
|
|
2933 (+) Configure Master and the Slave synchronization.
|
|
|
2934 (+) Configure the DMA Burst Mode.
|
|
|
2935
|
|
|
2936 @endverbatim
|
|
|
2937 * @{
|
|
|
2938 */
|
|
|
2939
|
|
|
2940 /**
|
|
|
2941 * @brief Initializes the TIM Output Compare Channels according to the specified
|
|
|
2942 * parameters in the TIM_OC_InitTypeDef.
|
|
|
2943 * @param htim: TIM Output Compare handle
|
|
|
2944 * @param sConfig: TIM Output Compare configuration structure
|
|
|
2945 * @param Channel : TIM Channels to configure
|
|
|
2946 * This parameter can be one of the following values:
|
|
|
2947 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
2948 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
2949 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
2950 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
2951 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
2952 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
2953 * @retval HAL status
|
|
|
2954 */
|
|
|
2955 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
|
2956 TIM_OC_InitTypeDef* sConfig,
|
|
|
2957 uint32_t Channel)
|
|
|
2958 {
|
|
|
2959 /* Check the parameters */
|
|
|
2960 assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
2961 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
|
|
|
2962 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
|
2963
|
|
|
2964 /* Process Locked */
|
|
|
2965 __HAL_LOCK(htim);
|
|
|
2966
|
|
|
2967 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
2968
|
|
|
2969 switch (Channel)
|
|
|
2970 {
|
|
|
2971 case TIM_CHANNEL_1:
|
|
|
2972 {
|
|
|
2973 /* Check the parameters */
|
|
|
2974 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
2975
|
|
|
2976 /* Configure the TIM Channel 1 in Output Compare */
|
|
|
2977 TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
|
2978 }
|
|
|
2979 break;
|
|
|
2980
|
|
|
2981 case TIM_CHANNEL_2:
|
|
|
2982 {
|
|
|
2983 /* Check the parameters */
|
|
|
2984 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
2985
|
|
|
2986 /* Configure the TIM Channel 2 in Output Compare */
|
|
|
2987 TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
|
2988 }
|
|
|
2989 break;
|
|
|
2990
|
|
|
2991 case TIM_CHANNEL_3:
|
|
|
2992 {
|
|
|
2993 /* Check the parameters */
|
|
|
2994 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
2995
|
|
|
2996 /* Configure the TIM Channel 3 in Output Compare */
|
|
|
2997 TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
|
2998 }
|
|
|
2999 break;
|
|
|
3000
|
|
|
3001 case TIM_CHANNEL_4:
|
|
|
3002 {
|
|
|
3003 /* Check the parameters */
|
|
|
3004 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
3005
|
|
|
3006 /* Configure the TIM Channel 4 in Output Compare */
|
|
|
3007 TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
|
3008 }
|
|
|
3009 break;
|
|
|
3010
|
|
|
3011 case TIM_CHANNEL_5:
|
|
|
3012 {
|
|
|
3013 /* Check the parameters */
|
|
|
3014 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
3015
|
|
|
3016 /* Configure the TIM Channel 5 in Output Compare */
|
|
|
3017 TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
|
3018 }
|
|
|
3019 break;
|
|
|
3020
|
|
|
3021 case TIM_CHANNEL_6:
|
|
|
3022 {
|
|
|
3023 /* Check the parameters */
|
|
|
3024 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
3025
|
|
|
3026 /* Configure the TIM Channel 6 in Output Compare */
|
|
|
3027 TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
|
3028 }
|
|
|
3029 break;
|
|
|
3030
|
|
|
3031 default:
|
|
|
3032 break;
|
|
|
3033 }
|
|
|
3034
|
|
|
3035 htim->State = HAL_TIM_STATE_READY;
|
|
|
3036
|
|
|
3037 __HAL_UNLOCK(htim);
|
|
|
3038
|
|
|
3039 return HAL_OK;
|
|
|
3040 }
|
|
|
3041
|
|
|
3042 /**
|
|
|
3043 * @brief Initializes the TIM Input Capture Channels according to the specified
|
|
|
3044 * parameters in the TIM_IC_InitTypeDef.
|
|
|
3045 * @param htim: TIM IC handle
|
|
|
3046 * @param sConfig: TIM Input Capture configuration structure
|
|
|
3047 * @param Channel : TIM Channels to be enabled
|
|
|
3048 * This parameter can be one of the following values:
|
|
|
3049 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
3050 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
3051 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
3052 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
3053 * @retval HAL status
|
|
|
3054 */
|
|
|
3055 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
|
|
|
3056 {
|
|
|
3057 /* Check the parameters */
|
|
|
3058 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
3059 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
|
|
|
3060 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
|
|
|
3061 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
|
|
|
3062 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
|
|
|
3063
|
|
|
3064 /* Process Locked */
|
|
|
3065 __HAL_LOCK(htim);
|
|
|
3066
|
|
|
3067 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
3068
|
|
|
3069 if (Channel == TIM_CHANNEL_1)
|
|
|
3070 {
|
|
|
3071 /* TI1 Configuration */
|
|
|
3072 TIM_TI1_SetConfig(htim->Instance,
|
|
|
3073 sConfig->ICPolarity,
|
|
|
3074 sConfig->ICSelection,
|
|
|
3075 sConfig->ICFilter);
|
|
|
3076
|
|
|
3077 /* Reset the IC1PSC Bits */
|
|
|
3078 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
|
|
|
3079
|
|
|
3080 /* Set the IC1PSC value */
|
|
|
3081 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
|
|
|
3082 }
|
|
|
3083 else if (Channel == TIM_CHANNEL_2)
|
|
|
3084 {
|
|
|
3085 /* TI2 Configuration */
|
|
|
3086 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
3087
|
|
|
3088 TIM_TI2_SetConfig(htim->Instance,
|
|
|
3089 sConfig->ICPolarity,
|
|
|
3090 sConfig->ICSelection,
|
|
|
3091 sConfig->ICFilter);
|
|
|
3092
|
|
|
3093 /* Reset the IC2PSC Bits */
|
|
|
3094 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
|
|
|
3095
|
|
|
3096 /* Set the IC2PSC value */
|
|
|
3097 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
|
|
|
3098 }
|
|
|
3099 else if (Channel == TIM_CHANNEL_3)
|
|
|
3100 {
|
|
|
3101 /* TI3 Configuration */
|
|
|
3102 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
3103
|
|
|
3104 TIM_TI3_SetConfig(htim->Instance,
|
|
|
3105 sConfig->ICPolarity,
|
|
|
3106 sConfig->ICSelection,
|
|
|
3107 sConfig->ICFilter);
|
|
|
3108
|
|
|
3109 /* Reset the IC3PSC Bits */
|
|
|
3110 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
|
|
|
3111
|
|
|
3112 /* Set the IC3PSC value */
|
|
|
3113 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
|
|
|
3114 }
|
|
|
3115 else
|
|
|
3116 {
|
|
|
3117 /* TI4 Configuration */
|
|
|
3118 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
3119
|
|
|
3120 TIM_TI4_SetConfig(htim->Instance,
|
|
|
3121 sConfig->ICPolarity,
|
|
|
3122 sConfig->ICSelection,
|
|
|
3123 sConfig->ICFilter);
|
|
|
3124
|
|
|
3125 /* Reset the IC4PSC Bits */
|
|
|
3126 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
|
|
|
3127
|
|
|
3128 /* Set the IC4PSC value */
|
|
|
3129 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
|
|
|
3130 }
|
|
|
3131
|
|
|
3132 htim->State = HAL_TIM_STATE_READY;
|
|
|
3133
|
|
|
3134 __HAL_UNLOCK(htim);
|
|
|
3135
|
|
|
3136 return HAL_OK;
|
|
|
3137 }
|
|
|
3138
|
|
|
3139 /**
|
|
|
3140 * @brief Initializes the TIM PWM channels according to the specified
|
|
|
3141 * parameters in the TIM_OC_InitTypeDef.
|
|
|
3142 * @param htim: TIM PWM handle
|
|
|
3143 * @param sConfig: TIM PWM configuration structure
|
|
|
3144 * @param Channel : TIM Channels to be configured
|
|
|
3145 * This parameter can be one of the following values:
|
|
|
3146 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
3147 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
3148 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
3149 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
3150 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
|
3151 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
|
3152 * @retval HAL status
|
|
|
3153 */
|
|
|
3154 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
|
3155 TIM_OC_InitTypeDef* sConfig,
|
|
|
3156 uint32_t Channel)
|
|
|
3157 {
|
|
|
3158 /* Check the parameters */
|
|
|
3159 assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
3160 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
|
3161 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
|
3162 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
3163
|
|
|
3164 /* Process Locked */
|
|
|
3165 __HAL_LOCK(htim);
|
|
|
3166
|
|
|
3167 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
3168
|
|
|
3169 switch (Channel)
|
|
|
3170 {
|
|
|
3171 case TIM_CHANNEL_1:
|
|
|
3172 {
|
|
|
3173 /* Check the parameters */
|
|
|
3174 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
3175
|
|
|
3176 /* Configure the Channel 1 in PWM mode */
|
|
|
3177 TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
|
3178
|
|
|
3179 /* Set the Preload enable bit for channel1 */
|
|
|
3180 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
|
3181
|
|
|
3182 /* Configure the Output Fast mode */
|
|
|
3183 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
|
3184 htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
|
3185 }
|
|
|
3186 break;
|
|
|
3187
|
|
|
3188 case TIM_CHANNEL_2:
|
|
|
3189 {
|
|
|
3190 /* Check the parameters */
|
|
|
3191 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
3192
|
|
|
3193 /* Configure the Channel 2 in PWM mode */
|
|
|
3194 TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
|
3195
|
|
|
3196 /* Set the Preload enable bit for channel2 */
|
|
|
3197 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
|
3198
|
|
|
3199 /* Configure the Output Fast mode */
|
|
|
3200 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
|
3201 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
|
|
|
3202 }
|
|
|
3203 break;
|
|
|
3204
|
|
|
3205 case TIM_CHANNEL_3:
|
|
|
3206 {
|
|
|
3207 /* Check the parameters */
|
|
|
3208 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
3209
|
|
|
3210 /* Configure the Channel 3 in PWM mode */
|
|
|
3211 TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
|
3212
|
|
|
3213 /* Set the Preload enable bit for channel3 */
|
|
|
3214 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
|
3215
|
|
|
3216 /* Configure the Output Fast mode */
|
|
|
3217 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
|
3218 htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
|
3219 }
|
|
|
3220 break;
|
|
|
3221
|
|
|
3222 case TIM_CHANNEL_4:
|
|
|
3223 {
|
|
|
3224 /* Check the parameters */
|
|
|
3225 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
3226
|
|
|
3227 /* Configure the Channel 4 in PWM mode */
|
|
|
3228 TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
|
3229
|
|
|
3230 /* Set the Preload enable bit for channel4 */
|
|
|
3231 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
|
3232
|
|
|
3233 /* Configure the Output Fast mode */
|
|
|
3234 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
|
3235 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
|
|
|
3236 }
|
|
|
3237 break;
|
|
|
3238
|
|
|
3239 case TIM_CHANNEL_5:
|
|
|
3240 {
|
|
|
3241 /* Check the parameters */
|
|
|
3242 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
3243
|
|
|
3244 /* Configure the Channel 5 in PWM mode */
|
|
|
3245 TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
|
3246
|
|
|
3247 /* Set the Preload enable bit for channel5*/
|
|
|
3248 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
|
3249
|
|
|
3250 /* Configure the Output Fast mode */
|
|
|
3251 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
|
3252 htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
|
3253 }
|
|
|
3254 break;
|
|
|
3255
|
|
|
3256 case TIM_CHANNEL_6:
|
|
|
3257 {
|
|
|
3258 /* Check the parameters */
|
|
|
3259 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
3260
|
|
|
3261 /* Configure the Channel 5 in PWM mode */
|
|
|
3262 TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
|
3263
|
|
|
3264 /* Set the Preload enable bit for channel6 */
|
|
|
3265 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
|
3266
|
|
|
3267 /* Configure the Output Fast mode */
|
|
|
3268 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
|
3269 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
|
|
|
3270 }
|
|
|
3271 break;
|
|
|
3272
|
|
|
3273 default:
|
|
|
3274 break;
|
|
|
3275 }
|
|
|
3276
|
|
|
3277 htim->State = HAL_TIM_STATE_READY;
|
|
|
3278
|
|
|
3279 __HAL_UNLOCK(htim);
|
|
|
3280
|
|
|
3281 return HAL_OK;
|
|
|
3282 }
|
|
|
3283
|
|
|
3284 /**
|
|
|
3285 * @brief Initializes the TIM One Pulse Channels according to the specified
|
|
|
3286 * parameters in the TIM_OnePulse_InitTypeDef.
|
|
|
3287 * @param htim: TIM One Pulse handle
|
|
|
3288 * @param sConfig: TIM One Pulse configuration structure
|
|
|
3289 * @param OutputChannel : TIM Channels to be enabled
|
|
|
3290 * This parameter can be one of the following values:
|
|
|
3291 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
3292 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
3293 * @param InputChannel : TIM Channels to be enabled
|
|
|
3294 * This parameter can be one of the following values:
|
|
|
3295 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
3296 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
3297 * @retval HAL status
|
|
|
3298 */
|
|
|
3299 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
|
|
|
3300 {
|
|
|
3301 TIM_OC_InitTypeDef temp1;
|
|
|
3302
|
|
|
3303 /* Check the parameters */
|
|
|
3304 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
|
|
|
3305 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
|
|
|
3306
|
|
|
3307 if(OutputChannel != InputChannel)
|
|
|
3308 {
|
|
|
3309 /* Process Locked */
|
|
|
3310 __HAL_LOCK(htim);
|
|
|
3311
|
|
|
3312 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
3313
|
|
|
3314 /* Extract the Ouput compare configuration from sConfig structure */
|
|
|
3315 temp1.OCMode = sConfig->OCMode;
|
|
|
3316 temp1.Pulse = sConfig->Pulse;
|
|
|
3317 temp1.OCPolarity = sConfig->OCPolarity;
|
|
|
3318 temp1.OCNPolarity = sConfig->OCNPolarity;
|
|
|
3319 temp1.OCIdleState = sConfig->OCIdleState;
|
|
|
3320 temp1.OCNIdleState = sConfig->OCNIdleState;
|
|
|
3321
|
|
|
3322 switch (OutputChannel)
|
|
|
3323 {
|
|
|
3324 case TIM_CHANNEL_1:
|
|
|
3325 {
|
|
|
3326 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
3327
|
|
|
3328 TIM_OC1_SetConfig(htim->Instance, &temp1);
|
|
|
3329 }
|
|
|
3330 break;
|
|
|
3331 case TIM_CHANNEL_2:
|
|
|
3332 {
|
|
|
3333 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
3334
|
|
|
3335 TIM_OC2_SetConfig(htim->Instance, &temp1);
|
|
|
3336 }
|
|
|
3337 break;
|
|
|
3338 default:
|
|
|
3339 break;
|
|
|
3340 }
|
|
|
3341 switch (InputChannel)
|
|
|
3342 {
|
|
|
3343 case TIM_CHANNEL_1:
|
|
|
3344 {
|
|
|
3345 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
3346
|
|
|
3347 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
|
|
|
3348 sConfig->ICSelection, sConfig->ICFilter);
|
|
|
3349
|
|
|
3350 /* Reset the IC1PSC Bits */
|
|
|
3351 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
|
|
|
3352
|
|
|
3353 /* Select the Trigger source */
|
|
|
3354 htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
|
|
3355 htim->Instance->SMCR |= TIM_TS_TI1FP1;
|
|
|
3356
|
|
|
3357 /* Select the Slave Mode */
|
|
|
3358 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
|
|
|
3359 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
|
|
|
3360 }
|
|
|
3361 break;
|
|
|
3362 case TIM_CHANNEL_2:
|
|
|
3363 {
|
|
|
3364 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
3365
|
|
|
3366 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
|
|
|
3367 sConfig->ICSelection, sConfig->ICFilter);
|
|
|
3368
|
|
|
3369 /* Reset the IC2PSC Bits */
|
|
|
3370 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
|
|
|
3371
|
|
|
3372 /* Select the Trigger source */
|
|
|
3373 htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
|
|
3374 htim->Instance->SMCR |= TIM_TS_TI2FP2;
|
|
|
3375
|
|
|
3376 /* Select the Slave Mode */
|
|
|
3377 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
|
|
|
3378 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
|
|
|
3379 }
|
|
|
3380 break;
|
|
|
3381
|
|
|
3382 default:
|
|
|
3383 break;
|
|
|
3384 }
|
|
|
3385
|
|
|
3386 htim->State = HAL_TIM_STATE_READY;
|
|
|
3387
|
|
|
3388 __HAL_UNLOCK(htim);
|
|
|
3389
|
|
|
3390 return HAL_OK;
|
|
|
3391 }
|
|
|
3392 else
|
|
|
3393 {
|
|
|
3394 return HAL_ERROR;
|
|
|
3395 }
|
|
|
3396 }
|
|
|
3397
|
|
|
3398 /**
|
|
|
3399 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
|
|
|
3400 * @param htim: TIM handle
|
|
|
3401 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
|
|
|
3402 * This parameters can be on of the following values:
|
|
|
3403 * @arg TIM_DMABASE_CR1
|
|
|
3404 * @arg TIM_DMABASE_CR2
|
|
|
3405 * @arg TIM_DMABASE_SMCR
|
|
|
3406 * @arg TIM_DMABASE_DIER
|
|
|
3407 * @arg TIM_DMABASE_SR
|
|
|
3408 * @arg TIM_DMABASE_EGR
|
|
|
3409 * @arg TIM_DMABASE_CCMR1
|
|
|
3410 * @arg TIM_DMABASE_CCMR2
|
|
|
3411 * @arg TIM_DMABASE_CCER
|
|
|
3412 * @arg TIM_DMABASE_CNT
|
|
|
3413 * @arg TIM_DMABASE_PSC
|
|
|
3414 * @arg TIM_DMABASE_ARR
|
|
|
3415 * @arg TIM_DMABASE_RCR
|
|
|
3416 * @arg TIM_DMABASE_CCR1
|
|
|
3417 * @arg TIM_DMABASE_CCR2
|
|
|
3418 * @arg TIM_DMABASE_CCR3
|
|
|
3419 * @arg TIM_DMABASE_CCR4
|
|
|
3420 * @arg TIM_DMABASE_BDTR
|
|
|
3421 * @arg TIM_DMABASE_DCR
|
|
|
3422 * @param BurstRequestSrc: TIM DMA Request sources
|
|
|
3423 * This parameters can be on of the following values:
|
|
|
3424 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
|
|
|
3425 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
|
|
|
3426 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
|
|
|
3427 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
|
|
|
3428 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
|
|
|
3429 * @arg TIM_DMA_COM: TIM Commutation DMA source
|
|
|
3430 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
|
|
|
3431 * @param BurstBuffer: The Buffer address.
|
|
|
3432 * @param BurstLength: DMA Burst length. This parameter can be one value
|
|
|
3433 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
|
|
|
3434 * @retval HAL status
|
|
|
3435 */
|
|
|
3436 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
|
|
|
3437 uint32_t* BurstBuffer, uint32_t BurstLength)
|
|
|
3438 {
|
|
|
3439 /* Check the parameters */
|
|
|
3440 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
|
|
|
3441 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
|
|
|
3442 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
|
|
|
3443 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
|
|
|
3444
|
|
|
3445 if((htim->State == HAL_TIM_STATE_BUSY))
|
|
|
3446 {
|
|
|
3447 return HAL_BUSY;
|
|
|
3448 }
|
|
|
3449 else if((htim->State == HAL_TIM_STATE_READY))
|
|
|
3450 {
|
|
|
3451 if((BurstBuffer == 0 ) && (BurstLength > 0))
|
|
|
3452 {
|
|
|
3453 return HAL_ERROR;
|
|
|
3454 }
|
|
|
3455 else
|
|
|
3456 {
|
|
|
3457 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
3458 }
|
|
|
3459 }
|
|
|
3460 switch(BurstRequestSrc)
|
|
|
3461 {
|
|
|
3462 case TIM_DMA_UPDATE:
|
|
|
3463 {
|
|
|
3464 /* Set the DMA Period elapsed callback */
|
|
|
3465 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
|
|
|
3466
|
|
|
3467 /* Set the DMA error callback */
|
|
|
3468 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
|
|
|
3469
|
|
|
3470 /* Enable the DMA channel */
|
|
|
3471 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
|
|
3472 }
|
|
|
3473 break;
|
|
|
3474 case TIM_DMA_CC1:
|
|
|
3475 {
|
|
|
3476 /* Set the DMA Period elapsed callback */
|
|
|
3477 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
3478
|
|
|
3479 /* Set the DMA error callback */
|
|
|
3480 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
3481
|
|
|
3482 /* Enable the DMA channel */
|
|
|
3483 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
|
|
3484 }
|
|
|
3485 break;
|
|
|
3486 case TIM_DMA_CC2:
|
|
|
3487 {
|
|
|
3488 /* Set the DMA Period elapsed callback */
|
|
|
3489 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
3490
|
|
|
3491 /* Set the DMA error callback */
|
|
|
3492 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
3493
|
|
|
3494 /* Enable the DMA channel */
|
|
|
3495 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
|
|
3496 }
|
|
|
3497 break;
|
|
|
3498 case TIM_DMA_CC3:
|
|
|
3499 {
|
|
|
3500 /* Set the DMA Period elapsed callback */
|
|
|
3501 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
3502
|
|
|
3503 /* Set the DMA error callback */
|
|
|
3504 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
|
|
3505
|
|
|
3506 /* Enable the DMA channel */
|
|
|
3507 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
|
|
3508 }
|
|
|
3509 break;
|
|
|
3510 case TIM_DMA_CC4:
|
|
|
3511 {
|
|
|
3512 /* Set the DMA Period elapsed callback */
|
|
|
3513 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
3514
|
|
|
3515 /* Set the DMA error callback */
|
|
|
3516 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
|
|
3517
|
|
|
3518 /* Enable the DMA channel */
|
|
|
3519 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
|
|
3520 }
|
|
|
3521 break;
|
|
|
3522 case TIM_DMA_COM:
|
|
|
3523 {
|
|
|
3524 /* Set the DMA Period elapsed callback */
|
|
|
3525 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
|
|
|
3526
|
|
|
3527 /* Set the DMA error callback */
|
|
|
3528 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
|
|
|
3529
|
|
|
3530 /* Enable the DMA channel */
|
|
|
3531 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
|
|
3532 }
|
|
|
3533 break;
|
|
|
3534 case TIM_DMA_TRIGGER:
|
|
|
3535 {
|
|
|
3536 /* Set the DMA Period elapsed callback */
|
|
|
3537 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
|
|
|
3538
|
|
|
3539 /* Set the DMA error callback */
|
|
|
3540 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
|
|
|
3541
|
|
|
3542 /* Enable the DMA channel */
|
|
|
3543 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
|
|
|
3544 }
|
|
|
3545 break;
|
|
|
3546 default:
|
|
|
3547 break;
|
|
|
3548 }
|
|
|
3549 /* configure the DMA Burst Mode */
|
|
|
3550 htim->Instance->DCR = BurstBaseAddress | BurstLength;
|
|
|
3551
|
|
|
3552 /* Enable the TIM DMA Request */
|
|
|
3553 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
|
|
|
3554
|
|
|
3555 htim->State = HAL_TIM_STATE_READY;
|
|
|
3556
|
|
|
3557 /* Return function status */
|
|
|
3558 return HAL_OK;
|
|
|
3559 }
|
|
|
3560
|
|
|
3561 /**
|
|
|
3562 * @brief Stops the TIM DMA Burst mode
|
|
|
3563 * @param htim: TIM handle
|
|
|
3564 * @param BurstRequestSrc: TIM DMA Request sources to disable
|
|
|
3565 * @retval HAL status
|
|
|
3566 */
|
|
|
3567 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
|
|
|
3568 {
|
|
|
3569 /* Check the parameters */
|
|
|
3570 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
|
|
|
3571
|
|
|
3572 /* Abort the DMA transfer (at least disable the DMA channel) */
|
|
|
3573 switch(BurstRequestSrc)
|
|
|
3574 {
|
|
|
3575 case TIM_DMA_UPDATE:
|
|
|
3576 {
|
|
|
3577 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
|
|
|
3578 }
|
|
|
3579 break;
|
|
|
3580 case TIM_DMA_CC1:
|
|
|
3581 {
|
|
|
3582 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
|
|
|
3583 }
|
|
|
3584 break;
|
|
|
3585 case TIM_DMA_CC2:
|
|
|
3586 {
|
|
|
3587 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
|
|
|
3588 }
|
|
|
3589 break;
|
|
|
3590 case TIM_DMA_CC3:
|
|
|
3591 {
|
|
|
3592 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
|
|
|
3593 }
|
|
|
3594 break;
|
|
|
3595 case TIM_DMA_CC4:
|
|
|
3596 {
|
|
|
3597 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
|
|
|
3598 }
|
|
|
3599 break;
|
|
|
3600 case TIM_DMA_COM:
|
|
|
3601 {
|
|
|
3602 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
|
|
|
3603 }
|
|
|
3604 break;
|
|
|
3605 case TIM_DMA_TRIGGER:
|
|
|
3606 {
|
|
|
3607 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
|
|
|
3608 }
|
|
|
3609 break;
|
|
|
3610 default:
|
|
|
3611 break;
|
|
|
3612 }
|
|
|
3613
|
|
|
3614 /* Disable the TIM Update DMA request */
|
|
|
3615 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
|
|
|
3616
|
|
|
3617 /* Return function status */
|
|
|
3618 return HAL_OK;
|
|
|
3619 }
|
|
|
3620
|
|
|
3621 /**
|
|
|
3622 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
|
|
|
3623 * @param htim: TIM handle
|
|
|
3624 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
|
|
|
3625 * This parameters can be on of the following values:
|
|
|
3626 * @arg TIM_DMABASE_CR1
|
|
|
3627 * @arg TIM_DMABASE_CR2
|
|
|
3628 * @arg TIM_DMABASE_SMCR
|
|
|
3629 * @arg TIM_DMABASE_DIER
|
|
|
3630 * @arg TIM_DMABASE_SR
|
|
|
3631 * @arg TIM_DMABASE_EGR
|
|
|
3632 * @arg TIM_DMABASE_CCMR1
|
|
|
3633 * @arg TIM_DMABASE_CCMR2
|
|
|
3634 * @arg TIM_DMABASE_CCER
|
|
|
3635 * @arg TIM_DMABASE_CNT
|
|
|
3636 * @arg TIM_DMABASE_PSC
|
|
|
3637 * @arg TIM_DMABASE_ARR
|
|
|
3638 * @arg TIM_DMABASE_RCR
|
|
|
3639 * @arg TIM_DMABASE_CCR1
|
|
|
3640 * @arg TIM_DMABASE_CCR2
|
|
|
3641 * @arg TIM_DMABASE_CCR3
|
|
|
3642 * @arg TIM_DMABASE_CCR4
|
|
|
3643 * @arg TIM_DMABASE_BDTR
|
|
|
3644 * @arg TIM_DMABASE_DCR
|
|
|
3645 * @param BurstRequestSrc: TIM DMA Request sources
|
|
|
3646 * This parameters can be on of the following values:
|
|
|
3647 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
|
|
|
3648 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
|
|
|
3649 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
|
|
|
3650 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
|
|
|
3651 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
|
|
|
3652 * @arg TIM_DMA_COM: TIM Commutation DMA source
|
|
|
3653 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
|
|
|
3654 * @param BurstBuffer: The Buffer address.
|
|
|
3655 * @param BurstLength: DMA Burst length. This parameter can be one value
|
|
|
3656 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
|
|
|
3657 * @retval HAL status
|
|
|
3658 */
|
|
|
3659 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
|
|
|
3660 uint32_t *BurstBuffer, uint32_t BurstLength)
|
|
|
3661 {
|
|
|
3662 /* Check the parameters */
|
|
|
3663 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
|
|
|
3664 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
|
|
|
3665 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
|
|
|
3666 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
|
|
|
3667
|
|
|
3668 if((htim->State == HAL_TIM_STATE_BUSY))
|
|
|
3669 {
|
|
|
3670 return HAL_BUSY;
|
|
|
3671 }
|
|
|
3672 else if((htim->State == HAL_TIM_STATE_READY))
|
|
|
3673 {
|
|
|
3674 if((BurstBuffer == 0 ) && (BurstLength > 0))
|
|
|
3675 {
|
|
|
3676 return HAL_ERROR;
|
|
|
3677 }
|
|
|
3678 else
|
|
|
3679 {
|
|
|
3680 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
3681 }
|
|
|
3682 }
|
|
|
3683 switch(BurstRequestSrc)
|
|
|
3684 {
|
|
|
3685 case TIM_DMA_UPDATE:
|
|
|
3686 {
|
|
|
3687 /* Set the DMA Period elapsed callback */
|
|
|
3688 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
|
|
|
3689
|
|
|
3690 /* Set the DMA error callback */
|
|
|
3691 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
|
|
|
3692
|
|
|
3693 /* Enable the DMA channel */
|
|
|
3694 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
|
|
3695 }
|
|
|
3696 break;
|
|
|
3697 case TIM_DMA_CC1:
|
|
|
3698 {
|
|
|
3699 /* Set the DMA Period elapsed callback */
|
|
|
3700 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
3701
|
|
|
3702 /* Set the DMA error callback */
|
|
|
3703 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
3704
|
|
|
3705 /* Enable the DMA channel */
|
|
|
3706 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
|
|
3707 }
|
|
|
3708 break;
|
|
|
3709 case TIM_DMA_CC2:
|
|
|
3710 {
|
|
|
3711 /* Set the DMA Period elapsed callback */
|
|
|
3712 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
3713
|
|
|
3714 /* Set the DMA error callback */
|
|
|
3715 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
3716
|
|
|
3717 /* Enable the DMA channel */
|
|
|
3718 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
|
|
3719 }
|
|
|
3720 break;
|
|
|
3721 case TIM_DMA_CC3:
|
|
|
3722 {
|
|
|
3723 /* Set the DMA Period elapsed callback */
|
|
|
3724 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
3725
|
|
|
3726 /* Set the DMA error callback */
|
|
|
3727 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
|
|
3728
|
|
|
3729 /* Enable the DMA channel */
|
|
|
3730 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
|
|
3731 }
|
|
|
3732 break;
|
|
|
3733 case TIM_DMA_CC4:
|
|
|
3734 {
|
|
|
3735 /* Set the DMA Period elapsed callback */
|
|
|
3736 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
3737
|
|
|
3738 /* Set the DMA error callback */
|
|
|
3739 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
|
|
3740
|
|
|
3741 /* Enable the DMA channel */
|
|
|
3742 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
|
|
3743 }
|
|
|
3744 break;
|
|
|
3745 case TIM_DMA_COM:
|
|
|
3746 {
|
|
|
3747 /* Set the DMA Period elapsed callback */
|
|
|
3748 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
|
|
|
3749
|
|
|
3750 /* Set the DMA error callback */
|
|
|
3751 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
|
|
|
3752
|
|
|
3753 /* Enable the DMA channel */
|
|
|
3754 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
|
|
3755 }
|
|
|
3756 break;
|
|
|
3757 case TIM_DMA_TRIGGER:
|
|
|
3758 {
|
|
|
3759 /* Set the DMA Period elapsed callback */
|
|
|
3760 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
|
|
|
3761
|
|
|
3762 /* Set the DMA error callback */
|
|
|
3763 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
|
|
|
3764
|
|
|
3765 /* Enable the DMA channel */
|
|
|
3766 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
|
|
|
3767 }
|
|
|
3768 break;
|
|
|
3769 default:
|
|
|
3770 break;
|
|
|
3771 }
|
|
|
3772
|
|
|
3773 /* configure the DMA Burst Mode */
|
|
|
3774 htim->Instance->DCR = BurstBaseAddress | BurstLength;
|
|
|
3775
|
|
|
3776 /* Enable the TIM DMA Request */
|
|
|
3777 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
|
|
|
3778
|
|
|
3779 htim->State = HAL_TIM_STATE_READY;
|
|
|
3780
|
|
|
3781 /* Return function status */
|
|
|
3782 return HAL_OK;
|
|
|
3783 }
|
|
|
3784
|
|
|
3785 /**
|
|
|
3786 * @brief Stop the DMA burst reading
|
|
|
3787 * @param htim: TIM handle
|
|
|
3788 * @param BurstRequestSrc: TIM DMA Request sources to disable.
|
|
|
3789 * @retval HAL status
|
|
|
3790 */
|
|
|
3791 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
|
|
|
3792 {
|
|
|
3793 /* Check the parameters */
|
|
|
3794 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
|
|
|
3795
|
|
|
3796 /* Abort the DMA transfer (at least disable the DMA channel) */
|
|
|
3797 switch(BurstRequestSrc)
|
|
|
3798 {
|
|
|
3799 case TIM_DMA_UPDATE:
|
|
|
3800 {
|
|
|
3801 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
|
|
|
3802 }
|
|
|
3803 break;
|
|
|
3804 case TIM_DMA_CC1:
|
|
|
3805 {
|
|
|
3806 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
|
|
|
3807 }
|
|
|
3808 break;
|
|
|
3809 case TIM_DMA_CC2:
|
|
|
3810 {
|
|
|
3811 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
|
|
|
3812 }
|
|
|
3813 break;
|
|
|
3814 case TIM_DMA_CC3:
|
|
|
3815 {
|
|
|
3816 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
|
|
|
3817 }
|
|
|
3818 break;
|
|
|
3819 case TIM_DMA_CC4:
|
|
|
3820 {
|
|
|
3821 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
|
|
|
3822 }
|
|
|
3823 break;
|
|
|
3824 case TIM_DMA_COM:
|
|
|
3825 {
|
|
|
3826 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
|
|
|
3827 }
|
|
|
3828 break;
|
|
|
3829 case TIM_DMA_TRIGGER:
|
|
|
3830 {
|
|
|
3831 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
|
|
|
3832 }
|
|
|
3833 break;
|
|
|
3834 default:
|
|
|
3835 break;
|
|
|
3836 }
|
|
|
3837
|
|
|
3838 /* Disable the TIM Update DMA request */
|
|
|
3839 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
|
|
|
3840
|
|
|
3841 /* Return function status */
|
|
|
3842 return HAL_OK;
|
|
|
3843 }
|
|
|
3844
|
|
|
3845 /**
|
|
|
3846 * @brief Generate a software event
|
|
|
3847 * @param htim: TIM handle
|
|
|
3848 * @param EventSource: specifies the event source.
|
|
|
3849 * This parameter can be one of the following values:
|
|
|
3850 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
|
|
|
3851 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
|
|
|
3852 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
|
|
|
3853 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
|
|
|
3854 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
|
|
|
3855 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
|
|
|
3856 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
|
|
|
3857 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
|
|
|
3858 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
|
|
|
3859 * @retval None
|
|
|
3860 */
|
|
|
3861
|
|
|
3862 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
|
|
|
3863 {
|
|
|
3864 /* Check the parameters */
|
|
|
3865 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
3866 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
|
|
|
3867
|
|
|
3868 /* Process Locked */
|
|
|
3869 __HAL_LOCK(htim);
|
|
|
3870
|
|
|
3871 /* Change the TIM state */
|
|
|
3872 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
3873
|
|
|
3874 /* Set the event sources */
|
|
|
3875 htim->Instance->EGR = EventSource;
|
|
|
3876
|
|
|
3877 /* Change the TIM state */
|
|
|
3878 htim->State = HAL_TIM_STATE_READY;
|
|
|
3879
|
|
|
3880 __HAL_UNLOCK(htim);
|
|
|
3881
|
|
|
3882 /* Return function status */
|
|
|
3883 return HAL_OK;
|
|
|
3884 }
|
|
|
3885
|
|
|
3886 /**
|
|
|
3887 * @brief Configures the OCRef clear feature
|
|
|
3888 * @param htim: TIM handle
|
|
|
3889 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
|
|
|
3890 * contains the OCREF clear feature and parameters for the TIM peripheral.
|
|
|
3891 * @param Channel: specifies the TIM Channel
|
|
|
3892 * This parameter can be one of the following values:
|
|
|
3893 * @arg TIM_Channel_1: TIM Channel 1
|
|
|
3894 * @arg TIM_Channel_2: TIM Channel 2
|
|
|
3895 * @arg TIM_Channel_3: TIM Channel 3
|
|
|
3896 * @arg TIM_Channel_4: TIM Channel 4
|
|
|
3897 * @arg TIM_Channel_5: TIM Channel 5
|
|
|
3898 * @arg TIM_Channel_6: TIM Channel 6
|
|
|
3899 * @retval None
|
|
|
3900 */
|
|
|
3901 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
|
|
|
3902 TIM_ClearInputConfigTypeDef *sClearInputConfig,
|
|
|
3903 uint32_t Channel)
|
|
|
3904 {
|
|
|
3905 uint32_t tmpsmcr = 0;
|
|
|
3906
|
|
|
3907 /* Check the parameters */
|
|
|
3908 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
|
|
|
3909 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
|
|
|
3910
|
|
|
3911 /* Process Locked */
|
|
|
3912 __HAL_LOCK(htim);
|
|
|
3913
|
|
|
3914 switch (sClearInputConfig->ClearInputSource)
|
|
|
3915 {
|
|
|
3916 case TIM_CLEARINPUTSOURCE_NONE:
|
|
|
3917 {
|
|
|
3918 /* Get the TIMx SMCR register value */
|
|
|
3919 tmpsmcr = htim->Instance->SMCR;
|
|
|
3920
|
|
|
3921 /* Clear the OCREF clear selection bit */
|
|
|
3922 tmpsmcr &= ~TIM_SMCR_OCCS;
|
|
|
3923
|
|
|
3924 /* Clear the ETR Bits */
|
|
|
3925 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
|
3926
|
|
|
3927 /* Set TIMx_SMCR */
|
|
|
3928 htim->Instance->SMCR = tmpsmcr;
|
|
|
3929 }
|
|
|
3930 break;
|
|
|
3931
|
|
|
3932 case TIM_CLEARINPUTSOURCE_OCREFCLR:
|
|
|
3933 {
|
|
|
3934 /* Clear the OCREF clear selection bit */
|
|
|
3935 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
|
|
|
3936 }
|
|
|
3937 break;
|
|
|
3938
|
|
|
3939 case TIM_CLEARINPUTSOURCE_ETR:
|
|
|
3940 {
|
|
|
3941 /* Check the parameters */
|
|
|
3942 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
|
|
|
3943 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
|
|
|
3944 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
|
|
|
3945
|
|
|
3946 TIM_ETR_SetConfig(htim->Instance,
|
|
|
3947 sClearInputConfig->ClearInputPrescaler,
|
|
|
3948 sClearInputConfig->ClearInputPolarity,
|
|
|
3949 sClearInputConfig->ClearInputFilter);
|
|
|
3950
|
|
|
3951 /* Set the OCREF clear selection bit */
|
|
|
3952 htim->Instance->SMCR |= TIM_SMCR_OCCS;
|
|
|
3953 }
|
|
|
3954 break;
|
|
|
3955
|
|
|
3956 default:
|
|
|
3957 break;
|
|
|
3958 }
|
|
|
3959
|
|
|
3960 switch (Channel)
|
|
|
3961 {
|
|
|
3962 case TIM_CHANNEL_1:
|
|
|
3963 {
|
|
|
3964 if(sClearInputConfig->ClearInputState != RESET)
|
|
|
3965 {
|
|
|
3966 /* Enable the OCREF clear feature for Channel 1 */
|
|
|
3967 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
|
|
|
3968 }
|
|
|
3969 else
|
|
|
3970 {
|
|
|
3971 /* Disable the OCREF clear feature for Channel 1 */
|
|
|
3972 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
|
|
|
3973 }
|
|
|
3974 }
|
|
|
3975 break;
|
|
|
3976 case TIM_CHANNEL_2:
|
|
|
3977 {
|
|
|
3978 if(sClearInputConfig->ClearInputState != RESET)
|
|
|
3979 {
|
|
|
3980 /* Enable the OCREF clear feature for Channel 2 */
|
|
|
3981 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
|
|
|
3982 }
|
|
|
3983 else
|
|
|
3984 {
|
|
|
3985 /* Disable the OCREF clear feature for Channel 2 */
|
|
|
3986 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
|
|
|
3987 }
|
|
|
3988 }
|
|
|
3989 break;
|
|
|
3990 case TIM_CHANNEL_3:
|
|
|
3991 {
|
|
|
3992 if(sClearInputConfig->ClearInputState != RESET)
|
|
|
3993 {
|
|
|
3994 /* Enable the OCREF clear feature for Channel 3 */
|
|
|
3995 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
|
|
|
3996 }
|
|
|
3997 else
|
|
|
3998 {
|
|
|
3999 /* Disable the OCREF clear feature for Channel 3 */
|
|
|
4000 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
|
|
|
4001 }
|
|
|
4002 }
|
|
|
4003 break;
|
|
|
4004 case TIM_CHANNEL_4:
|
|
|
4005 {
|
|
|
4006 if(sClearInputConfig->ClearInputState != RESET)
|
|
|
4007 {
|
|
|
4008 /* Enable the OCREF clear feature for Channel 4 */
|
|
|
4009 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
|
|
|
4010 }
|
|
|
4011 else
|
|
|
4012 {
|
|
|
4013 /* Disable the OCREF clear feature for Channel 4 */
|
|
|
4014 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
|
|
|
4015 }
|
|
|
4016 }
|
|
|
4017 break;
|
|
|
4018 case TIM_CHANNEL_5:
|
|
|
4019 {
|
|
|
4020 if(sClearInputConfig->ClearInputState != RESET)
|
|
|
4021 {
|
|
|
4022 /* Enable the OCREF clear feature for Channel 1 */
|
|
|
4023 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
|
|
|
4024 }
|
|
|
4025 else
|
|
|
4026 {
|
|
|
4027 /* Disable the OCREF clear feature for Channel 1 */
|
|
|
4028 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
|
|
|
4029 }
|
|
|
4030 }
|
|
|
4031 break;
|
|
|
4032 case TIM_CHANNEL_6:
|
|
|
4033 {
|
|
|
4034 if(sClearInputConfig->ClearInputState != RESET)
|
|
|
4035 {
|
|
|
4036 /* Enable the OCREF clear feature for Channel 1 */
|
|
|
4037 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
|
|
|
4038 }
|
|
|
4039 else
|
|
|
4040 {
|
|
|
4041 /* Disable the OCREF clear feature for Channel 1 */
|
|
|
4042 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
|
|
|
4043 }
|
|
|
4044 }
|
|
|
4045 break;
|
|
|
4046 default:
|
|
|
4047 break;
|
|
|
4048 }
|
|
|
4049
|
|
|
4050 __HAL_UNLOCK(htim);
|
|
|
4051
|
|
|
4052 return HAL_OK;
|
|
|
4053 }
|
|
|
4054
|
|
|
4055 /**
|
|
|
4056 * @brief Configures the clock source to be used
|
|
|
4057 * @param htim: TIM handle
|
|
|
4058 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
|
|
|
4059 * contains the clock source information for the TIM peripheral.
|
|
|
4060 * @retval HAL status
|
|
|
4061 */
|
|
|
4062 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
|
|
|
4063 {
|
|
|
4064 uint32_t tmpsmcr = 0;
|
|
|
4065
|
|
|
4066 /* Process Locked */
|
|
|
4067 __HAL_LOCK(htim);
|
|
|
4068
|
|
|
4069 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
4070
|
|
|
4071 /* Check the parameters */
|
|
|
4072 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
4073
|
|
|
4074 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
|
4075 tmpsmcr = htim->Instance->SMCR;
|
|
|
4076 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
|
4077 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
|
4078 htim->Instance->SMCR = tmpsmcr;
|
|
|
4079
|
|
|
4080 switch (sClockSourceConfig->ClockSource)
|
|
|
4081 {
|
|
|
4082 case TIM_CLOCKSOURCE_INTERNAL:
|
|
|
4083 {
|
|
|
4084 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
4085 /* Disable slave mode to clock the prescaler directly with the internal clock */
|
|
|
4086 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
|
|
|
4087 }
|
|
|
4088 break;
|
|
|
4089
|
|
|
4090 case TIM_CLOCKSOURCE_ETRMODE1:
|
|
|
4091 {
|
|
|
4092 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
|
|
|
4093 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
|
|
|
4094
|
|
|
4095 /* Check ETR input conditioning related parameters */
|
|
|
4096 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
|
4097 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
4098 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
4099
|
|
|
4100 /* Configure the ETR Clock source */
|
|
|
4101 TIM_ETR_SetConfig(htim->Instance,
|
|
|
4102 sClockSourceConfig->ClockPrescaler,
|
|
|
4103 sClockSourceConfig->ClockPolarity,
|
|
|
4104 sClockSourceConfig->ClockFilter);
|
|
|
4105 /* Get the TIMx SMCR register value */
|
|
|
4106 tmpsmcr = htim->Instance->SMCR;
|
|
|
4107 /* Reset the SMS and TS Bits */
|
|
|
4108 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
|
4109 /* Select the External clock mode1 and the ETRF trigger */
|
|
|
4110 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
|
4111 /* Write to TIMx SMCR */
|
|
|
4112 htim->Instance->SMCR = tmpsmcr;
|
|
|
4113 }
|
|
|
4114 break;
|
|
|
4115
|
|
|
4116 case TIM_CLOCKSOURCE_ETRMODE2:
|
|
|
4117 {
|
|
|
4118 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
|
|
|
4119 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
|
|
|
4120
|
|
|
4121 /* Check ETR input conditioning related parameters */
|
|
|
4122 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
|
4123 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
4124 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
4125
|
|
|
4126 /* Configure the ETR Clock source */
|
|
|
4127 TIM_ETR_SetConfig(htim->Instance,
|
|
|
4128 sClockSourceConfig->ClockPrescaler,
|
|
|
4129 sClockSourceConfig->ClockPolarity,
|
|
|
4130 sClockSourceConfig->ClockFilter);
|
|
|
4131 /* Enable the External clock mode2 */
|
|
|
4132 htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
|
4133 }
|
|
|
4134 break;
|
|
|
4135
|
|
|
4136 case TIM_CLOCKSOURCE_TI1:
|
|
|
4137 {
|
|
|
4138 /* Check whether or not the timer instance supports external clock mode 1 */
|
|
|
4139 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
|
|
|
4140
|
|
|
4141 /* Check TI1 input conditioning related parameters */
|
|
|
4142 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
4143 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
4144
|
|
|
4145 TIM_TI1_ConfigInputStage(htim->Instance,
|
|
|
4146 sClockSourceConfig->ClockPolarity,
|
|
|
4147 sClockSourceConfig->ClockFilter);
|
|
|
4148 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
|
4149 }
|
|
|
4150 break;
|
|
|
4151
|
|
|
4152 case TIM_CLOCKSOURCE_TI2:
|
|
|
4153 {
|
|
|
4154 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
|
|
|
4155 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
|
|
|
4156
|
|
|
4157 /* Check TI2 input conditioning related parameters */
|
|
|
4158 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
4159 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
4160
|
|
|
4161 TIM_TI2_ConfigInputStage(htim->Instance,
|
|
|
4162 sClockSourceConfig->ClockPolarity,
|
|
|
4163 sClockSourceConfig->ClockFilter);
|
|
|
4164 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
|
4165 }
|
|
|
4166 break;
|
|
|
4167
|
|
|
4168 case TIM_CLOCKSOURCE_TI1ED:
|
|
|
4169 {
|
|
|
4170 /* Check whether or not the timer instance supports external clock mode 1 */
|
|
|
4171 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
|
|
|
4172
|
|
|
4173 /* Check TI1 input conditioning related parameters */
|
|
|
4174 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
|
4175 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
4176
|
|
|
4177 TIM_TI1_ConfigInputStage(htim->Instance,
|
|
|
4178 sClockSourceConfig->ClockPolarity,
|
|
|
4179 sClockSourceConfig->ClockFilter);
|
|
|
4180 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
|
4181 }
|
|
|
4182 break;
|
|
|
4183
|
|
|
4184 case TIM_CLOCKSOURCE_ITR0:
|
|
|
4185 {
|
|
|
4186 /* Check whether or not the timer instance supports internal trigger input */
|
|
|
4187 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
4188
|
|
|
4189 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
|
|
|
4190 }
|
|
|
4191 break;
|
|
|
4192
|
|
|
4193 case TIM_CLOCKSOURCE_ITR1:
|
|
|
4194 {
|
|
|
4195 /* Check whether or not the timer instance supports internal trigger input */
|
|
|
4196 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
4197
|
|
|
4198 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
|
|
|
4199 }
|
|
|
4200 break;
|
|
|
4201
|
|
|
4202 case TIM_CLOCKSOURCE_ITR2:
|
|
|
4203 {
|
|
|
4204 /* Check whether or not the timer instance supports internal trigger input */
|
|
|
4205 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
4206
|
|
|
4207 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
|
|
|
4208 }
|
|
|
4209 break;
|
|
|
4210
|
|
|
4211 case TIM_CLOCKSOURCE_ITR3:
|
|
|
4212 {
|
|
|
4213 /* Check whether or not the timer instance supports internal trigger input */
|
|
|
4214 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
4215
|
|
|
4216 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
|
|
|
4217 }
|
|
|
4218 break;
|
|
|
4219
|
|
|
4220 default:
|
|
|
4221 break;
|
|
|
4222 }
|
|
|
4223 htim->State = HAL_TIM_STATE_READY;
|
|
|
4224
|
|
|
4225 __HAL_UNLOCK(htim);
|
|
|
4226
|
|
|
4227 return HAL_OK;
|
|
|
4228 }
|
|
|
4229
|
|
|
4230 /**
|
|
|
4231 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
|
|
|
4232 * or a XOR combination between CH1_input, CH2_input & CH3_input
|
|
|
4233 * @param htim: TIM handle.
|
|
|
4234 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
|
|
|
4235 * output of a XOR gate.
|
|
|
4236 * This parameter can be one of the following values:
|
|
|
4237 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
|
|
|
4238 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
|
|
|
4239 * pins are connected to the TI1 input (XOR combination)
|
|
|
4240 * @retval HAL status
|
|
|
4241 */
|
|
|
4242 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
|
|
|
4243 {
|
|
|
4244 uint32_t tmpcr2 = 0;
|
|
|
4245
|
|
|
4246 /* Check the parameters */
|
|
|
4247 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
|
|
|
4248 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
|
|
|
4249
|
|
|
4250 /* Get the TIMx CR2 register value */
|
|
|
4251 tmpcr2 = htim->Instance->CR2;
|
|
|
4252
|
|
|
4253 /* Reset the TI1 selection */
|
|
|
4254 tmpcr2 &= ~TIM_CR2_TI1S;
|
|
|
4255
|
|
|
4256 /* Set the TI1 selection */
|
|
|
4257 tmpcr2 |= TI1_Selection;
|
|
|
4258
|
|
|
4259 /* Write to TIMxCR2 */
|
|
|
4260 htim->Instance->CR2 = tmpcr2;
|
|
|
4261
|
|
|
4262 return HAL_OK;
|
|
|
4263 }
|
|
|
4264
|
|
|
4265 /**
|
|
|
4266 * @brief Configures the TIM in Slave mode
|
|
|
4267 * @param htim: TIM handle.
|
|
|
4268 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
|
|
|
4269 * contains the selected trigger (internal trigger input, filtered
|
|
|
4270 * timer input or external trigger input) and the ) and the Slave
|
|
|
4271 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
|
|
|
4272 * @retval HAL status
|
|
|
4273 */
|
|
|
4274 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
|
|
|
4275 {
|
|
|
4276 /* Check the parameters */
|
|
|
4277 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
|
|
|
4278 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
|
|
|
4279 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
|
|
|
4280
|
|
|
4281 __HAL_LOCK(htim);
|
|
|
4282
|
|
|
4283 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
4284
|
|
|
4285 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
|
|
|
4286
|
|
|
4287 /* Disable Trigger Interrupt */
|
|
|
4288 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
|
|
|
4289
|
|
|
4290 /* Disable Trigger DMA request */
|
|
|
4291 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
|
|
|
4292
|
|
|
4293 htim->State = HAL_TIM_STATE_READY;
|
|
|
4294
|
|
|
4295 __HAL_UNLOCK(htim);
|
|
|
4296
|
|
|
4297 return HAL_OK;
|
|
|
4298 }
|
|
|
4299
|
|
|
4300 /**
|
|
|
4301 * @brief Configures the TIM in Slave mode in interrupt mode
|
|
|
4302 * @param htim: TIM handle.
|
|
|
4303 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
|
|
|
4304 * contains the selected trigger (internal trigger input, filtered
|
|
|
4305 * timer input or external trigger input) and the ) and the Slave
|
|
|
4306 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
|
|
|
4307 * @retval HAL status
|
|
|
4308 */
|
|
|
4309 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
|
|
|
4310 TIM_SlaveConfigTypeDef * sSlaveConfig)
|
|
|
4311 {
|
|
|
4312 /* Check the parameters */
|
|
|
4313 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
|
|
|
4314 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
|
|
|
4315 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
|
|
|
4316
|
|
|
4317 __HAL_LOCK(htim);
|
|
|
4318
|
|
|
4319 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
4320
|
|
|
4321 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
|
|
|
4322
|
|
|
4323 /* Enable Trigger Interrupt */
|
|
|
4324 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
|
|
|
4325
|
|
|
4326 /* Disable Trigger DMA request */
|
|
|
4327 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
|
|
|
4328
|
|
|
4329 htim->State = HAL_TIM_STATE_READY;
|
|
|
4330
|
|
|
4331 __HAL_UNLOCK(htim);
|
|
|
4332
|
|
|
4333 return HAL_OK;
|
|
|
4334 }
|
|
|
4335
|
|
|
4336 /**
|
|
|
4337 * @brief Read the captured value from Capture Compare unit
|
|
|
4338 * @param htim: TIM handle.
|
|
|
4339 * @param Channel : TIM Channels to be enabled
|
|
|
4340 * This parameter can be one of the following values:
|
|
|
4341 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
4342 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
4343 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
4344 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
4345 * @retval Captured value
|
|
|
4346 */
|
|
|
4347 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
4348 {
|
|
|
4349 uint32_t tmpreg = 0;
|
|
|
4350
|
|
|
4351 __HAL_LOCK(htim);
|
|
|
4352
|
|
|
4353 switch (Channel)
|
|
|
4354 {
|
|
|
4355 case TIM_CHANNEL_1:
|
|
|
4356 {
|
|
|
4357 /* Check the parameters */
|
|
|
4358 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
4359
|
|
|
4360 /* Return the capture 1 value */
|
|
|
4361 tmpreg = htim->Instance->CCR1;
|
|
|
4362
|
|
|
4363 break;
|
|
|
4364 }
|
|
|
4365 case TIM_CHANNEL_2:
|
|
|
4366 {
|
|
|
4367 /* Check the parameters */
|
|
|
4368 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
4369
|
|
|
4370 /* Return the capture 2 value */
|
|
|
4371 tmpreg = htim->Instance->CCR2;
|
|
|
4372
|
|
|
4373 break;
|
|
|
4374 }
|
|
|
4375
|
|
|
4376 case TIM_CHANNEL_3:
|
|
|
4377 {
|
|
|
4378 /* Check the parameters */
|
|
|
4379 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
4380
|
|
|
4381 /* Return the capture 3 value */
|
|
|
4382 tmpreg = htim->Instance->CCR3;
|
|
|
4383
|
|
|
4384 break;
|
|
|
4385 }
|
|
|
4386
|
|
|
4387 case TIM_CHANNEL_4:
|
|
|
4388 {
|
|
|
4389 /* Check the parameters */
|
|
|
4390 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
4391
|
|
|
4392 /* Return the capture 4 value */
|
|
|
4393 tmpreg = htim->Instance->CCR4;
|
|
|
4394
|
|
|
4395 break;
|
|
|
4396 }
|
|
|
4397
|
|
|
4398 default:
|
|
|
4399 break;
|
|
|
4400 }
|
|
|
4401
|
|
|
4402 __HAL_UNLOCK(htim);
|
|
|
4403 return tmpreg;
|
|
|
4404 }
|
|
|
4405
|
|
|
4406 /**
|
|
|
4407 * @}
|
|
|
4408 */
|
|
|
4409
|
|
|
4410 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
|
|
|
4411 * @brief TIM Callbacks functions
|
|
|
4412 *
|
|
|
4413 @verbatim
|
|
|
4414 ==============================================================================
|
|
|
4415 ##### TIM Callbacks functions #####
|
|
|
4416 ==============================================================================
|
|
|
4417 [..]
|
|
|
4418 This section provides TIM callback functions:
|
|
|
4419 (+) Timer Period elapsed callback
|
|
|
4420 (+) Timer Output Compare callback
|
|
|
4421 (+) Timer Input capture callback
|
|
|
4422 (+) Timer Trigger callback
|
|
|
4423 (+) Timer Error callback
|
|
|
4424
|
|
|
4425 @endverbatim
|
|
|
4426 * @{
|
|
|
4427 */
|
|
|
4428
|
|
|
4429 /**
|
|
|
4430 * @brief Period elapsed callback in non-blocking mode
|
|
|
4431 * @param htim : TIM handle
|
|
|
4432 * @retval None
|
|
|
4433 */
|
|
|
4434 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|
|
4435 {
|
|
|
4436 /* Prevent unused argument(s) compilation warning */
|
|
|
4437 UNUSED(htim);
|
|
|
4438
|
|
|
4439 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
4440 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
|
|
|
4441 */
|
|
|
4442
|
|
|
4443 }
|
|
|
4444 /**
|
|
|
4445 * @brief Output Compare callback in non-blocking mode
|
|
|
4446 * @param htim : TIM OC handle
|
|
|
4447 * @retval None
|
|
|
4448 */
|
|
|
4449 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
|
4450 {
|
|
|
4451 /* Prevent unused argument(s) compilation warning */
|
|
|
4452 UNUSED(htim);
|
|
|
4453
|
|
|
4454 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
4455 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
|
4456 */
|
|
|
4457 }
|
|
|
4458 /**
|
|
|
4459 * @brief Input Capture callback in non-blocking mode
|
|
|
4460 * @param htim : TIM IC handle
|
|
|
4461 * @retval None
|
|
|
4462 */
|
|
|
4463 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
|
4464 {
|
|
|
4465 /* Prevent unused argument(s) compilation warning */
|
|
|
4466 UNUSED(htim);
|
|
|
4467
|
|
|
4468 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
4469 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
|
4470 */
|
|
|
4471 }
|
|
|
4472
|
|
|
4473 /**
|
|
|
4474 * @brief PWM Pulse finished callback in non-blocking mode
|
|
|
4475 * @param htim : TIM handle
|
|
|
4476 * @retval None
|
|
|
4477 */
|
|
|
4478 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
|
4479 {
|
|
|
4480 /* Prevent unused argument(s) compilation warning */
|
|
|
4481 UNUSED(htim);
|
|
|
4482
|
|
|
4483 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
4484 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
|
4485 */
|
|
|
4486 }
|
|
|
4487
|
|
|
4488 /**
|
|
|
4489 * @brief Hall Trigger detection callback in non-blocking mode
|
|
|
4490 * @param htim : TIM handle
|
|
|
4491 * @retval None
|
|
|
4492 */
|
|
|
4493 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
|
4494 {
|
|
|
4495 /* Prevent unused argument(s) compilation warning */
|
|
|
4496 UNUSED(htim);
|
|
|
4497
|
|
|
4498 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
4499 the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
|
4500 */
|
|
|
4501 }
|
|
|
4502
|
|
|
4503 /**
|
|
|
4504 * @brief Timer error callback in non-blocking mode
|
|
|
4505 * @param htim : TIM handle
|
|
|
4506 * @retval None
|
|
|
4507 */
|
|
|
4508 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
|
|
|
4509 {
|
|
|
4510 /* Prevent unused argument(s) compilation warning */
|
|
|
4511 UNUSED(htim);
|
|
|
4512
|
|
|
4513 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
4514 the HAL_TIM_ErrorCallback could be implemented in the user file
|
|
|
4515 */
|
|
|
4516 }
|
|
|
4517
|
|
|
4518 /**
|
|
|
4519 * @}
|
|
|
4520 */
|
|
|
4521
|
|
|
4522 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
|
|
|
4523 * @brief Peripheral State functions
|
|
|
4524 *
|
|
|
4525 @verbatim
|
|
|
4526 ==============================================================================
|
|
|
4527 ##### Peripheral State functions #####
|
|
|
4528 ==============================================================================
|
|
|
4529 [..]
|
|
|
4530 This subsection permits to get in run-time the status of the peripheral
|
|
|
4531 and the data flow.
|
|
|
4532
|
|
|
4533 @endverbatim
|
|
|
4534 * @{
|
|
|
4535 */
|
|
|
4536
|
|
|
4537 /**
|
|
|
4538 * @brief Return the TIM Base handle state.
|
|
|
4539 * @param htim: TIM Base handle
|
|
|
4540 * @retval HAL state
|
|
|
4541 */
|
|
|
4542 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
|
|
|
4543 {
|
|
|
4544 return htim->State;
|
|
|
4545 }
|
|
|
4546
|
|
|
4547 /**
|
|
|
4548 * @brief Return the TIM OC handle state.
|
|
|
4549 * @param htim: TIM Ouput Compare handle
|
|
|
4550 * @retval HAL state
|
|
|
4551 */
|
|
|
4552 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
|
|
|
4553 {
|
|
|
4554 return htim->State;
|
|
|
4555 }
|
|
|
4556
|
|
|
4557 /**
|
|
|
4558 * @brief Return the TIM PWM handle state.
|
|
|
4559 * @param htim: TIM handle
|
|
|
4560 * @retval HAL state
|
|
|
4561 */
|
|
|
4562 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
|
|
|
4563 {
|
|
|
4564 return htim->State;
|
|
|
4565 }
|
|
|
4566
|
|
|
4567 /**
|
|
|
4568 * @brief Return the TIM Input Capture handle state.
|
|
|
4569 * @param htim: TIM IC handle
|
|
|
4570 * @retval HAL state
|
|
|
4571 */
|
|
|
4572 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
|
|
|
4573 {
|
|
|
4574 return htim->State;
|
|
|
4575 }
|
|
|
4576
|
|
|
4577 /**
|
|
|
4578 * @brief Return the TIM One Pulse Mode handle state.
|
|
|
4579 * @param htim: TIM OPM handle
|
|
|
4580 * @retval HAL state
|
|
|
4581 */
|
|
|
4582 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
|
|
|
4583 {
|
|
|
4584 return htim->State;
|
|
|
4585 }
|
|
|
4586
|
|
|
4587 /**
|
|
|
4588 * @brief Return the TIM Encoder Mode handle state.
|
|
|
4589 * @param htim: TIM Encoder handle
|
|
|
4590 * @retval HAL state
|
|
|
4591 */
|
|
|
4592 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
|
|
|
4593 {
|
|
|
4594 return htim->State;
|
|
|
4595 }
|
|
|
4596
|
|
|
4597 /**
|
|
|
4598 * @}
|
|
|
4599 */
|
|
|
4600
|
|
|
4601 /**
|
|
|
4602 * @brief TIM DMA error callback
|
|
|
4603 * @param hdma : pointer to DMA handle.
|
|
|
4604 * @retval None
|
|
|
4605 */
|
|
|
4606 void TIM_DMAError(DMA_HandleTypeDef *hdma)
|
|
|
4607 {
|
|
|
4608 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
|
4609
|
|
|
4610 htim->State= HAL_TIM_STATE_READY;
|
|
|
4611
|
|
|
4612 HAL_TIM_ErrorCallback(htim);
|
|
|
4613 }
|
|
|
4614
|
|
|
4615 /**
|
|
|
4616 * @brief TIM DMA Delay Pulse complete callback.
|
|
|
4617 * @param hdma : pointer to DMA handle.
|
|
|
4618 * @retval None
|
|
|
4619 */
|
|
|
4620 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
|
|
|
4621 {
|
|
|
4622 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
|
4623
|
|
|
4624 htim->State= HAL_TIM_STATE_READY;
|
|
|
4625
|
|
|
4626 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
|
|
|
4627 {
|
|
|
4628 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
|
4629 }
|
|
|
4630 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
|
|
|
4631 {
|
|
|
4632 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
|
4633 }
|
|
|
4634 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
|
|
|
4635 {
|
|
|
4636 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
|
4637 }
|
|
|
4638 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
|
|
|
4639 {
|
|
|
4640 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
|
4641 }
|
|
|
4642
|
|
|
4643 HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
|
4644
|
|
|
4645 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
|
4646 }
|
|
|
4647 /**
|
|
|
4648 * @brief TIM DMA Capture complete callback.
|
|
|
4649 * @param hdma : pointer to DMA handle.
|
|
|
4650 * @retval None
|
|
|
4651 */
|
|
|
4652 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
|
|
|
4653 {
|
|
|
4654 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
|
4655
|
|
|
4656 htim->State= HAL_TIM_STATE_READY;
|
|
|
4657
|
|
|
4658 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
|
|
|
4659 {
|
|
|
4660 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
|
4661 }
|
|
|
4662 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
|
|
|
4663 {
|
|
|
4664 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
|
4665 }
|
|
|
4666 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
|
|
|
4667 {
|
|
|
4668 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
|
4669 }
|
|
|
4670 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
|
|
|
4671 {
|
|
|
4672 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
|
4673 }
|
|
|
4674
|
|
|
4675 HAL_TIM_IC_CaptureCallback(htim);
|
|
|
4676
|
|
|
4677 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
|
4678 }
|
|
|
4679
|
|
|
4680 /**
|
|
|
4681 * @brief TIM DMA Period Elapse complete callback.
|
|
|
4682 * @param hdma : pointer to DMA handle.
|
|
|
4683 * @retval None
|
|
|
4684 */
|
|
|
4685 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
|
|
|
4686 {
|
|
|
4687 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
|
4688
|
|
|
4689 htim->State= HAL_TIM_STATE_READY;
|
|
|
4690
|
|
|
4691 HAL_TIM_PeriodElapsedCallback(htim);
|
|
|
4692 }
|
|
|
4693
|
|
|
4694 /**
|
|
|
4695 * @brief TIM DMA Trigger callback.
|
|
|
4696 * @param hdma : pointer to DMA handle.
|
|
|
4697 * @retval None
|
|
|
4698 */
|
|
|
4699 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
|
|
|
4700 {
|
|
|
4701 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
|
4702
|
|
|
4703 htim->State= HAL_TIM_STATE_READY;
|
|
|
4704
|
|
|
4705 HAL_TIM_TriggerCallback(htim);
|
|
|
4706 }
|
|
|
4707
|
|
|
4708 /**
|
|
|
4709 * @brief Time Base configuration
|
|
|
4710 * @param TIMx: TIM peripheral
|
|
|
4711 * @param Structure: TIM Base configuration structure
|
|
|
4712 * @retval None
|
|
|
4713 */
|
|
|
4714 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
|
|
|
4715 {
|
|
|
4716 uint32_t tmpcr1 = 0;
|
|
|
4717 tmpcr1 = TIMx->CR1;
|
|
|
4718
|
|
|
4719 /* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
|
4720 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
|
4721 {
|
|
|
4722 /* Select the Counter Mode */
|
|
|
4723 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
|
4724 tmpcr1 |= Structure->CounterMode;
|
|
|
4725 }
|
|
|
4726
|
|
|
4727 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
|
4728 {
|
|
|
4729 /* Set the clock division */
|
|
|
4730 tmpcr1 &= ~TIM_CR1_CKD;
|
|
|
4731 tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
|
4732 }
|
|
|
4733
|
|
|
4734 TIMx->CR1 = tmpcr1;
|
|
|
4735
|
|
|
4736 /* Set the Autoreload value */
|
|
|
4737 TIMx->ARR = (uint32_t)Structure->Period ;
|
|
|
4738
|
|
|
4739 /* Set the Prescaler value */
|
|
|
4740 TIMx->PSC = (uint32_t)Structure->Prescaler;
|
|
|
4741
|
|
|
4742 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
|
4743 {
|
|
|
4744 /* Set the Repetition Counter value */
|
|
|
4745 TIMx->RCR = Structure->RepetitionCounter;
|
|
|
4746 }
|
|
|
4747
|
|
|
4748 /* Generate an update event to reload the Prescaler
|
|
|
4749 and the repetition counter(only for TIM1 and TIM8) value immediately */
|
|
|
4750 TIMx->EGR = TIM_EGR_UG;
|
|
|
4751 }
|
|
|
4752
|
|
|
4753 /**
|
|
|
4754 * @brief Time Ouput Compare 1 configuration
|
|
|
4755 * @param TIMx to select the TIM peripheral
|
|
|
4756 * @param OC_Config: The ouput configuration structure
|
|
|
4757 * @retval None
|
|
|
4758 */
|
|
|
4759 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
|
4760 {
|
|
|
4761 uint32_t tmpccmrx = 0;
|
|
|
4762 uint32_t tmpccer = 0;
|
|
|
4763 uint32_t tmpcr2 = 0;
|
|
|
4764
|
|
|
4765 /* Disable the Channel 1: Reset the CC1E Bit */
|
|
|
4766 TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
|
4767
|
|
|
4768 /* Get the TIMx CCER register value */
|
|
|
4769 tmpccer = TIMx->CCER;
|
|
|
4770 /* Get the TIMx CR2 register value */
|
|
|
4771 tmpcr2 = TIMx->CR2;
|
|
|
4772
|
|
|
4773 /* Get the TIMx CCMR1 register value */
|
|
|
4774 tmpccmrx = TIMx->CCMR1;
|
|
|
4775
|
|
|
4776 /* Reset the Output Compare Mode Bits */
|
|
|
4777 tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
|
4778 tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
|
4779 /* Select the Output Compare Mode */
|
|
|
4780 tmpccmrx |= OC_Config->OCMode;
|
|
|
4781
|
|
|
4782 /* Reset the Output Polarity level */
|
|
|
4783 tmpccer &= ~TIM_CCER_CC1P;
|
|
|
4784 /* Set the Output Compare Polarity */
|
|
|
4785 tmpccer |= OC_Config->OCPolarity;
|
|
|
4786
|
|
|
4787 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
|
4788 {
|
|
|
4789 /* Check parameters */
|
|
|
4790 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
4791
|
|
|
4792 /* Reset the Output N Polarity level */
|
|
|
4793 tmpccer &= ~TIM_CCER_CC1NP;
|
|
|
4794 /* Set the Output N Polarity */
|
|
|
4795 tmpccer |= OC_Config->OCNPolarity;
|
|
|
4796 /* Reset the Output N State */
|
|
|
4797 tmpccer &= ~TIM_CCER_CC1NE;
|
|
|
4798 }
|
|
|
4799
|
|
|
4800 if(IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
4801 {
|
|
|
4802 /* Check parameters */
|
|
|
4803 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
|
4804 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
4805
|
|
|
4806 /* Reset the Output Compare and Output Compare N IDLE State */
|
|
|
4807 tmpcr2 &= ~TIM_CR2_OIS1;
|
|
|
4808 tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
|
4809 /* Set the Output Idle state */
|
|
|
4810 tmpcr2 |= OC_Config->OCIdleState;
|
|
|
4811 /* Set the Output N Idle state */
|
|
|
4812 tmpcr2 |= OC_Config->OCNIdleState;
|
|
|
4813 }
|
|
|
4814 /* Write to TIMx CR2 */
|
|
|
4815 TIMx->CR2 = tmpcr2;
|
|
|
4816
|
|
|
4817 /* Write to TIMx CCMR1 */
|
|
|
4818 TIMx->CCMR1 = tmpccmrx;
|
|
|
4819
|
|
|
4820 /* Set the Capture Compare Register value */
|
|
|
4821 TIMx->CCR1 = OC_Config->Pulse;
|
|
|
4822
|
|
|
4823 /* Write to TIMx CCER */
|
|
|
4824 TIMx->CCER = tmpccer;
|
|
|
4825 }
|
|
|
4826
|
|
|
4827 /**
|
|
|
4828 * @brief Time Ouput Compare 2 configuration
|
|
|
4829 * @param TIMx to select the TIM peripheral
|
|
|
4830 * @param OC_Config: The ouput configuration structure
|
|
|
4831 * @retval None
|
|
|
4832 */
|
|
|
4833 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
|
4834 {
|
|
|
4835 uint32_t tmpccmrx = 0;
|
|
|
4836 uint32_t tmpccer = 0;
|
|
|
4837 uint32_t tmpcr2 = 0;
|
|
|
4838
|
|
|
4839 /* Disable the Channel 2: Reset the CC2E Bit */
|
|
|
4840 TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
|
4841
|
|
|
4842 /* Get the TIMx CCER register value */
|
|
|
4843 tmpccer = TIMx->CCER;
|
|
|
4844 /* Get the TIMx CR2 register value */
|
|
|
4845 tmpcr2 = TIMx->CR2;
|
|
|
4846
|
|
|
4847 /* Get the TIMx CCMR1 register value */
|
|
|
4848 tmpccmrx = TIMx->CCMR1;
|
|
|
4849
|
|
|
4850 /* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
|
4851 tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
|
4852 tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
|
4853
|
|
|
4854 /* Select the Output Compare Mode */
|
|
|
4855 tmpccmrx |= (OC_Config->OCMode << 8);
|
|
|
4856
|
|
|
4857 /* Reset the Output Polarity level */
|
|
|
4858 tmpccer &= ~TIM_CCER_CC2P;
|
|
|
4859 /* Set the Output Compare Polarity */
|
|
|
4860 tmpccer |= (OC_Config->OCPolarity << 4);
|
|
|
4861
|
|
|
4862 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
|
4863 {
|
|
|
4864 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
4865
|
|
|
4866 /* Reset the Output N Polarity level */
|
|
|
4867 tmpccer &= ~TIM_CCER_CC2NP;
|
|
|
4868 /* Set the Output N Polarity */
|
|
|
4869 tmpccer |= (OC_Config->OCNPolarity << 4);
|
|
|
4870 /* Reset the Output N State */
|
|
|
4871 tmpccer &= ~TIM_CCER_CC2NE;
|
|
|
4872
|
|
|
4873 }
|
|
|
4874
|
|
|
4875 if(IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
4876 {
|
|
|
4877 /* Check parameters */
|
|
|
4878 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
|
4879 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
4880
|
|
|
4881 /* Reset the Output Compare and Output Compare N IDLE State */
|
|
|
4882 tmpcr2 &= ~TIM_CR2_OIS2;
|
|
|
4883 tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
|
4884 /* Set the Output Idle state */
|
|
|
4885 tmpcr2 |= (OC_Config->OCIdleState << 2);
|
|
|
4886 /* Set the Output N Idle state */
|
|
|
4887 tmpcr2 |= (OC_Config->OCNIdleState << 2);
|
|
|
4888 }
|
|
|
4889
|
|
|
4890 /* Write to TIMx CR2 */
|
|
|
4891 TIMx->CR2 = tmpcr2;
|
|
|
4892
|
|
|
4893 /* Write to TIMx CCMR1 */
|
|
|
4894 TIMx->CCMR1 = tmpccmrx;
|
|
|
4895
|
|
|
4896 /* Set the Capture Compare Register value */
|
|
|
4897 TIMx->CCR2 = OC_Config->Pulse;
|
|
|
4898
|
|
|
4899 /* Write to TIMx CCER */
|
|
|
4900 TIMx->CCER = tmpccer;
|
|
|
4901 }
|
|
|
4902
|
|
|
4903 /**
|
|
|
4904 * @brief Time Ouput Compare 3 configuration
|
|
|
4905 * @param TIMx to select the TIM peripheral
|
|
|
4906 * @param OC_Config: The ouput configuration structure
|
|
|
4907 * @retval None
|
|
|
4908 */
|
|
|
4909 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
|
4910 {
|
|
|
4911 uint32_t tmpccmrx = 0;
|
|
|
4912 uint32_t tmpccer = 0;
|
|
|
4913 uint32_t tmpcr2 = 0;
|
|
|
4914
|
|
|
4915 /* Disable the Channel 3: Reset the CC2E Bit */
|
|
|
4916 TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
|
4917
|
|
|
4918 /* Get the TIMx CCER register value */
|
|
|
4919 tmpccer = TIMx->CCER;
|
|
|
4920 /* Get the TIMx CR2 register value */
|
|
|
4921 tmpcr2 = TIMx->CR2;
|
|
|
4922
|
|
|
4923 /* Get the TIMx CCMR2 register value */
|
|
|
4924 tmpccmrx = TIMx->CCMR2;
|
|
|
4925
|
|
|
4926 /* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
|
4927 tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
|
4928 tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
|
4929 /* Select the Output Compare Mode */
|
|
|
4930 tmpccmrx |= OC_Config->OCMode;
|
|
|
4931
|
|
|
4932 /* Reset the Output Polarity level */
|
|
|
4933 tmpccer &= ~TIM_CCER_CC3P;
|
|
|
4934 /* Set the Output Compare Polarity */
|
|
|
4935 tmpccer |= (OC_Config->OCPolarity << 8);
|
|
|
4936
|
|
|
4937 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
|
4938 {
|
|
|
4939 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
4940
|
|
|
4941 /* Reset the Output N Polarity level */
|
|
|
4942 tmpccer &= ~TIM_CCER_CC3NP;
|
|
|
4943 /* Set the Output N Polarity */
|
|
|
4944 tmpccer |= (OC_Config->OCNPolarity << 8);
|
|
|
4945 /* Reset the Output N State */
|
|
|
4946 tmpccer &= ~TIM_CCER_CC3NE;
|
|
|
4947 }
|
|
|
4948
|
|
|
4949 if(IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
4950 {
|
|
|
4951 /* Check parameters */
|
|
|
4952 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
|
4953 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
4954
|
|
|
4955 /* Reset the Output Compare and Output Compare N IDLE State */
|
|
|
4956 tmpcr2 &= ~TIM_CR2_OIS3;
|
|
|
4957 tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
|
4958 /* Set the Output Idle state */
|
|
|
4959 tmpcr2 |= (OC_Config->OCIdleState << 4);
|
|
|
4960 /* Set the Output N Idle state */
|
|
|
4961 tmpcr2 |= (OC_Config->OCNIdleState << 4);
|
|
|
4962 }
|
|
|
4963
|
|
|
4964 /* Write to TIMx CR2 */
|
|
|
4965 TIMx->CR2 = tmpcr2;
|
|
|
4966
|
|
|
4967 /* Write to TIMx CCMR2 */
|
|
|
4968 TIMx->CCMR2 = tmpccmrx;
|
|
|
4969
|
|
|
4970 /* Set the Capture Compare Register value */
|
|
|
4971 TIMx->CCR3 = OC_Config->Pulse;
|
|
|
4972
|
|
|
4973 /* Write to TIMx CCER */
|
|
|
4974 TIMx->CCER = tmpccer;
|
|
|
4975 }
|
|
|
4976
|
|
|
4977 /**
|
|
|
4978 * @brief Time Ouput Compare 4 configuration
|
|
|
4979 * @param TIMx to select the TIM peripheral
|
|
|
4980 * @param OC_Config: The ouput configuration structure
|
|
|
4981 * @retval None
|
|
|
4982 */
|
|
|
4983 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
|
4984 {
|
|
|
4985 uint32_t tmpccmrx = 0;
|
|
|
4986 uint32_t tmpccer = 0;
|
|
|
4987 uint32_t tmpcr2 = 0;
|
|
|
4988
|
|
|
4989 /* Disable the Channel 4: Reset the CC4E Bit */
|
|
|
4990 TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
|
4991
|
|
|
4992 /* Get the TIMx CCER register value */
|
|
|
4993 tmpccer = TIMx->CCER;
|
|
|
4994 /* Get the TIMx CR2 register value */
|
|
|
4995 tmpcr2 = TIMx->CR2;
|
|
|
4996
|
|
|
4997 /* Get the TIMx CCMR2 register value */
|
|
|
4998 tmpccmrx = TIMx->CCMR2;
|
|
|
4999
|
|
|
5000 /* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
|
5001 tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
|
5002 tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
|
5003
|
|
|
5004 /* Select the Output Compare Mode */
|
|
|
5005 tmpccmrx |= (OC_Config->OCMode << 8);
|
|
|
5006
|
|
|
5007 /* Reset the Output Polarity level */
|
|
|
5008 tmpccer &= ~TIM_CCER_CC4P;
|
|
|
5009 /* Set the Output Compare Polarity */
|
|
|
5010 tmpccer |= (OC_Config->OCPolarity << 12);
|
|
|
5011
|
|
|
5012 if(IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
5013 {
|
|
|
5014 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
5015
|
|
|
5016 /* Reset the Output Compare IDLE State */
|
|
|
5017 tmpcr2 &= ~TIM_CR2_OIS4;
|
|
|
5018 /* Set the Output Idle state */
|
|
|
5019 tmpcr2 |= (OC_Config->OCIdleState << 6);
|
|
|
5020 }
|
|
|
5021
|
|
|
5022 /* Write to TIMx CR2 */
|
|
|
5023 TIMx->CR2 = tmpcr2;
|
|
|
5024
|
|
|
5025 /* Write to TIMx CCMR2 */
|
|
|
5026 TIMx->CCMR2 = tmpccmrx;
|
|
|
5027
|
|
|
5028 /* Set the Capture Compare Register value */
|
|
|
5029 TIMx->CCR4 = OC_Config->Pulse;
|
|
|
5030
|
|
|
5031 /* Write to TIMx CCER */
|
|
|
5032 TIMx->CCER = tmpccer;
|
|
|
5033 }
|
|
|
5034
|
|
|
5035 /**
|
|
|
5036 * @brief Timer Ouput Compare 5 configuration
|
|
|
5037 * @param TIMx to select the TIM peripheral
|
|
|
5038 * @param OC_Config: The ouput configuration structure
|
|
|
5039 * @retval None
|
|
|
5040 */
|
|
|
5041 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
|
5042 TIM_OC_InitTypeDef *OC_Config)
|
|
|
5043 {
|
|
|
5044 uint32_t tmpccmrx = 0;
|
|
|
5045 uint32_t tmpccer = 0;
|
|
|
5046 uint32_t tmpcr2 = 0;
|
|
|
5047
|
|
|
5048 /* Disable the output: Reset the CCxE Bit */
|
|
|
5049 TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
|
5050
|
|
|
5051 /* Get the TIMx CCER register value */
|
|
|
5052 tmpccer = TIMx->CCER;
|
|
|
5053 /* Get the TIMx CR2 register value */
|
|
|
5054 tmpcr2 = TIMx->CR2;
|
|
|
5055 /* Get the TIMx CCMR1 register value */
|
|
|
5056 tmpccmrx = TIMx->CCMR3;
|
|
|
5057
|
|
|
5058 /* Reset the Output Compare Mode Bits */
|
|
|
5059 tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
|
5060 /* Select the Output Compare Mode */
|
|
|
5061 tmpccmrx |= OC_Config->OCMode;
|
|
|
5062
|
|
|
5063 /* Reset the Output Polarity level */
|
|
|
5064 tmpccer &= ~TIM_CCER_CC5P;
|
|
|
5065 /* Set the Output Compare Polarity */
|
|
|
5066 tmpccer |= (OC_Config->OCPolarity << 16);
|
|
|
5067
|
|
|
5068 if(IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
5069 {
|
|
|
5070 /* Reset the Output Compare IDLE State */
|
|
|
5071 tmpcr2 &= ~TIM_CR2_OIS5;
|
|
|
5072 /* Set the Output Idle state */
|
|
|
5073 tmpcr2 |= (OC_Config->OCIdleState << 8);
|
|
|
5074 }
|
|
|
5075 /* Write to TIMx CR2 */
|
|
|
5076 TIMx->CR2 = tmpcr2;
|
|
|
5077
|
|
|
5078 /* Write to TIMx CCMR3 */
|
|
|
5079 TIMx->CCMR3 = tmpccmrx;
|
|
|
5080
|
|
|
5081 /* Set the Capture Compare Register value */
|
|
|
5082 TIMx->CCR5 = OC_Config->Pulse;
|
|
|
5083
|
|
|
5084 /* Write to TIMx CCER */
|
|
|
5085 TIMx->CCER = tmpccer;
|
|
|
5086 }
|
|
|
5087
|
|
|
5088 /**
|
|
|
5089 * @brief Timer Ouput Compare 6 configuration
|
|
|
5090 * @param TIMx to select the TIM peripheral
|
|
|
5091 * @param OC_Config: The ouput configuration structure
|
|
|
5092 * @retval None
|
|
|
5093 */
|
|
|
5094 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
|
5095 TIM_OC_InitTypeDef *OC_Config)
|
|
|
5096 {
|
|
|
5097 uint32_t tmpccmrx = 0;
|
|
|
5098 uint32_t tmpccer = 0;
|
|
|
5099 uint32_t tmpcr2 = 0;
|
|
|
5100
|
|
|
5101 /* Disable the output: Reset the CCxE Bit */
|
|
|
5102 TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
|
5103
|
|
|
5104 /* Get the TIMx CCER register value */
|
|
|
5105 tmpccer = TIMx->CCER;
|
|
|
5106 /* Get the TIMx CR2 register value */
|
|
|
5107 tmpcr2 = TIMx->CR2;
|
|
|
5108 /* Get the TIMx CCMR1 register value */
|
|
|
5109 tmpccmrx = TIMx->CCMR3;
|
|
|
5110
|
|
|
5111 /* Reset the Output Compare Mode Bits */
|
|
|
5112 tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
|
5113 /* Select the Output Compare Mode */
|
|
|
5114 tmpccmrx |= (OC_Config->OCMode << 8);
|
|
|
5115
|
|
|
5116 /* Reset the Output Polarity level */
|
|
|
5117 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
|
5118 /* Set the Output Compare Polarity */
|
|
|
5119 tmpccer |= (OC_Config->OCPolarity << 20);
|
|
|
5120
|
|
|
5121 if(IS_TIM_BREAK_INSTANCE(TIMx))
|
|
|
5122 {
|
|
|
5123 /* Reset the Output Compare IDLE State */
|
|
|
5124 tmpcr2 &= ~TIM_CR2_OIS6;
|
|
|
5125 /* Set the Output Idle state */
|
|
|
5126 tmpcr2 |= (OC_Config->OCIdleState << 10);
|
|
|
5127 }
|
|
|
5128
|
|
|
5129 /* Write to TIMx CR2 */
|
|
|
5130 TIMx->CR2 = tmpcr2;
|
|
|
5131
|
|
|
5132 /* Write to TIMx CCMR3 */
|
|
|
5133 TIMx->CCMR3 = tmpccmrx;
|
|
|
5134
|
|
|
5135 /* Set the Capture Compare Register value */
|
|
|
5136 TIMx->CCR6 = OC_Config->Pulse;
|
|
|
5137
|
|
|
5138 /* Write to TIMx CCER */
|
|
|
5139 TIMx->CCER = tmpccer;
|
|
|
5140 }
|
|
|
5141
|
|
|
5142 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
|
|
|
5143 TIM_SlaveConfigTypeDef * sSlaveConfig)
|
|
|
5144 {
|
|
|
5145 uint32_t tmpsmcr = 0;
|
|
|
5146 uint32_t tmpccmr1 = 0;
|
|
|
5147 uint32_t tmpccer = 0;
|
|
|
5148
|
|
|
5149 /* Get the TIMx SMCR register value */
|
|
|
5150 tmpsmcr = htim->Instance->SMCR;
|
|
|
5151
|
|
|
5152 /* Reset the Trigger Selection Bits */
|
|
|
5153 tmpsmcr &= ~TIM_SMCR_TS;
|
|
|
5154 /* Set the Input Trigger source */
|
|
|
5155 tmpsmcr |= sSlaveConfig->InputTrigger;
|
|
|
5156
|
|
|
5157 /* Reset the slave mode Bits */
|
|
|
5158 tmpsmcr &= ~TIM_SMCR_SMS;
|
|
|
5159 /* Set the slave mode */
|
|
|
5160 tmpsmcr |= sSlaveConfig->SlaveMode;
|
|
|
5161
|
|
|
5162 /* Write to TIMx SMCR */
|
|
|
5163 htim->Instance->SMCR = tmpsmcr;
|
|
|
5164
|
|
|
5165 /* Configure the trigger prescaler, filter, and polarity */
|
|
|
5166 switch (sSlaveConfig->InputTrigger)
|
|
|
5167 {
|
|
|
5168 case TIM_TS_ETRF:
|
|
|
5169 {
|
|
|
5170 /* Check the parameters */
|
|
|
5171 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
|
|
|
5172 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
|
|
|
5173 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
|
|
|
5174 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
|
|
|
5175 /* Configure the ETR Trigger source */
|
|
|
5176 TIM_ETR_SetConfig(htim->Instance,
|
|
|
5177 sSlaveConfig->TriggerPrescaler,
|
|
|
5178 sSlaveConfig->TriggerPolarity,
|
|
|
5179 sSlaveConfig->TriggerFilter);
|
|
|
5180 }
|
|
|
5181 break;
|
|
|
5182
|
|
|
5183 case TIM_TS_TI1F_ED:
|
|
|
5184 {
|
|
|
5185 /* Check the parameters */
|
|
|
5186 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
5187 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
|
|
|
5188
|
|
|
5189 /* Disable the Channel 1: Reset the CC1E Bit */
|
|
|
5190 tmpccer = htim->Instance->CCER;
|
|
|
5191 htim->Instance->CCER &= ~TIM_CCER_CC1E;
|
|
|
5192 tmpccmr1 = htim->Instance->CCMR1;
|
|
|
5193
|
|
|
5194 /* Set the filter */
|
|
|
5195 tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
|
5196 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
|
|
|
5197
|
|
|
5198 /* Write to TIMx CCMR1 and CCER registers */
|
|
|
5199 htim->Instance->CCMR1 = tmpccmr1;
|
|
|
5200 htim->Instance->CCER = tmpccer;
|
|
|
5201
|
|
|
5202 }
|
|
|
5203 break;
|
|
|
5204
|
|
|
5205 case TIM_TS_TI1FP1:
|
|
|
5206 {
|
|
|
5207 /* Check the parameters */
|
|
|
5208 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
5209 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
|
|
|
5210 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
|
|
|
5211
|
|
|
5212 /* Configure TI1 Filter and Polarity */
|
|
|
5213 TIM_TI1_ConfigInputStage(htim->Instance,
|
|
|
5214 sSlaveConfig->TriggerPolarity,
|
|
|
5215 sSlaveConfig->TriggerFilter);
|
|
|
5216 }
|
|
|
5217 break;
|
|
|
5218
|
|
|
5219 case TIM_TS_TI2FP2:
|
|
|
5220 {
|
|
|
5221 /* Check the parameters */
|
|
|
5222 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
5223 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
|
|
|
5224 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
|
|
|
5225
|
|
|
5226 /* Configure TI2 Filter and Polarity */
|
|
|
5227 TIM_TI2_ConfigInputStage(htim->Instance,
|
|
|
5228 sSlaveConfig->TriggerPolarity,
|
|
|
5229 sSlaveConfig->TriggerFilter);
|
|
|
5230 }
|
|
|
5231 break;
|
|
|
5232
|
|
|
5233 case TIM_TS_ITR0:
|
|
|
5234 {
|
|
|
5235 /* Check the parameter */
|
|
|
5236 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
5237 }
|
|
|
5238 break;
|
|
|
5239
|
|
|
5240 case TIM_TS_ITR1:
|
|
|
5241 {
|
|
|
5242 /* Check the parameter */
|
|
|
5243 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
5244 }
|
|
|
5245 break;
|
|
|
5246
|
|
|
5247 case TIM_TS_ITR2:
|
|
|
5248 {
|
|
|
5249 /* Check the parameter */
|
|
|
5250 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
5251 }
|
|
|
5252 break;
|
|
|
5253
|
|
|
5254 case TIM_TS_ITR3:
|
|
|
5255 {
|
|
|
5256 /* Check the parameter */
|
|
|
5257 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
5258 }
|
|
|
5259 break;
|
|
|
5260
|
|
|
5261 default:
|
|
|
5262 break;
|
|
|
5263 }
|
|
|
5264 }
|
|
|
5265
|
|
|
5266 /**
|
|
|
5267 * @brief Configure the TI1 as Input.
|
|
|
5268 * @param TIMx to select the TIM peripheral.
|
|
|
5269 * @param TIM_ICPolarity : The Input Polarity.
|
|
|
5270 * This parameter can be one of the following values:
|
|
|
5271 * @arg TIM_ICPolarity_Rising
|
|
|
5272 * @arg TIM_ICPolarity_Falling
|
|
|
5273 * @arg TIM_ICPolarity_BothEdge
|
|
|
5274 * @param TIM_ICSelection: specifies the input to be used.
|
|
|
5275 * This parameter can be one of the following values:
|
|
|
5276 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
|
|
|
5277 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
|
|
|
5278 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
|
|
|
5279 * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
|
|
5280 * This parameter must be a value between 0x00 and 0x0F.
|
|
|
5281 * @retval None
|
|
|
5282 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
|
|
|
5283 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
|
|
|
5284 * protected against un-initialized filter and polarity values.
|
|
|
5285 */
|
|
|
5286 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
|
|
|
5287 uint32_t TIM_ICFilter)
|
|
|
5288 {
|
|
|
5289 uint32_t tmpccmr1 = 0;
|
|
|
5290 uint32_t tmpccer = 0;
|
|
|
5291
|
|
|
5292 /* Disable the Channel 1: Reset the CC1E Bit */
|
|
|
5293 TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
|
5294 tmpccmr1 = TIMx->CCMR1;
|
|
|
5295 tmpccer = TIMx->CCER;
|
|
|
5296
|
|
|
5297 /* Select the Input */
|
|
|
5298 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
|
|
|
5299 {
|
|
|
5300 tmpccmr1 &= ~TIM_CCMR1_CC1S;
|
|
|
5301 tmpccmr1 |= TIM_ICSelection;
|
|
|
5302 }
|
|
|
5303 else
|
|
|
5304 {
|
|
|
5305 tmpccmr1 |= TIM_CCMR1_CC1S_0;
|
|
|
5306 }
|
|
|
5307
|
|
|
5308 /* Set the filter */
|
|
|
5309 tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
|
5310 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
|
|
|
5311
|
|
|
5312 /* Select the Polarity and set the CC1E Bit */
|
|
|
5313 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
|
5314 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
|
|
|
5315
|
|
|
5316 /* Write to TIMx CCMR1 and CCER registers */
|
|
|
5317 TIMx->CCMR1 = tmpccmr1;
|
|
|
5318 TIMx->CCER = tmpccer;
|
|
|
5319 }
|
|
|
5320
|
|
|
5321 /**
|
|
|
5322 * @brief Configure the Polarity and Filter for TI1.
|
|
|
5323 * @param TIMx to select the TIM peripheral.
|
|
|
5324 * @param TIM_ICPolarity : The Input Polarity.
|
|
|
5325 * This parameter can be one of the following values:
|
|
|
5326 * @arg TIM_ICPolarity_Rising
|
|
|
5327 * @arg TIM_ICPolarity_Falling
|
|
|
5328 * @arg TIM_ICPolarity_BothEdge
|
|
|
5329 * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
|
|
5330 * This parameter must be a value between 0x00 and 0x0F.
|
|
|
5331 * @retval None
|
|
|
5332 */
|
|
|
5333 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
|
5334 {
|
|
|
5335 uint32_t tmpccmr1 = 0;
|
|
|
5336 uint32_t tmpccer = 0;
|
|
|
5337
|
|
|
5338 /* Disable the Channel 1: Reset the CC1E Bit */
|
|
|
5339 tmpccer = TIMx->CCER;
|
|
|
5340 TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
|
5341 tmpccmr1 = TIMx->CCMR1;
|
|
|
5342
|
|
|
5343 /* Set the filter */
|
|
|
5344 tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
|
5345 tmpccmr1 |= (TIM_ICFilter << 4);
|
|
|
5346
|
|
|
5347 /* Select the Polarity and set the CC1E Bit */
|
|
|
5348 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
|
5349 tmpccer |= TIM_ICPolarity;
|
|
|
5350
|
|
|
5351 /* Write to TIMx CCMR1 and CCER registers */
|
|
|
5352 TIMx->CCMR1 = tmpccmr1;
|
|
|
5353 TIMx->CCER = tmpccer;
|
|
|
5354 }
|
|
|
5355
|
|
|
5356 /**
|
|
|
5357 * @brief Configure the TI2 as Input.
|
|
|
5358 * @param TIMx to select the TIM peripheral
|
|
|
5359 * @param TIM_ICPolarity : The Input Polarity.
|
|
|
5360 * This parameter can be one of the following values:
|
|
|
5361 * @arg TIM_ICPolarity_Rising
|
|
|
5362 * @arg TIM_ICPolarity_Falling
|
|
|
5363 * @arg TIM_ICPolarity_BothEdge
|
|
|
5364 * @param TIM_ICSelection: specifies the input to be used.
|
|
|
5365 * This parameter can be one of the following values:
|
|
|
5366 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
|
|
|
5367 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
|
|
|
5368 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
|
|
|
5369 * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
|
|
5370 * This parameter must be a value between 0x00 and 0x0F.
|
|
|
5371 * @retval None
|
|
|
5372 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
|
|
|
5373 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
|
|
|
5374 * protected against un-initialized filter and polarity values.
|
|
|
5375 */
|
|
|
5376 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
|
|
|
5377 uint32_t TIM_ICFilter)
|
|
|
5378 {
|
|
|
5379 uint32_t tmpccmr1 = 0;
|
|
|
5380 uint32_t tmpccer = 0;
|
|
|
5381
|
|
|
5382 /* Disable the Channel 2: Reset the CC2E Bit */
|
|
|
5383 TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
|
5384 tmpccmr1 = TIMx->CCMR1;
|
|
|
5385 tmpccer = TIMx->CCER;
|
|
|
5386
|
|
|
5387 /* Select the Input */
|
|
|
5388 tmpccmr1 &= ~TIM_CCMR1_CC2S;
|
|
|
5389 tmpccmr1 |= (TIM_ICSelection << 8);
|
|
|
5390
|
|
|
5391 /* Set the filter */
|
|
|
5392 tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
|
5393 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
|
|
|
5394
|
|
|
5395 /* Select the Polarity and set the CC2E Bit */
|
|
|
5396 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
|
5397 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
|
|
|
5398
|
|
|
5399 /* Write to TIMx CCMR1 and CCER registers */
|
|
|
5400 TIMx->CCMR1 = tmpccmr1 ;
|
|
|
5401 TIMx->CCER = tmpccer;
|
|
|
5402 }
|
|
|
5403
|
|
|
5404 /**
|
|
|
5405 * @brief Configure the Polarity and Filter for TI2.
|
|
|
5406 * @param TIMx to select the TIM peripheral.
|
|
|
5407 * @param TIM_ICPolarity : The Input Polarity.
|
|
|
5408 * This parameter can be one of the following values:
|
|
|
5409 * @arg TIM_ICPolarity_Rising
|
|
|
5410 * @arg TIM_ICPolarity_Falling
|
|
|
5411 * @arg TIM_ICPolarity_BothEdge
|
|
|
5412 * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
|
|
5413 * This parameter must be a value between 0x00 and 0x0F.
|
|
|
5414 * @retval None
|
|
|
5415 */
|
|
|
5416 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
|
5417 {
|
|
|
5418 uint32_t tmpccmr1 = 0;
|
|
|
5419 uint32_t tmpccer = 0;
|
|
|
5420
|
|
|
5421 /* Disable the Channel 2: Reset the CC2E Bit */
|
|
|
5422 TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
|
5423 tmpccmr1 = TIMx->CCMR1;
|
|
|
5424 tmpccer = TIMx->CCER;
|
|
|
5425
|
|
|
5426 /* Set the filter */
|
|
|
5427 tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
|
5428 tmpccmr1 |= (TIM_ICFilter << 12);
|
|
|
5429
|
|
|
5430 /* Select the Polarity and set the CC2E Bit */
|
|
|
5431 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
|
5432 tmpccer |= (TIM_ICPolarity << 4);
|
|
|
5433
|
|
|
5434 /* Write to TIMx CCMR1 and CCER registers */
|
|
|
5435 TIMx->CCMR1 = tmpccmr1 ;
|
|
|
5436 TIMx->CCER = tmpccer;
|
|
|
5437 }
|
|
|
5438
|
|
|
5439 /**
|
|
|
5440 * @brief Configure the TI3 as Input.
|
|
|
5441 * @param TIMx to select the TIM peripheral
|
|
|
5442 * @param TIM_ICPolarity : The Input Polarity.
|
|
|
5443 * This parameter can be one of the following values:
|
|
|
5444 * @arg TIM_ICPolarity_Rising
|
|
|
5445 * @arg TIM_ICPolarity_Falling
|
|
|
5446 * @arg TIM_ICPolarity_BothEdge
|
|
|
5447 * @param TIM_ICSelection: specifies the input to be used.
|
|
|
5448 * This parameter can be one of the following values:
|
|
|
5449 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
|
|
|
5450 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
|
|
|
5451 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
|
|
|
5452 * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
|
|
5453 * This parameter must be a value between 0x00 and 0x0F.
|
|
|
5454 * @retval None
|
|
|
5455 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
|
|
|
5456 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
|
|
|
5457 * protected against un-initialized filter and polarity values.
|
|
|
5458 */
|
|
|
5459 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
|
|
|
5460 uint32_t TIM_ICFilter)
|
|
|
5461 {
|
|
|
5462 uint32_t tmpccmr2 = 0;
|
|
|
5463 uint32_t tmpccer = 0;
|
|
|
5464
|
|
|
5465 /* Disable the Channel 3: Reset the CC3E Bit */
|
|
|
5466 TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
|
5467 tmpccmr2 = TIMx->CCMR2;
|
|
|
5468 tmpccer = TIMx->CCER;
|
|
|
5469
|
|
|
5470 /* Select the Input */
|
|
|
5471 tmpccmr2 &= ~TIM_CCMR2_CC3S;
|
|
|
5472 tmpccmr2 |= TIM_ICSelection;
|
|
|
5473
|
|
|
5474 /* Set the filter */
|
|
|
5475 tmpccmr2 &= ~TIM_CCMR2_IC3F;
|
|
|
5476 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
|
|
|
5477
|
|
|
5478 /* Select the Polarity and set the CC3E Bit */
|
|
|
5479 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
|
|
|
5480 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
|
|
|
5481
|
|
|
5482 /* Write to TIMx CCMR2 and CCER registers */
|
|
|
5483 TIMx->CCMR2 = tmpccmr2;
|
|
|
5484 TIMx->CCER = tmpccer;
|
|
|
5485 }
|
|
|
5486
|
|
|
5487 /**
|
|
|
5488 * @brief Configure the TI4 as Input.
|
|
|
5489 * @param TIMx to select the TIM peripheral
|
|
|
5490 * @param TIM_ICPolarity : The Input Polarity.
|
|
|
5491 * This parameter can be one of the following values:
|
|
|
5492 * @arg TIM_ICPolarity_Rising
|
|
|
5493 * @arg TIM_ICPolarity_Falling
|
|
|
5494 * @arg TIM_ICPolarity_BothEdge
|
|
|
5495 * @param TIM_ICSelection: specifies the input to be used.
|
|
|
5496 * This parameter can be one of the following values:
|
|
|
5497 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
|
|
|
5498 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
|
|
|
5499 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
|
|
|
5500 * @param TIM_ICFilter: Specifies the Input Capture Filter.
|
|
|
5501 * This parameter must be a value between 0x00 and 0x0F.
|
|
|
5502 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
|
|
|
5503 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
|
|
|
5504 * protected against un-initialized filter and polarity values.
|
|
|
5505 * @retval None
|
|
|
5506 */
|
|
|
5507 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
|
|
|
5508 uint32_t TIM_ICFilter)
|
|
|
5509 {
|
|
|
5510 uint32_t tmpccmr2 = 0;
|
|
|
5511 uint32_t tmpccer = 0;
|
|
|
5512
|
|
|
5513 /* Disable the Channel 4: Reset the CC4E Bit */
|
|
|
5514 TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
|
5515 tmpccmr2 = TIMx->CCMR2;
|
|
|
5516 tmpccer = TIMx->CCER;
|
|
|
5517
|
|
|
5518 /* Select the Input */
|
|
|
5519 tmpccmr2 &= ~TIM_CCMR2_CC4S;
|
|
|
5520 tmpccmr2 |= (TIM_ICSelection << 8);
|
|
|
5521
|
|
|
5522 /* Set the filter */
|
|
|
5523 tmpccmr2 &= ~TIM_CCMR2_IC4F;
|
|
|
5524 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
|
|
|
5525
|
|
|
5526 /* Select the Polarity and set the CC4E Bit */
|
|
|
5527 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
|
|
|
5528 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
|
|
|
5529
|
|
|
5530 /* Write to TIMx CCMR2 and CCER registers */
|
|
|
5531 TIMx->CCMR2 = tmpccmr2;
|
|
|
5532 TIMx->CCER = tmpccer ;
|
|
|
5533 }
|
|
|
5534
|
|
|
5535 /**
|
|
|
5536 * @brief Selects the Input Trigger source
|
|
|
5537 * @param TIMx to select the TIM peripheral
|
|
|
5538 * @param InputTriggerSource: The Input Trigger source.
|
|
|
5539 * This parameter can be one of the following values:
|
|
|
5540 * @arg TIM_TS_ITR0: Internal Trigger 0
|
|
|
5541 * @arg TIM_TS_ITR1: Internal Trigger 1
|
|
|
5542 * @arg TIM_TS_ITR2: Internal Trigger 2
|
|
|
5543 * @arg TIM_TS_ITR3: Internal Trigger 3
|
|
|
5544 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
|
|
|
5545 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
|
|
|
5546 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
|
5547 * @arg TIM_TS_ETRF: External Trigger input
|
|
|
5548 * @retval None
|
|
|
5549 */
|
|
|
5550 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
|
|
|
5551 {
|
|
|
5552 uint32_t tmpsmcr = 0;
|
|
|
5553
|
|
|
5554 /* Get the TIMx SMCR register value */
|
|
|
5555 tmpsmcr = TIMx->SMCR;
|
|
|
5556 /* Reset the TS Bits */
|
|
|
5557 tmpsmcr &= ~TIM_SMCR_TS;
|
|
|
5558 /* Set the Input Trigger source and the slave mode*/
|
|
|
5559 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
|
|
|
5560 /* Write to TIMx SMCR */
|
|
|
5561 TIMx->SMCR = tmpsmcr;
|
|
|
5562 }
|
|
|
5563 /**
|
|
|
5564 * @brief Configures the TIMx External Trigger (ETR).
|
|
|
5565 * @param TIMx to select the TIM peripheral
|
|
|
5566 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
|
|
5567 * This parameter can be one of the following values:
|
|
|
5568 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
|
|
|
5569 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
|
|
|
5570 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
|
|
|
5571 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
|
|
|
5572 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
|
|
5573 * This parameter can be one of the following values:
|
|
|
5574 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
|
|
|
5575 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
|
|
|
5576 * @param ExtTRGFilter: External Trigger Filter.
|
|
|
5577 * This parameter must be a value between 0x00 and 0x0F
|
|
|
5578 * @retval None
|
|
|
5579 */
|
|
|
5580 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
|
5581 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
|
5582 {
|
|
|
5583 uint32_t tmpsmcr = 0;
|
|
|
5584
|
|
|
5585 tmpsmcr = TIMx->SMCR;
|
|
|
5586
|
|
|
5587 /* Reset the ETR Bits */
|
|
|
5588 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
|
5589
|
|
|
5590 /* Set the Prescaler, the Filter value and the Polarity */
|
|
|
5591 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
|
|
|
5592
|
|
|
5593 /* Write to TIMx SMCR */
|
|
|
5594 TIMx->SMCR = tmpsmcr;
|
|
|
5595 }
|
|
|
5596
|
|
|
5597 /**
|
|
|
5598 * @brief Enables or disables the TIM Capture Compare Channel x.
|
|
|
5599 * @param TIMx to select the TIM peripheral
|
|
|
5600 * @param Channel: specifies the TIM Channel
|
|
|
5601 * This parameter can be one of the following values:
|
|
|
5602 * @arg TIM_CHANNEL_1: TIM Channel 1
|
|
|
5603 * @arg TIM_CHANNEL_2: TIM Channel 2
|
|
|
5604 * @arg TIM_CHANNEL_3: TIM Channel 3
|
|
|
5605 * @arg TIM_CHANNEL_4: TIM Channel 4
|
|
|
5606 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
|
|
|
5607 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
|
|
|
5608 * @retval None
|
|
|
5609 */
|
|
|
5610 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
|
|
|
5611 {
|
|
|
5612 uint32_t tmp = 0;
|
|
|
5613
|
|
|
5614 /* Check the parameters */
|
|
|
5615 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
|
5616 assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
5617
|
|
|
5618 tmp = TIM_CCER_CC1E << Channel;
|
|
|
5619
|
|
|
5620 /* Reset the CCxE Bit */
|
|
|
5621 TIMx->CCER &= ~tmp;
|
|
|
5622
|
|
|
5623 /* Set or reset the CCxE Bit */
|
|
|
5624 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
|
|
|
5625 }
|
|
|
5626
|
|
|
5627
|
|
|
5628 /**
|
|
|
5629 * @}
|
|
|
5630 */
|
|
|
5631
|
|
|
5632 #endif /* HAL_TIM_MODULE_ENABLED */
|
|
|
5633 /**
|
|
|
5634 * @}
|
|
|
5635 */
|
|
|
5636
|
|
|
5637 /**
|
|
|
5638 * @}
|
|
|
5639 */
|
|
|
5640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
