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1 /**
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2 ******************************************************************************
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3 * @file stm32l476xx.h
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4 * @author MCD Application Team
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5 * @version V1.0.3
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6 * @date 29-January-2016
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7 * @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File.
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8 *
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9 * This file contains:
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10 * - Data structures and the address mapping for all peripherals
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11 * - Peripheral's registers declarations and bits definition
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12 * - Macros to access peripheral�s registers hardware
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13 *
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14 ******************************************************************************
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15 * @attention
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16 *
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17 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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18 *
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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29 *
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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40 *
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41 ******************************************************************************
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42 */
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43
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44 /** @addtogroup CMSIS_Device
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45 * @{
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46 */
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47
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48 /** @addtogroup stm32l476xx
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49 * @{
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50 */
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51
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52 #ifndef __STM32L476xx_H
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53 #define __STM32L476xx_H
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54
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55 #ifdef __cplusplus
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56 extern "C" {
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57 #endif /* __cplusplus */
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58
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59 /** @addtogroup Configuration_section_for_CMSIS
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60 * @{
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61 */
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62
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63 /**
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64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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65 */
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66 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
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67 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
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68 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
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69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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70 #define __FPU_PRESENT 1 /*!< FPU present */
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71
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72 /**
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73 * @}
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74 */
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75
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76 /** @addtogroup Peripheral_interrupt_number_definition
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77 * @{
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78 */
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79
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80 /**
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81 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
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82 * in @ref Library_configuration_section
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83 */
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84 typedef enum
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85 {
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86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
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87 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
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88 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
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89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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96 /****** STM32 specific Interrupt Numbers **********************************************************************/
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97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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98 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
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99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
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100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
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101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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102 RCC_IRQn = 5, /*!< RCC global Interrupt */
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103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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108 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
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109 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
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110 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
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111 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
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112 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
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113 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
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114 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
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115 ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */
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116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
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117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
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118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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121 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
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122 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
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123 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
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124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
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135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
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136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
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137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
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139 DFSDM3_IRQn = 42, /*!< SD Filter 3 global Interrupt */
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140 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
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141 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
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142 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
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143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
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144 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
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145 FMC_IRQn = 48, /*!< FMC global Interrupt */
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146 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
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147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
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150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
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151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
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152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
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153 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
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154 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
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155 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
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156 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
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157 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
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158 DFSDM0_IRQn = 61, /*!< SD Filter 0 global Interrupt */
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159 DFSDM1_IRQn = 62, /*!< SD Filter 1 global Interrupt */
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160 DFSDM2_IRQn = 63, /*!< SD Filter 2 global Interrupt */
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161 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
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162 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
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163 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
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164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
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165 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
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166 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
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167 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
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168 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
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169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
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170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
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171 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
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172 SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
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173 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
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174 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
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175 LCD_IRQn = 78, /*!< LCD global interrupt */
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176 RNG_IRQn = 80, /*!< RNG global interrupt */
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177 FPU_IRQn = 81 /*!< FPU global interrupt */
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178 } IRQn_Type;
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179
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180 /**
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181 * @}
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182 */
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183
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184 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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185 #include "system_stm32l4xx.h"
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186 #include <stdint.h>
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187
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188 /** @addtogroup Peripheral_registers_structures
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189 * @{
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190 */
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191
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192 /**
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193 * @brief Analog to Digital Converter
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194 */
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195
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196 typedef struct
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197 {
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198 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
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199 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
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200 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
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201 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
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202 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
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203 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
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204 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
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205 uint32_t RESERVED1; /*!< Reserved, 0x1C */
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206 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
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207 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
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208 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
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209 uint32_t RESERVED2; /*!< Reserved, 0x2C */
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210 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
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211 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
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212 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
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213 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
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214 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
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215 uint32_t RESERVED3; /*!< Reserved, 0x44 */
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216 uint32_t RESERVED4; /*!< Reserved, 0x48 */
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217 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
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218 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
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219 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
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220 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
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221 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
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222 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
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223 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
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224 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
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225 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
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226 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
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227 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
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228 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
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229 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
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230 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
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231 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
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232 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
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233 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
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234 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
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235
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236 } ADC_TypeDef;
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237
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238 typedef struct
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239 {
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240 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
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241 uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
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242 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
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243 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
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244 } ADC_Common_TypeDef;
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245
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246
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247 /**
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248 * @brief Controller Area Network TxMailBox
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249 */
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250
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251 typedef struct
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252 {
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253 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
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254 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
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255 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
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256 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
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257 } CAN_TxMailBox_TypeDef;
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258
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259 /**
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260 * @brief Controller Area Network FIFOMailBox
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261 */
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262
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263 typedef struct
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264 {
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265 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
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266 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
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267 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
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268 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
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269 } CAN_FIFOMailBox_TypeDef;
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270
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271 /**
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272 * @brief Controller Area Network FilterRegister
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273 */
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274
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275 typedef struct
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276 {
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277 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
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278 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
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279 } CAN_FilterRegister_TypeDef;
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280
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281 /**
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282 * @brief Controller Area Network
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283 */
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284
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285 typedef struct
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286 {
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287 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
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288 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
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289 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
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290 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
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291 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
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292 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
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293 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
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294 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
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295 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
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296 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
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297 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
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298 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
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299 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
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300 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
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301 uint32_t RESERVED2; /*!< Reserved, 0x208 */
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302 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
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303 uint32_t RESERVED3; /*!< Reserved, 0x210 */
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304 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
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305 uint32_t RESERVED4; /*!< Reserved, 0x218 */
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306 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
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307 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
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308 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
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309 } CAN_TypeDef;
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310
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311
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312 /**
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313 * @brief Comparator
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314 */
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315
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316 typedef struct
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317 {
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318 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
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319 } COMP_TypeDef;
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320
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321 typedef struct
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322 {
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323 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
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324 } COMP_Common_TypeDef;
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325
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326 /**
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327 * @brief CRC calculation unit
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328 */
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329
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330 typedef struct
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331 {
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332 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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333 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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334 uint8_t RESERVED0; /*!< Reserved, 0x05 */
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335 uint16_t RESERVED1; /*!< Reserved, 0x06 */
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336 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
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337 uint32_t RESERVED2; /*!< Reserved, 0x0C */
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338 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
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339 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
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340 } CRC_TypeDef;
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341
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342 /**
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343 * @brief Digital to Analog Converter
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344 */
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345
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346 typedef struct
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347 {
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348 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
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349 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
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350 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
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351 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
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352 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
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353 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
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354 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
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355 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
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356 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
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357 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
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358 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
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359 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
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360 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
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361 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
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362 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
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363 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
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364 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
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365 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
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366 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
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367 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
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368 } DAC_TypeDef;
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369
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370 /**
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371 * @brief DFSDM module registers
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372 */
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373 typedef struct
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374 {
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375 __IO uint32_t CR1; /*!< DFSDM control register1, Address offset: 0x100 */
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376 __IO uint32_t CR2; /*!< DFSDM control register2, Address offset: 0x104 */
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377 __IO uint32_t ISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
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378 __IO uint32_t ICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
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379 __IO uint32_t JCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
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380 __IO uint32_t FCR; /*!< DFSDM filter control register, Address offset: 0x114 */
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381 __IO uint32_t JDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
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382 __IO uint32_t RDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
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383 __IO uint32_t AWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
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384 __IO uint32_t AWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
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385 __IO uint32_t AWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
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386 __IO uint32_t AWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
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387 __IO uint32_t EXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
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388 __IO uint32_t EXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
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389 __IO uint32_t CNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
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390 } DFSDM_Filter_TypeDef;
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391
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392 /**
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393 * @brief DFSDM channel configuration registers
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394 */
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395 typedef struct
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396 {
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397 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
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398 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
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399 __IO uint32_t AWSCDR; /*!< DFSDM channel analog watchdog and
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400 short circuit detector register, Address offset: 0x08 */
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401 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
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402 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
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403 } DFSDM_Channel_TypeDef;
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404
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405 /**
|
|
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406 * @brief Debug MCU
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407 */
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408
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409 typedef struct
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410 {
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411 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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412 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
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413 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
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414 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
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415 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
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416 } DBGMCU_TypeDef;
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417
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418
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|
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419 /**
|
|
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420 * @brief DMA Controller
|
|
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421 */
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422
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|
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423 typedef struct
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|
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424 {
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|
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425 __IO uint32_t CCR; /*!< DMA channel x configuration register */
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426 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
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|
|
427 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
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428 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
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|
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429 } DMA_Channel_TypeDef;
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|
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430
|
|
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431 typedef struct
|
|
|
432 {
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|
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433 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
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|
434 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
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|
|
435 } DMA_TypeDef;
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|
436
|
|
|
437 typedef struct
|
|
|
438 {
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|
|
439 __IO uint32_t CSELR; /*!< DMA channel selection register */
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|
|
440 } DMA_Request_TypeDef;
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|
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441
|
|
|
442 /* Legacy define */
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|
|
443 #define DMA_request_TypeDef DMA_Request_TypeDef
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|
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444
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|
|
445 /**
|
|
|
446 * @brief External Interrupt/Event Controller
|
|
|
447 */
|
|
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448
|
|
|
449 typedef struct
|
|
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450 {
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|
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451 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
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|
|
452 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
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|
|
453 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
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|
|
454 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
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|
|
455 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
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|
|
456 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
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|
|
457 uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
|
|
458 uint32_t RESERVED2; /*!< Reserved, 0x1C */
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|
|
459 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
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|
|
460 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
|
|
|
461 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
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|
|
462 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
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|
|
463 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
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|
|
464 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
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|
|
465 } EXTI_TypeDef;
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|
|
466
|
|
|
467
|
|
|
468 /**
|
|
|
469 * @brief Firewall
|
|
|
470 */
|
|
|
471
|
|
|
472 typedef struct
|
|
|
473 {
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|
|
474 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
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|
|
475 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
|
|
|
476 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
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|
|
477 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
|
|
|
478 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
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|
|
479 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
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|
|
480 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
|
|
|
481 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
|
|
|
482 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
|
|
|
483 } FIREWALL_TypeDef;
|
|
|
484
|
|
|
485
|
|
|
486 /**
|
|
|
487 * @brief FLASH Registers
|
|
|
488 */
|
|
|
489
|
|
|
490 typedef struct
|
|
|
491 {
|
|
|
492 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
|
|
|
493 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
|
|
|
494 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
|
|
|
495 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
|
|
|
496 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
|
|
|
497 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
|
|
|
498 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
|
|
|
499 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
|
|
|
500 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
|
|
|
501 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
|
|
|
502 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
|
|
|
503 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
|
|
|
504 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
|
|
|
505 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
|
|
|
506 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
|
|
|
507 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
|
|
|
508 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
|
|
|
509 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
|
|
|
510 } FLASH_TypeDef;
|
|
|
511
|
|
|
512
|
|
|
513 /**
|
|
|
514 * @brief Flexible Memory Controller
|
|
|
515 */
|
|
|
516
|
|
|
517 typedef struct
|
|
|
518 {
|
|
|
519 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
|
|
|
520 } FMC_Bank1_TypeDef;
|
|
|
521
|
|
|
522 /**
|
|
|
523 * @brief Flexible Memory Controller Bank1E
|
|
|
524 */
|
|
|
525
|
|
|
526 typedef struct
|
|
|
527 {
|
|
|
528 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
|
|
|
529 } FMC_Bank1E_TypeDef;
|
|
|
530
|
|
|
531 /**
|
|
|
532 * @brief Flexible Memory Controller Bank3
|
|
|
533 */
|
|
|
534
|
|
|
535 typedef struct
|
|
|
536 {
|
|
|
537 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
|
|
|
538 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
|
|
|
539 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
|
|
|
540 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
|
|
|
541 uint32_t RESERVED0; /*!< Reserved, 0x90 */
|
|
|
542 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
|
|
|
543 } FMC_Bank3_TypeDef;
|
|
|
544
|
|
|
545 /**
|
|
|
546 * @brief General Purpose I/O
|
|
|
547 */
|
|
|
548
|
|
|
549 typedef struct
|
|
|
550 {
|
|
|
551 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
|
|
|
552 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
|
|
|
553 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
|
|
|
554 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
|
|
555 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
|
|
556 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
|
|
557 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
|
|
|
558 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
|
|
559 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
|
|
560 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
|
|
|
561 __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */
|
|
|
562
|
|
|
563 } GPIO_TypeDef;
|
|
|
564
|
|
|
565
|
|
|
566 /**
|
|
|
567 * @brief Inter-integrated Circuit Interface
|
|
|
568 */
|
|
|
569
|
|
|
570 typedef struct
|
|
|
571 {
|
|
|
572 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
|
|
|
573 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
|
|
|
574 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
|
|
|
575 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
|
|
|
576 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
|
|
|
577 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
|
|
|
578 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
|
|
|
579 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
|
|
|
580 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
|
|
|
581 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
|
|
|
582 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
|
|
|
583 } I2C_TypeDef;
|
|
|
584
|
|
|
585 /**
|
|
|
586 * @brief Independent WATCHDOG
|
|
|
587 */
|
|
|
588
|
|
|
589 typedef struct
|
|
|
590 {
|
|
|
591 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
|
|
|
592 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
|
|
|
593 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
|
|
|
594 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
|
|
|
595 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
|
|
|
596 } IWDG_TypeDef;
|
|
|
597
|
|
|
598 /**
|
|
|
599 * @brief LCD
|
|
|
600 */
|
|
|
601
|
|
|
602 typedef struct
|
|
|
603 {
|
|
|
604 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
|
|
|
605 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
|
|
|
606 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
|
|
|
607 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
|
|
|
608 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
|
|
|
609 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
|
|
|
610 } LCD_TypeDef;
|
|
|
611
|
|
|
612 /**
|
|
|
613 * @brief LPTIMER
|
|
|
614 */
|
|
|
615 typedef struct
|
|
|
616 {
|
|
|
617 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
|
|
|
618 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
|
|
|
619 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
|
|
|
620 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
|
|
|
621 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
|
|
|
622 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
|
|
|
623 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
|
|
|
624 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
|
|
|
625 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
|
|
|
626 } LPTIM_TypeDef;
|
|
|
627
|
|
|
628
|
|
|
629 /**
|
|
|
630 * @brief Operational Amplifier (OPAMP)
|
|
|
631 */
|
|
|
632
|
|
|
633 typedef struct
|
|
|
634 {
|
|
|
635 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
|
|
|
636 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
|
|
|
637 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
|
|
|
638 } OPAMP_TypeDef;
|
|
|
639
|
|
|
640 typedef struct
|
|
|
641 {
|
|
|
642 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
|
|
|
643 } OPAMP_Common_TypeDef;
|
|
|
644
|
|
|
645 /**
|
|
|
646 * @brief Power Control
|
|
|
647 */
|
|
|
648
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649 typedef struct
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650 {
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651 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
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652 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
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653 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
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654 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
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655 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
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|
656 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
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657 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
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658 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
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659 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
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660 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
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661 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
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662 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
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663 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
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664 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
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|
665 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
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666 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
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|
667 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
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668 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
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|
|
669 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
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|
670 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
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|
|
671 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
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|
672 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
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673 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
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674 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
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675 } PWR_TypeDef;
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676
|
|
|
677
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678 /**
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679 * @brief QUAD Serial Peripheral Interface
|
|
|
680 */
|
|
|
681
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|
682 typedef struct
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683 {
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684 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
|
|
|
685 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
|
|
|
686 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
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687 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
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|
|
688 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
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|
|
689 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
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|
|
690 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
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|
|
691 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
|
|
|
692 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
|
|
|
693 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
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|
|
694 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
|
|
|
695 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
|
|
|
696 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
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|
|
697 } QUADSPI_TypeDef;
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|
|
698
|
|
|
699
|
|
|
700 /**
|
|
|
701 * @brief Reset and Clock Control
|
|
|
702 */
|
|
|
703
|
|
|
704 typedef struct
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|
705 {
|
|
|
706 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
|
|
|
707 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
|
|
|
708 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
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|
|
709 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
|
|
|
710 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
|
|
|
711 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
|
|
|
712 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
|
|
|
713 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
|
|
|
714 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
|
|
|
715 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
|
|
|
716 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
|
|
|
717 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
|
|
|
718 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
|
|
|
719 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
|
|
|
720 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
|
|
|
721 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
|
|
|
722 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
|
|
|
723 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
|
|
|
724 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
|
|
|
725 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
|
|
|
726 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
|
|
|
727 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
|
|
|
728 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
|
|
|
729 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
|
|
|
730 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
|
|
|
731 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
|
|
|
732 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
|
|
|
733 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
|
|
|
734 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
|
|
|
735 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
|
|
|
736 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
|
|
|
737 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
|
|
|
738 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
|
|
|
739 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
|
|
|
740 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
|
|
|
741 __IO uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
|
|
|
742 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
|
|
|
743 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
|
|
|
744 } RCC_TypeDef;
|
|
|
745
|
|
|
746 /**
|
|
|
747 * @brief Real-Time Clock
|
|
|
748 */
|
|
|
749
|
|
|
750 typedef struct
|
|
|
751 {
|
|
|
752 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
|
|
|
753 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
|
|
|
754 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
|
|
|
755 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
|
|
|
756 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
|
|
|
757 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
|
|
|
758 uint32_t reserved; /*!< Reserved */
|
|
|
759 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
|
|
|
760 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
|
|
|
761 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
|
|
|
762 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
|
|
|
763 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
|
|
|
764 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
|
|
|
765 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
|
|
|
766 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
|
|
|
767 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
|
|
|
768 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
|
|
|
769 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
|
|
|
770 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
|
|
|
771 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
|
|
|
772 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
|
|
|
773 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
|
|
|
774 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
|
|
775 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
|
|
776 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
|
|
777 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
|
|
|
778 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
|
|
|
779 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
|
|
|
780 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
|
|
|
781 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
|
|
|
782 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
|
|
|
783 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
|
|
|
784 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
|
|
|
785 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
|
|
786 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
|
|
787 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
|
|
788 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
|
|
|
789 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
|
|
|
790 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
|
|
|
791 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
|
|
|
792 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
|
|
|
793 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
|
|
|
794 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
|
|
|
795 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
|
|
|
796 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
|
|
|
797 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
|
|
|
798 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
|
|
|
799 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
|
|
|
800 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
|
|
|
801 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
|
|
|
802 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
|
|
|
803 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
|
|
|
804 } RTC_TypeDef;
|
|
|
805
|
|
|
806
|
|
|
807 /**
|
|
|
808 * @brief Serial Audio Interface
|
|
|
809 */
|
|
|
810
|
|
|
811 typedef struct
|
|
|
812 {
|
|
|
813 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
|
|
|
814 } SAI_TypeDef;
|
|
|
815
|
|
|
816 typedef struct
|
|
|
817 {
|
|
|
818 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
|
|
|
819 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
|
|
|
820 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
|
|
|
821 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
|
|
|
822 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
|
|
|
823 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
|
|
|
824 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
|
|
|
825 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
|
|
|
826 } SAI_Block_TypeDef;
|
|
|
827
|
|
|
828
|
|
|
829 /**
|
|
|
830 * @brief Secure digital input/output Interface
|
|
|
831 */
|
|
|
832
|
|
|
833 typedef struct
|
|
|
834 {
|
|
|
835 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
|
|
|
836 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
|
|
|
837 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
|
|
|
838 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
|
|
|
839 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
|
|
|
840 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
|
|
|
841 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
|
|
|
842 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
|
|
|
843 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
|
|
|
844 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
|
|
|
845 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
|
|
|
846 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
|
|
|
847 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
|
|
|
848 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
|
|
|
849 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
|
|
|
850 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
|
|
|
851 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
|
|
|
852 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
|
|
|
853 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
|
|
|
854 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
|
|
|
855 } SDMMC_TypeDef;
|
|
|
856
|
|
|
857
|
|
|
858 /**
|
|
|
859 * @brief Serial Peripheral Interface
|
|
|
860 */
|
|
|
861
|
|
|
862 typedef struct
|
|
|
863 {
|
|
|
864 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
|
|
|
865 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
|
|
866 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
|
|
867 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
|
|
868 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
|
|
|
869 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
|
|
|
870 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
|
|
|
871 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
|
|
|
872 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
|
|
|
873 } SPI_TypeDef;
|
|
|
874
|
|
|
875
|
|
|
876 /**
|
|
|
877 * @brief Single Wire Protocol Master Interface SPWMI
|
|
|
878 */
|
|
|
879
|
|
|
880 typedef struct
|
|
|
881 {
|
|
|
882 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
|
|
|
883 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
|
|
|
884 uint32_t RESERVED1; /*!< Reserved, 0x08 */
|
|
|
885 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
|
|
|
886 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
|
|
|
887 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
|
|
|
888 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
|
|
|
889 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
|
|
|
890 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
|
|
|
891 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
|
|
|
892 } SWPMI_TypeDef;
|
|
|
893
|
|
|
894
|
|
|
895 /**
|
|
|
896 * @brief System configuration controller
|
|
|
897 */
|
|
|
898
|
|
|
899 typedef struct
|
|
|
900 {
|
|
|
901 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
|
|
|
902 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
|
|
|
903 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
|
|
|
904 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
|
|
|
905 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
|
|
|
906 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
|
|
|
907 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
|
|
|
908 } SYSCFG_TypeDef;
|
|
|
909
|
|
|
910
|
|
|
911 /**
|
|
|
912 * @brief TIM
|
|
|
913 */
|
|
|
914
|
|
|
915 typedef struct
|
|
|
916 {
|
|
|
917 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
|
|
|
918 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
|
|
|
919 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
|
|
|
920 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
|
|
|
921 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
|
|
|
922 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
|
|
|
923 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
|
|
|
924 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
|
|
|
925 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
|
|
|
926 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
|
|
|
927 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
|
|
|
928 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
|
|
|
929 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
|
|
|
930 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
|
|
|
931 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
|
|
|
932 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
|
|
|
933 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
|
|
|
934 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
|
|
|
935 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
|
|
|
936 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
|
|
|
937 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
|
|
|
938 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
|
|
|
939 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
|
|
|
940 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
|
|
|
941 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
|
|
|
942 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
|
|
|
943 } TIM_TypeDef;
|
|
|
944
|
|
|
945
|
|
|
946 /**
|
|
|
947 * @brief Touch Sensing Controller (TSC)
|
|
|
948 */
|
|
|
949
|
|
|
950 typedef struct
|
|
|
951 {
|
|
|
952 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
|
|
|
953 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
|
|
|
954 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
|
|
|
955 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
|
|
|
956 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
|
|
|
957 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
|
|
|
958 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
|
|
|
959 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
|
|
|
960 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
|
|
|
961 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
|
|
|
962 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
|
|
|
963 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
|
|
|
964 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
|
|
|
965 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
|
|
|
966 } TSC_TypeDef;
|
|
|
967
|
|
|
968 /**
|
|
|
969 * @brief Universal Synchronous Asynchronous Receiver Transmitter
|
|
|
970 */
|
|
|
971
|
|
|
972 typedef struct
|
|
|
973 {
|
|
|
974 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
|
|
|
975 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
|
|
|
976 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
|
|
|
977 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
|
|
|
978 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
|
|
|
979 uint16_t RESERVED2; /*!< Reserved, 0x12 */
|
|
|
980 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
|
|
|
981 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
|
|
|
982 uint16_t RESERVED3; /*!< Reserved, 0x1A */
|
|
|
983 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
|
|
|
984 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
|
|
|
985 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
|
|
|
986 uint16_t RESERVED4; /*!< Reserved, 0x26 */
|
|
|
987 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
|
|
|
988 uint16_t RESERVED5; /*!< Reserved, 0x2A */
|
|
|
989 } USART_TypeDef;
|
|
|
990
|
|
|
991 /**
|
|
|
992 * @brief VREFBUF
|
|
|
993 */
|
|
|
994
|
|
|
995 typedef struct
|
|
|
996 {
|
|
|
997 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
|
|
|
998 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
|
|
|
999 } VREFBUF_TypeDef;
|
|
|
1000
|
|
|
1001 /**
|
|
|
1002 * @brief Window WATCHDOG
|
|
|
1003 */
|
|
|
1004
|
|
|
1005 typedef struct
|
|
|
1006 {
|
|
|
1007 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
|
|
|
1008 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
|
|
|
1009 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
|
|
|
1010 } WWDG_TypeDef;
|
|
|
1011
|
|
|
1012 /**
|
|
|
1013 * @brief RNG
|
|
|
1014 */
|
|
|
1015
|
|
|
1016 typedef struct
|
|
|
1017 {
|
|
|
1018 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
|
|
|
1019 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
|
|
|
1020 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
|
|
|
1021 } RNG_TypeDef;
|
|
|
1022
|
|
|
1023 /**
|
|
|
1024 * @brief USB_OTG_Core_register
|
|
|
1025 */
|
|
|
1026 typedef struct
|
|
|
1027 {
|
|
|
1028 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
|
|
|
1029 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
|
|
|
1030 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
|
|
|
1031 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
|
|
|
1032 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
|
|
|
1033 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
|
|
|
1034 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
|
|
|
1035 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
|
|
|
1036 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
|
|
|
1037 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
|
|
|
1038 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
|
|
|
1039 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
|
|
|
1040 uint32_t Reserved30[2]; /* Reserved 030h*/
|
|
|
1041 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
|
|
|
1042 __IO uint32_t CID; /* User ID Register 03Ch*/
|
|
|
1043 uint32_t Reserved5[3]; /* Reserved 040h-048h*/
|
|
|
1044 __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
|
|
|
1045 uint32_t Reserved6; /* Reserved 050h*/
|
|
|
1046 __IO uint32_t GLPMCFG; /* LPM Register 054h*/
|
|
|
1047 __IO uint32_t GPWRDN; /* Power Down Register 058h*/
|
|
|
1048 __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
|
|
|
1049 __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
|
|
|
1050 uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
|
|
|
1051 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
|
|
|
1052 __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
|
|
|
1053 } USB_OTG_GlobalTypeDef;
|
|
|
1054
|
|
|
1055 /**
|
|
|
1056 * @brief USB_OTG_device_Registers
|
|
|
1057 */
|
|
|
1058 typedef struct
|
|
|
1059 {
|
|
|
1060 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
|
|
|
1061 __IO uint32_t DCTL; /* dev Control Register 804h*/
|
|
|
1062 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
|
|
|
1063 uint32_t Reserved0C; /* Reserved 80Ch*/
|
|
|
1064 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
|
|
|
1065 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
|
|
|
1066 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
|
|
|
1067 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
|
|
|
1068 uint32_t Reserved20; /* Reserved 820h*/
|
|
|
1069 uint32_t Reserved9; /* Reserved 824h*/
|
|
|
1070 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
|
|
|
1071 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
|
|
|
1072 __IO uint32_t DTHRCTL; /* dev thr 830h*/
|
|
|
1073 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
|
|
|
1074 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
|
|
|
1075 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
|
|
|
1076 uint32_t Reserved40; /* dedicated EP mask 840h*/
|
|
|
1077 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
|
|
|
1078 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
|
|
|
1079 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
|
|
|
1080 } USB_OTG_DeviceTypeDef;
|
|
|
1081
|
|
|
1082 /**
|
|
|
1083 * @brief USB_OTG_IN_Endpoint-Specific_Register
|
|
|
1084 */
|
|
|
1085 typedef struct
|
|
|
1086 {
|
|
|
1087 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
|
|
|
1088 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
|
|
|
1089 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
|
|
|
1090 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
|
|
|
1091 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
|
|
|
1092 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
|
|
|
1093 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
|
|
|
1094 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
|
|
|
1095 } USB_OTG_INEndpointTypeDef;
|
|
|
1096
|
|
|
1097 /**
|
|
|
1098 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
|
|
|
1099 */
|
|
|
1100 typedef struct
|
|
|
1101 {
|
|
|
1102 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
|
|
|
1103 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
|
|
|
1104 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
|
|
|
1105 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
|
|
|
1106 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
|
|
|
1107 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
|
|
|
1108 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
|
|
|
1109 } USB_OTG_OUTEndpointTypeDef;
|
|
|
1110
|
|
|
1111 /**
|
|
|
1112 * @brief USB_OTG_Host_Mode_Register_Structures
|
|
|
1113 */
|
|
|
1114 typedef struct
|
|
|
1115 {
|
|
|
1116 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
|
|
|
1117 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
|
|
|
1118 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
|
|
|
1119 uint32_t Reserved40C; /* Reserved 40Ch*/
|
|
|
1120 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
|
|
|
1121 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
|
|
|
1122 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
|
|
|
1123 } USB_OTG_HostTypeDef;
|
|
|
1124
|
|
|
1125 /**
|
|
|
1126 * @brief USB_OTG_Host_Channel_Specific_Registers
|
|
|
1127 */
|
|
|
1128 typedef struct
|
|
|
1129 {
|
|
|
1130 __IO uint32_t HCCHAR;
|
|
|
1131 __IO uint32_t HCSPLT;
|
|
|
1132 __IO uint32_t HCINT;
|
|
|
1133 __IO uint32_t HCINTMSK;
|
|
|
1134 __IO uint32_t HCTSIZ;
|
|
|
1135 __IO uint32_t HCDMA;
|
|
|
1136 uint32_t Reserved[2];
|
|
|
1137 } USB_OTG_HostChannelTypeDef;
|
|
|
1138
|
|
|
1139 /**
|
|
|
1140 * @}
|
|
|
1141 */
|
|
|
1142
|
|
|
1143 /** @addtogroup Peripheral_memory_map
|
|
|
1144 * @{
|
|
|
1145 */
|
|
|
1146 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
|
|
|
1147 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address*/
|
|
|
1148 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
|
|
|
1149 #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
|
|
|
1150 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address*/
|
|
|
1151 #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
|
|
|
1152 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
|
|
|
1153 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
|
|
|
1154 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
|
|
|
1155 #define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
|
|
|
1156
|
|
|
1157 /* Legacy defines */
|
|
|
1158 #define SRAM_BASE SRAM1_BASE
|
|
|
1159 #define SRAM_BB_BASE SRAM1_BB_BASE
|
|
|
1160
|
|
|
1161 #define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
|
|
|
1162 #define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
|
|
|
1163
|
|
|
1164 /*!< Peripheral memory map */
|
|
|
1165 #define APB1PERIPH_BASE PERIPH_BASE
|
|
|
1166 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
|
|
|
1167 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
|
|
|
1168 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
|
|
|
1169
|
|
|
1170 #define FMC_BANK1 FMC_BASE
|
|
|
1171 #define FMC_BANK1_1 FMC_BANK1
|
|
|
1172 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
|
|
|
1173 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
|
|
|
1174 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
|
|
|
1175 #define FMC_BANK3 (FMC_BASE + 0x20000000U)
|
|
|
1176
|
|
|
1177 /*!< APB1 peripherals */
|
|
|
1178 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
|
|
|
1179 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
|
|
|
1180 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
|
|
|
1181 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
|
|
|
1182 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
|
|
|
1183 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
|
|
|
1184 #define LCD_BASE (APB1PERIPH_BASE + 0x2400U)
|
|
|
1185 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
|
|
|
1186 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
|
|
|
1187 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
|
|
|
1188 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
|
|
|
1189 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
|
|
|
1190 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
|
|
|
1191 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
|
|
|
1192 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
|
|
|
1193 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
|
|
|
1194 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
|
|
|
1195 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
|
|
|
1196 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
|
|
|
1197 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
|
|
|
1198 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
|
|
|
1199 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
|
|
|
1200 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
|
|
|
1201 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
|
|
|
1202 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
|
|
|
1203 #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
|
|
|
1204 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
|
|
|
1205 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
|
|
|
1206 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
|
|
|
1207 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
|
|
|
1208
|
|
|
1209
|
|
|
1210 /*!< APB2 peripherals */
|
|
|
1211 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
|
|
|
1212 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
|
|
|
1213 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
|
|
|
1214 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
|
|
|
1215 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
|
|
|
1216 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
|
|
|
1217 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
|
|
|
1218 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
|
|
|
1219 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
|
|
|
1220 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
|
|
|
1221 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
|
|
|
1222 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
|
|
|
1223 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
|
|
|
1224 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
|
|
|
1225 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
|
|
|
1226 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
|
|
|
1227 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
|
|
|
1228 #define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
|
|
|
1229 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
|
|
|
1230 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
|
|
|
1231 #define DFSDM_BASE (APB2PERIPH_BASE + 0x6000U)
|
|
|
1232 #define DFSDM_Channel0_BASE (DFSDM_BASE + 0x00)
|
|
|
1233 #define DFSDM_Channel1_BASE (DFSDM_BASE + 0x20)
|
|
|
1234 #define DFSDM_Channel2_BASE (DFSDM_BASE + 0x40)
|
|
|
1235 #define DFSDM_Channel3_BASE (DFSDM_BASE + 0x60)
|
|
|
1236 #define DFSDM_Channel4_BASE (DFSDM_BASE + 0x80)
|
|
|
1237 #define DFSDM_Channel5_BASE (DFSDM_BASE + 0xA0)
|
|
|
1238 #define DFSDM_Channel6_BASE (DFSDM_BASE + 0xC0)
|
|
|
1239 #define DFSDM_Channel7_BASE (DFSDM_BASE + 0xE0)
|
|
|
1240 #define DFSDM_Filter0_BASE (DFSDM_BASE + 0x100)
|
|
|
1241 #define DFSDM_Filter1_BASE (DFSDM_BASE + 0x180)
|
|
|
1242 #define DFSDM_Filter2_BASE (DFSDM_BASE + 0x200)
|
|
|
1243 #define DFSDM_Filter3_BASE (DFSDM_BASE + 0x280)
|
|
|
1244
|
|
|
1245 /*!< AHB1 peripherals */
|
|
|
1246 #define DMA1_BASE (AHB1PERIPH_BASE)
|
|
|
1247 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
|
|
|
1248 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
|
|
|
1249 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
|
|
|
1250 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
|
|
|
1251 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
|
|
|
1252
|
|
|
1253
|
|
|
1254 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
|
|
|
1255 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
|
|
|
1256 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
|
|
|
1257 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
|
|
|
1258 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
|
|
|
1259 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
|
|
|
1260 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
|
|
|
1261 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
|
|
|
1262
|
|
|
1263
|
|
|
1264 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
|
|
|
1265 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
|
|
|
1266 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
|
|
|
1267 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
|
|
|
1268 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
|
|
|
1269 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
|
|
|
1270 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
|
|
|
1271 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
|
|
|
1272
|
|
|
1273
|
|
|
1274 /*!< AHB2 peripherals */
|
|
|
1275 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
|
|
|
1276 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
|
|
|
1277 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
|
|
|
1278 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
|
|
|
1279 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
|
|
|
1280 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
|
|
|
1281 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
|
|
|
1282 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
|
|
|
1283
|
|
|
1284 #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
|
|
|
1285
|
|
|
1286 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
|
|
|
1287 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U)
|
|
|
1288 #define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U)
|
|
|
1289 #define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
|
|
|
1290
|
|
|
1291
|
|
|
1292 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
|
|
|
1293
|
|
|
1294 /*!< FMC Banks registers base address */
|
|
|
1295 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
|
|
|
1296 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
|
|
|
1297 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
|
|
|
1298
|
|
|
1299 /* Debug MCU registers base address */
|
|
|
1300 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
|
|
|
1301
|
|
|
1302 /*!< USB registers base address */
|
|
|
1303 #define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
|
|
|
1304
|
|
|
1305 #define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
|
|
|
1306 #define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
|
|
|
1307 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
|
|
|
1308 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
|
|
|
1309 #define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
|
|
|
1310 #define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
|
|
|
1311 #define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
|
|
|
1312 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
|
|
|
1313 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
|
|
|
1314 #define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
|
|
|
1315 #define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
|
|
|
1316 #define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
|
|
|
1317
|
|
|
1318
|
|
|
1319 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
|
|
|
1320 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
|
|
|
1321 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
|
|
|
1322 /**
|
|
|
1323 * @}
|
|
|
1324 */
|
|
|
1325
|
|
|
1326 /** @addtogroup Peripheral_declaration
|
|
|
1327 * @{
|
|
|
1328 */
|
|
|
1329 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
|
|
|
1330 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
|
|
1331 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
|
|
|
1332 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
|
|
|
1333 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
|
|
|
1334 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
|
|
|
1335 #define LCD ((LCD_TypeDef *) LCD_BASE)
|
|
|
1336 #define RTC ((RTC_TypeDef *) RTC_BASE)
|
|
|
1337 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
|
|
1338 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
|
|
1339 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
|
|
|
1340 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
|
|
|
1341 #define USART2 ((USART_TypeDef *) USART2_BASE)
|
|
|
1342 #define USART3 ((USART_TypeDef *) USART3_BASE)
|
|
|
1343 #define UART4 ((USART_TypeDef *) UART4_BASE)
|
|
|
1344 #define UART5 ((USART_TypeDef *) UART5_BASE)
|
|
|
1345 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
|
|
1346 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
|
|
1347 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
|
|
|
1348 #define CAN ((CAN_TypeDef *) CAN1_BASE)
|
|
|
1349 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
|
|
|
1350 #define PWR ((PWR_TypeDef *) PWR_BASE)
|
|
|
1351 #define DAC ((DAC_TypeDef *) DAC1_BASE)
|
|
|
1352 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
|
|
|
1353 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
|
|
|
1354 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
|
|
|
1355 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
|
|
|
1356 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
|
|
|
1357 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
|
|
|
1358 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
|
|
|
1359 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
|
|
|
1360 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
|
|
|
1361
|
|
|
1362 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
|
|
1363 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
|
|
|
1364 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
|
|
|
1365 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
|
|
1366 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
|
|
|
1367 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
|
|
1368 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
|
|
|
1369 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
|
|
|
1370 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
|
|
1371 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
|
|
1372 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
|
|
|
1373 #define USART1 ((USART_TypeDef *) USART1_BASE)
|
|
|
1374 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
|
|
|
1375 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
|
|
|
1376 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
|
|
|
1377 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
|
|
|
1378 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
|
|
|
1379 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
|
|
|
1380 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
|
|
|
1381 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
|
|
|
1382 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
|
|
|
1383 #define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE)
|
|
|
1384 #define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE)
|
|
|
1385 #define DFSDM_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM_Channel2_BASE)
|
|
|
1386 #define DFSDM_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM_Channel3_BASE)
|
|
|
1387 #define DFSDM_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM_Channel4_BASE)
|
|
|
1388 #define DFSDM_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM_Channel5_BASE)
|
|
|
1389 #define DFSDM_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM_Channel6_BASE)
|
|
|
1390 #define DFSDM_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM_Channel7_BASE)
|
|
|
1391 #define DFSDM_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM_Filter0_BASE)
|
|
|
1392 #define DFSDM_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM_Filter1_BASE)
|
|
|
1393 #define DFSDM_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM_Filter2_BASE)
|
|
|
1394 #define DFSDM_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM_Filter3_BASE)
|
|
|
1395 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
|
|
1396 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
|
|
|
1397 #define RCC ((RCC_TypeDef *) RCC_BASE)
|
|
|
1398 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
|
|
1399 #define CRC ((CRC_TypeDef *) CRC_BASE)
|
|
|
1400 #define TSC ((TSC_TypeDef *) TSC_BASE)
|
|
|
1401
|
|
|
1402 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
|
|
1403 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
|
|
1404 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
|
|
1405 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
|
|
1406 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
|
|
1407 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
|
|
|
1408 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
|
|
|
1409 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
|
|
|
1410 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
|
|
1411 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
|
|
|
1412 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
|
|
|
1413 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
|
|
|
1414 #define RNG ((RNG_TypeDef *) RNG_BASE)
|
|
|
1415
|
|
|
1416
|
|
|
1417 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
|
|
|
1418 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
|
|
|
1419 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
|
|
|
1420 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
|
|
|
1421 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
|
|
|
1422 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
|
|
|
1423 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
|
|
|
1424 #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
|
|
|
1425
|
|
|
1426
|
|
|
1427 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
|
|
|
1428 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
|
|
|
1429 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
|
|
|
1430 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
|
|
|
1431 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
|
|
|
1432 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
|
|
|
1433 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
|
|
|
1434 #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
|
|
|
1435
|
|
|
1436
|
|
|
1437 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
|
|
|
1438 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
|
|
|
1439 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
|
|
|
1440
|
|
|
1441 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
|
|
|
1442
|
|
|
1443 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
|
|
1444
|
|
|
1445 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
|
|
|
1446 /**
|
|
|
1447 * @}
|
|
|
1448 */
|
|
|
1449
|
|
|
1450 /** @addtogroup Exported_constants
|
|
|
1451 * @{
|
|
|
1452 */
|
|
|
1453
|
|
|
1454 /** @addtogroup Peripheral_Registers_Bits_Definition
|
|
|
1455 * @{
|
|
|
1456 */
|
|
|
1457
|
|
|
1458 /******************************************************************************/
|
|
|
1459 /* Peripheral Registers_Bits_Definition */
|
|
|
1460 /******************************************************************************/
|
|
|
1461
|
|
|
1462 /******************************************************************************/
|
|
|
1463 /* */
|
|
|
1464 /* Analog to Digital Converter */
|
|
|
1465 /* */
|
|
|
1466 /******************************************************************************/
|
|
|
1467
|
|
|
1468 /*
|
|
|
1469 * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
|
|
|
1470 */
|
|
|
1471 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
|
|
|
1472
|
|
|
1473 /******************** Bit definition for ADC_ISR register *******************/
|
|
|
1474 #define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC ready flag */
|
|
|
1475 #define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling flag */
|
|
|
1476 #define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion flag */
|
|
|
1477 #define ADC_ISR_EOS ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions flag */
|
|
|
1478 #define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< ADC group regular overrun flag */
|
|
|
1479 #define ADC_ISR_JEOC ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion flag */
|
|
|
1480 #define ADC_ISR_JEOS ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions flag */
|
|
|
1481 #define ADC_ISR_AWD1 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 flag */
|
|
|
1482 #define ADC_ISR_AWD2 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 flag */
|
|
|
1483 #define ADC_ISR_AWD3 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 flag */
|
|
|
1484 #define ADC_ISR_JQOVF ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow flag */
|
|
|
1485
|
|
|
1486 /******************** Bit definition for ADC_IER register *******************/
|
|
|
1487 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC ready interrupt */
|
|
|
1488 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling interrupt */
|
|
|
1489 #define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion interrupt */
|
|
|
1490 #define ADC_IER_EOSIE ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions interrupt */
|
|
|
1491 #define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< ADC group regular overrun interrupt */
|
|
|
1492 #define ADC_IER_JEOCIE ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion interrupt */
|
|
|
1493 #define ADC_IER_JEOSIE ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions interrupt */
|
|
|
1494 #define ADC_IER_AWD1IE ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 interrupt */
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|
|
1495 #define ADC_IER_AWD2IE ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 interrupt */
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|
|
1496 #define ADC_IER_AWD3IE ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 interrupt */
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|
|
1497 #define ADC_IER_JQOVFIE ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow interrupt */
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|
|
1498
|
|
|
1499 /* Legacy defines */
|
|
|
1500 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
|
|
|
1501 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
|
|
|
1502 #define ADC_IER_EOC (ADC_IER_EOCIE)
|
|
|
1503 #define ADC_IER_EOS (ADC_IER_EOSIE)
|
|
|
1504 #define ADC_IER_OVR (ADC_IER_OVRIE)
|
|
|
1505 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
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|
|
1506 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
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|
|
1507 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
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|
|
1508 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
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|
|
1509 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
|
|
|
1510 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
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1511
|
|
|
1512 /******************** Bit definition for ADC_CR register ********************/
|
|
|
1513 #define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable */
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|
1514 #define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable */
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|
|
1515 #define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC group regular conversion start */
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|
1516 #define ADC_CR_JADSTART ((uint32_t)0x00000008U) /*!< ADC group injected conversion start */
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|
|
1517 #define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC group regular conversion stop */
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|
|
1518 #define ADC_CR_JADSTP ((uint32_t)0x00000020U) /*!< ADC group injected conversion stop */
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1519 #define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC voltage regulator enable */
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|
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1520 #define ADC_CR_DEEPPWD ((uint32_t)0x20000000U) /*!< ADC deep power down enable */
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|
|
1521 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000U) /*!< ADC differential mode for calibration */
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|
|
1522 #define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */
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|
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1523
|
|
|
1524 /******************** Bit definition for ADC_CFGR register ******************/
|
|
|
1525 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001U) /*!< ADC DMA transfer enable */
|
|
|
1526 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002U) /*!< ADC DMA transfer configuration */
|
|
|
1527
|
|
|
1528 #define ADC_CFGR_RES ((uint32_t)0x00000018U) /*!< ADC data resolution */
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|
|
1529 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008U) /*!< bit 0 */
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|
|
1530 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010U) /*!< bit 1 */
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|
|
1531
|
|
|
1532 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020U) /*!< ADC data alignement */
|
|
|
1533
|
|
|
1534 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0U) /*!< ADC group regular external trigger source */
|
|
|
1535 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1536 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1537 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1538 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1539
|
|
|
1540 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00U) /*!< ADC group regular external trigger polarity */
|
|
|
1541 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400U) /*!< bit 0 */
|
|
|
1542 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800U) /*!< bit 1 */
|
|
|
1543
|
|
|
1544 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000U) /*!< ADC group regular overrun configuration */
|
|
|
1545 #define ADC_CFGR_CONT ((uint32_t)0x00002000U) /*!< ADC group regular continuous conversion mode */
|
|
|
1546 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000U) /*!< ADC low power auto wait */
|
|
|
1547
|
|
|
1548 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000U) /*!< ADC group regular sequencer discontinuous mode */
|
|
|
1549
|
|
|
1550 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000U) /*!< ADC Discontinuous mode channel count */
|
|
|
1551 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000U) /*!< bit 0 */
|
|
|
1552 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000U) /*!< bit 1 */
|
|
|
1553 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000U) /*!< bit 2 */
|
|
|
1554
|
|
|
1555 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000U) /*!< ADC Discontinuous mode on injected channels */
|
|
|
1556 #define ADC_CFGR_JQM ((uint32_t)0x00200000U) /*!< ADC group injected contexts queue mode */
|
|
|
1557 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
|
|
|
1558 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */
|
|
|
1559 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */
|
|
|
1560 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000U) /*!< ADC group injected automatic trigger mode */
|
|
|
1561
|
|
|
1562 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000U) /*!< ADC analog watchdog 1 monitored channel selection */
|
|
|
1563 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
|
|
|
1564 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
|
|
|
1565 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
|
|
|
1566 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
|
|
|
1567 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
|
|
|
1568
|
|
|
1569 #define ADC_CFGR_JQDIS ((uint32_t)0x80000000U) /*!< ADC group injected contexts queue disable */
|
|
|
1570
|
|
|
1571 /******************** Bit definition for ADC_CFGR2 register *****************/
|
|
|
1572 #define ADC_CFGR2_ROVSE ((uint32_t)0x00000001U) /*!< ADC oversampler enable on scope ADC group regular */
|
|
|
1573 #define ADC_CFGR2_JOVSE ((uint32_t)0x00000002U) /*!< ADC oversampler enable on scope ADC group injected */
|
|
|
1574
|
|
|
1575 #define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< ADC oversampling ratio */
|
|
|
1576 #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< bit 0 */
|
|
|
1577 #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< bit 1 */
|
|
|
1578 #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< bit 2 */
|
|
|
1579
|
|
|
1580 #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< ADC oversampling shift */
|
|
|
1581 #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< bit 0 */
|
|
|
1582 #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< bit 1 */
|
|
|
1583 #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< bit 2 */
|
|
|
1584 #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< bit 3 */
|
|
|
1585
|
|
|
1586 #define ADC_CFGR2_TROVS ((uint32_t)0x00000200U) /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
|
|
|
1587 #define ADC_CFGR2_ROVSM ((uint32_t)0x00000400U) /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
|
|
|
1588
|
|
|
1589 /******************** Bit definition for ADC_SMPR1 register *****************/
|
|
|
1590 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */
|
|
|
1591 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1592 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1593 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1594
|
|
|
1595 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */
|
|
|
1596 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008U) /*!< bit 0 */
|
|
|
1597 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010U) /*!< bit 1 */
|
|
|
1598 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020U) /*!< bit 2 */
|
|
|
1599
|
|
|
1600 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */
|
|
|
1601 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1602 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1603 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1604
|
|
|
1605 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */
|
|
|
1606 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200U) /*!< bit 0 */
|
|
|
1607 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400U) /*!< bit 1 */
|
|
|
1608 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800U) /*!< bit 2 */
|
|
|
1609
|
|
|
1610 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */
|
|
|
1611 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1612 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1613 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1614
|
|
|
1615 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */
|
|
|
1616 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000U) /*!< bit 0 */
|
|
|
1617 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000U) /*!< bit 1 */
|
|
|
1618 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000U) /*!< bit 2 */
|
|
|
1619
|
|
|
1620 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */
|
|
|
1621 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1622 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1623 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1624
|
|
|
1625 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */
|
|
|
1626 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000U) /*!< bit 0 */
|
|
|
1627 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000U) /*!< bit 1 */
|
|
|
1628 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000U) /*!< bit 2 */
|
|
|
1629
|
|
|
1630 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */
|
|
|
1631 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1632 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1633 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1634
|
|
|
1635 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */
|
|
|
1636 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000U) /*!< bit 0 */
|
|
|
1637 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000U) /*!< bit 1 */
|
|
|
1638 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000U) /*!< bit 2 */
|
|
|
1639
|
|
|
1640 /******************** Bit definition for ADC_SMPR2 register *****************/
|
|
|
1641 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */
|
|
|
1642 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1643 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1644 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1645
|
|
|
1646 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */
|
|
|
1647 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< bit 0 */
|
|
|
1648 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< bit 1 */
|
|
|
1649 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< bit 2 */
|
|
|
1650
|
|
|
1651 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */
|
|
|
1652 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1653 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1654 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1655
|
|
|
1656 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */
|
|
|
1657 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< bit 0 */
|
|
|
1658 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< bit 1 */
|
|
|
1659 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< bit 2 */
|
|
|
1660
|
|
|
1661 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */
|
|
|
1662 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1663 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1664 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1665
|
|
|
1666 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 15 sampling time selection */
|
|
|
1667 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< bit 0 */
|
|
|
1668 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< bit 1 */
|
|
|
1669 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< bit 2 */
|
|
|
1670
|
|
|
1671 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */
|
|
|
1672 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1673 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1674 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1675
|
|
|
1676 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */
|
|
|
1677 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< bit 0 */
|
|
|
1678 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< bit 1 */
|
|
|
1679 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< bit 2 */
|
|
|
1680
|
|
|
1681 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */
|
|
|
1682 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1683 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1684 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1685
|
|
|
1686 /******************** Bit definition for ADC_TR1 register *******************/
|
|
|
1687 #define ADC_TR1_LT1 ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */
|
|
|
1688 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1689 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1690 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1691 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1692 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1693 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1694 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1695 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1696 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1697 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1698 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1699 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1700
|
|
|
1701 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000U) /*!< ADC Analog watchdog 1 threshold high */
|
|
|
1702 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
1703 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
1704 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000U) /*!< bit 2 */
|
|
|
1705 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000U) /*!< bit 3 */
|
|
|
1706 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000U) /*!< bit 4 */
|
|
|
1707 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000U) /*!< bit 5 */
|
|
|
1708 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000U) /*!< bit 6 */
|
|
|
1709 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000U) /*!< bit 7 */
|
|
|
1710 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000U) /*!< bit 8 */
|
|
|
1711 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000U) /*!< bit 9 */
|
|
|
1712 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000U) /*!< bit 10 */
|
|
|
1713 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000U) /*!< bit 11 */
|
|
|
1714
|
|
|
1715 /******************** Bit definition for ADC_TR2 register *******************/
|
|
|
1716 #define ADC_TR2_LT2 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 2 threshold low */
|
|
|
1717 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1718 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1719 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1720 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1721 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1722 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1723 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1724 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1725
|
|
|
1726 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 2 threshold high */
|
|
|
1727 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
1728 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
1729 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000U) /*!< bit 2 */
|
|
|
1730 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000U) /*!< bit 3 */
|
|
|
1731 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000U) /*!< bit 4 */
|
|
|
1732 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000U) /*!< bit 5 */
|
|
|
1733 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000U) /*!< bit 6 */
|
|
|
1734 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000U) /*!< bit 7 */
|
|
|
1735
|
|
|
1736 /******************** Bit definition for ADC_TR3 register *******************/
|
|
|
1737 #define ADC_TR3_LT3 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 3 threshold low */
|
|
|
1738 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1739 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1740 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1741 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1742 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1743 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1744 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1745 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1746
|
|
|
1747 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 3 threshold high */
|
|
|
1748 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
1749 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
1750 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000U) /*!< bit 2 */
|
|
|
1751 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000U) /*!< bit 3 */
|
|
|
1752 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000U) /*!< bit 4 */
|
|
|
1753 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000U) /*!< bit 5 */
|
|
|
1754 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000U) /*!< bit 6 */
|
|
|
1755 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000U) /*!< bit 7 */
|
|
|
1756
|
|
|
1757 /******************** Bit definition for ADC_SQR1 register ******************/
|
|
|
1758 #define ADC_SQR1_L ((uint32_t)0x0000000FU) /*!< ADC group regular sequencer scan length */
|
|
|
1759 #define ADC_SQR1_L_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1760 #define ADC_SQR1_L_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1761 #define ADC_SQR1_L_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1762 #define ADC_SQR1_L_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1763
|
|
|
1764 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 1 */
|
|
|
1765 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1766 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1767 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1768 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1769 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400U) /*!< bit 4 */
|
|
|
1770
|
|
|
1771 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 2 */
|
|
|
1772 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1773 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1774 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1775 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000U) /*!< bit 3 */
|
|
|
1776 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000U) /*!< bit 4 */
|
|
|
1777
|
|
|
1778 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 3 */
|
|
|
1779 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1780 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1781 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1782 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000U) /*!< bit 3 */
|
|
|
1783 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000U) /*!< bit 4 */
|
|
|
1784
|
|
|
1785 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 4 */
|
|
|
1786 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1787 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1788 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1789 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000U) /*!< bit 3 */
|
|
|
1790 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000U) /*!< bit 4 */
|
|
|
1791
|
|
|
1792 /******************** Bit definition for ADC_SQR2 register ******************/
|
|
|
1793 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 5 */
|
|
|
1794 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1795 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1796 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1797 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1798 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1799
|
|
|
1800 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 6 */
|
|
|
1801 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1802 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1803 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1804 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1805 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400U) /*!< bit 4 */
|
|
|
1806
|
|
|
1807 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 7 */
|
|
|
1808 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1809 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1810 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1811 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000U) /*!< bit 3 */
|
|
|
1812 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000U) /*!< bit 4 */
|
|
|
1813
|
|
|
1814 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 8 */
|
|
|
1815 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1816 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1817 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1818 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000U) /*!< bit 3 */
|
|
|
1819 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000U) /*!< bit 4 */
|
|
|
1820
|
|
|
1821 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 9 */
|
|
|
1822 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1823 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1824 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1825 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000U) /*!< bit 3 */
|
|
|
1826 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000U) /*!< bit 4 */
|
|
|
1827
|
|
|
1828 /******************** Bit definition for ADC_SQR3 register ******************/
|
|
|
1829 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 10 */
|
|
|
1830 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1831 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1832 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1833 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1834 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1835
|
|
|
1836 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 11 */
|
|
|
1837 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1838 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1839 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1840 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1841 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400U) /*!< bit 4 */
|
|
|
1842
|
|
|
1843 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 12 */
|
|
|
1844 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000U) /*!< bit 0 */
|
|
|
1845 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000U) /*!< bit 1 */
|
|
|
1846 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000U) /*!< bit 2 */
|
|
|
1847 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000U) /*!< bit 3 */
|
|
|
1848 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000U) /*!< bit 4 */
|
|
|
1849
|
|
|
1850 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 13 */
|
|
|
1851 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
1852 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
1853 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
1854 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000U) /*!< bit 3 */
|
|
|
1855 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000U) /*!< bit 4 */
|
|
|
1856
|
|
|
1857 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 14 */
|
|
|
1858 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000U) /*!< bit 0 */
|
|
|
1859 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000U) /*!< bit 1 */
|
|
|
1860 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000U) /*!< bit 2 */
|
|
|
1861 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000U) /*!< bit 3 */
|
|
|
1862 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000U) /*!< bit 4 */
|
|
|
1863
|
|
|
1864 /******************** Bit definition for ADC_SQR4 register ******************/
|
|
|
1865 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 15 */
|
|
|
1866 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1867 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1868 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1869 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1870 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010U) /*!<5 bit 4 */
|
|
|
1871
|
|
|
1872 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 16 */
|
|
|
1873 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1874 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1875 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100U) /*!< bit 2 */
|
|
|
1876 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200U) /*!< bit 3 */
|
|
|
1877 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400U) /*!< bit 4 */
|
|
|
1878
|
|
|
1879 /******************** Bit definition for ADC_DR register ********************/
|
|
|
1880 #define ADC_DR_RDATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */
|
|
|
1881 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1882 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1883 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
1884 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
1885 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
1886 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
1887 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
1888 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
1889 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
1890 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
1891 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
1892 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
1893 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
|
|
|
1894 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
|
|
|
1895 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
|
|
|
1896 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
|
|
|
1897
|
|
|
1898 /******************** Bit definition for ADC_JSQR register ******************/
|
|
|
1899 #define ADC_JSQR_JL ((uint32_t)0x00000003U) /*!< ADC group injected sequencer scan length */
|
|
|
1900 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
1901 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
1902
|
|
|
1903 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003CU) /*!< ADC group injected external trigger source */
|
|
|
1904 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004U) /*!< bit 0 */
|
|
|
1905 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008U) /*!< bit 1 */
|
|
|
1906 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010U) /*!< bit 2 */
|
|
|
1907 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020U) /*!< bit 3 */
|
|
|
1908
|
|
|
1909 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0U) /*!< ADC group injected external trigger polarity */
|
|
|
1910 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040U) /*!< bit 0 */
|
|
|
1911 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080U) /*!< bit 1 */
|
|
|
1912
|
|
|
1913 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00U) /*!< ADC group injected sequencer rank 1 */
|
|
|
1914 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100U) /*!< bit 0 */
|
|
|
1915 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200U) /*!< bit 1 */
|
|
|
1916 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400U) /*!< bit 2 */
|
|
|
1917 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800U) /*!< bit 3 */
|
|
|
1918 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000U) /*!< bit 4 */
|
|
|
1919
|
|
|
1920 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000U) /*!< ADC group injected sequencer rank 2 */
|
|
|
1921 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000U) /*!< bit 0 */
|
|
|
1922 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000U) /*!< bit 1 */
|
|
|
1923 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000U) /*!< bit 2 */
|
|
|
1924 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000U) /*!< bit 3 */
|
|
|
1925 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000U) /*!< bit 4 */
|
|
|
1926
|
|
|
1927 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000U) /*!< ADC group injected sequencer rank 3 */
|
|
|
1928 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000U) /*!< bit 0 */
|
|
|
1929 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000U) /*!< bit 1 */
|
|
|
1930 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000U) /*!< bit 2 */
|
|
|
1931 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000U) /*!< bit 3 */
|
|
|
1932 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000U) /*!< bit 4 */
|
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1933
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1934 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000U) /*!< ADC group injected sequencer rank 4 */
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1935 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000U) /*!< bit 0 */
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1936 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000U) /*!< bit 1 */
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1937 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000U) /*!< bit 2 */
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1938 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000U) /*!< bit 3 */
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1939 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000U) /*!< bit 4 */
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1940
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1941
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1942 /******************** Bit definition for ADC_OFR1 register ******************/
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1943 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC offset number 1 offset level */
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1944 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001U) /*!< bit 0 */
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1945 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002U) /*!< bit 1 */
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1946 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004U) /*!< bit 2 */
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1947 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008U) /*!< bit 3 */
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1948 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010U) /*!< bit 4 */
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1949 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020U) /*!< bit 5 */
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1950 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040U) /*!< bit 6 */
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1951 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080U) /*!< bit 7 */
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1952 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100U) /*!< bit 8 */
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1953 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200U) /*!< bit 9 */
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1954 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400U) /*!< bit 10 */
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1955 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800U) /*!< bit 11 */
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1956
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1957 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 1 channel selection */
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1958 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
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1959 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
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1960 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
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1961 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
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1962 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
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1963
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1964 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000U) /*!< ADC offset number 1 enable */
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1965
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1966 /******************** Bit definition for ADC_OFR2 register ******************/
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1967 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC offset number 2 offset level */
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1968 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001U) /*!< bit 0 */
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1969 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002U) /*!< bit 1 */
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1970 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004U) /*!< bit 2 */
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1971 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008U) /*!< bit 3 */
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1972 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010U) /*!< bit 4 */
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1973 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020U) /*!< bit 5 */
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1974 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040U) /*!< bit 6 */
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1975 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080U) /*!< bit 7 */
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1976 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100U) /*!< bit 8 */
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1977 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200U) /*!< bit 9 */
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1978 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400U) /*!< bit 10 */
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1979 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800U) /*!< bit 11 */
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1980
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1981 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 2 channel selection */
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1982 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
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1983 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
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1984 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
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1985 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
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1986 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
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1987
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1988 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000U) /*!< ADC offset number 2 enable */
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1989
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1990 /******************** Bit definition for ADC_OFR3 register ******************/
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1991 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC offset number 3 offset level */
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1992 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001U) /*!< bit 0 */
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1993 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002U) /*!< bit 1 */
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1994 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004U) /*!< bit 2 */
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1995 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008U) /*!< bit 3 */
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1996 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010U) /*!< bit 4 */
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1997 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020U) /*!< bit 5 */
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1998 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040U) /*!< bit 6 */
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1999 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080U) /*!< bit 7 */
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2000 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100U) /*!< bit 8 */
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2001 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200U) /*!< bit 9 */
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2002 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400U) /*!< bit 10 */
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2003 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800U) /*!< bit 11 */
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2004
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2005 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 3 channel selection */
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2006 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
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2007 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
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2008 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
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2009 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
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2010 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
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2011
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2012 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000U) /*!< ADC offset number 3 enable */
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2013
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2014 /******************** Bit definition for ADC_OFR4 register ******************/
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2015 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC offset number 4 offset level */
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2016 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001U) /*!< bit 0 */
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2017 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002U) /*!< bit 1 */
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2018 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004U) /*!< bit 2 */
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2019 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008U) /*!< bit 3 */
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2020 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010U) /*!< bit 4 */
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2021 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020U) /*!< bit 5 */
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2022 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040U) /*!< bit 6 */
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2023 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080U) /*!< bit 7 */
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2024 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100U) /*!< bit 8 */
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2025 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200U) /*!< bit 9 */
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2026 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400U) /*!< bit 10 */
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2027 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800U) /*!< bit 11 */
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2028
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2029 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 4 channel selection */
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2030 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
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2031 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
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2032 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
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2033 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
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2034 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
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2035
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2036 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000U) /*!< ADC offset number 4 enable */
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2037
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2038 /******************** Bit definition for ADC_JDR1 register ******************/
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2039 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */
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2040 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
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2041 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
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2042 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
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2043 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
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2044 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
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2045 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
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2046 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
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2047 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
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2048 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
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2049 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
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2050 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
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2051 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
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2052 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
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2053 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
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2054 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
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2055 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
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2056
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2057 /******************** Bit definition for ADC_JDR2 register ******************/
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2058 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */
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2059 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
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2060 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
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2061 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
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2062 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
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2063 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
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2064 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
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2065 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
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2066 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
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2067 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
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2068 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
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2069 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
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2070 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
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2071 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
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2072 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
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2073 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
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2074 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
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2075
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2076 /******************** Bit definition for ADC_JDR3 register ******************/
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2077 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */
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2078 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
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2079 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
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2080 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
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2081 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
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2082 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
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2083 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
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2084 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
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2085 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
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2086 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
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2087 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
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2088 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
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2089 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
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2090 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
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2091 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
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2092 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
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2093 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
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2094
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2095 /******************** Bit definition for ADC_JDR4 register ******************/
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2096 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */
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2097 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
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2098 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
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2099 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
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2100 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
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2101 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
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2102 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
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2103 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
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2104 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
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2105 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
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2106 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
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2107 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
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2108 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
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2109 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
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2110 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
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2111 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
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2112 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
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2113
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|
2114 /******************** Bit definition for ADC_AWD2CR register ****************/
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2115 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 2 monitored channel selection */
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2116 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 2 monitoring channel 0 */
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2117 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 2 monitoring channel 1 */
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2118 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 2 monitoring channel 2 */
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2119 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 2 monitoring channel 3 */
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2120 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 2 monitoring channel 4 */
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2121 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 2 monitoring channel 5 */
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2122 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 2 monitoring channel 6 */
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2123 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 2 monitoring channel 7 */
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2124 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 monitoring channel 8 */
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2125 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 2 monitoring channel 9 */
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2126 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 2 monitoring channel 10 */
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2127 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 2 monitoring channel 11 */
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2128 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 2 monitoring channel 12 */
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2129 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 2 monitoring channel 13 */
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2130 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 2 monitoring channel 14 */
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2131 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 2 monitoring channel 15 */
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|
2132 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 2 monitoring channel 16 */
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2133 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 2 monitoring channel 17 */
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|
2134 #define ADC_AWD2CR_AWD2CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 2 monitoring channel 18 */
|
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|
2135
|
|
|
2136 /******************** Bit definition for ADC_AWD3CR register ****************/
|
|
|
2137 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 3 monitored channel selection */
|
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|
2138 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 3 monitoring channel 0 */
|
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|
2139 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 3 monitoring channel 1 */
|
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|
2140 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 3 monitoring channel 2 */
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2141 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 3 monitoring channel 3 */
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|
|
2142 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 3 monitoring channel 4 */
|
|
|
2143 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 3 monitoring channel 5 */
|
|
|
2144 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 3 monitoring channel 6 */
|
|
|
2145 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 3 monitoring channel 7 */
|
|
|
2146 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 3 monitoring channel 8 */
|
|
|
2147 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 monitoring channel 9 */
|
|
|
2148 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 3 monitoring channel 10 */
|
|
|
2149 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 3 monitoring channel 11 */
|
|
|
2150 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 3 monitoring channel 12 */
|
|
|
2151 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 3 monitoring channel 13 */
|
|
|
2152 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 3 monitoring channel 14 */
|
|
|
2153 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 3 monitoring channel 15 */
|
|
|
2154 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 3 monitoring channel 16 */
|
|
|
2155 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 3 monitoring channel 17 */
|
|
|
2156 #define ADC_AWD3CR_AWD3CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 3 monitoring channel 18 */
|
|
|
2157
|
|
|
2158 /******************** Bit definition for ADC_DIFSEL register ****************/
|
|
|
2159 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFFU) /*!< ADC channel differential or single-ended mode */
|
|
|
2160 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
2161 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
2162 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
2163 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
2164 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
2165 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
2166 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
2167 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
2168 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
2169 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
2170 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
2171 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
2172 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00001000U) /*!< bit 12 */
|
|
|
2173 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00002000U) /*!< bit 13 */
|
|
|
2174 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00004000U) /*!< bit 14 */
|
|
|
2175 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00008000U) /*!< bit 15 */
|
|
|
2176 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00010000U) /*!< bit 16 */
|
|
|
2177 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00020000U) /*!< bit 17 */
|
|
|
2178 #define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00040000U) /*!< bit 18 */
|
|
|
2179
|
|
|
2180 /******************** Bit definition for ADC_CALFACT register ***************/
|
|
|
2181 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007FU) /*!< ADC calibration factor in single-ended mode */
|
|
|
2182 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
2183 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
2184 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
2185 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
2186 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
2187 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
2188 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
2189
|
|
|
2190 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000U) /*!< ADC calibration factor in differential mode */
|
|
|
2191 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
2192 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
2193 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000U) /*!< bit 2 */
|
|
|
2194 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000U) /*!< bit 3 */
|
|
|
2195 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000U) /*!< bit 4 */
|
|
|
2196 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000U) /*!< bit 5 */
|
|
|
2197 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000U) /*!< bit 6 */
|
|
|
2198
|
|
|
2199 /************************* ADC Common registers *****************************/
|
|
|
2200 /******************** Bit definition for ADC_CSR register *******************/
|
|
|
2201 #define ADC_CSR_ADRDY_MST ((uint32_t)0x00000001U) /*!< ADC multimode master ready flag */
|
|
|
2202 #define ADC_CSR_EOSMP_MST ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of sampling flag */
|
|
|
2203 #define ADC_CSR_EOC_MST ((uint32_t)0x00000004U) /*!< ADC multimode master group regular end of unitary conversion flag */
|
|
|
2204 #define ADC_CSR_EOS_MST ((uint32_t)0x00000008U) /*!< ADC multimode master group regular end of sequence conversions flag */
|
|
|
2205 #define ADC_CSR_OVR_MST ((uint32_t)0x00000010U) /*!< ADC multimode master group regular overrun flag */
|
|
|
2206 #define ADC_CSR_JEOC_MST ((uint32_t)0x00000020U) /*!< ADC multimode master group injected end of unitary conversion flag */
|
|
|
2207 #define ADC_CSR_JEOS_MST ((uint32_t)0x00000040U) /*!< ADC multimode master group injected end of sequence conversions flag */
|
|
|
2208 #define ADC_CSR_AWD1_MST ((uint32_t)0x00000080U) /*!< ADC multimode master analog watchdog 1 flag */
|
|
|
2209 #define ADC_CSR_AWD2_MST ((uint32_t)0x00000100U) /*!< ADC multimode master analog watchdog 2 flag */
|
|
|
2210 #define ADC_CSR_AWD3_MST ((uint32_t)0x00000200U) /*!< ADC multimode master analog watchdog 3 flag */
|
|
|
2211 #define ADC_CSR_JQOVF_MST ((uint32_t)0x00000400U) /*!< ADC multimode master group injected contexts queue overflow flag */
|
|
|
2212
|
|
|
2213 #define ADC_CSR_ADRDY_SLV ((uint32_t)0x00010000U) /*!< ADC multimode slave ready flag */
|
|
|
2214 #define ADC_CSR_EOSMP_SLV ((uint32_t)0x00020000U) /*!< ADC multimode slave group regular end of sampling flag */
|
|
|
2215 #define ADC_CSR_EOC_SLV ((uint32_t)0x00040000U) /*!< ADC multimode slave group regular end of unitary conversion flag */
|
|
|
2216 #define ADC_CSR_EOS_SLV ((uint32_t)0x00080000U) /*!< ADC multimode slave group regular end of sequence conversions flag */
|
|
|
2217 #define ADC_CSR_OVR_SLV ((uint32_t)0x00100000U) /*!< ADC multimode slave group regular overrun flag */
|
|
|
2218 #define ADC_CSR_JEOC_SLV ((uint32_t)0x00200000U) /*!< ADC multimode slave group injected end of unitary conversion flag */
|
|
|
2219 #define ADC_CSR_JEOS_SLV ((uint32_t)0x00400000U) /*!< ADC multimode slave group injected end of sequence conversions flag */
|
|
|
2220 #define ADC_CSR_AWD1_SLV ((uint32_t)0x00800000U) /*!< ADC multimode slave analog watchdog 1 flag */
|
|
|
2221 #define ADC_CSR_AWD2_SLV ((uint32_t)0x01000000U) /*!< ADC multimode slave analog watchdog 2 flag */
|
|
|
2222 #define ADC_CSR_AWD3_SLV ((uint32_t)0x02000000U) /*!< ADC multimode slave analog watchdog 3 flag */
|
|
|
2223 #define ADC_CSR_JQOVF_SLV ((uint32_t)0x04000000U) /*!< ADC multimode slave group injected contexts queue overflow flag */
|
|
|
2224
|
|
|
2225 /******************** Bit definition for ADC_CCR register *******************/
|
|
|
2226 #define ADC_CCR_DUAL ((uint32_t)0x0000001FU) /*!< ADC multimode mode selection */
|
|
|
2227 #define ADC_CCR_DUAL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
2228 #define ADC_CCR_DUAL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
2229 #define ADC_CCR_DUAL_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
2230 #define ADC_CCR_DUAL_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
2231 #define ADC_CCR_DUAL_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
2232
|
|
|
2233 #define ADC_CCR_DELAY ((uint32_t)0x00000F00U) /*!< ADC multimode delay between 2 sampling phases */
|
|
|
2234 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100U) /*!< bit 0 */
|
|
|
2235 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200U) /*!< bit 1 */
|
|
|
2236 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400U) /*!< bit 2 */
|
|
|
2237 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800U) /*!< bit 3 */
|
|
|
2238
|
|
|
2239 #define ADC_CCR_DMACFG ((uint32_t)0x00002000U) /*!< ADC multimode DMA transfer configuration */
|
|
|
2240
|
|
|
2241 #define ADC_CCR_MDMA ((uint32_t)0x0000C000U) /*!< ADC multimode DMA transfer enable */
|
|
|
2242 #define ADC_CCR_MDMA_0 ((uint32_t)0x00004000U) /*!< bit 0 */
|
|
|
2243 #define ADC_CCR_MDMA_1 ((uint32_t)0x00008000U) /*!< bit 1 */
|
|
|
2244
|
|
|
2245 #define ADC_CCR_CKMODE ((uint32_t)0x00030000U) /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
|
|
|
2246 #define ADC_CCR_CKMODE_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
2247 #define ADC_CCR_CKMODE_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
2248
|
|
|
2249 #define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< ADC common clock prescaler, only for clock source asynchronous */
|
|
|
2250 #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< bit 0 */
|
|
|
2251 #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< bit 1 */
|
|
|
2252 #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< bit 2 */
|
|
|
2253 #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< bit 3 */
|
|
|
2254
|
|
|
2255 #define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< ADC internal path to VrefInt enable */
|
|
|
2256 #define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< ADC internal path to temperature sensor enable */
|
|
|
2257 #define ADC_CCR_VBATEN ((uint32_t)0x01000000U) /*!< ADC internal path to battery voltage enable */
|
|
|
2258
|
|
|
2259 /******************** Bit definition for ADC_CDR register *******************/
|
|
|
2260 #define ADC_CDR_RDATA_MST ((uint32_t)0x0000FFFFU) /*!< ADC multimode master group regular conversion data */
|
|
|
2261 #define ADC_CDR_RDATA_MST_0 ((uint32_t)0x00000001U) /*!< bit 0 */
|
|
|
2262 #define ADC_CDR_RDATA_MST_1 ((uint32_t)0x00000002U) /*!< bit 1 */
|
|
|
2263 #define ADC_CDR_RDATA_MST_2 ((uint32_t)0x00000004U) /*!< bit 2 */
|
|
|
2264 #define ADC_CDR_RDATA_MST_3 ((uint32_t)0x00000008U) /*!< bit 3 */
|
|
|
2265 #define ADC_CDR_RDATA_MST_4 ((uint32_t)0x00000010U) /*!< bit 4 */
|
|
|
2266 #define ADC_CDR_RDATA_MST_5 ((uint32_t)0x00000020U) /*!< bit 5 */
|
|
|
2267 #define ADC_CDR_RDATA_MST_6 ((uint32_t)0x00000040U) /*!< bit 6 */
|
|
|
2268 #define ADC_CDR_RDATA_MST_7 ((uint32_t)0x00000080U) /*!< bit 7 */
|
|
|
2269 #define ADC_CDR_RDATA_MST_8 ((uint32_t)0x00000100U) /*!< bit 8 */
|
|
|
2270 #define ADC_CDR_RDATA_MST_9 ((uint32_t)0x00000200U) /*!< bit 9 */
|
|
|
2271 #define ADC_CDR_RDATA_MST_10 ((uint32_t)0x00000400U) /*!< bit 10 */
|
|
|
2272 #define ADC_CDR_RDATA_MST_11 ((uint32_t)0x00000800U) /*!< bit 11 */
|
|
|
2273 #define ADC_CDR_RDATA_MST_12 ((uint32_t)0x00001000U) /*!< bit 12 */
|
|
|
2274 #define ADC_CDR_RDATA_MST_13 ((uint32_t)0x00002000U) /*!< bit 13 */
|
|
|
2275 #define ADC_CDR_RDATA_MST_14 ((uint32_t)0x00004000U) /*!< bit 14 */
|
|
|
2276 #define ADC_CDR_RDATA_MST_15 ((uint32_t)0x00008000U) /*!< bit 15 */
|
|
|
2277
|
|
|
2278 #define ADC_CDR_RDATA_SLV ((uint32_t)0xFFFF0000U) /*!< ADC multimode slave group regular conversion data */
|
|
|
2279 #define ADC_CDR_RDATA_SLV_0 ((uint32_t)0x00010000U) /*!< bit 0 */
|
|
|
2280 #define ADC_CDR_RDATA_SLV_1 ((uint32_t)0x00020000U) /*!< bit 1 */
|
|
|
2281 #define ADC_CDR_RDATA_SLV_2 ((uint32_t)0x00040000U) /*!< bit 2 */
|
|
|
2282 #define ADC_CDR_RDATA_SLV_3 ((uint32_t)0x00080000U) /*!< bit 3 */
|
|
|
2283 #define ADC_CDR_RDATA_SLV_4 ((uint32_t)0x00100000U) /*!< bit 4 */
|
|
|
2284 #define ADC_CDR_RDATA_SLV_5 ((uint32_t)0x00200000U) /*!< bit 5 */
|
|
|
2285 #define ADC_CDR_RDATA_SLV_6 ((uint32_t)0x00400000U) /*!< bit 6 */
|
|
|
2286 #define ADC_CDR_RDATA_SLV_7 ((uint32_t)0x00800000U) /*!< bit 7 */
|
|
|
2287 #define ADC_CDR_RDATA_SLV_8 ((uint32_t)0x01000000U) /*!< bit 8 */
|
|
|
2288 #define ADC_CDR_RDATA_SLV_9 ((uint32_t)0x02000000U) /*!< bit 9 */
|
|
|
2289 #define ADC_CDR_RDATA_SLV_10 ((uint32_t)0x04000000U) /*!< bit 10 */
|
|
|
2290 #define ADC_CDR_RDATA_SLV_11 ((uint32_t)0x08000000U) /*!< bit 11 */
|
|
|
2291 #define ADC_CDR_RDATA_SLV_12 ((uint32_t)0x10000000U) /*!< bit 12 */
|
|
|
2292 #define ADC_CDR_RDATA_SLV_13 ((uint32_t)0x20000000U) /*!< bit 13 */
|
|
|
2293 #define ADC_CDR_RDATA_SLV_14 ((uint32_t)0x40000000U) /*!< bit 14 */
|
|
|
2294 #define ADC_CDR_RDATA_SLV_15 ((uint32_t)0x80000000U) /*!< bit 15 */
|
|
|
2295
|
|
|
2296 /******************************************************************************/
|
|
|
2297 /* */
|
|
|
2298 /* Controller Area Network */
|
|
|
2299 /* */
|
|
|
2300 /******************************************************************************/
|
|
|
2301 /*!<CAN control and status registers */
|
|
|
2302 /******************* Bit definition for CAN_MCR register ********************/
|
|
|
2303 #define CAN_MCR_INRQ ((uint16_t)0x0001U) /*!<Initialization Request */
|
|
|
2304 #define CAN_MCR_SLEEP ((uint16_t)0x0002U) /*!<Sleep Mode Request */
|
|
|
2305 #define CAN_MCR_TXFP ((uint16_t)0x0004U) /*!<Transmit FIFO Priority */
|
|
|
2306 #define CAN_MCR_RFLM ((uint16_t)0x0008U) /*!<Receive FIFO Locked Mode */
|
|
|
2307 #define CAN_MCR_NART ((uint16_t)0x0010U) /*!<No Automatic Retransmission */
|
|
|
2308 #define CAN_MCR_AWUM ((uint16_t)0x0020U) /*!<Automatic Wakeup Mode */
|
|
|
2309 #define CAN_MCR_ABOM ((uint16_t)0x0040U) /*!<Automatic Bus-Off Management */
|
|
|
2310 #define CAN_MCR_TTCM ((uint16_t)0x0080U) /*!<Time Triggered Communication Mode */
|
|
|
2311 #define CAN_MCR_RESET ((uint16_t)0x8000U) /*!<bxCAN software master reset */
|
|
|
2312
|
|
|
2313 /******************* Bit definition for CAN_MSR register ********************/
|
|
|
2314 #define CAN_MSR_INAK ((uint16_t)0x0001U) /*!<Initialization Acknowledge */
|
|
|
2315 #define CAN_MSR_SLAK ((uint16_t)0x0002U) /*!<Sleep Acknowledge */
|
|
|
2316 #define CAN_MSR_ERRI ((uint16_t)0x0004U) /*!<Error Interrupt */
|
|
|
2317 #define CAN_MSR_WKUI ((uint16_t)0x0008U) /*!<Wakeup Interrupt */
|
|
|
2318 #define CAN_MSR_SLAKI ((uint16_t)0x0010U) /*!<Sleep Acknowledge Interrupt */
|
|
|
2319 #define CAN_MSR_TXM ((uint16_t)0x0100U) /*!<Transmit Mode */
|
|
|
2320 #define CAN_MSR_RXM ((uint16_t)0x0200U) /*!<Receive Mode */
|
|
|
2321 #define CAN_MSR_SAMP ((uint16_t)0x0400U) /*!<Last Sample Point */
|
|
|
2322 #define CAN_MSR_RX ((uint16_t)0x0800U) /*!<CAN Rx Signal */
|
|
|
2323
|
|
|
2324 /******************* Bit definition for CAN_TSR register ********************/
|
|
|
2325 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001U) /*!<Request Completed Mailbox0 */
|
|
|
2326 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002U) /*!<Transmission OK of Mailbox0 */
|
|
|
2327 #define CAN_TSR_ALST0 ((uint32_t)0x00000004U) /*!<Arbitration Lost for Mailbox0 */
|
|
|
2328 #define CAN_TSR_TERR0 ((uint32_t)0x00000008U) /*!<Transmission Error of Mailbox0 */
|
|
|
2329 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080U) /*!<Abort Request for Mailbox0 */
|
|
|
2330 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100U) /*!<Request Completed Mailbox1 */
|
|
|
2331 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200U) /*!<Transmission OK of Mailbox1 */
|
|
|
2332 #define CAN_TSR_ALST1 ((uint32_t)0x00000400U) /*!<Arbitration Lost for Mailbox1 */
|
|
|
2333 #define CAN_TSR_TERR1 ((uint32_t)0x00000800U) /*!<Transmission Error of Mailbox1 */
|
|
|
2334 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000U) /*!<Abort Request for Mailbox 1 */
|
|
|
2335 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000U) /*!<Request Completed Mailbox2 */
|
|
|
2336 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000U) /*!<Transmission OK of Mailbox 2 */
|
|
|
2337 #define CAN_TSR_ALST2 ((uint32_t)0x00040000U) /*!<Arbitration Lost for mailbox 2 */
|
|
|
2338 #define CAN_TSR_TERR2 ((uint32_t)0x00080000U) /*!<Transmission Error of Mailbox 2 */
|
|
|
2339 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000U) /*!<Abort Request for Mailbox 2 */
|
|
|
2340 #define CAN_TSR_CODE ((uint32_t)0x03000000U) /*!<Mailbox Code */
|
|
|
2341
|
|
|
2342 #define CAN_TSR_TME ((uint32_t)0x1C000000U) /*!<TME[2:0] bits */
|
|
|
2343 #define CAN_TSR_TME0 ((uint32_t)0x04000000U) /*!<Transmit Mailbox 0 Empty */
|
|
|
2344 #define CAN_TSR_TME1 ((uint32_t)0x08000000U) /*!<Transmit Mailbox 1 Empty */
|
|
|
2345 #define CAN_TSR_TME2 ((uint32_t)0x10000000U) /*!<Transmit Mailbox 2 Empty */
|
|
|
2346
|
|
|
2347 #define CAN_TSR_LOW ((uint32_t)0xE0000000U) /*!<LOW[2:0] bits */
|
|
|
2348 #define CAN_TSR_LOW0 ((uint32_t)0x20000000U) /*!<Lowest Priority Flag for Mailbox 0 */
|
|
|
2349 #define CAN_TSR_LOW1 ((uint32_t)0x40000000U) /*!<Lowest Priority Flag for Mailbox 1 */
|
|
|
2350 #define CAN_TSR_LOW2 ((uint32_t)0x80000000U) /*!<Lowest Priority Flag for Mailbox 2 */
|
|
|
2351
|
|
|
2352 /******************* Bit definition for CAN_RF0R register *******************/
|
|
|
2353 #define CAN_RF0R_FMP0 ((uint8_t)0x03U) /*!<FIFO 0 Message Pending */
|
|
|
2354 #define CAN_RF0R_FULL0 ((uint8_t)0x08U) /*!<FIFO 0 Full */
|
|
|
2355 #define CAN_RF0R_FOVR0 ((uint8_t)0x10U) /*!<FIFO 0 Overrun */
|
|
|
2356 #define CAN_RF0R_RFOM0 ((uint8_t)0x20U) /*!<Release FIFO 0 Output Mailbox */
|
|
|
2357
|
|
|
2358 /******************* Bit definition for CAN_RF1R register *******************/
|
|
|
2359 #define CAN_RF1R_FMP1 ((uint8_t)0x03U) /*!<FIFO 1 Message Pending */
|
|
|
2360 #define CAN_RF1R_FULL1 ((uint8_t)0x08U) /*!<FIFO 1 Full */
|
|
|
2361 #define CAN_RF1R_FOVR1 ((uint8_t)0x10U) /*!<FIFO 1 Overrun */
|
|
|
2362 #define CAN_RF1R_RFOM1 ((uint8_t)0x20U) /*!<Release FIFO 1 Output Mailbox */
|
|
|
2363
|
|
|
2364 /******************** Bit definition for CAN_IER register *******************/
|
|
|
2365 #define CAN_IER_TMEIE ((uint32_t)0x00000001U) /*!<Transmit Mailbox Empty Interrupt Enable */
|
|
|
2366 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002U) /*!<FIFO Message Pending Interrupt Enable */
|
|
|
2367 #define CAN_IER_FFIE0 ((uint32_t)0x00000004U) /*!<FIFO Full Interrupt Enable */
|
|
|
2368 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008U) /*!<FIFO Overrun Interrupt Enable */
|
|
|
2369 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010U) /*!<FIFO Message Pending Interrupt Enable */
|
|
|
2370 #define CAN_IER_FFIE1 ((uint32_t)0x00000020U) /*!<FIFO Full Interrupt Enable */
|
|
|
2371 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040U) /*!<FIFO Overrun Interrupt Enable */
|
|
|
2372 #define CAN_IER_EWGIE ((uint32_t)0x00000100U) /*!<Error Warning Interrupt Enable */
|
|
|
2373 #define CAN_IER_EPVIE ((uint32_t)0x00000200U) /*!<Error Passive Interrupt Enable */
|
|
|
2374 #define CAN_IER_BOFIE ((uint32_t)0x00000400U) /*!<Bus-Off Interrupt Enable */
|
|
|
2375 #define CAN_IER_LECIE ((uint32_t)0x00000800U) /*!<Last Error Code Interrupt Enable */
|
|
|
2376 #define CAN_IER_ERRIE ((uint32_t)0x00008000U) /*!<Error Interrupt Enable */
|
|
|
2377 #define CAN_IER_WKUIE ((uint32_t)0x00010000U) /*!<Wakeup Interrupt Enable */
|
|
|
2378 #define CAN_IER_SLKIE ((uint32_t)0x00020000U) /*!<Sleep Interrupt Enable */
|
|
|
2379
|
|
|
2380 /******************** Bit definition for CAN_ESR register *******************/
|
|
|
2381 #define CAN_ESR_EWGF ((uint32_t)0x00000001U) /*!<Error Warning Flag */
|
|
|
2382 #define CAN_ESR_EPVF ((uint32_t)0x00000002U) /*!<Error Passive Flag */
|
|
|
2383 #define CAN_ESR_BOFF ((uint32_t)0x00000004U) /*!<Bus-Off Flag */
|
|
|
2384
|
|
|
2385 #define CAN_ESR_LEC ((uint32_t)0x00000070U) /*!<LEC[2:0] bits (Last Error Code) */
|
|
|
2386 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
2387 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
2388 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
2389
|
|
|
2390 #define CAN_ESR_TEC ((uint32_t)0x00FF0000U) /*!<Least significant byte of the 9-bit Transmit Error Counter */
|
|
|
2391 #define CAN_ESR_REC ((uint32_t)0xFF000000U) /*!<Receive Error Counter */
|
|
|
2392
|
|
|
2393 /******************* Bit definition for CAN_BTR register ********************/
|
|
|
2394 #define CAN_BTR_BRP ((uint32_t)0x000003FFU) /*!<Baud Rate Prescaler */
|
|
|
2395 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000U) /*!<Time Segment 1 (Bit 0) */
|
|
|
2396 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000U) /*!<Time Segment 1 (Bit 1) */
|
|
|
2397 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000U) /*!<Time Segment 1 (Bit 2) */
|
|
|
2398 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000U) /*!<Time Segment 1 (Bit 3) */
|
|
|
2399 #define CAN_BTR_TS1 ((uint32_t)0x000F0000U) /*!<Time Segment 1 */
|
|
|
2400 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000U) /*!<Time Segment 2 (Bit 0) */
|
|
|
2401 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000U) /*!<Time Segment 2 (Bit 1) */
|
|
|
2402 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000U) /*!<Time Segment 2 (Bit 2) */
|
|
|
2403 #define CAN_BTR_TS2 ((uint32_t)0x00700000U) /*!<Time Segment 2 */
|
|
|
2404 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000U) /*!<Resynchronization Jump Width (Bit 0) */
|
|
|
2405 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000U) /*!<Resynchronization Jump Width (Bit 1) */
|
|
|
2406 #define CAN_BTR_SJW ((uint32_t)0x03000000U) /*!<Resynchronization Jump Width */
|
|
|
2407 #define CAN_BTR_LBKM ((uint32_t)0x40000000U) /*!<Loop Back Mode (Debug) */
|
|
|
2408 #define CAN_BTR_SILM ((uint32_t)0x80000000U) /*!<Silent Mode */
|
|
|
2409
|
|
|
2410 /*!<Mailbox registers */
|
|
|
2411 /****************** Bit definition for CAN_TI0R register ********************/
|
|
|
2412 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
|
|
|
2413 #define CAN_TI0R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2414 #define CAN_TI0R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2415 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
|
|
|
2416 #define CAN_TI0R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2417
|
|
|
2418 /****************** Bit definition for CAN_TDT0R register *******************/
|
|
|
2419 #define CAN_TDT0R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2420 #define CAN_TDT0R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
|
|
|
2421 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2422
|
|
|
2423 /****************** Bit definition for CAN_TDL0R register *******************/
|
|
|
2424 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2425 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2426 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2427 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2428
|
|
|
2429 /****************** Bit definition for CAN_TDH0R register *******************/
|
|
|
2430 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2431 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2432 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2433 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2434
|
|
|
2435 /******************* Bit definition for CAN_TI1R register *******************/
|
|
|
2436 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
|
|
|
2437 #define CAN_TI1R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2438 #define CAN_TI1R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2439 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
|
|
|
2440 #define CAN_TI1R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2441
|
|
|
2442 /******************* Bit definition for CAN_TDT1R register ******************/
|
|
|
2443 #define CAN_TDT1R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2444 #define CAN_TDT1R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
|
|
|
2445 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2446
|
|
|
2447 /******************* Bit definition for CAN_TDL1R register ******************/
|
|
|
2448 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2449 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2450 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2451 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2452
|
|
|
2453 /******************* Bit definition for CAN_TDH1R register ******************/
|
|
|
2454 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2455 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2456 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2457 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2458
|
|
|
2459 /******************* Bit definition for CAN_TI2R register *******************/
|
|
|
2460 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
|
|
|
2461 #define CAN_TI2R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2462 #define CAN_TI2R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2463 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended identifier */
|
|
|
2464 #define CAN_TI2R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2465
|
|
|
2466 /******************* Bit definition for CAN_TDT2R register ******************/
|
|
|
2467 #define CAN_TDT2R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2468 #define CAN_TDT2R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
|
|
|
2469 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2470
|
|
|
2471 /******************* Bit definition for CAN_TDL2R register ******************/
|
|
|
2472 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2473 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2474 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2475 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2476
|
|
|
2477 /******************* Bit definition for CAN_TDH2R register ******************/
|
|
|
2478 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2479 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2480 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2481 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2482
|
|
|
2483 /******************* Bit definition for CAN_RI0R register *******************/
|
|
|
2484 #define CAN_RI0R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2485 #define CAN_RI0R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2486 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
|
|
|
2487 #define CAN_RI0R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2488
|
|
|
2489 /******************* Bit definition for CAN_RDT0R register ******************/
|
|
|
2490 #define CAN_RDT0R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2491 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00U) /*!<Filter Match Index */
|
|
|
2492 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2493
|
|
|
2494 /******************* Bit definition for CAN_RDL0R register ******************/
|
|
|
2495 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2496 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2497 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2498 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2499
|
|
|
2500 /******************* Bit definition for CAN_RDH0R register ******************/
|
|
|
2501 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2502 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2503 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2504 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2505
|
|
|
2506 /******************* Bit definition for CAN_RI1R register *******************/
|
|
|
2507 #define CAN_RI1R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
|
|
|
2508 #define CAN_RI1R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
|
|
|
2509 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended identifier */
|
|
|
2510 #define CAN_RI1R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
|
|
|
2511
|
|
|
2512 /******************* Bit definition for CAN_RDT1R register ******************/
|
|
|
2513 #define CAN_RDT1R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
|
|
|
2514 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00U) /*!<Filter Match Index */
|
|
|
2515 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
|
|
|
2516
|
|
|
2517 /******************* Bit definition for CAN_RDL1R register ******************/
|
|
|
2518 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
|
|
|
2519 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
|
|
|
2520 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
|
|
|
2521 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
|
|
|
2522
|
|
|
2523 /******************* Bit definition for CAN_RDH1R register ******************/
|
|
|
2524 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
|
|
|
2525 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
|
|
|
2526 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
|
|
|
2527 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
|
|
|
2528
|
|
|
2529 /*!<CAN filter registers */
|
|
|
2530 /******************* Bit definition for CAN_FMR register ********************/
|
|
|
2531 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
|
|
|
2532
|
|
|
2533 /******************* Bit definition for CAN_FM1R register *******************/
|
|
|
2534 #define CAN_FM1R_FBM ((uint16_t)0x3FFFU) /*!<Filter Mode */
|
|
|
2535 #define CAN_FM1R_FBM0 ((uint16_t)0x0001U) /*!<Filter Init Mode bit 0 */
|
|
|
2536 #define CAN_FM1R_FBM1 ((uint16_t)0x0002U) /*!<Filter Init Mode bit 1 */
|
|
|
2537 #define CAN_FM1R_FBM2 ((uint16_t)0x0004U) /*!<Filter Init Mode bit 2 */
|
|
|
2538 #define CAN_FM1R_FBM3 ((uint16_t)0x0008U) /*!<Filter Init Mode bit 3 */
|
|
|
2539 #define CAN_FM1R_FBM4 ((uint16_t)0x0010U) /*!<Filter Init Mode bit 4 */
|
|
|
2540 #define CAN_FM1R_FBM5 ((uint16_t)0x0020U) /*!<Filter Init Mode bit 5 */
|
|
|
2541 #define CAN_FM1R_FBM6 ((uint16_t)0x0040U) /*!<Filter Init Mode bit 6 */
|
|
|
2542 #define CAN_FM1R_FBM7 ((uint16_t)0x0080U) /*!<Filter Init Mode bit 7 */
|
|
|
2543 #define CAN_FM1R_FBM8 ((uint16_t)0x0100U) /*!<Filter Init Mode bit 8 */
|
|
|
2544 #define CAN_FM1R_FBM9 ((uint16_t)0x0200U) /*!<Filter Init Mode bit 9 */
|
|
|
2545 #define CAN_FM1R_FBM10 ((uint16_t)0x0400U) /*!<Filter Init Mode bit 10 */
|
|
|
2546 #define CAN_FM1R_FBM11 ((uint16_t)0x0800U) /*!<Filter Init Mode bit 11 */
|
|
|
2547 #define CAN_FM1R_FBM12 ((uint16_t)0x1000U) /*!<Filter Init Mode bit 12 */
|
|
|
2548 #define CAN_FM1R_FBM13 ((uint16_t)0x2000U) /*!<Filter Init Mode bit 13 */
|
|
|
2549
|
|
|
2550 /******************* Bit definition for CAN_FS1R register *******************/
|
|
|
2551 #define CAN_FS1R_FSC ((uint16_t)0x3FFFU) /*!<Filter Scale Configuration */
|
|
|
2552 #define CAN_FS1R_FSC0 ((uint16_t)0x0001U) /*!<Filter Scale Configuration bit 0 */
|
|
|
2553 #define CAN_FS1R_FSC1 ((uint16_t)0x0002U) /*!<Filter Scale Configuration bit 1 */
|
|
|
2554 #define CAN_FS1R_FSC2 ((uint16_t)0x0004U) /*!<Filter Scale Configuration bit 2 */
|
|
|
2555 #define CAN_FS1R_FSC3 ((uint16_t)0x0008U) /*!<Filter Scale Configuration bit 3 */
|
|
|
2556 #define CAN_FS1R_FSC4 ((uint16_t)0x0010U) /*!<Filter Scale Configuration bit 4 */
|
|
|
2557 #define CAN_FS1R_FSC5 ((uint16_t)0x0020U) /*!<Filter Scale Configuration bit 5 */
|
|
|
2558 #define CAN_FS1R_FSC6 ((uint16_t)0x0040U) /*!<Filter Scale Configuration bit 6 */
|
|
|
2559 #define CAN_FS1R_FSC7 ((uint16_t)0x0080U) /*!<Filter Scale Configuration bit 7 */
|
|
|
2560 #define CAN_FS1R_FSC8 ((uint16_t)0x0100U) /*!<Filter Scale Configuration bit 8 */
|
|
|
2561 #define CAN_FS1R_FSC9 ((uint16_t)0x0200U) /*!<Filter Scale Configuration bit 9 */
|
|
|
2562 #define CAN_FS1R_FSC10 ((uint16_t)0x0400U) /*!<Filter Scale Configuration bit 10 */
|
|
|
2563 #define CAN_FS1R_FSC11 ((uint16_t)0x0800U) /*!<Filter Scale Configuration bit 11 */
|
|
|
2564 #define CAN_FS1R_FSC12 ((uint16_t)0x1000U) /*!<Filter Scale Configuration bit 12 */
|
|
|
2565 #define CAN_FS1R_FSC13 ((uint16_t)0x2000U) /*!<Filter Scale Configuration bit 13 */
|
|
|
2566
|
|
|
2567 /****************** Bit definition for CAN_FFA1R register *******************/
|
|
|
2568 #define CAN_FFA1R_FFA ((uint16_t)0x3FFFU) /*!<Filter FIFO Assignment */
|
|
|
2569 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001U) /*!<Filter FIFO Assignment for Filter 0 */
|
|
|
2570 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002U) /*!<Filter FIFO Assignment for Filter 1 */
|
|
|
2571 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004U) /*!<Filter FIFO Assignment for Filter 2 */
|
|
|
2572 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008U) /*!<Filter FIFO Assignment for Filter 3 */
|
|
|
2573 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010U) /*!<Filter FIFO Assignment for Filter 4 */
|
|
|
2574 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020U) /*!<Filter FIFO Assignment for Filter 5 */
|
|
|
2575 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040U) /*!<Filter FIFO Assignment for Filter 6 */
|
|
|
2576 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080U) /*!<Filter FIFO Assignment for Filter 7 */
|
|
|
2577 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100U) /*!<Filter FIFO Assignment for Filter 8 */
|
|
|
2578 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200U) /*!<Filter FIFO Assignment for Filter 9 */
|
|
|
2579 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400U) /*!<Filter FIFO Assignment for Filter 10 */
|
|
|
2580 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800U) /*!<Filter FIFO Assignment for Filter 11 */
|
|
|
2581 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000U) /*!<Filter FIFO Assignment for Filter 12 */
|
|
|
2582 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000U) /*!<Filter FIFO Assignment for Filter 13 */
|
|
|
2583
|
|
|
2584 /******************* Bit definition for CAN_FA1R register *******************/
|
|
|
2585 #define CAN_FA1R_FACT ((uint16_t)0x3FFFU) /*!<Filter Active */
|
|
|
2586 #define CAN_FA1R_FACT0 ((uint16_t)0x0001U) /*!<Filter 0 Active */
|
|
|
2587 #define CAN_FA1R_FACT1 ((uint16_t)0x0002U) /*!<Filter 1 Active */
|
|
|
2588 #define CAN_FA1R_FACT2 ((uint16_t)0x0004U) /*!<Filter 2 Active */
|
|
|
2589 #define CAN_FA1R_FACT3 ((uint16_t)0x0008U) /*!<Filter 3 Active */
|
|
|
2590 #define CAN_FA1R_FACT4 ((uint16_t)0x0010U) /*!<Filter 4 Active */
|
|
|
2591 #define CAN_FA1R_FACT5 ((uint16_t)0x0020U) /*!<Filter 5 Active */
|
|
|
2592 #define CAN_FA1R_FACT6 ((uint16_t)0x0040U) /*!<Filter 6 Active */
|
|
|
2593 #define CAN_FA1R_FACT7 ((uint16_t)0x0080U) /*!<Filter 7 Active */
|
|
|
2594 #define CAN_FA1R_FACT8 ((uint16_t)0x0100U) /*!<Filter 8 Active */
|
|
|
2595 #define CAN_FA1R_FACT9 ((uint16_t)0x0200U) /*!<Filter 9 Active */
|
|
|
2596 #define CAN_FA1R_FACT10 ((uint16_t)0x0400U) /*!<Filter 10 Active */
|
|
|
2597 #define CAN_FA1R_FACT11 ((uint16_t)0x0800U) /*!<Filter 11 Active */
|
|
|
2598 #define CAN_FA1R_FACT12 ((uint16_t)0x1000U) /*!<Filter 12 Active */
|
|
|
2599 #define CAN_FA1R_FACT13 ((uint16_t)0x2000U) /*!<Filter 13 Active */
|
|
|
2600
|
|
|
2601 /******************* Bit definition for CAN_F0R1 register *******************/
|
|
|
2602 #define CAN_F0R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2603 #define CAN_F0R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2604 #define CAN_F0R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2605 #define CAN_F0R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2606 #define CAN_F0R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2607 #define CAN_F0R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2608 #define CAN_F0R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2609 #define CAN_F0R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2610 #define CAN_F0R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2611 #define CAN_F0R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2612 #define CAN_F0R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2613 #define CAN_F0R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2614 #define CAN_F0R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2615 #define CAN_F0R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2616 #define CAN_F0R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2617 #define CAN_F0R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2618 #define CAN_F0R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2619 #define CAN_F0R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2620 #define CAN_F0R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2621 #define CAN_F0R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2622 #define CAN_F0R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2623 #define CAN_F0R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2624 #define CAN_F0R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2625 #define CAN_F0R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2626 #define CAN_F0R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2627 #define CAN_F0R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2628 #define CAN_F0R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2629 #define CAN_F0R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2630 #define CAN_F0R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2631 #define CAN_F0R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2632 #define CAN_F0R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2633 #define CAN_F0R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2634
|
|
|
2635 /******************* Bit definition for CAN_F1R1 register *******************/
|
|
|
2636 #define CAN_F1R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2637 #define CAN_F1R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2638 #define CAN_F1R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2639 #define CAN_F1R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2640 #define CAN_F1R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2641 #define CAN_F1R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2642 #define CAN_F1R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2643 #define CAN_F1R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2644 #define CAN_F1R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2645 #define CAN_F1R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2646 #define CAN_F1R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2647 #define CAN_F1R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2648 #define CAN_F1R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2649 #define CAN_F1R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2650 #define CAN_F1R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2651 #define CAN_F1R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2652 #define CAN_F1R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2653 #define CAN_F1R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2654 #define CAN_F1R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2655 #define CAN_F1R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2656 #define CAN_F1R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2657 #define CAN_F1R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2658 #define CAN_F1R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2659 #define CAN_F1R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2660 #define CAN_F1R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2661 #define CAN_F1R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2662 #define CAN_F1R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2663 #define CAN_F1R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2664 #define CAN_F1R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2665 #define CAN_F1R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2666 #define CAN_F1R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2667 #define CAN_F1R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2668
|
|
|
2669 /******************* Bit definition for CAN_F2R1 register *******************/
|
|
|
2670 #define CAN_F2R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2671 #define CAN_F2R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2672 #define CAN_F2R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2673 #define CAN_F2R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2674 #define CAN_F2R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2675 #define CAN_F2R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2676 #define CAN_F2R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2677 #define CAN_F2R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2678 #define CAN_F2R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2679 #define CAN_F2R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2680 #define CAN_F2R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2681 #define CAN_F2R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2682 #define CAN_F2R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2683 #define CAN_F2R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2684 #define CAN_F2R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2685 #define CAN_F2R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2686 #define CAN_F2R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2687 #define CAN_F2R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2688 #define CAN_F2R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2689 #define CAN_F2R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2690 #define CAN_F2R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2691 #define CAN_F2R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2692 #define CAN_F2R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2693 #define CAN_F2R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2694 #define CAN_F2R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2695 #define CAN_F2R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2696 #define CAN_F2R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2697 #define CAN_F2R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2698 #define CAN_F2R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2699 #define CAN_F2R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2700 #define CAN_F2R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2701 #define CAN_F2R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2702
|
|
|
2703 /******************* Bit definition for CAN_F3R1 register *******************/
|
|
|
2704 #define CAN_F3R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2705 #define CAN_F3R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2706 #define CAN_F3R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2707 #define CAN_F3R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2708 #define CAN_F3R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2709 #define CAN_F3R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2710 #define CAN_F3R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2711 #define CAN_F3R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2712 #define CAN_F3R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2713 #define CAN_F3R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2714 #define CAN_F3R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2715 #define CAN_F3R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2716 #define CAN_F3R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2717 #define CAN_F3R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2718 #define CAN_F3R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2719 #define CAN_F3R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2720 #define CAN_F3R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2721 #define CAN_F3R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2722 #define CAN_F3R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2723 #define CAN_F3R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2724 #define CAN_F3R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2725 #define CAN_F3R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2726 #define CAN_F3R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2727 #define CAN_F3R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2728 #define CAN_F3R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2729 #define CAN_F3R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2730 #define CAN_F3R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2731 #define CAN_F3R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2732 #define CAN_F3R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2733 #define CAN_F3R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2734 #define CAN_F3R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2735 #define CAN_F3R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2736
|
|
|
2737 /******************* Bit definition for CAN_F4R1 register *******************/
|
|
|
2738 #define CAN_F4R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2739 #define CAN_F4R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2740 #define CAN_F4R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2741 #define CAN_F4R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2742 #define CAN_F4R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2743 #define CAN_F4R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2744 #define CAN_F4R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2745 #define CAN_F4R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2746 #define CAN_F4R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2747 #define CAN_F4R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2748 #define CAN_F4R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2749 #define CAN_F4R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2750 #define CAN_F4R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2751 #define CAN_F4R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2752 #define CAN_F4R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2753 #define CAN_F4R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2754 #define CAN_F4R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2755 #define CAN_F4R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2756 #define CAN_F4R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2757 #define CAN_F4R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2758 #define CAN_F4R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2759 #define CAN_F4R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2760 #define CAN_F4R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2761 #define CAN_F4R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2762 #define CAN_F4R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2763 #define CAN_F4R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2764 #define CAN_F4R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2765 #define CAN_F4R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2766 #define CAN_F4R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2767 #define CAN_F4R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2768 #define CAN_F4R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2769 #define CAN_F4R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2770
|
|
|
2771 /******************* Bit definition for CAN_F5R1 register *******************/
|
|
|
2772 #define CAN_F5R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2773 #define CAN_F5R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2774 #define CAN_F5R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2775 #define CAN_F5R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2776 #define CAN_F5R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2777 #define CAN_F5R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2778 #define CAN_F5R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2779 #define CAN_F5R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2780 #define CAN_F5R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2781 #define CAN_F5R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2782 #define CAN_F5R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2783 #define CAN_F5R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2784 #define CAN_F5R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2785 #define CAN_F5R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2786 #define CAN_F5R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2787 #define CAN_F5R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2788 #define CAN_F5R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2789 #define CAN_F5R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2790 #define CAN_F5R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2791 #define CAN_F5R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2792 #define CAN_F5R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2793 #define CAN_F5R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2794 #define CAN_F5R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2795 #define CAN_F5R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2796 #define CAN_F5R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2797 #define CAN_F5R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2798 #define CAN_F5R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2799 #define CAN_F5R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2800 #define CAN_F5R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2801 #define CAN_F5R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2802 #define CAN_F5R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2803 #define CAN_F5R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2804
|
|
|
2805 /******************* Bit definition for CAN_F6R1 register *******************/
|
|
|
2806 #define CAN_F6R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2807 #define CAN_F6R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2808 #define CAN_F6R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2809 #define CAN_F6R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2810 #define CAN_F6R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2811 #define CAN_F6R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2812 #define CAN_F6R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2813 #define CAN_F6R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2814 #define CAN_F6R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2815 #define CAN_F6R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2816 #define CAN_F6R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2817 #define CAN_F6R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2818 #define CAN_F6R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2819 #define CAN_F6R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2820 #define CAN_F6R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2821 #define CAN_F6R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2822 #define CAN_F6R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2823 #define CAN_F6R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2824 #define CAN_F6R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2825 #define CAN_F6R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2826 #define CAN_F6R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2827 #define CAN_F6R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2828 #define CAN_F6R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2829 #define CAN_F6R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2830 #define CAN_F6R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2831 #define CAN_F6R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2832 #define CAN_F6R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2833 #define CAN_F6R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2834 #define CAN_F6R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2835 #define CAN_F6R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2836 #define CAN_F6R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2837 #define CAN_F6R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2838
|
|
|
2839 /******************* Bit definition for CAN_F7R1 register *******************/
|
|
|
2840 #define CAN_F7R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2841 #define CAN_F7R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2842 #define CAN_F7R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2843 #define CAN_F7R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2844 #define CAN_F7R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2845 #define CAN_F7R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2846 #define CAN_F7R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2847 #define CAN_F7R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2848 #define CAN_F7R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2849 #define CAN_F7R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2850 #define CAN_F7R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2851 #define CAN_F7R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2852 #define CAN_F7R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2853 #define CAN_F7R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2854 #define CAN_F7R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2855 #define CAN_F7R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2856 #define CAN_F7R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2857 #define CAN_F7R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2858 #define CAN_F7R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2859 #define CAN_F7R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2860 #define CAN_F7R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2861 #define CAN_F7R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2862 #define CAN_F7R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2863 #define CAN_F7R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2864 #define CAN_F7R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2865 #define CAN_F7R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2866 #define CAN_F7R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2867 #define CAN_F7R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2868 #define CAN_F7R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2869 #define CAN_F7R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2870 #define CAN_F7R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2871 #define CAN_F7R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2872
|
|
|
2873 /******************* Bit definition for CAN_F8R1 register *******************/
|
|
|
2874 #define CAN_F8R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2875 #define CAN_F8R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2876 #define CAN_F8R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2877 #define CAN_F8R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2878 #define CAN_F8R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2879 #define CAN_F8R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2880 #define CAN_F8R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2881 #define CAN_F8R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2882 #define CAN_F8R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2883 #define CAN_F8R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2884 #define CAN_F8R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2885 #define CAN_F8R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2886 #define CAN_F8R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2887 #define CAN_F8R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2888 #define CAN_F8R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2889 #define CAN_F8R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2890 #define CAN_F8R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2891 #define CAN_F8R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2892 #define CAN_F8R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2893 #define CAN_F8R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2894 #define CAN_F8R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2895 #define CAN_F8R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2896 #define CAN_F8R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2897 #define CAN_F8R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2898 #define CAN_F8R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2899 #define CAN_F8R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2900 #define CAN_F8R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2901 #define CAN_F8R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2902 #define CAN_F8R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2903 #define CAN_F8R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2904 #define CAN_F8R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2905 #define CAN_F8R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2906
|
|
|
2907 /******************* Bit definition for CAN_F9R1 register *******************/
|
|
|
2908 #define CAN_F9R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2909 #define CAN_F9R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2910 #define CAN_F9R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2911 #define CAN_F9R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2912 #define CAN_F9R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2913 #define CAN_F9R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2914 #define CAN_F9R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2915 #define CAN_F9R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2916 #define CAN_F9R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2917 #define CAN_F9R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2918 #define CAN_F9R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2919 #define CAN_F9R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2920 #define CAN_F9R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2921 #define CAN_F9R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2922 #define CAN_F9R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2923 #define CAN_F9R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2924 #define CAN_F9R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2925 #define CAN_F9R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2926 #define CAN_F9R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2927 #define CAN_F9R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2928 #define CAN_F9R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2929 #define CAN_F9R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2930 #define CAN_F9R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2931 #define CAN_F9R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2932 #define CAN_F9R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2933 #define CAN_F9R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2934 #define CAN_F9R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2935 #define CAN_F9R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2936 #define CAN_F9R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2937 #define CAN_F9R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2938 #define CAN_F9R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2939 #define CAN_F9R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2940
|
|
|
2941 /******************* Bit definition for CAN_F10R1 register ******************/
|
|
|
2942 #define CAN_F10R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2943 #define CAN_F10R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2944 #define CAN_F10R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2945 #define CAN_F10R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2946 #define CAN_F10R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2947 #define CAN_F10R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2948 #define CAN_F10R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2949 #define CAN_F10R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2950 #define CAN_F10R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2951 #define CAN_F10R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2952 #define CAN_F10R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2953 #define CAN_F10R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2954 #define CAN_F10R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2955 #define CAN_F10R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2956 #define CAN_F10R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2957 #define CAN_F10R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2958 #define CAN_F10R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2959 #define CAN_F10R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2960 #define CAN_F10R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2961 #define CAN_F10R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2962 #define CAN_F10R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2963 #define CAN_F10R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2964 #define CAN_F10R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2965 #define CAN_F10R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
2966 #define CAN_F10R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
2967 #define CAN_F10R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
2968 #define CAN_F10R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
2969 #define CAN_F10R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
2970 #define CAN_F10R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
2971 #define CAN_F10R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
2972 #define CAN_F10R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
2973 #define CAN_F10R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
2974
|
|
|
2975 /******************* Bit definition for CAN_F11R1 register ******************/
|
|
|
2976 #define CAN_F11R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
2977 #define CAN_F11R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
2978 #define CAN_F11R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
2979 #define CAN_F11R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
2980 #define CAN_F11R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
2981 #define CAN_F11R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
2982 #define CAN_F11R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
2983 #define CAN_F11R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
2984 #define CAN_F11R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
2985 #define CAN_F11R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
2986 #define CAN_F11R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
2987 #define CAN_F11R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
2988 #define CAN_F11R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
2989 #define CAN_F11R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
2990 #define CAN_F11R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
2991 #define CAN_F11R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
2992 #define CAN_F11R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
2993 #define CAN_F11R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
2994 #define CAN_F11R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
2995 #define CAN_F11R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
2996 #define CAN_F11R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
2997 #define CAN_F11R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
2998 #define CAN_F11R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
2999 #define CAN_F11R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3000 #define CAN_F11R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3001 #define CAN_F11R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3002 #define CAN_F11R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3003 #define CAN_F11R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3004 #define CAN_F11R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3005 #define CAN_F11R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3006 #define CAN_F11R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3007 #define CAN_F11R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3008
|
|
|
3009 /******************* Bit definition for CAN_F12R1 register ******************/
|
|
|
3010 #define CAN_F12R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3011 #define CAN_F12R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3012 #define CAN_F12R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3013 #define CAN_F12R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3014 #define CAN_F12R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3015 #define CAN_F12R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3016 #define CAN_F12R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3017 #define CAN_F12R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3018 #define CAN_F12R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3019 #define CAN_F12R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3020 #define CAN_F12R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3021 #define CAN_F12R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3022 #define CAN_F12R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3023 #define CAN_F12R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3024 #define CAN_F12R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3025 #define CAN_F12R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3026 #define CAN_F12R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3027 #define CAN_F12R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3028 #define CAN_F12R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3029 #define CAN_F12R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3030 #define CAN_F12R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3031 #define CAN_F12R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3032 #define CAN_F12R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3033 #define CAN_F12R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3034 #define CAN_F12R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3035 #define CAN_F12R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3036 #define CAN_F12R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3037 #define CAN_F12R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3038 #define CAN_F12R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3039 #define CAN_F12R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3040 #define CAN_F12R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3041 #define CAN_F12R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3042
|
|
|
3043 /******************* Bit definition for CAN_F13R1 register ******************/
|
|
|
3044 #define CAN_F13R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3045 #define CAN_F13R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3046 #define CAN_F13R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3047 #define CAN_F13R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3048 #define CAN_F13R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3049 #define CAN_F13R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3050 #define CAN_F13R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3051 #define CAN_F13R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3052 #define CAN_F13R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3053 #define CAN_F13R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3054 #define CAN_F13R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3055 #define CAN_F13R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3056 #define CAN_F13R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3057 #define CAN_F13R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3058 #define CAN_F13R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3059 #define CAN_F13R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3060 #define CAN_F13R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3061 #define CAN_F13R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3062 #define CAN_F13R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3063 #define CAN_F13R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3064 #define CAN_F13R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3065 #define CAN_F13R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3066 #define CAN_F13R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3067 #define CAN_F13R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3068 #define CAN_F13R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3069 #define CAN_F13R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3070 #define CAN_F13R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3071 #define CAN_F13R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3072 #define CAN_F13R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3073 #define CAN_F13R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3074 #define CAN_F13R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3075 #define CAN_F13R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3076
|
|
|
3077 /******************* Bit definition for CAN_F0R2 register *******************/
|
|
|
3078 #define CAN_F0R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3079 #define CAN_F0R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3080 #define CAN_F0R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3081 #define CAN_F0R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3082 #define CAN_F0R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3083 #define CAN_F0R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3084 #define CAN_F0R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3085 #define CAN_F0R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3086 #define CAN_F0R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3087 #define CAN_F0R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3088 #define CAN_F0R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3089 #define CAN_F0R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3090 #define CAN_F0R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3091 #define CAN_F0R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3092 #define CAN_F0R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3093 #define CAN_F0R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3094 #define CAN_F0R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3095 #define CAN_F0R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3096 #define CAN_F0R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3097 #define CAN_F0R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3098 #define CAN_F0R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3099 #define CAN_F0R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3100 #define CAN_F0R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3101 #define CAN_F0R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3102 #define CAN_F0R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3103 #define CAN_F0R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3104 #define CAN_F0R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3105 #define CAN_F0R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3106 #define CAN_F0R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3107 #define CAN_F0R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3108 #define CAN_F0R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3109 #define CAN_F0R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3110
|
|
|
3111 /******************* Bit definition for CAN_F1R2 register *******************/
|
|
|
3112 #define CAN_F1R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3113 #define CAN_F1R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3114 #define CAN_F1R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3115 #define CAN_F1R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3116 #define CAN_F1R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3117 #define CAN_F1R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3118 #define CAN_F1R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3119 #define CAN_F1R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3120 #define CAN_F1R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3121 #define CAN_F1R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3122 #define CAN_F1R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3123 #define CAN_F1R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3124 #define CAN_F1R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3125 #define CAN_F1R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3126 #define CAN_F1R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3127 #define CAN_F1R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3128 #define CAN_F1R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3129 #define CAN_F1R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3130 #define CAN_F1R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3131 #define CAN_F1R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3132 #define CAN_F1R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3133 #define CAN_F1R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3134 #define CAN_F1R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3135 #define CAN_F1R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3136 #define CAN_F1R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3137 #define CAN_F1R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3138 #define CAN_F1R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3139 #define CAN_F1R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3140 #define CAN_F1R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3141 #define CAN_F1R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3142 #define CAN_F1R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3143 #define CAN_F1R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3144
|
|
|
3145 /******************* Bit definition for CAN_F2R2 register *******************/
|
|
|
3146 #define CAN_F2R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3147 #define CAN_F2R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3148 #define CAN_F2R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3149 #define CAN_F2R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3150 #define CAN_F2R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3151 #define CAN_F2R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3152 #define CAN_F2R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3153 #define CAN_F2R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3154 #define CAN_F2R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3155 #define CAN_F2R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3156 #define CAN_F2R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3157 #define CAN_F2R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3158 #define CAN_F2R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3159 #define CAN_F2R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3160 #define CAN_F2R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3161 #define CAN_F2R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3162 #define CAN_F2R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3163 #define CAN_F2R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3164 #define CAN_F2R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3165 #define CAN_F2R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3166 #define CAN_F2R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3167 #define CAN_F2R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3168 #define CAN_F2R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3169 #define CAN_F2R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3170 #define CAN_F2R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3171 #define CAN_F2R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3172 #define CAN_F2R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3173 #define CAN_F2R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3174 #define CAN_F2R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3175 #define CAN_F2R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3176 #define CAN_F2R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3177 #define CAN_F2R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3178
|
|
|
3179 /******************* Bit definition for CAN_F3R2 register *******************/
|
|
|
3180 #define CAN_F3R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3181 #define CAN_F3R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3182 #define CAN_F3R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3183 #define CAN_F3R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3184 #define CAN_F3R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3185 #define CAN_F3R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3186 #define CAN_F3R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3187 #define CAN_F3R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3188 #define CAN_F3R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3189 #define CAN_F3R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3190 #define CAN_F3R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3191 #define CAN_F3R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3192 #define CAN_F3R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3193 #define CAN_F3R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3194 #define CAN_F3R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3195 #define CAN_F3R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3196 #define CAN_F3R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3197 #define CAN_F3R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3198 #define CAN_F3R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3199 #define CAN_F3R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3200 #define CAN_F3R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3201 #define CAN_F3R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3202 #define CAN_F3R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3203 #define CAN_F3R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3204 #define CAN_F3R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3205 #define CAN_F3R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3206 #define CAN_F3R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3207 #define CAN_F3R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3208 #define CAN_F3R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3209 #define CAN_F3R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3210 #define CAN_F3R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3211 #define CAN_F3R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3212
|
|
|
3213 /******************* Bit definition for CAN_F4R2 register *******************/
|
|
|
3214 #define CAN_F4R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3215 #define CAN_F4R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3216 #define CAN_F4R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3217 #define CAN_F4R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3218 #define CAN_F4R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3219 #define CAN_F4R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3220 #define CAN_F4R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3221 #define CAN_F4R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3222 #define CAN_F4R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3223 #define CAN_F4R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3224 #define CAN_F4R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3225 #define CAN_F4R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3226 #define CAN_F4R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3227 #define CAN_F4R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3228 #define CAN_F4R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3229 #define CAN_F4R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3230 #define CAN_F4R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3231 #define CAN_F4R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3232 #define CAN_F4R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3233 #define CAN_F4R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3234 #define CAN_F4R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3235 #define CAN_F4R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3236 #define CAN_F4R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3237 #define CAN_F4R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3238 #define CAN_F4R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3239 #define CAN_F4R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3240 #define CAN_F4R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3241 #define CAN_F4R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3242 #define CAN_F4R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3243 #define CAN_F4R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3244 #define CAN_F4R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3245 #define CAN_F4R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3246
|
|
|
3247 /******************* Bit definition for CAN_F5R2 register *******************/
|
|
|
3248 #define CAN_F5R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3249 #define CAN_F5R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3250 #define CAN_F5R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3251 #define CAN_F5R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3252 #define CAN_F5R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3253 #define CAN_F5R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3254 #define CAN_F5R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3255 #define CAN_F5R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3256 #define CAN_F5R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3257 #define CAN_F5R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3258 #define CAN_F5R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3259 #define CAN_F5R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3260 #define CAN_F5R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3261 #define CAN_F5R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3262 #define CAN_F5R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3263 #define CAN_F5R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3264 #define CAN_F5R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3265 #define CAN_F5R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3266 #define CAN_F5R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3267 #define CAN_F5R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3268 #define CAN_F5R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3269 #define CAN_F5R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3270 #define CAN_F5R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3271 #define CAN_F5R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3272 #define CAN_F5R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3273 #define CAN_F5R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3274 #define CAN_F5R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3275 #define CAN_F5R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3276 #define CAN_F5R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3277 #define CAN_F5R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3278 #define CAN_F5R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3279 #define CAN_F5R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3280
|
|
|
3281 /******************* Bit definition for CAN_F6R2 register *******************/
|
|
|
3282 #define CAN_F6R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3283 #define CAN_F6R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3284 #define CAN_F6R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3285 #define CAN_F6R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3286 #define CAN_F6R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3287 #define CAN_F6R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3288 #define CAN_F6R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3289 #define CAN_F6R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3290 #define CAN_F6R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3291 #define CAN_F6R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3292 #define CAN_F6R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3293 #define CAN_F6R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3294 #define CAN_F6R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3295 #define CAN_F6R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3296 #define CAN_F6R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3297 #define CAN_F6R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3298 #define CAN_F6R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3299 #define CAN_F6R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3300 #define CAN_F6R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3301 #define CAN_F6R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3302 #define CAN_F6R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3303 #define CAN_F6R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3304 #define CAN_F6R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3305 #define CAN_F6R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3306 #define CAN_F6R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3307 #define CAN_F6R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3308 #define CAN_F6R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3309 #define CAN_F6R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3310 #define CAN_F6R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3311 #define CAN_F6R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3312 #define CAN_F6R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3313 #define CAN_F6R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3314
|
|
|
3315 /******************* Bit definition for CAN_F7R2 register *******************/
|
|
|
3316 #define CAN_F7R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3317 #define CAN_F7R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3318 #define CAN_F7R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3319 #define CAN_F7R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3320 #define CAN_F7R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3321 #define CAN_F7R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3322 #define CAN_F7R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3323 #define CAN_F7R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3324 #define CAN_F7R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3325 #define CAN_F7R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3326 #define CAN_F7R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3327 #define CAN_F7R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3328 #define CAN_F7R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3329 #define CAN_F7R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3330 #define CAN_F7R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3331 #define CAN_F7R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3332 #define CAN_F7R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3333 #define CAN_F7R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3334 #define CAN_F7R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3335 #define CAN_F7R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3336 #define CAN_F7R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3337 #define CAN_F7R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3338 #define CAN_F7R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3339 #define CAN_F7R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3340 #define CAN_F7R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3341 #define CAN_F7R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3342 #define CAN_F7R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3343 #define CAN_F7R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3344 #define CAN_F7R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3345 #define CAN_F7R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3346 #define CAN_F7R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3347 #define CAN_F7R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3348
|
|
|
3349 /******************* Bit definition for CAN_F8R2 register *******************/
|
|
|
3350 #define CAN_F8R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3351 #define CAN_F8R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3352 #define CAN_F8R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3353 #define CAN_F8R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3354 #define CAN_F8R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3355 #define CAN_F8R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3356 #define CAN_F8R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3357 #define CAN_F8R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3358 #define CAN_F8R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3359 #define CAN_F8R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3360 #define CAN_F8R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3361 #define CAN_F8R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3362 #define CAN_F8R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3363 #define CAN_F8R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3364 #define CAN_F8R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3365 #define CAN_F8R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3366 #define CAN_F8R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3367 #define CAN_F8R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3368 #define CAN_F8R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3369 #define CAN_F8R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3370 #define CAN_F8R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3371 #define CAN_F8R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3372 #define CAN_F8R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3373 #define CAN_F8R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3374 #define CAN_F8R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3375 #define CAN_F8R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3376 #define CAN_F8R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3377 #define CAN_F8R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3378 #define CAN_F8R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3379 #define CAN_F8R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3380 #define CAN_F8R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3381 #define CAN_F8R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3382
|
|
|
3383 /******************* Bit definition for CAN_F9R2 register *******************/
|
|
|
3384 #define CAN_F9R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3385 #define CAN_F9R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3386 #define CAN_F9R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3387 #define CAN_F9R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3388 #define CAN_F9R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3389 #define CAN_F9R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3390 #define CAN_F9R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3391 #define CAN_F9R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3392 #define CAN_F9R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3393 #define CAN_F9R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3394 #define CAN_F9R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3395 #define CAN_F9R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3396 #define CAN_F9R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3397 #define CAN_F9R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3398 #define CAN_F9R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3399 #define CAN_F9R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3400 #define CAN_F9R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3401 #define CAN_F9R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3402 #define CAN_F9R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3403 #define CAN_F9R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3404 #define CAN_F9R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3405 #define CAN_F9R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3406 #define CAN_F9R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3407 #define CAN_F9R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3408 #define CAN_F9R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3409 #define CAN_F9R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3410 #define CAN_F9R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3411 #define CAN_F9R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3412 #define CAN_F9R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3413 #define CAN_F9R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3414 #define CAN_F9R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3415 #define CAN_F9R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3416
|
|
|
3417 /******************* Bit definition for CAN_F10R2 register ******************/
|
|
|
3418 #define CAN_F10R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3419 #define CAN_F10R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3420 #define CAN_F10R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3421 #define CAN_F10R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3422 #define CAN_F10R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3423 #define CAN_F10R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3424 #define CAN_F10R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3425 #define CAN_F10R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3426 #define CAN_F10R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3427 #define CAN_F10R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3428 #define CAN_F10R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3429 #define CAN_F10R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3430 #define CAN_F10R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3431 #define CAN_F10R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3432 #define CAN_F10R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3433 #define CAN_F10R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3434 #define CAN_F10R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3435 #define CAN_F10R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3436 #define CAN_F10R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3437 #define CAN_F10R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3438 #define CAN_F10R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3439 #define CAN_F10R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3440 #define CAN_F10R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3441 #define CAN_F10R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3442 #define CAN_F10R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3443 #define CAN_F10R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3444 #define CAN_F10R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3445 #define CAN_F10R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3446 #define CAN_F10R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3447 #define CAN_F10R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3448 #define CAN_F10R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3449 #define CAN_F10R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3450
|
|
|
3451 /******************* Bit definition for CAN_F11R2 register ******************/
|
|
|
3452 #define CAN_F11R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3453 #define CAN_F11R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3454 #define CAN_F11R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3455 #define CAN_F11R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3456 #define CAN_F11R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3457 #define CAN_F11R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3458 #define CAN_F11R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3459 #define CAN_F11R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3460 #define CAN_F11R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3461 #define CAN_F11R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3462 #define CAN_F11R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3463 #define CAN_F11R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3464 #define CAN_F11R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3465 #define CAN_F11R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3466 #define CAN_F11R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3467 #define CAN_F11R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3468 #define CAN_F11R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3469 #define CAN_F11R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3470 #define CAN_F11R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3471 #define CAN_F11R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3472 #define CAN_F11R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3473 #define CAN_F11R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3474 #define CAN_F11R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3475 #define CAN_F11R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3476 #define CAN_F11R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3477 #define CAN_F11R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3478 #define CAN_F11R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3479 #define CAN_F11R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3480 #define CAN_F11R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3481 #define CAN_F11R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3482 #define CAN_F11R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3483 #define CAN_F11R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3484
|
|
|
3485 /******************* Bit definition for CAN_F12R2 register ******************/
|
|
|
3486 #define CAN_F12R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3487 #define CAN_F12R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3488 #define CAN_F12R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3489 #define CAN_F12R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3490 #define CAN_F12R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3491 #define CAN_F12R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3492 #define CAN_F12R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3493 #define CAN_F12R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3494 #define CAN_F12R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3495 #define CAN_F12R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3496 #define CAN_F12R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3497 #define CAN_F12R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3498 #define CAN_F12R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3499 #define CAN_F12R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3500 #define CAN_F12R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3501 #define CAN_F12R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3502 #define CAN_F12R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3503 #define CAN_F12R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3504 #define CAN_F12R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3505 #define CAN_F12R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3506 #define CAN_F12R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3507 #define CAN_F12R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3508 #define CAN_F12R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3509 #define CAN_F12R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3510 #define CAN_F12R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3511 #define CAN_F12R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3512 #define CAN_F12R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3513 #define CAN_F12R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3514 #define CAN_F12R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3515 #define CAN_F12R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3516 #define CAN_F12R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3517 #define CAN_F12R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3518
|
|
|
3519 /******************* Bit definition for CAN_F13R2 register ******************/
|
|
|
3520 #define CAN_F13R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
|
|
|
3521 #define CAN_F13R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
|
|
|
3522 #define CAN_F13R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
|
|
|
3523 #define CAN_F13R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
|
|
|
3524 #define CAN_F13R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
|
|
|
3525 #define CAN_F13R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
|
|
|
3526 #define CAN_F13R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
|
|
|
3527 #define CAN_F13R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
|
|
|
3528 #define CAN_F13R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
|
|
|
3529 #define CAN_F13R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
|
|
|
3530 #define CAN_F13R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
|
|
|
3531 #define CAN_F13R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
|
|
|
3532 #define CAN_F13R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
|
|
|
3533 #define CAN_F13R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
|
|
|
3534 #define CAN_F13R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
|
|
|
3535 #define CAN_F13R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
|
|
|
3536 #define CAN_F13R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
|
|
|
3537 #define CAN_F13R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
|
|
|
3538 #define CAN_F13R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
|
|
|
3539 #define CAN_F13R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
|
|
|
3540 #define CAN_F13R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
|
|
|
3541 #define CAN_F13R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
|
|
|
3542 #define CAN_F13R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
|
|
|
3543 #define CAN_F13R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
|
|
|
3544 #define CAN_F13R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
|
|
|
3545 #define CAN_F13R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
|
|
|
3546 #define CAN_F13R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
|
|
|
3547 #define CAN_F13R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
|
|
|
3548 #define CAN_F13R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
|
|
|
3549 #define CAN_F13R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
|
|
|
3550 #define CAN_F13R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
|
|
|
3551 #define CAN_F13R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
|
|
|
3552
|
|
|
3553 /******************************************************************************/
|
|
|
3554 /* */
|
|
|
3555 /* CRC calculation unit */
|
|
|
3556 /* */
|
|
|
3557 /******************************************************************************/
|
|
|
3558 /******************* Bit definition for CRC_DR register *********************/
|
|
|
3559 #define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
|
|
|
3560
|
|
|
3561 /******************* Bit definition for CRC_IDR register ********************/
|
|
|
3562 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
|
|
|
3563
|
|
|
3564 /******************** Bit definition for CRC_CR register ********************/
|
|
|
3565 #define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
|
|
|
3566 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */
|
|
|
3567 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
|
|
|
3568 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
|
|
|
3569 #define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
|
|
|
3570 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
|
|
|
3571 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
|
|
|
3572 #define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
|
|
|
3573
|
|
|
3574 /******************* Bit definition for CRC_INIT register *******************/
|
|
|
3575 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
|
|
|
3576
|
|
|
3577 /******************* Bit definition for CRC_POL register ********************/
|
|
|
3578 #define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
|
|
|
3579
|
|
|
3580 /******************************************************************************/
|
|
|
3581 /* */
|
|
|
3582 /* Digital to Analog Converter */
|
|
|
3583 /* */
|
|
|
3584 /******************************************************************************/
|
|
|
3585 /******************** Bit definition for DAC_CR register ********************/
|
|
|
3586 #define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!<DAC channel1 enable */
|
|
|
3587 #define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!<DAC channel1 Trigger enable */
|
|
|
3588
|
|
|
3589 #define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
|
|
|
3590 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
|
|
|
3591 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
|
|
|
3592 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
|
|
|
3593
|
|
|
3594 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
|
|
|
3595 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
|
|
|
3596 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
|
|
|
3597
|
|
|
3598 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
|
|
|
3599 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
3600 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
3601 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
3602 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
3603
|
|
|
3604 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!<DAC channel1 DMA enable */
|
|
|
3605 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!<DAC channel 1 DMA underrun interrupt enable >*/
|
|
|
3606 #define DAC_CR_CEN1 ((uint32_t)0x00004000U) /*!<DAC channel 1 calibration enable >*/
|
|
|
3607
|
|
|
3608 #define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!<DAC channel2 enable */
|
|
|
3609 #define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!<DAC channel2 Trigger enable */
|
|
|
3610
|
|
|
3611 #define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
|
|
|
3612 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!<Bit 0 */
|
|
|
3613 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!<Bit 1 */
|
|
|
3614 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!<Bit 2 */
|
|
|
3615
|
|
|
3616 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
|
|
|
3617 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
|
|
|
3618 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
|
|
|
3619
|
|
|
3620 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
|
|
|
3621 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
3622 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
3623 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
3624 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
3625
|
|
|
3626 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!<DAC channel2 DMA enabled */
|
|
|
3627 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun interrupt enable >*/
|
|
|
3628 #define DAC_CR_CEN2 ((uint32_t)0x40000000U) /*!<DAC channel2 calibration enable >*/
|
|
|
3629
|
|
|
3630 /***************** Bit definition for DAC_SWTRIGR register ******************/
|
|
|
3631 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!<DAC channel1 software trigger */
|
|
|
3632 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!<DAC channel2 software trigger */
|
|
|
3633
|
|
|
3634 /***************** Bit definition for DAC_DHR12R1 register ******************/
|
|
|
3635 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
|
|
|
3636
|
|
|
3637 /***************** Bit definition for DAC_DHR12L1 register ******************/
|
|
|
3638 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
|
|
|
3639
|
|
|
3640 /****************** Bit definition for DAC_DHR8R1 register ******************/
|
|
|
3641 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
|
|
|
3642
|
|
|
3643 /***************** Bit definition for DAC_DHR12R2 register ******************/
|
|
|
3644 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!<DAC channel2 12-bit Right aligned data */
|
|
|
3645
|
|
|
3646 /***************** Bit definition for DAC_DHR12L2 register ******************/
|
|
|
3647 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel2 12-bit Left aligned data */
|
|
|
3648
|
|
|
3649 /****************** Bit definition for DAC_DHR8R2 register ******************/
|
|
|
3650 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!<DAC channel2 8-bit Right aligned data */
|
|
|
3651
|
|
|
3652 /***************** Bit definition for DAC_DHR12RD register ******************/
|
|
|
3653 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
|
|
|
3654 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!<DAC channel2 12-bit Right aligned data */
|
|
|
3655
|
|
|
3656 /***************** Bit definition for DAC_DHR12LD register ******************/
|
|
|
3657 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
|
|
|
3658 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!<DAC channel2 12-bit Left aligned data */
|
|
|
3659
|
|
|
3660 /****************** Bit definition for DAC_DHR8RD register ******************/
|
|
|
3661 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
|
|
|
3662 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!<DAC channel2 8-bit Right aligned data */
|
|
|
3663
|
|
|
3664 /******************* Bit definition for DAC_DOR1 register *******************/
|
|
|
3665 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFFU) /*!<DAC channel1 data output */
|
|
|
3666
|
|
|
3667 /******************* Bit definition for DAC_DOR2 register *******************/
|
|
|
3668 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFFU) /*!<DAC channel2 data output */
|
|
|
3669
|
|
|
3670 /******************** Bit definition for DAC_SR register ********************/
|
|
|
3671 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!<DAC channel1 DMA underrun flag */
|
|
|
3672 #define DAC_SR_CAL_FLAG1 ((uint32_t)0x00004000U) /*!<DAC channel1 calibration offset status */
|
|
|
3673 #define DAC_SR_BWST1 ((uint32_t)0x20008000U) /*!<DAC channel1 busy writing sample time flag */
|
|
|
3674
|
|
|
3675 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun flag */
|
|
|
3676 #define DAC_SR_CAL_FLAG2 ((uint32_t)0x40000000U) /*!<DAC channel2 calibration offset status */
|
|
|
3677 #define DAC_SR_BWST2 ((uint32_t)0x80000000U) /*!<DAC channel2 busy writing sample time flag */
|
|
|
3678
|
|
|
3679 /******************* Bit definition for DAC_CCR register ********************/
|
|
|
3680 #define DAC_CCR_OTRIM1 ((uint32_t)0x0000001FU) /*!<DAC channel1 offset trimming value */
|
|
|
3681 #define DAC_CCR_OTRIM2 ((uint32_t)0x001F0000U) /*!<DAC channel2 offset trimming value */
|
|
|
3682
|
|
|
3683 /******************* Bit definition for DAC_MCR register *******************/
|
|
|
3684 #define DAC_MCR_MODE1 ((uint32_t)0x00000007U) /*!<MODE1[2:0] (DAC channel1 mode) */
|
|
|
3685 #define DAC_MCR_MODE1_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
3686 #define DAC_MCR_MODE1_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
3687 #define DAC_MCR_MODE1_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
3688
|
|
|
3689 #define DAC_MCR_MODE2 ((uint32_t)0x00070000U) /*!<MODE2[2:0] (DAC channel2 mode) */
|
|
|
3690 #define DAC_MCR_MODE2_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
3691 #define DAC_MCR_MODE2_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
3692 #define DAC_MCR_MODE2_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
3693
|
|
|
3694 /****************** Bit definition for DAC_SHSR1 register ******************/
|
|
|
3695 #define DAC_SHSR1_TSAMPLE1 ((uint32_t)0x000003FFU) /*!<DAC channel1 sample time */
|
|
|
3696
|
|
|
3697 /****************** Bit definition for DAC_SHSR2 register ******************/
|
|
|
3698 #define DAC_SHSR2_TSAMPLE2 ((uint32_t)0x000003FFU) /*!<DAC channel2 sample time */
|
|
|
3699
|
|
|
3700 /****************** Bit definition for DAC_SHHR register ******************/
|
|
|
3701 #define DAC_SHHR_THOLD1 ((uint32_t)0x000003FFU) /*!<DAC channel1 hold time */
|
|
|
3702 #define DAC_SHHR_THOLD2 ((uint32_t)0x03FF0000U) /*!<DAC channel2 hold time */
|
|
|
3703
|
|
|
3704 /****************** Bit definition for DAC_SHRR register ******************/
|
|
|
3705 #define DAC_SHRR_TREFRESH1 ((uint32_t)0x000000FFU) /*!<DAC channel1 refresh time */
|
|
|
3706 #define DAC_SHRR_TREFRESH2 ((uint32_t)0x00FF0000U) /*!<DAC channel2 refresh time */
|
|
|
3707
|
|
|
3708
|
|
|
3709 /******************************************************************************/
|
|
|
3710 /* */
|
|
|
3711 /* Digital Filter for Sigma Delta Modulators */
|
|
|
3712 /* */
|
|
|
3713 /******************************************************************************/
|
|
|
3714
|
|
|
3715 /**************** DFSDM channel configuration registers ********************/
|
|
|
3716
|
|
|
3717 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
|
|
|
3718 #define DFSDM_CHCFGR1_DFSDMEN ((uint32_t)0x80000000U) /*!< Global enable for DFSDM interface */
|
|
|
3719 #define DFSDM_CHCFGR1_CKOUTSRC ((uint32_t)0x40000000U) /*!< Output serial clock source selection */
|
|
|
3720 #define DFSDM_CHCFGR1_CKOUTDIV ((uint32_t)0x00FF0000U) /*!< CKOUTDIV[7:0] output serial clock divider */
|
|
|
3721 #define DFSDM_CHCFGR1_DATPACK ((uint32_t)0x0000C000U) /*!< DATPACK[1:0] Data packing mode */
|
|
|
3722 #define DFSDM_CHCFGR1_DATPACK_1 ((uint32_t)0x00008000U) /*!< Data packing mode, Bit 1 */
|
|
|
3723 #define DFSDM_CHCFGR1_DATPACK_0 ((uint32_t)0x00004000U) /*!< Data packing mode, Bit 0 */
|
|
|
3724 #define DFSDM_CHCFGR1_DATMPX ((uint32_t)0x00003000U) /*!< DATMPX[1:0] Input data multiplexer for channel y */
|
|
|
3725 #define DFSDM_CHCFGR1_DATMPX_1 ((uint32_t)0x00002000U) /*!< Input data multiplexer for channel y, Bit 1 */
|
|
|
3726 #define DFSDM_CHCFGR1_DATMPX_0 ((uint32_t)0x00001000U) /*!< Input data multiplexer for channel y, Bit 0 */
|
|
|
3727 #define DFSDM_CHCFGR1_CHINSEL ((uint32_t)0x00000100U) /*!< Serial inputs selection for channel y */
|
|
|
3728 #define DFSDM_CHCFGR1_CHEN ((uint32_t)0x00000080U) /*!< Channel y enable */
|
|
|
3729 #define DFSDM_CHCFGR1_CKABEN ((uint32_t)0x00000040U) /*!< Clock absence detector enable on channel y */
|
|
|
3730 #define DFSDM_CHCFGR1_SCDEN ((uint32_t)0x00000020U) /*!< Short circuit detector enable on channel y */
|
|
|
3731 #define DFSDM_CHCFGR1_SPICKSEL ((uint32_t)0x0000000CU) /*!< SPICKSEL[1:0] SPI clock select for channel y */
|
|
|
3732 #define DFSDM_CHCFGR1_SPICKSEL_1 ((uint32_t)0x00000008U) /*!< SPI clock select for channel y, Bit 1 */
|
|
|
3733 #define DFSDM_CHCFGR1_SPICKSEL_0 ((uint32_t)0x00000004U) /*!< SPI clock select for channel y, Bit 0 */
|
|
|
3734 #define DFSDM_CHCFGR1_SITP ((uint32_t)0x00000003U) /*!< SITP[1:0] Serial interface type for channel y */
|
|
|
3735 #define DFSDM_CHCFGR1_SITP_1 ((uint32_t)0x00000002U) /*!< Serial interface type for channel y, Bit 1 */
|
|
|
3736 #define DFSDM_CHCFGR1_SITP_0 ((uint32_t)0x00000001U) /*!< Serial interface type for channel y, Bit 0 */
|
|
|
3737
|
|
|
3738 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
|
|
|
3739 #define DFSDM_CHCFGR2_OFFSET ((uint32_t)0xFFFFFF00U) /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
|
|
|
3740 #define DFSDM_CHCFGR2_DTRBS ((uint32_t)0x000000F8U) /*!< DTRBS[4:0] Data right bit-shift for channel y */
|
|
|
3741
|
|
|
3742 /****************** Bit definition for DFSDM_AWSCDR register *****************/
|
|
|
3743 #define DFSDM_AWSCDR_AWFORD ((uint32_t)0x00C00000U) /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
|
|
|
3744 #define DFSDM_AWSCDR_AWFORD_1 ((uint32_t)0x00800000U) /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
|
|
|
3745 #define DFSDM_AWSCDR_AWFORD_0 ((uint32_t)0x00400000U) /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
|
|
|
3746 #define DFSDM_AWSCDR_AWFOSR ((uint32_t)0x001F0000U) /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
|
|
|
3747 #define DFSDM_AWSCDR_BKSCD ((uint32_t)0x0000F000U) /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
|
|
|
3748 #define DFSDM_AWSCDR_SCDT ((uint32_t)0x000000FFU) /*!< SCDT[7:0] Short circuit detector threshold for channel y */
|
|
|
3749
|
|
|
3750 /**************** Bit definition for DFSDM_CHWDATR register *******************/
|
|
|
3751 #define DFSDM_AWSCDR_WDATA ((uint32_t)0x0000FFFFU) /*!< WDATA[15:0] Input channel y watchdog data */
|
|
|
3752
|
|
|
3753 /**************** Bit definition for DFSDM_CHDATINR register *****************/
|
|
|
3754 #define DFSDM_AWSCDR_INDAT0 ((uint32_t)0x0000FFFFU) /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
|
|
|
3755 #define DFSDM_AWSCDR_INDAT1 ((uint32_t)0xFFFF0000U) /*!< INDAT0[15:0] Input data for channel y */
|
|
|
3756
|
|
|
3757 /************************ DFSDM module registers ****************************/
|
|
|
3758
|
|
|
3759 /******************** Bit definition for DFSDM_CR1 register *******************/
|
|
|
3760 #define DFSDM_CR1_AWFSEL ((uint32_t)0x40000000U) /*!< Analog watchdog fast mode select */
|
|
|
3761 #define DFSDM_CR1_FAST ((uint32_t)0x20000000U) /*!< Fast conversion mode selection */
|
|
|
3762 #define DFSDM_CR1_RCH ((uint32_t)0x07000000U) /*!< RCH[2:0] Regular channel selection */
|
|
|
3763 #define DFSDM_CR1_RDMAEN ((uint32_t)0x00200000U) /*!< DMA channel enabled to read data for the regular conversion */
|
|
|
3764 #define DFSDM_CR1_RSYNC ((uint32_t)0x00080000U) /*!< Launch regular conversion synchronously with DFSDMx */
|
|
|
3765 #define DFSDM_CR1_RCONT ((uint32_t)0x00040000U) /*!< Continuous mode selection for regular conversions */
|
|
|
3766 #define DFSDM_CR1_RSWSTART ((uint32_t)0x00020000U) /*!< Software start of a conversion on the regular channel */
|
|
|
3767 #define DFSDM_CR1_JEXTEN ((uint32_t)0x00006000U) /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
|
|
|
3768 #define DFSDM_CR1_JEXTEN_1 ((uint32_t)0x00004000U) /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
|
|
|
3769 #define DFSDM_CR1_JEXTEN_0 ((uint32_t)0x00002000U) /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
|
|
|
3770 #define DFSDM_CR1_JEXTSEL ((uint32_t)0x00000700U) /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
|
|
|
3771 #define DFSDM_CR1_JEXTSEL_2 ((uint32_t)0x00000400U) /*!< Trigger signal selection for launching injected conversions, Bit 2 */
|
|
|
3772 #define DFSDM_CR1_JEXTSEL_1 ((uint32_t)0x00000200U) /*!< Trigger signal selection for launching injected conversions, Bit 1 */
|
|
|
3773 #define DFSDM_CR1_JEXTSEL_0 ((uint32_t)0x00000100U) /*!< Trigger signal selection for launching injected conversions, Bit 0 */
|
|
|
3774 #define DFSDM_CR1_JDMAEN ((uint32_t)0x00000020U) /*!< DMA channel enabled to read data for the injected channel group */
|
|
|
3775 #define DFSDM_CR1_JSCAN ((uint32_t)0x00000010U) /*!< Scanning conversion in continuous mode selection for injected conversions */
|
|
|
3776 #define DFSDM_CR1_JSYNC ((uint32_t)0x00000008U) /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
|
|
|
3777 #define DFSDM_CR1_JSWSTART ((uint32_t)0x00000002U) /*!< Start the conversion of the injected group of channels */
|
|
|
3778 #define DFSDM_CR1_DFEN ((uint32_t)0x00000001U) /*!< DFSDM enable */
|
|
|
3779
|
|
|
3780 /******************** Bit definition for DFSDM_CR2 register *******************/
|
|
|
3781 #define DFSDM_CR2_AWDCH ((uint32_t)0x00FF0000U) /*!< AWDCH[7:0] Analog watchdog channel selection */
|
|
|
3782 #define DFSDM_CR2_EXCH ((uint32_t)0x0000FF00U) /*!< EXCH[7:0] Extreme detector channel selection */
|
|
|
3783 #define DFSDM_CR2_CKABIE ((uint32_t)0x00000040U) /*!< Clock absence interrupt enable */
|
|
|
3784 #define DFSDM_CR2_SCDIE ((uint32_t)0x00000020U) /*!< Short circuit detector interrupt enable */
|
|
|
3785 #define DFSDM_CR2_AWDIE ((uint32_t)0x00000010U) /*!< Analog watchdog interrupt enable */
|
|
|
3786 #define DFSDM_CR2_ROVRIE ((uint32_t)0x00000008U) /*!< Regular data overrun interrupt enable */
|
|
|
3787 #define DFSDM_CR2_JOVRIE ((uint32_t)0x00000004U) /*!< Injected data overrun interrupt enable */
|
|
|
3788 #define DFSDM_CR2_REOCIE ((uint32_t)0x00000002U) /*!< Regular end of conversion interrupt enable */
|
|
|
3789 #define DFSDM_CR2_JEOCIE ((uint32_t)0x00000001U) /*!< Injected end of conversion interrupt enable */
|
|
|
3790
|
|
|
3791 /******************** Bit definition for DFSDM_ISR register *******************/
|
|
|
3792 #define DFSDM_ISR_SCDF ((uint32_t)0xFF000000U) /*!< SCDF[7:0] Short circuit detector flag */
|
|
|
3793 #define DFSDM_ISR_CKABF ((uint32_t)0x00FF0000U) /*!< CKABF[7:0] Clock absence flag */
|
|
|
3794 #define DFSDM_ISR_RCIP ((uint32_t)0x00004000U) /*!< Regular conversion in progress status */
|
|
|
3795 #define DFSDM_ISR_JCIP ((uint32_t)0x00002000U) /*!< Injected conversion in progress status */
|
|
|
3796 #define DFSDM_ISR_AWDF ((uint32_t)0x00000010U) /*!< Analog watchdog */
|
|
|
3797 #define DFSDM_ISR_ROVRF ((uint32_t)0x00000008U) /*!< Regular conversion overrun flag */
|
|
|
3798 #define DFSDM_ISR_JOVRF ((uint32_t)0x00000004U) /*!< Injected conversion overrun flag */
|
|
|
3799 #define DFSDM_ISR_REOCF ((uint32_t)0x00000002U) /*!< End of regular conversion flag */
|
|
|
3800 #define DFSDM_ISR_JEOCF ((uint32_t)0x00000001U) /*!< End of injected conversion flag */
|
|
|
3801
|
|
|
3802 /******************** Bit definition for DFSDM_ICR register *******************/
|
|
|
3803 #define DFSDM_ICR_CLRSCSDF ((uint32_t)0xFF000000U) /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
|
|
|
3804 #define DFSDM_ICR_CLRCKABF ((uint32_t)0x00FF0000U) /*!< CLRCKABF[7:0] Clear the clock absence flag */
|
|
|
3805 #define DFSDM_ICR_CLRROVRF ((uint32_t)0x00000008U) /*!< Clear the regular conversion overrun flag */
|
|
|
3806 #define DFSDM_ICR_CLRJOVRF ((uint32_t)0x00000004U) /*!< Clear the injected conversion overrun flag */
|
|
|
3807
|
|
|
3808 /******************* Bit definition for DFSDM_JCHGR register ******************/
|
|
|
3809 #define DFSDM_JCHGR_JCHG ((uint32_t)0x000000FFU) /*!< JCHG[7:0] Injected channel group selection */
|
|
|
3810
|
|
|
3811 /******************** Bit definition for DFSDM_FCR register *******************/
|
|
|
3812 #define DFSDM_FCR_FORD ((uint32_t)0xE0000000U) /*!< FORD[2:0] Sinc filter order */
|
|
|
3813 #define DFSDM_FCR_FORD_2 ((uint32_t)0x80000000U) /*!< Sinc filter order, Bit 2 */
|
|
|
3814 #define DFSDM_FCR_FORD_1 ((uint32_t)0x40000000U) /*!< Sinc filter order, Bit 1 */
|
|
|
3815 #define DFSDM_FCR_FORD_0 ((uint32_t)0x20000000U) /*!< Sinc filter order, Bit 0 */
|
|
|
3816 #define DFSDM_FCR_FOSR ((uint32_t)0x03FF0000U) /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
|
|
|
3817 #define DFSDM_FCR_IOSR ((uint32_t)0x000000FFU) /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
|
|
|
3818
|
|
|
3819 /****************** Bit definition for DFSDM_JDATAR register *****************/
|
|
|
3820 #define DFSDM_JDATAR_JDATA ((uint32_t)0xFFFFFF00U) /*!< JDATA[23:0] Injected group conversion data */
|
|
|
3821 #define DFSDM_JDATAR_JDATACH ((uint32_t)0x00000007U) /*!< JDATACH[2:0] Injected channel most recently converted */
|
|
|
3822
|
|
|
3823 /****************** Bit definition for DFSDM_RDATAR register *****************/
|
|
|
3824 #define DFSDM_RDATAR_RDATA ((uint32_t)0xFFFFFF00U) /*!< RDATA[23:0] Regular channel conversion data */
|
|
|
3825 #define DFSDM_RDATAR_RPEND ((uint32_t)0x00000010U) /*!< RPEND Regular channel pending data */
|
|
|
3826 #define DFSDM_RDATAR_RDATACH ((uint32_t)0x00000007U) /*!< RDATACH[2:0] Regular channel most recently converted */
|
|
|
3827
|
|
|
3828 /****************** Bit definition for DFSDM_AWHTR register ******************/
|
|
|
3829 #define DFSDM_AWHTR_AWHT ((uint32_t)0xFFFFFF00U) /*!< AWHT[23:0] Analog watchdog high threshold */
|
|
|
3830 #define DFSDM_AWHTR_BKAWH ((uint32_t)0x0000000FU) /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
|
|
|
3831
|
|
|
3832 /****************** Bit definition for DFSDM_AWLTR register ******************/
|
|
|
3833 #define DFSDM_AWLTR_AWLT ((uint32_t)0xFFFFFF00U) /*!< AWHT[23:0] Analog watchdog low threshold */
|
|
|
3834 #define DFSDM_AWLTR_BKAWL ((uint32_t)0x0000000FU) /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
|
|
|
3835
|
|
|
3836 /****************** Bit definition for DFSDM_AWSR register ******************/
|
|
|
3837 #define DFSDM_AWSR_AWHTF ((uint32_t)0x0000FF00U) /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
|
|
|
3838 #define DFSDM_AWSR_AWLTF ((uint32_t)0x000000FFU) /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
|
|
|
3839
|
|
|
3840 /****************** Bit definition for DFSDM_AWCFR) register *****************/
|
|
|
3841 #define DFSDM_AWCFR_CLRAWHTF ((uint32_t)0x0000FF00U) /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
|
|
|
3842 #define DFSDM_AWCFR_CLRAWLTF ((uint32_t)0x000000FFU) /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
|
|
|
3843
|
|
|
3844 /****************** Bit definition for DFSDM_EXMAX register ******************/
|
|
|
3845 #define DFSDM_EXMAX_EXMAX ((uint32_t)0xFFFFFF00U) /*!< EXMAX[23:0] Extreme detector maximum value */
|
|
|
3846 #define DFSDM_EXMAX_EXMAXCH ((uint32_t)0x00000007U) /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
|
|
|
3847
|
|
|
3848 /****************** Bit definition for DFSDM_EXMIN register ******************/
|
|
|
3849 #define DFSDM_EXMIN_EXMIN ((uint32_t)0xFFFFFF00U) /*!< EXMIN[23:0] Extreme detector minimum value */
|
|
|
3850 #define DFSDM_EXMIN_EXMINCH ((uint32_t)0x00000007U) /*!< EXMINCH[2:0] Extreme detector minimum data channel */
|
|
|
3851
|
|
|
3852 /****************** Bit definition for DFSDM_EXMIN register ******************/
|
|
|
3853 #define DFSDM_CNVTIMR_CNVCNT ((uint32_t)0xFFFFFFF0U) /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
|
|
|
3854
|
|
|
3855 /******************************************************************************/
|
|
|
3856 /* */
|
|
|
3857 /* DMA Controller (DMA) */
|
|
|
3858 /* */
|
|
|
3859 /******************************************************************************/
|
|
|
3860
|
|
|
3861 /******************* Bit definition for DMA_ISR register ********************/
|
|
|
3862 #define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
|
|
|
3863 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
|
|
|
3864 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
|
|
|
3865 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
|
|
|
3866 #define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
|
|
|
3867 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
|
|
|
3868 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
|
|
|
3869 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
|
|
|
3870 #define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
|
|
|
3871 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
|
|
|
3872 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
|
|
|
3873 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
|
|
|
3874 #define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
|
|
|
3875 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
|
|
|
3876 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
|
|
|
3877 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
|
|
|
3878 #define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
|
|
|
3879 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
|
|
|
3880 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
|
|
|
3881 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
|
|
|
3882 #define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
|
|
|
3883 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
|
|
|
3884 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
|
|
|
3885 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
|
|
|
3886 #define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
|
|
|
3887 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
|
|
|
3888 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
|
|
|
3889 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
|
|
|
3890
|
|
|
3891 /******************* Bit definition for DMA_IFCR register *******************/
|
|
|
3892 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clearr */
|
|
|
3893 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
|
|
|
3894 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
|
|
|
3895 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
|
|
|
3896 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
|
|
|
3897 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
|
|
|
3898 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
|
|
|
3899 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
|
|
|
3900 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
|
|
|
3901 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
|
|
|
3902 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
|
|
|
3903 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
|
|
|
3904 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
|
|
|
3905 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
|
|
|
3906 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
|
|
|
3907 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
|
|
|
3908 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
|
|
|
3909 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
|
|
|
3910 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
|
|
|
3911 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
|
|
|
3912 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
|
|
|
3913 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
|
|
|
3914 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
|
|
|
3915 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
|
|
|
3916 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
|
|
|
3917 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
|
|
|
3918 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
|
|
|
3919 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
|
|
|
3920
|
|
|
3921 /******************* Bit definition for DMA_CCR register ********************/
|
|
|
3922 #define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */
|
|
|
3923 #define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
|
|
|
3924 #define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
|
|
|
3925 #define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
|
|
|
3926 #define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
|
|
|
3927 #define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
|
|
|
3928 #define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
|
|
|
3929 #define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
|
|
|
3930
|
|
|
3931 #define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
|
|
|
3932 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
3933 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
3934
|
|
|
3935 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
|
|
|
3936 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
|
|
|
3937 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
|
|
|
3938
|
|
|
3939 #define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/
|
|
|
3940 #define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
|
|
|
3941 #define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
|
|
|
3942
|
|
|
3943 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
|
|
|
3944
|
|
|
3945 /****************** Bit definition for DMA_CNDTR register *******************/
|
|
|
3946 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
|
|
|
3947
|
|
|
3948 /****************** Bit definition for DMA_CPAR register ********************/
|
|
|
3949 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
|
|
|
3950
|
|
|
3951 /****************** Bit definition for DMA_CMAR register ********************/
|
|
|
3952 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
|
|
|
3953
|
|
|
3954
|
|
|
3955 /******************* Bit definition for DMA_CSELR register *******************/
|
|
|
3956 #define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */
|
|
|
3957 #define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */
|
|
|
3958 #define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */
|
|
|
3959 #define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */
|
|
|
3960 #define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */
|
|
|
3961 #define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */
|
|
|
3962 #define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */
|
|
|
3963
|
|
|
3964
|
|
|
3965 /******************************************************************************/
|
|
|
3966 /* */
|
|
|
3967 /* External Interrupt/Event Controller */
|
|
|
3968 /* */
|
|
|
3969 /******************************************************************************/
|
|
|
3970 /******************* Bit definition for EXTI_IMR1 register ******************/
|
|
|
3971 #define EXTI_IMR1_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
|
|
|
3972 #define EXTI_IMR1_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
|
|
|
3973 #define EXTI_IMR1_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
|
|
|
3974 #define EXTI_IMR1_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
|
|
|
3975 #define EXTI_IMR1_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
|
|
|
3976 #define EXTI_IMR1_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
|
|
|
3977 #define EXTI_IMR1_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
|
|
|
3978 #define EXTI_IMR1_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
|
|
|
3979 #define EXTI_IMR1_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
|
|
|
3980 #define EXTI_IMR1_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
|
|
|
3981 #define EXTI_IMR1_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
|
|
|
3982 #define EXTI_IMR1_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
|
|
|
3983 #define EXTI_IMR1_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
|
|
|
3984 #define EXTI_IMR1_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
|
|
|
3985 #define EXTI_IMR1_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
|
|
|
3986 #define EXTI_IMR1_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
|
|
|
3987 #define EXTI_IMR1_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
|
|
|
3988 #define EXTI_IMR1_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
|
|
|
3989 #define EXTI_IMR1_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
|
|
|
3990 #define EXTI_IMR1_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
|
|
|
3991 #define EXTI_IMR1_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
|
|
|
3992 #define EXTI_IMR1_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
|
|
|
3993 #define EXTI_IMR1_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
|
|
|
3994 #define EXTI_IMR1_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
|
|
|
3995 #define EXTI_IMR1_IM24 ((uint32_t)0x01000000U) /*!< Interrupt Mask on line 24 */
|
|
|
3996 #define EXTI_IMR1_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */
|
|
|
3997 #define EXTI_IMR1_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */
|
|
|
3998 #define EXTI_IMR1_IM27 ((uint32_t)0x08000000U) /*!< Interrupt Mask on line 27 */
|
|
|
3999 #define EXTI_IMR1_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */
|
|
|
4000 #define EXTI_IMR1_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */
|
|
|
4001 #define EXTI_IMR1_IM30 ((uint32_t)0x40000000U) /*!< Interrupt Mask on line 30 */
|
|
|
4002 #define EXTI_IMR1_IM31 ((uint32_t)0x80000000U) /*!< Interrupt Mask on line 31 */
|
|
|
4003
|
|
|
4004 /******************* Bit definition for EXTI_EMR1 register ******************/
|
|
|
4005 #define EXTI_EMR1_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
|
|
|
4006 #define EXTI_EMR1_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
|
|
|
4007 #define EXTI_EMR1_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
|
|
|
4008 #define EXTI_EMR1_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
|
|
|
4009 #define EXTI_EMR1_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
|
|
|
4010 #define EXTI_EMR1_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
|
|
|
4011 #define EXTI_EMR1_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
|
|
|
4012 #define EXTI_EMR1_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
|
|
|
4013 #define EXTI_EMR1_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
|
|
|
4014 #define EXTI_EMR1_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
|
|
|
4015 #define EXTI_EMR1_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
|
|
|
4016 #define EXTI_EMR1_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
|
|
|
4017 #define EXTI_EMR1_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
|
|
|
4018 #define EXTI_EMR1_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
|
|
|
4019 #define EXTI_EMR1_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
|
|
|
4020 #define EXTI_EMR1_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
|
|
|
4021 #define EXTI_EMR1_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
|
|
|
4022 #define EXTI_EMR1_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
|
|
|
4023 #define EXTI_EMR1_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
|
|
|
4024 #define EXTI_EMR1_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
|
|
|
4025 #define EXTI_EMR1_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
|
|
|
4026 #define EXTI_EMR1_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
|
|
|
4027 #define EXTI_EMR1_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
|
|
|
4028 #define EXTI_EMR1_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
|
|
|
4029 #define EXTI_EMR1_EM24 ((uint32_t)0x01000000U) /*!< Event Mask on line 24 */
|
|
|
4030 #define EXTI_EMR1_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */
|
|
|
4031 #define EXTI_EMR1_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */
|
|
|
4032 #define EXTI_EMR1_EM27 ((uint32_t)0x08000000U) /*!< Event Mask on line 27 */
|
|
|
4033 #define EXTI_EMR1_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */
|
|
|
4034 #define EXTI_EMR1_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */
|
|
|
4035 #define EXTI_EMR1_EM30 ((uint32_t)0x40000000U) /*!< Event Mask on line 30 */
|
|
|
4036 #define EXTI_EMR1_EM31 ((uint32_t)0x80000000U) /*!< Event Mask on line 31 */
|
|
|
4037
|
|
|
4038 /****************** Bit definition for EXTI_RTSR1 register ******************/
|
|
|
4039 #define EXTI_RTSR1_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
|
|
|
4040 #define EXTI_RTSR1_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
|
|
|
4041 #define EXTI_RTSR1_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
|
|
|
4042 #define EXTI_RTSR1_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
|
|
|
4043 #define EXTI_RTSR1_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
|
|
|
4044 #define EXTI_RTSR1_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
|
|
|
4045 #define EXTI_RTSR1_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
|
|
|
4046 #define EXTI_RTSR1_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
|
|
|
4047 #define EXTI_RTSR1_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
|
|
|
4048 #define EXTI_RTSR1_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
|
|
|
4049 #define EXTI_RTSR1_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
|
|
|
4050 #define EXTI_RTSR1_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
|
|
|
4051 #define EXTI_RTSR1_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
|
|
|
4052 #define EXTI_RTSR1_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
|
|
|
4053 #define EXTI_RTSR1_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
|
|
|
4054 #define EXTI_RTSR1_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
|
|
|
4055 #define EXTI_RTSR1_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
|
|
|
4056 #define EXTI_RTSR1_RT18 ((uint32_t)0x00040000U) /*!< Rising trigger event configuration bit of line 18 */
|
|
|
4057 #define EXTI_RTSR1_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
|
|
|
4058 #define EXTI_RTSR1_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
|
|
|
4059 #define EXTI_RTSR1_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
|
|
|
4060 #define EXTI_RTSR1_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
|
|
|
4061
|
|
|
4062 /****************** Bit definition for EXTI_FTSR1 register ******************/
|
|
|
4063 #define EXTI_FTSR1_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
|
|
|
4064 #define EXTI_FTSR1_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
|
|
|
4065 #define EXTI_FTSR1_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
|
|
|
4066 #define EXTI_FTSR1_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
|
|
|
4067 #define EXTI_FTSR1_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
|
|
|
4068 #define EXTI_FTSR1_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
|
|
|
4069 #define EXTI_FTSR1_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
|
|
|
4070 #define EXTI_FTSR1_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
|
|
|
4071 #define EXTI_FTSR1_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
|
|
|
4072 #define EXTI_FTSR1_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
|
|
|
4073 #define EXTI_FTSR1_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
|
|
|
4074 #define EXTI_FTSR1_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
|
|
|
4075 #define EXTI_FTSR1_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
|
|
|
4076 #define EXTI_FTSR1_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
|
|
|
4077 #define EXTI_FTSR1_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
|
|
|
4078 #define EXTI_FTSR1_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
|
|
|
4079 #define EXTI_FTSR1_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
|
|
|
4080 #define EXTI_FTSR1_FT18 ((uint32_t)0x00040000U) /*!< Falling trigger event configuration bit of line 18 */
|
|
|
4081 #define EXTI_FTSR1_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
|
|
|
4082 #define EXTI_FTSR1_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
|
|
|
4083 #define EXTI_FTSR1_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
|
|
|
4084 #define EXTI_FTSR1_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
|
|
|
4085
|
|
|
4086 /****************** Bit definition for EXTI_SWIER1 register *****************/
|
|
|
4087 #define EXTI_SWIER1_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
|
|
|
4088 #define EXTI_SWIER1_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
|
|
|
4089 #define EXTI_SWIER1_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
|
|
|
4090 #define EXTI_SWIER1_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
|
|
|
4091 #define EXTI_SWIER1_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
|
|
|
4092 #define EXTI_SWIER1_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
|
|
|
4093 #define EXTI_SWIER1_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
|
|
|
4094 #define EXTI_SWIER1_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
|
|
|
4095 #define EXTI_SWIER1_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
|
|
|
4096 #define EXTI_SWIER1_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
|
|
|
4097 #define EXTI_SWIER1_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
|
|
|
4098 #define EXTI_SWIER1_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
|
|
|
4099 #define EXTI_SWIER1_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
|
|
|
4100 #define EXTI_SWIER1_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
|
|
|
4101 #define EXTI_SWIER1_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
|
|
|
4102 #define EXTI_SWIER1_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
|
|
|
4103 #define EXTI_SWIER1_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
|
|
|
4104 #define EXTI_SWIER1_SWI18 ((uint32_t)0x00040000U) /*!< Software Interrupt on line 18 */
|
|
|
4105 #define EXTI_SWIER1_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
|
|
|
4106 #define EXTI_SWIER1_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
|
|
|
4107 #define EXTI_SWIER1_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
|
|
|
4108 #define EXTI_SWIER1_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
|
|
|
4109
|
|
|
4110 /******************* Bit definition for EXTI_PR1 register *******************/
|
|
|
4111 #define EXTI_PR1_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit for line 0 */
|
|
|
4112 #define EXTI_PR1_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit for line 1 */
|
|
|
4113 #define EXTI_PR1_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit for line 2 */
|
|
|
4114 #define EXTI_PR1_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit for line 3 */
|
|
|
4115 #define EXTI_PR1_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit for line 4 */
|
|
|
4116 #define EXTI_PR1_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit for line 5 */
|
|
|
4117 #define EXTI_PR1_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit for line 6 */
|
|
|
4118 #define EXTI_PR1_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit for line 7 */
|
|
|
4119 #define EXTI_PR1_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit for line 8 */
|
|
|
4120 #define EXTI_PR1_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit for line 9 */
|
|
|
4121 #define EXTI_PR1_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit for line 10 */
|
|
|
4122 #define EXTI_PR1_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit for line 11 */
|
|
|
4123 #define EXTI_PR1_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit for line 12 */
|
|
|
4124 #define EXTI_PR1_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit for line 13 */
|
|
|
4125 #define EXTI_PR1_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit for line 14 */
|
|
|
4126 #define EXTI_PR1_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit for line 15 */
|
|
|
4127 #define EXTI_PR1_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit for line 16 */
|
|
|
4128 #define EXTI_PR1_PIF18 ((uint32_t)0x00040000U) /*!< Pending bit for line 18 */
|
|
|
4129 #define EXTI_PR1_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit for line 19 */
|
|
|
4130 #define EXTI_PR1_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit for line 20 */
|
|
|
4131 #define EXTI_PR1_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit for line 21 */
|
|
|
4132 #define EXTI_PR1_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit for line 22 */
|
|
|
4133
|
|
|
4134 /******************* Bit definition for EXTI_IMR2 register ******************/
|
|
|
4135 #define EXTI_IMR2_IM32 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 32 */
|
|
|
4136 #define EXTI_IMR2_IM33 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 33 */
|
|
|
4137 #define EXTI_IMR2_IM34 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 34 */
|
|
|
4138 #define EXTI_IMR2_IM35 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 35 */
|
|
|
4139 #define EXTI_IMR2_IM36 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 36 */
|
|
|
4140 #define EXTI_IMR2_IM37 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 37 */
|
|
|
4141 #define EXTI_IMR2_IM38 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 38 */
|
|
|
4142 #define EXTI_IMR2_IM39 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 39 */
|
|
|
4143
|
|
|
4144 /******************* Bit definition for EXTI_EMR2 register ******************/
|
|
|
4145 #define EXTI_EMR2_EM32 ((uint32_t)0x00000001U) /*!< Event Mask on line 32 */
|
|
|
4146 #define EXTI_EMR2_EM33 ((uint32_t)0x00000002U) /*!< Event Mask on line 33 */
|
|
|
4147 #define EXTI_EMR2_EM34 ((uint32_t)0x00000004U) /*!< Event Mask on line 34 */
|
|
|
4148 #define EXTI_EMR2_EM35 ((uint32_t)0x00000008U) /*!< Event Mask on line 35 */
|
|
|
4149 #define EXTI_EMR2_EM36 ((uint32_t)0x00000010U) /*!< Event Mask on line 36 */
|
|
|
4150 #define EXTI_EMR2_EM37 ((uint32_t)0x00000020U) /*!< Event Mask on line 37 */
|
|
|
4151 #define EXTI_EMR2_EM38 ((uint32_t)0x00000040U) /*!< Event Mask on line 38 */
|
|
|
4152 #define EXTI_EMR2_EM39 ((uint32_t)0x00000080U) /*!< Event Mask on line 39 */
|
|
|
4153
|
|
|
4154 /****************** Bit definition for EXTI_RTSR2 register ******************/
|
|
|
4155 #define EXTI_RTSR2_RT35 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 35 */
|
|
|
4156 #define EXTI_RTSR2_RT36 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 36 */
|
|
|
4157 #define EXTI_RTSR2_RT37 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 37 */
|
|
|
4158 #define EXTI_RTSR2_RT38 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 38 */
|
|
|
4159
|
|
|
4160 /****************** Bit definition for EXTI_FTSR2 register ******************/
|
|
|
4161 #define EXTI_FTSR2_FT35 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 35 */
|
|
|
4162 #define EXTI_FTSR2_FT36 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 36 */
|
|
|
4163 #define EXTI_FTSR2_FT37 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 37 */
|
|
|
4164 #define EXTI_FTSR2_FT38 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 38 */
|
|
|
4165
|
|
|
4166 /****************** Bit definition for EXTI_SWIER2 register *****************/
|
|
|
4167 #define EXTI_SWIER2_SWI35 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 35 */
|
|
|
4168 #define EXTI_SWIER2_SWI36 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 36 */
|
|
|
4169 #define EXTI_SWIER2_SWI37 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 37 */
|
|
|
4170 #define EXTI_SWIER2_SWI38 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 38 */
|
|
|
4171
|
|
|
4172 /******************* Bit definition for EXTI_PR2 register *******************/
|
|
|
4173 #define EXTI_PR2_PIF35 ((uint32_t)0x00000008U) /*!< Pending bit for line 35 */
|
|
|
4174 #define EXTI_PR2_PIF36 ((uint32_t)0x00000010U) /*!< Pending bit for line 36 */
|
|
|
4175 #define EXTI_PR2_PIF37 ((uint32_t)0x00000020U) /*!< Pending bit for line 37 */
|
|
|
4176 #define EXTI_PR2_PIF38 ((uint32_t)0x00000040U) /*!< Pending bit for line 38 */
|
|
|
4177
|
|
|
4178
|
|
|
4179 /******************************************************************************/
|
|
|
4180 /* */
|
|
|
4181 /* FLASH */
|
|
|
4182 /* */
|
|
|
4183 /******************************************************************************/
|
|
|
4184 /******************* Bits definition for FLASH_ACR register *****************/
|
|
|
4185 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007U)
|
|
|
4186 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000U)
|
|
|
4187 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001U)
|
|
|
4188 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002U)
|
|
|
4189 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003U)
|
|
|
4190 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004U)
|
|
|
4191 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100U)
|
|
|
4192 #define FLASH_ACR_ICEN ((uint32_t)0x00000200U)
|
|
|
4193 #define FLASH_ACR_DCEN ((uint32_t)0x00000400U)
|
|
|
4194 #define FLASH_ACR_ICRST ((uint32_t)0x00000800U)
|
|
|
4195 #define FLASH_ACR_DCRST ((uint32_t)0x00001000U)
|
|
|
4196 #define FLASH_ACR_RUN_PD ((uint32_t)0x00002000U) /*!< Flash power down mode during run */
|
|
|
4197 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00004000U) /*!< Flash power down mode during sleep */
|
|
|
4198
|
|
|
4199 /******************* Bits definition for FLASH_SR register ******************/
|
|
|
4200 #define FLASH_SR_EOP ((uint32_t)0x00000001U)
|
|
|
4201 #define FLASH_SR_OPERR ((uint32_t)0x00000002U)
|
|
|
4202 #define FLASH_SR_PROGERR ((uint32_t)0x00000008U)
|
|
|
4203 #define FLASH_SR_WRPERR ((uint32_t)0x00000010U)
|
|
|
4204 #define FLASH_SR_PGAERR ((uint32_t)0x00000020U)
|
|
|
4205 #define FLASH_SR_SIZERR ((uint32_t)0x00000040U)
|
|
|
4206 #define FLASH_SR_PGSERR ((uint32_t)0x00000080U)
|
|
|
4207 #define FLASH_SR_MISERR ((uint32_t)0x00000100U)
|
|
|
4208 #define FLASH_SR_FASTERR ((uint32_t)0x00000200U)
|
|
|
4209 #define FLASH_SR_RDERR ((uint32_t)0x00004000U)
|
|
|
4210 #define FLASH_SR_OPTVERR ((uint32_t)0x00008000U)
|
|
|
4211 #define FLASH_SR_BSY ((uint32_t)0x00010000U)
|
|
|
4212
|
|
|
4213 /******************* Bits definition for FLASH_CR register ******************/
|
|
|
4214 #define FLASH_CR_PG ((uint32_t)0x00000001U)
|
|
|
4215 #define FLASH_CR_PER ((uint32_t)0x00000002U)
|
|
|
4216 #define FLASH_CR_MER1 ((uint32_t)0x00000004U)
|
|
|
4217 #define FLASH_CR_PNB ((uint32_t)0x000007F8U)
|
|
|
4218 #define FLASH_CR_BKER ((uint32_t)0x00000800U)
|
|
|
4219 #define FLASH_CR_MER2 ((uint32_t)0x00008000U)
|
|
|
4220 #define FLASH_CR_STRT ((uint32_t)0x00010000U)
|
|
|
4221 #define FLASH_CR_OPTSTRT ((uint32_t)0x00020000U)
|
|
|
4222 #define FLASH_CR_FSTPG ((uint32_t)0x00040000U)
|
|
|
4223 #define FLASH_CR_EOPIE ((uint32_t)0x01000000U)
|
|
|
4224 #define FLASH_CR_ERRIE ((uint32_t)0x02000000U)
|
|
|
4225 #define FLASH_CR_RDERRIE ((uint32_t)0x04000000U)
|
|
|
4226 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x08000000U)
|
|
|
4227 #define FLASH_CR_OPTLOCK ((uint32_t)0x40000000U)
|
|
|
4228 #define FLASH_CR_LOCK ((uint32_t)0x80000000U)
|
|
|
4229
|
|
|
4230 /******************* Bits definition for FLASH_ECCR register ***************/
|
|
|
4231 #define FLASH_ECCR_ADDR_ECC ((uint32_t)0x0007FFFFU)
|
|
|
4232 #define FLASH_ECCR_BK_ECC ((uint32_t)0x00080000U)
|
|
|
4233 #define FLASH_ECCR_SYSF_ECC ((uint32_t)0x00100000U)
|
|
|
4234 #define FLASH_ECCR_ECCIE ((uint32_t)0x01000000U)
|
|
|
4235 #define FLASH_ECCR_ECCC ((uint32_t)0x40000000U)
|
|
|
4236 #define FLASH_ECCR_ECCD ((uint32_t)0x80000000U)
|
|
|
4237
|
|
|
4238 /******************* Bits definition for FLASH_OPTR register ***************/
|
|
|
4239 #define FLASH_OPTR_RDP ((uint32_t)0x000000FFU)
|
|
|
4240 #define FLASH_OPTR_BOR_LEV ((uint32_t)0x00000700U)
|
|
|
4241 #define FLASH_OPTR_BOR_LEV_0 ((uint32_t)0x00000000U)
|
|
|
4242 #define FLASH_OPTR_BOR_LEV_1 ((uint32_t)0x00000100U)
|
|
|
4243 #define FLASH_OPTR_BOR_LEV_2 ((uint32_t)0x00000200U)
|
|
|
4244 #define FLASH_OPTR_BOR_LEV_3 ((uint32_t)0x00000300U)
|
|
|
4245 #define FLASH_OPTR_BOR_LEV_4 ((uint32_t)0x00000400U)
|
|
|
4246 #define FLASH_OPTR_nRST_STOP ((uint32_t)0x00001000U)
|
|
|
4247 #define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00002000U)
|
|
|
4248 #define FLASH_OPTR_nRST_SHDW ((uint32_t)0x00004000U)
|
|
|
4249 #define FLASH_OPTR_IWDG_SW ((uint32_t)0x00010000U)
|
|
|
4250 #define FLASH_OPTR_IWDG_STOP ((uint32_t)0x00020000U)
|
|
|
4251 #define FLASH_OPTR_IWDG_STDBY ((uint32_t)0x00040000U)
|
|
|
4252 #define FLASH_OPTR_WWDG_SW ((uint32_t)0x00080000U)
|
|
|
4253 #define FLASH_OPTR_BFB2 ((uint32_t)0x00100000U)
|
|
|
4254 #define FLASH_OPTR_DUALBANK ((uint32_t)0x00200000U)
|
|
|
4255 #define FLASH_OPTR_nBOOT1 ((uint32_t)0x00800000U)
|
|
|
4256 #define FLASH_OPTR_SRAM2_PE ((uint32_t)0x01000000U)
|
|
|
4257 #define FLASH_OPTR_SRAM2_RST ((uint32_t)0x02000000U)
|
|
|
4258
|
|
|
4259 /****************** Bits definition for FLASH_PCROP1SR register **********/
|
|
|
4260 #define FLASH_PCROP1SR_PCROP1_STRT ((uint32_t)0x0000FFFFU)
|
|
|
4261
|
|
|
4262 /****************** Bits definition for FLASH_PCROP1ER register ***********/
|
|
|
4263 #define FLASH_PCROP1ER_PCROP1_END ((uint32_t)0x0000FFFFU)
|
|
|
4264 #define FLASH_PCROP1ER_PCROP_RDP ((uint32_t)0x80000000U)
|
|
|
4265
|
|
|
4266 /****************** Bits definition for FLASH_WRP1AR register ***************/
|
|
|
4267 #define FLASH_WRP1AR_WRP1A_STRT ((uint32_t)0x000000FFU)
|
|
|
4268 #define FLASH_WRP1AR_WRP1A_END ((uint32_t)0x00FF0000U)
|
|
|
4269
|
|
|
4270 /****************** Bits definition for FLASH_WRPB1R register ***************/
|
|
|
4271 #define FLASH_WRP1BR_WRP1B_STRT ((uint32_t)0x000000FFU)
|
|
|
4272 #define FLASH_WRP1BR_WRP1B_END ((uint32_t)0x00FF0000U)
|
|
|
4273
|
|
|
4274 /****************** Bits definition for FLASH_PCROP2SR register **********/
|
|
|
4275 #define FLASH_PCROP2SR_PCROP2_STRT ((uint32_t)0x0000FFFFU)
|
|
|
4276
|
|
|
4277 /****************** Bits definition for FLASH_PCROP2ER register ***********/
|
|
|
4278 #define FLASH_PCROP2ER_PCROP2_END ((uint32_t)0x0000FFFFU)
|
|
|
4279
|
|
|
4280 /****************** Bits definition for FLASH_WRP2AR register ***************/
|
|
|
4281 #define FLASH_WRP2AR_WRP2A_STRT ((uint32_t)0x000000FFU)
|
|
|
4282 #define FLASH_WRP2AR_WRP2A_END ((uint32_t)0x00FF0000U)
|
|
|
4283
|
|
|
4284 /****************** Bits definition for FLASH_WRP2BR register ***************/
|
|
|
4285 #define FLASH_WRP2BR_WRP2B_STRT ((uint32_t)0x000000FFU)
|
|
|
4286 #define FLASH_WRP2BR_WRP2B_END ((uint32_t)0x00FF0000U)
|
|
|
4287
|
|
|
4288
|
|
|
4289 /******************************************************************************/
|
|
|
4290 /* */
|
|
|
4291 /* Flexible Memory Controller */
|
|
|
4292 /* */
|
|
|
4293 /******************************************************************************/
|
|
|
4294 /****************** Bit definition for FMC_BCR1 register *******************/
|
|
|
4295 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000U) /*!<Continous clock enable */
|
|
|
4296
|
|
|
4297 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
|
|
|
4298 #define FMC_BCRx_MBKEN ((uint32_t)0x00000001U) /*!<Memory bank enable bit */
|
|
|
4299 #define FMC_BCRx_MUXEN ((uint32_t)0x00000002U) /*!<Address/data multiplexing enable bit */
|
|
|
4300
|
|
|
4301 #define FMC_BCRx_MTYP ((uint32_t)0x0000000CU) /*!<MTYP[1:0] bits (Memory type) */
|
|
|
4302 #define FMC_BCRx_MTYP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
4303 #define FMC_BCRx_MTYP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
4304
|
|
|
4305 #define FMC_BCRx_MWID ((uint32_t)0x00000030U) /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
4306 #define FMC_BCRx_MWID_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
4307 #define FMC_BCRx_MWID_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
4308
|
|
|
4309 #define FMC_BCRx_FACCEN ((uint32_t)0x00000040U) /*!<Flash access enable */
|
|
|
4310 #define FMC_BCRx_BURSTEN ((uint32_t)0x00000100U) /*!<Burst enable bit */
|
|
|
4311 #define FMC_BCRx_WAITPOL ((uint32_t)0x00000200U) /*!<Wait signal polarity bit */
|
|
|
4312 #define FMC_BCRx_WAITCFG ((uint32_t)0x00000800U) /*!<Wait timing configuration */
|
|
|
4313 #define FMC_BCRx_WREN ((uint32_t)0x00001000U) /*!<Write enable bit */
|
|
|
4314 #define FMC_BCRx_WAITEN ((uint32_t)0x00002000U) /*!<Wait enable bit */
|
|
|
4315 #define FMC_BCRx_EXTMOD ((uint32_t)0x00004000U) /*!<Extended mode enable */
|
|
|
4316 #define FMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000U) /*!<Asynchronous wait */
|
|
|
4317
|
|
|
4318 #define FMC_BCRx_CPSIZE ((uint32_t)0x00070000U) /*!<CRAM page size */
|
|
|
4319 #define FMC_BCRx_CPSIZE_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
4320 #define FMC_BCRx_CPSIZE_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
4321 #define FMC_BCRx_CPSIZE_2 ((uint32_t)0x00040000U) /*!<Bit 1 */
|
|
|
4322
|
|
|
4323 #define FMC_BCRx_CBURSTRW ((uint32_t)0x00080000U) /*!<Write burst enable */
|
|
|
4324
|
|
|
4325 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
|
|
|
4326 #define FMC_BTRx_ADDSET ((uint32_t)0x0000000FU) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
4327 #define FMC_BTRx_ADDSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
4328 #define FMC_BTRx_ADDSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
4329 #define FMC_BTRx_ADDSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
4330 #define FMC_BTRx_ADDSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
4331
|
|
|
4332 #define FMC_BTRx_ADDHLD ((uint32_t)0x000000F0U) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
4333 #define FMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
4334 #define FMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
4335 #define FMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
4336 #define FMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
|
|
|
4337
|
|
|
4338 #define FMC_BTRx_DATAST ((uint32_t)0x0000FF00U) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
4339 #define FMC_BTRx_DATAST_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
4340 #define FMC_BTRx_DATAST_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
4341 #define FMC_BTRx_DATAST_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
4342 #define FMC_BTRx_DATAST_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
4343 #define FMC_BTRx_DATAST_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
4344 #define FMC_BTRx_DATAST_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
|
|
|
4345 #define FMC_BTRx_DATAST_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
|
|
|
4346 #define FMC_BTRx_DATAST_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
|
|
|
4347
|
|
|
4348 #define FMC_BTRx_BUSTURN ((uint32_t)0x000F0000U) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
|
|
4349 #define FMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
4350 #define FMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
4351 #define FMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
4352 #define FMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
|
|
|
4353
|
|
|
4354 #define FMC_BTRx_CLKDIV ((uint32_t)0x00F00000U) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
4355 #define FMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
|
|
|
4356 #define FMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
|
|
|
4357 #define FMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
|
|
|
4358 #define FMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000U) /*!<Bit 3 */
|
|
|
4359
|
|
|
4360 #define FMC_BTRx_DATLAT ((uint32_t)0x0F000000U) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
4361 #define FMC_BTRx_DATLAT_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
4362 #define FMC_BTRx_DATLAT_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
4363 #define FMC_BTRx_DATLAT_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
4364 #define FMC_BTRx_DATLAT_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
4365
|
|
|
4366 #define FMC_BTRx_ACCMOD ((uint32_t)0x30000000U) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4367 #define FMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
|
|
|
4368 #define FMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
|
|
|
4369
|
|
|
4370 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
|
|
|
4371 #define FMC_BWTRx_ADDSET ((uint32_t)0x0000000FU) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
4372 #define FMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
4373 #define FMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
4374 #define FMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
4375 #define FMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
4376
|
|
|
4377 #define FMC_BWTRx_ADDHLD ((uint32_t)0x000000F0U) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
4378 #define FMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
4379 #define FMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
4380 #define FMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
4381 #define FMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
|
|
|
4382
|
|
|
4383 #define FMC_BWTRx_DATAST ((uint32_t)0x0000FF00U) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
4384 #define FMC_BWTRx_DATAST_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
4385 #define FMC_BWTRx_DATAST_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
4386 #define FMC_BWTRx_DATAST_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
4387 #define FMC_BWTRx_DATAST_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
4388 #define FMC_BWTRx_DATAST_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
4389 #define FMC_BWTRx_DATAST_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
|
|
|
4390 #define FMC_BWTRx_DATAST_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
|
|
|
4391 #define FMC_BWTRx_DATAST_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
|
|
|
4392
|
|
|
4393 #define FMC_BWTRx_ACCMOD ((uint32_t)0x30000000U) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
4394 #define FMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
|
|
|
4395 #define FMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
|
|
|
4396
|
|
|
4397 /****************** Bit definition for FMC_PCR register ********************/
|
|
|
4398 #define FMC_PCR_PWAITEN ((uint32_t)0x00000002U) /*!<Wait feature enable bit */
|
|
|
4399 #define FMC_PCR_PBKEN ((uint32_t)0x00000004U) /*!<NAND Flash memory bank enable bit */
|
|
|
4400 #define FMC_PCR_PTYP ((uint32_t)0x00000008U) /*!<Memory type */
|
|
|
4401
|
|
|
4402 #define FMC_PCR_PWID ((uint32_t)0x00000030U) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
|
|
4403 #define FMC_PCR_PWID_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
4404 #define FMC_PCR_PWID_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
4405
|
|
|
4406 #define FMC_PCR_ECCEN ((uint32_t)0x00000040U) /*!<ECC computation logic enable bit */
|
|
|
4407
|
|
|
4408 #define FMC_PCR_TCLR ((uint32_t)0x00001E00U) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
|
|
4409 #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
|
|
|
4410 #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
|
|
|
4411 #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800U) /*!<Bit 2 */
|
|
|
4412 #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000U) /*!<Bit 3 */
|
|
|
4413
|
|
|
4414 #define FMC_PCR_TAR ((uint32_t)0x0001E000U) /*!<TAR[3:0] bits (ALE to RE delay) */
|
|
|
4415 #define FMC_PCR_TAR_0 ((uint32_t)0x00002000U) /*!<Bit 0 */
|
|
|
4416 #define FMC_PCR_TAR_1 ((uint32_t)0x00004000U) /*!<Bit 1 */
|
|
|
4417 #define FMC_PCR_TAR_2 ((uint32_t)0x00008000U) /*!<Bit 2 */
|
|
|
4418 #define FMC_PCR_TAR_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
4419
|
|
|
4420 #define FMC_PCR_ECCPS ((uint32_t)0x000E0000U) /*!<ECCPS[1:0] bits (ECC page size) */
|
|
|
4421 #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
|
|
|
4422 #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
|
|
|
4423 #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
|
|
|
4424
|
|
|
4425 /******************* Bit definition for FMC_SR register ********************/
|
|
|
4426 #define FMC_SR_IRS ((uint32_t)0x00000001U) /*!<Interrupt Rising Edge status */
|
|
|
4427 #define FMC_SR_ILS ((uint32_t)0x00000002U) /*!<Interrupt Level status */
|
|
|
4428 #define FMC_SR_IFS ((uint32_t)0x00000004U) /*!<Interrupt Falling Edge status */
|
|
|
4429 #define FMC_SR_IREN ((uint32_t)0x00000008U) /*!<Interrupt Rising Edge detection Enable bit */
|
|
|
4430 #define FMC_SR_ILEN ((uint32_t)0x00000010U) /*!<Interrupt Level detection Enable bit */
|
|
|
4431 #define FMC_SR_IFEN ((uint32_t)0x00000020U) /*!<Interrupt Falling Edge detection Enable bit */
|
|
|
4432 #define FMC_SR_FEMPT ((uint32_t)0x00000040U) /*!<FIFO empty */
|
|
|
4433
|
|
|
4434 /****************** Bit definition for FMC_PMEM register ******************/
|
|
|
4435 #define FMC_PMEM_MEMSET ((uint32_t)0x000000FFU) /*!<MEMSET[7:0] bits (Common memory setup time) */
|
|
|
4436 #define FMC_PMEM_MEMSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
4437 #define FMC_PMEM_MEMSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
4438 #define FMC_PMEM_MEMSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
4439 #define FMC_PMEM_MEMSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
4440 #define FMC_PMEM_MEMSET_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
4441 #define FMC_PMEM_MEMSET_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
4442 #define FMC_PMEM_MEMSET_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
4443 #define FMC_PMEM_MEMSET_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
|
|
|
4444
|
|
|
4445 #define FMC_PMEM_MEMWAIT ((uint32_t)0x0000FF00U) /*!<MEMWAIT[7:0] bits (Common memory wait time) */
|
|
|
4446 #define FMC_PMEM_MEMWAIT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
4447 #define FMC_PMEM_MEMWAIT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
4448 #define FMC_PMEM_MEMWAIT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
4449 #define FMC_PMEM_MEMWAIT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
4450 #define FMC_PMEM_MEMWAIT_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
4451 #define FMC_PMEM_MEMWAIT_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
|
|
|
4452 #define FMC_PMEM_MEMWAIT_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
|
|
|
4453 #define FMC_PMEM_MEMWAIT_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
|
|
|
4454
|
|
|
4455 #define FMC_PMEM_MEMHOLD ((uint32_t)0x00FF0000U) /*!<MEMHOLD[7:0] bits (Common memory hold time) */
|
|
|
4456 #define FMC_PMEM_MEMHOLD_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
4457 #define FMC_PMEM_MEMHOLD_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
4458 #define FMC_PMEM_MEMHOLD_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
4459 #define FMC_PMEM_MEMHOLD_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
|
|
|
4460 #define FMC_PMEM_MEMHOLD_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
|
|
|
4461 #define FMC_PMEM_MEMHOLD_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
|
|
|
4462 #define FMC_PMEM_MEMHOLD_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
|
|
|
4463 #define FMC_PMEM_MEMHOLD_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
|
|
|
4464
|
|
|
4465 #define FMC_PMEM_MEMHIZ ((uint32_t)0xFF000000U) /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
|
|
|
4466 #define FMC_PMEM_MEMHIZ_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
4467 #define FMC_PMEM_MEMHIZ_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
4468 #define FMC_PMEM_MEMHIZ_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
4469 #define FMC_PMEM_MEMHIZ_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
4470 #define FMC_PMEM_MEMHIZ_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
|
|
|
4471 #define FMC_PMEM_MEMHIZ_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
|
|
|
4472 #define FMC_PMEM_MEMHIZ_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
|
|
|
4473 #define FMC_PMEM_MEMHIZ_7 ((uint32_t)0x80000000U) /*!<Bit 7 */
|
|
|
4474
|
|
|
4475 /****************** Bit definition for FMC_PATT register *******************/
|
|
|
4476 #define FMC_PATT_ATTSET ((uint32_t)0x000000FFU) /*!<ATTSET[7:0] bits (Attribute memory setup time) */
|
|
|
4477 #define FMC_PATT_ATTSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
4478 #define FMC_PATT_ATTSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
4479 #define FMC_PATT_ATTSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
4480 #define FMC_PATT_ATTSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
4481 #define FMC_PATT_ATTSET_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
4482 #define FMC_PATT_ATTSET_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
4483 #define FMC_PATT_ATTSET_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
4484 #define FMC_PATT_ATTSET_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
|
|
|
4485
|
|
|
4486 #define FMC_PATT_ATTWAIT ((uint32_t)0x0000FF00U) /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
|
|
|
4487 #define FMC_PATT_ATTWAIT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
4488 #define FMC_PATT_ATTWAIT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
4489 #define FMC_PATT_ATTWAIT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
4490 #define FMC_PATT_ATTWAIT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
4491 #define FMC_PATT_ATTWAIT_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
4492 #define FMC_PATT_ATTWAIT_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
|
|
|
4493 #define FMC_PATT_ATTWAIT_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
|
|
|
4494 #define FMC_PATT_ATTWAIT_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
|
|
|
4495
|
|
|
4496 #define FMC_PATT_ATTHOLD ((uint32_t)0x00FF0000U) /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
|
|
|
4497 #define FMC_PATT_ATTHOLD_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
4498 #define FMC_PATT_ATTHOLD_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
4499 #define FMC_PATT_ATTHOLD_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
4500 #define FMC_PATT_ATTHOLD_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
|
|
|
4501 #define FMC_PATT_ATTHOLD_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
|
|
|
4502 #define FMC_PATT_ATTHOLD_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
|
|
|
4503 #define FMC_PATT_ATTHOLD_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
|
|
|
4504 #define FMC_PATT_ATTHOLD_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
|
|
|
4505
|
|
|
4506 #define FMC_PATT_ATTHIZ ((uint32_t)0xFF000000U) /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
|
|
|
4507 #define FMC_PATT_ATTHIZ_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
4508 #define FMC_PATT_ATTHIZ_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
4509 #define FMC_PATT_ATTHIZ_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
4510 #define FMC_PATT_ATTHIZ_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
4511 #define FMC_PATT_ATTHIZ_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
|
|
|
4512 #define FMC_PATT_ATTHIZ_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
|
|
|
4513 #define FMC_PATT_ATTHIZ_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
|
|
|
4514 #define FMC_PATT_ATTHIZ_7 ((uint32_t)0x80000000U) /*!<Bit 7 */
|
|
|
4515
|
|
|
4516 /****************** Bit definition for FMC_ECCR register *******************/
|
|
|
4517 #define FMC_ECCR_ECC ((uint32_t)0xFFFFFFFFU) /*!<ECC result */
|
|
|
4518
|
|
|
4519 /******************************************************************************/
|
|
|
4520 /* */
|
|
|
4521 /* General Purpose IOs (GPIO) */
|
|
|
4522 /* */
|
|
|
4523 /******************************************************************************/
|
|
|
4524 /****************** Bits definition for GPIO_MODER register *****************/
|
|
|
4525 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
|
|
|
4526 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
|
|
|
4527 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
|
|
|
4528 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
|
|
|
4529 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
|
|
|
4530 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
|
|
|
4531 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
|
|
|
4532 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
|
|
|
4533 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
|
|
|
4534 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
|
|
|
4535 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
|
|
|
4536 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
|
|
|
4537 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
|
|
|
4538 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
|
|
|
4539 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
|
|
|
4540 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
|
|
|
4541 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
|
|
|
4542 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
|
|
|
4543 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
|
|
|
4544 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
|
|
|
4545 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
|
|
|
4546 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
|
|
|
4547 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
|
|
|
4548 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
|
|
|
4549 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
|
|
|
4550 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
|
|
|
4551 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
|
|
|
4552 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
|
|
|
4553 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
|
|
|
4554 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
|
|
|
4555 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
|
|
|
4556 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
|
|
|
4557 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
|
|
|
4558 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
|
|
|
4559 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
|
|
|
4560 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
|
|
|
4561 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
|
|
|
4562 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
|
|
|
4563 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
|
|
|
4564 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
|
|
|
4565 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
|
|
|
4566 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
|
|
|
4567 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
|
|
|
4568 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
|
|
|
4569 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
|
|
|
4570 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
|
|
|
4571 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
|
|
|
4572 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
|
|
|
4573
|
|
|
4574 /* Legacy defines */
|
|
|
4575 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
|
|
|
4576 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
|
|
|
4577 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
|
|
|
4578 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
|
|
|
4579 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
|
|
|
4580 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
|
|
|
4581 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
|
|
|
4582 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
|
|
|
4583 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
|
|
|
4584 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
|
|
|
4585 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
|
|
|
4586 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
|
|
|
4587 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
|
|
|
4588 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
|
|
|
4589 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
|
|
|
4590 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
|
|
|
4591 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
|
|
|
4592 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
|
|
|
4593 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
|
|
|
4594 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
|
|
|
4595 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
|
|
|
4596 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
|
|
|
4597 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
|
|
|
4598 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
|
|
|
4599 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
|
|
|
4600 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
|
|
|
4601 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
|
|
|
4602 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
|
|
|
4603 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
|
|
|
4604 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
|
|
|
4605 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
|
|
|
4606 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
|
|
|
4607 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
|
|
|
4608 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
|
|
|
4609 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
|
|
|
4610 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
|
|
|
4611 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
|
|
|
4612 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
|
|
|
4613 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
|
|
|
4614 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
|
|
|
4615 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
|
|
|
4616 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
|
|
|
4617 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
|
|
|
4618 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
|
|
|
4619 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
|
|
|
4620 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
|
|
|
4621 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
|
|
|
4622 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
|
|
|
4623
|
|
|
4624 /****************** Bits definition for GPIO_OTYPER register ****************/
|
|
|
4625 #define GPIO_OTYPER_OT0 ((uint32_t)0x00000001U)
|
|
|
4626 #define GPIO_OTYPER_OT1 ((uint32_t)0x00000002U)
|
|
|
4627 #define GPIO_OTYPER_OT2 ((uint32_t)0x00000004U)
|
|
|
4628 #define GPIO_OTYPER_OT3 ((uint32_t)0x00000008U)
|
|
|
4629 #define GPIO_OTYPER_OT4 ((uint32_t)0x00000010U)
|
|
|
4630 #define GPIO_OTYPER_OT5 ((uint32_t)0x00000020U)
|
|
|
4631 #define GPIO_OTYPER_OT6 ((uint32_t)0x00000040U)
|
|
|
4632 #define GPIO_OTYPER_OT7 ((uint32_t)0x00000080U)
|
|
|
4633 #define GPIO_OTYPER_OT8 ((uint32_t)0x00000100U)
|
|
|
4634 #define GPIO_OTYPER_OT9 ((uint32_t)0x00000200U)
|
|
|
4635 #define GPIO_OTYPER_OT10 ((uint32_t)0x00000400U)
|
|
|
4636 #define GPIO_OTYPER_OT11 ((uint32_t)0x00000800U)
|
|
|
4637 #define GPIO_OTYPER_OT12 ((uint32_t)0x00001000U)
|
|
|
4638 #define GPIO_OTYPER_OT13 ((uint32_t)0x00002000U)
|
|
|
4639 #define GPIO_OTYPER_OT14 ((uint32_t)0x00004000U)
|
|
|
4640 #define GPIO_OTYPER_OT15 ((uint32_t)0x00008000U)
|
|
|
4641
|
|
|
4642 /* Legacy defines */
|
|
|
4643 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
|
|
|
4644 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
|
|
|
4645 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
|
|
|
4646 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
|
|
|
4647 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
|
|
|
4648 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
|
|
|
4649 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
|
|
|
4650 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
|
|
|
4651 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
|
|
|
4652 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
|
|
|
4653 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
|
|
|
4654 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
|
|
|
4655 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
|
|
|
4656 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
|
|
|
4657 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
|
|
|
4658 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
|
|
|
4659
|
|
|
4660 /****************** Bits definition for GPIO_OSPEEDR register ***************/
|
|
|
4661 #define GPIO_OSPEEDR_OSPEED0 ((uint32_t)0x00000003U)
|
|
|
4662 #define GPIO_OSPEEDR_OSPEED0_0 ((uint32_t)0x00000001U)
|
|
|
4663 #define GPIO_OSPEEDR_OSPEED0_1 ((uint32_t)0x00000002U)
|
|
|
4664 #define GPIO_OSPEEDR_OSPEED1 ((uint32_t)0x0000000CU)
|
|
|
4665 #define GPIO_OSPEEDR_OSPEED1_0 ((uint32_t)0x00000004U)
|
|
|
4666 #define GPIO_OSPEEDR_OSPEED1_1 ((uint32_t)0x00000008U)
|
|
|
4667 #define GPIO_OSPEEDR_OSPEED2 ((uint32_t)0x00000030U)
|
|
|
4668 #define GPIO_OSPEEDR_OSPEED2_0 ((uint32_t)0x00000010U)
|
|
|
4669 #define GPIO_OSPEEDR_OSPEED2_1 ((uint32_t)0x00000020U)
|
|
|
4670 #define GPIO_OSPEEDR_OSPEED3 ((uint32_t)0x000000C0U)
|
|
|
4671 #define GPIO_OSPEEDR_OSPEED3_0 ((uint32_t)0x00000040U)
|
|
|
4672 #define GPIO_OSPEEDR_OSPEED3_1 ((uint32_t)0x00000080U)
|
|
|
4673 #define GPIO_OSPEEDR_OSPEED4 ((uint32_t)0x00000300U)
|
|
|
4674 #define GPIO_OSPEEDR_OSPEED4_0 ((uint32_t)0x00000100U)
|
|
|
4675 #define GPIO_OSPEEDR_OSPEED4_1 ((uint32_t)0x00000200U)
|
|
|
4676 #define GPIO_OSPEEDR_OSPEED5 ((uint32_t)0x00000C00U)
|
|
|
4677 #define GPIO_OSPEEDR_OSPEED5_0 ((uint32_t)0x00000400U)
|
|
|
4678 #define GPIO_OSPEEDR_OSPEED5_1 ((uint32_t)0x00000800U)
|
|
|
4679 #define GPIO_OSPEEDR_OSPEED6 ((uint32_t)0x00003000U)
|
|
|
4680 #define GPIO_OSPEEDR_OSPEED6_0 ((uint32_t)0x00001000U)
|
|
|
4681 #define GPIO_OSPEEDR_OSPEED6_1 ((uint32_t)0x00002000U)
|
|
|
4682 #define GPIO_OSPEEDR_OSPEED7 ((uint32_t)0x0000C000U)
|
|
|
4683 #define GPIO_OSPEEDR_OSPEED7_0 ((uint32_t)0x00004000U)
|
|
|
4684 #define GPIO_OSPEEDR_OSPEED7_1 ((uint32_t)0x00008000U)
|
|
|
4685 #define GPIO_OSPEEDR_OSPEED8 ((uint32_t)0x00030000U)
|
|
|
4686 #define GPIO_OSPEEDR_OSPEED8_0 ((uint32_t)0x00010000U)
|
|
|
4687 #define GPIO_OSPEEDR_OSPEED8_1 ((uint32_t)0x00020000U)
|
|
|
4688 #define GPIO_OSPEEDR_OSPEED9 ((uint32_t)0x000C0000U)
|
|
|
4689 #define GPIO_OSPEEDR_OSPEED9_0 ((uint32_t)0x00040000U)
|
|
|
4690 #define GPIO_OSPEEDR_OSPEED9_1 ((uint32_t)0x00080000U)
|
|
|
4691 #define GPIO_OSPEEDR_OSPEED10 ((uint32_t)0x00300000U)
|
|
|
4692 #define GPIO_OSPEEDR_OSPEED10_0 ((uint32_t)0x00100000U)
|
|
|
4693 #define GPIO_OSPEEDR_OSPEED10_1 ((uint32_t)0x00200000U)
|
|
|
4694 #define GPIO_OSPEEDR_OSPEED11 ((uint32_t)0x00C00000U)
|
|
|
4695 #define GPIO_OSPEEDR_OSPEED11_0 ((uint32_t)0x00400000U)
|
|
|
4696 #define GPIO_OSPEEDR_OSPEED11_1 ((uint32_t)0x00800000U)
|
|
|
4697 #define GPIO_OSPEEDR_OSPEED12 ((uint32_t)0x03000000U)
|
|
|
4698 #define GPIO_OSPEEDR_OSPEED12_0 ((uint32_t)0x01000000U)
|
|
|
4699 #define GPIO_OSPEEDR_OSPEED12_1 ((uint32_t)0x02000000U)
|
|
|
4700 #define GPIO_OSPEEDR_OSPEED13 ((uint32_t)0x0C000000U)
|
|
|
4701 #define GPIO_OSPEEDR_OSPEED13_0 ((uint32_t)0x04000000U)
|
|
|
4702 #define GPIO_OSPEEDR_OSPEED13_1 ((uint32_t)0x08000000U)
|
|
|
4703 #define GPIO_OSPEEDR_OSPEED14 ((uint32_t)0x30000000U)
|
|
|
4704 #define GPIO_OSPEEDR_OSPEED14_0 ((uint32_t)0x10000000U)
|
|
|
4705 #define GPIO_OSPEEDR_OSPEED14_1 ((uint32_t)0x20000000U)
|
|
|
4706 #define GPIO_OSPEEDR_OSPEED15 ((uint32_t)0xC0000000U)
|
|
|
4707 #define GPIO_OSPEEDR_OSPEED15_0 ((uint32_t)0x40000000U)
|
|
|
4708 #define GPIO_OSPEEDR_OSPEED15_1 ((uint32_t)0x80000000U)
|
|
|
4709
|
|
|
4710 /* Legacy defines */
|
|
|
4711 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
|
|
|
4712 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
|
|
|
4713 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
|
|
|
4714 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
|
|
|
4715 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
|
|
|
4716 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
|
|
|
4717 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
|
|
|
4718 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
|
|
|
4719 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
|
|
|
4720 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
|
|
|
4721 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
|
|
|
4722 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
|
|
|
4723 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
|
|
|
4724 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
|
|
|
4725 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
|
|
|
4726 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
|
|
|
4727 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
|
|
|
4728 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
|
|
|
4729 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
|
|
|
4730 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
|
|
|
4731 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
|
|
|
4732 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
|
|
|
4733 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
|
|
|
4734 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
|
|
|
4735 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
|
|
|
4736 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
|
|
|
4737 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
|
|
|
4738 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
|
|
|
4739 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
|
|
|
4740 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
|
|
|
4741 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
|
|
|
4742 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
|
|
|
4743 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
|
|
|
4744 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
|
|
|
4745 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
|
|
|
4746 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
|
|
|
4747 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
|
|
|
4748 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
|
|
|
4749 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
|
|
|
4750 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
|
|
|
4751 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
|
|
|
4752 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
|
|
|
4753 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
|
|
|
4754 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
|
|
|
4755 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
|
|
|
4756 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
|
|
|
4757 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
|
|
|
4758 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
|
|
|
4759
|
|
|
4760 /****************** Bits definition for GPIO_PUPDR register *****************/
|
|
|
4761 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
|
|
|
4762 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
|
|
|
4763 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
|
|
|
4764 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
|
|
|
4765 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
|
|
|
4766 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
|
|
|
4767 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
|
|
|
4768 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
|
|
|
4769 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
|
|
|
4770 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
|
|
|
4771 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
|
|
|
4772 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
|
|
|
4773 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
|
|
|
4774 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
|
|
|
4775 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
|
|
|
4776 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
|
|
|
4777 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
|
|
|
4778 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
|
|
|
4779 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
|
|
|
4780 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
|
|
|
4781 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
|
|
|
4782 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
|
|
|
4783 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
|
|
|
4784 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
|
|
|
4785 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
|
|
|
4786 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
|
|
|
4787 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
|
|
|
4788 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
|
|
|
4789 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
|
|
|
4790 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
|
|
|
4791 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
|
|
|
4792 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
|
|
|
4793 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
|
|
|
4794 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
|
|
|
4795 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
|
|
|
4796 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
|
|
|
4797 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
|
|
|
4798 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
|
|
|
4799 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
|
|
|
4800 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
|
|
|
4801 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
|
|
|
4802 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
|
|
|
4803 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
|
|
|
4804 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
|
|
|
4805 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
|
|
|
4806 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
|
|
|
4807 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
|
|
|
4808 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
|
|
|
4809
|
|
|
4810 /* Legacy defines */
|
|
|
4811 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
|
|
|
4812 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
|
|
|
4813 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
|
|
|
4814 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
|
|
|
4815 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
|
|
|
4816 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
|
|
|
4817 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
|
|
|
4818 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
|
|
|
4819 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
|
|
|
4820 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
|
|
|
4821 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
|
|
|
4822 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
|
|
|
4823 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
|
|
|
4824 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
|
|
|
4825 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
|
|
|
4826 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
|
|
|
4827 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
|
|
|
4828 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
|
|
|
4829 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
|
|
|
4830 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
|
|
|
4831 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
|
|
|
4832 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
|
|
|
4833 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
|
|
|
4834 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
|
|
|
4835 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
|
|
|
4836 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
|
|
|
4837 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
|
|
|
4838 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
|
|
|
4839 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
|
|
|
4840 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
|
|
|
4841 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
|
|
|
4842 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
|
|
|
4843 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
|
|
|
4844 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
|
|
|
4845 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
|
|
|
4846 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
|
|
|
4847 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
|
|
|
4848 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
|
|
|
4849 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
|
|
|
4850 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
|
|
|
4851 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
|
|
|
4852 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
|
|
|
4853 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
|
|
|
4854 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
|
|
|
4855 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
|
|
|
4856 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
|
|
|
4857 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
|
|
|
4858 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
|
|
|
4859
|
|
|
4860 /****************** Bits definition for GPIO_IDR register *******************/
|
|
|
4861 #define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
|
|
|
4862 #define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
|
|
|
4863 #define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
|
|
|
4864 #define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
|
|
|
4865 #define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
|
|
|
4866 #define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
|
|
|
4867 #define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
|
|
|
4868 #define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
|
|
|
4869 #define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
|
|
|
4870 #define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
|
|
|
4871 #define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
|
|
|
4872 #define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
|
|
|
4873 #define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
|
|
|
4874 #define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
|
|
|
4875 #define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
|
|
|
4876 #define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
|
|
|
4877
|
|
|
4878 /* Legacy defines */
|
|
|
4879 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
|
|
|
4880 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
|
|
|
4881 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
|
|
|
4882 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
|
|
|
4883 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
|
|
|
4884 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
|
|
|
4885 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
|
|
|
4886 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
|
|
|
4887 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
|
|
|
4888 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
|
|
|
4889 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
|
|
|
4890 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
|
|
|
4891 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
|
|
|
4892 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
|
|
|
4893 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
|
|
|
4894 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
|
|
|
4895
|
|
|
4896 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
|
|
|
4897 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
|
|
|
4898 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
|
|
|
4899 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
|
|
|
4900 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
|
|
|
4901 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
|
|
|
4902 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
|
|
|
4903 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
|
|
|
4904 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
|
|
|
4905 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
|
|
|
4906 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
|
|
|
4907 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
|
|
|
4908 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
|
|
|
4909 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
|
|
|
4910 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
|
|
|
4911 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
|
|
|
4912 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
|
|
|
4913
|
|
|
4914 /****************** Bits definition for GPIO_ODR register *******************/
|
|
|
4915 #define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
|
|
|
4916 #define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
|
|
|
4917 #define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
|
|
|
4918 #define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
|
|
|
4919 #define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
|
|
|
4920 #define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
|
|
|
4921 #define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
|
|
|
4922 #define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
|
|
|
4923 #define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
|
|
|
4924 #define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
|
|
|
4925 #define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
|
|
|
4926 #define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
|
|
|
4927 #define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
|
|
|
4928 #define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
|
|
|
4929 #define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
|
|
|
4930 #define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
|
|
|
4931
|
|
|
4932 /* Legacy defines */
|
|
|
4933 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
|
|
|
4934 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
|
|
|
4935 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
|
|
|
4936 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
|
|
|
4937 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
|
|
|
4938 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
|
|
|
4939 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
|
|
|
4940 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
|
|
|
4941 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
|
|
|
4942 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
|
|
|
4943 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
|
|
|
4944 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
|
|
|
4945 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
|
|
|
4946 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
|
|
|
4947 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
|
|
|
4948 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
|
|
|
4949
|
|
|
4950 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
|
|
|
4951 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
|
|
|
4952 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
|
|
|
4953 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
|
|
|
4954 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
|
|
|
4955 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
|
|
|
4956 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
|
|
|
4957 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
|
|
|
4958 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
|
|
|
4959 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
|
|
|
4960 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
|
|
|
4961 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
|
|
|
4962 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
|
|
|
4963 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
|
|
|
4964 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
|
|
|
4965 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
|
|
|
4966 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
|
|
|
4967
|
|
|
4968 /****************** Bits definition for GPIO_BSRR register ******************/
|
|
|
4969 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001U)
|
|
|
4970 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002U)
|
|
|
4971 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004U)
|
|
|
4972 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008U)
|
|
|
4973 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010U)
|
|
|
4974 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020U)
|
|
|
4975 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040U)
|
|
|
4976 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080U)
|
|
|
4977 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100U)
|
|
|
4978 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200U)
|
|
|
4979 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400U)
|
|
|
4980 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800U)
|
|
|
4981 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000U)
|
|
|
4982 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000U)
|
|
|
4983 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000U)
|
|
|
4984 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000U)
|
|
|
4985 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000U)
|
|
|
4986 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000U)
|
|
|
4987 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000U)
|
|
|
4988 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000U)
|
|
|
4989 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000U)
|
|
|
4990 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000U)
|
|
|
4991 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000U)
|
|
|
4992 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000U)
|
|
|
4993 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000U)
|
|
|
4994 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000U)
|
|
|
4995 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000U)
|
|
|
4996 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000U)
|
|
|
4997 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000U)
|
|
|
4998 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000U)
|
|
|
4999 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000U)
|
|
|
5000 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000U)
|
|
|
5001
|
|
|
5002 /* Legacy defines */
|
|
|
5003 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
|
|
|
5004 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
|
|
|
5005 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
|
|
|
5006 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
|
|
|
5007 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
|
|
|
5008 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
|
|
|
5009 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
|
|
|
5010 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
|
|
|
5011 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
|
|
|
5012 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
|
|
|
5013 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
|
|
|
5014 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
|
|
|
5015 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
|
|
|
5016 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
|
|
|
5017 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
|
|
|
5018 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
|
|
|
5019 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
|
|
|
5020 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
|
|
|
5021 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
|
|
|
5022 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
|
|
|
5023 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
|
|
|
5024 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
|
|
|
5025 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
|
|
|
5026 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
|
|
|
5027 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
|
|
|
5028 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
|
|
|
5029 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
|
|
|
5030 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
|
|
|
5031 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
|
|
|
5032 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
|
|
|
5033 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
|
|
|
5034 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
|
|
|
5035
|
|
|
5036 /****************** Bit definition for GPIO_LCKR register *********************/
|
|
|
5037 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
|
|
|
5038 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
|
|
|
5039 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
|
|
|
5040 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
|
|
|
5041 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
|
|
|
5042 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
|
|
|
5043 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
|
|
|
5044 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
|
|
|
5045 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
|
|
|
5046 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
|
|
|
5047 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
|
|
|
5048 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
|
|
|
5049 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
|
|
|
5050 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
|
|
|
5051 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
|
|
|
5052 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
|
|
|
5053 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
|
|
|
5054
|
|
|
5055 /****************** Bit definition for GPIO_AFRL register *********************/
|
|
|
5056 #define GPIO_AFRL_AFSEL0 ((uint32_t)0x0000000FU)
|
|
|
5057 #define GPIO_AFRL_AFSEL0_0 ((uint32_t)0x00000001U)
|
|
|
5058 #define GPIO_AFRL_AFSEL0_1 ((uint32_t)0x00000002U)
|
|
|
5059 #define GPIO_AFRL_AFSEL0_2 ((uint32_t)0x00000004U)
|
|
|
5060 #define GPIO_AFRL_AFSEL0_3 ((uint32_t)0x00000008U)
|
|
|
5061 #define GPIO_AFRL_AFSEL1 ((uint32_t)0x000000F0U)
|
|
|
5062 #define GPIO_AFRL_AFSEL1_0 ((uint32_t)0x00000010U)
|
|
|
5063 #define GPIO_AFRL_AFSEL1_1 ((uint32_t)0x00000020U)
|
|
|
5064 #define GPIO_AFRL_AFSEL1_2 ((uint32_t)0x00000040U)
|
|
|
5065 #define GPIO_AFRL_AFSEL1_3 ((uint32_t)0x00000080U)
|
|
|
5066 #define GPIO_AFRL_AFSEL2 ((uint32_t)0x00000F00U)
|
|
|
5067 #define GPIO_AFRL_AFSEL2_0 ((uint32_t)0x00000100U)
|
|
|
5068 #define GPIO_AFRL_AFSEL2_1 ((uint32_t)0x00000200U)
|
|
|
5069 #define GPIO_AFRL_AFSEL2_2 ((uint32_t)0x00000400U)
|
|
|
5070 #define GPIO_AFRL_AFSEL2_3 ((uint32_t)0x00000800U)
|
|
|
5071 #define GPIO_AFRL_AFSEL3 ((uint32_t)0x0000F000U)
|
|
|
5072 #define GPIO_AFRL_AFSEL3_0 ((uint32_t)0x00001000U)
|
|
|
5073 #define GPIO_AFRL_AFSEL3_1 ((uint32_t)0x00002000U)
|
|
|
5074 #define GPIO_AFRL_AFSEL3_2 ((uint32_t)0x00004000U)
|
|
|
5075 #define GPIO_AFRL_AFSEL3_3 ((uint32_t)0x00008000U)
|
|
|
5076 #define GPIO_AFRL_AFSEL4 ((uint32_t)0x000F0000U)
|
|
|
5077 #define GPIO_AFRL_AFSEL4_0 ((uint32_t)0x00010000U)
|
|
|
5078 #define GPIO_AFRL_AFSEL4_1 ((uint32_t)0x00020000U)
|
|
|
5079 #define GPIO_AFRL_AFSEL4_2 ((uint32_t)0x00040000U)
|
|
|
5080 #define GPIO_AFRL_AFSEL4_3 ((uint32_t)0x00080000U)
|
|
|
5081 #define GPIO_AFRL_AFSEL5 ((uint32_t)0x00F00000U)
|
|
|
5082 #define GPIO_AFRL_AFSEL5_0 ((uint32_t)0x00100000U)
|
|
|
5083 #define GPIO_AFRL_AFSEL5_1 ((uint32_t)0x00200000U)
|
|
|
5084 #define GPIO_AFRL_AFSEL5_2 ((uint32_t)0x00400000U)
|
|
|
5085 #define GPIO_AFRL_AFSEL5_3 ((uint32_t)0x00800000U)
|
|
|
5086 #define GPIO_AFRL_AFSEL6 ((uint32_t)0x0F000000U)
|
|
|
5087 #define GPIO_AFRL_AFSEL6_0 ((uint32_t)0x01000000U)
|
|
|
5088 #define GPIO_AFRL_AFSEL6_1 ((uint32_t)0x02000000U)
|
|
|
5089 #define GPIO_AFRL_AFSEL6_2 ((uint32_t)0x04000000U)
|
|
|
5090 #define GPIO_AFRL_AFSEL6_3 ((uint32_t)0x08000000U)
|
|
|
5091 #define GPIO_AFRL_AFSEL7 ((uint32_t)0xF0000000U)
|
|
|
5092 #define GPIO_AFRL_AFSEL7_0 ((uint32_t)0x10000000U)
|
|
|
5093 #define GPIO_AFRL_AFSEL7_1 ((uint32_t)0x20000000U)
|
|
|
5094 #define GPIO_AFRL_AFSEL7_2 ((uint32_t)0x40000000U)
|
|
|
5095 #define GPIO_AFRL_AFSEL7_3 ((uint32_t)0x80000000U)
|
|
|
5096
|
|
|
5097 /* Legacy defines */
|
|
|
5098 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
|
|
|
5099 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
|
|
|
5100 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
|
|
|
5101 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
|
|
|
5102 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
|
|
|
5103 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
|
|
|
5104 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
|
|
|
5105 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
|
|
|
5106
|
|
|
5107 /****************** Bit definition for GPIO_AFRH register *********************/
|
|
|
5108 #define GPIO_AFRH_AFSEL8 ((uint32_t)0x0000000FU)
|
|
|
5109 #define GPIO_AFRH_AFSEL8_0 ((uint32_t)0x00000001U)
|
|
|
5110 #define GPIO_AFRH_AFSEL8_1 ((uint32_t)0x00000002U)
|
|
|
5111 #define GPIO_AFRH_AFSEL8_2 ((uint32_t)0x00000004U)
|
|
|
5112 #define GPIO_AFRH_AFSEL8_3 ((uint32_t)0x00000008U)
|
|
|
5113 #define GPIO_AFRH_AFSEL9 ((uint32_t)0x000000F0U)
|
|
|
5114 #define GPIO_AFRH_AFSEL9_0 ((uint32_t)0x00000010U)
|
|
|
5115 #define GPIO_AFRH_AFSEL9_1 ((uint32_t)0x00000020U)
|
|
|
5116 #define GPIO_AFRH_AFSEL9_2 ((uint32_t)0x00000040U)
|
|
|
5117 #define GPIO_AFRH_AFSEL9_3 ((uint32_t)0x00000080U)
|
|
|
5118 #define GPIO_AFRH_AFSEL10 ((uint32_t)0x00000F00U)
|
|
|
5119 #define GPIO_AFRH_AFSEL10_0 ((uint32_t)0x00000100U)
|
|
|
5120 #define GPIO_AFRH_AFSEL10_1 ((uint32_t)0x00000200U)
|
|
|
5121 #define GPIO_AFRH_AFSEL10_2 ((uint32_t)0x00000400U)
|
|
|
5122 #define GPIO_AFRH_AFSEL10_3 ((uint32_t)0x00000800U)
|
|
|
5123 #define GPIO_AFRH_AFSEL11 ((uint32_t)0x0000F000U)
|
|
|
5124 #define GPIO_AFRH_AFSEL11_0 ((uint32_t)0x00001000U)
|
|
|
5125 #define GPIO_AFRH_AFSEL11_1 ((uint32_t)0x00002000U)
|
|
|
5126 #define GPIO_AFRH_AFSEL11_2 ((uint32_t)0x00004000U)
|
|
|
5127 #define GPIO_AFRH_AFSEL11_3 ((uint32_t)0x00008000U)
|
|
|
5128 #define GPIO_AFRH_AFSEL12 ((uint32_t)0x000F0000U)
|
|
|
5129 #define GPIO_AFRH_AFSEL12_0 ((uint32_t)0x00010000U)
|
|
|
5130 #define GPIO_AFRH_AFSEL12_1 ((uint32_t)0x00020000U)
|
|
|
5131 #define GPIO_AFRH_AFSEL12_2 ((uint32_t)0x00040000U)
|
|
|
5132 #define GPIO_AFRH_AFSEL12_3 ((uint32_t)0x00080000U)
|
|
|
5133 #define GPIO_AFRH_AFSEL13 ((uint32_t)0x00F00000U)
|
|
|
5134 #define GPIO_AFRH_AFSEL13_0 ((uint32_t)0x00100000U)
|
|
|
5135 #define GPIO_AFRH_AFSEL13_1 ((uint32_t)0x00200000U)
|
|
|
5136 #define GPIO_AFRH_AFSEL13_2 ((uint32_t)0x00400000U)
|
|
|
5137 #define GPIO_AFRH_AFSEL13_3 ((uint32_t)0x00800000U)
|
|
|
5138 #define GPIO_AFRH_AFSEL14 ((uint32_t)0x0F000000U)
|
|
|
5139 #define GPIO_AFRH_AFSEL14_0 ((uint32_t)0x01000000U)
|
|
|
5140 #define GPIO_AFRH_AFSEL14_1 ((uint32_t)0x02000000U)
|
|
|
5141 #define GPIO_AFRH_AFSEL14_2 ((uint32_t)0x04000000U)
|
|
|
5142 #define GPIO_AFRH_AFSEL14_3 ((uint32_t)0x08000000U)
|
|
|
5143 #define GPIO_AFRH_AFSEL15 ((uint32_t)0xF0000000U)
|
|
|
5144 #define GPIO_AFRH_AFSEL15_0 ((uint32_t)0x10000000U)
|
|
|
5145 #define GPIO_AFRH_AFSEL15_1 ((uint32_t)0x20000000U)
|
|
|
5146 #define GPIO_AFRH_AFSEL15_2 ((uint32_t)0x40000000U)
|
|
|
5147 #define GPIO_AFRH_AFSEL15_3 ((uint32_t)0x80000000U)
|
|
|
5148
|
|
|
5149 /* Legacy defines */
|
|
|
5150 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
|
|
|
5151 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
|
|
|
5152 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
|
|
|
5153 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
|
|
|
5154 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
|
|
|
5155 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
|
|
|
5156 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
|
|
|
5157 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
|
|
|
5158
|
|
|
5159 /****************** Bits definition for GPIO_BRR register ******************/
|
|
|
5160 #define GPIO_BRR_BR0 ((uint32_t)0x00000001U)
|
|
|
5161 #define GPIO_BRR_BR1 ((uint32_t)0x00000002U)
|
|
|
5162 #define GPIO_BRR_BR2 ((uint32_t)0x00000004U)
|
|
|
5163 #define GPIO_BRR_BR3 ((uint32_t)0x00000008U)
|
|
|
5164 #define GPIO_BRR_BR4 ((uint32_t)0x00000010U)
|
|
|
5165 #define GPIO_BRR_BR5 ((uint32_t)0x00000020U)
|
|
|
5166 #define GPIO_BRR_BR6 ((uint32_t)0x00000040U)
|
|
|
5167 #define GPIO_BRR_BR7 ((uint32_t)0x00000080U)
|
|
|
5168 #define GPIO_BRR_BR8 ((uint32_t)0x00000100U)
|
|
|
5169 #define GPIO_BRR_BR9 ((uint32_t)0x00000200U)
|
|
|
5170 #define GPIO_BRR_BR10 ((uint32_t)0x00000400U)
|
|
|
5171 #define GPIO_BRR_BR11 ((uint32_t)0x00000800U)
|
|
|
5172 #define GPIO_BRR_BR12 ((uint32_t)0x00001000U)
|
|
|
5173 #define GPIO_BRR_BR13 ((uint32_t)0x00002000U)
|
|
|
5174 #define GPIO_BRR_BR14 ((uint32_t)0x00004000U)
|
|
|
5175 #define GPIO_BRR_BR15 ((uint32_t)0x00008000U)
|
|
|
5176
|
|
|
5177 /* Legacy defines */
|
|
|
5178 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
|
|
|
5179 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
|
|
|
5180 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
|
|
|
5181 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
|
|
|
5182 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
|
|
|
5183 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
|
|
|
5184 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
|
|
|
5185 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
|
|
|
5186 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
|
|
|
5187 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
|
|
|
5188 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
|
|
|
5189 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
|
|
|
5190 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
|
|
|
5191 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
|
|
|
5192 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
|
|
|
5193 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
|
|
|
5194
|
|
|
5195
|
|
|
5196 /****************** Bits definition for GPIO_ASCR register *******************/
|
|
|
5197 #define GPIO_ASCR_ASC0 ((uint32_t)0x00000001U)
|
|
|
5198 #define GPIO_ASCR_ASC1 ((uint32_t)0x00000002U)
|
|
|
5199 #define GPIO_ASCR_ASC2 ((uint32_t)0x00000004U)
|
|
|
5200 #define GPIO_ASCR_ASC3 ((uint32_t)0x00000008U)
|
|
|
5201 #define GPIO_ASCR_ASC4 ((uint32_t)0x00000010U)
|
|
|
5202 #define GPIO_ASCR_ASC5 ((uint32_t)0x00000020U)
|
|
|
5203 #define GPIO_ASCR_ASC6 ((uint32_t)0x00000040U)
|
|
|
5204 #define GPIO_ASCR_ASC7 ((uint32_t)0x00000080U)
|
|
|
5205 #define GPIO_ASCR_ASC8 ((uint32_t)0x00000100U)
|
|
|
5206 #define GPIO_ASCR_ASC9 ((uint32_t)0x00000200U)
|
|
|
5207 #define GPIO_ASCR_ASC10 ((uint32_t)0x00000400U)
|
|
|
5208 #define GPIO_ASCR_ASC11 ((uint32_t)0x00000800U)
|
|
|
5209 #define GPIO_ASCR_ASC12 ((uint32_t)0x00001000U)
|
|
|
5210 #define GPIO_ASCR_ASC13 ((uint32_t)0x00002000U)
|
|
|
5211 #define GPIO_ASCR_ASC14 ((uint32_t)0x00004000U)
|
|
|
5212 #define GPIO_ASCR_ASC15 ((uint32_t)0x00008000U)
|
|
|
5213
|
|
|
5214 /* Legacy defines */
|
|
|
5215 #define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
|
|
|
5216 #define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
|
|
|
5217 #define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
|
|
|
5218 #define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
|
|
|
5219 #define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
|
|
|
5220 #define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
|
|
|
5221 #define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
|
|
|
5222 #define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
|
|
|
5223 #define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
|
|
|
5224 #define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
|
|
|
5225 #define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
|
|
|
5226 #define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
|
|
|
5227 #define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
|
|
|
5228 #define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
|
|
|
5229 #define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
|
|
|
5230 #define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
|
|
|
5231
|
|
|
5232 /******************************************************************************/
|
|
|
5233 /* */
|
|
|
5234 /* Inter-integrated Circuit Interface (I2C) */
|
|
|
5235 /* */
|
|
|
5236 /******************************************************************************/
|
|
|
5237 /******************* Bit definition for I2C_CR1 register *******************/
|
|
|
5238 #define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */
|
|
|
5239 #define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */
|
|
|
5240 #define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */
|
|
|
5241 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */
|
|
|
5242 #define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */
|
|
|
5243 #define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */
|
|
|
5244 #define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */
|
|
|
5245 #define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */
|
|
|
5246 #define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */
|
|
|
5247 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */
|
|
|
5248 #define I2C_CR1_SWRST ((uint32_t)0x00002000U) /*!< Software reset */
|
|
|
5249 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */
|
|
|
5250 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */
|
|
|
5251 #define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */
|
|
|
5252 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */
|
|
|
5253 #define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */
|
|
|
5254 #define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */
|
|
|
5255 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */
|
|
|
5256 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */
|
|
|
5257 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */
|
|
|
5258 #define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */
|
|
|
5259
|
|
|
5260 /****************** Bit definition for I2C_CR2 register ********************/
|
|
|
5261 #define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */
|
|
|
5262 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */
|
|
|
5263 #define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */
|
|
|
5264 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */
|
|
|
5265 #define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */
|
|
|
5266 #define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */
|
|
|
5267 #define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */
|
|
|
5268 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */
|
|
|
5269 #define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */
|
|
|
5270 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */
|
|
|
5271 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */
|
|
|
5272
|
|
|
5273 /******************* Bit definition for I2C_OAR1 register ******************/
|
|
|
5274 #define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */
|
|
|
5275 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */
|
|
|
5276 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */
|
|
|
5277
|
|
|
5278 /******************* Bit definition for I2C_OAR2 register ******************/
|
|
|
5279 #define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */
|
|
|
5280 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */
|
|
|
5281 #define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */
|
|
|
5282 #define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
|
|
|
5283 #define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
|
|
|
5284 #define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
|
|
|
5285 #define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
|
|
|
5286 #define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
|
|
|
5287 #define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
|
|
|
5288 #define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */
|
|
|
5289 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */
|
|
|
5290
|
|
|
5291 /******************* Bit definition for I2C_TIMINGR register *******************/
|
|
|
5292 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */
|
|
|
5293 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */
|
|
|
5294 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */
|
|
|
5295 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */
|
|
|
5296 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */
|
|
|
5297
|
|
|
5298 /******************* Bit definition for I2C_TIMEOUTR register *******************/
|
|
|
5299 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */
|
|
|
5300 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */
|
|
|
5301 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */
|
|
|
5302 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B */
|
|
|
5303 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */
|
|
|
5304
|
|
|
5305 /****************** Bit definition for I2C_ISR register *********************/
|
|
|
5306 #define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */
|
|
|
5307 #define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */
|
|
|
5308 #define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */
|
|
|
5309 #define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode) */
|
|
|
5310 #define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */
|
|
|
5311 #define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */
|
|
|
5312 #define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */
|
|
|
5313 #define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */
|
|
|
5314 #define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */
|
|
|
5315 #define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */
|
|
|
5316 #define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */
|
|
|
5317 #define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */
|
|
|
5318 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */
|
|
|
5319 #define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */
|
|
|
5320 #define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */
|
|
|
5321 #define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */
|
|
|
5322 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */
|
|
|
5323
|
|
|
5324 /****************** Bit definition for I2C_ICR register *********************/
|
|
|
5325 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */
|
|
|
5326 #define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */
|
|
|
5327 #define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */
|
|
|
5328 #define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */
|
|
|
5329 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */
|
|
|
5330 #define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */
|
|
|
5331 #define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */
|
|
|
5332 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */
|
|
|
5333 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */
|
|
|
5334
|
|
|
5335 /****************** Bit definition for I2C_PECR register *********************/
|
|
|
5336 #define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */
|
|
|
5337
|
|
|
5338 /****************** Bit definition for I2C_RXDR register *********************/
|
|
|
5339 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */
|
|
|
5340
|
|
|
5341 /****************** Bit definition for I2C_TXDR register *********************/
|
|
|
5342 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */
|
|
|
5343
|
|
|
5344 /******************************************************************************/
|
|
|
5345 /* */
|
|
|
5346 /* Independent WATCHDOG */
|
|
|
5347 /* */
|
|
|
5348 /******************************************************************************/
|
|
|
5349 /******************* Bit definition for IWDG_KR register ********************/
|
|
|
5350 #define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!<Key value (write only, read 0000h) */
|
|
|
5351
|
|
|
5352 /******************* Bit definition for IWDG_PR register ********************/
|
|
|
5353 #define IWDG_PR_PR ((uint32_t)0x00000007U) /*!<PR[2:0] (Prescaler divider) */
|
|
|
5354 #define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
5355 #define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
5356 #define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
5357
|
|
|
5358 /******************* Bit definition for IWDG_RLR register *******************/
|
|
|
5359 #define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!<Watchdog counter reload value */
|
|
|
5360
|
|
|
5361 /******************* Bit definition for IWDG_SR register ********************/
|
|
|
5362 #define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
|
|
|
5363 #define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
|
|
|
5364 #define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */
|
|
|
5365
|
|
|
5366 /******************* Bit definition for IWDG_KR register ********************/
|
|
|
5367 #define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */
|
|
|
5368
|
|
|
5369 /******************************************************************************/
|
|
|
5370 /* */
|
|
|
5371 /* Firewall */
|
|
|
5372 /* */
|
|
|
5373 /******************************************************************************/
|
|
|
5374
|
|
|
5375 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */
|
|
|
5376 #define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */
|
|
|
5377 #define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */
|
|
|
5378 #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */
|
|
|
5379 #define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */
|
|
|
5380 #define FW_VDSSA_ADD ((uint32_t)0x0001FFC0U) /*!< Volatile Data Segment Start Address */
|
|
|
5381 #define FW_VDSL_LENG ((uint32_t)0x0001FFC0U) /*!< Volatile Data Segment Length */
|
|
|
5382 #define FW_LSSA_ADD ((uint32_t)0x0007FF80U) /*!< Library Segment Start Address*/
|
|
|
5383 #define FW_LSL_LENG ((uint32_t)0x0007FF80U) /*!< Library Segment Length*/
|
|
|
5384
|
|
|
5385 /**************************Bit definition for CR register *********************/
|
|
|
5386 #define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/
|
|
|
5387 #define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/
|
|
|
5388 #define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/
|
|
|
5389
|
|
|
5390 /******************************************************************************/
|
|
|
5391 /* */
|
|
|
5392 /* Power Control */
|
|
|
5393 /* */
|
|
|
5394 /******************************************************************************/
|
|
|
5395
|
|
|
5396 /******************** Bit definition for PWR_CR1 register ********************/
|
|
|
5397
|
|
|
5398 #define PWR_CR1_LPR ((uint32_t)0x00004000U) /*!< Regulator low-power mode */
|
|
|
5399 #define PWR_CR1_VOS ((uint32_t)0x00000600U) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
|
|
|
5400 #define PWR_CR1_VOS_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
|
|
|
5401 #define PWR_CR1_VOS_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
|
|
|
5402 #define PWR_CR1_DBP ((uint32_t)0x00000100U) /*!< Disable Back-up domain Protection */
|
|
|
5403 #define PWR_CR1_LPMS ((uint32_t)0x00000007U) /*!< Low-power mode selection field */
|
|
|
5404 #define PWR_CR1_LPMS_STOP0 ((uint32_t)0x00000000U) /*!< Stop 0 mode */
|
|
|
5405 #define PWR_CR1_LPMS_STOP1 ((uint32_t)0x00000001U) /*!< Stop 1 mode */
|
|
|
5406 #define PWR_CR1_LPMS_STOP2 ((uint32_t)0x00000002U) /*!< Stop 2 mode */
|
|
|
5407 #define PWR_CR1_LPMS_STANDBY ((uint32_t)0x00000003U) /*!< Stand-by mode */
|
|
|
5408 #define PWR_CR1_LPMS_SHUTDOWN ((uint32_t)0x00000004U) /*!< Shut-down mode */
|
|
|
5409
|
|
|
5410
|
|
|
5411 /******************** Bit definition for PWR_CR2 register ********************/
|
|
|
5412 #define PWR_CR2_USV ((uint32_t)0x00000400U) /*!< VDD USB Supply Valid */
|
|
|
5413 #define PWR_CR2_IOSV ((uint32_t)0x00000200U) /*!< VDD IO2 independent I/Os Supply Valid */
|
|
|
5414 /*!< PVME Peripheral Voltage Monitor Enable */
|
|
|
5415 #define PWR_CR2_PVME ((uint32_t)0x000000F0U) /*!< PVM bits field */
|
|
|
5416 #define PWR_CR2_PVME4 ((uint32_t)0x00000080U) /*!< PVM 4 Enable */
|
|
|
5417 #define PWR_CR2_PVME3 ((uint32_t)0x00000040U) /*!< PVM 3 Enable */
|
|
|
5418 #define PWR_CR2_PVME2 ((uint32_t)0x00000020U) /*!< PVM 2 Enable */
|
|
|
5419 #define PWR_CR2_PVME1 ((uint32_t)0x00000010U) /*!< PVM 1 Enable */
|
|
|
5420 /*!< PVD level configuration */
|
|
|
5421 #define PWR_CR2_PLS ((uint32_t)0x0000000EU) /*!< PVD level selection */
|
|
|
5422 #define PWR_CR2_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
|
|
|
5423 #define PWR_CR2_PLS_LEV1 ((uint32_t)0x00000002U) /*!< PVD level 1 */
|
|
|
5424 #define PWR_CR2_PLS_LEV2 ((uint32_t)0x00000004U) /*!< PVD level 2 */
|
|
|
5425 #define PWR_CR2_PLS_LEV3 ((uint32_t)0x00000006U) /*!< PVD level 3 */
|
|
|
5426 #define PWR_CR2_PLS_LEV4 ((uint32_t)0x00000008U) /*!< PVD level 4 */
|
|
|
5427 #define PWR_CR2_PLS_LEV5 ((uint32_t)0x0000000AU) /*!< PVD level 5 */
|
|
|
5428 #define PWR_CR2_PLS_LEV6 ((uint32_t)0x0000000CU) /*!< PVD level 6 */
|
|
|
5429 #define PWR_CR2_PLS_LEV7 ((uint32_t)0x0000000EU) /*!< PVD level 7 */
|
|
|
5430 #define PWR_CR2_PVDE ((uint32_t)0x00000001U) /*!< Power Voltage Detector Enable */
|
|
|
5431
|
|
|
5432 /******************** Bit definition for PWR_CR3 register ********************/
|
|
|
5433 #define PWR_CR3_EIWF ((uint32_t)0x00008000U) /*!< Enable Internal Wake-up line */
|
|
|
5434 #define PWR_CR3_APC ((uint32_t)0x00000400U) /*!< Apply pull-up and pull-down configuration */
|
|
|
5435 #define PWR_CR3_RRS ((uint32_t)0x00000100U) /*!< SRAM2 Retention in Stand-by mode */
|
|
|
5436 #define PWR_CR3_EWUP5 ((uint32_t)0x00000010U) /*!< Enable Wake-Up Pin 5 */
|
|
|
5437 #define PWR_CR3_EWUP4 ((uint32_t)0x00000008U) /*!< Enable Wake-Up Pin 4 */
|
|
|
5438 #define PWR_CR3_EWUP3 ((uint32_t)0x00000004U) /*!< Enable Wake-Up Pin 3 */
|
|
|
5439 #define PWR_CR3_EWUP2 ((uint32_t)0x00000002U) /*!< Enable Wake-Up Pin 2 */
|
|
|
5440 #define PWR_CR3_EWUP1 ((uint32_t)0x00000001U) /*!< Enable Wake-Up Pin 1 */
|
|
|
5441 #define PWR_CR3_EWUP ((uint32_t)0x0000001FU) /*!< Enable Wake-Up Pins */
|
|
|
5442
|
|
|
5443 /******************** Bit definition for PWR_CR4 register ********************/
|
|
|
5444 #define PWR_CR4_VBRS ((uint32_t)0x00000200U) /*!< VBAT Battery charging Resistor Selection */
|
|
|
5445 #define PWR_CR4_VBE ((uint32_t)0x00000100U) /*!< VBAT Battery charging Enable */
|
|
|
5446 #define PWR_CR4_WP5 ((uint32_t)0x00000010U) /*!< Wake-Up Pin 5 polarity */
|
|
|
5447 #define PWR_CR4_WP4 ((uint32_t)0x00000008U) /*!< Wake-Up Pin 4 polarity */
|
|
|
5448 #define PWR_CR4_WP3 ((uint32_t)0x00000004U) /*!< Wake-Up Pin 3 polarity */
|
|
|
5449 #define PWR_CR4_WP2 ((uint32_t)0x00000002U) /*!< Wake-Up Pin 2 polarity */
|
|
|
5450 #define PWR_CR4_WP1 ((uint32_t)0x00000001U) /*!< Wake-Up Pin 1 polarity */
|
|
|
5451
|
|
|
5452 /******************** Bit definition for PWR_SR1 register ********************/
|
|
|
5453 #define PWR_SR1_WUFI ((uint32_t)0x00008000U) /*!< Wake-Up Flag Internal */
|
|
|
5454 #define PWR_SR1_SBF ((uint32_t)0x00000100U) /*!< Stand-By Flag */
|
|
|
5455 #define PWR_SR1_WUF ((uint32_t)0x0000001FU) /*!< Wake-up Flags */
|
|
|
5456 #define PWR_SR1_WUF5 ((uint32_t)0x00000010U) /*!< Wake-up Flag 5 */
|
|
|
5457 #define PWR_SR1_WUF4 ((uint32_t)0x00000008U) /*!< Wake-up Flag 4 */
|
|
|
5458 #define PWR_SR1_WUF3 ((uint32_t)0x00000004U) /*!< Wake-up Flag 3 */
|
|
|
5459 #define PWR_SR1_WUF2 ((uint32_t)0x00000002U) /*!< Wake-up Flag 2 */
|
|
|
5460 #define PWR_SR1_WUF1 ((uint32_t)0x00000001U) /*!< Wake-up Flag 1 */
|
|
|
5461
|
|
|
5462 /******************** Bit definition for PWR_SR2 register ********************/
|
|
|
5463 #define PWR_SR2_PVMO4 ((uint32_t)0x00008000U) /*!< Peripheral Voltage Monitoring Output 4 */
|
|
|
5464 #define PWR_SR2_PVMO3 ((uint32_t)0x00004000U) /*!< Peripheral Voltage Monitoring Output 3 */
|
|
|
5465 #define PWR_SR2_PVMO2 ((uint32_t)0x00002000U) /*!< Peripheral Voltage Monitoring Output 2 */
|
|
|
5466 #define PWR_SR2_PVMO1 ((uint32_t)0x00001000U) /*!< Peripheral Voltage Monitoring Output 1 */
|
|
|
5467 #define PWR_SR2_PVDO ((uint32_t)0x00000800U) /*!< Power Voltage Detector Output */
|
|
|
5468 #define PWR_SR2_VOSF ((uint32_t)0x00000400U) /*!< Voltage Scaling Flag */
|
|
|
5469 #define PWR_SR2_REGLPF ((uint32_t)0x00000200U) /*!< Low-power Regulator Flag */
|
|
|
5470 #define PWR_SR2_REGLPS ((uint32_t)0x00000100U) /*!< Low-power Regulator Started */
|
|
|
5471
|
|
|
5472 /******************** Bit definition for PWR_SCR register ********************/
|
|
|
5473 #define PWR_SCR_CSBF ((uint32_t)0x00000100U) /*!< Clear Stand-By Flag */
|
|
|
5474 #define PWR_SCR_CWUF ((uint32_t)0x0000001FU) /*!< Clear Wake-up Flags */
|
|
|
5475 #define PWR_SCR_CWUF5 ((uint32_t)0x00000010U) /*!< Clear Wake-up Flag 5 */
|
|
|
5476 #define PWR_SCR_CWUF4 ((uint32_t)0x00000008U) /*!< Clear Wake-up Flag 4 */
|
|
|
5477 #define PWR_SCR_CWUF3 ((uint32_t)0x00000004U) /*!< Clear Wake-up Flag 3 */
|
|
|
5478 #define PWR_SCR_CWUF2 ((uint32_t)0x00000002U) /*!< Clear Wake-up Flag 2 */
|
|
|
5479 #define PWR_SCR_CWUF1 ((uint32_t)0x00000001U) /*!< Clear Wake-up Flag 1 */
|
|
|
5480
|
|
|
5481 /******************** Bit definition for PWR_PUCRA register ********************/
|
|
|
5482 #define PWR_PUCRA_PA15 ((uint32_t)0x00008000U) /*!< Port PA15 Pull-Up set */
|
|
|
5483 #define PWR_PUCRA_PA13 ((uint32_t)0x00002000U) /*!< Port PA13 Pull-Up set */
|
|
|
5484 #define PWR_PUCRA_PA12 ((uint32_t)0x00001000U) /*!< Port PA12 Pull-Up set */
|
|
|
5485 #define PWR_PUCRA_PA11 ((uint32_t)0x00000800U) /*!< Port PA11 Pull-Up set */
|
|
|
5486 #define PWR_PUCRA_PA10 ((uint32_t)0x00000400U) /*!< Port PA10 Pull-Up set */
|
|
|
5487 #define PWR_PUCRA_PA9 ((uint32_t)0x00000200U) /*!< Port PA9 Pull-Up set */
|
|
|
5488 #define PWR_PUCRA_PA8 ((uint32_t)0x00000100U) /*!< Port PA8 Pull-Up set */
|
|
|
5489 #define PWR_PUCRA_PA7 ((uint32_t)0x00000080U) /*!< Port PA7 Pull-Up set */
|
|
|
5490 #define PWR_PUCRA_PA6 ((uint32_t)0x00000040U) /*!< Port PA6 Pull-Up set */
|
|
|
5491 #define PWR_PUCRA_PA5 ((uint32_t)0x00000020U) /*!< Port PA5 Pull-Up set */
|
|
|
5492 #define PWR_PUCRA_PA4 ((uint32_t)0x00000010U) /*!< Port PA4 Pull-Up set */
|
|
|
5493 #define PWR_PUCRA_PA3 ((uint32_t)0x00000008U) /*!< Port PA3 Pull-Up set */
|
|
|
5494 #define PWR_PUCRA_PA2 ((uint32_t)0x00000004U) /*!< Port PA2 Pull-Up set */
|
|
|
5495 #define PWR_PUCRA_PA1 ((uint32_t)0x00000002U) /*!< Port PA1 Pull-Up set */
|
|
|
5496 #define PWR_PUCRA_PA0 ((uint32_t)0x00000001U) /*!< Port PA0 Pull-Up set */
|
|
|
5497
|
|
|
5498 /******************** Bit definition for PWR_PDCRA register ********************/
|
|
|
5499 #define PWR_PDCRA_PA14 ((uint32_t)0x00004000U) /*!< Port PA14 Pull-Down set */
|
|
|
5500 #define PWR_PDCRA_PA12 ((uint32_t)0x00001000U) /*!< Port PA12 Pull-Down set */
|
|
|
5501 #define PWR_PDCRA_PA11 ((uint32_t)0x00000800U) /*!< Port PA11 Pull-Down set */
|
|
|
5502 #define PWR_PDCRA_PA10 ((uint32_t)0x00000400U) /*!< Port PA10 Pull-Down set */
|
|
|
5503 #define PWR_PDCRA_PA9 ((uint32_t)0x00000200U) /*!< Port PA9 Pull-Down set */
|
|
|
5504 #define PWR_PDCRA_PA8 ((uint32_t)0x00000100U) /*!< Port PA8 Pull-Down set */
|
|
|
5505 #define PWR_PDCRA_PA7 ((uint32_t)0x00000080U) /*!< Port PA7 Pull-Down set */
|
|
|
5506 #define PWR_PDCRA_PA6 ((uint32_t)0x00000040U) /*!< Port PA6 Pull-Down set */
|
|
|
5507 #define PWR_PDCRA_PA5 ((uint32_t)0x00000020U) /*!< Port PA5 Pull-Down set */
|
|
|
5508 #define PWR_PDCRA_PA4 ((uint32_t)0x00000010U) /*!< Port PA4 Pull-Down set */
|
|
|
5509 #define PWR_PDCRA_PA3 ((uint32_t)0x00000008U) /*!< Port PA3 Pull-Down set */
|
|
|
5510 #define PWR_PDCRA_PA2 ((uint32_t)0x00000004U) /*!< Port PA2 Pull-Down set */
|
|
|
5511 #define PWR_PDCRA_PA1 ((uint32_t)0x00000002U) /*!< Port PA1 Pull-Down set */
|
|
|
5512 #define PWR_PDCRA_PA0 ((uint32_t)0x00000001U) /*!< Port PA0 Pull-Down set */
|
|
|
5513
|
|
|
5514 /******************** Bit definition for PWR_PUCRB register ********************/
|
|
|
5515 #define PWR_PUCRB_PB15 ((uint32_t)0x00008000U) /*!< Port PB15 Pull-Up set */
|
|
|
5516 #define PWR_PUCRB_PB14 ((uint32_t)0x00004000U) /*!< Port PB14 Pull-Up set */
|
|
|
5517 #define PWR_PUCRB_PB13 ((uint32_t)0x00002000U) /*!< Port PB13 Pull-Up set */
|
|
|
5518 #define PWR_PUCRB_PB12 ((uint32_t)0x00001000U) /*!< Port PB12 Pull-Up set */
|
|
|
5519 #define PWR_PUCRB_PB11 ((uint32_t)0x00000800U) /*!< Port PB11 Pull-Up set */
|
|
|
5520 #define PWR_PUCRB_PB10 ((uint32_t)0x00000400U) /*!< Port PB10 Pull-Up set */
|
|
|
5521 #define PWR_PUCRB_PB9 ((uint32_t)0x00000200U) /*!< Port PB9 Pull-Up set */
|
|
|
5522 #define PWR_PUCRB_PB8 ((uint32_t)0x00000100U) /*!< Port PB8 Pull-Up set */
|
|
|
5523 #define PWR_PUCRB_PB7 ((uint32_t)0x00000080U) /*!< Port PB7 Pull-Up set */
|
|
|
5524 #define PWR_PUCRB_PB6 ((uint32_t)0x00000040U) /*!< Port PB6 Pull-Up set */
|
|
|
5525 #define PWR_PUCRB_PB5 ((uint32_t)0x00000020U) /*!< Port PB5 Pull-Up set */
|
|
|
5526 #define PWR_PUCRB_PB4 ((uint32_t)0x00000010U) /*!< Port PB4 Pull-Up set */
|
|
|
5527 #define PWR_PUCRB_PB3 ((uint32_t)0x00000008U) /*!< Port PB3 Pull-Up set */
|
|
|
5528 #define PWR_PUCRB_PB2 ((uint32_t)0x00000004U) /*!< Port PB2 Pull-Up set */
|
|
|
5529 #define PWR_PUCRB_PB1 ((uint32_t)0x00000002U) /*!< Port PB1 Pull-Up set */
|
|
|
5530 #define PWR_PUCRB_PB0 ((uint32_t)0x00000001U) /*!< Port PB0 Pull-Up set */
|
|
|
5531
|
|
|
5532 /******************** Bit definition for PWR_PDCRB register ********************/
|
|
|
5533 #define PWR_PDCRB_PB15 ((uint32_t)0x00008000U) /*!< Port PB15 Pull-Down set */
|
|
|
5534 #define PWR_PDCRB_PB14 ((uint32_t)0x00004000U) /*!< Port PB14 Pull-Down set */
|
|
|
5535 #define PWR_PDCRB_PB13 ((uint32_t)0x00002000U) /*!< Port PB13 Pull-Down set */
|
|
|
5536 #define PWR_PDCRB_PB12 ((uint32_t)0x00001000U) /*!< Port PB12 Pull-Down set */
|
|
|
5537 #define PWR_PDCRB_PB11 ((uint32_t)0x00000800U) /*!< Port PB11 Pull-Down set */
|
|
|
5538 #define PWR_PDCRB_PB10 ((uint32_t)0x00000400U) /*!< Port PB10 Pull-Down set */
|
|
|
5539 #define PWR_PDCRB_PB9 ((uint32_t)0x00000200U) /*!< Port PB9 Pull-Down set */
|
|
|
5540 #define PWR_PDCRB_PB8 ((uint32_t)0x00000100U) /*!< Port PB8 Pull-Down set */
|
|
|
5541 #define PWR_PDCRB_PB7 ((uint32_t)0x00000080U) /*!< Port PB7 Pull-Down set */
|
|
|
5542 #define PWR_PDCRB_PB6 ((uint32_t)0x00000040U) /*!< Port PB6 Pull-Down set */
|
|
|
5543 #define PWR_PDCRB_PB5 ((uint32_t)0x00000020U) /*!< Port PB5 Pull-Down set */
|
|
|
5544 #define PWR_PDCRB_PB3 ((uint32_t)0x00000008U) /*!< Port PB3 Pull-Down set */
|
|
|
5545 #define PWR_PDCRB_PB2 ((uint32_t)0x00000004U) /*!< Port PB2 Pull-Down set */
|
|
|
5546 #define PWR_PDCRB_PB1 ((uint32_t)0x00000002U) /*!< Port PB1 Pull-Down set */
|
|
|
5547 #define PWR_PDCRB_PB0 ((uint32_t)0x00000001U) /*!< Port PB0 Pull-Down set */
|
|
|
5548
|
|
|
5549 /******************** Bit definition for PWR_PUCRC register ********************/
|
|
|
5550 #define PWR_PUCRC_PC15 ((uint32_t)0x00008000U) /*!< Port PC15 Pull-Up set */
|
|
|
5551 #define PWR_PUCRC_PC14 ((uint32_t)0x00004000U) /*!< Port PC14 Pull-Up set */
|
|
|
5552 #define PWR_PUCRC_PC13 ((uint32_t)0x00002000U) /*!< Port PC13 Pull-Up set */
|
|
|
5553 #define PWR_PUCRC_PC12 ((uint32_t)0x00001000U) /*!< Port PC12 Pull-Up set */
|
|
|
5554 #define PWR_PUCRC_PC11 ((uint32_t)0x00000800U) /*!< Port PC11 Pull-Up set */
|
|
|
5555 #define PWR_PUCRC_PC10 ((uint32_t)0x00000400U) /*!< Port PC10 Pull-Up set */
|
|
|
5556 #define PWR_PUCRC_PC9 ((uint32_t)0x00000200U) /*!< Port PC9 Pull-Up set */
|
|
|
5557 #define PWR_PUCRC_PC8 ((uint32_t)0x00000100U) /*!< Port PC8 Pull-Up set */
|
|
|
5558 #define PWR_PUCRC_PC7 ((uint32_t)0x00000080U) /*!< Port PC7 Pull-Up set */
|
|
|
5559 #define PWR_PUCRC_PC6 ((uint32_t)0x00000040U) /*!< Port PC6 Pull-Up set */
|
|
|
5560 #define PWR_PUCRC_PC5 ((uint32_t)0x00000020U) /*!< Port PC5 Pull-Up set */
|
|
|
5561 #define PWR_PUCRC_PC4 ((uint32_t)0x00000010U) /*!< Port PC4 Pull-Up set */
|
|
|
5562 #define PWR_PUCRC_PC3 ((uint32_t)0x00000008U) /*!< Port PC3 Pull-Up set */
|
|
|
5563 #define PWR_PUCRC_PC2 ((uint32_t)0x00000004U) /*!< Port PC2 Pull-Up set */
|
|
|
5564 #define PWR_PUCRC_PC1 ((uint32_t)0x00000002U) /*!< Port PC1 Pull-Up set */
|
|
|
5565 #define PWR_PUCRC_PC0 ((uint32_t)0x00000001U) /*!< Port PC0 Pull-Up set */
|
|
|
5566
|
|
|
5567 /******************** Bit definition for PWR_PDCRC register ********************/
|
|
|
5568 #define PWR_PDCRC_PC15 ((uint32_t)0x00008000U) /*!< Port PC15 Pull-Down set */
|
|
|
5569 #define PWR_PDCRC_PC14 ((uint32_t)0x00004000U) /*!< Port PC14 Pull-Down set */
|
|
|
5570 #define PWR_PDCRC_PC13 ((uint32_t)0x00002000U) /*!< Port PC13 Pull-Down set */
|
|
|
5571 #define PWR_PDCRC_PC12 ((uint32_t)0x00001000U) /*!< Port PC12 Pull-Down set */
|
|
|
5572 #define PWR_PDCRC_PC11 ((uint32_t)0x00000800U) /*!< Port PC11 Pull-Down set */
|
|
|
5573 #define PWR_PDCRC_PC10 ((uint32_t)0x00000400U) /*!< Port PC10 Pull-Down set */
|
|
|
5574 #define PWR_PDCRC_PC9 ((uint32_t)0x00000200U) /*!< Port PC9 Pull-Down set */
|
|
|
5575 #define PWR_PDCRC_PC8 ((uint32_t)0x00000100U) /*!< Port PC8 Pull-Down set */
|
|
|
5576 #define PWR_PDCRC_PC7 ((uint32_t)0x00000080U) /*!< Port PC7 Pull-Down set */
|
|
|
5577 #define PWR_PDCRC_PC6 ((uint32_t)0x00000040U) /*!< Port PC6 Pull-Down set */
|
|
|
5578 #define PWR_PDCRC_PC5 ((uint32_t)0x00000020U) /*!< Port PC5 Pull-Down set */
|
|
|
5579 #define PWR_PDCRC_PC4 ((uint32_t)0x00000010U) /*!< Port PC4 Pull-Down set */
|
|
|
5580 #define PWR_PDCRC_PC3 ((uint32_t)0x00000008U) /*!< Port PC3 Pull-Down set */
|
|
|
5581 #define PWR_PDCRC_PC2 ((uint32_t)0x00000004U) /*!< Port PC2 Pull-Down set */
|
|
|
5582 #define PWR_PDCRC_PC1 ((uint32_t)0x00000002U) /*!< Port PC1 Pull-Down set */
|
|
|
5583 #define PWR_PDCRC_PC0 ((uint32_t)0x00000001U) /*!< Port PC0 Pull-Down set */
|
|
|
5584
|
|
|
5585 /******************** Bit definition for PWR_PUCRD register ********************/
|
|
|
5586 #define PWR_PUCRD_PD15 ((uint32_t)0x00008000U) /*!< Port PD15 Pull-Up set */
|
|
|
5587 #define PWR_PUCRD_PD14 ((uint32_t)0x00004000U) /*!< Port PD14 Pull-Up set */
|
|
|
5588 #define PWR_PUCRD_PD13 ((uint32_t)0x00002000U) /*!< Port PD13 Pull-Up set */
|
|
|
5589 #define PWR_PUCRD_PD12 ((uint32_t)0x00001000U) /*!< Port PD12 Pull-Up set */
|
|
|
5590 #define PWR_PUCRD_PD11 ((uint32_t)0x00000800U) /*!< Port PD11 Pull-Up set */
|
|
|
5591 #define PWR_PUCRD_PD10 ((uint32_t)0x00000400U) /*!< Port PD10 Pull-Up set */
|
|
|
5592 #define PWR_PUCRD_PD9 ((uint32_t)0x00000200U) /*!< Port PD9 Pull-Up set */
|
|
|
5593 #define PWR_PUCRD_PD8 ((uint32_t)0x00000100U) /*!< Port PD8 Pull-Up set */
|
|
|
5594 #define PWR_PUCRD_PD7 ((uint32_t)0x00000080U) /*!< Port PD7 Pull-Up set */
|
|
|
5595 #define PWR_PUCRD_PD6 ((uint32_t)0x00000040U) /*!< Port PD6 Pull-Up set */
|
|
|
5596 #define PWR_PUCRD_PD5 ((uint32_t)0x00000020U) /*!< Port PD5 Pull-Up set */
|
|
|
5597 #define PWR_PUCRD_PD4 ((uint32_t)0x00000010U) /*!< Port PD4 Pull-Up set */
|
|
|
5598 #define PWR_PUCRD_PD3 ((uint32_t)0x00000008U) /*!< Port PD3 Pull-Up set */
|
|
|
5599 #define PWR_PUCRD_PD2 ((uint32_t)0x00000004U) /*!< Port PD2 Pull-Up set */
|
|
|
5600 #define PWR_PUCRD_PD1 ((uint32_t)0x00000002U) /*!< Port PD1 Pull-Up set */
|
|
|
5601 #define PWR_PUCRD_PD0 ((uint32_t)0x00000001U) /*!< Port PD0 Pull-Up set */
|
|
|
5602
|
|
|
5603 /******************** Bit definition for PWR_PDCRD register ********************/
|
|
|
5604 #define PWR_PDCRD_PD15 ((uint32_t)0x00008000U) /*!< Port PD15 Pull-Down set */
|
|
|
5605 #define PWR_PDCRD_PD14 ((uint32_t)0x00004000U) /*!< Port PD14 Pull-Down set */
|
|
|
5606 #define PWR_PDCRD_PD13 ((uint32_t)0x00002000U) /*!< Port PD13 Pull-Down set */
|
|
|
5607 #define PWR_PDCRD_PD12 ((uint32_t)0x00001000U) /*!< Port PD12 Pull-Down set */
|
|
|
5608 #define PWR_PDCRD_PD11 ((uint32_t)0x00000800U) /*!< Port PD11 Pull-Down set */
|
|
|
5609 #define PWR_PDCRD_PD10 ((uint32_t)0x00000400U) /*!< Port PD10 Pull-Down set */
|
|
|
5610 #define PWR_PDCRD_PD9 ((uint32_t)0x00000200U) /*!< Port PD9 Pull-Down set */
|
|
|
5611 #define PWR_PDCRD_PD8 ((uint32_t)0x00000100U) /*!< Port PD8 Pull-Down set */
|
|
|
5612 #define PWR_PDCRD_PD7 ((uint32_t)0x00000080U) /*!< Port PD7 Pull-Down set */
|
|
|
5613 #define PWR_PDCRD_PD6 ((uint32_t)0x00000040U) /*!< Port PD6 Pull-Down set */
|
|
|
5614 #define PWR_PDCRD_PD5 ((uint32_t)0x00000020U) /*!< Port PD5 Pull-Down set */
|
|
|
5615 #define PWR_PDCRD_PD4 ((uint32_t)0x00000010U) /*!< Port PD4 Pull-Down set */
|
|
|
5616 #define PWR_PDCRD_PD3 ((uint32_t)0x00000008U) /*!< Port PD3 Pull-Down set */
|
|
|
5617 #define PWR_PDCRD_PD2 ((uint32_t)0x00000004U) /*!< Port PD2 Pull-Down set */
|
|
|
5618 #define PWR_PDCRD_PD1 ((uint32_t)0x00000002U) /*!< Port PD1 Pull-Down set */
|
|
|
5619 #define PWR_PDCRD_PD0 ((uint32_t)0x00000001U) /*!< Port PD0 Pull-Down set */
|
|
|
5620
|
|
|
5621 /******************** Bit definition for PWR_PUCRE register ********************/
|
|
|
5622 #define PWR_PUCRE_PE15 ((uint32_t)0x00008000U) /*!< Port PE15 Pull-Up set */
|
|
|
5623 #define PWR_PUCRE_PE14 ((uint32_t)0x00004000U) /*!< Port PE14 Pull-Up set */
|
|
|
5624 #define PWR_PUCRE_PE13 ((uint32_t)0x00002000U) /*!< Port PE13 Pull-Up set */
|
|
|
5625 #define PWR_PUCRE_PE12 ((uint32_t)0x00001000U) /*!< Port PE12 Pull-Up set */
|
|
|
5626 #define PWR_PUCRE_PE11 ((uint32_t)0x00000800U) /*!< Port PE11 Pull-Up set */
|
|
|
5627 #define PWR_PUCRE_PE10 ((uint32_t)0x00000400U) /*!< Port PE10 Pull-Up set */
|
|
|
5628 #define PWR_PUCRE_PE9 ((uint32_t)0x00000200U) /*!< Port PE9 Pull-Up set */
|
|
|
5629 #define PWR_PUCRE_PE8 ((uint32_t)0x00000100U) /*!< Port PE8 Pull-Up set */
|
|
|
5630 #define PWR_PUCRE_PE7 ((uint32_t)0x00000080U) /*!< Port PE7 Pull-Up set */
|
|
|
5631 #define PWR_PUCRE_PE6 ((uint32_t)0x00000040U) /*!< Port PE6 Pull-Up set */
|
|
|
5632 #define PWR_PUCRE_PE5 ((uint32_t)0x00000020U) /*!< Port PE5 Pull-Up set */
|
|
|
5633 #define PWR_PUCRE_PE4 ((uint32_t)0x00000010U) /*!< Port PE4 Pull-Up set */
|
|
|
5634 #define PWR_PUCRE_PE3 ((uint32_t)0x00000008U) /*!< Port PE3 Pull-Up set */
|
|
|
5635 #define PWR_PUCRE_PE2 ((uint32_t)0x00000004U) /*!< Port PE2 Pull-Up set */
|
|
|
5636 #define PWR_PUCRE_PE1 ((uint32_t)0x00000002U) /*!< Port PE1 Pull-Up set */
|
|
|
5637 #define PWR_PUCRE_PE0 ((uint32_t)0x00000001U) /*!< Port PE0 Pull-Up set */
|
|
|
5638
|
|
|
5639 /******************** Bit definition for PWR_PDCRE register ********************/
|
|
|
5640 #define PWR_PDCRE_PE15 ((uint32_t)0x00008000U) /*!< Port PE15 Pull-Down set */
|
|
|
5641 #define PWR_PDCRE_PE14 ((uint32_t)0x00004000U) /*!< Port PE14 Pull-Down set */
|
|
|
5642 #define PWR_PDCRE_PE13 ((uint32_t)0x00002000U) /*!< Port PE13 Pull-Down set */
|
|
|
5643 #define PWR_PDCRE_PE12 ((uint32_t)0x00001000U) /*!< Port PE12 Pull-Down set */
|
|
|
5644 #define PWR_PDCRE_PE11 ((uint32_t)0x00000800U) /*!< Port PE11 Pull-Down set */
|
|
|
5645 #define PWR_PDCRE_PE10 ((uint32_t)0x00000400U) /*!< Port PE10 Pull-Down set */
|
|
|
5646 #define PWR_PDCRE_PE9 ((uint32_t)0x00000200U) /*!< Port PE9 Pull-Down set */
|
|
|
5647 #define PWR_PDCRE_PE8 ((uint32_t)0x00000100U) /*!< Port PE8 Pull-Down set */
|
|
|
5648 #define PWR_PDCRE_PE7 ((uint32_t)0x00000080U) /*!< Port PE7 Pull-Down set */
|
|
|
5649 #define PWR_PDCRE_PE6 ((uint32_t)0x00000040U) /*!< Port PE6 Pull-Down set */
|
|
|
5650 #define PWR_PDCRE_PE5 ((uint32_t)0x00000020U) /*!< Port PE5 Pull-Down set */
|
|
|
5651 #define PWR_PDCRE_PE4 ((uint32_t)0x00000010U) /*!< Port PE4 Pull-Down set */
|
|
|
5652 #define PWR_PDCRE_PE3 ((uint32_t)0x00000008U) /*!< Port PE3 Pull-Down set */
|
|
|
5653 #define PWR_PDCRE_PE2 ((uint32_t)0x00000004U) /*!< Port PE2 Pull-Down set */
|
|
|
5654 #define PWR_PDCRE_PE1 ((uint32_t)0x00000002U) /*!< Port PE1 Pull-Down set */
|
|
|
5655 #define PWR_PDCRE_PE0 ((uint32_t)0x00000001U) /*!< Port PE0 Pull-Down set */
|
|
|
5656
|
|
|
5657 /******************** Bit definition for PWR_PUCRF register ********************/
|
|
|
5658 #define PWR_PUCRF_PF15 ((uint32_t)0x00008000U) /*!< Port PF15 Pull-Up set */
|
|
|
5659 #define PWR_PUCRF_PF14 ((uint32_t)0x00004000U) /*!< Port PF14 Pull-Up set */
|
|
|
5660 #define PWR_PUCRF_PF13 ((uint32_t)0x00002000U) /*!< Port PF13 Pull-Up set */
|
|
|
5661 #define PWR_PUCRF_PF12 ((uint32_t)0x00001000U) /*!< Port PF12 Pull-Up set */
|
|
|
5662 #define PWR_PUCRF_PF11 ((uint32_t)0x00000800U) /*!< Port PF11 Pull-Up set */
|
|
|
5663 #define PWR_PUCRF_PF10 ((uint32_t)0x00000400U) /*!< Port PF10 Pull-Up set */
|
|
|
5664 #define PWR_PUCRF_PF9 ((uint32_t)0x00000200U) /*!< Port PF9 Pull-Up set */
|
|
|
5665 #define PWR_PUCRF_PF8 ((uint32_t)0x00000100U) /*!< Port PF8 Pull-Up set */
|
|
|
5666 #define PWR_PUCRF_PF7 ((uint32_t)0x00000080U) /*!< Port PF7 Pull-Up set */
|
|
|
5667 #define PWR_PUCRF_PF6 ((uint32_t)0x00000040U) /*!< Port PF6 Pull-Up set */
|
|
|
5668 #define PWR_PUCRF_PF5 ((uint32_t)0x00000020U) /*!< Port PF5 Pull-Up set */
|
|
|
5669 #define PWR_PUCRF_PF4 ((uint32_t)0x00000010U) /*!< Port PF4 Pull-Up set */
|
|
|
5670 #define PWR_PUCRF_PF3 ((uint32_t)0x00000008U) /*!< Port PF3 Pull-Up set */
|
|
|
5671 #define PWR_PUCRF_PF2 ((uint32_t)0x00000004U) /*!< Port PF2 Pull-Up set */
|
|
|
5672 #define PWR_PUCRF_PF1 ((uint32_t)0x00000002U) /*!< Port PF1 Pull-Up set */
|
|
|
5673 #define PWR_PUCRF_PF0 ((uint32_t)0x00000001U) /*!< Port PF0 Pull-Up set */
|
|
|
5674
|
|
|
5675 /******************** Bit definition for PWR_PDCRF register ********************/
|
|
|
5676 #define PWR_PDCRF_PF15 ((uint32_t)0x00008000U) /*!< Port PF15 Pull-Down set */
|
|
|
5677 #define PWR_PDCRF_PF14 ((uint32_t)0x00004000U) /*!< Port PF14 Pull-Down set */
|
|
|
5678 #define PWR_PDCRF_PF13 ((uint32_t)0x00002000U) /*!< Port PF13 Pull-Down set */
|
|
|
5679 #define PWR_PDCRF_PF12 ((uint32_t)0x00001000U) /*!< Port PF12 Pull-Down set */
|
|
|
5680 #define PWR_PDCRF_PF11 ((uint32_t)0x00000800U) /*!< Port PF11 Pull-Down set */
|
|
|
5681 #define PWR_PDCRF_PF10 ((uint32_t)0x00000400U) /*!< Port PF10 Pull-Down set */
|
|
|
5682 #define PWR_PDCRF_PF9 ((uint32_t)0x00000200U) /*!< Port PF9 Pull-Down set */
|
|
|
5683 #define PWR_PDCRF_PF8 ((uint32_t)0x00000100U) /*!< Port PF8 Pull-Down set */
|
|
|
5684 #define PWR_PDCRF_PF7 ((uint32_t)0x00000080U) /*!< Port PF7 Pull-Down set */
|
|
|
5685 #define PWR_PDCRF_PF6 ((uint32_t)0x00000040U) /*!< Port PF6 Pull-Down set */
|
|
|
5686 #define PWR_PDCRF_PF5 ((uint32_t)0x00000020U) /*!< Port PF5 Pull-Down set */
|
|
|
5687 #define PWR_PDCRF_PF4 ((uint32_t)0x00000010U) /*!< Port PF4 Pull-Down set */
|
|
|
5688 #define PWR_PDCRF_PF3 ((uint32_t)0x00000008U) /*!< Port PF3 Pull-Down set */
|
|
|
5689 #define PWR_PDCRF_PF2 ((uint32_t)0x00000004U) /*!< Port PF2 Pull-Down set */
|
|
|
5690 #define PWR_PDCRF_PF1 ((uint32_t)0x00000002U) /*!< Port PF1 Pull-Down set */
|
|
|
5691 #define PWR_PDCRF_PF0 ((uint32_t)0x00000001U) /*!< Port PF0 Pull-Down set */
|
|
|
5692
|
|
|
5693 /******************** Bit definition for PWR_PUCRG register ********************/
|
|
|
5694 #define PWR_PUCRG_PG15 ((uint32_t)0x00008000U) /*!< Port PG15 Pull-Up set */
|
|
|
5695 #define PWR_PUCRG_PG14 ((uint32_t)0x00004000U) /*!< Port PG14 Pull-Up set */
|
|
|
5696 #define PWR_PUCRG_PG13 ((uint32_t)0x00002000U) /*!< Port PG13 Pull-Up set */
|
|
|
5697 #define PWR_PUCRG_PG12 ((uint32_t)0x00001000U) /*!< Port PG12 Pull-Up set */
|
|
|
5698 #define PWR_PUCRG_PG11 ((uint32_t)0x00000800U) /*!< Port PG11 Pull-Up set */
|
|
|
5699 #define PWR_PUCRG_PG10 ((uint32_t)0x00000400U) /*!< Port PG10 Pull-Up set */
|
|
|
5700 #define PWR_PUCRG_PG9 ((uint32_t)0x00000200U) /*!< Port PG9 Pull-Up set */
|
|
|
5701 #define PWR_PUCRG_PG8 ((uint32_t)0x00000100U) /*!< Port PG8 Pull-Up set */
|
|
|
5702 #define PWR_PUCRG_PG7 ((uint32_t)0x00000080U) /*!< Port PG7 Pull-Up set */
|
|
|
5703 #define PWR_PUCRG_PG6 ((uint32_t)0x00000040U) /*!< Port PG6 Pull-Up set */
|
|
|
5704 #define PWR_PUCRG_PG5 ((uint32_t)0x00000020U) /*!< Port PG5 Pull-Up set */
|
|
|
5705 #define PWR_PUCRG_PG4 ((uint32_t)0x00000010U) /*!< Port PG4 Pull-Up set */
|
|
|
5706 #define PWR_PUCRG_PG3 ((uint32_t)0x00000008U) /*!< Port PG3 Pull-Up set */
|
|
|
5707 #define PWR_PUCRG_PG2 ((uint32_t)0x00000004U) /*!< Port PG2 Pull-Up set */
|
|
|
5708 #define PWR_PUCRG_PG1 ((uint32_t)0x00000002U) /*!< Port PG1 Pull-Up set */
|
|
|
5709 #define PWR_PUCRG_PG0 ((uint32_t)0x00000001U) /*!< Port PG0 Pull-Up set */
|
|
|
5710
|
|
|
5711 /******************** Bit definition for PWR_PDCRG register ********************/
|
|
|
5712 #define PWR_PDCRG_PG15 ((uint32_t)0x00008000U) /*!< Port PG15 Pull-Down set */
|
|
|
5713 #define PWR_PDCRG_PG14 ((uint32_t)0x00004000U) /*!< Port PG14 Pull-Down set */
|
|
|
5714 #define PWR_PDCRG_PG13 ((uint32_t)0x00002000U) /*!< Port PG13 Pull-Down set */
|
|
|
5715 #define PWR_PDCRG_PG12 ((uint32_t)0x00001000U) /*!< Port PG12 Pull-Down set */
|
|
|
5716 #define PWR_PDCRG_PG11 ((uint32_t)0x00000800U) /*!< Port PG11 Pull-Down set */
|
|
|
5717 #define PWR_PDCRG_PG10 ((uint32_t)0x00000400U) /*!< Port PG10 Pull-Down set */
|
|
|
5718 #define PWR_PDCRG_PG9 ((uint32_t)0x00000200U) /*!< Port PG9 Pull-Down set */
|
|
|
5719 #define PWR_PDCRG_PG8 ((uint32_t)0x00000100U) /*!< Port PG8 Pull-Down set */
|
|
|
5720 #define PWR_PDCRG_PG7 ((uint32_t)0x00000080U) /*!< Port PG7 Pull-Down set */
|
|
|
5721 #define PWR_PDCRG_PG6 ((uint32_t)0x00000040U) /*!< Port PG6 Pull-Down set */
|
|
|
5722 #define PWR_PDCRG_PG5 ((uint32_t)0x00000020U) /*!< Port PG5 Pull-Down set */
|
|
|
5723 #define PWR_PDCRG_PG4 ((uint32_t)0x00000010U) /*!< Port PG4 Pull-Down set */
|
|
|
5724 #define PWR_PDCRG_PG3 ((uint32_t)0x00000008U) /*!< Port PG3 Pull-Down set */
|
|
|
5725 #define PWR_PDCRG_PG2 ((uint32_t)0x00000004U) /*!< Port PG2 Pull-Down set */
|
|
|
5726 #define PWR_PDCRG_PG1 ((uint32_t)0x00000002U) /*!< Port PG1 Pull-Down set */
|
|
|
5727 #define PWR_PDCRG_PG0 ((uint32_t)0x00000001U) /*!< Port PG0 Pull-Down set */
|
|
|
5728
|
|
|
5729 /******************** Bit definition for PWR_PUCRH register ********************/
|
|
|
5730 #define PWR_PUCRH_PH1 ((uint32_t)0x00000002U) /*!< Port PH1 Pull-Up set */
|
|
|
5731 #define PWR_PUCRH_PH0 ((uint32_t)0x00000001U) /*!< Port PH0 Pull-Up set */
|
|
|
5732
|
|
|
5733 /******************** Bit definition for PWR_PDCRH register ********************/
|
|
|
5734 #define PWR_PDCRH_PH1 ((uint32_t)0x00000002U) /*!< Port PH1 Pull-Down set */
|
|
|
5735 #define PWR_PDCRH_PH0 ((uint32_t)0x00000001U) /*!< Port PH0 Pull-Down set */
|
|
|
5736
|
|
|
5737
|
|
|
5738 /******************************************************************************/
|
|
|
5739 /* */
|
|
|
5740 /* Reset and Clock Control */
|
|
|
5741 /* */
|
|
|
5742 /******************************************************************************/
|
|
|
5743 /*
|
|
|
5744 * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
|
|
|
5745 */
|
|
|
5746 #define RCC_PLLSAI2_SUPPORT
|
|
|
5747
|
|
|
5748 /******************** Bit definition for RCC_CR register ********************/
|
|
|
5749 #define RCC_CR_MSION ((uint32_t)0x00000001U) /*!< Internal Multi Speed oscillator (MSI) clock enable */
|
|
|
5750 #define RCC_CR_MSIRDY ((uint32_t)0x00000002U) /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
|
|
|
5751 #define RCC_CR_MSIPLLEN ((uint32_t)0x00000004U) /*!< Internal Multi Speed oscillator (MSI) PLL enable */
|
|
|
5752 #define RCC_CR_MSIRGSEL ((uint32_t)0x00000008U) /*!< Internal Multi Speed oscillator (MSI) range selection */
|
|
|
5753
|
|
|
5754 /*!< MSIRANGE configuration : 12 frequency ranges available */
|
|
|
5755 #define RCC_CR_MSIRANGE ((uint32_t)0x000000F0U) /*!< Internal Multi Speed oscillator (MSI) clock Range */
|
|
|
5756 #define RCC_CR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed oscillator (MSI) clock Range 100 KHz */
|
|
|
5757 #define RCC_CR_MSIRANGE_1 ((uint32_t)0x00000010U) /*!< Internal Multi Speed oscillator (MSI) clock Range 200 KHz */
|
|
|
5758 #define RCC_CR_MSIRANGE_2 ((uint32_t)0x00000020U) /*!< Internal Multi Speed oscillator (MSI) clock Range 400 KHz */
|
|
|
5759 #define RCC_CR_MSIRANGE_3 ((uint32_t)0x00000030U) /*!< Internal Multi Speed oscillator (MSI) clock Range 800 KHz */
|
|
|
5760 #define RCC_CR_MSIRANGE_4 ((uint32_t)0x00000040U) /*!< Internal Multi Speed oscillator (MSI) clock Range 1 MHz */
|
|
|
5761 #define RCC_CR_MSIRANGE_5 ((uint32_t)0x00000050U) /*!< Internal Multi Speed oscillator (MSI) clock Range 2 MHz */
|
|
|
5762 #define RCC_CR_MSIRANGE_6 ((uint32_t)0x00000060U) /*!< Internal Multi Speed oscillator (MSI) clock Range 4 MHz */
|
|
|
5763 #define RCC_CR_MSIRANGE_7 ((uint32_t)0x00000070U) /*!< Internal Multi Speed oscillator (MSI) clock Range 8 KHz */
|
|
|
5764 #define RCC_CR_MSIRANGE_8 ((uint32_t)0x00000080U) /*!< Internal Multi Speed oscillator (MSI) clock Range 16 MHz */
|
|
|
5765 #define RCC_CR_MSIRANGE_9 ((uint32_t)0x00000090U) /*!< Internal Multi Speed oscillator (MSI) clock Range 24 MHz */
|
|
|
5766 #define RCC_CR_MSIRANGE_10 ((uint32_t)0x000000A0U) /*!< Internal Multi Speed oscillator (MSI) clock Range 32 MHz */
|
|
|
5767 #define RCC_CR_MSIRANGE_11 ((uint32_t)0x000000B0U) /*!< Internal Multi Speed oscillator (MSI) clock Range 48 MHz */
|
|
|
5768
|
|
|
5769 #define RCC_CR_HSION ((uint32_t)0x00000100U) /*!< Internal High Speed oscillator (HSI16) clock enable */
|
|
|
5770 #define RCC_CR_HSIKERON ((uint32_t)0x00000200U) /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
|
|
|
5771 #define RCC_CR_HSIRDY ((uint32_t)0x00000400U) /*!< Internal High Speed oscillator (HSI16) clock ready flag */
|
|
|
5772 #define RCC_CR_HSIASFS ((uint32_t)0x00000800U) /*!< HSI16 Automatic Start from Stop */
|
|
|
5773
|
|
|
5774 #define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed oscillator (HSE) clock enable */
|
|
|
5775 #define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed oscillator (HSE) clock ready */
|
|
|
5776 #define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed oscillator (HSE) clock bypass */
|
|
|
5777 #define RCC_CR_CSSON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */
|
|
|
5778
|
|
|
5779 #define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< System PLL clock enable */
|
|
|
5780 #define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< System PLL clock ready */
|
|
|
5781 #define RCC_CR_PLLSAI1ON ((uint32_t)0x04000000U) /*!< SAI1 PLL enable */
|
|
|
5782 #define RCC_CR_PLLSAI1RDY ((uint32_t)0x08000000U) /*!< SAI1 PLL ready */
|
|
|
5783 #define RCC_CR_PLLSAI2ON ((uint32_t)0x10000000U) /*!< SAI2 PLL enable */
|
|
|
5784 #define RCC_CR_PLLSAI2RDY ((uint32_t)0x20000000U) /*!< SAI2 PLL ready */
|
|
|
5785
|
|
|
5786 /******************** Bit definition for RCC_ICSCR register ***************/
|
|
|
5787 /*!< MSICAL configuration */
|
|
|
5788 #define RCC_ICSCR_MSICAL ((uint32_t)0x000000FFU) /*!< MSICAL[7:0] bits */
|
|
|
5789 #define RCC_ICSCR_MSICAL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
5790 #define RCC_ICSCR_MSICAL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
5791 #define RCC_ICSCR_MSICAL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
5792 #define RCC_ICSCR_MSICAL_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
5793 #define RCC_ICSCR_MSICAL_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
5794 #define RCC_ICSCR_MSICAL_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
5795 #define RCC_ICSCR_MSICAL_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
5796 #define RCC_ICSCR_MSICAL_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
|
|
|
5797
|
|
|
5798 /*!< MSITRIM configuration */
|
|
|
5799 #define RCC_ICSCR_MSITRIM ((uint32_t)0x0000FF00U) /*!< MSITRIM[7:0] bits */
|
|
|
5800 #define RCC_ICSCR_MSITRIM_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
5801 #define RCC_ICSCR_MSITRIM_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
5802 #define RCC_ICSCR_MSITRIM_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
5803 #define RCC_ICSCR_MSITRIM_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
5804 #define RCC_ICSCR_MSITRIM_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
5805 #define RCC_ICSCR_MSITRIM_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
|
|
|
5806 #define RCC_ICSCR_MSITRIM_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
|
|
|
5807 #define RCC_ICSCR_MSITRIM_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
|
|
|
5808
|
|
|
5809 /*!< HSICAL configuration */
|
|
|
5810 #define RCC_ICSCR_HSICAL ((uint32_t)0x00FF0000U) /*!< HSICAL[7:0] bits */
|
|
|
5811 #define RCC_ICSCR_HSICAL_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
5812 #define RCC_ICSCR_HSICAL_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
5813 #define RCC_ICSCR_HSICAL_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
5814 #define RCC_ICSCR_HSICAL_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
|
|
|
5815 #define RCC_ICSCR_HSICAL_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
|
|
|
5816 #define RCC_ICSCR_HSICAL_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
|
|
|
5817 #define RCC_ICSCR_HSICAL_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
|
|
|
5818 #define RCC_ICSCR_HSICAL_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
|
|
|
5819
|
|
|
5820 /*!< HSITRIM configuration */
|
|
|
5821 #define RCC_ICSCR_HSITRIM ((uint32_t)0x1F000000U) /*!< HSITRIM[4:0] bits */
|
|
|
5822 #define RCC_ICSCR_HSITRIM_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
5823 #define RCC_ICSCR_HSITRIM_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
5824 #define RCC_ICSCR_HSITRIM_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
5825 #define RCC_ICSCR_HSITRIM_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
5826 #define RCC_ICSCR_HSITRIM_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
|
|
|
5827
|
|
|
5828 /******************** Bit definition for RCC_CFGR register ******************/
|
|
|
5829 /*!< SW configuration */
|
|
|
5830 #define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
|
|
|
5831 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
5832 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
5833
|
|
|
5834 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator selection as system clock */
|
|
|
5835 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI16 oscillator selection as system clock */
|
|
|
5836 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE oscillator selection as system clock */
|
|
|
5837 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selection as system clock */
|
|
|
5838
|
|
|
5839 /*!< SWS configuration */
|
|
|
5840 #define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
|
|
|
5841 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
5842 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
5843
|
|
|
5844 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
|
|
|
5845 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI16 oscillator used as system clock */
|
|
|
5846 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
|
|
|
5847 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
|
|
|
5848
|
|
|
5849 /*!< HPRE configuration */
|
|
|
5850 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
|
|
|
5851 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
5852 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
5853 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
5854 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
|
|
|
5855
|
|
|
5856 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
|
|
|
5857 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
|
|
|
5858 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
|
|
|
5859 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
|
|
|
5860 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
|
|
|
5861 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
|
|
|
5862 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
|
|
|
5863 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
|
|
|
5864 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
|
|
|
5865
|
|
|
5866 /*!< PPRE1 configuration */
|
|
|
5867 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB2 prescaler) */
|
|
|
5868 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
5869 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
5870 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
5871
|
|
|
5872 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
|
|
|
5873 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
|
|
|
5874 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
|
|
|
5875 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
|
|
|
5876 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
|
|
|
5877
|
|
|
5878 /*!< PPRE2 configuration */
|
|
|
5879 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
|
|
|
5880 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!<Bit 0 */
|
|
|
5881 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!<Bit 1 */
|
|
|
5882 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!<Bit 2 */
|
|
|
5883
|
|
|
5884 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
|
|
|
5885 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
|
|
|
5886 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
|
|
|
5887 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
|
|
|
5888 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
|
|
|
5889
|
|
|
5890 #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from stop and CSS backup clock selection */
|
|
|
5891
|
|
|
5892 /*!< MCOSEL configuration */
|
|
|
5893 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000U) /*!< MCOSEL [2:0] bits (Clock output selection) */
|
|
|
5894 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
5895 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
5896 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
5897
|
|
|
5898 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */
|
|
|
5899 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
|
|
|
5900 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
|
|
|
5901 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
|
|
|
5902
|
|
|
5903 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
|
|
|
5904 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
|
|
|
5905 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
|
|
|
5906 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
|
|
|
5907 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
|
|
|
5908
|
|
|
5909 /* Legacy aliases */
|
|
|
5910 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
|
|
|
5911 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
|
|
|
5912 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
|
|
|
5913 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
|
|
|
5914 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
|
|
|
5915 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
|
|
|
5916
|
|
|
5917 /******************** Bit definition for RCC_PLLCFGR register ***************/
|
|
|
5918 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00000003U)
|
|
|
5919
|
|
|
5920 #define RCC_PLLCFGR_PLLSRC_MSI ((uint32_t)0x00000001U) /*!< MSI oscillator source clock selected */
|
|
|
5921 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000002U) /*!< HSI16 oscillator source clock selected */
|
|
|
5922 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00000003U) /*!< HSE oscillator source clock selected */
|
|
|
5923
|
|
|
5924 #define RCC_PLLCFGR_PLLM ((uint32_t)0x00000070U)
|
|
|
5925 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000010U)
|
|
|
5926 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000020U)
|
|
|
5927 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000040U)
|
|
|
5928
|
|
|
5929 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007F00U)
|
|
|
5930 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000100U)
|
|
|
5931 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000200U)
|
|
|
5932 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000400U)
|
|
|
5933 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000800U)
|
|
|
5934 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00001000U)
|
|
|
5935 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00002000U)
|
|
|
5936 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00004000U)
|
|
|
5937
|
|
|
5938 #define RCC_PLLCFGR_PLLPEN ((uint32_t)0x00010000U)
|
|
|
5939 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00020000U)
|
|
|
5940 #define RCC_PLLCFGR_PLLQEN ((uint32_t)0x00100000U)
|
|
|
5941
|
|
|
5942 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x00600000U)
|
|
|
5943 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x00200000U)
|
|
|
5944 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x00400000U)
|
|
|
5945
|
|
|
5946 #define RCC_PLLCFGR_PLLREN ((uint32_t)0x01000000U)
|
|
|
5947 #define RCC_PLLCFGR_PLLR ((uint32_t)0x06000000U)
|
|
|
5948 #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x02000000U)
|
|
|
5949 #define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x04000000U)
|
|
|
5950
|
|
|
5951 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
|
|
|
5952 #define RCC_PLLSAI1CFGR_PLLSAI1N ((uint32_t)0x00007F00U)
|
|
|
5953 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 ((uint32_t)0x00000100U)
|
|
|
5954 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 ((uint32_t)0x00000200U)
|
|
|
5955 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 ((uint32_t)0x00000400U)
|
|
|
5956 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 ((uint32_t)0x00000800U)
|
|
|
5957 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 ((uint32_t)0x00001000U)
|
|
|
5958 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 ((uint32_t)0x00002000U)
|
|
|
5959 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 ((uint32_t)0x00004000U)
|
|
|
5960
|
|
|
5961 #define RCC_PLLSAI1CFGR_PLLSAI1PEN ((uint32_t)0x00010000U)
|
|
|
5962 #define RCC_PLLSAI1CFGR_PLLSAI1P ((uint32_t)0x00020000U)
|
|
|
5963
|
|
|
5964 #define RCC_PLLSAI1CFGR_PLLSAI1QEN ((uint32_t)0x00100000U)
|
|
|
5965 #define RCC_PLLSAI1CFGR_PLLSAI1Q ((uint32_t)0x00600000U)
|
|
|
5966 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 ((uint32_t)0x00200000U)
|
|
|
5967 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 ((uint32_t)0x00400000U)
|
|
|
5968
|
|
|
5969 #define RCC_PLLSAI1CFGR_PLLSAI1REN ((uint32_t)0x01000000U)
|
|
|
5970 #define RCC_PLLSAI1CFGR_PLLSAI1R ((uint32_t)0x06000000U)
|
|
|
5971 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 ((uint32_t)0x02000000U)
|
|
|
5972 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 ((uint32_t)0x04000000U)
|
|
|
5973
|
|
|
5974 /******************** Bit definition for RCC_PLLSAI2CFGR register ************/
|
|
|
5975 #define RCC_PLLSAI2CFGR_PLLSAI2N ((uint32_t)0x00007F00U)
|
|
|
5976 #define RCC_PLLSAI2CFGR_PLLSAI2N_0 ((uint32_t)0x00000100U)
|
|
|
5977 #define RCC_PLLSAI2CFGR_PLLSAI2N_1 ((uint32_t)0x00000200U)
|
|
|
5978 #define RCC_PLLSAI2CFGR_PLLSAI2N_2 ((uint32_t)0x00000400U)
|
|
|
5979 #define RCC_PLLSAI2CFGR_PLLSAI2N_3 ((uint32_t)0x00000800U)
|
|
|
5980 #define RCC_PLLSAI2CFGR_PLLSAI2N_4 ((uint32_t)0x00001000U)
|
|
|
5981 #define RCC_PLLSAI2CFGR_PLLSAI2N_5 ((uint32_t)0x00002000U)
|
|
|
5982 #define RCC_PLLSAI2CFGR_PLLSAI2N_6 ((uint32_t)0x00004000U)
|
|
|
5983
|
|
|
5984 #define RCC_PLLSAI2CFGR_PLLSAI2PEN ((uint32_t)0x00010000U)
|
|
|
5985 #define RCC_PLLSAI2CFGR_PLLSAI2P ((uint32_t)0x00020000U)
|
|
|
5986
|
|
|
5987 #define RCC_PLLSAI2CFGR_PLLSAI2REN ((uint32_t)0x01000000U)
|
|
|
5988 #define RCC_PLLSAI2CFGR_PLLSAI2R ((uint32_t)0x06000000U)
|
|
|
5989 #define RCC_PLLSAI2CFGR_PLLSAI2R_0 ((uint32_t)0x02000000U)
|
|
|
5990 #define RCC_PLLSAI2CFGR_PLLSAI2R_1 ((uint32_t)0x04000000U)
|
|
|
5991
|
|
|
5992 /******************** Bit definition for RCC_CIER register ******************/
|
|
|
5993 #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U)
|
|
|
5994 #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U)
|
|
|
5995 #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000004U)
|
|
|
5996 #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000008U)
|
|
|
5997 #define RCC_CIER_HSERDYIE ((uint32_t)0x00000010U)
|
|
|
5998 #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000020U)
|
|
|
5999 #define RCC_CIER_PLLSAI1RDYIE ((uint32_t)0x00000040U)
|
|
|
6000 #define RCC_CIER_PLLSAI2RDYIE ((uint32_t)0x00000080U)
|
|
|
6001 #define RCC_CIER_LSECSSIE ((uint32_t)0x00000200U)
|
|
|
6002
|
|
|
6003 /******************** Bit definition for RCC_CIFR register ******************/
|
|
|
6004 #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U)
|
|
|
6005 #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U)
|
|
|
6006 #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000004U)
|
|
|
6007 #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000008U)
|
|
|
6008 #define RCC_CIFR_HSERDYF ((uint32_t)0x00000010U)
|
|
|
6009 #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000020U)
|
|
|
6010 #define RCC_CIFR_PLLSAI1RDYF ((uint32_t)0x00000040U)
|
|
|
6011 #define RCC_CIFR_PLLSAI2RDYF ((uint32_t)0x00000080U)
|
|
|
6012 #define RCC_CIFR_CSSF ((uint32_t)0x00000100U)
|
|
|
6013 #define RCC_CIFR_LSECSSF ((uint32_t)0x00000200U)
|
|
|
6014
|
|
|
6015 /******************** Bit definition for RCC_CICR register ******************/
|
|
|
6016 #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U)
|
|
|
6017 #define RCC_CICR_LSERDYC ((uint32_t)0x00000002U)
|
|
|
6018 #define RCC_CICR_MSIRDYC ((uint32_t)0x00000004U)
|
|
|
6019 #define RCC_CICR_HSIRDYC ((uint32_t)0x00000008U)
|
|
|
6020 #define RCC_CICR_HSERDYC ((uint32_t)0x00000010U)
|
|
|
6021 #define RCC_CICR_PLLRDYC ((uint32_t)0x00000020U)
|
|
|
6022 #define RCC_CICR_PLLSAI1RDYC ((uint32_t)0x00000040U)
|
|
|
6023 #define RCC_CICR_PLLSAI2RDYC ((uint32_t)0x00000080U)
|
|
|
6024 #define RCC_CICR_CSSC ((uint32_t)0x00000100U)
|
|
|
6025 #define RCC_CICR_LSECSSC ((uint32_t)0x00000200U)
|
|
|
6026
|
|
|
6027 /******************** Bit definition for RCC_AHB1RSTR register **************/
|
|
|
6028 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00000001U)
|
|
|
6029 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00000002U)
|
|
|
6030 #define RCC_AHB1RSTR_FLASHRST ((uint32_t)0x00000100U)
|
|
|
6031 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000U)
|
|
|
6032 #define RCC_AHB1RSTR_TSCRST ((uint32_t)0x00010000U)
|
|
|
6033
|
|
|
6034 /******************** Bit definition for RCC_AHB2RSTR register **************/
|
|
|
6035 #define RCC_AHB2RSTR_GPIOARST ((uint32_t)0x00000001U)
|
|
|
6036 #define RCC_AHB2RSTR_GPIOBRST ((uint32_t)0x00000002U)
|
|
|
6037 #define RCC_AHB2RSTR_GPIOCRST ((uint32_t)0x00000004U)
|
|
|
6038 #define RCC_AHB2RSTR_GPIODRST ((uint32_t)0x00000008U)
|
|
|
6039 #define RCC_AHB2RSTR_GPIOERST ((uint32_t)0x00000010U)
|
|
|
6040 #define RCC_AHB2RSTR_GPIOFRST ((uint32_t)0x00000020U)
|
|
|
6041 #define RCC_AHB2RSTR_GPIOGRST ((uint32_t)0x00000040U)
|
|
|
6042 #define RCC_AHB2RSTR_GPIOHRST ((uint32_t)0x00000080U)
|
|
|
6043 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00001000U)
|
|
|
6044 #define RCC_AHB2RSTR_ADCRST ((uint32_t)0x00002000U)
|
|
|
6045 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00040000U)
|
|
|
6046
|
|
|
6047 /******************** Bit definition for RCC_AHB3RSTR register **************/
|
|
|
6048 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001U)
|
|
|
6049 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000100U)
|
|
|
6050
|
|
|
6051 /******************** Bit definition for RCC_APB1RSTR1 register **************/
|
|
|
6052 #define RCC_APB1RSTR1_TIM2RST ((uint32_t)0x00000001U)
|
|
|
6053 #define RCC_APB1RSTR1_TIM3RST ((uint32_t)0x00000002U)
|
|
|
6054 #define RCC_APB1RSTR1_TIM4RST ((uint32_t)0x00000004U)
|
|
|
6055 #define RCC_APB1RSTR1_TIM5RST ((uint32_t)0x00000008U)
|
|
|
6056 #define RCC_APB1RSTR1_TIM6RST ((uint32_t)0x00000010U)
|
|
|
6057 #define RCC_APB1RSTR1_TIM7RST ((uint32_t)0x00000020U)
|
|
|
6058 #define RCC_APB1RSTR1_LCDRST ((uint32_t)0x00000200U)
|
|
|
6059 #define RCC_APB1RSTR1_SPI2RST ((uint32_t)0x00004000U)
|
|
|
6060 #define RCC_APB1RSTR1_SPI3RST ((uint32_t)0x00008000U)
|
|
|
6061 #define RCC_APB1RSTR1_USART2RST ((uint32_t)0x00020000U)
|
|
|
6062 #define RCC_APB1RSTR1_USART3RST ((uint32_t)0x00040000U)
|
|
|
6063 #define RCC_APB1RSTR1_UART4RST ((uint32_t)0x00080000U)
|
|
|
6064 #define RCC_APB1RSTR1_UART5RST ((uint32_t)0x00100000U)
|
|
|
6065 #define RCC_APB1RSTR1_I2C1RST ((uint32_t)0x00200000U)
|
|
|
6066 #define RCC_APB1RSTR1_I2C2RST ((uint32_t)0x00400000U)
|
|
|
6067 #define RCC_APB1RSTR1_I2C3RST ((uint32_t)0x00800000U)
|
|
|
6068 #define RCC_APB1RSTR1_CAN1RST ((uint32_t)0x02000000U)
|
|
|
6069 #define RCC_APB1RSTR1_PWRRST ((uint32_t)0x10000000U)
|
|
|
6070 #define RCC_APB1RSTR1_DAC1RST ((uint32_t)0x20000000U)
|
|
|
6071 #define RCC_APB1RSTR1_OPAMPRST ((uint32_t)0x40000000U)
|
|
|
6072 #define RCC_APB1RSTR1_LPTIM1RST ((uint32_t)0x80000000U)
|
|
|
6073
|
|
|
6074 /******************** Bit definition for RCC_APB1RSTR2 register **************/
|
|
|
6075 #define RCC_APB1RSTR2_LPUART1RST ((uint32_t)0x00000001U)
|
|
|
6076 #define RCC_APB1RSTR2_SWPMI1RST ((uint32_t)0x00000004U)
|
|
|
6077 #define RCC_APB1RSTR2_LPTIM2RST ((uint32_t)0x00000020U)
|
|
|
6078
|
|
|
6079 /******************** Bit definition for RCC_APB2RSTR register **************/
|
|
|
6080 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U)
|
|
|
6081 #define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000400U)
|
|
|
6082 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800U)
|
|
|
6083 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U)
|
|
|
6084 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000U)
|
|
|
6085 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U)
|
|
|
6086 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000U)
|
|
|
6087 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000U)
|
|
|
6088 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000U)
|
|
|
6089 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00200000U)
|
|
|
6090 #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00400000U)
|
|
|
6091 #define RCC_APB2RSTR_DFSDMRST ((uint32_t)0x01000000U)
|
|
|
6092
|
|
|
6093 /******************** Bit definition for RCC_AHB1ENR register ***************/
|
|
|
6094 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00000001U)
|
|
|
6095 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00000002U)
|
|
|
6096 #define RCC_AHB1ENR_FLASHEN ((uint32_t)0x00000100U)
|
|
|
6097 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000U)
|
|
|
6098 #define RCC_AHB1ENR_TSCEN ((uint32_t)0x00010000U)
|
|
|
6099
|
|
|
6100 /******************** Bit definition for RCC_AHB2ENR register ***************/
|
|
|
6101 #define RCC_AHB2ENR_GPIOAEN ((uint32_t)0x00000001U)
|
|
|
6102 #define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002U)
|
|
|
6103 #define RCC_AHB2ENR_GPIOCEN ((uint32_t)0x00000004U)
|
|
|
6104 #define RCC_AHB2ENR_GPIODEN ((uint32_t)0x00000008U)
|
|
|
6105 #define RCC_AHB2ENR_GPIOEEN ((uint32_t)0x00000010U)
|
|
|
6106 #define RCC_AHB2ENR_GPIOFEN ((uint32_t)0x00000020U)
|
|
|
6107 #define RCC_AHB2ENR_GPIOGEN ((uint32_t)0x00000040U)
|
|
|
6108 #define RCC_AHB2ENR_GPIOHEN ((uint32_t)0x00000080U)
|
|
|
6109 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00001000U)
|
|
|
6110 #define RCC_AHB2ENR_ADCEN ((uint32_t)0x00002000U)
|
|
|
6111 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00040000U)
|
|
|
6112
|
|
|
6113 /******************** Bit definition for RCC_AHB3ENR register ***************/
|
|
|
6114 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001U)
|
|
|
6115 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000100U)
|
|
|
6116
|
|
|
6117 /******************** Bit definition for RCC_APB1ENR1 register ***************/
|
|
|
6118 #define RCC_APB1ENR1_TIM2EN ((uint32_t)0x00000001U)
|
|
|
6119 #define RCC_APB1ENR1_TIM3EN ((uint32_t)0x00000002U)
|
|
|
6120 #define RCC_APB1ENR1_TIM4EN ((uint32_t)0x00000004U)
|
|
|
6121 #define RCC_APB1ENR1_TIM5EN ((uint32_t)0x00000008U)
|
|
|
6122 #define RCC_APB1ENR1_TIM6EN ((uint32_t)0x00000010U)
|
|
|
6123 #define RCC_APB1ENR1_TIM7EN ((uint32_t)0x00000020U)
|
|
|
6124 #define RCC_APB1ENR1_LCDEN ((uint32_t)0x00000200U)
|
|
|
6125 #define RCC_APB1ENR1_WWDGEN ((uint32_t)0x00000800U)
|
|
|
6126 #define RCC_APB1ENR1_SPI2EN ((uint32_t)0x00004000U)
|
|
|
6127 #define RCC_APB1ENR1_SPI3EN ((uint32_t)0x00008000U)
|
|
|
6128 #define RCC_APB1ENR1_USART2EN ((uint32_t)0x00020000U)
|
|
|
6129 #define RCC_APB1ENR1_USART3EN ((uint32_t)0x00040000U)
|
|
|
6130 #define RCC_APB1ENR1_UART4EN ((uint32_t)0x00080000U)
|
|
|
6131 #define RCC_APB1ENR1_UART5EN ((uint32_t)0x00100000U)
|
|
|
6132 #define RCC_APB1ENR1_I2C1EN ((uint32_t)0x00200000U)
|
|
|
6133 #define RCC_APB1ENR1_I2C2EN ((uint32_t)0x00400000U)
|
|
|
6134 #define RCC_APB1ENR1_I2C3EN ((uint32_t)0x00800000U)
|
|
|
6135 #define RCC_APB1ENR1_CAN1EN ((uint32_t)0x02000000U)
|
|
|
6136 #define RCC_APB1ENR1_PWREN ((uint32_t)0x10000000U)
|
|
|
6137 #define RCC_APB1ENR1_DAC1EN ((uint32_t)0x20000000U)
|
|
|
6138 #define RCC_APB1ENR1_OPAMPEN ((uint32_t)0x40000000U)
|
|
|
6139 #define RCC_APB1ENR1_LPTIM1EN ((uint32_t)0x80000000U)
|
|
|
6140
|
|
|
6141 /******************** Bit definition for RCC_APB1RSTR2 register **************/
|
|
|
6142 #define RCC_APB1ENR2_LPUART1EN ((uint32_t)0x00000001U)
|
|
|
6143 #define RCC_APB1ENR2_SWPMI1EN ((uint32_t)0x00000004U)
|
|
|
6144 #define RCC_APB1ENR2_LPTIM2EN ((uint32_t)0x00000020U)
|
|
|
6145
|
|
|
6146 /******************** Bit definition for RCC_APB2ENR register ***************/
|
|
|
6147 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U)
|
|
|
6148 #define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U)
|
|
|
6149 #define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000400U)
|
|
|
6150 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800U)
|
|
|
6151 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U)
|
|
|
6152 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000U)
|
|
|
6153 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U)
|
|
|
6154 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000U)
|
|
|
6155 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000U)
|
|
|
6156 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000U)
|
|
|
6157 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00200000U)
|
|
|
6158 #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00400000U)
|
|
|
6159 #define RCC_APB2ENR_DFSDMEN ((uint32_t)0x01000000U)
|
|
|
6160
|
|
|
6161 /******************** Bit definition for RCC_AHB1SMENR register ***************/
|
|
|
6162 #define RCC_AHB1SMENR_DMA1SMEN ((uint32_t)0x00000001U)
|
|
|
6163 #define RCC_AHB1SMENR_DMA2SMEN ((uint32_t)0x00000002U)
|
|
|
6164 #define RCC_AHB1SMENR_FLASHSMEN ((uint32_t)0x00000100U)
|
|
|
6165 #define RCC_AHB1SMENR_SRAM1SMEN ((uint32_t)0x00000200U)
|
|
|
6166 #define RCC_AHB1SMENR_CRCSMEN ((uint32_t)0x00001000U)
|
|
|
6167 #define RCC_AHB1SMENR_TSCSMEN ((uint32_t)0x00010000U)
|
|
|
6168
|
|
|
6169 /******************** Bit definition for RCC_AHB2SMENR register *************/
|
|
|
6170 #define RCC_AHB2SMENR_GPIOASMEN ((uint32_t)0x00000001U)
|
|
|
6171 #define RCC_AHB2SMENR_GPIOBSMEN ((uint32_t)0x00000002U)
|
|
|
6172 #define RCC_AHB2SMENR_GPIOCSMEN ((uint32_t)0x00000004U)
|
|
|
6173 #define RCC_AHB2SMENR_GPIODSMEN ((uint32_t)0x00000008U)
|
|
|
6174 #define RCC_AHB2SMENR_GPIOESMEN ((uint32_t)0x00000010U)
|
|
|
6175 #define RCC_AHB2SMENR_GPIOFSMEN ((uint32_t)0x00000020U)
|
|
|
6176 #define RCC_AHB2SMENR_GPIOGSMEN ((uint32_t)0x00000040U)
|
|
|
6177 #define RCC_AHB2SMENR_GPIOHSMEN ((uint32_t)0x00000080U)
|
|
|
6178 #define RCC_AHB2SMENR_SRAM2SMEN ((uint32_t)0x00000200U)
|
|
|
6179 #define RCC_AHB2SMENR_OTGFSSMEN ((uint32_t)0x00001000U)
|
|
|
6180 #define RCC_AHB2SMENR_ADCSMEN ((uint32_t)0x00002000U)
|
|
|
6181 #define RCC_AHB2SMENR_RNGSMEN ((uint32_t)0x00040000U)
|
|
|
6182
|
|
|
6183 /******************** Bit definition for RCC_AHB3SMENR register *************/
|
|
|
6184 #define RCC_AHB3SMENR_FMCSMEN ((uint32_t)0x00000001U)
|
|
|
6185 #define RCC_AHB3SMENR_QSPISMEN ((uint32_t)0x00000100U)
|
|
|
6186
|
|
|
6187 /******************** Bit definition for RCC_APB1SMENR1 register *************/
|
|
|
6188 #define RCC_APB1SMENR1_TIM2SMEN ((uint32_t)0x00000001U)
|
|
|
6189 #define RCC_APB1SMENR1_TIM3SMEN ((uint32_t)0x00000002U)
|
|
|
6190 #define RCC_APB1SMENR1_TIM4SMEN ((uint32_t)0x00000004U)
|
|
|
6191 #define RCC_APB1SMENR1_TIM5SMEN ((uint32_t)0x00000008U)
|
|
|
6192 #define RCC_APB1SMENR1_TIM6SMEN ((uint32_t)0x00000010U)
|
|
|
6193 #define RCC_APB1SMENR1_TIM7SMEN ((uint32_t)0x00000020U)
|
|
|
6194 #define RCC_APB1SMENR1_LCDSMEN ((uint32_t)0x00000200U)
|
|
|
6195 #define RCC_APB1SMENR1_WWDGSMEN ((uint32_t)0x00000800U)
|
|
|
6196 #define RCC_APB1SMENR1_SPI2SMEN ((uint32_t)0x00004000U)
|
|
|
6197 #define RCC_APB1SMENR1_SPI3SMEN ((uint32_t)0x00008000U)
|
|
|
6198 #define RCC_APB1SMENR1_USART2SMEN ((uint32_t)0x00020000U)
|
|
|
6199 #define RCC_APB1SMENR1_USART3SMEN ((uint32_t)0x00040000U)
|
|
|
6200 #define RCC_APB1SMENR1_UART4SMEN ((uint32_t)0x00080000U)
|
|
|
6201 #define RCC_APB1SMENR1_UART5SMEN ((uint32_t)0x00100000U)
|
|
|
6202 #define RCC_APB1SMENR1_I2C1SMEN ((uint32_t)0x00200000U)
|
|
|
6203 #define RCC_APB1SMENR1_I2C2SMEN ((uint32_t)0x00400000U)
|
|
|
6204 #define RCC_APB1SMENR1_I2C3SMEN ((uint32_t)0x00800000U)
|
|
|
6205 #define RCC_APB1SMENR1_CAN1SMEN ((uint32_t)0x02000000U)
|
|
|
6206 #define RCC_APB1SMENR1_PWRSMEN ((uint32_t)0x10000000U)
|
|
|
6207 #define RCC_APB1SMENR1_DAC1SMEN ((uint32_t)0x20000000U)
|
|
|
6208 #define RCC_APB1SMENR1_OPAMPSMEN ((uint32_t)0x40000000U)
|
|
|
6209 #define RCC_APB1SMENR1_LPTIM1SMEN ((uint32_t)0x80000000U)
|
|
|
6210
|
|
|
6211 /******************** Bit definition for RCC_APB1SMENR2 register *************/
|
|
|
6212 #define RCC_APB1SMENR2_LPUART1SMEN ((uint32_t)0x00000001U)
|
|
|
6213 #define RCC_APB1SMENR2_SWPMI1SMEN ((uint32_t)0x00000004U)
|
|
|
6214 #define RCC_APB1SMENR2_LPTIM2SMEN ((uint32_t)0x00000020U)
|
|
|
6215
|
|
|
6216 /******************** Bit definition for RCC_APB2SMENR register *************/
|
|
|
6217 #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U)
|
|
|
6218 #define RCC_APB2SMENR_SDMMC1SMEN ((uint32_t)0x00000400U)
|
|
|
6219 #define RCC_APB2SMENR_TIM1SMEN ((uint32_t)0x00000800U)
|
|
|
6220 #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U)
|
|
|
6221 #define RCC_APB2SMENR_TIM8SMEN ((uint32_t)0x00002000U)
|
|
|
6222 #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U)
|
|
|
6223 #define RCC_APB2SMENR_TIM15SMEN ((uint32_t)0x00010000U)
|
|
|
6224 #define RCC_APB2SMENR_TIM16SMEN ((uint32_t)0x00020000U)
|
|
|
6225 #define RCC_APB2SMENR_TIM17SMEN ((uint32_t)0x00040000U)
|
|
|
6226 #define RCC_APB2SMENR_SAI1SMEN ((uint32_t)0x00200000U)
|
|
|
6227 #define RCC_APB2SMENR_SAI2SMEN ((uint32_t)0x00400000U)
|
|
|
6228 #define RCC_APB2SMENR_DFSDMSMEN ((uint32_t)0x01000000U)
|
|
|
6229
|
|
|
6230 /******************** Bit definition for RCC_CCIPR register ******************/
|
|
|
6231 #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U)
|
|
|
6232 #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U)
|
|
|
6233 #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U)
|
|
|
6234
|
|
|
6235 #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU)
|
|
|
6236 #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U)
|
|
|
6237 #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U)
|
|
|
6238
|
|
|
6239 #define RCC_CCIPR_USART3SEL ((uint32_t)0x00000030U)
|
|
|
6240 #define RCC_CCIPR_USART3SEL_0 ((uint32_t)0x00000010U)
|
|
|
6241 #define RCC_CCIPR_USART3SEL_1 ((uint32_t)0x00000020U)
|
|
|
6242
|
|
|
6243 #define RCC_CCIPR_UART4SEL ((uint32_t)0x000000C0U)
|
|
|
6244 #define RCC_CCIPR_UART4SEL_0 ((uint32_t)0x00000040U)
|
|
|
6245 #define RCC_CCIPR_UART4SEL_1 ((uint32_t)0x00000080U)
|
|
|
6246
|
|
|
6247 #define RCC_CCIPR_UART5SEL ((uint32_t)0x00000300U)
|
|
|
6248 #define RCC_CCIPR_UART5SEL_0 ((uint32_t)0x00000100U)
|
|
|
6249 #define RCC_CCIPR_UART5SEL_1 ((uint32_t)0x00000200U)
|
|
|
6250
|
|
|
6251 #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x00000C00U)
|
|
|
6252 #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x00000400U)
|
|
|
6253 #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x00000800U)
|
|
|
6254
|
|
|
6255 #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U)
|
|
|
6256 #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U)
|
|
|
6257 #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U)
|
|
|
6258
|
|
|
6259 #define RCC_CCIPR_I2C2SEL ((uint32_t)0x0000C000U)
|
|
|
6260 #define RCC_CCIPR_I2C2SEL_0 ((uint32_t)0x00004000U)
|
|
|
6261 #define RCC_CCIPR_I2C2SEL_1 ((uint32_t)0x00008000U)
|
|
|
6262
|
|
|
6263 #define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000U)
|
|
|
6264 #define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000U)
|
|
|
6265 #define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000U)
|
|
|
6266
|
|
|
6267 #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U)
|
|
|
6268 #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U)
|
|
|
6269 #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U)
|
|
|
6270
|
|
|
6271 #define RCC_CCIPR_LPTIM2SEL ((uint32_t)0x00300000U)
|
|
|
6272 #define RCC_CCIPR_LPTIM2SEL_0 ((uint32_t)0x00100000U)
|
|
|
6273 #define RCC_CCIPR_LPTIM2SEL_1 ((uint32_t)0x00200000U)
|
|
|
6274
|
|
|
6275 #define RCC_CCIPR_SAI1SEL ((uint32_t)0x00C00000U)
|
|
|
6276 #define RCC_CCIPR_SAI1SEL_0 ((uint32_t)0x00400000U)
|
|
|
6277 #define RCC_CCIPR_SAI1SEL_1 ((uint32_t)0x00800000U)
|
|
|
6278
|
|
|
6279 #define RCC_CCIPR_SAI2SEL ((uint32_t)0x03000000U)
|
|
|
6280 #define RCC_CCIPR_SAI2SEL_0 ((uint32_t)0x01000000U)
|
|
|
6281 #define RCC_CCIPR_SAI2SEL_1 ((uint32_t)0x02000000U)
|
|
|
6282
|
|
|
6283 #define RCC_CCIPR_CLK48SEL ((uint32_t)0x0C000000U)
|
|
|
6284 #define RCC_CCIPR_CLK48SEL_0 ((uint32_t)0x04000000U)
|
|
|
6285 #define RCC_CCIPR_CLK48SEL_1 ((uint32_t)0x08000000U)
|
|
|
6286
|
|
|
6287 #define RCC_CCIPR_ADCSEL ((uint32_t)0x30000000U)
|
|
|
6288 #define RCC_CCIPR_ADCSEL_0 ((uint32_t)0x10000000U)
|
|
|
6289 #define RCC_CCIPR_ADCSEL_1 ((uint32_t)0x20000000U)
|
|
|
6290
|
|
|
6291 #define RCC_CCIPR_SWPMI1SEL ((uint32_t)0x40000000U)
|
|
|
6292 #define RCC_CCIPR_DFSDMSEL ((uint32_t)0x80000000U)
|
|
|
6293
|
|
|
6294 /******************** Bit definition for RCC_BDCR register ******************/
|
|
|
6295 #define RCC_BDCR_LSEON ((uint32_t)0x00000001U)
|
|
|
6296 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002U)
|
|
|
6297 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004U)
|
|
|
6298
|
|
|
6299 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018U)
|
|
|
6300 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008U)
|
|
|
6301 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010U)
|
|
|
6302
|
|
|
6303 #define RCC_BDCR_LSECSSON ((uint32_t)0x00000020U)
|
|
|
6304 #define RCC_BDCR_LSECSSD ((uint32_t)0x00000040U)
|
|
|
6305
|
|
|
6306 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300U)
|
|
|
6307 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100U)
|
|
|
6308 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200U)
|
|
|
6309
|
|
|
6310 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000U)
|
|
|
6311 #define RCC_BDCR_BDRST ((uint32_t)0x00010000U)
|
|
|
6312 #define RCC_BDCR_LSCOEN ((uint32_t)0x01000000U)
|
|
|
6313 #define RCC_BDCR_LSCOSEL ((uint32_t)0x02000000U)
|
|
|
6314
|
|
|
6315 /******************** Bit definition for RCC_CSR register *******************/
|
|
|
6316 #define RCC_CSR_LSION ((uint32_t)0x00000001U)
|
|
|
6317 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002U)
|
|
|
6318
|
|
|
6319 #define RCC_CSR_MSISRANGE ((uint32_t)0x00000F00U)
|
|
|
6320 #define RCC_CSR_MSISRANGE_1 ((uint32_t)0x00000400U) /*!< MSI frequency 1MHZ */
|
|
|
6321 #define RCC_CSR_MSISRANGE_2 ((uint32_t)0x00000500U) /*!< MSI frequency 2MHZ */
|
|
|
6322 #define RCC_CSR_MSISRANGE_4 ((uint32_t)0x00000600U) /*!< The default frequency 4MHZ */
|
|
|
6323 #define RCC_CSR_MSISRANGE_8 ((uint32_t)0x00000700U) /*!< MSI frequency 8MHZ */
|
|
|
6324
|
|
|
6325 #define RCC_CSR_RMVF ((uint32_t)0x00800000U)
|
|
|
6326 #define RCC_CSR_FWRSTF ((uint32_t)0x01000000U)
|
|
|
6327 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U)
|
|
|
6328 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000U)
|
|
|
6329 #define RCC_CSR_BORRSTF ((uint32_t)0x08000000U)
|
|
|
6330 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U)
|
|
|
6331 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U)
|
|
|
6332 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U)
|
|
|
6333 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U)
|
|
|
6334
|
|
|
6335
|
|
|
6336
|
|
|
6337 /******************************************************************************/
|
|
|
6338 /* */
|
|
|
6339 /* RNG */
|
|
|
6340 /* */
|
|
|
6341 /******************************************************************************/
|
|
|
6342 /******************** Bits definition for RNG_CR register *******************/
|
|
|
6343 #define RNG_CR_RNGEN ((uint32_t)0x00000004U)
|
|
|
6344 #define RNG_CR_IE ((uint32_t)0x00000008U)
|
|
|
6345
|
|
|
6346 /******************** Bits definition for RNG_SR register *******************/
|
|
|
6347 #define RNG_SR_DRDY ((uint32_t)0x00000001U)
|
|
|
6348 #define RNG_SR_CECS ((uint32_t)0x00000002U)
|
|
|
6349 #define RNG_SR_SECS ((uint32_t)0x00000004U)
|
|
|
6350 #define RNG_SR_CEIS ((uint32_t)0x00000020U)
|
|
|
6351 #define RNG_SR_SEIS ((uint32_t)0x00000040U)
|
|
|
6352
|
|
|
6353 /******************************************************************************/
|
|
|
6354 /* */
|
|
|
6355 /* Real-Time Clock (RTC) */
|
|
|
6356 /* */
|
|
|
6357 /******************************************************************************/
|
|
|
6358 /*
|
|
|
6359 * @brief Specific device feature definitions
|
|
|
6360 */
|
|
|
6361 #define RTC_TAMPER1_SUPPORT
|
|
|
6362 #define RTC_TAMPER3_SUPPORT
|
|
|
6363 #define RTC_WAKEUP_SUPPORT
|
|
|
6364 #define RTC_BACKUP_SUPPORT
|
|
|
6365
|
|
|
6366 /******************** Bits definition for RTC_TR register *******************/
|
|
|
6367 #define RTC_TR_PM ((uint32_t)0x00400000U)
|
|
|
6368 #define RTC_TR_HT ((uint32_t)0x00300000U)
|
|
|
6369 #define RTC_TR_HT_0 ((uint32_t)0x00100000U)
|
|
|
6370 #define RTC_TR_HT_1 ((uint32_t)0x00200000U)
|
|
|
6371 #define RTC_TR_HU ((uint32_t)0x000F0000U)
|
|
|
6372 #define RTC_TR_HU_0 ((uint32_t)0x00010000U)
|
|
|
6373 #define RTC_TR_HU_1 ((uint32_t)0x00020000U)
|
|
|
6374 #define RTC_TR_HU_2 ((uint32_t)0x00040000U)
|
|
|
6375 #define RTC_TR_HU_3 ((uint32_t)0x00080000U)
|
|
|
6376 #define RTC_TR_MNT ((uint32_t)0x00007000U)
|
|
|
6377 #define RTC_TR_MNT_0 ((uint32_t)0x00001000U)
|
|
|
6378 #define RTC_TR_MNT_1 ((uint32_t)0x00002000U)
|
|
|
6379 #define RTC_TR_MNT_2 ((uint32_t)0x00004000U)
|
|
|
6380 #define RTC_TR_MNU ((uint32_t)0x00000F00U)
|
|
|
6381 #define RTC_TR_MNU_0 ((uint32_t)0x00000100U)
|
|
|
6382 #define RTC_TR_MNU_1 ((uint32_t)0x00000200U)
|
|
|
6383 #define RTC_TR_MNU_2 ((uint32_t)0x00000400U)
|
|
|
6384 #define RTC_TR_MNU_3 ((uint32_t)0x00000800U)
|
|
|
6385 #define RTC_TR_ST ((uint32_t)0x00000070U)
|
|
|
6386 #define RTC_TR_ST_0 ((uint32_t)0x00000010U)
|
|
|
6387 #define RTC_TR_ST_1 ((uint32_t)0x00000020U)
|
|
|
6388 #define RTC_TR_ST_2 ((uint32_t)0x00000040U)
|
|
|
6389 #define RTC_TR_SU ((uint32_t)0x0000000FU)
|
|
|
6390 #define RTC_TR_SU_0 ((uint32_t)0x00000001U)
|
|
|
6391 #define RTC_TR_SU_1 ((uint32_t)0x00000002U)
|
|
|
6392 #define RTC_TR_SU_2 ((uint32_t)0x00000004U)
|
|
|
6393 #define RTC_TR_SU_3 ((uint32_t)0x00000008U)
|
|
|
6394
|
|
|
6395 /******************** Bits definition for RTC_DR register *******************/
|
|
|
6396 #define RTC_DR_YT ((uint32_t)0x00F00000U)
|
|
|
6397 #define RTC_DR_YT_0 ((uint32_t)0x00100000U)
|
|
|
6398 #define RTC_DR_YT_1 ((uint32_t)0x00200000U)
|
|
|
6399 #define RTC_DR_YT_2 ((uint32_t)0x00400000U)
|
|
|
6400 #define RTC_DR_YT_3 ((uint32_t)0x00800000U)
|
|
|
6401 #define RTC_DR_YU ((uint32_t)0x000F0000U)
|
|
|
6402 #define RTC_DR_YU_0 ((uint32_t)0x00010000U)
|
|
|
6403 #define RTC_DR_YU_1 ((uint32_t)0x00020000U)
|
|
|
6404 #define RTC_DR_YU_2 ((uint32_t)0x00040000U)
|
|
|
6405 #define RTC_DR_YU_3 ((uint32_t)0x00080000U)
|
|
|
6406 #define RTC_DR_WDU ((uint32_t)0x0000E000U)
|
|
|
6407 #define RTC_DR_WDU_0 ((uint32_t)0x00002000U)
|
|
|
6408 #define RTC_DR_WDU_1 ((uint32_t)0x00004000U)
|
|
|
6409 #define RTC_DR_WDU_2 ((uint32_t)0x00008000U)
|
|
|
6410 #define RTC_DR_MT ((uint32_t)0x00001000U)
|
|
|
6411 #define RTC_DR_MU ((uint32_t)0x00000F00U)
|
|
|
6412 #define RTC_DR_MU_0 ((uint32_t)0x00000100U)
|
|
|
6413 #define RTC_DR_MU_1 ((uint32_t)0x00000200U)
|
|
|
6414 #define RTC_DR_MU_2 ((uint32_t)0x00000400U)
|
|
|
6415 #define RTC_DR_MU_3 ((uint32_t)0x00000800U)
|
|
|
6416 #define RTC_DR_DT ((uint32_t)0x00000030U)
|
|
|
6417 #define RTC_DR_DT_0 ((uint32_t)0x00000010U)
|
|
|
6418 #define RTC_DR_DT_1 ((uint32_t)0x00000020U)
|
|
|
6419 #define RTC_DR_DU ((uint32_t)0x0000000FU)
|
|
|
6420 #define RTC_DR_DU_0 ((uint32_t)0x00000001U)
|
|
|
6421 #define RTC_DR_DU_1 ((uint32_t)0x00000002U)
|
|
|
6422 #define RTC_DR_DU_2 ((uint32_t)0x00000004U)
|
|
|
6423 #define RTC_DR_DU_3 ((uint32_t)0x00000008U)
|
|
|
6424
|
|
|
6425 /******************** Bits definition for RTC_CR register *******************/
|
|
|
6426 #define RTC_CR_ITSE ((uint32_t)0x01000000U)
|
|
|
6427 #define RTC_CR_COE ((uint32_t)0x00800000U)
|
|
|
6428 #define RTC_CR_OSEL ((uint32_t)0x00600000U)
|
|
|
6429 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000U)
|
|
|
6430 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000U)
|
|
|
6431 #define RTC_CR_POL ((uint32_t)0x00100000U)
|
|
|
6432 #define RTC_CR_COSEL ((uint32_t)0x00080000U)
|
|
|
6433 #define RTC_CR_BCK ((uint32_t)0x00040000U)
|
|
|
6434 #define RTC_CR_SUB1H ((uint32_t)0x00020000U)
|
|
|
6435 #define RTC_CR_ADD1H ((uint32_t)0x00010000U)
|
|
|
6436 #define RTC_CR_TSIE ((uint32_t)0x00008000U)
|
|
|
6437 #define RTC_CR_WUTIE ((uint32_t)0x00004000U)
|
|
|
6438 #define RTC_CR_ALRBIE ((uint32_t)0x00002000U)
|
|
|
6439 #define RTC_CR_ALRAIE ((uint32_t)0x00001000U)
|
|
|
6440 #define RTC_CR_TSE ((uint32_t)0x00000800U)
|
|
|
6441 #define RTC_CR_WUTE ((uint32_t)0x00000400U)
|
|
|
6442 #define RTC_CR_ALRBE ((uint32_t)0x00000200U)
|
|
|
6443 #define RTC_CR_ALRAE ((uint32_t)0x00000100U)
|
|
|
6444 #define RTC_CR_FMT ((uint32_t)0x00000040U)
|
|
|
6445 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020U)
|
|
|
6446 #define RTC_CR_REFCKON ((uint32_t)0x00000010U)
|
|
|
6447 #define RTC_CR_TSEDGE ((uint32_t)0x00000008U)
|
|
|
6448 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007U)
|
|
|
6449 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U)
|
|
|
6450 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U)
|
|
|
6451 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U)
|
|
|
6452
|
|
|
6453 /******************** Bits definition for RTC_ISR register ******************/
|
|
|
6454 #define RTC_ISR_ITSF ((uint32_t)0x00020000U)
|
|
|
6455 #define RTC_ISR_RECALPF ((uint32_t)0x00010000U)
|
|
|
6456 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000U)
|
|
|
6457 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000U)
|
|
|
6458 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000U)
|
|
|
6459 #define RTC_ISR_TSOVF ((uint32_t)0x00001000U)
|
|
|
6460 #define RTC_ISR_TSF ((uint32_t)0x00000800U)
|
|
|
6461 #define RTC_ISR_WUTF ((uint32_t)0x00000400U)
|
|
|
6462 #define RTC_ISR_ALRBF ((uint32_t)0x00000200U)
|
|
|
6463 #define RTC_ISR_ALRAF ((uint32_t)0x00000100U)
|
|
|
6464 #define RTC_ISR_INIT ((uint32_t)0x00000080U)
|
|
|
6465 #define RTC_ISR_INITF ((uint32_t)0x00000040U)
|
|
|
6466 #define RTC_ISR_RSF ((uint32_t)0x00000020U)
|
|
|
6467 #define RTC_ISR_INITS ((uint32_t)0x00000010U)
|
|
|
6468 #define RTC_ISR_SHPF ((uint32_t)0x00000008U)
|
|
|
6469 #define RTC_ISR_WUTWF ((uint32_t)0x00000004U)
|
|
|
6470 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002U)
|
|
|
6471 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001U)
|
|
|
6472
|
|
|
6473 /******************** Bits definition for RTC_PRER register *****************/
|
|
|
6474 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U)
|
|
|
6475 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU)
|
|
|
6476
|
|
|
6477 /******************** Bits definition for RTC_WUTR register *****************/
|
|
|
6478 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
|
|
|
6479
|
|
|
6480 /******************** Bits definition for RTC_ALRMAR register ***************/
|
|
|
6481 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U)
|
|
|
6482 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U)
|
|
|
6483 #define RTC_ALRMAR_DT ((uint32_t)0x30000000U)
|
|
|
6484 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U)
|
|
|
6485 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U)
|
|
|
6486 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000U)
|
|
|
6487 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U)
|
|
|
6488 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U)
|
|
|
6489 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U)
|
|
|
6490 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U)
|
|
|
6491 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U)
|
|
|
6492 #define RTC_ALRMAR_PM ((uint32_t)0x00400000U)
|
|
|
6493 #define RTC_ALRMAR_HT ((uint32_t)0x00300000U)
|
|
|
6494 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U)
|
|
|
6495 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U)
|
|
|
6496 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000U)
|
|
|
6497 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U)
|
|
|
6498 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U)
|
|
|
6499 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U)
|
|
|
6500 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U)
|
|
|
6501 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U)
|
|
|
6502 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000U)
|
|
|
6503 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U)
|
|
|
6504 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U)
|
|
|
6505 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U)
|
|
|
6506 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U)
|
|
|
6507 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U)
|
|
|
6508 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U)
|
|
|
6509 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U)
|
|
|
6510 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U)
|
|
|
6511 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U)
|
|
|
6512 #define RTC_ALRMAR_ST ((uint32_t)0x00000070U)
|
|
|
6513 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U)
|
|
|
6514 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U)
|
|
|
6515 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U)
|
|
|
6516 #define RTC_ALRMAR_SU ((uint32_t)0x0000000FU)
|
|
|
6517 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U)
|
|
|
6518 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U)
|
|
|
6519 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U)
|
|
|
6520 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U)
|
|
|
6521
|
|
|
6522 /******************** Bits definition for RTC_ALRMBR register ***************/
|
|
|
6523 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U)
|
|
|
6524 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U)
|
|
|
6525 #define RTC_ALRMBR_DT ((uint32_t)0x30000000U)
|
|
|
6526 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U)
|
|
|
6527 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U)
|
|
|
6528 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000U)
|
|
|
6529 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U)
|
|
|
6530 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U)
|
|
|
6531 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U)
|
|
|
6532 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U)
|
|
|
6533 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U)
|
|
|
6534 #define RTC_ALRMBR_PM ((uint32_t)0x00400000U)
|
|
|
6535 #define RTC_ALRMBR_HT ((uint32_t)0x00300000U)
|
|
|
6536 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U)
|
|
|
6537 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U)
|
|
|
6538 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000U)
|
|
|
6539 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U)
|
|
|
6540 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U)
|
|
|
6541 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U)
|
|
|
6542 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U)
|
|
|
6543 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U)
|
|
|
6544 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000U)
|
|
|
6545 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U)
|
|
|
6546 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U)
|
|
|
6547 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U)
|
|
|
6548 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U)
|
|
|
6549 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U)
|
|
|
6550 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U)
|
|
|
6551 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U)
|
|
|
6552 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U)
|
|
|
6553 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U)
|
|
|
6554 #define RTC_ALRMBR_ST ((uint32_t)0x00000070U)
|
|
|
6555 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U)
|
|
|
6556 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U)
|
|
|
6557 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U)
|
|
|
6558 #define RTC_ALRMBR_SU ((uint32_t)0x0000000FU)
|
|
|
6559 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U)
|
|
|
6560 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U)
|
|
|
6561 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U)
|
|
|
6562 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U)
|
|
|
6563
|
|
|
6564 /******************** Bits definition for RTC_WPR register ******************/
|
|
|
6565 #define RTC_WPR_KEY ((uint32_t)0x000000FFU)
|
|
|
6566
|
|
|
6567 /******************** Bits definition for RTC_SSR register ******************/
|
|
|
6568 #define RTC_SSR_SS ((uint32_t)0x0000FFFFU)
|
|
|
6569
|
|
|
6570 /******************** Bits definition for RTC_SHIFTR register ***************/
|
|
|
6571 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU)
|
|
|
6572 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U)
|
|
|
6573
|
|
|
6574 /******************** Bits definition for RTC_TSTR register *****************/
|
|
|
6575 #define RTC_TSTR_PM ((uint32_t)0x00400000U)
|
|
|
6576 #define RTC_TSTR_HT ((uint32_t)0x00300000U)
|
|
|
6577 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000U)
|
|
|
6578 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000U)
|
|
|
6579 #define RTC_TSTR_HU ((uint32_t)0x000F0000U)
|
|
|
6580 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000U)
|
|
|
6581 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000U)
|
|
|
6582 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000U)
|
|
|
6583 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000U)
|
|
|
6584 #define RTC_TSTR_MNT ((uint32_t)0x00007000U)
|
|
|
6585 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U)
|
|
|
6586 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U)
|
|
|
6587 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U)
|
|
|
6588 #define RTC_TSTR_MNU ((uint32_t)0x00000F00U)
|
|
|
6589 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U)
|
|
|
6590 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U)
|
|
|
6591 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U)
|
|
|
6592 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U)
|
|
|
6593 #define RTC_TSTR_ST ((uint32_t)0x00000070U)
|
|
|
6594 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010U)
|
|
|
6595 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020U)
|
|
|
6596 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040U)
|
|
|
6597 #define RTC_TSTR_SU ((uint32_t)0x0000000FU)
|
|
|
6598 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001U)
|
|
|
6599 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002U)
|
|
|
6600 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004U)
|
|
|
6601 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008U)
|
|
|
6602
|
|
|
6603 /******************** Bits definition for RTC_TSDR register *****************/
|
|
|
6604 #define RTC_TSDR_WDU ((uint32_t)0x0000E000U)
|
|
|
6605 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U)
|
|
|
6606 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U)
|
|
|
6607 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U)
|
|
|
6608 #define RTC_TSDR_MT ((uint32_t)0x00001000U)
|
|
|
6609 #define RTC_TSDR_MU ((uint32_t)0x00000F00U)
|
|
|
6610 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100U)
|
|
|
6611 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200U)
|
|
|
6612 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400U)
|
|
|
6613 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800U)
|
|
|
6614 #define RTC_TSDR_DT ((uint32_t)0x00000030U)
|
|
|
6615 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010U)
|
|
|
6616 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020U)
|
|
|
6617 #define RTC_TSDR_DU ((uint32_t)0x0000000FU)
|
|
|
6618 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001U)
|
|
|
6619 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002U)
|
|
|
6620 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004U)
|
|
|
6621 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008U)
|
|
|
6622
|
|
|
6623 /******************** Bits definition for RTC_TSSSR register ****************/
|
|
|
6624 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
|
|
|
6625
|
|
|
6626 /******************** Bits definition for RTC_CAL register *****************/
|
|
|
6627 #define RTC_CALR_CALP ((uint32_t)0x00008000U)
|
|
|
6628 #define RTC_CALR_CALW8 ((uint32_t)0x00004000U)
|
|
|
6629 #define RTC_CALR_CALW16 ((uint32_t)0x00002000U)
|
|
|
6630 #define RTC_CALR_CALM ((uint32_t)0x000001FFU)
|
|
|
6631 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001U)
|
|
|
6632 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002U)
|
|
|
6633 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004U)
|
|
|
6634 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008U)
|
|
|
6635 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010U)
|
|
|
6636 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020U)
|
|
|
6637 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040U)
|
|
|
6638 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080U)
|
|
|
6639 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100U)
|
|
|
6640
|
|
|
6641 /******************** Bits definition for RTC_TAMPCR register ***************/
|
|
|
6642 #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U)
|
|
|
6643 #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U)
|
|
|
6644 #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U)
|
|
|
6645 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U)
|
|
|
6646 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U)
|
|
|
6647 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U)
|
|
|
6648 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U)
|
|
|
6649 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U)
|
|
|
6650 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U)
|
|
|
6651 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U)
|
|
|
6652 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U)
|
|
|
6653 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U)
|
|
|
6654 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U)
|
|
|
6655 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U)
|
|
|
6656 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U)
|
|
|
6657 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U)
|
|
|
6658 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U)
|
|
|
6659 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U)
|
|
|
6660 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U)
|
|
|
6661 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U)
|
|
|
6662 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U)
|
|
|
6663 #define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U)
|
|
|
6664 #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U)
|
|
|
6665 #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U)
|
|
|
6666 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U)
|
|
|
6667 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U)
|
|
|
6668 #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U)
|
|
|
6669 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U)
|
|
|
6670
|
|
|
6671 /******************** Bits definition for RTC_ALRMASSR register *************/
|
|
|
6672 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
|
|
|
6673 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
|
|
|
6674 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
|
|
|
6675 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
|
|
|
6676 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
|
|
|
6677 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
|
|
|
6678
|
|
|
6679 /******************** Bits definition for RTC_ALRMBSSR register *************/
|
|
|
6680 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
|
|
|
6681 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
|
|
|
6682 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
|
|
|
6683 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
|
|
|
6684 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
|
|
|
6685 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
|
|
|
6686
|
|
|
6687 /******************** Bits definition for RTC_0R register *******************/
|
|
|
6688 #define RTC_OR_OUT_RMP ((uint32_t)0x00000002U)
|
|
|
6689 #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U)
|
|
|
6690
|
|
|
6691
|
|
|
6692 /******************** Bits definition for RTC_BKP0R register ****************/
|
|
|
6693 #define RTC_BKP0R ((uint32_t)0xFFFFFFFFU)
|
|
|
6694
|
|
|
6695 /******************** Bits definition for RTC_BKP1R register ****************/
|
|
|
6696 #define RTC_BKP1R ((uint32_t)0xFFFFFFFFU)
|
|
|
6697
|
|
|
6698 /******************** Bits definition for RTC_BKP2R register ****************/
|
|
|
6699 #define RTC_BKP2R ((uint32_t)0xFFFFFFFFU)
|
|
|
6700
|
|
|
6701 /******************** Bits definition for RTC_BKP3R register ****************/
|
|
|
6702 #define RTC_BKP3R ((uint32_t)0xFFFFFFFFU)
|
|
|
6703
|
|
|
6704 /******************** Bits definition for RTC_BKP4R register ****************/
|
|
|
6705 #define RTC_BKP4R ((uint32_t)0xFFFFFFFFU)
|
|
|
6706
|
|
|
6707 /******************** Bits definition for RTC_BKP5R register ****************/
|
|
|
6708 #define RTC_BKP5R ((uint32_t)0xFFFFFFFFU)
|
|
|
6709
|
|
|
6710 /******************** Bits definition for RTC_BKP6R register ****************/
|
|
|
6711 #define RTC_BKP6R ((uint32_t)0xFFFFFFFFU)
|
|
|
6712
|
|
|
6713 /******************** Bits definition for RTC_BKP7R register ****************/
|
|
|
6714 #define RTC_BKP7R ((uint32_t)0xFFFFFFFFU)
|
|
|
6715
|
|
|
6716 /******************** Bits definition for RTC_BKP8R register ****************/
|
|
|
6717 #define RTC_BKP8R ((uint32_t)0xFFFFFFFFU)
|
|
|
6718
|
|
|
6719 /******************** Bits definition for RTC_BKP9R register ****************/
|
|
|
6720 #define RTC_BKP9R ((uint32_t)0xFFFFFFFFU)
|
|
|
6721
|
|
|
6722 /******************** Bits definition for RTC_BKP10R register ***************/
|
|
|
6723 #define RTC_BKP10R ((uint32_t)0xFFFFFFFFU)
|
|
|
6724
|
|
|
6725 /******************** Bits definition for RTC_BKP11R register ***************/
|
|
|
6726 #define RTC_BKP11R ((uint32_t)0xFFFFFFFFU)
|
|
|
6727
|
|
|
6728 /******************** Bits definition for RTC_BKP12R register ***************/
|
|
|
6729 #define RTC_BKP12R ((uint32_t)0xFFFFFFFFU)
|
|
|
6730
|
|
|
6731 /******************** Bits definition for RTC_BKP13R register ***************/
|
|
|
6732 #define RTC_BKP13R ((uint32_t)0xFFFFFFFFU)
|
|
|
6733
|
|
|
6734 /******************** Bits definition for RTC_BKP14R register ***************/
|
|
|
6735 #define RTC_BKP14R ((uint32_t)0xFFFFFFFFU)
|
|
|
6736
|
|
|
6737 /******************** Bits definition for RTC_BKP15R register ***************/
|
|
|
6738 #define RTC_BKP15R ((uint32_t)0xFFFFFFFFU)
|
|
|
6739
|
|
|
6740 /******************** Bits definition for RTC_BKP16R register ***************/
|
|
|
6741 #define RTC_BKP16R ((uint32_t)0xFFFFFFFFU)
|
|
|
6742
|
|
|
6743 /******************** Bits definition for RTC_BKP17R register ***************/
|
|
|
6744 #define RTC_BKP17R ((uint32_t)0xFFFFFFFFU)
|
|
|
6745
|
|
|
6746 /******************** Bits definition for RTC_BKP18R register ***************/
|
|
|
6747 #define RTC_BKP18R ((uint32_t)0xFFFFFFFFU)
|
|
|
6748
|
|
|
6749 /******************** Bits definition for RTC_BKP19R register ***************/
|
|
|
6750 #define RTC_BKP19R ((uint32_t)0xFFFFFFFFU)
|
|
|
6751
|
|
|
6752 /******************** Bits definition for RTC_BKP20R register ***************/
|
|
|
6753 #define RTC_BKP20R ((uint32_t)0xFFFFFFFFU)
|
|
|
6754
|
|
|
6755 /******************** Bits definition for RTC_BKP21R register ***************/
|
|
|
6756 #define RTC_BKP21R ((uint32_t)0xFFFFFFFFU)
|
|
|
6757
|
|
|
6758 /******************** Bits definition for RTC_BKP22R register ***************/
|
|
|
6759 #define RTC_BKP22R ((uint32_t)0xFFFFFFFFU)
|
|
|
6760
|
|
|
6761 /******************** Bits definition for RTC_BKP23R register ***************/
|
|
|
6762 #define RTC_BKP23R ((uint32_t)0xFFFFFFFFU)
|
|
|
6763
|
|
|
6764 /******************** Bits definition for RTC_BKP24R register ***************/
|
|
|
6765 #define RTC_BKP24R ((uint32_t)0xFFFFFFFFU)
|
|
|
6766
|
|
|
6767 /******************** Bits definition for RTC_BKP25R register ***************/
|
|
|
6768 #define RTC_BKP25R ((uint32_t)0xFFFFFFFFU)
|
|
|
6769
|
|
|
6770 /******************** Bits definition for RTC_BKP26R register ***************/
|
|
|
6771 #define RTC_BKP26R ((uint32_t)0xFFFFFFFFU)
|
|
|
6772
|
|
|
6773 /******************** Bits definition for RTC_BKP27R register ***************/
|
|
|
6774 #define RTC_BKP27R ((uint32_t)0xFFFFFFFFU)
|
|
|
6775
|
|
|
6776 /******************** Bits definition for RTC_BKP28R register ***************/
|
|
|
6777 #define RTC_BKP28R ((uint32_t)0xFFFFFFFFU)
|
|
|
6778
|
|
|
6779 /******************** Bits definition for RTC_BKP29R register ***************/
|
|
|
6780 #define RTC_BKP29R ((uint32_t)0xFFFFFFFFU)
|
|
|
6781
|
|
|
6782 /******************** Bits definition for RTC_BKP30R register ***************/
|
|
|
6783 #define RTC_BKP30R ((uint32_t)0xFFFFFFFFU)
|
|
|
6784
|
|
|
6785 /******************** Bits definition for RTC_BKP31R register ***************/
|
|
|
6786 #define RTC_BKP31R ((uint32_t)0xFFFFFFFFU)
|
|
|
6787
|
|
|
6788 /******************** Number of backup registers ******************************/
|
|
|
6789 #define RTC_BKP_NUMBER ((uint32_t)0x00000020U)
|
|
|
6790
|
|
|
6791 /******************************************************************************/
|
|
|
6792 /* */
|
|
|
6793 /* Serial Audio Interface */
|
|
|
6794 /* */
|
|
|
6795 /******************************************************************************/
|
|
|
6796 /******************** Bit definition for SAI_GCR register *******************/
|
|
|
6797 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003U) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
|
|
|
6798 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6799 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6800
|
|
|
6801 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030U) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
|
|
|
6802 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
6803 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
6804
|
|
|
6805 /******************* Bit definition for SAI_xCR1 register *******************/
|
|
|
6806 #define SAI_xCR1_MODE ((uint32_t)0x00000003U) /*!<MODE[1:0] bits (Audio Block Mode) */
|
|
|
6807 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6808 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6809
|
|
|
6810 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000CU) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
|
|
|
6811 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
6812 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
6813
|
|
|
6814 #define SAI_xCR1_DS ((uint32_t)0x000000E0U) /*!<DS[1:0] bits (Data Size) */
|
|
|
6815 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
|
|
|
6816 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
|
|
|
6817 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
|
|
|
6818
|
|
|
6819 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100U) /*!<LSB First Configuration */
|
|
|
6820 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200U) /*!<ClocK STRobing edge */
|
|
|
6821
|
|
|
6822 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00U) /*!<SYNCEN[1:0](SYNChronization ENable) */
|
|
|
6823 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
|
|
|
6824 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
|
|
|
6825
|
|
|
6826 #define SAI_xCR1_MONO ((uint32_t)0x00001000U) /*!<Mono mode */
|
|
|
6827 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000U) /*!<Output Drive */
|
|
|
6828 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000U) /*!<Audio Block enable */
|
|
|
6829 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000U) /*!<DMA enable */
|
|
|
6830 #define SAI_xCR1_NODIV ((uint32_t)0x00080000U) /*!<No Divider Configuration */
|
|
|
6831
|
|
|
6832 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000U) /*!<MCKDIV[3:0] (Master ClocK Divider) */
|
|
|
6833 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
|
|
|
6834 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
|
|
|
6835 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
|
|
|
6836 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000U) /*!<Bit 3 */
|
|
|
6837
|
|
|
6838 /******************* Bit definition for SAI_xCR2 register *******************/
|
|
|
6839 #define SAI_xCR2_FTH ((uint32_t)0x00000007U) /*!<FTH[2:0](Fifo THreshold) */
|
|
|
6840 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6841 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6842 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
6843
|
|
|
6844 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008U) /*!<Fifo FLUSH */
|
|
|
6845 #define SAI_xCR2_TRIS ((uint32_t)0x00000010U) /*!<TRIState Management on data line */
|
|
|
6846 #define SAI_xCR2_MUTE ((uint32_t)0x00000020U) /*!<Mute mode */
|
|
|
6847 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040U) /*!<Muate value */
|
|
|
6848
|
|
|
6849
|
|
|
6850 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80U) /*!<MUTECNT[5:0] (MUTE counter) */
|
|
|
6851 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
|
|
|
6852 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
|
|
|
6853 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200U) /*!<Bit 2 */
|
|
|
6854 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400U) /*!<Bit 3 */
|
|
|
6855 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800U) /*!<Bit 4 */
|
|
|
6856 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000U) /*!<Bit 5 */
|
|
|
6857
|
|
|
6858 #define SAI_xCR2_CPL ((uint32_t)0x00002000U) /*!<CPL mode */
|
|
|
6859 #define SAI_xCR2_COMP ((uint32_t)0x0000C000U) /*!<COMP[1:0] (Companding mode) */
|
|
|
6860 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
|
|
|
6861 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
|
|
|
6862
|
|
|
6863
|
|
|
6864 /****************** Bit definition for SAI_xFRCR register *******************/
|
|
|
6865 #define SAI_xFRCR_FRL ((uint32_t)0x000000FFU) /*!<FRL[7:0](Frame length) */
|
|
|
6866 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6867 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6868 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
6869 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
6870 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
6871 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
6872 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
6873 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
|
|
|
6874
|
|
|
6875 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00U) /*!<FRL[6:0] (Frame synchronization active level length) */
|
|
|
6876 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
6877 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6878 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
6879 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
6880 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
6881 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
|
|
|
6882 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
|
|
|
6883
|
|
|
6884 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000U) /*!< Frame Synchronization Definition */
|
|
|
6885 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000U) /*!<Frame Synchronization POLarity */
|
|
|
6886 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000U) /*!<Frame Synchronization OFFset */
|
|
|
6887
|
|
|
6888 /****************** Bit definition for SAI_xSLOTR register *******************/
|
|
|
6889 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001FU) /*!<FRL[4:0](First Bit Offset) */
|
|
|
6890 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
6891 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
6892 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
6893 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
6894 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
6895
|
|
|
6896 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0U) /*!<SLOTSZ[1:0] (Slot size) */
|
|
|
6897 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
|
|
|
6898 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
|
|
|
6899
|
|
|
6900 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00U) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
|
|
|
6901 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
6902 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
6903 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
6904 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
6905
|
|
|
6906 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000U) /*!<SLOTEN[15:0] (Slot Enable) */
|
|
|
6907
|
|
|
6908 /******************* Bit definition for SAI_xIMR register *******************/
|
|
|
6909 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001U) /*!<Overrun underrun interrupt enable */
|
|
|
6910 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002U) /*!<Mute detection interrupt enable */
|
|
|
6911 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004U) /*!<Wrong Clock Configuration interrupt enable */
|
|
|
6912 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008U) /*!<FIFO request interrupt enable */
|
|
|
6913 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010U) /*!<Codec not ready interrupt enable */
|
|
|
6914 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020U) /*!<Anticipated frame synchronization detection interrupt enable */
|
|
|
6915 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040U) /*!<Late frame synchronization detection interrupt enable */
|
|
|
6916
|
|
|
6917 /******************** Bit definition for SAI_xSR register *******************/
|
|
|
6918 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001U) /*!<Overrun underrun */
|
|
|
6919 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002U) /*!<Mute detection */
|
|
|
6920 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004U) /*!<Wrong Clock Configuration */
|
|
|
6921 #define SAI_xSR_FREQ ((uint32_t)0x00000008U) /*!<FIFO request */
|
|
|
6922 #define SAI_xSR_CNRDY ((uint32_t)0x00000010U) /*!<Codec not ready */
|
|
|
6923 #define SAI_xSR_AFSDET ((uint32_t)0x00000020U) /*!<Anticipated frame synchronization detection */
|
|
|
6924 #define SAI_xSR_LFSDET ((uint32_t)0x00000040U) /*!<Late frame synchronization detection */
|
|
|
6925
|
|
|
6926 #define SAI_xSR_FLVL ((uint32_t)0x00070000U) /*!<FLVL[2:0] (FIFO Level Threshold) */
|
|
|
6927 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
6928 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
6929 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000U) /*!<Bit 2 */
|
|
|
6930
|
|
|
6931 /****************** Bit definition for SAI_xCLRFR register ******************/
|
|
|
6932 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001U) /*!<Clear Overrun underrun */
|
|
|
6933 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002U) /*!<Clear Mute detection */
|
|
|
6934 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004U) /*!<Clear Wrong Clock Configuration */
|
|
|
6935 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008U) /*!<Clear FIFO request */
|
|
|
6936 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010U) /*!<Clear Codec not ready */
|
|
|
6937 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020U) /*!<Clear Anticipated frame synchronization detection */
|
|
|
6938 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040U) /*!<Clear Late frame synchronization detection */
|
|
|
6939
|
|
|
6940 /****************** Bit definition for SAI_xDR register ******************/
|
|
|
6941 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFFU)
|
|
|
6942
|
|
|
6943 /******************************************************************************/
|
|
|
6944 /* */
|
|
|
6945 /* LCD Controller (LCD) */
|
|
|
6946 /* */
|
|
|
6947 /******************************************************************************/
|
|
|
6948
|
|
|
6949 /******************* Bit definition for LCD_CR register *********************/
|
|
|
6950 #define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */
|
|
|
6951 #define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */
|
|
|
6952
|
|
|
6953 #define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */
|
|
|
6954 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */
|
|
|
6955 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */
|
|
|
6956 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */
|
|
|
6957
|
|
|
6958 #define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */
|
|
|
6959 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */
|
|
|
6960 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */
|
|
|
6961
|
|
|
6962 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */
|
|
|
6963 #define LCD_CR_BUFEN ((uint32_t)0x00000100U) /*!< Voltage output buffer enable */
|
|
|
6964
|
|
|
6965 /******************* Bit definition for LCD_FCR register ********************/
|
|
|
6966 #define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */
|
|
|
6967 #define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */
|
|
|
6968 #define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */
|
|
|
6969
|
|
|
6970 #define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Pulse ON Duration) */
|
|
|
6971 #define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
|
|
|
6972 #define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
|
|
|
6973 #define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
|
|
|
6974
|
|
|
6975 #define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */
|
|
|
6976 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
|
|
|
6977 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
|
|
|
6978 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */
|
|
|
6979
|
|
|
6980 #define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */
|
|
|
6981 #define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
|
|
|
6982 #define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
|
|
|
6983 #define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
|
|
|
6984
|
|
|
6985 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */
|
|
|
6986 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
|
|
|
6987 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
|
|
|
6988 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
|
|
|
6989
|
|
|
6990 #define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */
|
|
|
6991 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
|
|
|
6992 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
|
|
|
6993
|
|
|
6994 #define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */
|
|
|
6995 #define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */
|
|
|
6996
|
|
|
6997 /******************* Bit definition for LCD_SR register *********************/
|
|
|
6998 #define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */
|
|
|
6999 #define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */
|
|
|
7000 #define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */
|
|
|
7001 #define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */
|
|
|
7002 #define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */
|
|
|
7003 #define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */
|
|
|
7004
|
|
|
7005 /******************* Bit definition for LCD_CLR register ********************/
|
|
|
7006 #define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */
|
|
|
7007 #define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */
|
|
|
7008
|
|
|
7009 /******************* Bit definition for LCD_RAM register ********************/
|
|
|
7010 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */
|
|
|
7011
|
|
|
7012 /******************************************************************************/
|
|
|
7013 /* */
|
|
|
7014 /* SDMMC Interface */
|
|
|
7015 /* */
|
|
|
7016 /******************************************************************************/
|
|
|
7017 /****************** Bit definition for SDMMC_POWER register ******************/
|
|
|
7018 #define SDMMC_POWER_PWRCTRL ((uint8_t)0x03U) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
|
|
|
7019 #define SDMMC_POWER_PWRCTRL_0 ((uint8_t)0x01U) /*!<Bit 0 */
|
|
|
7020 #define SDMMC_POWER_PWRCTRL_1 ((uint8_t)0x02U) /*!<Bit 1 */
|
|
|
7021
|
|
|
7022 /****************** Bit definition for SDMMC_CLKCR register ******************/
|
|
|
7023 #define SDMMC_CLKCR_CLKDIV ((uint16_t)0x00FFU) /*!<Clock divide factor */
|
|
|
7024 #define SDMMC_CLKCR_CLKEN ((uint16_t)0x0100U) /*!<Clock enable bit */
|
|
|
7025 #define SDMMC_CLKCR_PWRSAV ((uint16_t)0x0200U) /*!<Power saving configuration bit */
|
|
|
7026 #define SDMMC_CLKCR_BYPASS ((uint16_t)0x0400U) /*!<Clock divider bypass enable bit */
|
|
|
7027
|
|
|
7028 #define SDMMC_CLKCR_WIDBUS ((uint16_t)0x1800U) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
|
|
|
7029 #define SDMMC_CLKCR_WIDBUS_0 ((uint16_t)0x0800U) /*!<Bit 0 */
|
|
|
7030 #define SDMMC_CLKCR_WIDBUS_1 ((uint16_t)0x1000U) /*!<Bit 1 */
|
|
|
7031
|
|
|
7032 #define SDMMC_CLKCR_NEGEDGE ((uint16_t)0x2000U) /*!<SDMMC_CK dephasing selection bit */
|
|
|
7033 #define SDMMC_CLKCR_HWFC_EN ((uint16_t)0x4000U) /*!<HW Flow Control enable */
|
|
|
7034
|
|
|
7035 /******************* Bit definition for SDMMC_ARG register *******************/
|
|
|
7036 #define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFFU) /*!<Command argument */
|
|
|
7037
|
|
|
7038 /******************* Bit definition for SDMMC_CMD register *******************/
|
|
|
7039 #define SDMMC_CMD_CMDINDEX ((uint16_t)0x003FU) /*!<Command Index */
|
|
|
7040
|
|
|
7041 #define SDMMC_CMD_WAITRESP ((uint16_t)0x00C0U) /*!<WAITRESP[1:0] bits (Wait for response bits) */
|
|
|
7042 #define SDMMC_CMD_WAITRESP_0 ((uint16_t)0x0040U) /*!< Bit 0 */
|
|
|
7043 #define SDMMC_CMD_WAITRESP_1 ((uint16_t)0x0080U) /*!< Bit 1 */
|
|
|
7044
|
|
|
7045 #define SDMMC_CMD_WAITINT ((uint16_t)0x0100U) /*!<CPSM Waits for Interrupt Request */
|
|
|
7046 #define SDMMC_CMD_WAITPEND ((uint16_t)0x0200U) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
|
|
|
7047 #define SDMMC_CMD_CPSMEN ((uint16_t)0x0400U) /*!<Command path state machine (CPSM) Enable bit */
|
|
|
7048 #define SDMMC_CMD_SDIOSUSPEND ((uint16_t)0x0800U) /*!<SD I/O suspend command */
|
|
|
7049
|
|
|
7050 /***************** Bit definition for SDMMC_RESPCMD register *****************/
|
|
|
7051 #define SDMMC_RESPCMD_RESPCMD ((uint8_t)0x3FU) /*!<Response command index */
|
|
|
7052
|
|
|
7053 /****************** Bit definition for SDMMC_RESP0 register ******************/
|
|
|
7054 #define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
7055
|
|
|
7056 /****************** Bit definition for SDMMC_RESP1 register ******************/
|
|
|
7057 #define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
7058
|
|
|
7059 /****************** Bit definition for SDMMC_RESP2 register ******************/
|
|
|
7060 #define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
7061
|
|
|
7062 /****************** Bit definition for SDMMC_RESP3 register ******************/
|
|
|
7063 #define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
7064
|
|
|
7065 /****************** Bit definition for SDMMC_RESP4 register ******************/
|
|
|
7066 #define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
|
|
|
7067
|
|
|
7068 /****************** Bit definition for SDMMC_DTIMER register *****************/
|
|
|
7069 #define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFFU) /*!<Data timeout period. */
|
|
|
7070
|
|
|
7071 /****************** Bit definition for SDMMC_DLEN register *******************/
|
|
|
7072 #define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFFU) /*!<Data length value */
|
|
|
7073
|
|
|
7074 /****************** Bit definition for SDMMC_DCTRL register ******************/
|
|
|
7075 #define SDMMC_DCTRL_DTEN ((uint16_t)0x0001U) /*!<Data transfer enabled bit */
|
|
|
7076 #define SDMMC_DCTRL_DTDIR ((uint16_t)0x0002U) /*!<Data transfer direction selection */
|
|
|
7077 #define SDMMC_DCTRL_DTMODE ((uint16_t)0x0004U) /*!<Data transfer mode selection */
|
|
|
7078 #define SDMMC_DCTRL_DMAEN ((uint16_t)0x0008U) /*!<DMA enabled bit */
|
|
|
7079
|
|
|
7080 #define SDMMC_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0U) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
|
|
|
7081 #define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010U) /*!<Bit 0 */
|
|
|
7082 #define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020U) /*!<Bit 1 */
|
|
|
7083 #define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040U) /*!<Bit 2 */
|
|
|
7084 #define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080U) /*!<Bit 3 */
|
|
|
7085
|
|
|
7086 #define SDMMC_DCTRL_RWSTART ((uint16_t)0x0100U) /*!<Read wait start */
|
|
|
7087 #define SDMMC_DCTRL_RWSTOP ((uint16_t)0x0200U) /*!<Read wait stop */
|
|
|
7088 #define SDMMC_DCTRL_RWMOD ((uint16_t)0x0400U) /*!<Read wait mode */
|
|
|
7089 #define SDMMC_DCTRL_SDIOEN ((uint16_t)0x0800U) /*!<SD I/O enable functions */
|
|
|
7090
|
|
|
7091 /****************** Bit definition for SDMMC_DCOUNT register *****************/
|
|
|
7092 #define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFFU) /*!<Data count value */
|
|
|
7093
|
|
|
7094 /****************** Bit definition for SDMMC_STA register ********************/
|
|
|
7095 #define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001U) /*!<Command response received (CRC check failed) */
|
|
|
7096 #define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002U) /*!<Data block sent/received (CRC check failed) */
|
|
|
7097 #define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004U) /*!<Command response timeout */
|
|
|
7098 #define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008U) /*!<Data timeout */
|
|
|
7099 #define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010U) /*!<Transmit FIFO underrun error */
|
|
|
7100 #define SDMMC_STA_RXOVERR ((uint32_t)0x00000020U) /*!<Received FIFO overrun error */
|
|
|
7101 #define SDMMC_STA_CMDREND ((uint32_t)0x00000040U) /*!<Command response received (CRC check passed) */
|
|
|
7102 #define SDMMC_STA_CMDSENT ((uint32_t)0x00000080U) /*!<Command sent (no response required) */
|
|
|
7103 #define SDMMC_STA_DATAEND ((uint32_t)0x00000100U) /*!<Data end (data counter, SDIDCOUNT, is zero) */
|
|
|
7104 #define SDMMC_STA_STBITERR ((uint32_t)0x00000200U) /*!<Start bit not detected on all data signals in wide bus mode */
|
|
|
7105 #define SDMMC_STA_DBCKEND ((uint32_t)0x00000400U) /*!<Data block sent/received (CRC check passed) */
|
|
|
7106 #define SDMMC_STA_CMDACT ((uint32_t)0x00000800U) /*!<Command transfer in progress */
|
|
|
7107 #define SDMMC_STA_TXACT ((uint32_t)0x00001000U) /*!<Data transmit in progress */
|
|
|
7108 #define SDMMC_STA_RXACT ((uint32_t)0x00002000U) /*!<Data receive in progress */
|
|
|
7109 #define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000U) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
|
|
|
7110 #define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000U) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
|
|
|
7111 #define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000U) /*!<Transmit FIFO full */
|
|
|
7112 #define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000U) /*!<Receive FIFO full */
|
|
|
7113 #define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000U) /*!<Transmit FIFO empty */
|
|
|
7114 #define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000U) /*!<Receive FIFO empty */
|
|
|
7115 #define SDMMC_STA_TXDAVL ((uint32_t)0x00100000U) /*!<Data available in transmit FIFO */
|
|
|
7116 #define SDMMC_STA_RXDAVL ((uint32_t)0x00200000U) /*!<Data available in receive FIFO */
|
|
|
7117 #define SDMMC_STA_SDIOIT ((uint32_t)0x00400000U) /*!<SDIO interrupt received */
|
|
|
7118
|
|
|
7119 /******************* Bit definition for SDMMC_ICR register *******************/
|
|
|
7120 #define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001U) /*!<CCRCFAIL flag clear bit */
|
|
|
7121 #define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002U) /*!<DCRCFAIL flag clear bit */
|
|
|
7122 #define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004U) /*!<CTIMEOUT flag clear bit */
|
|
|
7123 #define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008U) /*!<DTIMEOUT flag clear bit */
|
|
|
7124 #define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010U) /*!<TXUNDERR flag clear bit */
|
|
|
7125 #define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020U) /*!<RXOVERR flag clear bit */
|
|
|
7126 #define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040U) /*!<CMDREND flag clear bit */
|
|
|
7127 #define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080U) /*!<CMDSENT flag clear bit */
|
|
|
7128 #define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100U) /*!<DATAEND flag clear bit */
|
|
|
7129 #define SDMMC_ICR_STBITERRC ((uint32_t)0x00000200U) /*!<STBITERR flag clear bit */
|
|
|
7130 #define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400U) /*!<DBCKEND flag clear bit */
|
|
|
7131 #define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000U) /*!<SDIOIT flag clear bit */
|
|
|
7132
|
|
|
7133 /****************** Bit definition for SDMMC_MASK register *******************/
|
|
|
7134 #define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001U) /*!<Command CRC Fail Interrupt Enable */
|
|
|
7135 #define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002U) /*!<Data CRC Fail Interrupt Enable */
|
|
|
7136 #define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004U) /*!<Command TimeOut Interrupt Enable */
|
|
|
7137 #define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008U) /*!<Data TimeOut Interrupt Enable */
|
|
|
7138 #define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010U) /*!<Tx FIFO UnderRun Error Interrupt Enable */
|
|
|
7139 #define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020U) /*!<Rx FIFO OverRun Error Interrupt Enable */
|
|
|
7140 #define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040U) /*!<Command Response Received Interrupt Enable */
|
|
|
7141 #define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080U) /*!<Command Sent Interrupt Enable */
|
|
|
7142 #define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100U) /*!<Data End Interrupt Enable */
|
|
|
7143 #define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400U) /*!<Data Block End Interrupt Enable */
|
|
|
7144 #define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800U) /*!<CCommand Acting Interrupt Enable */
|
|
|
7145 #define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000U) /*!<Data Transmit Acting Interrupt Enable */
|
|
|
7146 #define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000U) /*!<Data receive acting interrupt enabled */
|
|
|
7147 #define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000U) /*!<Tx FIFO Half Empty interrupt Enable */
|
|
|
7148 #define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000U) /*!<Rx FIFO Half Full interrupt Enable */
|
|
|
7149 #define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000U) /*!<Tx FIFO Full interrupt Enable */
|
|
|
7150 #define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000U) /*!<Rx FIFO Full interrupt Enable */
|
|
|
7151 #define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000U) /*!<Tx FIFO Empty interrupt Enable */
|
|
|
7152 #define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000U) /*!<Rx FIFO Empty interrupt Enable */
|
|
|
7153 #define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000U) /*!<Data available in Tx FIFO interrupt Enable */
|
|
|
7154 #define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000U) /*!<Data available in Rx FIFO interrupt Enable */
|
|
|
7155 #define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000U) /*!<SDIO Mode Interrupt Received interrupt Enable */
|
|
|
7156
|
|
|
7157 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
|
|
|
7158 #define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFFU) /*!<Remaining number of words to be written to or read from the FIFO */
|
|
|
7159
|
|
|
7160 /****************** Bit definition for SDMMC_FIFO register *******************/
|
|
|
7161 #define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFFU) /*!<Receive and transmit FIFO data */
|
|
|
7162
|
|
|
7163 /******************************************************************************/
|
|
|
7164 /* */
|
|
|
7165 /* Serial Peripheral Interface (SPI) */
|
|
|
7166 /* */
|
|
|
7167 /******************************************************************************/
|
|
|
7168 /******************* Bit definition for SPI_CR1 register ********************/
|
|
|
7169 #define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!<Clock Phase */
|
|
|
7170 #define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!<Clock Polarity */
|
|
|
7171 #define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!<Master Selection */
|
|
|
7172
|
|
|
7173 #define SPI_CR1_BR ((uint32_t)0x00000038U) /*!<BR[2:0] bits (Baud Rate Control) */
|
|
|
7174 #define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
|
|
|
7175 #define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
|
|
|
7176 #define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
|
|
|
7177
|
|
|
7178 #define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!<SPI Enable */
|
|
|
7179 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!<Frame Format */
|
|
|
7180 #define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!<Internal slave select */
|
|
|
7181 #define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!<Software slave management */
|
|
|
7182 #define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!<Receive only */
|
|
|
7183 #define SPI_CR1_CRCL ((uint32_t)0x00000800U) /*!< CRC Length */
|
|
|
7184 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!<Transmit CRC next */
|
|
|
7185 #define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!<Hardware CRC calculation enable */
|
|
|
7186 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!<Output enable in bidirectional mode */
|
|
|
7187 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!<Bidirectional data mode enable */
|
|
|
7188
|
|
|
7189 /******************* Bit definition for SPI_CR2 register ********************/
|
|
|
7190 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
|
|
|
7191 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
|
|
|
7192 #define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
|
|
|
7193 #define SPI_CR2_NSSP ((uint32_t)0x00000008U) /*!< NSS pulse management Enable */
|
|
|
7194 #define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */
|
|
|
7195 #define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
|
|
|
7196 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
|
|
|
7197 #define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
|
|
|
7198 #define SPI_CR2_DS ((uint32_t)0x00000F00U) /*!< DS[3:0] Data Size */
|
|
|
7199 #define SPI_CR2_DS_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
7200 #define SPI_CR2_DS_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
7201 #define SPI_CR2_DS_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
|
|
|
7202 #define SPI_CR2_DS_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
|
|
|
7203 #define SPI_CR2_FRXTH ((uint32_t)0x00001000U) /*!< FIFO reception Threshold */
|
|
|
7204 #define SPI_CR2_LDMARX ((uint32_t)0x00002000U) /*!< Last DMA transfer for reception */
|
|
|
7205 #define SPI_CR2_LDMATX ((uint32_t)0x00004000U) /*!< Last DMA transfer for transmission */
|
|
|
7206
|
|
|
7207 /******************** Bit definition for SPI_SR register ********************/
|
|
|
7208 #define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
|
|
|
7209 #define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
|
|
|
7210 #define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
|
|
|
7211 #define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
|
|
|
7212 #define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
|
|
|
7213 #define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
|
|
|
7214 #define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
|
|
|
7215 #define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
|
|
|
7216 #define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */
|
|
|
7217 #define SPI_SR_FRLVL ((uint32_t)0x00000600U) /*!< FIFO Reception Level */
|
|
|
7218 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
|
|
|
7219 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
|
|
|
7220 #define SPI_SR_FTLVL ((uint32_t)0x00001800U) /*!< FIFO Transmission Level */
|
|
|
7221 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
|
|
|
7222 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
|
|
|
7223
|
|
|
7224 /******************** Bit definition for SPI_DR register ********************/
|
|
|
7225 #define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!<Data Register */
|
|
|
7226
|
|
|
7227 /******************* Bit definition for SPI_CRCPR register ******************/
|
|
|
7228 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!<CRC polynomial register */
|
|
|
7229
|
|
|
7230 /****************** Bit definition for SPI_RXCRCR register ******************/
|
|
|
7231 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!<Rx CRC Register */
|
|
|
7232
|
|
|
7233 /****************** Bit definition for SPI_TXCRCR register ******************/
|
|
|
7234 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!<Tx CRC Register */
|
|
|
7235
|
|
|
7236 /******************************************************************************/
|
|
|
7237 /* */
|
|
|
7238 /* QUADSPI */
|
|
|
7239 /* */
|
|
|
7240 /******************************************************************************/
|
|
|
7241 /***************** Bit definition for QUADSPI_CR register *******************/
|
|
|
7242 #define QUADSPI_CR_EN ((uint32_t)0x00000001U) /*!< Enable */
|
|
|
7243 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002U) /*!< Abort request */
|
|
|
7244 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004U) /*!< DMA Enable */
|
|
|
7245 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008U) /*!< Timeout Counter Enable */
|
|
|
7246 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010U) /*!< Sample Shift */
|
|
|
7247 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00U) /*!< FTHRES[3:0] FIFO Level */
|
|
|
7248 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000U) /*!< Transfer Error Interrupt Enable */
|
|
|
7249 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000U) /*!< Transfer Complete Interrupt Enable */
|
|
|
7250 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000U) /*!< FIFO Threshold Interrupt Enable */
|
|
|
7251 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000U) /*!< Status Match Interrupt Enable */
|
|
|
7252 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000U) /*!< TimeOut Interrupt Enable */
|
|
|
7253 #define QUADSPI_CR_APMS ((uint32_t)0x00400000U) /*!< Automatic Polling Mode Stop */
|
|
|
7254 #define QUADSPI_CR_PMM ((uint32_t)0x00800000U) /*!< Polling Match Mode */
|
|
|
7255 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000U) /*!< PRESCALER[7:0] Clock prescaler */
|
|
|
7256
|
|
|
7257 /***************** Bit definition for QUADSPI_DCR register ******************/
|
|
|
7258 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001U) /*!< Mode 0 / Mode 3 */
|
|
|
7259 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700U) /*!< CSHT[2:0]: ChipSelect High Time */
|
|
|
7260 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
7261 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
7262 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
|
|
|
7263 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000U) /*!< FSIZE[4:0]: Flash Size */
|
|
|
7264
|
|
|
7265 /****************** Bit definition for QUADSPI_SR register *******************/
|
|
|
7266 #define QUADSPI_SR_TEF ((uint32_t)0x00000001U) /*!< Transfer Error Flag */
|
|
|
7267 #define QUADSPI_SR_TCF ((uint32_t)0x00000002U) /*!< Transfer Complete Flag */
|
|
|
7268 #define QUADSPI_SR_FTF ((uint32_t)0x00000004U) /*!< FIFO Threshlod Flag */
|
|
|
7269 #define QUADSPI_SR_SMF ((uint32_t)0x00000008U) /*!< Status Match Flag */
|
|
|
7270 #define QUADSPI_SR_TOF ((uint32_t)0x00000010U) /*!< Timeout Flag */
|
|
|
7271 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020U) /*!< Busy */
|
|
|
7272 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00U) /*!< FIFO Threshlod Flag */
|
|
|
7273
|
|
|
7274 /****************** Bit definition for QUADSPI_FCR register ******************/
|
|
|
7275 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001U) /*!< Clear Transfer Error Flag */
|
|
|
7276 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002U) /*!< Clear Transfer Complete Flag */
|
|
|
7277 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008U) /*!< Clear Status Match Flag */
|
|
|
7278 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010U) /*!< Clear Timeout Flag */
|
|
|
7279
|
|
|
7280 /****************** Bit definition for QUADSPI_DLR register ******************/
|
|
|
7281 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFFU) /*!< DL[31:0]: Data Length */
|
|
|
7282
|
|
|
7283 /****************** Bit definition for QUADSPI_CCR register ******************/
|
|
|
7284 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FFU) /*!< INSTRUCTION[7:0]: Instruction */
|
|
|
7285 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300U) /*!< IMODE[1:0]: Instruction Mode */
|
|
|
7286 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
7287 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
7288 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00U) /*!< ADMODE[1:0]: Address Mode */
|
|
|
7289 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
|
|
|
7290 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
|
|
|
7291 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000U) /*!< ADSIZE[1:0]: Address Size */
|
|
|
7292 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
|
|
|
7293 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
|
|
|
7294 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000U) /*!< ABMODE[1:0]: Alternate Bytes Mode */
|
|
|
7295 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000U) /*!< Bit 0 */
|
|
|
7296 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000U) /*!< Bit 1 */
|
|
|
7297 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000U) /*!< ABSIZE[1:0]: Instruction Mode */
|
|
|
7298 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
|
|
|
7299 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
|
|
|
7300 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000U) /*!< DCYC[4:0]: Dummy Cycles */
|
|
|
7301 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000U) /*!< DMODE[1:0]: Data Mode */
|
|
|
7302 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
|
|
|
7303 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
|
|
|
7304 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000U) /*!< FMODE[1:0]: Functional Mode */
|
|
|
7305 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
|
|
|
7306 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
|
|
|
7307 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000U) /*!< SIOO: Send Instruction Only Once Mode */
|
|
|
7308 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000U) /*!< DDRM: Double Data Rate Mode */
|
|
|
7309
|
|
|
7310 /****************** Bit definition for QUADSPI_AR register *******************/
|
|
|
7311 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFFU) /*!< ADDRESS[31:0]: Address */
|
|
|
7312
|
|
|
7313 /****************** Bit definition for QUADSPI_ABR register ******************/
|
|
|
7314 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFFU) /*!< ALTERNATE[31:0]: Alternate Bytes */
|
|
|
7315
|
|
|
7316 /****************** Bit definition for QUADSPI_DR register *******************/
|
|
|
7317 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFFU) /*!< DATA[31:0]: Data */
|
|
|
7318
|
|
|
7319 /****************** Bit definition for QUADSPI_PSMKR register ****************/
|
|
|
7320 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFFU) /*!< MASK[31:0]: Status Mask */
|
|
|
7321
|
|
|
7322 /****************** Bit definition for QUADSPI_PSMAR register ****************/
|
|
|
7323 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFFU) /*!< MATCH[31:0]: Status Match */
|
|
|
7324
|
|
|
7325 /****************** Bit definition for QUADSPI_PIR register *****************/
|
|
|
7326 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFFU) /*!< INTERVAL[15:0]: Polling Interval */
|
|
|
7327
|
|
|
7328 /****************** Bit definition for QUADSPI_LPTR register *****************/
|
|
|
7329 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< TIMEOUT[15:0]: Timeout period */
|
|
|
7330
|
|
|
7331 /******************************************************************************/
|
|
|
7332 /* */
|
|
|
7333 /* SYSCFG */
|
|
|
7334 /* */
|
|
|
7335 /******************************************************************************/
|
|
|
7336 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
|
|
|
7337 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
|
|
|
7338 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001U)
|
|
|
7339 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002U)
|
|
|
7340 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004U)
|
|
|
7341
|
|
|
7342 #define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100U) /*!< Flash Bank mode selection */
|
|
|
7343
|
|
|
7344
|
|
|
7345 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
|
|
|
7346 #define SYSCFG_CFGR1_FWDIS ((uint32_t)0x00000001U) /*!< FIREWALL access enable*/
|
|
|
7347 #define SYSCFG_CFGR1_BOOSTEN ((uint32_t)0x00000100U) /*!< I/O analog switch voltage booster enable */
|
|
|
7348 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000U) /*!< I2C PB6 Fast mode plus */
|
|
|
7349 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000U) /*!< I2C PB7 Fast mode plus */
|
|
|
7350 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000U) /*!< I2C PB8 Fast mode plus */
|
|
|
7351 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000U) /*!< I2C PB9 Fast mode plus */
|
|
|
7352 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000U) /*!< I2C1 Fast mode plus */
|
|
|
7353 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000U) /*!< I2C2 Fast mode plus */
|
|
|
7354 #define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x00400000U) /*!< I2C3 Fast mode plus */
|
|
|
7355 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000U) /*!< Invalid operation Interrupt enable */
|
|
|
7356 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000U) /*!< Divide-by-zero Interrupt enable */
|
|
|
7357 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000U) /*!< Underflow Interrupt enable */
|
|
|
7358 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000U) /*!< Overflow Interrupt enable */
|
|
|
7359 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000U) /*!< Input denormal Interrupt enable */
|
|
|
7360 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
|
|
|
7361
|
|
|
7362 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
|
|
7363 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x00000007U) /*!<EXTI 0 configuration */
|
|
|
7364 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00000070U) /*!<EXTI 1 configuration */
|
|
|
7365 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000700U) /*!<EXTI 2 configuration */
|
|
|
7366 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x00007000U) /*!<EXTI 3 configuration */
|
|
|
7367 /**
|
|
|
7368 * @brief EXTI0 configuration
|
|
|
7369 */
|
|
|
7370 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!<PA[0] pin */
|
|
|
7371 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!<PB[0] pin */
|
|
|
7372 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!<PC[0] pin */
|
|
|
7373 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003U) /*!<PD[0] pin */
|
|
|
7374 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004U) /*!<PE[0] pin */
|
|
|
7375 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005U) /*!<PF[0] pin */
|
|
|
7376 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006U) /*!<PG[0] pin */
|
|
|
7377 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007U) /*!<PH[0] pin */
|
|
|
7378
|
|
|
7379
|
|
|
7380 /**
|
|
|
7381 * @brief EXTI1 configuration
|
|
|
7382 */
|
|
|
7383 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!<PA[1] pin */
|
|
|
7384 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!<PB[1] pin */
|
|
|
7385 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!<PC[1] pin */
|
|
|
7386 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030U) /*!<PD[1] pin */
|
|
|
7387 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040U) /*!<PE[1] pin */
|
|
|
7388 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050U) /*!<PF[1] pin */
|
|
|
7389 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060U) /*!<PG[1] pin */
|
|
|
7390 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070U) /*!<PH[1] pin */
|
|
|
7391
|
|
|
7392 /**
|
|
|
7393 * @brief EXTI2 configuration
|
|
|
7394 */
|
|
|
7395 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!<PA[2] pin */
|
|
|
7396 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!<PB[2] pin */
|
|
|
7397 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!<PC[2] pin */
|
|
|
7398 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!<PD[2] pin */
|
|
|
7399 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400U) /*!<PE[2] pin */
|
|
|
7400 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500U) /*!<PF[2] pin */
|
|
|
7401 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600U) /*!<PG[2] pin */
|
|
|
7402
|
|
|
7403
|
|
|
7404 /**
|
|
|
7405 * @brief EXTI3 configuration
|
|
|
7406 */
|
|
|
7407 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!<PA[3] pin */
|
|
|
7408 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!<PB[3] pin */
|
|
|
7409 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!<PC[3] pin */
|
|
|
7410 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000U) /*!<PD[3] pin */
|
|
|
7411 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000U) /*!<PE[3] pin */
|
|
|
7412 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000U) /*!<PF[3] pin */
|
|
|
7413 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000U) /*!<PG[3] pin */
|
|
|
7414
|
|
|
7415
|
|
|
7416 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
|
|
7417 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x00000007U) /*!<EXTI 4 configuration */
|
|
|
7418 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00000070U) /*!<EXTI 5 configuration */
|
|
|
7419 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000700U) /*!<EXTI 6 configuration */
|
|
|
7420 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x00007000U) /*!<EXTI 7 configuration */
|
|
|
7421 /**
|
|
|
7422 * @brief EXTI4 configuration
|
|
|
7423 */
|
|
|
7424 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!<PA[4] pin */
|
|
|
7425 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!<PB[4] pin */
|
|
|
7426 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!<PC[4] pin */
|
|
|
7427 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003U) /*!<PD[4] pin */
|
|
|
7428 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004U) /*!<PE[4] pin */
|
|
|
7429 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005U) /*!<PF[4] pin */
|
|
|
7430 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006U) /*!<PG[4] pin */
|
|
|
7431
|
|
|
7432 /**
|
|
|
7433 * @brief EXTI5 configuration
|
|
|
7434 */
|
|
|
7435 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!<PA[5] pin */
|
|
|
7436 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!<PB[5] pin */
|
|
|
7437 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!<PC[5] pin */
|
|
|
7438 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030U) /*!<PD[5] pin */
|
|
|
7439 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040U) /*!<PE[5] pin */
|
|
|
7440 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050U) /*!<PF[5] pin */
|
|
|
7441 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060U) /*!<PG[5] pin */
|
|
|
7442
|
|
|
7443 /**
|
|
|
7444 * @brief EXTI6 configuration
|
|
|
7445 */
|
|
|
7446 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!<PA[6] pin */
|
|
|
7447 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!<PB[6] pin */
|
|
|
7448 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!<PC[6] pin */
|
|
|
7449 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300U) /*!<PD[6] pin */
|
|
|
7450 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400U) /*!<PE[6] pin */
|
|
|
7451 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500U) /*!<PF[6] pin */
|
|
|
7452 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600U) /*!<PG[6] pin */
|
|
|
7453
|
|
|
7454 /**
|
|
|
7455 * @brief EXTI7 configuration
|
|
|
7456 */
|
|
|
7457 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!<PA[7] pin */
|
|
|
7458 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!<PB[7] pin */
|
|
|
7459 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!<PC[7] pin */
|
|
|
7460 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000U) /*!<PD[7] pin */
|
|
|
7461 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000U) /*!<PE[7] pin */
|
|
|
7462 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000U) /*!<PF[7] pin */
|
|
|
7463 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000U) /*!<PG[7] pin */
|
|
|
7464
|
|
|
7465
|
|
|
7466 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
|
|
7467 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x00000007U) /*!<EXTI 8 configuration */
|
|
|
7468 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00000070U) /*!<EXTI 9 configuration */
|
|
|
7469 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000700U) /*!<EXTI 10 configuration */
|
|
|
7470 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x00007000U) /*!<EXTI 11 configuration */
|
|
|
7471
|
|
|
7472 /**
|
|
|
7473 * @brief EXTI8 configuration
|
|
|
7474 */
|
|
|
7475 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!<PA[8] pin */
|
|
|
7476 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!<PB[8] pin */
|
|
|
7477 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!<PC[8] pin */
|
|
|
7478 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003U) /*!<PD[8] pin */
|
|
|
7479 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004U) /*!<PE[8] pin */
|
|
|
7480 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005U) /*!<PF[8] pin */
|
|
|
7481 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006U) /*!<PG[8] pin */
|
|
|
7482
|
|
|
7483 /**
|
|
|
7484 * @brief EXTI9 configuration
|
|
|
7485 */
|
|
|
7486 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!<PA[9] pin */
|
|
|
7487 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!<PB[9] pin */
|
|
|
7488 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!<PC[9] pin */
|
|
|
7489 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030U) /*!<PD[9] pin */
|
|
|
7490 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040U) /*!<PE[9] pin */
|
|
|
7491 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050U) /*!<PF[9] pin */
|
|
|
7492 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060U) /*!<PG[9] pin */
|
|
|
7493
|
|
|
7494 /**
|
|
|
7495 * @brief EXTI10 configuration
|
|
|
7496 */
|
|
|
7497 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!<PA[10] pin */
|
|
|
7498 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!<PB[10] pin */
|
|
|
7499 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!<PC[10] pin */
|
|
|
7500 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300U) /*!<PD[10] pin */
|
|
|
7501 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400U) /*!<PE[10] pin */
|
|
|
7502 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500U) /*!<PF[10] pin */
|
|
|
7503 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600U) /*!<PG[10] pin */
|
|
|
7504
|
|
|
7505 /**
|
|
|
7506 * @brief EXTI11 configuration
|
|
|
7507 */
|
|
|
7508 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!<PA[11] pin */
|
|
|
7509 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!<PB[11] pin */
|
|
|
7510 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!<PC[11] pin */
|
|
|
7511 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000U) /*!<PD[11] pin */
|
|
|
7512 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000U) /*!<PE[11] pin */
|
|
|
7513 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000U) /*!<PF[11] pin */
|
|
|
7514 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000U) /*!<PG[11] pin */
|
|
|
7515
|
|
|
7516 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
|
|
7517 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x00000007U) /*!<EXTI 12 configuration */
|
|
|
7518 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00000070U) /*!<EXTI 13 configuration */
|
|
|
7519 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000700U) /*!<EXTI 14 configuration */
|
|
|
7520 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x00007000U) /*!<EXTI 15 configuration */
|
|
|
7521 /**
|
|
|
7522 * @brief EXTI12 configuration
|
|
|
7523 */
|
|
|
7524 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!<PA[12] pin */
|
|
|
7525 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!<PB[12] pin */
|
|
|
7526 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!<PC[12] pin */
|
|
|
7527 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003U) /*!<PD[12] pin */
|
|
|
7528 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004U) /*!<PE[12] pin */
|
|
|
7529 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005U) /*!<PF[12] pin */
|
|
|
7530 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006U) /*!<PG[12] pin */
|
|
|
7531
|
|
|
7532 /**
|
|
|
7533 * @brief EXTI13 configuration
|
|
|
7534 */
|
|
|
7535 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!<PA[13] pin */
|
|
|
7536 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!<PB[13] pin */
|
|
|
7537 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!<PC[13] pin */
|
|
|
7538 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030U) /*!<PD[13] pin */
|
|
|
7539 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040U) /*!<PE[13] pin */
|
|
|
7540 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050U) /*!<PF[13] pin */
|
|
|
7541 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060U) /*!<PG[13] pin */
|
|
|
7542
|
|
|
7543 /**
|
|
|
7544 * @brief EXTI14 configuration
|
|
|
7545 */
|
|
|
7546 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!<PA[14] pin */
|
|
|
7547 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!<PB[14] pin */
|
|
|
7548 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!<PC[14] pin */
|
|
|
7549 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300U) /*!<PD[14] pin */
|
|
|
7550 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400U) /*!<PE[14] pin */
|
|
|
7551 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500U) /*!<PF[14] pin */
|
|
|
7552 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600U) /*!<PG[14] pin */
|
|
|
7553
|
|
|
7554 /**
|
|
|
7555 * @brief EXTI15 configuration
|
|
|
7556 */
|
|
|
7557 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!<PA[15] pin */
|
|
|
7558 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!<PB[15] pin */
|
|
|
7559 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!<PC[15] pin */
|
|
|
7560 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000U) /*!<PD[15] pin */
|
|
|
7561 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000U) /*!<PE[15] pin */
|
|
|
7562 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000U) /*!<PF[15] pin */
|
|
|
7563 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000U) /*!<PG[15] pin */
|
|
|
7564
|
|
|
7565 /****************** Bit definition for SYSCFG_SCSR register ****************/
|
|
|
7566 #define SYSCFG_SCSR_SRAM2ER ((uint32_t)0x00000001U) /*!< SRAM2 Erase Request */
|
|
|
7567 #define SYSCFG_SCSR_SRAM2BSY ((uint32_t)0x00000002U) /*!< SRAM2 Erase Ongoing */
|
|
|
7568
|
|
|
7569 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
|
|
|
7570 #define SYSCFG_CFGR2_CLL ((uint32_t)0x00000001U) /*!< Core Lockup Lock */
|
|
|
7571 #define SYSCFG_CFGR2_SPL ((uint32_t)0x00000002U) /*!< SRAM Parity Lock*/
|
|
|
7572 #define SYSCFG_CFGR2_PVDL ((uint32_t)0x00000004U) /*!< PVD Lock */
|
|
|
7573 #define SYSCFG_CFGR2_ECCL ((uint32_t)0x00000008U) /*!< ECC Lock*/
|
|
|
7574 #define SYSCFG_CFGR2_SPF ((uint32_t)0x00000100U) /*!< SRAM Parity Flag */
|
|
|
7575
|
|
|
7576 /****************** Bit definition for SYSCFG_SWPR register ****************/
|
|
|
7577 #define SYSCFG_SWPR_PAGE0 ((uint32_t)0x00000001U) /*!< SRAM2 Write protection page 0 */
|
|
|
7578 #define SYSCFG_SWPR_PAGE1 ((uint32_t)0x00000002U) /*!< SRAM2 Write protection page 1 */
|
|
|
7579 #define SYSCFG_SWPR_PAGE2 ((uint32_t)0x00000004U) /*!< SRAM2 Write protection page 2 */
|
|
|
7580 #define SYSCFG_SWPR_PAGE3 ((uint32_t)0x00000008U) /*!< SRAM2 Write protection page 3 */
|
|
|
7581 #define SYSCFG_SWPR_PAGE4 ((uint32_t)0x00000010U) /*!< SRAM2 Write protection page 4 */
|
|
|
7582 #define SYSCFG_SWPR_PAGE5 ((uint32_t)0x00000020U) /*!< SRAM2 Write protection page 5 */
|
|
|
7583 #define SYSCFG_SWPR_PAGE6 ((uint32_t)0x00000040U) /*!< SRAM2 Write protection page 6 */
|
|
|
7584 #define SYSCFG_SWPR_PAGE7 ((uint32_t)0x00000080U) /*!< SRAM2 Write protection page 7 */
|
|
|
7585 #define SYSCFG_SWPR_PAGE8 ((uint32_t)0x00000100U) /*!< SRAM2 Write protection page 8 */
|
|
|
7586 #define SYSCFG_SWPR_PAGE9 ((uint32_t)0x00000200U) /*!< SRAM2 Write protection page 9 */
|
|
|
7587 #define SYSCFG_SWPR_PAGE10 ((uint32_t)0x00000400U) /*!< SRAM2 Write protection page 10*/
|
|
|
7588 #define SYSCFG_SWPR_PAGE11 ((uint32_t)0x00000800U) /*!< SRAM2 Write protection page 11*/
|
|
|
7589 #define SYSCFG_SWPR_PAGE12 ((uint32_t)0x00001000U) /*!< SRAM2 Write protection page 12*/
|
|
|
7590 #define SYSCFG_SWPR_PAGE13 ((uint32_t)0x00002000U) /*!< SRAM2 Write protection page 13*/
|
|
|
7591 #define SYSCFG_SWPR_PAGE14 ((uint32_t)0x00004000U) /*!< SRAM2 Write protection page 14*/
|
|
|
7592 #define SYSCFG_SWPR_PAGE15 ((uint32_t)0x00008000U) /*!< SRAM2 Write protection page 15*/
|
|
|
7593 #define SYSCFG_SWPR_PAGE16 ((uint32_t)0x00010000U) /*!< SRAM2 Write protection page 16*/
|
|
|
7594 #define SYSCFG_SWPR_PAGE17 ((uint32_t)0x00020000U) /*!< SRAM2 Write protection page 17*/
|
|
|
7595 #define SYSCFG_SWPR_PAGE18 ((uint32_t)0x00040000U) /*!< SRAM2 Write protection page 18*/
|
|
|
7596 #define SYSCFG_SWPR_PAGE19 ((uint32_t)0x00080000U) /*!< SRAM2 Write protection page 19*/
|
|
|
7597 #define SYSCFG_SWPR_PAGE20 ((uint32_t)0x00100000U) /*!< SRAM2 Write protection page 20*/
|
|
|
7598 #define SYSCFG_SWPR_PAGE21 ((uint32_t)0x00200000U) /*!< SRAM2 Write protection page 21*/
|
|
|
7599 #define SYSCFG_SWPR_PAGE22 ((uint32_t)0x00400000U) /*!< SRAM2 Write protection page 22*/
|
|
|
7600 #define SYSCFG_SWPR_PAGE23 ((uint32_t)0x00800000U) /*!< SRAM2 Write protection page 23*/
|
|
|
7601 #define SYSCFG_SWPR_PAGE24 ((uint32_t)0x01000000U) /*!< SRAM2 Write protection page 24*/
|
|
|
7602 #define SYSCFG_SWPR_PAGE25 ((uint32_t)0x02000000U) /*!< SRAM2 Write protection page 25*/
|
|
|
7603 #define SYSCFG_SWPR_PAGE26 ((uint32_t)0x04000000U) /*!< SRAM2 Write protection page 26*/
|
|
|
7604 #define SYSCFG_SWPR_PAGE27 ((uint32_t)0x08000000U) /*!< SRAM2 Write protection page 27*/
|
|
|
7605 #define SYSCFG_SWPR_PAGE28 ((uint32_t)0x10000000U) /*!< SRAM2 Write protection page 28*/
|
|
|
7606 #define SYSCFG_SWPR_PAGE29 ((uint32_t)0x20000000U) /*!< SRAM2 Write protection page 29*/
|
|
|
7607 #define SYSCFG_SWPR_PAGE30 ((uint32_t)0x40000000U) /*!< SRAM2 Write protection page 30*/
|
|
|
7608 #define SYSCFG_SWPR_PAGE31 ((uint32_t)0x80000000U) /*!< SRAM2 Write protection page 31*/
|
|
|
7609
|
|
|
7610 /****************** Bit definition for SYSCFG_SKR register ****************/
|
|
|
7611 #define SYSCFG_SKR_KEY ((uint32_t)0x000000FFU) /*!< SRAM2 write protection key for software erase */
|
|
|
7612
|
|
|
7613
|
|
|
7614
|
|
|
7615
|
|
|
7616 /******************************************************************************/
|
|
|
7617 /* */
|
|
|
7618 /* TIM */
|
|
|
7619 /* */
|
|
|
7620 /******************************************************************************/
|
|
|
7621 /******************* Bit definition for TIM_CR1 register ********************/
|
|
|
7622 #define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
|
|
|
7623 #define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
|
|
|
7624 #define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
|
|
|
7625 #define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
|
|
|
7626 #define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
|
|
|
7627
|
|
|
7628 #define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
|
|
|
7629 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
|
|
|
7630 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
|
|
|
7631
|
|
|
7632 #define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
|
|
|
7633
|
|
|
7634 #define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
|
|
|
7635 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
7636 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
7637
|
|
|
7638 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800U) /*!<Update interrupt flag remap */
|
|
|
7639
|
|
|
7640 /******************* Bit definition for TIM_CR2 register ********************/
|
|
|
7641 #define TIM_CR2_CCPC ((uint32_t)0x00000001U) /*!<Capture/Compare Preloaded Control */
|
|
|
7642 #define TIM_CR2_CCUS ((uint32_t)0x00000004U) /*!<Capture/Compare Control Update Selection */
|
|
|
7643 #define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
|
|
|
7644
|
|
|
7645 #define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
|
|
|
7646 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
7647 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
7648 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
7649
|
|
|
7650 #define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
|
|
|
7651 #define TIM_CR2_OIS1 ((uint32_t)0x00000100U) /*!<Output Idle state 1 (OC1 output) */
|
|
|
7652 #define TIM_CR2_OIS1N ((uint32_t)0x00000200U) /*!<Output Idle state 1 (OC1N output) */
|
|
|
7653 #define TIM_CR2_OIS2 ((uint32_t)0x00000400U) /*!<Output Idle state 2 (OC2 output) */
|
|
|
7654 #define TIM_CR2_OIS2N ((uint32_t)0x00000800U) /*!<Output Idle state 2 (OC2N output) */
|
|
|
7655 #define TIM_CR2_OIS3 ((uint32_t)0x00001000U) /*!<Output Idle state 3 (OC3 output) */
|
|
|
7656 #define TIM_CR2_OIS3N ((uint32_t)0x00002000U) /*!<Output Idle state 3 (OC3N output) */
|
|
|
7657 #define TIM_CR2_OIS4 ((uint32_t)0x00004000U) /*!<Output Idle state 4 (OC4 output) */
|
|
|
7658 #define TIM_CR2_OIS5 ((uint32_t)0x00010000U) /*!<Output Idle state 5 (OC5 output) */
|
|
|
7659 #define TIM_CR2_OIS6 ((uint32_t)0x00040000U) /*!<Output Idle state 6 (OC6 output) */
|
|
|
7660
|
|
|
7661 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000U) /*!<MMS[2:0] bits (Master Mode Selection) */
|
|
|
7662 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
|
|
|
7663 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
|
|
|
7664 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
|
|
|
7665 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000U) /*!<Bit 2 */
|
|
|
7666
|
|
|
7667 /******************* Bit definition for TIM_SMCR register *******************/
|
|
|
7668 #define TIM_SMCR_SMS ((uint32_t)0x00010007U) /*!<SMS[2:0] bits (Slave mode selection) */
|
|
|
7669 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
7670 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
7671 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
7672 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
7673
|
|
|
7674 #define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
|
|
|
7675
|
|
|
7676 #define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
|
|
|
7677 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
7678 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
7679 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
7680
|
|
|
7681 #define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
|
|
|
7682
|
|
|
7683 #define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
|
|
|
7684 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
7685 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
7686 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
7687 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
7688
|
|
|
7689 #define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
|
|
|
7690 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
7691 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
7692
|
|
|
7693 #define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
|
|
|
7694 #define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
|
|
|
7695
|
|
|
7696 /******************* Bit definition for TIM_DIER register *******************/
|
|
|
7697 #define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
|
|
|
7698 #define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
|
|
|
7699 #define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
|
|
|
7700 #define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
|
|
|
7701 #define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
|
|
|
7702 #define TIM_DIER_COMIE ((uint32_t)0x00000020U) /*!<COM interrupt enable */
|
|
|
7703 #define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
|
|
|
7704 #define TIM_DIER_BIE ((uint32_t)0x00000080U) /*!<Break interrupt enable */
|
|
|
7705 #define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
|
|
|
7706 #define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
|
|
|
7707 #define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
|
|
|
7708 #define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
|
|
|
7709 #define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
|
|
|
7710 #define TIM_DIER_COMDE ((uint32_t)0x00002000U) /*!<COM DMA request enable */
|
|
|
7711 #define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
|
|
|
7712
|
|
|
7713 /******************** Bit definition for TIM_SR register ********************/
|
|
|
7714 #define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
|
|
|
7715 #define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
|
|
|
7716 #define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
|
|
|
7717 #define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
|
|
|
7718 #define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
|
|
|
7719 #define TIM_SR_COMIF ((uint32_t)0x00000020U) /*!<COM interrupt Flag */
|
|
|
7720 #define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
|
|
|
7721 #define TIM_SR_BIF ((uint32_t)0x00000080U) /*!<Break interrupt Flag */
|
|
|
7722 #define TIM_SR_B2IF ((uint32_t)0x00000100U) /*!<Break 2 interrupt Flag */
|
|
|
7723 #define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
|
|
|
7724 #define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
|
|
|
7725 #define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
|
|
|
7726 #define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
|
|
|
7727 #define TIM_SR_SBIF ((uint32_t)0x00002000U) /*!<System Break interrupt Flag */
|
|
|
7728 #define TIM_SR_CC5IF ((uint32_t)0x00010000U) /*!<Capture/Compare 5 interrupt Flag */
|
|
|
7729 #define TIM_SR_CC6IF ((uint32_t)0x00020000U) /*!<Capture/Compare 6 interrupt Flag */
|
|
|
7730
|
|
|
7731
|
|
|
7732 /******************* Bit definition for TIM_EGR register ********************/
|
|
|
7733 #define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
|
|
|
7734 #define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
|
|
|
7735 #define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
|
|
|
7736 #define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
|
|
|
7737 #define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
|
|
|
7738 #define TIM_EGR_COMG ((uint32_t)0x00000020U) /*!<Capture/Compare Control Update Generation */
|
|
|
7739 #define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
|
|
|
7740 #define TIM_EGR_BG ((uint32_t)0x00000080U) /*!<Break Generation */
|
|
|
7741 #define TIM_EGR_B2G ((uint32_t)0x00000100U) /*!<Break 2 Generation */
|
|
|
7742
|
|
|
7743
|
|
|
7744 /****************** Bit definition for TIM_CCMR1 register *******************/
|
|
|
7745 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
|
|
|
7746 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
7747 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
7748
|
|
|
7749 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
|
|
|
7750 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
|
|
|
7751
|
|
|
7752 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
|
|
|
7753 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
7754 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
7755 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
7756 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
7757
|
|
|
7758 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1 Clear Enable */
|
|
|
7759
|
|
|
7760 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
|
|
|
7761 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
7762 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
7763
|
|
|
7764 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
|
|
|
7765 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
|
|
|
7766
|
|
|
7767 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
|
|
|
7768 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
7769 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
7770 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
7771 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
|
|
|
7772
|
|
|
7773 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
|
|
|
7774
|
|
|
7775 /*----------------------------------------------------------------------------*/
|
|
|
7776 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
|
|
|
7777 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
7778 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
7779
|
|
|
7780 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
|
|
|
7781 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
7782 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
7783 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
7784 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
|
|
|
7785
|
|
|
7786 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
|
|
|
7787 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
|
|
|
7788 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
|
|
|
7789
|
|
|
7790 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
|
|
|
7791 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
7792 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
7793 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
7794 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
|
|
|
7795
|
|
|
7796 /****************** Bit definition for TIM_CCMR2 register *******************/
|
|
|
7797 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
|
|
|
7798 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
7799 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
7800
|
|
|
7801 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
|
|
|
7802 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
|
|
|
7803
|
|
|
7804 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
|
|
7805 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
7806 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
7807 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
7808 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
7809
|
|
|
7810 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
|
|
|
7811
|
|
|
7812 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
|
|
|
7813 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
7814 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
7815
|
|
|
7816 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
|
|
|
7817 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
|
|
|
7818
|
|
|
7819 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
|
|
7820 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
7821 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
7822 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
7823 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
|
|
|
7824
|
|
|
7825 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
|
|
|
7826
|
|
|
7827 /*----------------------------------------------------------------------------*/
|
|
|
7828 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
|
|
|
7829 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
7830 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
7831
|
|
|
7832 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
|
|
|
7833 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
7834 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
7835 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
7836 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
|
|
|
7837
|
|
|
7838 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
|
|
|
7839 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
|
|
|
7840 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
|
|
|
7841
|
|
|
7842 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
|
|
|
7843 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
7844 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
7845 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
7846 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
|
|
|
7847
|
|
|
7848 /****************** Bit definition for TIM_CCMR3 register *******************/
|
|
|
7849 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004U) /*!<Output Compare 5 Fast enable */
|
|
|
7850 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008U) /*!<Output Compare 5 Preload enable */
|
|
|
7851
|
|
|
7852 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070U) /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
|
|
7853 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
7854 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
7855 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
7856 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
7857
|
|
|
7858 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080U) /*!<Output Compare 5 Clear Enable */
|
|
|
7859
|
|
|
7860 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400U) /*!<Output Compare 6 Fast enable */
|
|
|
7861 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800U) /*!<Output Compare 6 Preload enable */
|
|
|
7862
|
|
|
7863 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000U) /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
|
|
|
7864 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
7865 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
7866 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
7867 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
|
|
|
7868
|
|
|
7869 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000U) /*!<Output Compare 6 Clear Enable */
|
|
|
7870
|
|
|
7871 /******************* Bit definition for TIM_CCER register *******************/
|
|
|
7872 #define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
|
|
|
7873 #define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
|
|
|
7874 #define TIM_CCER_CC1NE ((uint32_t)0x00000004U) /*!<Capture/Compare 1 Complementary output enable */
|
|
|
7875 #define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
|
|
|
7876 #define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
|
|
|
7877 #define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
|
|
|
7878 #define TIM_CCER_CC2NE ((uint32_t)0x00000040U) /*!<Capture/Compare 2 Complementary output enable */
|
|
|
7879 #define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
|
|
|
7880 #define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
|
|
|
7881 #define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
|
|
|
7882 #define TIM_CCER_CC3NE ((uint32_t)0x00000400U) /*!<Capture/Compare 3 Complementary output enable */
|
|
|
7883 #define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
|
|
|
7884 #define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
|
|
|
7885 #define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
|
|
|
7886 #define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
|
|
|
7887 #define TIM_CCER_CC5E ((uint32_t)0x00010000U) /*!<Capture/Compare 5 output enable */
|
|
|
7888 #define TIM_CCER_CC5P ((uint32_t)0x00020000U) /*!<Capture/Compare 5 output Polarity */
|
|
|
7889 #define TIM_CCER_CC6E ((uint32_t)0x00100000U) /*!<Capture/Compare 6 output enable */
|
|
|
7890 #define TIM_CCER_CC6P ((uint32_t)0x00200000U) /*!<Capture/Compare 6 output Polarity */
|
|
|
7891
|
|
|
7892 /******************* Bit definition for TIM_CNT register ********************/
|
|
|
7893 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFFU) /*!<Counter Value */
|
|
|
7894 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000U) /*!<Update interrupt flag copy (if UIFREMAP=1) */
|
|
|
7895
|
|
|
7896 /******************* Bit definition for TIM_PSC register ********************/
|
|
|
7897 #define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
|
|
|
7898
|
|
|
7899 /******************* Bit definition for TIM_ARR register ********************/
|
|
|
7900 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFFU) /*!<Actual auto-reload Value */
|
|
|
7901
|
|
|
7902 /******************* Bit definition for TIM_RCR register ********************/
|
|
|
7903 #define TIM_RCR_REP ((uint32_t)0x0000FFFFU) /*!<Repetition Counter Value */
|
|
|
7904
|
|
|
7905 /******************* Bit definition for TIM_CCR1 register *******************/
|
|
|
7906 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
|
|
|
7907
|
|
|
7908 /******************* Bit definition for TIM_CCR2 register *******************/
|
|
|
7909 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
|
|
|
7910
|
|
|
7911 /******************* Bit definition for TIM_CCR3 register *******************/
|
|
|
7912 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
|
|
|
7913
|
|
|
7914 /******************* Bit definition for TIM_CCR4 register *******************/
|
|
|
7915 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
|
|
|
7916
|
|
|
7917 /******************* Bit definition for TIM_CCR5 register *******************/
|
|
|
7918 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFFU) /*!<Capture/Compare 5 Value */
|
|
|
7919 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000U) /*!<Group Channel 5 and Channel 1 */
|
|
|
7920 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000U) /*!<Group Channel 5 and Channel 2 */
|
|
|
7921 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000U) /*!<Group Channel 5 and Channel 3 */
|
|
|
7922
|
|
|
7923 /******************* Bit definition for TIM_CCR6 register *******************/
|
|
|
7924 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 6 Value */
|
|
|
7925
|
|
|
7926 /******************* Bit definition for TIM_BDTR register *******************/
|
|
|
7927 #define TIM_BDTR_DTG ((uint32_t)0x000000FFU) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
|
|
|
7928 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
7929 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
7930 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
7931 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
7932 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
7933 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
7934 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
7935 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
|
|
|
7936
|
|
|
7937 #define TIM_BDTR_LOCK ((uint32_t)0x00000300U) /*!<LOCK[1:0] bits (Lock Configuration) */
|
|
|
7938 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
7939 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
7940
|
|
|
7941 #define TIM_BDTR_OSSI ((uint32_t)0x00000400U) /*!<Off-State Selection for Idle mode */
|
|
|
7942 #define TIM_BDTR_OSSR ((uint32_t)0x00000800U) /*!<Off-State Selection for Run mode */
|
|
|
7943 #define TIM_BDTR_BKE ((uint32_t)0x00001000U) /*!<Break enable for Break 1 */
|
|
|
7944 #define TIM_BDTR_BKP ((uint32_t)0x00002000U) /*!<Break Polarity for Break 1 */
|
|
|
7945 #define TIM_BDTR_AOE ((uint32_t)0x00004000U) /*!<Automatic Output enable */
|
|
|
7946 #define TIM_BDTR_MOE ((uint32_t)0x00008000U) /*!<Main Output enable */
|
|
|
7947
|
|
|
7948 #define TIM_BDTR_BKF ((uint32_t)0x000F0000U) /*!<Break Filter for Break 1 */
|
|
|
7949 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000U) /*!<Break Filter for Break 2 */
|
|
|
7950
|
|
|
7951 #define TIM_BDTR_BK2E ((uint32_t)0x01000000U) /*!<Break enable for Break 2 */
|
|
|
7952 #define TIM_BDTR_BK2P ((uint32_t)0x02000000U) /*!<Break Polarity for Break 2 */
|
|
|
7953
|
|
|
7954 /******************* Bit definition for TIM_DCR register ********************/
|
|
|
7955 #define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
|
|
|
7956 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
7957 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
7958 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
7959 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
7960 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
7961
|
|
|
7962 #define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
|
|
|
7963 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
|
|
|
7964 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
|
|
|
7965 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
|
|
|
7966 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
|
|
|
7967 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
|
|
|
7968
|
|
|
7969 /******************* Bit definition for TIM_DMAR register *******************/
|
|
|
7970 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
|
|
|
7971
|
|
|
7972 /******************* Bit definition for TIM1_OR1 register *******************/
|
|
|
7973 #define TIM1_OR1_ETR_ADC1_RMP ((uint32_t)0x00000003U) /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
|
|
|
7974 #define TIM1_OR1_ETR_ADC1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
7975 #define TIM1_OR1_ETR_ADC1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
7976
|
|
|
7977 #define TIM1_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000CU) /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
|
|
|
7978 #define TIM1_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
7979 #define TIM1_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
7980
|
|
|
7981 #define TIM1_OR1_TI1_RMP ((uint32_t)0x00000010U) /*!<TIM1 Input Capture 1 remap */
|
|
|
7982
|
|
|
7983 /******************* Bit definition for TIM1_OR2 register *******************/
|
|
|
7984 #define TIM1_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
|
|
|
7985 #define TIM1_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
|
|
|
7986 #define TIM1_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
|
|
|
7987 #define TIM1_OR2_BKDFBK0E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[0] enable */
|
|
|
7988 #define TIM1_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
|
|
|
7989 #define TIM1_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
|
|
|
7990 #define TIM1_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
|
|
|
7991
|
|
|
7992 #define TIM1_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
|
|
|
7993 #define TIM1_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
|
|
|
7994 #define TIM1_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
|
|
|
7995 #define TIM1_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
|
|
|
7996
|
|
|
7997 /******************* Bit definition for TIM1_OR3 register *******************/
|
|
|
7998 #define TIM1_OR3_BK2INE ((uint32_t)0x00000001U) /*!<BRK2 BKIN2 input enable */
|
|
|
7999 #define TIM1_OR3_BK2CMP1E ((uint32_t)0x00000002U) /*!<BRK2 COMP1 enable */
|
|
|
8000 #define TIM1_OR3_BK2CMP2E ((uint32_t)0x00000004U) /*!<BRK2 COMP2 enable */
|
|
|
8001 #define TIM1_OR3_BK2DFBK1E ((uint32_t)0x00000100U) /*!<BRK2 DFSDM_BREAK[1] enable */
|
|
|
8002 #define TIM1_OR3_BK2INP ((uint32_t)0x00000200U) /*!<BRK2 BKIN2 input polarity */
|
|
|
8003 #define TIM1_OR3_BK2CMP1P ((uint32_t)0x00000400U) /*!<BRK2 COMP1 input polarity */
|
|
|
8004 #define TIM1_OR3_BK2CMP2P ((uint32_t)0x00000800U) /*!<BRK2 COMP2 input polarity */
|
|
|
8005
|
|
|
8006 /******************* Bit definition for TIM8_OR1 register *******************/
|
|
|
8007 #define TIM8_OR1_ETR_ADC2_RMP ((uint32_t)0x00000003U) /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
|
|
|
8008 #define TIM8_OR1_ETR_ADC2_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
8009 #define TIM8_OR1_ETR_ADC2_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
8010
|
|
|
8011 #define TIM8_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000CU) /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
|
|
|
8012 #define TIM8_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
8013 #define TIM8_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
8014
|
|
|
8015 #define TIM8_OR1_TI1_RMP ((uint32_t)0x00000010U) /*!<TIM8 Input Capture 1 remap */
|
|
|
8016
|
|
|
8017 /******************* Bit definition for TIM8_OR2 register *******************/
|
|
|
8018 #define TIM8_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
|
|
|
8019 #define TIM8_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
|
|
|
8020 #define TIM8_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
|
|
|
8021 #define TIM8_OR2_BKDFBK2E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[2] enable */
|
|
|
8022 #define TIM8_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
|
|
|
8023 #define TIM8_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
|
|
|
8024 #define TIM8_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
|
|
|
8025
|
|
|
8026 #define TIM8_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
|
|
|
8027 #define TIM8_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
|
|
|
8028 #define TIM8_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
|
|
|
8029 #define TIM8_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
|
|
|
8030
|
|
|
8031 /******************* Bit definition for TIM8_OR3 register *******************/
|
|
|
8032 #define TIM8_OR3_BK2INE ((uint32_t)0x00000001U) /*!<BRK2 BKIN2 input enable */
|
|
|
8033 #define TIM8_OR3_BK2CMP1E ((uint32_t)0x00000002U) /*!<BRK2 COMP1 enable */
|
|
|
8034 #define TIM8_OR3_BK2CMP2E ((uint32_t)0x00000004U) /*!<BRK2 COMP2 enable */
|
|
|
8035 #define TIM8_OR3_BK2DFBK3E ((uint32_t)0x00000100U) /*!<BRK2 DFSDM_BREAK[3] enable */
|
|
|
8036 #define TIM8_OR3_BK2INP ((uint32_t)0x00000200U) /*!<BRK2 BKIN2 input polarity */
|
|
|
8037 #define TIM8_OR3_BK2CMP1P ((uint32_t)0x00000400U) /*!<BRK2 COMP1 input polarity */
|
|
|
8038 #define TIM8_OR3_BK2CMP2P ((uint32_t)0x00000800U) /*!<BRK2 COMP2 input polarity */
|
|
|
8039
|
|
|
8040 /******************* Bit definition for TIM2_OR1 register *******************/
|
|
|
8041 #define TIM2_OR1_ITR1_RMP ((uint32_t)0x00000001U) /*!<TIM2 Internal trigger 1 remap */
|
|
|
8042 #define TIM2_OR1_ETR1_RMP ((uint32_t)0x00000002U) /*!<TIM2 External trigger 1 remap */
|
|
|
8043
|
|
|
8044 #define TIM2_OR1_TI4_RMP ((uint32_t)0x0000000CU) /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
|
|
|
8045 #define TIM2_OR1_TI4_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
8046 #define TIM2_OR1_TI4_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
8047
|
|
|
8048 /******************* Bit definition for TIM2_OR2 register *******************/
|
|
|
8049 #define TIM2_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
|
|
|
8050 #define TIM2_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
|
|
|
8051 #define TIM2_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
|
|
|
8052 #define TIM2_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
|
|
|
8053
|
|
|
8054 /******************* Bit definition for TIM3_OR1 register *******************/
|
|
|
8055 #define TIM3_OR1_TI1_RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
|
|
|
8056 #define TIM3_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
8057 #define TIM3_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
8058
|
|
|
8059 /******************* Bit definition for TIM3_OR2 register *******************/
|
|
|
8060 #define TIM3_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
|
|
|
8061 #define TIM3_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
|
|
|
8062 #define TIM3_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
|
|
|
8063 #define TIM3_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
|
|
|
8064
|
|
|
8065 /******************* Bit definition for TIM15_OR1 register ******************/
|
|
|
8066 #define TIM15_OR1_TI1_RMP ((uint32_t)0x00000001U) /*!<TIM15 Input Capture 1 remap */
|
|
|
8067
|
|
|
8068 #define TIM15_OR1_ENCODER_MODE ((uint32_t)0x00000006U) /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
|
|
|
8069 #define TIM15_OR1_ENCODER_MODE_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
|
|
|
8070 #define TIM15_OR1_ENCODER_MODE_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
|
|
|
8071
|
|
|
8072 /******************* Bit definition for TIM15_OR2 register ******************/
|
|
|
8073 #define TIM15_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
|
|
|
8074 #define TIM15_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
|
|
|
8075 #define TIM15_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
|
|
|
8076 #define TIM15_OR2_BKDFBK0E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[0] enable */
|
|
|
8077 #define TIM15_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
|
|
|
8078 #define TIM15_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
|
|
|
8079 #define TIM15_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
|
|
|
8080
|
|
|
8081 /******************* Bit definition for TIM16_OR1 register ******************/
|
|
|
8082 #define TIM16_OR1_TI1_RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
|
|
|
8083 #define TIM16_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
8084 #define TIM16_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
8085
|
|
|
8086 /******************* Bit definition for TIM16_OR2 register ******************/
|
|
|
8087 #define TIM16_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
|
|
|
8088 #define TIM16_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
|
|
|
8089 #define TIM16_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
|
|
|
8090 #define TIM16_OR2_BKDFBK1E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[1] enable */
|
|
|
8091 #define TIM16_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
|
|
|
8092 #define TIM16_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
|
|
|
8093 #define TIM16_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
|
|
|
8094
|
|
|
8095 /******************* Bit definition for TIM17_OR1 register ******************/
|
|
|
8096 #define TIM17_OR1_TI1_RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
|
|
|
8097 #define TIM17_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
8098 #define TIM17_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
8099
|
|
|
8100 /******************* Bit definition for TIM17_OR2 register ******************/
|
|
|
8101 #define TIM17_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
|
|
|
8102 #define TIM17_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
|
|
|
8103 #define TIM17_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
|
|
|
8104 #define TIM17_OR2_BKDFBK2E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[2] enable */
|
|
|
8105 #define TIM17_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
|
|
|
8106 #define TIM17_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
|
|
|
8107 #define TIM17_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
|
|
|
8108
|
|
|
8109 /******************************************************************************/
|
|
|
8110 /* */
|
|
|
8111 /* Low Power Timer (LPTTIM) */
|
|
|
8112 /* */
|
|
|
8113 /******************************************************************************/
|
|
|
8114 /****************** Bit definition for LPTIM_ISR register *******************/
|
|
|
8115 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */
|
|
|
8116 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */
|
|
|
8117 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */
|
|
|
8118 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */
|
|
|
8119 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */
|
|
|
8120 #define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */
|
|
|
8121 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */
|
|
|
8122
|
|
|
8123 /****************** Bit definition for LPTIM_ICR register *******************/
|
|
|
8124 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */
|
|
|
8125 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */
|
|
|
8126 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */
|
|
|
8127 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */
|
|
|
8128 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */
|
|
|
8129 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */
|
|
|
8130 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */
|
|
|
8131
|
|
|
8132 /****************** Bit definition for LPTIM_IER register ********************/
|
|
|
8133 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */
|
|
|
8134 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */
|
|
|
8135 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */
|
|
|
8136 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */
|
|
|
8137 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */
|
|
|
8138 #define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */
|
|
|
8139 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */
|
|
|
8140
|
|
|
8141 /****************** Bit definition for LPTIM_CFGR register *******************/
|
|
|
8142 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */
|
|
|
8143
|
|
|
8144 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */
|
|
|
8145 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
|
|
|
8146 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
|
|
|
8147
|
|
|
8148 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
|
|
|
8149 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
|
|
|
8150 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
|
|
|
8151
|
|
|
8152 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
|
|
|
8153 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
|
|
|
8154 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
|
|
|
8155
|
|
|
8156 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */
|
|
|
8157 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
|
|
|
8158 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
|
|
|
8159 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
|
|
|
8160
|
|
|
8161 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
|
|
|
8162 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
|
|
|
8163 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
|
|
|
8164 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
|
|
|
8165
|
|
|
8166 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
|
|
|
8167 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
|
|
|
8168 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
|
|
|
8169
|
|
|
8170 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */
|
|
|
8171 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */
|
|
|
8172 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */
|
|
|
8173 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */
|
|
|
8174 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */
|
|
|
8175 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */
|
|
|
8176
|
|
|
8177 /****************** Bit definition for LPTIM_CR register ********************/
|
|
|
8178 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */
|
|
|
8179 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */
|
|
|
8180 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */
|
|
|
8181
|
|
|
8182 /****************** Bit definition for LPTIM_CMP register *******************/
|
|
|
8183 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */
|
|
|
8184
|
|
|
8185 /****************** Bit definition for LPTIM_ARR register *******************/
|
|
|
8186 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */
|
|
|
8187
|
|
|
8188 /****************** Bit definition for LPTIM_CNT register *******************/
|
|
|
8189 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */
|
|
|
8190
|
|
|
8191 /****************** Bit definition for LPTIM_OR register *******************/
|
|
|
8192 #define LPTIM_OR_OR ((uint32_t)0x00000003U) /*!< LPTIMER[1:0] bits (Remap selection) */
|
|
|
8193 #define LPTIM_OR_OR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
|
|
|
8194 #define LPTIM_OR_OR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
|
|
|
8195
|
|
|
8196 /******************************************************************************/
|
|
|
8197 /* */
|
|
|
8198 /* Analog Comparators (COMP) */
|
|
|
8199 /* */
|
|
|
8200 /******************************************************************************/
|
|
|
8201 /********************** Bit definition for COMPx_CSR register ***************/
|
|
|
8202 #define COMP_CSR_EN ((uint32_t)0x00000001U) /*!< COMPx enable */
|
|
|
8203
|
|
|
8204 #define COMP_CSR_PWRMODE ((uint32_t)0x0000000CU) /*!< COMPx power mode */
|
|
|
8205 #define COMP_CSR_PWRMODE_0 ((uint32_t)0x00000004U) /*!< COMPx power mode bit 0 */
|
|
|
8206 #define COMP_CSR_PWRMODE_1 ((uint32_t)0x00000008U) /*!< COMPx power mode bit 1 */
|
|
|
8207
|
|
|
8208 #define COMP_CSR_INMSEL ((uint32_t)0x00000070U) /*!< COMPx inverting input (minus) selection */
|
|
|
8209 #define COMP_CSR_INMSEL_0 ((uint32_t)0x00000010U) /*!< COMPx inverting input (minus) selection bit 0 */
|
|
|
8210 #define COMP_CSR_INMSEL_1 ((uint32_t)0x00000020U) /*!< COMPx inverting input (minus) selection bit 1 */
|
|
|
8211 #define COMP_CSR_INMSEL_2 ((uint32_t)0x00000040U) /*!< COMPx inverting input (minus) selection bit 2 */
|
|
|
8212
|
|
|
8213 #define COMP_CSR_INPSEL ((uint32_t)0x00000080U) /*!< COMPx non inverting input (plus) selection */
|
|
|
8214 #define COMP_CSR_INPSEL_0 ((uint32_t)0x00000080U) /*!< COMPx non inverting input (plus) selection bit 0*/
|
|
|
8215 #define COMP_CSR_WINMODE ((uint32_t)0x00000200U) /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
|
|
|
8216 #define COMP_CSR_POLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */
|
|
|
8217
|
|
|
8218 #define COMP_CSR_HYST ((uint32_t)0x00030000U) /*!< COMPx hysteresis */
|
|
|
8219 #define COMP_CSR_HYST_0 ((uint32_t)0x00010000U) /*!< COMPx hysteresis bit 0 */
|
|
|
8220 #define COMP_CSR_HYST_1 ((uint32_t)0x00020000U) /*!< COMPx hysteresis bit 1 */
|
|
|
8221
|
|
|
8222 #define COMP_CSR_BLANKING ((uint32_t)0x001C0000U) /*!< COMPx blanking source */
|
|
|
8223 #define COMP_CSR_BLANKING_0 ((uint32_t)0x00040000U) /*!< COMPx blanking source bit 0 */
|
|
|
8224 #define COMP_CSR_BLANKING_1 ((uint32_t)0x00080000U) /*!< COMPx blanking source bit 1 */
|
|
|
8225 #define COMP_CSR_BLANKING_2 ((uint32_t)0x00100000U) /*!< COMPx blanking source bit 2 */
|
|
|
8226
|
|
|
8227 #define COMP_CSR_BRGEN ((uint32_t)0x00400000U) /*!< COMPx voltage scaler enable */
|
|
|
8228 #define COMP_CSR_SCALEN ((uint32_t)0x00800000U) /*!< COMPx scaler bridge enable */
|
|
|
8229 #define COMP_CSR_VALUE ((uint32_t)0x40000000U) /*!< COMPx value */
|
|
|
8230 #define COMP_CSR_LOCK ((uint32_t)0x80000000U) /*!< COMPx lock */
|
|
|
8231
|
|
|
8232 /******************************************************************************/
|
|
|
8233 /* */
|
|
|
8234 /* Operational Amplifier (OPAMP) */
|
|
|
8235 /* */
|
|
|
8236 /******************************************************************************/
|
|
|
8237 /********************* Bit definition for OPAMPx_CSR register ***************/
|
|
|
8238 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001U) /*!< OPAMP enable */
|
|
|
8239 #define OPAMP_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier Low Power Mode */
|
|
|
8240
|
|
|
8241 #define OPAMP_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier PGA mode */
|
|
|
8242 #define OPAMP_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
|
|
|
8243 #define OPAMP_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
|
|
|
8244
|
|
|
8245 #define OPAMP_CSR_PGGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier Programmable amplifier gain value */
|
|
|
8246 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
|
|
|
8247 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
|
|
|
8248
|
|
|
8249 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
|
|
|
8250 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
8251 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
8252
|
|
|
8253 #define OPAMP_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
|
|
|
8254 #define OPAMP_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
|
|
|
8255 #define OPAMP_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
|
|
|
8256 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
|
|
|
8257 #define OPAMP_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
|
|
|
8258
|
|
|
8259 /********************* Bit definition for OPAMP1_CSR register ***************/
|
|
|
8260 #define OPAMP1_CSR_OPAEN ((uint32_t)0x00000001U) /*!< Operational amplifier1 Enable */
|
|
|
8261 #define OPAMP1_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier1 Low Power Mode */
|
|
|
8262
|
|
|
8263 #define OPAMP1_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier1 PGA mode */
|
|
|
8264 #define OPAMP1_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
|
|
|
8265 #define OPAMP1_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
|
|
|
8266
|
|
|
8267 #define OPAMP1_CSR_PGAGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier1 Programmable amplifier gain value */
|
|
|
8268 #define OPAMP1_CSR_PGAGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
|
|
|
8269 #define OPAMP1_CSR_PGAGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
|
|
|
8270
|
|
|
8271 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
|
|
|
8272 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
8273 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
8274
|
|
|
8275 #define OPAMP1_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
|
|
|
8276 #define OPAMP1_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
|
|
|
8277 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
|
|
|
8278 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
|
|
|
8279 #define OPAMP1_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
|
|
|
8280 #define OPAMP1_CSR_OPARANGE ((uint32_t)0x80000000U) /*!< Operational amplifiers power supply range for stability */
|
|
|
8281
|
|
|
8282 /********************* Bit definition for OPAMP2_CSR register ***************/
|
|
|
8283 #define OPAMP2_CSR_OPAEN ((uint32_t)0x00000001U) /*!< Operational amplifier2 Enable */
|
|
|
8284 #define OPAMP2_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier2 Low Power Mode */
|
|
|
8285
|
|
|
8286 #define OPAMP2_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier2 PGA mode */
|
|
|
8287 #define OPAMP2_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
|
|
|
8288 #define OPAMP2_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
|
|
|
8289
|
|
|
8290 #define OPAMP2_CSR_PGAGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier2 Programmable amplifier gain value */
|
|
|
8291 #define OPAMP2_CSR_PGAGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
|
|
|
8292 #define OPAMP2_CSR_PGAGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
|
|
|
8293
|
|
|
8294 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
|
|
|
8295 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
|
|
|
8296 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
|
|
|
8297
|
|
|
8298 #define OPAMP2_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
|
|
|
8299 #define OPAMP2_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
|
|
|
8300 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
|
|
|
8301 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
|
|
|
8302 #define OPAMP2_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier2 calibration output */
|
|
|
8303
|
|
|
8304 /******************* Bit definition for OPAMP_OTR register ******************/
|
|
|
8305 #define OPAMP_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
8306 #define OPAMP_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
8307
|
|
|
8308 /******************* Bit definition for OPAMP1_OTR register ******************/
|
|
|
8309 #define OPAMP1_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
8310 #define OPAMP1_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
8311
|
|
|
8312 /******************* Bit definition for OPAMP2_OTR register ******************/
|
|
|
8313 #define OPAMP2_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
8314 #define OPAMP2_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
8315
|
|
|
8316 /******************* Bit definition for OPAMP_LPOTR register ****************/
|
|
|
8317 #define OPAMP_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
8318 #define OPAMP_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
8319
|
|
|
8320 /******************* Bit definition for OPAMP1_LPOTR register ****************/
|
|
|
8321 #define OPAMP1_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
8322 #define OPAMP1_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
8323
|
|
|
8324 /******************* Bit definition for OPAMP2_LPOTR register ****************/
|
|
|
8325 #define OPAMP2_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
|
|
|
8326 #define OPAMP2_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
|
|
|
8327
|
|
|
8328 /******************************************************************************/
|
|
|
8329 /* */
|
|
|
8330 /* Touch Sensing Controller (TSC) */
|
|
|
8331 /* */
|
|
|
8332 /******************************************************************************/
|
|
|
8333 /******************* Bit definition for TSC_CR register *********************/
|
|
|
8334 #define TSC_CR_TSCE ((uint32_t)0x00000001U) /*!<Touch sensing controller enable */
|
|
|
8335 #define TSC_CR_START ((uint32_t)0x00000002U) /*!<Start acquisition */
|
|
|
8336 #define TSC_CR_AM ((uint32_t)0x00000004U) /*!<Acquisition mode */
|
|
|
8337 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /*!<Synchronization pin polarity */
|
|
|
8338 #define TSC_CR_IODEF ((uint32_t)0x00000010U) /*!<IO default mode */
|
|
|
8339
|
|
|
8340 #define TSC_CR_MCV ((uint32_t)0x000000E0U) /*!<MCV[2:0] bits (Max Count Value) */
|
|
|
8341 #define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
|
|
|
8342 #define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
|
|
|
8343 #define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
|
|
|
8344
|
|
|
8345 #define TSC_CR_PGPSC ((uint32_t)0x00007000U) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
|
|
|
8346 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
|
|
|
8347 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
|
|
|
8348 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
|
|
|
8349
|
|
|
8350 #define TSC_CR_SSPSC ((uint32_t)0x00008000U) /*!<Spread Spectrum Prescaler */
|
|
|
8351 #define TSC_CR_SSE ((uint32_t)0x00010000U) /*!<Spread Spectrum Enable */
|
|
|
8352
|
|
|
8353 #define TSC_CR_SSD ((uint32_t)0x00FE0000U) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
|
|
|
8354 #define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
|
|
|
8355 #define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
|
|
|
8356 #define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
|
|
|
8357 #define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
|
|
|
8358 #define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
|
|
|
8359 #define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
|
|
|
8360 #define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
|
|
|
8361
|
|
|
8362 #define TSC_CR_CTPL ((uint32_t)0x0F000000U) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
|
|
|
8363 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
8364 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
8365 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
8366 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
8367
|
|
|
8368 #define TSC_CR_CTPH ((uint32_t)0xF0000000U) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
|
|
|
8369 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
|
|
|
8370 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
|
|
|
8371 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
|
|
|
8372 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /*!<Bit 3 */
|
|
|
8373
|
|
|
8374 /******************* Bit definition for TSC_IER register ********************/
|
|
|
8375 #define TSC_IER_EOAIE ((uint32_t)0x00000001U) /*!<End of acquisition interrupt enable */
|
|
|
8376 #define TSC_IER_MCEIE ((uint32_t)0x00000002U) /*!<Max count error interrupt enable */
|
|
|
8377
|
|
|
8378 /******************* Bit definition for TSC_ICR register ********************/
|
|
|
8379 #define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /*!<End of acquisition interrupt clear */
|
|
|
8380 #define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /*!<Max count error interrupt clear */
|
|
|
8381
|
|
|
8382 /******************* Bit definition for TSC_ISR register ********************/
|
|
|
8383 #define TSC_ISR_EOAF ((uint32_t)0x00000001U) /*!<End of acquisition flag */
|
|
|
8384 #define TSC_ISR_MCEF ((uint32_t)0x00000002U) /*!<Max count error flag */
|
|
|
8385
|
|
|
8386 /******************* Bit definition for TSC_IOHCR register ******************/
|
|
|
8387 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
|
|
|
8388 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
|
|
|
8389 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
|
|
|
8390 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
|
|
|
8391 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
|
|
|
8392 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
|
|
|
8393 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
|
|
|
8394 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
|
|
|
8395 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
|
|
|
8396 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
|
|
|
8397 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
|
|
|
8398 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
|
|
|
8399 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
|
|
|
8400 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
|
|
|
8401 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
|
|
|
8402 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
|
|
|
8403 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
|
|
|
8404 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
|
|
|
8405 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
|
|
|
8406 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
|
|
|
8407 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
|
|
|
8408 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
|
|
|
8409 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
|
|
|
8410 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
|
|
|
8411 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
|
|
|
8412 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
|
|
|
8413 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
|
|
|
8414 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
|
|
|
8415 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
|
|
|
8416 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
|
|
|
8417 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
|
|
|
8418 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
|
|
|
8419
|
|
|
8420 /******************* Bit definition for TSC_IOASCR register *****************/
|
|
|
8421 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 analog switch enable */
|
|
|
8422 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 analog switch enable */
|
|
|
8423 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 analog switch enable */
|
|
|
8424 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 analog switch enable */
|
|
|
8425 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 analog switch enable */
|
|
|
8426 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 analog switch enable */
|
|
|
8427 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 analog switch enable */
|
|
|
8428 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 analog switch enable */
|
|
|
8429 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 analog switch enable */
|
|
|
8430 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 analog switch enable */
|
|
|
8431 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 analog switch enable */
|
|
|
8432 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 analog switch enable */
|
|
|
8433 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 analog switch enable */
|
|
|
8434 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 analog switch enable */
|
|
|
8435 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 analog switch enable */
|
|
|
8436 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 analog switch enable */
|
|
|
8437 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 analog switch enable */
|
|
|
8438 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 analog switch enable */
|
|
|
8439 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 analog switch enable */
|
|
|
8440 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 analog switch enable */
|
|
|
8441 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 analog switch enable */
|
|
|
8442 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 analog switch enable */
|
|
|
8443 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 analog switch enable */
|
|
|
8444 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 analog switch enable */
|
|
|
8445 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 analog switch enable */
|
|
|
8446 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 analog switch enable */
|
|
|
8447 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 analog switch enable */
|
|
|
8448 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 analog switch enable */
|
|
|
8449 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 analog switch enable */
|
|
|
8450 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 analog switch enable */
|
|
|
8451 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 analog switch enable */
|
|
|
8452 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 analog switch enable */
|
|
|
8453
|
|
|
8454 /******************* Bit definition for TSC_IOSCR register ******************/
|
|
|
8455 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 sampling mode */
|
|
|
8456 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 sampling mode */
|
|
|
8457 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 sampling mode */
|
|
|
8458 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 sampling mode */
|
|
|
8459 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 sampling mode */
|
|
|
8460 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 sampling mode */
|
|
|
8461 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 sampling mode */
|
|
|
8462 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 sampling mode */
|
|
|
8463 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 sampling mode */
|
|
|
8464 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 sampling mode */
|
|
|
8465 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 sampling mode */
|
|
|
8466 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 sampling mode */
|
|
|
8467 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 sampling mode */
|
|
|
8468 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 sampling mode */
|
|
|
8469 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 sampling mode */
|
|
|
8470 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 sampling mode */
|
|
|
8471 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 sampling mode */
|
|
|
8472 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 sampling mode */
|
|
|
8473 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 sampling mode */
|
|
|
8474 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 sampling mode */
|
|
|
8475 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 sampling mode */
|
|
|
8476 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 sampling mode */
|
|
|
8477 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 sampling mode */
|
|
|
8478 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 sampling mode */
|
|
|
8479 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 sampling mode */
|
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|
8480 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 sampling mode */
|
|
|
8481 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 sampling mode */
|
|
|
8482 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 sampling mode */
|
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8483 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 sampling mode */
|
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|
8484 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 sampling mode */
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8485 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 sampling mode */
|
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|
8486 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 sampling mode */
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8487
|
|
|
8488 /******************* Bit definition for TSC_IOCCR register ******************/
|
|
|
8489 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 channel mode */
|
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|
8490 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 channel mode */
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8491 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 channel mode */
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8492 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 channel mode */
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8493 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 channel mode */
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8494 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 channel mode */
|
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|
8495 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 channel mode */
|
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8496 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 channel mode */
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8497 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 channel mode */
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8498 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 channel mode */
|
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|
8499 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 channel mode */
|
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|
8500 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 channel mode */
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|
8501 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 channel mode */
|
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|
8502 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 channel mode */
|
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|
8503 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 channel mode */
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|
8504 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 channel mode */
|
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|
8505 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 channel mode */
|
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|
8506 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 channel mode */
|
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|
8507 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 channel mode */
|
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|
8508 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 channel mode */
|
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8509 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 channel mode */
|
|
|
8510 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 channel mode */
|
|
|
8511 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 channel mode */
|
|
|
8512 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 channel mode */
|
|
|
8513 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 channel mode */
|
|
|
8514 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 channel mode */
|
|
|
8515 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 channel mode */
|
|
|
8516 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 channel mode */
|
|
|
8517 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 channel mode */
|
|
|
8518 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 channel mode */
|
|
|
8519 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 channel mode */
|
|
|
8520 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 channel mode */
|
|
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8521
|
|
|
8522 /******************* Bit definition for TSC_IOGCSR register *****************/
|
|
|
8523 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /*!<Analog IO GROUP1 enable */
|
|
|
8524 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /*!<Analog IO GROUP2 enable */
|
|
|
8525 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /*!<Analog IO GROUP3 enable */
|
|
|
8526 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /*!<Analog IO GROUP4 enable */
|
|
|
8527 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /*!<Analog IO GROUP5 enable */
|
|
|
8528 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /*!<Analog IO GROUP6 enable */
|
|
|
8529 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /*!<Analog IO GROUP7 enable */
|
|
|
8530 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080U) /*!<Analog IO GROUP8 enable */
|
|
|
8531 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /*!<Analog IO GROUP1 status */
|
|
|
8532 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /*!<Analog IO GROUP2 status */
|
|
|
8533 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /*!<Analog IO GROUP3 status */
|
|
|
8534 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /*!<Analog IO GROUP4 status */
|
|
|
8535 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /*!<Analog IO GROUP5 status */
|
|
|
8536 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /*!<Analog IO GROUP6 status */
|
|
|
8537 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /*!<Analog IO GROUP7 status */
|
|
|
8538 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000U) /*!<Analog IO GROUP8 status */
|
|
|
8539
|
|
|
8540 /******************* Bit definition for TSC_IOGXCR register *****************/
|
|
|
8541 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /*!<CNT[13:0] bits (Counter value) */
|
|
|
8542
|
|
|
8543 /******************************************************************************/
|
|
|
8544 /* */
|
|
|
8545 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
|
|
8546 /* */
|
|
|
8547 /******************************************************************************/
|
|
|
8548 /****************** Bit definition for USART_CR1 register *******************/
|
|
|
8549 #define USART_CR1_UE ((uint32_t)0x00000001U) /*!< USART Enable */
|
|
|
8550 #define USART_CR1_UESM ((uint32_t)0x00000002U) /*!< USART Enable in STOP Mode */
|
|
|
8551 #define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
|
|
|
8552 #define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
|
|
|
8553 #define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
|
|
|
8554 #define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
|
|
|
8555 #define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
|
|
|
8556 #define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< TXE Interrupt Enable */
|
|
|
8557 #define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
|
|
|
8558 #define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
|
|
|
8559 #define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
|
|
|
8560 #define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Receiver Wakeup method */
|
|
|
8561 #define USART_CR1_M ((uint32_t)0x10001000U) /*!< Word length */
|
|
|
8562 #define USART_CR1_M0 ((uint32_t)0x00001000U) /*!< Word length - Bit 0 */
|
|
|
8563 #define USART_CR1_MME ((uint32_t)0x00002000U) /*!< Mute Mode Enable */
|
|
|
8564 #define USART_CR1_CMIE ((uint32_t)0x00004000U) /*!< Character match interrupt enable */
|
|
|
8565 #define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit or 16-bit mode */
|
|
|
8566 #define USART_CR1_DEDT ((uint32_t)0x001F0000U) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
|
|
|
8567 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
|
|
|
8568 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
|
|
|
8569 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
|
|
|
8570 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
|
|
|
8571 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
|
|
|
8572 #define USART_CR1_DEAT ((uint32_t)0x03E00000U) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
|
|
|
8573 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
|
|
|
8574 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
|
|
|
8575 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
|
|
|
8576 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /*!< Bit 3 */
|
|
|
8577 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /*!< Bit 4 */
|
|
|
8578 #define USART_CR1_RTOIE ((uint32_t)0x04000000U) /*!< Receive Time Out interrupt enable */
|
|
|
8579 #define USART_CR1_EOBIE ((uint32_t)0x08000000U) /*!< End of Block interrupt enable */
|
|
|
8580 #define USART_CR1_M1 ((uint32_t)0x10000000U) /*!< Word length - Bit 1 */
|
|
|
8581
|
|
|
8582 /****************** Bit definition for USART_CR2 register *******************/
|
|
|
8583 #define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /*!< 7-bit or 4-bit Address Detection */
|
|
|
8584 #define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
|
|
|
8585 #define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
|
|
|
8586 #define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
|
|
|
8587 #define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
|
|
|
8588 #define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
|
|
|
8589 #define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
|
|
|
8590 #define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
|
|
|
8591 #define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
|
|
|
8592 #define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
|
|
|
8593 #define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
|
|
|
8594 #define USART_CR2_SWAP ((uint32_t)0x00008000U) /*!< SWAP TX/RX pins */
|
|
|
8595 #define USART_CR2_RXINV ((uint32_t)0x00010000U) /*!< RX pin active level inversion */
|
|
|
8596 #define USART_CR2_TXINV ((uint32_t)0x00020000U) /*!< TX pin active level inversion */
|
|
|
8597 #define USART_CR2_DATAINV ((uint32_t)0x00040000U) /*!< Binary data inversion */
|
|
|
8598 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /*!< Most Significant Bit First */
|
|
|
8599 #define USART_CR2_ABREN ((uint32_t)0x00100000U) /*!< Auto Baud-Rate Enable*/
|
|
|
8600 #define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
|
|
|
8601 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
|
|
|
8602 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
|
|
|
8603 #define USART_CR2_RTOEN ((uint32_t)0x00800000U) /*!< Receiver Time-Out enable */
|
|
|
8604 #define USART_CR2_ADD ((uint32_t)0xFF000000U) /*!< Address of the USART node */
|
|
|
8605
|
|
|
8606 /****************** Bit definition for USART_CR3 register *******************/
|
|
|
8607 #define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
|
|
|
8608 #define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
|
|
|
8609 #define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
|
|
|
8610 #define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
|
|
|
8611 #define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< SmartCard NACK enable */
|
|
|
8612 #define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< SmartCard mode enable */
|
|
|
8613 #define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
|
|
|
8614 #define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
|
|
|
8615 #define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
|
|
|
8616 #define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
|
|
|
8617 #define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
|
|
|
8618 #define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
|
|
|
8619 #define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /*!< Overrun Disable */
|
|
|
8620 #define USART_CR3_DDRE ((uint32_t)0x00002000U) /*!< DMA Disable on Reception Error */
|
|
|
8621 #define USART_CR3_DEM ((uint32_t)0x00004000U) /*!< Driver Enable Mode */
|
|
|
8622 #define USART_CR3_DEP ((uint32_t)0x00008000U) /*!< Driver Enable Polarity Selection */
|
|
|
8623 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
|
|
|
8624 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
|
|
|
8625 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
|
|
|
8626 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /*!< Bit 2 */
|
|
|
8627 #define USART_CR3_WUS ((uint32_t)0x00300000U) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
|
|
|
8628 #define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
|
|
|
8629 #define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
|
|
|
8630 #define USART_CR3_WUFIE ((uint32_t)0x00400000U) /*!< Wake Up Interrupt Enable */
|
|
|
8631
|
|
|
8632 /****************** Bit definition for USART_BRR register *******************/
|
|
|
8633 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000FU) /*!< Fraction of USARTDIV */
|
|
|
8634 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0U) /*!< Mantissa of USARTDIV */
|
|
|
8635
|
|
|
8636 /****************** Bit definition for USART_GTPR register ******************/
|
|
|
8637 #define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
|
|
|
8638 #define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< GT[7:0] bits (Guard time value) */
|
|
|
8639
|
|
|
8640
|
|
|
8641 /******************* Bit definition for USART_RTOR register *****************/
|
|
|
8642 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /*!< Receiver Time Out Value */
|
|
|
8643 #define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /*!< Block Length */
|
|
|
8644
|
|
|
8645 /******************* Bit definition for USART_RQR register ******************/
|
|
|
8646 #define USART_RQR_ABRRQ ((uint16_t)0x0001U) /*!< Auto-Baud Rate Request */
|
|
|
8647 #define USART_RQR_SBKRQ ((uint16_t)0x0002U) /*!< Send Break Request */
|
|
|
8648 #define USART_RQR_MMRQ ((uint16_t)0x0004U) /*!< Mute Mode Request */
|
|
|
8649 #define USART_RQR_RXFRQ ((uint16_t)0x0008U) /*!< Receive Data flush Request */
|
|
|
8650 #define USART_RQR_TXFRQ ((uint16_t)0x0010U) /*!< Transmit data flush Request */
|
|
|
8651
|
|
|
8652 /******************* Bit definition for USART_ISR register ******************/
|
|
|
8653 #define USART_ISR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
|
|
|
8654 #define USART_ISR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
|
|
|
8655 #define USART_ISR_NE ((uint32_t)0x00000004U) /*!< Noise detected Flag */
|
|
|
8656 #define USART_ISR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
|
|
|
8657 #define USART_ISR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
|
|
|
8658 #define USART_ISR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
|
|
|
8659 #define USART_ISR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
|
|
|
8660 #define USART_ISR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
|
|
|
8661 #define USART_ISR_LBDF ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
|
|
|
8662 #define USART_ISR_CTSIF ((uint32_t)0x00000200U) /*!< CTS interrupt flag */
|
|
|
8663 #define USART_ISR_CTS ((uint32_t)0x00000400U) /*!< CTS flag */
|
|
|
8664 #define USART_ISR_RTOF ((uint32_t)0x00000800U) /*!< Receiver Time Out */
|
|
|
8665 #define USART_ISR_EOBF ((uint32_t)0x00001000U) /*!< End Of Block Flag */
|
|
|
8666 #define USART_ISR_ABRE ((uint32_t)0x00004000U) /*!< Auto-Baud Rate Error */
|
|
|
8667 #define USART_ISR_ABRF ((uint32_t)0x00008000U) /*!< Auto-Baud Rate Flag */
|
|
|
8668 #define USART_ISR_BUSY ((uint32_t)0x00010000U) /*!< Busy Flag */
|
|
|
8669 #define USART_ISR_CMF ((uint32_t)0x00020000U) /*!< Character Match Flag */
|
|
|
8670 #define USART_ISR_SBKF ((uint32_t)0x00040000U) /*!< Send Break Flag */
|
|
|
8671 #define USART_ISR_RWU ((uint32_t)0x00080000U) /*!< Receive Wake Up from mute mode Flag */
|
|
|
8672 #define USART_ISR_WUF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Flag */
|
|
|
8673 #define USART_ISR_TEACK ((uint32_t)0x00200000U) /*!< Transmit Enable Acknowledge Flag */
|
|
|
8674 #define USART_ISR_REACK ((uint32_t)0x00400000U) /*!< Receive Enable Acknowledge Flag */
|
|
|
8675
|
|
|
8676 /******************* Bit definition for USART_ICR register ******************/
|
|
|
8677 #define USART_ICR_PECF ((uint32_t)0x00000001U) /*!< Parity Error Clear Flag */
|
|
|
8678 #define USART_ICR_FECF ((uint32_t)0x00000002U) /*!< Framing Error Clear Flag */
|
|
|
8679 #define USART_ICR_NCF ((uint32_t)0x00000004U) /*!< Noise detected Clear Flag */
|
|
|
8680 #define USART_ICR_ORECF ((uint32_t)0x00000008U) /*!< OverRun Error Clear Flag */
|
|
|
8681 #define USART_ICR_IDLECF ((uint32_t)0x00000010U) /*!< IDLE line detected Clear Flag */
|
|
|
8682 #define USART_ICR_TCCF ((uint32_t)0x00000040U) /*!< Transmission Complete Clear Flag */
|
|
|
8683 #define USART_ICR_LBDCF ((uint32_t)0x00000100U) /*!< LIN Break Detection Clear Flag */
|
|
|
8684 #define USART_ICR_CTSCF ((uint32_t)0x00000200U) /*!< CTS Interrupt Clear Flag */
|
|
|
8685 #define USART_ICR_RTOCF ((uint32_t)0x00000800U) /*!< Receiver Time Out Clear Flag */
|
|
|
8686 #define USART_ICR_EOBCF ((uint32_t)0x00001000U) /*!< End Of Block Clear Flag */
|
|
|
8687 #define USART_ICR_CMCF ((uint32_t)0x00020000U) /*!< Character Match Clear Flag */
|
|
|
8688 #define USART_ICR_WUCF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Clear Flag */
|
|
|
8689
|
|
|
8690 /******************* Bit definition for USART_RDR register ******************/
|
|
|
8691 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
|
|
|
8692
|
|
|
8693 /******************* Bit definition for USART_TDR register ******************/
|
|
|
8694 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
|
|
|
8695
|
|
|
8696 /******************************************************************************/
|
|
|
8697 /* */
|
|
|
8698 /* Single Wire Protocol Master Interface (SWPMI) */
|
|
|
8699 /* */
|
|
|
8700 /******************************************************************************/
|
|
|
8701
|
|
|
8702 /******************* Bit definition for SWPMI_CR register ********************/
|
|
|
8703 #define SWPMI_CR_RXDMA ((uint32_t)0x00000001U) /*!<Reception DMA enable */
|
|
|
8704 #define SWPMI_CR_TXDMA ((uint32_t)0x00000002U) /*!<Transmission DMA enable */
|
|
|
8705 #define SWPMI_CR_RXMODE ((uint32_t)0x00000004U) /*!<Reception buffering mode */
|
|
|
8706 #define SWPMI_CR_TXMODE ((uint32_t)0x00000008U) /*!<Transmission buffering mode */
|
|
|
8707 #define SWPMI_CR_LPBK ((uint32_t)0x00000010U) /*!<Loopback mode enable */
|
|
|
8708 #define SWPMI_CR_SWPACT ((uint32_t)0x00000020U) /*!<Single wire protocol master interface activate */
|
|
|
8709 #define SWPMI_CR_DEACT ((uint32_t)0x00000400U) /*!<Single wire protocol master interface deactivate */
|
|
|
8710
|
|
|
8711 /******************* Bit definition for SWPMI_BRR register ********************/
|
|
|
8712 #define SWPMI_BRR_BR ((uint32_t)0x0000003FU) /*!<BR[5:0] bits (Bitrate prescaler) */
|
|
|
8713
|
|
|
8714 /******************* Bit definition for SWPMI_ISR register ********************/
|
|
|
8715 #define SWPMI_ISR_RXBFF ((uint32_t)0x00000001U) /*!<Receive buffer full flag */
|
|
|
8716 #define SWPMI_ISR_TXBEF ((uint32_t)0x00000002U) /*!<Transmit buffer empty flag */
|
|
|
8717 #define SWPMI_ISR_RXBERF ((uint32_t)0x00000004U) /*!<Receive CRC error flag */
|
|
|
8718 #define SWPMI_ISR_RXOVRF ((uint32_t)0x00000008U) /*!<Receive overrun error flag */
|
|
|
8719 #define SWPMI_ISR_TXUNRF ((uint32_t)0x00000010U) /*!<Transmit underrun error flag */
|
|
|
8720 #define SWPMI_ISR_RXNE ((uint32_t)0x00000020U) /*!<Receive data register not empty */
|
|
|
8721 #define SWPMI_ISR_TXE ((uint32_t)0x00000040U) /*!<Transmit data register empty */
|
|
|
8722 #define SWPMI_ISR_TCF ((uint32_t)0x00000080U) /*!<Transfer complete flag */
|
|
|
8723 #define SWPMI_ISR_SRF ((uint32_t)0x00000100U) /*!<Slave resume flag */
|
|
|
8724 #define SWPMI_ISR_SUSP ((uint32_t)0x00000200U) /*!<SUSPEND flag */
|
|
|
8725 #define SWPMI_ISR_DEACTF ((uint32_t)0x00000400U) /*!<DEACTIVATED flag */
|
|
|
8726
|
|
|
8727 /******************* Bit definition for SWPMI_ICR register ********************/
|
|
|
8728 #define SWPMI_ICR_CRXBFF ((uint32_t)0x00000001U) /*!<Clear receive buffer full flag */
|
|
|
8729 #define SWPMI_ICR_CTXBEF ((uint32_t)0x00000002U) /*!<Clear transmit buffer empty flag */
|
|
|
8730 #define SWPMI_ICR_CRXBERF ((uint32_t)0x00000004U) /*!<Clear receive CRC error flag */
|
|
|
8731 #define SWPMI_ICR_CRXOVRF ((uint32_t)0x00000008U) /*!<Clear receive overrun error flag */
|
|
|
8732 #define SWPMI_ICR_CTXUNRF ((uint32_t)0x00000010U) /*!<Clear transmit underrun error flag */
|
|
|
8733 #define SWPMI_ICR_CTCF ((uint32_t)0x00000080U) /*!<Clear transfer complete flag */
|
|
|
8734 #define SWPMI_ICR_CSRF ((uint32_t)0x00000100U) /*!<Clear slave resume flag */
|
|
|
8735
|
|
|
8736 /******************* Bit definition for SWPMI_IER register ********************/
|
|
|
8737 #define SWPMI_IER_SRIE ((uint32_t)0x00000100U) /*!<Slave resume interrupt enable */
|
|
|
8738 #define SWPMI_IER_TCIE ((uint32_t)0x00000080U) /*!<Transmit complete interrupt enable */
|
|
|
8739 #define SWPMI_IER_TIE ((uint32_t)0x00000040U) /*!<Transmit interrupt enable */
|
|
|
8740 #define SWPMI_IER_RIE ((uint32_t)0x00000020U) /*!<Receive interrupt enable */
|
|
|
8741 #define SWPMI_IER_TXUNRIE ((uint32_t)0x00000010U) /*!<Transmit underrun error interrupt enable */
|
|
|
8742 #define SWPMI_IER_RXOVRIE ((uint32_t)0x00000008U) /*!<Receive overrun error interrupt enable */
|
|
|
8743 #define SWPMI_IER_RXBERIE ((uint32_t)0x00000004U) /*!<Receive CRC error interrupt enable */
|
|
|
8744 #define SWPMI_IER_TXBEIE ((uint32_t)0x00000002U) /*!<Transmit buffer empty interrupt enable */
|
|
|
8745 #define SWPMI_IER_RXBFIE ((uint32_t)0x00000001U) /*!<Receive buffer full interrupt enable */
|
|
|
8746
|
|
|
8747 /******************* Bit definition for SWPMI_RFL register ********************/
|
|
|
8748 #define SWPMI_RFL_RFL ((uint32_t)0x0000001FU) /*!<RFL[4:0] bits (Receive Frame length) */
|
|
|
8749 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
|
|
8750
|
|
|
8751 /******************* Bit definition for SWPMI_TDR register ********************/
|
|
|
8752 #define SWPMI_TDR_TD ((uint32_t)0xFFFFFFFFU) /*!<Transmit Data Register */
|
|
|
8753
|
|
|
8754 /******************* Bit definition for SWPMI_RDR register ********************/
|
|
|
8755 #define SWPMI_RDR_RD ((uint32_t)0xFFFFFFFFU) /*!<Receive Data Register */
|
|
|
8756
|
|
|
8757 /******************* Bit definition for SWPMI_OR register ********************/
|
|
|
8758 #define SWPMI_OR_TBYP ((uint32_t)0x00000001U) /*!<SWP Transceiver Bypass */
|
|
|
8759 #define SWPMI_OR_CLASS ((uint32_t)0x00000002U) /*!<SWP Voltage Class selection */
|
|
|
8760
|
|
|
8761 /******************************************************************************/
|
|
|
8762 /* */
|
|
|
8763 /* VREFBUF */
|
|
|
8764 /* */
|
|
|
8765 /******************************************************************************/
|
|
|
8766 /******************* Bit definition for VREFBUF_CSR register ****************/
|
|
|
8767 #define VREFBUF_CSR_ENVR ((uint32_t)0x00000001U) /*!<Voltage reference buffer enable */
|
|
|
8768 #define VREFBUF_CSR_HIZ ((uint32_t)0x00000002U) /*!<High impedance mode */
|
|
|
8769 #define VREFBUF_CSR_VRS ((uint32_t)0x00000004U) /*!<Voltage reference scale */
|
|
|
8770 #define VREFBUF_CSR_VRR ((uint32_t)0x00000008U) /*!<Voltage reference buffer ready */
|
|
|
8771
|
|
|
8772 /******************* Bit definition for VREFBUF_CCR register ******************/
|
|
|
8773 #define VREFBUF_CCR_TRIM ((uint32_t)0x0000003FU) /*!<TRIM[5:0] bits (Trimming code) */
|
|
|
8774
|
|
|
8775 /******************************************************************************/
|
|
|
8776 /* */
|
|
|
8777 /* Window WATCHDOG */
|
|
|
8778 /* */
|
|
|
8779 /******************************************************************************/
|
|
|
8780 /******************* Bit definition for WWDG_CR register ********************/
|
|
|
8781 #define WWDG_CR_T ((uint32_t)0x0000007FU) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
|
|
8782 #define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
8783 #define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
8784 #define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
8785 #define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
8786 #define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
8787 #define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
8788 #define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
8789
|
|
|
8790 #define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!<Activation bit */
|
|
|
8791
|
|
|
8792 /******************* Bit definition for WWDG_CFR register *******************/
|
|
|
8793 #define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!<W[6:0] bits (7-bit window value) */
|
|
|
8794 #define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
8795 #define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
8796 #define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
8797 #define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
8798 #define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
8799 #define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
8800 #define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
8801
|
|
|
8802 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!<WDGTB[1:0] bits (Timer Base) */
|
|
|
8803 #define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
|
|
|
8804 #define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
|
|
|
8805
|
|
|
8806 #define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!<Early Wakeup Interrupt */
|
|
|
8807
|
|
|
8808 /******************* Bit definition for WWDG_SR register ********************/
|
|
|
8809 #define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!<Early Wakeup Interrupt Flag */
|
|
|
8810
|
|
|
8811
|
|
|
8812 /******************************************************************************/
|
|
|
8813 /* */
|
|
|
8814 /* Debug MCU */
|
|
|
8815 /* */
|
|
|
8816 /******************************************************************************/
|
|
|
8817 /******************** Bit definition for DBGMCU_IDCODE register *************/
|
|
|
8818 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU)
|
|
|
8819 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U)
|
|
|
8820
|
|
|
8821 /******************** Bit definition for DBGMCU_CR register *****************/
|
|
|
8822 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U)
|
|
|
8823 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U)
|
|
|
8824 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U)
|
|
|
8825 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020U)
|
|
|
8826
|
|
|
8827 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0U)
|
|
|
8828 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040U)/*!<Bit 0 */
|
|
|
8829 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080U)/*!<Bit 1 */
|
|
|
8830
|
|
|
8831 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
|
|
|
8832 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP ((uint32_t)0x00000001U)
|
|
|
8833 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP ((uint32_t)0x00000002U)
|
|
|
8834 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP ((uint32_t)0x00000004U)
|
|
|
8835 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP ((uint32_t)0x00000008U)
|
|
|
8836 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP ((uint32_t)0x00000010U)
|
|
|
8837 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP ((uint32_t)0x00000020U)
|
|
|
8838 #define DBGMCU_APB1FZR1_DBG_RTC_STOP ((uint32_t)0x00000400U)
|
|
|
8839 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP ((uint32_t)0x00000800U)
|
|
|
8840 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP ((uint32_t)0x00001000U)
|
|
|
8841 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP ((uint32_t)0x00200000U)
|
|
|
8842 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP ((uint32_t)0x00400000U)
|
|
|
8843 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP ((uint32_t)0x00800000U)
|
|
|
8844 #define DBGMCU_APB1FZR1_DBG_CAN_STOP ((uint32_t)0x02000000U)
|
|
|
8845 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP ((uint32_t)0x80000000U)
|
|
|
8846
|
|
|
8847 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
|
|
|
8848 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP ((uint32_t)0x00000020U)
|
|
|
8849
|
|
|
8850 /******************** Bit definition for DBGMCU_APB2FZ register ************/
|
|
|
8851 #define DBGMCU_APB2FZ_DBG_TIM1_STOP ((uint32_t)0x00000800U)
|
|
|
8852 #define DBGMCU_APB2FZ_DBG_TIM8_STOP ((uint32_t)0x00002000U)
|
|
|
8853 #define DBGMCU_APB2FZ_DBG_TIM15_STOP ((uint32_t)0x00010000U)
|
|
|
8854 #define DBGMCU_APB2FZ_DBG_TIM16_STOP ((uint32_t)0x00020000U)
|
|
|
8855 #define DBGMCU_APB2FZ_DBG_TIM17_STOP ((uint32_t)0x00040000U)
|
|
|
8856
|
|
|
8857 /******************************************************************************/
|
|
|
8858 /* */
|
|
|
8859 /* USB_OTG */
|
|
|
8860 /* */
|
|
|
8861 /******************************************************************************/
|
|
|
8862 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
|
|
|
8863 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001U) /*!< Session request success */
|
|
|
8864 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002U) /*!< Session request */
|
|
|
8865 #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004U) /*!< VBUS valid override enable */
|
|
|
8866 #define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008U) /*!< VBUS valid override value */
|
|
|
8867 #define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010U) /*!< A-peripheral session valid override enable */
|
|
|
8868 #define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020U) /*!< A-peripheral session valid override value */
|
|
|
8869 #define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040U) /*!< B-peripheral session valid override enable */
|
|
|
8870 #define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080U) /*!< B-peripheral session valid override value */
|
|
|
8871 #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000U) /*!< B-session valid*/
|
|
|
8872
|
|
|
8873 /******************** Bit definition for USB_OTG_HCFG register ********************/
|
|
|
8874
|
|
|
8875 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003U) /*!< FS/LS PHY clock select */
|
|
|
8876 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
8877 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
8878 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004U) /*!< FS- and LS-only support */
|
|
|
8879
|
|
|
8880 /******************** Bit definition for USB_OTG_DCFG register ********************/
|
|
|
8881
|
|
|
8882 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003U) /*!< Device speed */
|
|
|
8883 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
8884 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
8885 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004U) /*!< Nonzero-length status OUT handshake */
|
|
|
8886 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0U) /*!< Device address */
|
|
|
8887 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
8888 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
8889 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
8890 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
|
|
|
8891 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100U) /*!<Bit 4 */
|
|
|
8892 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200U) /*!<Bit 5 */
|
|
|
8893 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400U) /*!<Bit 6 */
|
|
|
8894 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800U) /*!< Periodic (micro)frame interval */
|
|
|
8895 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800U) /*!<Bit 0 */
|
|
|
8896 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000U) /*!<Bit 1 */
|
|
|
8897 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000U) /*!< Periodic scheduling interval */
|
|
|
8898 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
8899 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
8900
|
|
|
8901 /******************** Bit definition for USB_OTG_PCGCR register ********************/
|
|
|
8902 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001U) /*!< Stop PHY clock */
|
|
|
8903 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002U) /*!< Gate HCLK */
|
|
|
8904 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010U) /*!< PHY suspended */
|
|
|
8905
|
|
|
8906 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
|
|
|
8907 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004U) /*!< Session end detected */
|
|
|
8908 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100U) /*!< Session request success status change */
|
|
|
8909 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200U) /*!< Host negotiation success status change */
|
|
|
8910 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000U) /*!< Host negotiation detected */
|
|
|
8911 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000U) /*!< A-device timeout change */
|
|
|
8912 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000U) /*!< Debounce done */
|
|
|
8913
|
|
|
8914 /******************** Bit definition for USB_OTG_DCTL register ********************/
|
|
|
8915 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001U) /*!< Remote wakeup signaling */
|
|
|
8916 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002U) /*!< Soft disconnect */
|
|
|
8917 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004U) /*!< Global IN NAK status */
|
|
|
8918 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008U) /*!< Global OUT NAK status */
|
|
|
8919
|
|
|
8920 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070U) /*!< Test control */
|
|
|
8921 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
|
|
|
8922 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
|
|
|
8923 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
|
|
|
8924 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080U) /*!< Set global IN NAK */
|
|
|
8925 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100U) /*!< Clear global IN NAK */
|
|
|
8926 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200U) /*!< Set global OUT NAK */
|
|
|
8927 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400U) /*!< Clear global OUT NAK */
|
|
|
8928 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800U) /*!< Power-on programming done */
|
|
|
8929
|
|
|
8930 /******************** Bit definition for USB_OTG_HFIR register ********************/
|
|
|
8931 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFFU) /*!< Frame interval */
|
|
|
8932
|
|
|
8933 /******************** Bit definition for USB_OTG_HFNUM register ********************/
|
|
|
8934 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFFU) /*!< Frame number */
|
|
|
8935 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000U) /*!< Frame time remaining */
|
|
|
8936
|
|
|
8937 /******************** Bit definition for USB_OTG_DSTS register ********************/
|
|
|
8938 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001U) /*!< Suspend status */
|
|
|
8939
|
|
|
8940 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006U) /*!< Enumerated speed */
|
|
|
8941 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
|
|
|
8942 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
|
|
|
8943 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008U) /*!< Erratic error */
|
|
|
8944 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00U) /*!< Frame number of the received SOF */
|
|
|
8945
|
|
|
8946 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
|
|
|
8947 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001U) /*!< Global interrupt mask */
|
|
|
8948 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001EU) /*!< Burst length/type */
|
|
|
8949 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
|
|
|
8950 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
|
|
|
8951 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008U) /*!<Bit 2 */
|
|
|
8952 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010U) /*!<Bit 3 */
|
|
|
8953 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020U) /*!< DMA enable */
|
|
|
8954 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080U) /*!< TxFIFO empty level */
|
|
|
8955 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100U) /*!< Periodic TxFIFO empty level */
|
|
|
8956
|
|
|
8957 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
|
|
|
8958
|
|
|
8959 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007U) /*!< FS timeout calibration */
|
|
|
8960 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
8961 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
8962 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
8963 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040U) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
|
|
|
8964 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100U) /*!< SRP-capable */
|
|
|
8965 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200U) /*!< HNP-capable */
|
|
|
8966 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00U) /*!< USB turnaround time */
|
|
|
8967 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
|
|
|
8968 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
|
|
|
8969 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000U) /*!<Bit 2 */
|
|
|
8970 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000U) /*!<Bit 3 */
|
|
|
8971 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000U) /*!< PHY Low-power clock select */
|
|
|
8972 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000U) /*!< ULPI FS/LS select */
|
|
|
8973 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000U) /*!< ULPI Auto-resume */
|
|
|
8974 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000U) /*!< ULPI Clock SuspendM */
|
|
|
8975 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000U) /*!< ULPI External VBUS Drive */
|
|
|
8976 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000U) /*!< ULPI external VBUS indicator */
|
|
|
8977 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000U) /*!< TermSel DLine pulsing selection */
|
|
|
8978 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000U) /*!< Indicator complement */
|
|
|
8979 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000U) /*!< Indicator pass through */
|
|
|
8980 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000U) /*!< ULPI interface protect disable */
|
|
|
8981 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000U) /*!< Forced host mode */
|
|
|
8982 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000U) /*!< Forced peripheral mode */
|
|
|
8983 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000U) /*!< Corrupt Tx packet */
|
|
|
8984
|
|
|
8985 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
|
|
|
8986 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001U) /*!< Core soft reset */
|
|
|
8987 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002U) /*!< HCLK soft reset */
|
|
|
8988 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004U) /*!< Host frame counter reset */
|
|
|
8989 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010U) /*!< RxFIFO flush */
|
|
|
8990 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020U) /*!< TxFIFO flush */
|
|
|
8991 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0U) /*!< TxFIFO number */
|
|
|
8992 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
|
|
|
8993 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
|
|
|
8994 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100U) /*!<Bit 2 */
|
|
|
8995 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200U) /*!<Bit 3 */
|
|
|
8996 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400U) /*!<Bit 4 */
|
|
|
8997 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000U) /*!< DMA request signal */
|
|
|
8998 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000U) /*!< AHB master idle */
|
|
|
8999
|
|
|
9000 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
|
|
|
9001 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed interrupt mask */
|
|
|
9002 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt mask */
|
|
|
9003 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008U) /*!< Timeout condition mask (nonisochronous endpoints) */
|
|
|
9004 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010U) /*!< IN token received when TxFIFO empty mask */
|
|
|
9005 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020U) /*!< IN token received with EP mismatch mask */
|
|
|
9006 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040U) /*!< IN endpoint NAK effective mask */
|
|
|
9007 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100U) /*!< FIFO underrun mask */
|
|
|
9008 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200U) /*!< BNA interrupt mask */
|
|
|
9009
|
|
|
9010 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
|
|
|
9011 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFFU) /*!< Periodic transmit data FIFO space available */
|
|
|
9012 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000U) /*!< Periodic transmit request queue space available */
|
|
|
9013 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
9014 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
9015 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
9016 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
|
|
|
9017 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
|
|
|
9018 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
|
|
|
9019 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
|
|
|
9020 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
|
|
|
9021
|
|
|
9022 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000U) /*!< Top of the periodic transmit request queue */
|
|
|
9023 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
9024 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
9025 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
9026 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
9027 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
|
|
|
9028 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
|
|
|
9029 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
|
|
|
9030 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000U) /*!<Bit 7 */
|
|
|
9031
|
|
|
9032 /******************** Bit definition for USB_OTG_HAINT register ********************/
|
|
|
9033 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFFU) /*!< Channel interrupts */
|
|
|
9034
|
|
|
9035 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
|
|
|
9036 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed interrupt mask */
|
|
|
9037 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt mask */
|
|
|
9038 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008U) /*!< SETUP phase done mask */
|
|
|
9039 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010U) /*!< OUT token received when endpoint disabled mask */
|
|
|
9040 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040U) /*!< Back-to-back SETUP packets received mask */
|
|
|
9041 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100U) /*!< OUT packet error mask */
|
|
|
9042 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200U) /*!< BNA interrupt mask */
|
|
|
9043
|
|
|
9044 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
|
|
|
9045 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001U) /*!< Current mode of operation */
|
|
|
9046 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002U) /*!< Mode mismatch interrupt */
|
|
|
9047 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004U) /*!< OTG interrupt */
|
|
|
9048 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008U) /*!< Start of frame */
|
|
|
9049 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010U) /*!< RxFIFO nonempty */
|
|
|
9050 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020U) /*!< Nonperiodic TxFIFO empty */
|
|
|
9051 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040U) /*!< Global IN nonperiodic NAK effective */
|
|
|
9052 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080U) /*!< Global OUT NAK effective */
|
|
|
9053 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400U) /*!< Early suspend */
|
|
|
9054 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800U) /*!< USB suspend */
|
|
|
9055 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000U) /*!< USB reset */
|
|
|
9056 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000U) /*!< Enumeration done */
|
|
|
9057 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000U) /*!< Isochronous OUT packet dropped interrupt */
|
|
|
9058 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000U) /*!< End of periodic frame interrupt */
|
|
|
9059 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000U) /*!< IN endpoint interrupt */
|
|
|
9060 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000U) /*!< OUT endpoint interrupt */
|
|
|
9061 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000U) /*!< Incomplete isochronous IN transfer */
|
|
|
9062 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000U) /*!< Incomplete periodic transfer */
|
|
|
9063 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000U) /*!< Data fetch suspended */
|
|
|
9064 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000U) /*!< Host port interrupt */
|
|
|
9065 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000U) /*!< Host channels interrupt */
|
|
|
9066 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000U) /*!< Periodic TxFIFO empty */
|
|
|
9067 #define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000U) /*!< LPM interrupt */
|
|
|
9068 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000U) /*!< Connector ID status change */
|
|
|
9069 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000U) /*!< Disconnect detected interrupt */
|
|
|
9070 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000U) /*!< Session request/new session detected interrupt */
|
|
|
9071 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000U) /*!< Resume/remote wakeup detected interrupt */
|
|
|
9072
|
|
|
9073 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
|
|
|
9074
|
|
|
9075 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002U) /*!< Mode mismatch interrupt mask */
|
|
|
9076 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004U) /*!< OTG interrupt mask */
|
|
|
9077 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008U) /*!< Start of frame mask */
|
|
|
9078 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010U) /*!< Receive FIFO nonempty mask */
|
|
|
9079 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020U) /*!< Nonperiodic TxFIFO empty mask */
|
|
|
9080 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040U) /*!< Global nonperiodic IN NAK effective mask */
|
|
|
9081 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080U) /*!< Global OUT NAK effective mask */
|
|
|
9082 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400U) /*!< Early suspend mask */
|
|
|
9083 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800U) /*!< USB suspend mask */
|
|
|
9084 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000U) /*!< USB reset mask */
|
|
|
9085 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000U) /*!< Enumeration done mask */
|
|
|
9086 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000U) /*!< Isochronous OUT packet dropped interrupt mask */
|
|
|
9087 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000U) /*!< End of periodic frame interrupt mask */
|
|
|
9088 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000U) /*!< Endpoint mismatch interrupt mask */
|
|
|
9089 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000U) /*!< IN endpoints interrupt mask */
|
|
|
9090 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000U) /*!< OUT endpoints interrupt mask */
|
|
|
9091 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000U) /*!< Incomplete isochronous IN transfer mask */
|
|
|
9092 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000U) /*!< Incomplete periodic transfer mask */
|
|
|
9093 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000U) /*!< Data fetch suspended mask */
|
|
|
9094 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000U) /*!< Host port interrupt mask */
|
|
|
9095 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000U) /*!< Host channels interrupt mask */
|
|
|
9096 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000U) /*!< Periodic TxFIFO empty mask */
|
|
|
9097 #define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000U) /*!< LPM interrupt Mask */
|
|
|
9098 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000U) /*!< Connector ID status change mask */
|
|
|
9099 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000U) /*!< Disconnect detected interrupt mask */
|
|
|
9100 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000U) /*!< Session request/new session detected interrupt mask */
|
|
|
9101 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000U) /*!< Resume/remote wakeup detected interrupt mask */
|
|
|
9102
|
|
|
9103 /******************** Bit definition for USB_OTG_DAINT register ********************/
|
|
|
9104 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFFU) /*!< IN endpoint interrupt bits */
|
|
|
9105 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000U) /*!< OUT endpoint interrupt bits */
|
|
|
9106
|
|
|
9107 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
|
|
|
9108 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFFU) /*!< Channel interrupt mask */
|
|
|
9109
|
|
|
9110 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
|
|
|
9111 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000FU) /*!< IN EP interrupt mask bits */
|
|
|
9112 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0U) /*!< OUT EP interrupt mask bits */
|
|
|
9113 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000U) /*!< OUT EP interrupt mask bits */
|
|
|
9114 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000U) /*!< OUT EP interrupt mask bits */
|
|
|
9115
|
|
|
9116 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
|
|
|
9117 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFFU) /*!< IN EP interrupt mask bits */
|
|
|
9118 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000U) /*!< OUT EP interrupt mask bits */
|
|
|
9119
|
|
|
9120 /******************** Bit definition for OTG register ********************/
|
|
|
9121
|
|
|
9122 #define USB_OTG_CHNUM ((uint32_t)0x0000000FU) /*!< Channel number */
|
|
|
9123 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
9124 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
9125 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
9126 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
9127 #define USB_OTG_BCNT ((uint32_t)0x00007FF0U) /*!< Byte count */
|
|
|
9128 #define USB_OTG_DPID ((uint32_t)0x00018000U) /*!< Data PID */
|
|
|
9129 #define USB_OTG_DPID_0 ((uint32_t)0x00008000U) /*!<Bit 0 */
|
|
|
9130 #define USB_OTG_DPID_1 ((uint32_t)0x00010000U) /*!<Bit 1 */
|
|
|
9131 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000U) /*!< Packet status */
|
|
|
9132 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
|
|
|
9133 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
|
|
|
9134 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
|
|
|
9135 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
|
|
|
9136 #define USB_OTG_EPNUM ((uint32_t)0x0000000FU) /*!< Endpoint number */
|
|
|
9137 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
9138 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
9139 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
9140 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
9141 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000U) /*!< Frame number */
|
|
|
9142 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000U) /*!<Bit 0 */
|
|
|
9143 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000U) /*!<Bit 1 */
|
|
|
9144 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000U) /*!<Bit 2 */
|
|
|
9145 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
|
|
|
9146
|
|
|
9147 /******************** Bit definition for OTG register ********************/
|
|
|
9148
|
|
|
9149 #define USB_OTG_CHNUM ((uint32_t)0x0000000FU) /*!< Channel number */
|
|
|
9150 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
9151 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
9152 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
9153 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
9154 #define USB_OTG_BCNT ((uint32_t)0x00007FF0U) /*!< Byte count */
|
|
|
9155 #define USB_OTG_DPID ((uint32_t)0x00018000U) /*!< Data PID */
|
|
|
9156 #define USB_OTG_DPID_0 ((uint32_t)0x00008000U) /*!<Bit 0 */
|
|
|
9157 #define USB_OTG_DPID_1 ((uint32_t)0x00010000U) /*!<Bit 1 */
|
|
|
9158 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000U) /*!< Packet status */
|
|
|
9159 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
|
|
|
9160 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
|
|
|
9161 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
|
|
|
9162 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
|
|
|
9163 #define USB_OTG_EPNUM ((uint32_t)0x0000000FU) /*!< Endpoint number */
|
|
|
9164 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
9165 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
9166 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
9167 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
9168 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000U) /*!< Frame number */
|
|
|
9169 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000U) /*!<Bit 0 */
|
|
|
9170 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000U) /*!<Bit 1 */
|
|
|
9171 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000U) /*!<Bit 2 */
|
|
|
9172 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
|
|
|
9173
|
|
|
9174 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
|
|
|
9175 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFFU) /*!< RxFIFO depth */
|
|
|
9176
|
|
|
9177 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
|
|
|
9178 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFFU) /*!< Device VBUS discharge time */
|
|
|
9179
|
|
|
9180 /******************** Bit definition for OTG register ********************/
|
|
|
9181 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFFU) /*!< Nonperiodic transmit RAM start address */
|
|
|
9182 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000U) /*!< Nonperiodic TxFIFO depth */
|
|
|
9183 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFFU) /*!< Endpoint 0 transmit RAM start address */
|
|
|
9184 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000U) /*!< Endpoint 0 TxFIFO depth */
|
|
|
9185
|
|
|
9186 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
|
|
|
9187 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFFU) /*!< Device VBUS pulsing time */
|
|
|
9188
|
|
|
9189 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
|
|
|
9190 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFFU) /*!< Nonperiodic TxFIFO space available */
|
|
|
9191
|
|
|
9192 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000U) /*!< Nonperiodic transmit request queue space available */
|
|
|
9193 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
|
|
|
9194 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
|
|
|
9195 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
|
|
|
9196 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
|
|
|
9197 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
|
|
|
9198 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
|
|
|
9199 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
|
|
|
9200 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
|
|
|
9201
|
|
|
9202 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000U) /*!< Top of the nonperiodic transmit request queue */
|
|
|
9203 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
|
|
|
9204 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
|
|
|
9205 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
|
|
|
9206 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
|
|
|
9207 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
|
|
|
9208 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
|
|
|
9209 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
|
|
|
9210
|
|
|
9211 /******************** Bit definition for USB_OTG_DTHRCTL register ***************/
|
|
|
9212 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001U) /*!< Nonisochronous IN endpoints threshold enable */
|
|
|
9213 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002U) /*!< ISO IN endpoint threshold enable */
|
|
|
9214
|
|
|
9215 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FCU) /*!< Transmit threshold length */
|
|
|
9216 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
|
|
|
9217 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
|
|
|
9218 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010U) /*!<Bit 2 */
|
|
|
9219 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020U) /*!<Bit 3 */
|
|
|
9220 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040U) /*!<Bit 4 */
|
|
|
9221 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080U) /*!<Bit 5 */
|
|
|
9222 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100U) /*!<Bit 6 */
|
|
|
9223 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200U) /*!<Bit 7 */
|
|
|
9224 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400U) /*!<Bit 8 */
|
|
|
9225 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000U) /*!< Receive threshold enable */
|
|
|
9226
|
|
|
9227 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000U) /*!< Receive threshold length */
|
|
|
9228 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
|
|
|
9229 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
|
|
|
9230 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
|
|
|
9231 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
|
|
|
9232 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
|
|
|
9233 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
|
|
|
9234 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
|
|
|
9235 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000U) /*!<Bit 7 */
|
|
|
9236 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000U) /*!<Bit 8 */
|
|
|
9237 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000U) /*!< Arbiter parking enable */
|
|
|
9238
|
|
|
9239 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
|
|
|
9240 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFFU) /*!< IN EP Tx FIFO empty interrupt mask bits */
|
|
|
9241
|
|
|
9242 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
|
|
|
9243 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002U) /*!< IN endpoint 1interrupt bit */
|
|
|
9244 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000U) /*!< OUT endpoint 1 interrupt bit */
|
|
|
9245
|
|
|
9246 /******************** Bit definition for USB_OTG_GCCFG register ********************/
|
|
|
9247 #define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001U) /*!< Data contact detection (DCD) status */
|
|
|
9248 #define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002U) /*!< Primary detection (PD) status */
|
|
|
9249 #define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004U) /*!< Secondary detection (SD) status */
|
|
|
9250 #define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008U) /*!< DM pull-up detection status */
|
|
|
9251 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000U) /*!< Power down */
|
|
|
9252 #define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000U) /*!< Battery charging detector (BCD) enable */
|
|
|
9253 #define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000U) /*!< Data contact detection (DCD) mode enable*/
|
|
|
9254 #define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000U) /*!< Primary detection (PD) mode enable*/
|
|
|
9255 #define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000U) /*!< Secondary detection (SD) mode enable */
|
|
|
9256 #define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000U) /*!< Secondary detection (SD) mode enable */
|
|
|
9257
|
|
|
9258 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
|
|
|
9259 #define USB_OTG_GPWRDN_DISABLEVBUS ((uint32_t)0x00000040U) /*!< Power down */
|
|
|
9260
|
|
|
9261 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
|
|
|
9262 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002U) /*!< IN Endpoint 1 interrupt mask bit */
|
|
|
9263 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000U) /*!< OUT Endpoint 1 interrupt mask bit */
|
|
|
9264
|
|
|
9265 /******************** Bit definition for USB_OTG_CID register ********************/
|
|
|
9266 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFFU) /*!< Product ID field */
|
|
|
9267
|
|
|
9268
|
|
|
9269 /******************** Bit definition for USB_OTG_GHWCFG3 register ********************/
|
|
|
9270 #define USB_OTG_GHWCFG3_LPMMode ((uint32_t)0x00004000U) /* LPM mode specified for Mode of Operation */
|
|
|
9271
|
|
|
9272 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
|
|
|
9273 #define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000U) /* Enable best effort service latency */
|
|
|
9274 #define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000U) /* LPM retry count status */
|
|
|
9275 #define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000U) /* Send LPM transaction */
|
|
|
9276 #define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000U) /* LPM retry count */
|
|
|
9277 #define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000U) /* LPMCHIDX: */
|
|
|
9278 #define USB_OTG_GLPMCFG_L1ResumeOK ((uint32_t)0x00010000U) /* Sleep State Resume OK */
|
|
|
9279 #define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000U) /* Port sleep status */
|
|
|
9280 #define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000U) /* LPM response */
|
|
|
9281 #define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000U) /* L1 deep sleep enable */
|
|
|
9282 #define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00U) /* BESL threshold */
|
|
|
9283 #define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080U) /* L1 shallow sleep enable */
|
|
|
9284 #define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040U) /* bRemoteWake value received with last ACKed LPM Token */
|
|
|
9285 #define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003CU) /* BESL value received with last ACKed LPM Token */
|
|
|
9286 #define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002U) /* LPM Token acknowledge enable*/
|
|
|
9287 #define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001U) /* LPM support enable */
|
|
|
9288
|
|
|
9289
|
|
|
9290 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
|
|
|
9291 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed interrupt mask */
|
|
|
9292 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt mask */
|
|
|
9293 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008U) /*!< Timeout condition mask (nonisochronous endpoints) */
|
|
|
9294 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010U) /*!< IN token received when TxFIFO empty mask */
|
|
|
9295 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020U) /*!< IN token received with EP mismatch mask */
|
|
|
9296 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040U) /*!< IN endpoint NAK effective mask */
|
|
|
9297 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100U) /*!< FIFO underrun mask */
|
|
|
9298 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200U) /*!< BNA interrupt mask */
|
|
|
9299 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000U) /*!< NAK interrupt mask */
|
|
|
9300
|
|
|
9301 /******************** Bit definition for USB_OTG_HPRT register ********************/
|
|
|
9302 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001U) /*!< Port connect status */
|
|
|
9303 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002U) /*!< Port connect detected */
|
|
|
9304 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004U) /*!< Port enable */
|
|
|
9305 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008U) /*!< Port enable/disable change */
|
|
|
9306 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010U) /*!< Port overcurrent active */
|
|
|
9307 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020U) /*!< Port overcurrent change */
|
|
|
9308 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040U) /*!< Port resume */
|
|
|
9309 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080U) /*!< Port suspend */
|
|
|
9310 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100U) /*!< Port reset */
|
|
|
9311
|
|
|
9312 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00U) /*!< Port line status */
|
|
|
9313 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
|
|
|
9314 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
|
|
|
9315 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000U) /*!< Port power */
|
|
|
9316
|
|
|
9317 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000U) /*!< Port test control */
|
|
|
9318 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000U) /*!<Bit 0 */
|
|
|
9319 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000U) /*!<Bit 1 */
|
|
|
9320 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000U) /*!<Bit 2 */
|
|
|
9321 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
|
|
|
9322
|
|
|
9323 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000U) /*!< Port speed */
|
|
|
9324 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
|
|
|
9325 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
|
|
|
9326
|
|
|
9327 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
|
|
|
9328 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed interrupt mask */
|
|
|
9329 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt mask */
|
|
|
9330 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008U) /*!< Timeout condition mask */
|
|
|
9331 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010U) /*!< IN token received when TxFIFO empty mask */
|
|
|
9332 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020U) /*!< IN token received with EP mismatch mask */
|
|
|
9333 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040U) /*!< IN endpoint NAK effective mask */
|
|
|
9334 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100U) /*!< OUT packet error mask */
|
|
|
9335 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200U) /*!< BNA interrupt mask */
|
|
|
9336 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000U) /*!< Bubble error interrupt mask */
|
|
|
9337 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000U) /*!< NAK interrupt mask */
|
|
|
9338 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000U) /*!< NYET interrupt mask */
|
|
|
9339
|
|
|
9340 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
|
|
|
9341 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFFU) /*!< Host periodic TxFIFO start address */
|
|
|
9342 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000U) /*!< Host periodic TxFIFO depth */
|
|
|
9343
|
|
|
9344 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
|
|
|
9345 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FFU) /*!< Maximum packet size */
|
|
|
9346 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000U) /*!< USB active endpoint */
|
|
|
9347 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000U) /*!< Even/odd frame */
|
|
|
9348 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000U) /*!< NAK status */
|
|
|
9349
|
|
|
9350 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000U) /*!< Endpoint type */
|
|
|
9351 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000U) /*!<Bit 0 */
|
|
|
9352 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000U) /*!<Bit 1 */
|
|
|
9353 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000U) /*!< STALL handshake */
|
|
|
9354
|
|
|
9355 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000U) /*!< TxFIFO number */
|
|
|
9356 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
|
|
|
9357 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
|
|
|
9358 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000U) /*!<Bit 2 */
|
|
|
9359 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000U) /*!<Bit 3 */
|
|
|
9360 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000U) /*!< Clear NAK */
|
|
|
9361 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000U) /*!< Set NAK */
|
|
|
9362 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000U) /*!< Set DATA0 PID */
|
|
|
9363 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000U) /*!< Set odd frame */
|
|
|
9364 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000U) /*!< Endpoint disable */
|
|
|
9365 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000U) /*!< Endpoint enable */
|
|
|
9366
|
|
|
9367 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
|
|
|
9368 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FFU) /*!< Maximum packet size */
|
|
|
9369
|
|
|
9370 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800U) /*!< Endpoint number */
|
|
|
9371 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800U) /*!<Bit 0 */
|
|
|
9372 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000U) /*!<Bit 1 */
|
|
|
9373 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000U) /*!<Bit 2 */
|
|
|
9374 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000U) /*!<Bit 3 */
|
|
|
9375 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000U) /*!< Endpoint direction */
|
|
|
9376 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000U) /*!< Low-speed device */
|
|
|
9377
|
|
|
9378 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000U) /*!< Endpoint type */
|
|
|
9379 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000U) /*!<Bit 0 */
|
|
|
9380 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000U) /*!<Bit 1 */
|
|
|
9381
|
|
|
9382 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000U) /*!< Multi Count (MC) / Error Count (EC) */
|
|
|
9383 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
|
|
|
9384 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
|
|
|
9385
|
|
|
9386 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000U) /*!< Device address */
|
|
|
9387 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
|
|
|
9388 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
|
|
|
9389 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000U) /*!<Bit 2 */
|
|
|
9390 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000U) /*!<Bit 3 */
|
|
|
9391 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000U) /*!<Bit 4 */
|
|
|
9392 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000U) /*!<Bit 5 */
|
|
|
9393 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000U) /*!<Bit 6 */
|
|
|
9394 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000U) /*!< Odd frame */
|
|
|
9395 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000U) /*!< Channel disable */
|
|
|
9396 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000U) /*!< Channel enable */
|
|
|
9397
|
|
|
9398 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
|
|
|
9399
|
|
|
9400 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007FU) /*!< Port address */
|
|
|
9401 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
|
|
|
9402 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
|
|
|
9403 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
|
|
|
9404 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
|
|
|
9405 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
|
|
|
9406 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
|
|
|
9407 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
|
|
|
9408
|
|
|
9409 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80U) /*!< Hub address */
|
|
|
9410 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
|
|
|
9411 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
|
|
|
9412 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200U) /*!<Bit 2 */
|
|
|
9413 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400U) /*!<Bit 3 */
|
|
|
9414 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800U) /*!<Bit 4 */
|
|
|
9415 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000U) /*!<Bit 5 */
|
|
|
9416 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000U) /*!<Bit 6 */
|
|
|
9417
|
|
|
9418 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000U) /*!< XACTPOS */
|
|
|
9419 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
|
|
|
9420 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
|
|
|
9421 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000U) /*!< Do complete split */
|
|
|
9422 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000U) /*!< Split enable */
|
|
|
9423
|
|
|
9424 /******************** Bit definition for USB_OTG_HCINT register ********************/
|
|
|
9425 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001U) /*!< Transfer completed */
|
|
|
9426 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002U) /*!< Channel halted */
|
|
|
9427 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004U) /*!< AHB error */
|
|
|
9428 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008U) /*!< STALL response received interrupt */
|
|
|
9429 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010U) /*!< NAK response received interrupt */
|
|
|
9430 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020U) /*!< ACK response received/transmitted interrupt */
|
|
|
9431 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040U) /*!< Response received interrupt */
|
|
|
9432 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080U) /*!< Transaction error */
|
|
|
9433 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100U) /*!< Babble error */
|
|
|
9434 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200U) /*!< Frame overrun */
|
|
|
9435 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400U) /*!< Data toggle error */
|
|
|
9436
|
|
|
9437 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
|
|
|
9438 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001U) /*!< Transfer completed interrupt */
|
|
|
9439 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt */
|
|
|
9440 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008U) /*!< Timeout condition */
|
|
|
9441 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010U) /*!< IN token received when TxFIFO is empty */
|
|
|
9442 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040U) /*!< IN endpoint NAK effective */
|
|
|
9443 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080U) /*!< Transmit FIFO empty */
|
|
|
9444 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100U) /*!< Transmit Fifo Underrun */
|
|
|
9445 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200U) /*!< Buffer not available interrupt */
|
|
|
9446 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800U) /*!< Packet dropped status */
|
|
|
9447 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000U) /*!< Babble error interrupt */
|
|
|
9448 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000U) /*!< NAK interrupt */
|
|
|
9449
|
|
|
9450 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
|
|
|
9451 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed mask */
|
|
|
9452 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002U) /*!< Channel halted mask */
|
|
|
9453 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004U) /*!< AHB error */
|
|
|
9454 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008U) /*!< STALL response received interrupt mask */
|
|
|
9455 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010U) /*!< NAK response received interrupt mask */
|
|
|
9456 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020U) /*!< ACK response received/transmitted interrupt mask */
|
|
|
9457 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040U) /*!< response received interrupt mask */
|
|
|
9458 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080U) /*!< Transaction error mask */
|
|
|
9459 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100U) /*!< Babble error mask */
|
|
|
9460 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200U) /*!< Frame overrun mask */
|
|
|
9461 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400U) /*!< Data toggle error mask */
|
|
|
9462
|
|
|
9463 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
|
|
|
9464
|
|
|
9465 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFFU) /*!< Transfer size */
|
|
|
9466 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000U) /*!< Packet count */
|
|
|
9467 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000U) /*!< Packet count */
|
|
|
9468 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
|
|
|
9469 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFFU) /*!< Transfer size */
|
|
|
9470 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000U) /*!< Packet count */
|
|
|
9471 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000U) /*!< Do PING */
|
|
|
9472 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000U) /*!< Data PID */
|
|
|
9473 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000U) /*!<Bit 0 */
|
|
|
9474 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000U) /*!<Bit 1 */
|
|
|
9475
|
|
|
9476 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
|
|
|
9477 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFFU) /*!< DMA address */
|
|
|
9478
|
|
|
9479 /******************** Bit definition for USB_OTG_HCDMA register ********************/
|
|
|
9480 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFFU) /*!< DMA address */
|
|
|
9481
|
|
|
9482 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
|
|
|
9483 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFFU) /*!< IN endpoint TxFIFO space avail */
|
|
|
9484
|
|
|
9485 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
|
|
|
9486 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFFU) /*!< IN endpoint FIFOx transmit RAM start address */
|
|
|
9487 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000U) /*!< IN endpoint TxFIFO depth */
|
|
|
9488
|
|
|
9489 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
|
|
|
9490
|
|
|
9491 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FFU) /*!< Maximum packet size */ /*!<Bit 1 */
|
|
|
9492 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000U) /*!< USB active endpoint */
|
|
|
9493 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000U) /*!< NAK status */
|
|
|
9494 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000U) /*!< Set DATA0 PID */
|
|
|
9495 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000U) /*!< Set odd frame */
|
|
|
9496 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000U) /*!< Endpoint type */
|
|
|
9497 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000U) /*!<Bit 0 */
|
|
|
9498 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000U) /*!<Bit 1 */
|
|
|
9499 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000U) /*!< Snoop mode */
|
|
|
9500 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000U) /*!< STALL handshake */
|
|
|
9501 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000U) /*!< Clear NAK */
|
|
|
9502 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000U) /*!< Set NAK */
|
|
|
9503 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000U) /*!< Endpoint disable */
|
|
|
9504 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000U) /*!< Endpoint enable */
|
|
|
9505
|
|
|
9506 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
|
|
|
9507 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001U) /*!< Transfer completed interrupt */
|
|
|
9508 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt */
|
|
|
9509 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008U) /*!< SETUP phase done */
|
|
|
9510 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010U) /*!< OUT token received when endpoint disabled */
|
|
|
9511 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040U) /*!< Back-to-back SETUP packets received */
|
|
|
9512 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000U) /*!< NYET interrupt */
|
|
|
9513
|
|
|
9514 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
|
|
|
9515
|
|
|
9516 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFFU) /*!< Transfer size */
|
|
|
9517 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000U) /*!< Packet count */
|
|
|
9518
|
|
|
9519 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000U) /*!< SETUP packet count */
|
|
|
9520 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000U) /*!<Bit 0 */
|
|
|
9521 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000U) /*!<Bit 1 */
|
|
|
9522
|
|
|
9523 /******************** Bit definition for PCGCCTL register ********************/
|
|
|
9524 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001U) /*!< SETUP packet count */
|
|
|
9525 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002U) /*!<Bit 0 */
|
|
|
9526 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010U) /*!<Bit 1 */
|
|
|
9527
|
|
|
9528
|
|
|
9529 /**
|
|
|
9530 * @}
|
|
|
9531 */
|
|
|
9532
|
|
|
9533 /**
|
|
|
9534 * @}
|
|
|
9535 */
|
|
|
9536
|
|
|
9537 /** @addtogroup Exported_macros
|
|
|
9538 * @{
|
|
|
9539 */
|
|
|
9540
|
|
|
9541 /******************************* ADC Instances ********************************/
|
|
|
9542 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
|
|
|
9543 ((INSTANCE) == ADC2) || \
|
|
|
9544 ((INSTANCE) == ADC3))
|
|
|
9545
|
|
|
9546 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
|
|
|
9547
|
|
|
9548 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
|
|
|
9549
|
|
|
9550 /******************************** CAN Instances ******************************/
|
|
|
9551 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
|
|
|
9552
|
|
|
9553 /******************************** COMP Instances ******************************/
|
|
|
9554 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
|
|
|
9555 ((INSTANCE) == COMP2))
|
|
|
9556
|
|
|
9557 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
|
|
|
9558
|
|
|
9559 /******************** COMP Instances with window mode capability **************/
|
|
|
9560 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
|
|
|
9561
|
|
|
9562 /******************************* CRC Instances ********************************/
|
|
|
9563 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
|
|
|
9564
|
|
|
9565 /******************************* DAC Instances ********************************/
|
|
|
9566 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
|
|
|
9567
|
|
|
9568 /****************************** DFSDM Instances *******************************/
|
|
|
9569 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Filter0) || \
|
|
|
9570 ((INSTANCE) == DFSDM_Filter1) || \
|
|
|
9571 ((INSTANCE) == DFSDM_Filter2) || \
|
|
|
9572 ((INSTANCE) == DFSDM_Filter3))
|
|
|
9573
|
|
|
9574 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Channel0) || \
|
|
|
9575 ((INSTANCE) == DFSDM_Channel1) || \
|
|
|
9576 ((INSTANCE) == DFSDM_Channel2) || \
|
|
|
9577 ((INSTANCE) == DFSDM_Channel3) || \
|
|
|
9578 ((INSTANCE) == DFSDM_Channel4) || \
|
|
|
9579 ((INSTANCE) == DFSDM_Channel5) || \
|
|
|
9580 ((INSTANCE) == DFSDM_Channel6) || \
|
|
|
9581 ((INSTANCE) == DFSDM_Channel7))
|
|
|
9582
|
|
|
9583 /******************************** DMA Instances *******************************/
|
|
|
9584 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
|
|
|
9585 ((INSTANCE) == DMA1_Channel2) || \
|
|
|
9586 ((INSTANCE) == DMA1_Channel3) || \
|
|
|
9587 ((INSTANCE) == DMA1_Channel4) || \
|
|
|
9588 ((INSTANCE) == DMA1_Channel5) || \
|
|
|
9589 ((INSTANCE) == DMA1_Channel6) || \
|
|
|
9590 ((INSTANCE) == DMA1_Channel7) || \
|
|
|
9591 ((INSTANCE) == DMA2_Channel1) || \
|
|
|
9592 ((INSTANCE) == DMA2_Channel2) || \
|
|
|
9593 ((INSTANCE) == DMA2_Channel3) || \
|
|
|
9594 ((INSTANCE) == DMA2_Channel4) || \
|
|
|
9595 ((INSTANCE) == DMA2_Channel5) || \
|
|
|
9596 ((INSTANCE) == DMA2_Channel6) || \
|
|
|
9597 ((INSTANCE) == DMA2_Channel7))
|
|
|
9598
|
|
|
9599 /******************************* GPIO Instances *******************************/
|
|
|
9600 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
|
|
9601 ((INSTANCE) == GPIOB) || \
|
|
|
9602 ((INSTANCE) == GPIOC) || \
|
|
|
9603 ((INSTANCE) == GPIOD) || \
|
|
|
9604 ((INSTANCE) == GPIOE) || \
|
|
|
9605 ((INSTANCE) == GPIOF) || \
|
|
|
9606 ((INSTANCE) == GPIOG) || \
|
|
|
9607 ((INSTANCE) == GPIOH))
|
|
|
9608
|
|
|
9609 /******************************* GPIO AF Instances ****************************/
|
|
|
9610 /* On L4, all GPIO Bank support AF */
|
|
|
9611 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
|
|
|
9612
|
|
|
9613 /**************************** GPIO Lock Instances *****************************/
|
|
|
9614 /* On L4, all GPIO Bank support the Lock mechanism */
|
|
|
9615 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
|
|
|
9616
|
|
|
9617 /******************************** I2C Instances *******************************/
|
|
|
9618 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
|
|
9619 ((INSTANCE) == I2C2) || \
|
|
|
9620 ((INSTANCE) == I2C3))
|
|
|
9621
|
|
|
9622 /******************************* LCD Instances ********************************/
|
|
|
9623 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
|
|
|
9624
|
|
|
9625 /******************************* HCD Instances *******************************/
|
|
|
9626 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
|
|
|
9627
|
|
|
9628 /****************************** OPAMP Instances *******************************/
|
|
|
9629 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
|
|
|
9630 ((INSTANCE) == OPAMP2))
|
|
|
9631
|
|
|
9632 #define IS_OPAMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP12_COMMON)
|
|
|
9633
|
|
|
9634 /******************************* PCD Instances *******************************/
|
|
|
9635 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
|
|
|
9636
|
|
|
9637 /******************************* QSPI Instances *******************************/
|
|
|
9638 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
|
|
|
9639
|
|
|
9640 /******************************* RNG Instances ********************************/
|
|
|
9641 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
|
|
|
9642
|
|
|
9643 /****************************** RTC Instances *********************************/
|
|
|
9644 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
|
|
9645
|
|
|
9646 /******************************** SAI Instances *******************************/
|
|
|
9647 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
|
|
|
9648 ((INSTANCE) == SAI1_Block_B) || \
|
|
|
9649 ((INSTANCE) == SAI2_Block_A) || \
|
|
|
9650 ((INSTANCE) == SAI2_Block_B))
|
|
|
9651
|
|
|
9652 /****************************** SDMMC Instances *******************************/
|
|
|
9653 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
|
|
|
9654
|
|
|
9655 /****************************** SMBUS Instances *******************************/
|
|
|
9656 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
|
|
9657 ((INSTANCE) == I2C2) || \
|
|
|
9658 ((INSTANCE) == I2C3))
|
|
|
9659
|
|
|
9660 /******************************** SPI Instances *******************************/
|
|
|
9661 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
|
|
9662 ((INSTANCE) == SPI2) || \
|
|
|
9663 ((INSTANCE) == SPI3))
|
|
|
9664
|
|
|
9665 /******************************** SWPMI Instances *****************************/
|
|
|
9666 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
|
|
|
9667
|
|
|
9668 /****************** LPTIM Instances : All supported instances *****************/
|
|
|
9669 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
|
|
|
9670 ((INSTANCE) == LPTIM2))
|
|
|
9671
|
|
|
9672 /****************** TIM Instances : All supported instances *******************/
|
|
|
9673 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9674 ((INSTANCE) == TIM2) || \
|
|
|
9675 ((INSTANCE) == TIM3) || \
|
|
|
9676 ((INSTANCE) == TIM4) || \
|
|
|
9677 ((INSTANCE) == TIM5) || \
|
|
|
9678 ((INSTANCE) == TIM6) || \
|
|
|
9679 ((INSTANCE) == TIM7) || \
|
|
|
9680 ((INSTANCE) == TIM8) || \
|
|
|
9681 ((INSTANCE) == TIM15) || \
|
|
|
9682 ((INSTANCE) == TIM16) || \
|
|
|
9683 ((INSTANCE) == TIM17))
|
|
|
9684
|
|
|
9685 /****************** TIM Instances : supporting 32 bits counter ****************/
|
|
|
9686 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
|
|
9687 ((INSTANCE) == TIM5))
|
|
|
9688
|
|
|
9689 /****************** TIM Instances : supporting the break function *************/
|
|
|
9690 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9691 ((INSTANCE) == TIM8) || \
|
|
|
9692 ((INSTANCE) == TIM15) || \
|
|
|
9693 ((INSTANCE) == TIM16) || \
|
|
|
9694 ((INSTANCE) == TIM17))
|
|
|
9695
|
|
|
9696 /************** TIM Instances : supporting Break source selection *************/
|
|
|
9697 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9698 ((INSTANCE) == TIM8) || \
|
|
|
9699 ((INSTANCE) == TIM15) || \
|
|
|
9700 ((INSTANCE) == TIM16) || \
|
|
|
9701 ((INSTANCE) == TIM17))
|
|
|
9702
|
|
|
9703 /****************** TIM Instances : supporting 2 break inputs *****************/
|
|
|
9704 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9705 ((INSTANCE) == TIM8))
|
|
|
9706
|
|
|
9707 /************* TIM Instances : at least 1 capture/compare channel *************/
|
|
|
9708 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9709 ((INSTANCE) == TIM2) || \
|
|
|
9710 ((INSTANCE) == TIM3) || \
|
|
|
9711 ((INSTANCE) == TIM4) || \
|
|
|
9712 ((INSTANCE) == TIM5) || \
|
|
|
9713 ((INSTANCE) == TIM8) || \
|
|
|
9714 ((INSTANCE) == TIM15) || \
|
|
|
9715 ((INSTANCE) == TIM16) || \
|
|
|
9716 ((INSTANCE) == TIM17))
|
|
|
9717
|
|
|
9718 /************ TIM Instances : at least 2 capture/compare channels *************/
|
|
|
9719 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9720 ((INSTANCE) == TIM2) || \
|
|
|
9721 ((INSTANCE) == TIM3) || \
|
|
|
9722 ((INSTANCE) == TIM4) || \
|
|
|
9723 ((INSTANCE) == TIM5) || \
|
|
|
9724 ((INSTANCE) == TIM8) || \
|
|
|
9725 ((INSTANCE) == TIM15))
|
|
|
9726
|
|
|
9727 /************ TIM Instances : at least 3 capture/compare channels *************/
|
|
|
9728 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9729 ((INSTANCE) == TIM2) || \
|
|
|
9730 ((INSTANCE) == TIM3) || \
|
|
|
9731 ((INSTANCE) == TIM4) || \
|
|
|
9732 ((INSTANCE) == TIM5) || \
|
|
|
9733 ((INSTANCE) == TIM8))
|
|
|
9734
|
|
|
9735 /************ TIM Instances : at least 4 capture/compare channels *************/
|
|
|
9736 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9737 ((INSTANCE) == TIM2) || \
|
|
|
9738 ((INSTANCE) == TIM3) || \
|
|
|
9739 ((INSTANCE) == TIM4) || \
|
|
|
9740 ((INSTANCE) == TIM5) || \
|
|
|
9741 ((INSTANCE) == TIM8))
|
|
|
9742
|
|
|
9743 /****************** TIM Instances : at least 5 capture/compare channels *******/
|
|
|
9744 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9745 ((INSTANCE) == TIM8))
|
|
|
9746
|
|
|
9747 /****************** TIM Instances : at least 6 capture/compare channels *******/
|
|
|
9748 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9749 ((INSTANCE) == TIM8))
|
|
|
9750
|
|
|
9751 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
|
|
|
9752 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9753 ((INSTANCE) == TIM8) || \
|
|
|
9754 ((INSTANCE) == TIM15) || \
|
|
|
9755 ((INSTANCE) == TIM16) || \
|
|
|
9756 ((INSTANCE) == TIM17))
|
|
|
9757
|
|
|
9758 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
|
|
|
9759 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9760 ((INSTANCE) == TIM2) || \
|
|
|
9761 ((INSTANCE) == TIM3) || \
|
|
|
9762 ((INSTANCE) == TIM4) || \
|
|
|
9763 ((INSTANCE) == TIM5) || \
|
|
|
9764 ((INSTANCE) == TIM6) || \
|
|
|
9765 ((INSTANCE) == TIM7) || \
|
|
|
9766 ((INSTANCE) == TIM8) || \
|
|
|
9767 ((INSTANCE) == TIM15) || \
|
|
|
9768 ((INSTANCE) == TIM16) || \
|
|
|
9769 ((INSTANCE) == TIM17))
|
|
|
9770
|
|
|
9771 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
|
|
|
9772 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9773 ((INSTANCE) == TIM2) || \
|
|
|
9774 ((INSTANCE) == TIM3) || \
|
|
|
9775 ((INSTANCE) == TIM4) || \
|
|
|
9776 ((INSTANCE) == TIM5) || \
|
|
|
9777 ((INSTANCE) == TIM8) || \
|
|
|
9778 ((INSTANCE) == TIM15) || \
|
|
|
9779 ((INSTANCE) == TIM16) || \
|
|
|
9780 ((INSTANCE) == TIM17))
|
|
|
9781
|
|
|
9782 /******************** TIM Instances : DMA burst feature ***********************/
|
|
|
9783 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9784 ((INSTANCE) == TIM2) || \
|
|
|
9785 ((INSTANCE) == TIM3) || \
|
|
|
9786 ((INSTANCE) == TIM4) || \
|
|
|
9787 ((INSTANCE) == TIM5) || \
|
|
|
9788 ((INSTANCE) == TIM8) || \
|
|
|
9789 ((INSTANCE) == TIM15) || \
|
|
|
9790 ((INSTANCE) == TIM16) || \
|
|
|
9791 ((INSTANCE) == TIM17))
|
|
|
9792
|
|
|
9793 /******************* TIM Instances : output(s) available **********************/
|
|
|
9794 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
|
|
|
9795 ((((INSTANCE) == TIM1) && \
|
|
|
9796 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9797 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9798 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9799 ((CHANNEL) == TIM_CHANNEL_4) || \
|
|
|
9800 ((CHANNEL) == TIM_CHANNEL_5) || \
|
|
|
9801 ((CHANNEL) == TIM_CHANNEL_6))) \
|
|
|
9802 || \
|
|
|
9803 (((INSTANCE) == TIM2) && \
|
|
|
9804 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9805 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9806 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9807 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9808 || \
|
|
|
9809 (((INSTANCE) == TIM3) && \
|
|
|
9810 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9811 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9812 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9813 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9814 || \
|
|
|
9815 (((INSTANCE) == TIM4) && \
|
|
|
9816 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9817 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9818 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9819 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9820 || \
|
|
|
9821 (((INSTANCE) == TIM5) && \
|
|
|
9822 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9823 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9824 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9825 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
9826 || \
|
|
|
9827 (((INSTANCE) == TIM8) && \
|
|
|
9828 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9829 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9830 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
9831 ((CHANNEL) == TIM_CHANNEL_4) || \
|
|
|
9832 ((CHANNEL) == TIM_CHANNEL_5) || \
|
|
|
9833 ((CHANNEL) == TIM_CHANNEL_6))) \
|
|
|
9834 || \
|
|
|
9835 (((INSTANCE) == TIM15) && \
|
|
|
9836 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9837 ((CHANNEL) == TIM_CHANNEL_2))) \
|
|
|
9838 || \
|
|
|
9839 (((INSTANCE) == TIM16) && \
|
|
|
9840 (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
9841 || \
|
|
|
9842 (((INSTANCE) == TIM17) && \
|
|
|
9843 (((CHANNEL) == TIM_CHANNEL_1))))
|
|
|
9844
|
|
|
9845 /****************** TIM Instances : supporting complementary output(s) ********/
|
|
|
9846 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
|
|
|
9847 ((((INSTANCE) == TIM1) && \
|
|
|
9848 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9849 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9850 ((CHANNEL) == TIM_CHANNEL_3))) \
|
|
|
9851 || \
|
|
|
9852 (((INSTANCE) == TIM8) && \
|
|
|
9853 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
9854 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
9855 ((CHANNEL) == TIM_CHANNEL_3))) \
|
|
|
9856 || \
|
|
|
9857 (((INSTANCE) == TIM15) && \
|
|
|
9858 ((CHANNEL) == TIM_CHANNEL_1)) \
|
|
|
9859 || \
|
|
|
9860 (((INSTANCE) == TIM16) && \
|
|
|
9861 ((CHANNEL) == TIM_CHANNEL_1)) \
|
|
|
9862 || \
|
|
|
9863 (((INSTANCE) == TIM17) && \
|
|
|
9864 ((CHANNEL) == TIM_CHANNEL_1)))
|
|
|
9865
|
|
|
9866 /****************** TIM Instances : supporting clock division *****************/
|
|
|
9867 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9868 ((INSTANCE) == TIM2) || \
|
|
|
9869 ((INSTANCE) == TIM3) || \
|
|
|
9870 ((INSTANCE) == TIM4) || \
|
|
|
9871 ((INSTANCE) == TIM5) || \
|
|
|
9872 ((INSTANCE) == TIM8) || \
|
|
|
9873 ((INSTANCE) == TIM15) || \
|
|
|
9874 ((INSTANCE) == TIM16) || \
|
|
|
9875 ((INSTANCE) == TIM17))
|
|
|
9876
|
|
|
9877 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
|
|
|
9878 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9879 ((INSTANCE) == TIM2) || \
|
|
|
9880 ((INSTANCE) == TIM3) || \
|
|
|
9881 ((INSTANCE) == TIM4) || \
|
|
|
9882 ((INSTANCE) == TIM5) || \
|
|
|
9883 ((INSTANCE) == TIM8) || \
|
|
|
9884 ((INSTANCE) == TIM15))
|
|
|
9885
|
|
|
9886 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
|
|
|
9887 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9888 ((INSTANCE) == TIM2) || \
|
|
|
9889 ((INSTANCE) == TIM3) || \
|
|
|
9890 ((INSTANCE) == TIM4) || \
|
|
|
9891 ((INSTANCE) == TIM5) || \
|
|
|
9892 ((INSTANCE) == TIM8))
|
|
|
9893
|
|
|
9894 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
|
|
|
9895 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9896 ((INSTANCE) == TIM2) || \
|
|
|
9897 ((INSTANCE) == TIM3) || \
|
|
|
9898 ((INSTANCE) == TIM4) || \
|
|
|
9899 ((INSTANCE) == TIM5) || \
|
|
|
9900 ((INSTANCE) == TIM8) || \
|
|
|
9901 ((INSTANCE) == TIM15))
|
|
|
9902
|
|
|
9903 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
|
|
9904 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9905 ((INSTANCE) == TIM2) || \
|
|
|
9906 ((INSTANCE) == TIM3) || \
|
|
|
9907 ((INSTANCE) == TIM4) || \
|
|
|
9908 ((INSTANCE) == TIM5) || \
|
|
|
9909 ((INSTANCE) == TIM8) || \
|
|
|
9910 ((INSTANCE) == TIM15))
|
|
|
9911
|
|
|
9912 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
|
|
|
9913 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9914 ((INSTANCE) == TIM8))
|
|
|
9915
|
|
|
9916 /****************** TIM Instances : supporting commutation event generation ***/
|
|
|
9917 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9918 ((INSTANCE) == TIM8) || \
|
|
|
9919 ((INSTANCE) == TIM15) || \
|
|
|
9920 ((INSTANCE) == TIM16) || \
|
|
|
9921 ((INSTANCE) == TIM17))
|
|
|
9922
|
|
|
9923 /****************** TIM Instances : supporting counting mode selection ********/
|
|
|
9924 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9925 ((INSTANCE) == TIM2) || \
|
|
|
9926 ((INSTANCE) == TIM3) || \
|
|
|
9927 ((INSTANCE) == TIM4) || \
|
|
|
9928 ((INSTANCE) == TIM5) || \
|
|
|
9929 ((INSTANCE) == TIM8))
|
|
|
9930
|
|
|
9931 /****************** TIM Instances : supporting encoder interface **************/
|
|
|
9932 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9933 ((INSTANCE) == TIM2) || \
|
|
|
9934 ((INSTANCE) == TIM3) || \
|
|
|
9935 ((INSTANCE) == TIM4) || \
|
|
|
9936 ((INSTANCE) == TIM5) || \
|
|
|
9937 ((INSTANCE) == TIM8))
|
|
|
9938
|
|
|
9939 /****************** TIM Instances : supporting Hall sensor interface **********/
|
|
|
9940 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9941 ((INSTANCE) == TIM2) || \
|
|
|
9942 ((INSTANCE) == TIM3) || \
|
|
|
9943 ((INSTANCE) == TIM4) || \
|
|
|
9944 ((INSTANCE) == TIM5))
|
|
|
9945
|
|
|
9946 /**************** TIM Instances : external trigger input available ************/
|
|
|
9947 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9948 ((INSTANCE) == TIM2) || \
|
|
|
9949 ((INSTANCE) == TIM3) || \
|
|
|
9950 ((INSTANCE) == TIM4) || \
|
|
|
9951 ((INSTANCE) == TIM5) || \
|
|
|
9952 ((INSTANCE) == TIM8))
|
|
|
9953
|
|
|
9954 /************* TIM Instances : supporting ETR source selection ***************/
|
|
|
9955 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9956 ((INSTANCE) == TIM2) || \
|
|
|
9957 ((INSTANCE) == TIM3) || \
|
|
|
9958 ((INSTANCE) == TIM8))
|
|
|
9959
|
|
|
9960 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
|
|
|
9961 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9962 ((INSTANCE) == TIM2) || \
|
|
|
9963 ((INSTANCE) == TIM3) || \
|
|
|
9964 ((INSTANCE) == TIM4) || \
|
|
|
9965 ((INSTANCE) == TIM5) || \
|
|
|
9966 ((INSTANCE) == TIM6) || \
|
|
|
9967 ((INSTANCE) == TIM7) || \
|
|
|
9968 ((INSTANCE) == TIM8) || \
|
|
|
9969 ((INSTANCE) == TIM15))
|
|
|
9970
|
|
|
9971 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
|
|
|
9972 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9973 ((INSTANCE) == TIM2) || \
|
|
|
9974 ((INSTANCE) == TIM3) || \
|
|
|
9975 ((INSTANCE) == TIM4) || \
|
|
|
9976 ((INSTANCE) == TIM5) || \
|
|
|
9977 ((INSTANCE) == TIM8) || \
|
|
|
9978 ((INSTANCE) == TIM15))
|
|
|
9979
|
|
|
9980 /****************** TIM Instances : supporting OCxREF clear *******************/
|
|
|
9981 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9982 ((INSTANCE) == TIM2) || \
|
|
|
9983 ((INSTANCE) == TIM3) || \
|
|
|
9984 ((INSTANCE) == TIM4) || \
|
|
|
9985 ((INSTANCE) == TIM5) || \
|
|
|
9986 ((INSTANCE) == TIM8))
|
|
|
9987
|
|
|
9988 /****************** TIM Instances : remapping capability **********************/
|
|
|
9989 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9990 ((INSTANCE) == TIM2) || \
|
|
|
9991 ((INSTANCE) == TIM3) || \
|
|
|
9992 ((INSTANCE) == TIM8) || \
|
|
|
9993 ((INSTANCE) == TIM15) || \
|
|
|
9994 ((INSTANCE) == TIM16) || \
|
|
|
9995 ((INSTANCE) == TIM17))
|
|
|
9996
|
|
|
9997 /****************** TIM Instances : supporting repetition counter *************/
|
|
|
9998 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
9999 ((INSTANCE) == TIM8) || \
|
|
|
10000 ((INSTANCE) == TIM15) || \
|
|
|
10001 ((INSTANCE) == TIM16) || \
|
|
|
10002 ((INSTANCE) == TIM17))
|
|
|
10003
|
|
|
10004 /****************** TIM Instances : supporting synchronization ****************/
|
|
|
10005 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
|
|
10006
|
|
|
10007 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
|
|
10008 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
10009 ((INSTANCE) == TIM8))
|
|
|
10010
|
|
|
10011 /******************* TIM Instances : Timer input XOR function *****************/
|
|
|
10012 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
10013 ((INSTANCE) == TIM2) || \
|
|
|
10014 ((INSTANCE) == TIM3) || \
|
|
|
10015 ((INSTANCE) == TIM4) || \
|
|
|
10016 ((INSTANCE) == TIM5) || \
|
|
|
10017 ((INSTANCE) == TIM8) || \
|
|
|
10018 ((INSTANCE) == TIM15))
|
|
|
10019
|
|
|
10020 /****************************** TSC Instances *********************************/
|
|
|
10021 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
|
|
|
10022
|
|
|
10023 /******************** USART Instances : Synchronous mode **********************/
|
|
|
10024 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
10025 ((INSTANCE) == USART2) || \
|
|
|
10026 ((INSTANCE) == USART3))
|
|
|
10027
|
|
|
10028 /******************** UART Instances : Asynchronous mode **********************/
|
|
|
10029 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
10030 ((INSTANCE) == USART2) || \
|
|
|
10031 ((INSTANCE) == USART3) || \
|
|
|
10032 ((INSTANCE) == UART4) || \
|
|
|
10033 ((INSTANCE) == UART5))
|
|
|
10034
|
|
|
10035 /****************** UART Instances : Auto Baud Rate detection ****************/
|
|
|
10036 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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10037 ((INSTANCE) == USART2) || \
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10038 ((INSTANCE) == USART3) || \
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10039 ((INSTANCE) == UART4) || \
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10040 ((INSTANCE) == UART5))
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10041
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10042 /****************** UART Instances : Driver Enable *****************/
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10043 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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10044 ((INSTANCE) == USART2) || \
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10045 ((INSTANCE) == USART3) || \
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10046 ((INSTANCE) == UART4) || \
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10047 ((INSTANCE) == UART5) || \
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10048 ((INSTANCE) == LPUART1))
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10049
|
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10050 /******************** UART Instances : Half-Duplex mode **********************/
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10051 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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10052 ((INSTANCE) == USART2) || \
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10053 ((INSTANCE) == USART3) || \
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10054 ((INSTANCE) == UART4) || \
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10055 ((INSTANCE) == UART5) || \
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10056 ((INSTANCE) == LPUART1))
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10057
|
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10058 /****************** UART Instances : Hardware Flow control ********************/
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10059 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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10060 ((INSTANCE) == USART2) || \
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10061 ((INSTANCE) == USART3) || \
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10062 ((INSTANCE) == UART4) || \
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10063 ((INSTANCE) == UART5) || \
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10064 ((INSTANCE) == LPUART1))
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10065
|
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10066 /******************** UART Instances : LIN mode **********************/
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10067 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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10068 ((INSTANCE) == USART2) || \
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10069 ((INSTANCE) == USART3) || \
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10070 ((INSTANCE) == UART4) || \
|
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10071 ((INSTANCE) == UART5))
|
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10072
|
|
|
10073 /******************** UART Instances : Wake-up from Stop mode **********************/
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|
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10074 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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10075 ((INSTANCE) == USART2) || \
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10076 ((INSTANCE) == USART3) || \
|
|
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10077 ((INSTANCE) == UART4) || \
|
|
|
10078 ((INSTANCE) == UART5) || \
|
|
|
10079 ((INSTANCE) == LPUART1))
|
|
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10080
|
|
|
10081 /*********************** UART Instances : IRDA mode ***************************/
|
|
|
10082 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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|
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10083 ((INSTANCE) == USART2) || \
|
|
|
10084 ((INSTANCE) == USART3) || \
|
|
|
10085 ((INSTANCE) == UART4) || \
|
|
|
10086 ((INSTANCE) == UART5))
|
|
|
10087
|
|
|
10088 /********************* USART Instances : Smard card mode ***********************/
|
|
|
10089 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
10090 ((INSTANCE) == USART2) || \
|
|
|
10091 ((INSTANCE) == USART3))
|
|
|
10092
|
|
|
10093 /******************** LPUART Instance *****************************************/
|
|
|
10094 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
|
|
|
10095
|
|
|
10096 /****************************** IWDG Instances ********************************/
|
|
|
10097 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
|
|
10098
|
|
|
10099 /****************************** WWDG Instances ********************************/
|
|
|
10100 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
|
|
10101
|
|
|
10102 /**
|
|
|
10103 * @}
|
|
|
10104 */
|
|
|
10105
|
|
|
10106
|
|
|
10107 /******************************************************************************/
|
|
|
10108 /* For a painless codes migration between the STM32L4xx device product */
|
|
|
10109 /* lines, the aliases defined below are put in place to overcome the */
|
|
|
10110 /* differences in the interrupt handlers and IRQn definitions. */
|
|
|
10111 /* No need to update developed interrupt code when moving across */
|
|
|
10112 /* product lines within the same STM32L4 Family */
|
|
|
10113 /******************************************************************************/
|
|
|
10114
|
|
|
10115 /* Aliases for __IRQn */
|
|
|
10116 #define TIM8_IRQn TIM8_UP_IRQn
|
|
|
10117
|
|
|
10118 /* Aliases for __IRQHandler */
|
|
|
10119 #define TIM8_IRQHandler TIM8_UP_IRQHandler
|
|
|
10120
|
|
|
10121
|
|
|
10122 #ifdef __cplusplus
|
|
|
10123 }
|
|
|
10124 #endif /* __cplusplus */
|
|
|
10125
|
|
|
10126 #endif /* __STM32L476xx_H */
|
|
|
10127
|
|
|
10128 /**
|
|
|
10129 * @}
|
|
|
10130 */
|
|
|
10131
|
|
|
10132 /**
|
|
|
10133 * @}
|
|
|
10134 */
|
|
|
10135
|
|
|
10136 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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