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1 /* ----------------------------------------------------------------------
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2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
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3 *
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4 * $Date: 19. March 2015
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5 * $Revision: V.1.4.5
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6 *
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7 * Project: CMSIS DSP Library
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8 * Title: arm_add_q7.c
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9 *
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10 * Description: Q7 vector addition.
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11 *
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12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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13 *
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14 * Redistribution and use in source and binary forms, with or without
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15 * modification, are permitted provided that the following conditions
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16 * are met:
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17 * - Redistributions of source code must retain the above copyright
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18 * notice, this list of conditions and the following disclaimer.
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19 * - Redistributions in binary form must reproduce the above copyright
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20 * notice, this list of conditions and the following disclaimer in
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21 * the documentation and/or other materials provided with the
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22 * distribution.
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23 * - Neither the name of ARM LIMITED nor the names of its contributors
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24 * may be used to endorse or promote products derived from this
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25 * software without specific prior written permission.
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26 *
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27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 * POSSIBILITY OF SUCH DAMAGE.
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39 * -------------------------------------------------------------------- */
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40
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41 #include "arm_math.h"
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42
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43 /**
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44 * @ingroup groupMath
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45 */
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46
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47 /**
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48 * @addtogroup BasicAdd
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49 * @{
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50 */
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51
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52 /**
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53 * @brief Q7 vector addition.
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54 * @param[in] *pSrcA points to the first input vector
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55 * @param[in] *pSrcB points to the second input vector
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56 * @param[out] *pDst points to the output vector
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57 * @param[in] blockSize number of samples in each vector
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58 * @return none.
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59 *
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60 * <b>Scaling and Overflow Behavior:</b>
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61 * \par
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62 * The function uses saturating arithmetic.
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63 * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
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64 */
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65
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66 void arm_add_q7(
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67 q7_t * pSrcA,
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68 q7_t * pSrcB,
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69 q7_t * pDst,
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70 uint32_t blockSize)
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71 {
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72 uint32_t blkCnt; /* loop counter */
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73
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74 #ifndef ARM_MATH_CM0_FAMILY
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75
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76 /* Run the below code for Cortex-M4 and Cortex-M3 */
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77
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78
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79 /*loop Unrolling */
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80 blkCnt = blockSize >> 2u;
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81
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82 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
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83 ** a second loop below computes the remaining 1 to 3 samples. */
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84 while(blkCnt > 0u)
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85 {
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86 /* C = A + B */
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87 /* Add and then store the results in the destination buffer. */
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88 *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
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89
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90 /* Decrement the loop counter */
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91 blkCnt--;
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92 }
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93
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94 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
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95 ** No loop unrolling is used. */
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96 blkCnt = blockSize % 0x4u;
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97
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98 while(blkCnt > 0u)
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99 {
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100 /* C = A + B */
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101 /* Add and then store the results in the destination buffer. */
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102 *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);
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103
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104 /* Decrement the loop counter */
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105 blkCnt--;
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106 }
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107
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108 #else
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109
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110 /* Run the below code for Cortex-M0 */
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111
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112
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113
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114 /* Initialize blkCnt with number of samples */
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115 blkCnt = blockSize;
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116
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117 while(blkCnt > 0u)
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118 {
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119 /* C = A + B */
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120 /* Add and then store the results in the destination buffer. */
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121 *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);
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122
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123 /* Decrement the loop counter */
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124 blkCnt--;
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125 }
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126
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127 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
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128
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129
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130 }
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131
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132 /**
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133 * @} end of BasicAdd group
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134 */
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