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1 /**
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2 ******************************************************************************
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3 * @file stm32f1xx_hal_pwr.c
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4 * @author MCD Application Team
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5 * @version V1.0.4
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6 * @date 29-April-2016
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7 * @brief PWR HAL module driver.
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8 *
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9 * This file provides firmware functions to manage the following
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10 * functionalities of the Power Controller (PWR) peripheral:
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11 * + Initialization/de-initialization functions
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12 * + Peripheral Control functions
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13 *
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14 ******************************************************************************
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15 * @attention
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16 *
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17 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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18 *
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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29 *
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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40 *
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41 ******************************************************************************
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42 */
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #include "stm32f1xx_hal.h"
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46
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47 /** @addtogroup STM32F1xx_HAL_Driver
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48 * @{
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49 */
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50
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51 /** @defgroup PWR PWR
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52 * @brief PWR HAL module driver
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53 * @{
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54 */
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55
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56 #ifdef HAL_PWR_MODULE_ENABLED
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57
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58 /* Private typedef -----------------------------------------------------------*/
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59 /* Private define ------------------------------------------------------------*/
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60
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61 /** @defgroup PWR_Private_Constants PWR Private Constants
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62 * @{
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63 */
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64
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65 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
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66 * @{
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67 */
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68 #define PVD_MODE_IT ((uint32_t)0x00010000)
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69 #define PVD_MODE_EVT ((uint32_t)0x00020000)
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70 #define PVD_RISING_EDGE ((uint32_t)0x00000001)
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71 #define PVD_FALLING_EDGE ((uint32_t)0x00000002)
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72 /**
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73 * @}
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74 */
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75
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76
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77 /** @defgroup PWR_register_alias_address PWR Register alias address
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78 * @{
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79 */
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80 /* ------------- PWR registers bit address in the alias region ---------------*/
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81 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
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82 #define PWR_CR_OFFSET 0x00
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83 #define PWR_CSR_OFFSET 0x04
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84 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
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85 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
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86 /**
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87 * @}
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88 */
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89
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90 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
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91 * @{
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92 */
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93 /* --- CR Register ---*/
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94 /* Alias word address of LPSDSR bit */
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95 #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPDS)
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96 #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
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97
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98 /* Alias word address of DBP bit */
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99 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
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100 #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
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101
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102 /* Alias word address of PVDE bit */
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103 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
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104 #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
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105
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106 /**
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107 * @}
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108 */
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109
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110 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
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111 * @{
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112 */
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113
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114 /* --- CSR Register ---*/
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115 /* Alias word address of EWUP1 bit */
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116 #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
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117 /**
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118 * @}
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119 */
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120
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121 /**
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122 * @}
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123 */
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124
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125 /* Private variables ---------------------------------------------------------*/
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126 /* Private function prototypes -----------------------------------------------*/
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127 /** @defgroup PWR_Private_Functions PWR Private Functions
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128 * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
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129 * @{
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130 */
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131 static void PWR_OverloadWfe(void);
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132
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133 /* Private functions ---------------------------------------------------------*/
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134 __NOINLINE
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135 static void PWR_OverloadWfe(void)
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136 {
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137 __asm volatile( "wfe" );
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138 __asm volatile( "nop" );
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139 }
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140
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141 /**
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142 * @}
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143 */
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144
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145
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146 /** @defgroup PWR_Exported_Functions PWR Exported Functions
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147 * @{
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148 */
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149
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150 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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151 * @brief Initialization and de-initialization functions
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152 *
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153 @verbatim
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154 ===============================================================================
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155 ##### Initialization and de-initialization functions #####
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156 ===============================================================================
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157 [..]
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158 After reset, the backup domain (RTC registers, RTC backup data
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159 registers) is protected against possible unwanted
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160 write accesses.
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161 To enable access to the RTC Domain and RTC registers, proceed as follows:
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162 (+) Enable the Power Controller (PWR) APB1 interface clock using the
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163 __HAL_RCC_PWR_CLK_ENABLE() macro.
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164 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
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165
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166 @endverbatim
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167 * @{
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168 */
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169
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170 /**
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171 * @brief Deinitializes the PWR peripheral registers to their default reset values.
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172 * @retval None
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173 */
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174 void HAL_PWR_DeInit(void)
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175 {
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176 __HAL_RCC_PWR_FORCE_RESET();
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177 __HAL_RCC_PWR_RELEASE_RESET();
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178 }
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179
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180 /**
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181 * @brief Enables access to the backup domain (RTC registers, RTC
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182 * backup data registers ).
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183 * @note If the HSE divided by 128 is used as the RTC clock, the
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184 * Backup Domain Access should be kept enabled.
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185 * @retval None
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186 */
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187 void HAL_PWR_EnableBkUpAccess(void)
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188 {
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189 /* Enable access to RTC and backup registers */
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190 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
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191 }
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192
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193 /**
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194 * @brief Disables access to the backup domain (RTC registers, RTC
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195 * backup data registers).
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196 * @note If the HSE divided by 128 is used as the RTC clock, the
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197 * Backup Domain Access should be kept enabled.
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198 * @retval None
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199 */
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200 void HAL_PWR_DisableBkUpAccess(void)
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201 {
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202 /* Disable access to RTC and backup registers */
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203 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
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204 }
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205
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206 /**
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207 * @}
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208 */
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209
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210 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
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211 * @brief Low Power modes configuration functions
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212 *
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213 @verbatim
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214 ===============================================================================
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215 ##### Peripheral Control functions #####
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216 ===============================================================================
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217
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218 *** PVD configuration ***
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219 =========================
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220 [..]
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221 (+) The PVD is used to monitor the VDD power supply by comparing it to a
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222 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
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223
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224 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
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225 than the PVD threshold. This event is internally connected to the EXTI
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226 line16 and can generate an interrupt if enabled. This is done through
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227 __HAL_PVD_EXTI_ENABLE_IT() macro.
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228 (+) The PVD is stopped in Standby mode.
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229
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230 *** WakeUp pin configuration ***
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231 ================================
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232 [..]
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233 (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
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234 forced in input pull-down configuration and is active on rising edges.
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235 (+) There is one WakeUp pin:
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236 WakeUp Pin 1 on PA.00.
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237
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238 [..]
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239
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240 *** Low Power modes configuration ***
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241 =====================================
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242 [..]
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243 The device features 3 low-power modes:
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244 (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
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245 NVIC, SysTick, etc. are kept running
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246 (+) Stop mode: All clocks are stopped
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247 (+) Standby mode: 1.8V domain powered off
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248
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249
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250 *** Sleep mode ***
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251 ==================
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252 [..]
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253 (+) Entry:
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254 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
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255 functions with
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256 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
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257 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
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258
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259 (+) Exit:
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260 (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
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261 controller (NVIC) can wake up the device from Sleep mode.
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262 (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
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263 (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
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264 (+++) Any EXTI Line (Internal or External) configured in Event mode
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265
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266 *** Stop mode ***
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267 =================
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268 [..]
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269 The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
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270 clock gating. The voltage regulator can be configured either in normal or low-power mode.
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271 In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
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272 oscillators are disabled. SRAM and register contents are preserved.
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273 In Stop mode, all I/O pins keep the same state as in Run mode.
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274
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275 (+) Entry:
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276 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
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277 function with:
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278 (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
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279 (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
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280 (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
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281 (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
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282 (+) Exit:
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283 (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
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284 (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
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285
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286 *** Standby mode ***
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287 ====================
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288 [..]
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289 The Standby mode allows to achieve the lowest power consumption. It is based on the
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290 Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
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291 consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
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292 switched off. SRAM and register contents are lost except for registers in the Backup domain
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293 and Standby circuitry
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294
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295 (+) Entry:
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296 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
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297 (+) Exit:
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298 (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
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299 NRSTpin, IWDG Reset
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300
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301 *** Auto-wakeup (AWU) from low-power mode ***
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302 =============================================
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303 [..]
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304
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305 (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
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306 without depending on an external interrupt (Auto-wakeup mode).
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307
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308 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
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309
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310 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
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311 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
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312
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313 *** PWR Workarounds linked to Silicon Limitation ***
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314 ====================================================
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315 [..]
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316 Below the list of all silicon limitations known on STM32F1xx prouct.
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317
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318 (#)Workarounds Implemented inside PWR HAL Driver
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319 (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
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320
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321 @endverbatim
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322 * @{
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323 */
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324
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325 /**
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326 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
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327 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
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328 * information for the PVD.
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329 * @note Refer to the electrical characteristics of your device datasheet for
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330 * more details about the voltage threshold corresponding to each
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331 * detection level.
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332 * @retval None
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333 */
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334 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
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335 {
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336 /* Check the parameters */
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337 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
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338 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
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339
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340 /* Set PLS[7:5] bits according to PVDLevel value */
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341 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
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342
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343 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
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344 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
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345 __HAL_PWR_PVD_EXTI_DISABLE_IT();
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346 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
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347 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
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348
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349 /* Configure interrupt mode */
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350 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
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351 {
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352 __HAL_PWR_PVD_EXTI_ENABLE_IT();
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353 }
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354
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355 /* Configure event mode */
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356 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
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357 {
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358 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
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359 }
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360
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361 /* Configure the edge */
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362 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
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363 {
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364 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
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365 }
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366
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367 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
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368 {
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369 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
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370 }
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371 }
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372
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373 /**
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374 * @brief Enables the Power Voltage Detector(PVD).
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375 * @retval None
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376 */
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377 void HAL_PWR_EnablePVD(void)
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378 {
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379 /* Enable the power voltage detector */
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380 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
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381 }
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382
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383 /**
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384 * @brief Disables the Power Voltage Detector(PVD).
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385 * @retval None
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386 */
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387 void HAL_PWR_DisablePVD(void)
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388 {
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389 /* Disable the power voltage detector */
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390 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
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391 }
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392
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393 /**
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394 * @brief Enables the WakeUp PINx functionality.
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395 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
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396 * This parameter can be one of the following values:
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397 * @arg PWR_WAKEUP_PIN1
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398 * @retval None
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399 */
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400 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
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401 {
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402 /* Check the parameter */
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403 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
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404 /* Enable the EWUPx pin */
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405 *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
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406 }
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407
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408 /**
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409 * @brief Disables the WakeUp PINx functionality.
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410 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
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411 * This parameter can be one of the following values:
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412 * @arg PWR_WAKEUP_PIN1
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413 * @retval None
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414 */
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415 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
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416 {
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417 /* Check the parameter */
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418 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
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419 /* Disable the EWUPx pin */
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420 *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
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421 }
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422
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423 /**
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424 * @brief Enters Sleep mode.
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425 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
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426 * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software
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427 * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
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428 * When WFI entry is used, tick interrupt have to be disabled if not desired as
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429 * the interrupt wake up source.
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430 * This parameter can be one of the following values:
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431 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
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432 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
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433 * @retval None
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434 */
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435 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
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436 {
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437 /* Check the parameters */
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438 /* No check on Regulator because parameter not used in SLEEP mode */
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439 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
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440
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441 /* Clear SLEEPDEEP bit of Cortex System Control Register */
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442 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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443
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444 /* Select SLEEP mode entry -------------------------------------------------*/
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445 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
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446 {
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447 /* Request Wait For Interrupt */
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448 __WFI();
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449 }
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450 else
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451 {
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452 /* Request Wait For Event */
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453 __SEV();
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454 __WFE();
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455 __WFE();
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456 }
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457 }
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458
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459 /**
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460 * @brief Enters Stop mode.
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461 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
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462 * @note When exiting Stop mode by using an interrupt or a wakeup event,
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463 * HSI RC oscillator is selected as system clock.
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464 * @note When the voltage regulator operates in low power mode, an additional
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465 * startup delay is incurred when waking up from Stop mode.
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466 * By keeping the internal regulator ON during Stop mode, the consumption
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467 * is higher although the startup time is reduced.
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468 * @param Regulator: Specifies the regulator state in Stop mode.
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469 * This parameter can be one of the following values:
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470 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
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471 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
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472 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
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473 * This parameter can be one of the following values:
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474 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
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475 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
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476 * @retval None
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477 */
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478 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
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479 {
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480 /* Check the parameters */
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481 assert_param(IS_PWR_REGULATOR(Regulator));
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482 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
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483
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484 /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
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485 CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
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486
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487 /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
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488 MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
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489
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490 /* Set SLEEPDEEP bit of Cortex System Control Register */
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491 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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492
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493 /* Select Stop mode entry --------------------------------------------------*/
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494 if(STOPEntry == PWR_STOPENTRY_WFI)
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495 {
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496 /* Request Wait For Interrupt */
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497 __WFI();
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498 }
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499 else
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500 {
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501 /* Request Wait For Event */
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502 __SEV();
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503 PWR_OverloadWfe(); /* WFE redefine locally */
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504 PWR_OverloadWfe(); /* WFE redefine locally */
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505 }
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506 /* Reset SLEEPDEEP bit of Cortex System Control Register */
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507 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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508 }
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509
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510 /**
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511 * @brief Enters Standby mode.
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512 * @note In Standby mode, all I/O pins are high impedance except for:
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513 * - Reset pad (still available)
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514 * - TAMPER pin if configured for tamper or calibration out.
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515 * - WKUP pin (PA0) if enabled.
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516 * @retval None
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517 */
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518 void HAL_PWR_EnterSTANDBYMode(void)
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519 {
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520 /* Select Standby mode */
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521 SET_BIT(PWR->CR, PWR_CR_PDDS);
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522
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523 /* Set SLEEPDEEP bit of Cortex System Control Register */
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524 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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525
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526 /* This option is used to ensure that store operations are completed */
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527 #if defined ( __CC_ARM)
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528 __force_stores();
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529 #endif
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530 /* Request Wait For Interrupt */
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531 __WFI();
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532 }
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533
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534
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535 /**
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536 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
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537 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
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538 * re-enters SLEEP mode when an interruption handling is over.
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539 * Setting this bit is useful when the processor is expected to run only on
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540 * interruptions handling.
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541 * @retval None
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542 */
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543 void HAL_PWR_EnableSleepOnExit(void)
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544 {
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545 /* Set SLEEPONEXIT bit of Cortex System Control Register */
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546 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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547 }
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548
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549
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550 /**
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551 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
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552 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
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553 * re-enters SLEEP mode when an interruption handling is over.
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554 * @retval None
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555 */
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556 void HAL_PWR_DisableSleepOnExit(void)
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557 {
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558 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
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559 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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560 }
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561
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562
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563 /**
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564 * @brief Enables CORTEX M3 SEVONPEND bit.
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565 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
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566 * WFE to wake up when an interrupt moves from inactive to pended.
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567 * @retval None
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568 */
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569 void HAL_PWR_EnableSEVOnPend(void)
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570 {
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571 /* Set SEVONPEND bit of Cortex System Control Register */
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572 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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573 }
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574
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575
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576 /**
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577 * @brief Disables CORTEX M3 SEVONPEND bit.
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578 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
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579 * WFE to wake up when an interrupt moves from inactive to pended.
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580 * @retval None
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581 */
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582 void HAL_PWR_DisableSEVOnPend(void)
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583 {
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584 /* Clear SEVONPEND bit of Cortex System Control Register */
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585 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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586 }
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587
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588
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589
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590 /**
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591 * @brief This function handles the PWR PVD interrupt request.
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592 * @note This API should be called under the PVD_IRQHandler().
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593 * @retval None
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594 */
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595 void HAL_PWR_PVD_IRQHandler(void)
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596 {
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597 /* Check PWR exti flag */
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598 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
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599 {
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600 /* PWR PVD interrupt user callback */
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601 HAL_PWR_PVDCallback();
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602
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603 /* Clear PWR Exti pending bit */
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604 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
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605 }
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606 }
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607
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608 /**
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609 * @brief PWR PVD interrupt callback
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610 * @retval None
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611 */
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612 __weak void HAL_PWR_PVDCallback(void)
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613 {
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614 /* NOTE : This function Should not be modified, when the callback is needed,
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615 the HAL_PWR_PVDCallback could be implemented in the user file
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616 */
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617 }
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618
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619 /**
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620 * @}
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621 */
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622
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623 /**
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624 * @}
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625 */
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626
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627 #endif /* HAL_PWR_MODULE_ENABLED */
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628 /**
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629 * @}
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630 */
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631
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632 /**
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633 * @}
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634 */
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635
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636 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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