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1 /**
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2 ******************************************************************************
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3 * @file startup_stm32l486xx.s
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4 * @author MCD Application Team
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5 * @version V1.0.3
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6 * @date 29-January-2016
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7 * @brief STM32L486xx devices vector table for GCC toolchain.
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8 * This module performs:
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9 * - Set the initial SP
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10 * - Set the initial PC == Reset_Handler,
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11 * - Set the vector table entries with the exceptions ISR address,
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12 * - Configure the clock system
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13 * - Branches to main in the C library (which eventually
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14 * calls main()).
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15 * After Reset the Cortex-M4 processor is in Thread mode,
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16 * priority is Privileged, and the Stack is set to Main.
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17 ******************************************************************************
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18 * @attention
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19 *
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20 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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21 *
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22 * Redistribution and use in source and binary forms, with or without modification,
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23 * are permitted provided that the following conditions are met:
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24 * 1. Redistributions of source code must retain the above copyright notice,
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25 * this list of conditions and the following disclaimer.
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26 * 2. Redistributions in binary form must reproduce the above copyright notice,
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27 * this list of conditions and the following disclaimer in the documentation
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28 * and/or other materials provided with the distribution.
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29 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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30 * may be used to endorse or promote products derived from this software
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31 * without specific prior written permission.
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32 *
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33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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36 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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40 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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41 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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42 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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43 *
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44 ******************************************************************************
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45 */
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46
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47 .syntax unified
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48 .cpu cortex-m4
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49 .fpu softvfp
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50 .thumb
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51
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52 .global g_pfnVectors
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53 .global Default_Handler
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54
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55 /* start address for the initialization values of the .data section.
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56 defined in linker script */
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57 .word _sidata
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58 /* start address for the .data section. defined in linker script */
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59 .word _sdata
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60 /* end address for the .data section. defined in linker script */
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61 .word _edata
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62 /* start address for the .bss section. defined in linker script */
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63 .word _sbss
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64 /* end address for the .bss section. defined in linker script */
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65 .word _ebss
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66
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67 .equ BootRAM, 0xF1E0F85F
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68 /**
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69 * @brief This is the code that gets called when the processor first
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70 * starts execution following a reset event. Only the absolutely
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71 * necessary set is performed, after which the application
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72 * supplied main() routine is called.
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73 * @param None
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74 * @retval : None
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75 */
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76
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77 .section .text.Reset_Handler
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78 .weak Reset_Handler
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79 .type Reset_Handler, %function
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80 Reset_Handler:
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81 ldr sp, =_estack /* Atollic update: set stack pointer */
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82
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83 /* Copy the data segment initializers from flash to SRAM */
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84 movs r1, #0
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85 b LoopCopyDataInit
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86
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87 CopyDataInit:
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88 ldr r3, =_sidata
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89 ldr r3, [r3, r1]
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90 str r3, [r0, r1]
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91 adds r1, r1, #4
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92
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93 LoopCopyDataInit:
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94 ldr r0, =_sdata
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95 ldr r3, =_edata
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96 adds r2, r0, r1
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97 cmp r2, r3
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98 bcc CopyDataInit
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99 ldr r2, =_sbss
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100 b LoopFillZerobss
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101 /* Zero fill the bss segment. */
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102 FillZerobss:
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103 movs r3, #0
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104 str r3, [r2], #4
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105
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106 LoopFillZerobss:
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107 ldr r3, = _ebss
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108 cmp r2, r3
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109 bcc FillZerobss
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110
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111 /* Call the clock system intitialization function.*/
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112 bl SystemInit
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113 /* Call static constructors */
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114 bl __libc_init_array
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115 /* Call the application's entry point.*/
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116 bl main
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117
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118 LoopForever:
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119 b LoopForever
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120
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121 .size Reset_Handler, .-Reset_Handler
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122
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123 /**
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124 * @brief This is the code that gets called when the processor receives an
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125 * unexpected interrupt. This simply enters an infinite loop, preserving
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126 * the system state for examination by a debugger.
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127 *
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128 * @param None
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129 * @retval : None
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130 */
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131 .section .text.Default_Handler,"ax",%progbits
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132 Default_Handler:
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133 Infinite_Loop:
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134 b Infinite_Loop
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135 .size Default_Handler, .-Default_Handler
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136 /******************************************************************************
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137 *
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138 * The minimal vector table for a Cortex-M4. Note that the proper constructs
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139 * must be placed on this to ensure that it ends up at physical address
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140 * 0x0000.0000.
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141 *
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142 ******************************************************************************/
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143 .section .isr_vector,"a",%progbits
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144 .type g_pfnVectors, %object
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145 .size g_pfnVectors, .-g_pfnVectors
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146
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147
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148 g_pfnVectors:
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149 .word _estack
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150 .word Reset_Handler
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151 .word NMI_Handler
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152 .word HardFault_Handler
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153 .word MemManage_Handler
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154 .word BusFault_Handler
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155 .word UsageFault_Handler
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156 .word 0
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157 .word 0
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158 .word 0
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159 .word 0
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160 .word SVC_Handler
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161 .word DebugMon_Handler
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162 .word 0
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163 .word PendSV_Handler
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164 .word SysTick_Handler
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165 .word WWDG_IRQHandler
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166 .word PVD_PVM_IRQHandler
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167 .word TAMP_STAMP_IRQHandler
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168 .word RTC_WKUP_IRQHandler
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169 .word FLASH_IRQHandler
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170 .word RCC_IRQHandler
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171 .word EXTI0_IRQHandler
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172 .word EXTI1_IRQHandler
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173 .word EXTI2_IRQHandler
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174 .word EXTI3_IRQHandler
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175 .word EXTI4_IRQHandler
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176 .word DMA1_Channel1_IRQHandler
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177 .word DMA1_Channel2_IRQHandler
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178 .word DMA1_Channel3_IRQHandler
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179 .word DMA1_Channel4_IRQHandler
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180 .word DMA1_Channel5_IRQHandler
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181 .word DMA1_Channel6_IRQHandler
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182 .word DMA1_Channel7_IRQHandler
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183 .word ADC1_2_IRQHandler
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184 .word CAN1_TX_IRQHandler
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185 .word CAN1_RX0_IRQHandler
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186 .word CAN1_RX1_IRQHandler
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187 .word CAN1_SCE_IRQHandler
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188 .word EXTI9_5_IRQHandler
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189 .word TIM1_BRK_TIM15_IRQHandler
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190 .word TIM1_UP_TIM16_IRQHandler
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191 .word TIM1_TRG_COM_TIM17_IRQHandler
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192 .word TIM1_CC_IRQHandler
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193 .word TIM2_IRQHandler
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194 .word TIM3_IRQHandler
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195 .word TIM4_IRQHandler
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196 .word I2C1_EV_IRQHandler
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197 .word I2C1_ER_IRQHandler
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198 .word I2C2_EV_IRQHandler
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199 .word I2C2_ER_IRQHandler
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200 .word SPI1_IRQHandler
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201 .word SPI2_IRQHandler
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202 .word USART1_IRQHandler
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203 .word USART2_IRQHandler
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204 .word USART3_IRQHandler
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205 .word EXTI15_10_IRQHandler
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206 .word RTC_Alarm_IRQHandler
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207 .word DFSDM3_IRQHandler
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208 .word TIM8_BRK_IRQHandler
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209 .word TIM8_UP_IRQHandler
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210 .word TIM8_TRG_COM_IRQHandler
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211 .word TIM8_CC_IRQHandler
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212 .word ADC3_IRQHandler
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213 .word FMC_IRQHandler
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214 .word SDMMC1_IRQHandler
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215 .word TIM5_IRQHandler
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216 .word SPI3_IRQHandler
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217 .word UART4_IRQHandler
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218 .word UART5_IRQHandler
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219 .word TIM6_DAC_IRQHandler
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220 .word TIM7_IRQHandler
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221 .word DMA2_Channel1_IRQHandler
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222 .word DMA2_Channel2_IRQHandler
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223 .word DMA2_Channel3_IRQHandler
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224 .word DMA2_Channel4_IRQHandler
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225 .word DMA2_Channel5_IRQHandler
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226 .word DFSDM0_IRQHandler
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227 .word DFSDM1_IRQHandler
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228 .word DFSDM2_IRQHandler
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229 .word COMP_IRQHandler
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230 .word LPTIM1_IRQHandler
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231 .word LPTIM2_IRQHandler
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232 .word OTG_FS_IRQHandler
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233 .word DMA2_Channel6_IRQHandler
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234 .word DMA2_Channel7_IRQHandler
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235 .word LPUART1_IRQHandler
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236 .word QUADSPI_IRQHandler
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237 .word I2C3_EV_IRQHandler
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238 .word I2C3_ER_IRQHandler
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239 .word SAI1_IRQHandler
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240 .word SAI2_IRQHandler
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241 .word SWPMI1_IRQHandler
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242 .word TSC_IRQHandler
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243 .word LCD_IRQHandler
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244 .word AES_IRQHandler
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245 .word RNG_IRQHandler
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246 .word FPU_IRQHandler
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247
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248
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249 /*******************************************************************************
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250 *
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251 * Provide weak aliases for each Exception handler to the Default_Handler.
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252 * As they are weak aliases, any function with the same name will override
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253 * this definition.
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254 *
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255 *******************************************************************************/
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256
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257 .weak NMI_Handler
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258 .thumb_set NMI_Handler,Default_Handler
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259
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260 .weak HardFault_Handler
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261 .thumb_set HardFault_Handler,Default_Handler
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262
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263 .weak MemManage_Handler
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264 .thumb_set MemManage_Handler,Default_Handler
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265
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266 .weak BusFault_Handler
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267 .thumb_set BusFault_Handler,Default_Handler
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268
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269 .weak UsageFault_Handler
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270 .thumb_set UsageFault_Handler,Default_Handler
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271
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272 .weak SVC_Handler
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273 .thumb_set SVC_Handler,Default_Handler
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274
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275 .weak DebugMon_Handler
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276 .thumb_set DebugMon_Handler,Default_Handler
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277
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278 .weak PendSV_Handler
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279 .thumb_set PendSV_Handler,Default_Handler
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280
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281 .weak SysTick_Handler
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282 .thumb_set SysTick_Handler,Default_Handler
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283
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284 .weak WWDG_IRQHandler
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285 .thumb_set WWDG_IRQHandler,Default_Handler
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286
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287 .weak PVD_PVM_IRQHandler
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288 .thumb_set PVD_PVM_IRQHandler,Default_Handler
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289
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290 .weak TAMP_STAMP_IRQHandler
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291 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
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292
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293 .weak RTC_WKUP_IRQHandler
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294 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
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295
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296 .weak FLASH_IRQHandler
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297 .thumb_set FLASH_IRQHandler,Default_Handler
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298
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299 .weak RCC_IRQHandler
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300 .thumb_set RCC_IRQHandler,Default_Handler
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301
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302 .weak EXTI0_IRQHandler
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303 .thumb_set EXTI0_IRQHandler,Default_Handler
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304
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305 .weak EXTI1_IRQHandler
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306 .thumb_set EXTI1_IRQHandler,Default_Handler
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307
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308 .weak EXTI2_IRQHandler
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309 .thumb_set EXTI2_IRQHandler,Default_Handler
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310
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311 .weak EXTI3_IRQHandler
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312 .thumb_set EXTI3_IRQHandler,Default_Handler
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313
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314 .weak EXTI4_IRQHandler
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315 .thumb_set EXTI4_IRQHandler,Default_Handler
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316
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317 .weak DMA1_Channel1_IRQHandler
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318 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
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319
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320 .weak DMA1_Channel2_IRQHandler
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321 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
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322
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323 .weak DMA1_Channel3_IRQHandler
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324 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
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325
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326 .weak DMA1_Channel4_IRQHandler
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327 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
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328
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329 .weak DMA1_Channel5_IRQHandler
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330 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
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331
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332 .weak DMA1_Channel6_IRQHandler
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333 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
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334
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335 .weak DMA1_Channel7_IRQHandler
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336 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
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337
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338 .weak ADC1_2_IRQHandler
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339 .thumb_set ADC1_2_IRQHandler,Default_Handler
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340
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341 .weak CAN1_TX_IRQHandler
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342 .thumb_set CAN1_TX_IRQHandler,Default_Handler
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343
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344 .weak CAN1_RX0_IRQHandler
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345 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
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346
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347 .weak CAN1_RX1_IRQHandler
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348 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
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349
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350 .weak CAN1_SCE_IRQHandler
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351 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
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352
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353 .weak EXTI9_5_IRQHandler
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354 .thumb_set EXTI9_5_IRQHandler,Default_Handler
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355
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356 .weak TIM1_BRK_TIM15_IRQHandler
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357 .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
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358
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359 .weak TIM1_UP_TIM16_IRQHandler
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360 .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
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361
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362 .weak TIM1_TRG_COM_TIM17_IRQHandler
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363 .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
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364
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365 .weak TIM1_CC_IRQHandler
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366 .thumb_set TIM1_CC_IRQHandler,Default_Handler
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367
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368 .weak TIM2_IRQHandler
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369 .thumb_set TIM2_IRQHandler,Default_Handler
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370
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371 .weak TIM3_IRQHandler
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372 .thumb_set TIM3_IRQHandler,Default_Handler
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373
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374 .weak TIM4_IRQHandler
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375 .thumb_set TIM4_IRQHandler,Default_Handler
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376
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377 .weak I2C1_EV_IRQHandler
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378 .thumb_set I2C1_EV_IRQHandler,Default_Handler
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379
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380 .weak I2C1_ER_IRQHandler
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381 .thumb_set I2C1_ER_IRQHandler,Default_Handler
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382
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383 .weak I2C2_EV_IRQHandler
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384 .thumb_set I2C2_EV_IRQHandler,Default_Handler
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385
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386 .weak I2C2_ER_IRQHandler
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387 .thumb_set I2C2_ER_IRQHandler,Default_Handler
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388
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389 .weak SPI1_IRQHandler
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390 .thumb_set SPI1_IRQHandler,Default_Handler
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391
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392 .weak SPI2_IRQHandler
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393 .thumb_set SPI2_IRQHandler,Default_Handler
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394
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395 .weak USART1_IRQHandler
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396 .thumb_set USART1_IRQHandler,Default_Handler
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397
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398 .weak USART2_IRQHandler
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399 .thumb_set USART2_IRQHandler,Default_Handler
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400
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401 .weak USART3_IRQHandler
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402 .thumb_set USART3_IRQHandler,Default_Handler
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403
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404 .weak EXTI15_10_IRQHandler
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405 .thumb_set EXTI15_10_IRQHandler,Default_Handler
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406
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407 .weak RTC_Alarm_IRQHandler
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408 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
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409
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410 .weak DFSDM3_IRQHandler
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411 .thumb_set DFSDM3_IRQHandler,Default_Handler
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412
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413 .weak TIM8_BRK_IRQHandler
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414 .thumb_set TIM8_BRK_IRQHandler,Default_Handler
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415
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416 .weak TIM8_UP_IRQHandler
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417 .thumb_set TIM8_UP_IRQHandler,Default_Handler
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418
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419 .weak TIM8_TRG_COM_IRQHandler
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420 .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
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421
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422 .weak TIM8_CC_IRQHandler
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423 .thumb_set TIM8_CC_IRQHandler,Default_Handler
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424
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425 .weak ADC3_IRQHandler
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426 .thumb_set ADC3_IRQHandler,Default_Handler
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427
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428 .weak FMC_IRQHandler
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429 .thumb_set FMC_IRQHandler,Default_Handler
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430
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431 .weak SDMMC1_IRQHandler
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432 .thumb_set SDMMC1_IRQHandler,Default_Handler
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433
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434 .weak TIM5_IRQHandler
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435 .thumb_set TIM5_IRQHandler,Default_Handler
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436
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437 .weak SPI3_IRQHandler
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438 .thumb_set SPI3_IRQHandler,Default_Handler
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439
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440 .weak UART4_IRQHandler
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441 .thumb_set UART4_IRQHandler,Default_Handler
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442
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443 .weak UART5_IRQHandler
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444 .thumb_set UART5_IRQHandler,Default_Handler
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445
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446 .weak TIM6_DAC_IRQHandler
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447 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
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448
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449 .weak TIM7_IRQHandler
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450 .thumb_set TIM7_IRQHandler,Default_Handler
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451
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452 .weak DMA2_Channel1_IRQHandler
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453 .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
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454
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455 .weak DMA2_Channel2_IRQHandler
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456 .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
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457
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458 .weak DMA2_Channel3_IRQHandler
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459 .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
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460
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461 .weak DMA2_Channel4_IRQHandler
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462 .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
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463
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464 .weak DMA2_Channel5_IRQHandler
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465 .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
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466
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467 .weak DFSDM0_IRQHandler
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468 .thumb_set DFSDM0_IRQHandler,Default_Handler
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469
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470 .weak DFSDM1_IRQHandler
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471 .thumb_set DFSDM1_IRQHandler,Default_Handler
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472
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473 .weak DFSDM2_IRQHandler
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474 .thumb_set DFSDM2_IRQHandler,Default_Handler
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475
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476 .weak COMP_IRQHandler
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477 .thumb_set COMP_IRQHandler,Default_Handler
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478
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479 .weak LPTIM1_IRQHandler
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480 .thumb_set LPTIM1_IRQHandler,Default_Handler
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481
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482 .weak LPTIM2_IRQHandler
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483 .thumb_set LPTIM2_IRQHandler,Default_Handler
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484
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485 .weak OTG_FS_IRQHandler
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486 .thumb_set OTG_FS_IRQHandler,Default_Handler
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487
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488 .weak DMA2_Channel6_IRQHandler
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489 .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
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490
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491 .weak DMA2_Channel7_IRQHandler
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492 .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
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493
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494 .weak LPUART1_IRQHandler
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495 .thumb_set LPUART1_IRQHandler,Default_Handler
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496
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497 .weak QUADSPI_IRQHandler
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498 .thumb_set QUADSPI_IRQHandler,Default_Handler
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499
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500 .weak I2C3_EV_IRQHandler
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501 .thumb_set I2C3_EV_IRQHandler,Default_Handler
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502
|
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503 .weak I2C3_ER_IRQHandler
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|
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504 .thumb_set I2C3_ER_IRQHandler,Default_Handler
|
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505
|
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506 .weak SAI1_IRQHandler
|
|
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507 .thumb_set SAI1_IRQHandler,Default_Handler
|
|
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508
|
|
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509 .weak SAI2_IRQHandler
|
|
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510 .thumb_set SAI2_IRQHandler,Default_Handler
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|
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511
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512 .weak SWPMI1_IRQHandler
|
|
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513 .thumb_set SWPMI1_IRQHandler,Default_Handler
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|
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514
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515 .weak TSC_IRQHandler
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|
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516 .thumb_set TSC_IRQHandler,Default_Handler
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517
|
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518 .weak LCD_IRQHandler
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|
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519 .thumb_set LCD_IRQHandler,Default_Handler
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520
|
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521 .weak AES_IRQHandler
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522 .thumb_set AES_IRQHandler,Default_Handler
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523
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524 .weak RNG_IRQHandler
|
|
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525 .thumb_set RNG_IRQHandler,Default_Handler
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|
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526
|
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527 .weak FPU_IRQHandler
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528 .thumb_set FPU_IRQHandler,Default_Handler
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529 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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