|
0
|
1 /**
|
|
|
2 ******************************************************************************
|
|
|
3 * @file stm32l4xx_hal_dma.h
|
|
|
4 * @author MCD Application Team
|
|
|
5 * @version V1.6.0
|
|
|
6 * @date 28-October-2016
|
|
|
7 * @brief Header file of DMA HAL module.
|
|
|
8 ******************************************************************************
|
|
|
9 * @attention
|
|
|
10 *
|
|
|
11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
|
|
12 *
|
|
|
13 * Redistribution and use in source and binary forms, with or without modification,
|
|
|
14 * are permitted provided that the following conditions are met:
|
|
|
15 * 1. Redistributions of source code must retain the above copyright notice,
|
|
|
16 * this list of conditions and the following disclaimer.
|
|
|
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
|
18 * this list of conditions and the following disclaimer in the documentation
|
|
|
19 * and/or other materials provided with the distribution.
|
|
|
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
|
21 * may be used to endorse or promote products derived from this software
|
|
|
22 * without specific prior written permission.
|
|
|
23 *
|
|
|
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
|
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
|
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
|
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
|
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
|
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
|
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
|
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
|
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
34 *
|
|
|
35 ******************************************************************************
|
|
|
36 */
|
|
|
37
|
|
|
38 /* Define to prevent recursive inclusion -------------------------------------*/
|
|
|
39 #ifndef __STM32L4xx_HAL_DMA_H
|
|
|
40 #define __STM32L4xx_HAL_DMA_H
|
|
|
41
|
|
|
42 #ifdef __cplusplus
|
|
|
43 extern "C" {
|
|
|
44 #endif
|
|
|
45
|
|
|
46 /* Includes ------------------------------------------------------------------*/
|
|
|
47 #include "stm32l4xx_hal_def.h"
|
|
|
48
|
|
|
49 /** @addtogroup STM32L4xx_HAL_Driver
|
|
|
50 * @{
|
|
|
51 */
|
|
|
52
|
|
|
53 /** @addtogroup DMA
|
|
|
54 * @{
|
|
|
55 */
|
|
|
56
|
|
|
57 /* Exported types ------------------------------------------------------------*/
|
|
|
58
|
|
|
59 /** @defgroup DMA_Exported_Types DMA Exported Types
|
|
|
60 * @{
|
|
|
61 */
|
|
|
62
|
|
|
63 /**
|
|
|
64 * @brief DMA Configuration Structure definition
|
|
|
65 */
|
|
|
66 typedef struct
|
|
|
67 {
|
|
|
68 uint32_t Request; /*!< Specifies the request selected for the specified channel.
|
|
|
69 This parameter can be a value of @ref DMA_request */
|
|
|
70
|
|
|
71 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
|
|
72 from memory to memory or from peripheral to memory.
|
|
|
73 This parameter can be a value of @ref DMA_Data_transfer_direction */
|
|
|
74
|
|
|
75 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
|
|
76 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
|
|
77
|
|
|
78 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
|
|
79 This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
|
|
80
|
|
|
81 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
|
|
82 This parameter can be a value of @ref DMA_Peripheral_data_size */
|
|
|
83
|
|
|
84 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
|
|
85 This parameter can be a value of @ref DMA_Memory_data_size */
|
|
|
86
|
|
|
87 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
|
|
88 This parameter can be a value of @ref DMA_mode
|
|
|
89 @note The circular buffer mode cannot be used if the memory-to-memory
|
|
|
90 data transfer is configured on the selected Channel */
|
|
|
91
|
|
|
92 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
|
|
93 This parameter can be a value of @ref DMA_Priority_level */
|
|
|
94 } DMA_InitTypeDef;
|
|
|
95
|
|
|
96 /**
|
|
|
97 * @brief HAL DMA State structures definition
|
|
|
98 */
|
|
|
99 typedef enum
|
|
|
100 {
|
|
|
101 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
|
|
|
102 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
|
|
|
103 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
|
|
|
104 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
|
|
|
105 }HAL_DMA_StateTypeDef;
|
|
|
106
|
|
|
107 /**
|
|
|
108 * @brief HAL DMA Error Code structure definition
|
|
|
109 */
|
|
|
110 typedef enum
|
|
|
111 {
|
|
|
112 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
|
|
|
113 HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
|
|
|
114 }HAL_DMA_LevelCompleteTypeDef;
|
|
|
115
|
|
|
116
|
|
|
117 /**
|
|
|
118 * @brief HAL DMA Callback ID structure definition
|
|
|
119 */
|
|
|
120 typedef enum
|
|
|
121 {
|
|
|
122 HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */
|
|
|
123 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */
|
|
|
124 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */
|
|
|
125 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */
|
|
|
126 HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
|
|
|
127
|
|
|
128 }HAL_DMA_CallbackIDTypeDef;
|
|
|
129
|
|
|
130 /**
|
|
|
131 * @brief DMA handle Structure definition
|
|
|
132 */
|
|
|
133 typedef struct __DMA_HandleTypeDef
|
|
|
134 {
|
|
|
135 DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
|
|
136
|
|
|
137 DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
|
|
138
|
|
|
139 HAL_LockTypeDef Lock; /*!< DMA locking object */
|
|
|
140
|
|
|
141 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
|
|
142
|
|
|
143 void *Parent; /*!< Parent object state */
|
|
|
144
|
|
|
145 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
|
|
146
|
|
|
147 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
|
|
148
|
|
|
149 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
|
|
150
|
|
|
151 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
|
|
|
152
|
|
|
153 __IO uint32_t ErrorCode; /*!< DMA Error code */
|
|
|
154
|
|
|
155 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
|
|
156
|
|
|
157 uint32_t ChannelIndex; /*!< DMA Channel Index */
|
|
|
158 }DMA_HandleTypeDef;
|
|
|
159 /**
|
|
|
160 * @}
|
|
|
161 */
|
|
|
162
|
|
|
163 /* Exported constants --------------------------------------------------------*/
|
|
|
164
|
|
|
165 /** @defgroup DMA_Exported_Constants DMA Exported Constants
|
|
|
166 * @{
|
|
|
167 */
|
|
|
168
|
|
|
169 /** @defgroup DMA_Error_Code DMA Error Code
|
|
|
170 * @{
|
|
|
171 */
|
|
|
172 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
|
|
|
173 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
|
|
|
174 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */
|
|
|
175 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
|
|
|
176 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /*!< Not supported mode */
|
|
|
177 /**
|
|
|
178 * @}
|
|
|
179 */
|
|
|
180
|
|
|
181 /** @defgroup DMA_request DMA request
|
|
|
182 * @{
|
|
|
183 */
|
|
|
184 #define DMA_REQUEST_0 ((uint32_t)0x00000000)
|
|
|
185 #define DMA_REQUEST_1 ((uint32_t)0x00000001)
|
|
|
186 #define DMA_REQUEST_2 ((uint32_t)0x00000002)
|
|
|
187 #define DMA_REQUEST_3 ((uint32_t)0x00000003)
|
|
|
188 #define DMA_REQUEST_4 ((uint32_t)0x00000004)
|
|
|
189 #define DMA_REQUEST_5 ((uint32_t)0x00000005)
|
|
|
190 #define DMA_REQUEST_6 ((uint32_t)0x00000006)
|
|
|
191 #define DMA_REQUEST_7 ((uint32_t)0x00000007)
|
|
|
192 /**
|
|
|
193 * @}
|
|
|
194 */
|
|
|
195
|
|
|
196 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
|
|
197 * @{
|
|
|
198 */
|
|
|
199 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
|
|
|
200 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
|
|
|
201 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
|
|
|
202 /**
|
|
|
203 * @}
|
|
|
204 */
|
|
|
205
|
|
|
206 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
|
|
207 * @{
|
|
|
208 */
|
|
|
209 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
|
|
|
210 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
|
|
|
211 /**
|
|
|
212 * @}
|
|
|
213 */
|
|
|
214
|
|
|
215 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
|
|
216 * @{
|
|
|
217 */
|
|
|
218 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
|
|
|
219 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
|
|
|
220 /**
|
|
|
221 * @}
|
|
|
222 */
|
|
|
223
|
|
|
224 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
|
|
225 * @{
|
|
|
226 */
|
|
|
227 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
|
|
|
228 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
|
|
|
229 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
|
|
|
230 /**
|
|
|
231 * @}
|
|
|
232 */
|
|
|
233
|
|
|
234 /** @defgroup DMA_Memory_data_size DMA Memory data size
|
|
|
235 * @{
|
|
|
236 */
|
|
|
237 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
|
|
|
238 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
|
|
|
239 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
|
|
|
240 /**
|
|
|
241 * @}
|
|
|
242 */
|
|
|
243
|
|
|
244 /** @defgroup DMA_mode DMA mode
|
|
|
245 * @{
|
|
|
246 */
|
|
|
247 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
|
|
|
248 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
|
|
|
249 /**
|
|
|
250 * @}
|
|
|
251 */
|
|
|
252
|
|
|
253 /** @defgroup DMA_Priority_level DMA Priority level
|
|
|
254 * @{
|
|
|
255 */
|
|
|
256 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
|
|
|
257 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
|
|
|
258 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
|
|
|
259 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
|
|
|
260 /**
|
|
|
261 * @}
|
|
|
262 */
|
|
|
263
|
|
|
264
|
|
|
265 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
|
|
266 * @{
|
|
|
267 */
|
|
|
268 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
|
|
|
269 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
|
|
|
270 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
|
|
|
271 /**
|
|
|
272 * @}
|
|
|
273 */
|
|
|
274
|
|
|
275 /** @defgroup DMA_flag_definitions DMA flag definitions
|
|
|
276 * @{
|
|
|
277 */
|
|
|
278 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
|
|
|
279 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
|
|
|
280 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
|
|
|
281 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
|
|
|
282 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
|
|
|
283 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
|
|
|
284 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
|
|
|
285 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
|
|
|
286 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
|
|
|
287 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
|
|
|
288 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
|
|
|
289 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
|
|
|
290 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
|
|
|
291 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
|
|
|
292 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
|
|
|
293 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
|
|
|
294 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
|
|
|
295 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
|
|
|
296 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
|
|
|
297 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
|
|
|
298 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
|
|
|
299 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
|
|
|
300 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
|
|
|
301 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
|
|
|
302 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
|
|
|
303 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
|
|
|
304 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
|
|
|
305 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
|
|
|
306 /**
|
|
|
307 * @}
|
|
|
308 */
|
|
|
309
|
|
|
310 /**
|
|
|
311 * @}
|
|
|
312 */
|
|
|
313
|
|
|
314 /* Exported macros -----------------------------------------------------------*/
|
|
|
315 /** @defgroup DMA_Exported_Macros DMA Exported Macros
|
|
|
316 * @{
|
|
|
317 */
|
|
|
318
|
|
|
319 /** @brief Reset DMA handle state.
|
|
|
320 * @param __HANDLE__: DMA handle
|
|
|
321 * @retval None
|
|
|
322 */
|
|
|
323 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
|
|
324
|
|
|
325 /**
|
|
|
326 * @brief Enable the specified DMA Channel.
|
|
|
327 * @param __HANDLE__: DMA handle
|
|
|
328 * @retval None
|
|
|
329 */
|
|
|
330 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
|
|
331
|
|
|
332 /**
|
|
|
333 * @brief Disable the specified DMA Channel.
|
|
|
334 * @param __HANDLE__: DMA handle
|
|
|
335 * @retval None
|
|
|
336 */
|
|
|
337 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
|
|
338
|
|
|
339
|
|
|
340 /* Interrupt & Flag management */
|
|
|
341
|
|
|
342 /**
|
|
|
343 * @brief Return the current DMA Channel transfer complete flag.
|
|
|
344 * @param __HANDLE__: DMA handle
|
|
|
345 * @retval The specified transfer complete flag index.
|
|
|
346 */
|
|
|
347
|
|
|
348 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
|
|
349 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
|
|
350 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
|
|
351 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
|
|
352 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
|
|
353 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
|
|
354 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
|
|
355 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
|
|
356 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
|
|
357 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
|
|
358 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
|
|
|
359 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
|
|
360 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
|
|
|
361 DMA_FLAG_TC7)
|
|
|
362
|
|
|
363 /**
|
|
|
364 * @brief Return the current DMA Channel half transfer complete flag.
|
|
|
365 * @param __HANDLE__: DMA handle
|
|
|
366 * @retval The specified half transfer complete flag index.
|
|
|
367 */
|
|
|
368 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
|
|
369 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
|
|
370 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
|
|
371 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
|
|
372 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
|
|
373 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
|
|
374 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
|
|
375 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
|
|
376 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
|
|
377 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
|
|
378 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
|
|
|
379 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
|
|
380 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
|
|
|
381 DMA_FLAG_HT7)
|
|
|
382
|
|
|
383 /**
|
|
|
384 * @brief Return the current DMA Channel transfer error flag.
|
|
|
385 * @param __HANDLE__: DMA handle
|
|
|
386 * @retval The specified transfer error flag index.
|
|
|
387 */
|
|
|
388 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
|
|
389 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
|
|
390 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
|
|
391 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
|
|
392 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
|
|
393 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
|
|
394 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
|
|
395 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
|
|
396 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
|
|
397 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
|
|
398 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
|
|
|
399 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
|
|
400 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
|
|
|
401 DMA_FLAG_TE7)
|
|
|
402
|
|
|
403 /**
|
|
|
404 * @brief Return the current DMA Channel Global interrupt flag.
|
|
|
405 * @param __HANDLE__: DMA handle
|
|
|
406 * @retval The specified transfer error flag index.
|
|
|
407 */
|
|
|
408 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
|
|
409 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
|
|
410 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
|
|
|
411 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
|
|
412 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
|
|
|
413 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
|
|
414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
|
|
|
415 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
|
|
416 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
|
|
|
417 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
|
|
418 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
|
|
|
419 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
|
|
|
420 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
|
|
|
421 DMA_ISR_GIF7)
|
|
|
422
|
|
|
423 /**
|
|
|
424 * @brief Get the DMA Channel pending flags.
|
|
|
425 * @param __HANDLE__: DMA handle
|
|
|
426 * @param __FLAG__: Get the specified flag.
|
|
|
427 * This parameter can be any combination of the following values:
|
|
|
428 * @arg DMA_FLAG_TCx: Transfer complete flag
|
|
|
429 * @arg DMA_FLAG_HTx: Half transfer complete flag
|
|
|
430 * @arg DMA_FLAG_TEx: Transfer error flag
|
|
|
431 * @arg DMA_FLAG_GLx: Global interrupt flag
|
|
|
432 * Where x can be from 1 to 7 to select the DMA Channel x flag.
|
|
|
433 * @retval The state of FLAG (SET or RESET).
|
|
|
434 */
|
|
|
435 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
|
|
436 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
|
|
|
437
|
|
|
438 /**
|
|
|
439 * @brief Clear the DMA Channel pending flags.
|
|
|
440 * @param __HANDLE__: DMA handle
|
|
|
441 * @param __FLAG__: specifies the flag to clear.
|
|
|
442 * This parameter can be any combination of the following values:
|
|
|
443 * @arg DMA_FLAG_TCx: Transfer complete flag
|
|
|
444 * @arg DMA_FLAG_HTx: Half transfer complete flag
|
|
|
445 * @arg DMA_FLAG_TEx: Transfer error flag
|
|
|
446 * @arg DMA_FLAG_GLx: Global interrupt flag
|
|
|
447 * Where x can be from 1 to 7 to select the DMA Channel x flag.
|
|
|
448 * @retval None
|
|
|
449 */
|
|
|
450 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
|
|
451 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
|
|
|
452
|
|
|
453 /**
|
|
|
454 * @brief Enable the specified DMA Channel interrupts.
|
|
|
455 * @param __HANDLE__: DMA handle
|
|
|
456 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
|
|
457 * This parameter can be any combination of the following values:
|
|
|
458 * @arg DMA_IT_TC: Transfer complete interrupt mask
|
|
|
459 * @arg DMA_IT_HT: Half transfer complete interrupt mask
|
|
|
460 * @arg DMA_IT_TE: Transfer error interrupt mask
|
|
|
461 * @retval None
|
|
|
462 */
|
|
|
463 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
|
|
464
|
|
|
465 /**
|
|
|
466 * @brief Disable the specified DMA Channel interrupts.
|
|
|
467 * @param __HANDLE__: DMA handle
|
|
|
468 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
|
|
469 * This parameter can be any combination of the following values:
|
|
|
470 * @arg DMA_IT_TC: Transfer complete interrupt mask
|
|
|
471 * @arg DMA_IT_HT: Half transfer complete interrupt mask
|
|
|
472 * @arg DMA_IT_TE: Transfer error interrupt mask
|
|
|
473 * @retval None
|
|
|
474 */
|
|
|
475 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
|
|
476
|
|
|
477 /**
|
|
|
478 * @brief Check whether the specified DMA Channel interrupt is enabled or not.
|
|
|
479 * @param __HANDLE__: DMA handle
|
|
|
480 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
|
|
|
481 * This parameter can be one of the following values:
|
|
|
482 * @arg DMA_IT_TC: Transfer complete interrupt mask
|
|
|
483 * @arg DMA_IT_HT: Half transfer complete interrupt mask
|
|
|
484 * @arg DMA_IT_TE: Transfer error interrupt mask
|
|
|
485 * @retval The state of DMA_IT (SET or RESET).
|
|
|
486 */
|
|
|
487 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
|
|
488
|
|
|
489 /**
|
|
|
490 * @brief Return the number of remaining data units in the current DMA Channel transfer.
|
|
|
491 * @param __HANDLE__: DMA handle
|
|
|
492 * @retval The number of remaining data units in the current DMA Channel transfer.
|
|
|
493 */
|
|
|
494 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
|
|
495
|
|
|
496 /**
|
|
|
497 * @}
|
|
|
498 */
|
|
|
499
|
|
|
500 /* Exported functions --------------------------------------------------------*/
|
|
|
501
|
|
|
502 /** @addtogroup DMA_Exported_Functions
|
|
|
503 * @{
|
|
|
504 */
|
|
|
505
|
|
|
506 /** @addtogroup DMA_Exported_Functions_Group1
|
|
|
507 * @{
|
|
|
508 */
|
|
|
509 /* Initialization and de-initialization functions *****************************/
|
|
|
510 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
|
|
511 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
|
|
|
512 /**
|
|
|
513 * @}
|
|
|
514 */
|
|
|
515
|
|
|
516 /** @addtogroup DMA_Exported_Functions_Group2
|
|
|
517 * @{
|
|
|
518 */
|
|
|
519 /* IO operation functions *****************************************************/
|
|
|
520 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
|
|
521 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
|
|
522 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
|
|
523 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
|
|
524 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
|
|
|
525 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
|
|
526 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
|
|
|
527 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
|
|
528
|
|
|
529 /**
|
|
|
530 * @}
|
|
|
531 */
|
|
|
532
|
|
|
533 /** @addtogroup DMA_Exported_Functions_Group3
|
|
|
534 * @{
|
|
|
535 */
|
|
|
536 /* Peripheral State and Error functions ***************************************/
|
|
|
537 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
|
|
538 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
|
|
539 /**
|
|
|
540 * @}
|
|
|
541 */
|
|
|
542
|
|
|
543 /**
|
|
|
544 * @}
|
|
|
545 */
|
|
|
546
|
|
|
547 /* Private macros ------------------------------------------------------------*/
|
|
|
548 /** @defgroup DMA_Private_Macros DMA Private Macros
|
|
|
549 * @{
|
|
|
550 */
|
|
|
551
|
|
|
552 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
|
|
553 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
|
|
554 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
|
|
555
|
|
|
556 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
|
|
557
|
|
|
558 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
|
|
559 ((STATE) == DMA_PINC_DISABLE))
|
|
|
560
|
|
|
561 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
|
|
562 ((STATE) == DMA_MINC_DISABLE))
|
|
|
563
|
|
|
564 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
|
|
|
565 ((REQUEST) == DMA_REQUEST_1) || \
|
|
|
566 ((REQUEST) == DMA_REQUEST_2) || \
|
|
|
567 ((REQUEST) == DMA_REQUEST_3) || \
|
|
|
568 ((REQUEST) == DMA_REQUEST_4) || \
|
|
|
569 ((REQUEST) == DMA_REQUEST_5) || \
|
|
|
570 ((REQUEST) == DMA_REQUEST_6) || \
|
|
|
571 ((REQUEST) == DMA_REQUEST_7))
|
|
|
572
|
|
|
573 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
|
|
574 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
|
|
575 ((SIZE) == DMA_PDATAALIGN_WORD))
|
|
|
576
|
|
|
577 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
|
|
578 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
|
|
579 ((SIZE) == DMA_MDATAALIGN_WORD ))
|
|
|
580
|
|
|
581 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
|
|
582 ((MODE) == DMA_CIRCULAR))
|
|
|
583
|
|
|
584 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
|
|
585 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
|
|
586 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
|
|
587 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
|
|
588
|
|
|
589 /**
|
|
|
590 * @}
|
|
|
591 */
|
|
|
592
|
|
|
593 /* Private functions ---------------------------------------------------------*/
|
|
|
594
|
|
|
595 /**
|
|
|
596 * @}
|
|
|
597 */
|
|
|
598
|
|
|
599 /**
|
|
|
600 * @}
|
|
|
601 */
|
|
|
602
|
|
|
603 #ifdef __cplusplus
|
|
|
604 }
|
|
|
605 #endif
|
|
|
606
|
|
|
607 #endif /* __STM32L4xx_HAL_DMA_H */
|
|
|
608
|
|
|
609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
