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comparison f103c8/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c @ 2:0c59e7a7782a
Working on GPIO and RCC
author | cin |
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date | Mon, 16 Jan 2017 11:04:47 +0300 |
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1 /* ---------------------------------------------------------------------- | |
2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved. | |
3 * | |
4 * $Date: 19. March 2015 | |
5 * $Revision: V.1.4.5 | |
6 * | |
7 * Project: CMSIS DSP Library | |
8 * Title: arm_min_q31.c | |
9 * | |
10 * Description: Minimum value of a Q31 vector. | |
11 * | |
12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 | |
13 * | |
14 * Redistribution and use in source and binary forms, with or without | |
15 * modification, are permitted provided that the following conditions | |
16 * are met: | |
17 * - Redistributions of source code must retain the above copyright | |
18 * notice, this list of conditions and the following disclaimer. | |
19 * - Redistributions in binary form must reproduce the above copyright | |
20 * notice, this list of conditions and the following disclaimer in | |
21 * the documentation and/or other materials provided with the | |
22 * distribution. | |
23 * - Neither the name of ARM LIMITED nor the names of its contributors | |
24 * may be used to endorse or promote products derived from this | |
25 * software without specific prior written permission. | |
26 * | |
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN | |
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
38 * POSSIBILITY OF SUCH DAMAGE. | |
39 * ---------------------------------------------------------------------------- */ | |
40 | |
41 #include "arm_math.h" | |
42 | |
43 /** | |
44 * @ingroup groupStats | |
45 */ | |
46 | |
47 | |
48 /** | |
49 * @addtogroup Min | |
50 * @{ | |
51 */ | |
52 | |
53 | |
54 /** | |
55 * @brief Minimum value of a Q31 vector. | |
56 * @param[in] *pSrc points to the input vector | |
57 * @param[in] blockSize length of the input vector | |
58 * @param[out] *pResult minimum value returned here | |
59 * @param[out] *pIndex index of minimum value returned here | |
60 * @return none. | |
61 * | |
62 */ | |
63 | |
64 void arm_min_q31( | |
65 q31_t * pSrc, | |
66 uint32_t blockSize, | |
67 q31_t * pResult, | |
68 uint32_t * pIndex) | |
69 { | |
70 #ifndef ARM_MATH_CM0_FAMILY | |
71 | |
72 /* Run the below code for Cortex-M4 and Cortex-M3 */ | |
73 q31_t minVal1, minVal2, out; /* Temporary variables to store the output value. */ | |
74 uint32_t blkCnt, outIndex, count; /* loop counter */ | |
75 | |
76 /* Initialise the count value. */ | |
77 count = 0u; | |
78 /* Initialise the index value to zero. */ | |
79 outIndex = 0u; | |
80 /* Load first input value that act as reference value for comparision */ | |
81 out = *pSrc++; | |
82 | |
83 | |
84 /* Loop unrolling */ | |
85 blkCnt = (blockSize - 1u) >> 2u; | |
86 | |
87 while(blkCnt > 0) | |
88 { | |
89 /* Initialize minVal to the next consecutive values one by one */ | |
90 minVal1 = *pSrc++; | |
91 minVal2 = *pSrc++; | |
92 | |
93 /* compare for the minimum value */ | |
94 if(out > minVal1) | |
95 { | |
96 /* Update the minimum value and its index */ | |
97 out = minVal1; | |
98 outIndex = count + 1u; | |
99 } | |
100 | |
101 minVal1 = *pSrc++; | |
102 | |
103 /* compare for the minimum value */ | |
104 if(out > minVal2) | |
105 { | |
106 /* Update the minimum value and its index */ | |
107 out = minVal2; | |
108 outIndex = count + 2u; | |
109 } | |
110 | |
111 minVal2 = *pSrc++; | |
112 | |
113 /* compare for the minimum value */ | |
114 if(out > minVal1) | |
115 { | |
116 /* Update the minimum value and its index */ | |
117 out = minVal1; | |
118 outIndex = count + 3u; | |
119 } | |
120 | |
121 /* compare for the minimum value */ | |
122 if(out > minVal2) | |
123 { | |
124 /* Update the minimum value and its index */ | |
125 out = minVal2; | |
126 outIndex = count + 4u; | |
127 } | |
128 | |
129 count += 4u; | |
130 | |
131 blkCnt--; | |
132 } | |
133 | |
134 /* if (blockSize - 1u ) is not multiple of 4 */ | |
135 blkCnt = (blockSize - 1u) % 4u; | |
136 | |
137 #else | |
138 | |
139 /* Run the below code for Cortex-M0 */ | |
140 q31_t minVal1, out; /* Temporary variables to store the output value. */ | |
141 uint32_t blkCnt, outIndex; /* loop counter */ | |
142 | |
143 blkCnt = (blockSize - 1u); | |
144 | |
145 /* Initialise the index value to zero. */ | |
146 outIndex = 0u; | |
147 /* Load first input value that act as reference value for comparision */ | |
148 out = *pSrc++; | |
149 | |
150 #endif // #ifndef ARM_MATH_CM0_FAMILY | |
151 | |
152 while(blkCnt > 0) | |
153 { | |
154 /* Initialize minVal to the next consecutive values one by one */ | |
155 minVal1 = *pSrc++; | |
156 | |
157 /* compare for the minimum value */ | |
158 if(out > minVal1) | |
159 { | |
160 /* Update the minimum value and it's index */ | |
161 out = minVal1; | |
162 outIndex = blockSize - blkCnt; | |
163 } | |
164 | |
165 blkCnt--; | |
166 | |
167 } | |
168 | |
169 /* Store the minimum value and its index into destination pointers */ | |
170 *pResult = out; | |
171 *pIndex = outIndex; | |
172 } | |
173 | |
174 /** | |
175 * @} end of Min group | |
176 */ |