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comparison f103c8/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c @ 2:0c59e7a7782a
Working on GPIO and RCC
author | cin |
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date | Mon, 16 Jan 2017 11:04:47 +0300 |
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1 /* ---------------------------------------------------------------------- | |
2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved. | |
3 * | |
4 * $Date: 19. March 2015 | |
5 * $Revision: V.1.4.5 | |
6 * | |
7 * Project: CMSIS DSP Library | |
8 * Title: arm_min_q7.c | |
9 * | |
10 * Description: Minimum value of a Q7 vector. | |
11 * | |
12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 | |
13 * | |
14 * Redistribution and use in source and binary forms, with or without | |
15 * modification, are permitted provided that the following conditions | |
16 * are met: | |
17 * - Redistributions of source code must retain the above copyright | |
18 * notice, this list of conditions and the following disclaimer. | |
19 * - Redistributions in binary form must reproduce the above copyright | |
20 * notice, this list of conditions and the following disclaimer in | |
21 * the documentation and/or other materials provided with the | |
22 * distribution. | |
23 * - Neither the name of ARM LIMITED nor the names of its contributors | |
24 * may be used to endorse or promote products derived from this | |
25 * software without specific prior written permission. | |
26 * | |
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN | |
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
38 * POSSIBILITY OF SUCH DAMAGE. | |
39 * ---------------------------------------------------------------------------- */ | |
40 | |
41 #include "arm_math.h" | |
42 | |
43 /** | |
44 * @ingroup groupStats | |
45 */ | |
46 | |
47 /** | |
48 * @addtogroup Min | |
49 * @{ | |
50 */ | |
51 | |
52 | |
53 /** | |
54 * @brief Minimum value of a Q7 vector. | |
55 * @param[in] *pSrc points to the input vector | |
56 * @param[in] blockSize length of the input vector | |
57 * @param[out] *pResult minimum value returned here | |
58 * @param[out] *pIndex index of minimum value returned here | |
59 * @return none. | |
60 * | |
61 */ | |
62 | |
63 void arm_min_q7( | |
64 q7_t * pSrc, | |
65 uint32_t blockSize, | |
66 q7_t * pResult, | |
67 uint32_t * pIndex) | |
68 { | |
69 #ifndef ARM_MATH_CM0_FAMILY | |
70 | |
71 /* Run the below code for Cortex-M4 and Cortex-M3 */ | |
72 | |
73 q7_t minVal1, minVal2, out; /* Temporary variables to store the output value. */ | |
74 uint32_t blkCnt, outIndex, count; /* loop counter */ | |
75 | |
76 /* Initialise the count value. */ | |
77 count = 0u; | |
78 /* Initialise the index value to zero. */ | |
79 outIndex = 0u; | |
80 /* Load first input value that act as reference value for comparision */ | |
81 out = *pSrc++; | |
82 | |
83 /* Loop unrolling */ | |
84 blkCnt = (blockSize - 1u) >> 2u; | |
85 | |
86 while(blkCnt > 0) | |
87 { | |
88 /* Initialize minVal to the next consecutive values one by one */ | |
89 minVal1 = *pSrc++; | |
90 minVal2 = *pSrc++; | |
91 | |
92 /* compare for the minimum value */ | |
93 if(out > minVal1) | |
94 { | |
95 /* Update the minimum value and its index */ | |
96 out = minVal1; | |
97 outIndex = count + 1u; | |
98 } | |
99 | |
100 minVal1 = *pSrc++; | |
101 | |
102 /* compare for the minimum value */ | |
103 if(out > minVal2) | |
104 { | |
105 /* Update the minimum value and its index */ | |
106 out = minVal2; | |
107 outIndex = count + 2u; | |
108 } | |
109 | |
110 minVal2 = *pSrc++; | |
111 | |
112 /* compare for the minimum value */ | |
113 if(out > minVal1) | |
114 { | |
115 /* Update the minimum value and its index */ | |
116 out = minVal1; | |
117 outIndex = count + 3u; | |
118 } | |
119 | |
120 /* compare for the minimum value */ | |
121 if(out > minVal2) | |
122 { | |
123 /* Update the minimum value and its index */ | |
124 out = minVal2; | |
125 outIndex = count + 4u; | |
126 } | |
127 | |
128 count += 4u; | |
129 | |
130 blkCnt--; | |
131 } | |
132 | |
133 /* if (blockSize - 1u ) is not multiple of 4 */ | |
134 blkCnt = (blockSize - 1u) % 4u; | |
135 | |
136 #else | |
137 | |
138 /* Run the below code for Cortex-M0 */ | |
139 | |
140 q7_t minVal1, out; /* Temporary variables to store the output value. */ | |
141 uint32_t blkCnt, outIndex; /* loop counter */ | |
142 | |
143 /* Initialise the index value to zero. */ | |
144 outIndex = 0u; | |
145 /* Load first input value that act as reference value for comparision */ | |
146 out = *pSrc++; | |
147 | |
148 blkCnt = (blockSize - 1u); | |
149 | |
150 #endif // #ifndef ARM_MATH_CM0_FAMILY | |
151 | |
152 while(blkCnt > 0) | |
153 { | |
154 /* Initialize minVal to the next consecutive values one by one */ | |
155 minVal1 = *pSrc++; | |
156 | |
157 /* compare for the minimum value */ | |
158 if(out > minVal1) | |
159 { | |
160 /* Update the minimum value and it's index */ | |
161 out = minVal1; | |
162 outIndex = blockSize - blkCnt; | |
163 } | |
164 | |
165 blkCnt--; | |
166 | |
167 } | |
168 | |
169 /* Store the minimum value and its index into destination pointers */ | |
170 *pResult = out; | |
171 *pIndex = outIndex; | |
172 | |
173 | |
174 } | |
175 | |
176 /** | |
177 * @} end of Min group | |
178 */ |