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comparison f103c8/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h @ 2:0c59e7a7782a

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Working on GPIO and RCC
author cin
date Mon, 16 Jan 2017 11:04:47 +0300
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1:a0b14b11ad9f 2:0c59e7a7782a
1 /**
2 ******************************************************************************
3 * @file stm32f103xb.h
4 * @author MCD Application Team
5 * @version V4.1.0
6 * @date 29-April-2016
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for STM32F1xx devices.
10 *
11 * This file contains:
12 * - Data structures and the address mapping for all peripherals
13 * - Peripheral's registers declarations and bits definition
14 * - Macros to access peripheral’s registers hardware
15 *
16 ******************************************************************************
17 * @attention
18 *
19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
20 *
21 * Redistribution and use in source and binary forms, with or without modification,
22 * are permitted provided that the following conditions are met:
23 * 1. Redistributions of source code must retain the above copyright notice,
24 * this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright notice,
26 * this list of conditions and the following disclaimer in the documentation
27 * and/or other materials provided with the distribution.
28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
29 * may be used to endorse or promote products derived from this software
30 * without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 ******************************************************************************
44 */
45
46
47 /** @addtogroup CMSIS
48 * @{
49 */
50
51 /** @addtogroup stm32f103xb
52 * @{
53 */
54
55 #ifndef __STM32F103xB_H
56 #define __STM32F103xB_H
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 /** @addtogroup Configuration_section_for_CMSIS
63 * @{
64 */
65 /**
66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
67 */
68 #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
69 #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
70 #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
71 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
72
73 /**
74 * @}
75 */
76
77 /** @addtogroup Peripheral_interrupt_number_definition
78 * @{
79 */
80
81 /**
82 * @brief STM32F10x Interrupt Number Definition, according to the selected device
83 * in @ref Library_configuration_section
84 */
85
86 /*!< Interrupt Number Definition */
87 typedef enum
88 {
89 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
91 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
92 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
93 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
94 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
95 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
96 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
97 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
98 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
99
100 /****** STM32 specific Interrupt Numbers *********************************************************/
101 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
102 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
103 TAMPER_IRQn = 2, /*!< Tamper Interrupt */
104 RTC_IRQn = 3, /*!< RTC global Interrupt */
105 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
106 RCC_IRQn = 5, /*!< RCC global Interrupt */
107 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
108 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
109 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
110 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
111 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
112 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
113 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
114 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
115 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
116 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
117 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
118 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
119 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
120 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
121 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
122 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
123 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
124 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
125 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
126 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
127 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
128 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
129 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
130 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
131 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
132 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
133 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
134 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
135 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
136 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
137 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
138 USART1_IRQn = 37, /*!< USART1 global Interrupt */
139 USART2_IRQn = 38, /*!< USART2 global Interrupt */
140 USART3_IRQn = 39, /*!< USART3 global Interrupt */
141 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
142 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
143 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
144 } IRQn_Type;
145
146
147 /**
148 * @}
149 */
150
151 #include "core_cm3.h"
152 #include "system_stm32f1xx.h"
153 #include <stdint.h>
154
155 /** @addtogroup Peripheral_registers_structures
156 * @{
157 */
158
159 /**
160 * @brief Analog to Digital Converter
161 */
162
163 typedef struct
164 {
165 __IO uint32_t SR;
166 __IO uint32_t CR1;
167 __IO uint32_t CR2;
168 __IO uint32_t SMPR1;
169 __IO uint32_t SMPR2;
170 __IO uint32_t JOFR1;
171 __IO uint32_t JOFR2;
172 __IO uint32_t JOFR3;
173 __IO uint32_t JOFR4;
174 __IO uint32_t HTR;
175 __IO uint32_t LTR;
176 __IO uint32_t SQR1;
177 __IO uint32_t SQR2;
178 __IO uint32_t SQR3;
179 __IO uint32_t JSQR;
180 __IO uint32_t JDR1;
181 __IO uint32_t JDR2;
182 __IO uint32_t JDR3;
183 __IO uint32_t JDR4;
184 __IO uint32_t DR;
185 } ADC_TypeDef;
186
187 typedef struct
188 {
189 __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
190 __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
191 __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
192 uint32_t RESERVED[16];
193 __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
194 } ADC_Common_TypeDef;
195
196 /**
197 * @brief Backup Registers
198 */
199
200 typedef struct
201 {
202 uint32_t RESERVED0;
203 __IO uint32_t DR1;
204 __IO uint32_t DR2;
205 __IO uint32_t DR3;
206 __IO uint32_t DR4;
207 __IO uint32_t DR5;
208 __IO uint32_t DR6;
209 __IO uint32_t DR7;
210 __IO uint32_t DR8;
211 __IO uint32_t DR9;
212 __IO uint32_t DR10;
213 __IO uint32_t RTCCR;
214 __IO uint32_t CR;
215 __IO uint32_t CSR;
216 } BKP_TypeDef;
217
218 /**
219 * @brief Controller Area Network TxMailBox
220 */
221
222 typedef struct
223 {
224 __IO uint32_t TIR;
225 __IO uint32_t TDTR;
226 __IO uint32_t TDLR;
227 __IO uint32_t TDHR;
228 } CAN_TxMailBox_TypeDef;
229
230 /**
231 * @brief Controller Area Network FIFOMailBox
232 */
233
234 typedef struct
235 {
236 __IO uint32_t RIR;
237 __IO uint32_t RDTR;
238 __IO uint32_t RDLR;
239 __IO uint32_t RDHR;
240 } CAN_FIFOMailBox_TypeDef;
241
242 /**
243 * @brief Controller Area Network FilterRegister
244 */
245
246 typedef struct
247 {
248 __IO uint32_t FR1;
249 __IO uint32_t FR2;
250 } CAN_FilterRegister_TypeDef;
251
252 /**
253 * @brief Controller Area Network
254 */
255
256 typedef struct
257 {
258 __IO uint32_t MCR;
259 __IO uint32_t MSR;
260 __IO uint32_t TSR;
261 __IO uint32_t RF0R;
262 __IO uint32_t RF1R;
263 __IO uint32_t IER;
264 __IO uint32_t ESR;
265 __IO uint32_t BTR;
266 uint32_t RESERVED0[88];
267 CAN_TxMailBox_TypeDef sTxMailBox[3];
268 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
269 uint32_t RESERVED1[12];
270 __IO uint32_t FMR;
271 __IO uint32_t FM1R;
272 uint32_t RESERVED2;
273 __IO uint32_t FS1R;
274 uint32_t RESERVED3;
275 __IO uint32_t FFA1R;
276 uint32_t RESERVED4;
277 __IO uint32_t FA1R;
278 uint32_t RESERVED5[8];
279 CAN_FilterRegister_TypeDef sFilterRegister[14];
280 } CAN_TypeDef;
281
282 /**
283 * @brief CRC calculation unit
284 */
285
286 typedef struct
287 {
288 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
289 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
290 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
291 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
292 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
293 } CRC_TypeDef;
294
295
296 /**
297 * @brief Debug MCU
298 */
299
300 typedef struct
301 {
302 __IO uint32_t IDCODE;
303 __IO uint32_t CR;
304 }DBGMCU_TypeDef;
305
306 /**
307 * @brief DMA Controller
308 */
309
310 typedef struct
311 {
312 __IO uint32_t CCR;
313 __IO uint32_t CNDTR;
314 __IO uint32_t CPAR;
315 __IO uint32_t CMAR;
316 } DMA_Channel_TypeDef;
317
318 typedef struct
319 {
320 __IO uint32_t ISR;
321 __IO uint32_t IFCR;
322 } DMA_TypeDef;
323
324
325
326 /**
327 * @brief External Interrupt/Event Controller
328 */
329
330 typedef struct
331 {
332 __IO uint32_t IMR;
333 __IO uint32_t EMR;
334 __IO uint32_t RTSR;
335 __IO uint32_t FTSR;
336 __IO uint32_t SWIER;
337 __IO uint32_t PR;
338 } EXTI_TypeDef;
339
340 /**
341 * @brief FLASH Registers
342 */
343
344 typedef struct
345 {
346 __IO uint32_t ACR;
347 __IO uint32_t KEYR;
348 __IO uint32_t OPTKEYR;
349 __IO uint32_t SR;
350 __IO uint32_t CR;
351 __IO uint32_t AR;
352 __IO uint32_t RESERVED;
353 __IO uint32_t OBR;
354 __IO uint32_t WRPR;
355 } FLASH_TypeDef;
356
357 /**
358 * @brief Option Bytes Registers
359 */
360
361 typedef struct
362 {
363 __IO uint16_t RDP;
364 __IO uint16_t USER;
365 __IO uint16_t Data0;
366 __IO uint16_t Data1;
367 __IO uint16_t WRP0;
368 __IO uint16_t WRP1;
369 __IO uint16_t WRP2;
370 __IO uint16_t WRP3;
371 } OB_TypeDef;
372
373 /**
374 * @brief General Purpose I/O
375 */
376
377 typedef struct
378 {
379 __IO uint32_t CRL;
380 __IO uint32_t CRH;
381 __IO uint32_t IDR;
382 __IO uint32_t ODR;
383 __IO uint32_t BSRR;
384 __IO uint32_t BRR;
385 __IO uint32_t LCKR;
386 } GPIO_TypeDef;
387
388 /**
389 * @brief Alternate Function I/O
390 */
391
392 typedef struct
393 {
394 __IO uint32_t EVCR;
395 __IO uint32_t MAPR;
396 __IO uint32_t EXTICR[4];
397 uint32_t RESERVED0;
398 __IO uint32_t MAPR2;
399 } AFIO_TypeDef;
400 /**
401 * @brief Inter Integrated Circuit Interface
402 */
403
404 typedef struct
405 {
406 __IO uint32_t CR1;
407 __IO uint32_t CR2;
408 __IO uint32_t OAR1;
409 __IO uint32_t OAR2;
410 __IO uint32_t DR;
411 __IO uint32_t SR1;
412 __IO uint32_t SR2;
413 __IO uint32_t CCR;
414 __IO uint32_t TRISE;
415 } I2C_TypeDef;
416
417 /**
418 * @brief Independent WATCHDOG
419 */
420
421 typedef struct
422 {
423 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
424 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
425 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
426 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
427 } IWDG_TypeDef;
428
429 /**
430 * @brief Power Control
431 */
432
433 typedef struct
434 {
435 __IO uint32_t CR;
436 __IO uint32_t CSR;
437 } PWR_TypeDef;
438
439 /**
440 * @brief Reset and Clock Control
441 */
442
443 typedef struct
444 {
445 __IO uint32_t CR;
446 __IO uint32_t CFGR;
447 __IO uint32_t CIR;
448 __IO uint32_t APB2RSTR;
449 __IO uint32_t APB1RSTR;
450 __IO uint32_t AHBENR;
451 __IO uint32_t APB2ENR;
452 __IO uint32_t APB1ENR;
453 __IO uint32_t BDCR;
454 __IO uint32_t CSR;
455
456
457 } RCC_TypeDef;
458
459 /**
460 * @brief Real-Time Clock
461 */
462
463 typedef struct
464 {
465 __IO uint32_t CRH;
466 __IO uint32_t CRL;
467 __IO uint32_t PRLH;
468 __IO uint32_t PRLL;
469 __IO uint32_t DIVH;
470 __IO uint32_t DIVL;
471 __IO uint32_t CNTH;
472 __IO uint32_t CNTL;
473 __IO uint32_t ALRH;
474 __IO uint32_t ALRL;
475 } RTC_TypeDef;
476
477 /**
478 * @brief SD host Interface
479 */
480
481 typedef struct
482 {
483 __IO uint32_t POWER;
484 __IO uint32_t CLKCR;
485 __IO uint32_t ARG;
486 __IO uint32_t CMD;
487 __I uint32_t RESPCMD;
488 __I uint32_t RESP1;
489 __I uint32_t RESP2;
490 __I uint32_t RESP3;
491 __I uint32_t RESP4;
492 __IO uint32_t DTIMER;
493 __IO uint32_t DLEN;
494 __IO uint32_t DCTRL;
495 __I uint32_t DCOUNT;
496 __I uint32_t STA;
497 __IO uint32_t ICR;
498 __IO uint32_t MASK;
499 uint32_t RESERVED0[2];
500 __I uint32_t FIFOCNT;
501 uint32_t RESERVED1[13];
502 __IO uint32_t FIFO;
503 } SDIO_TypeDef;
504
505 /**
506 * @brief Serial Peripheral Interface
507 */
508
509 typedef struct
510 {
511 __IO uint32_t CR1;
512 __IO uint32_t CR2;
513 __IO uint32_t SR;
514 __IO uint32_t DR;
515 __IO uint32_t CRCPR;
516 __IO uint32_t RXCRCR;
517 __IO uint32_t TXCRCR;
518 __IO uint32_t I2SCFGR;
519 } SPI_TypeDef;
520
521 /**
522 * @brief TIM Timers
523 */
524 typedef struct
525 {
526 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
527 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
528 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
529 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
530 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
531 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
532 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
533 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
534 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
535 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
536 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
537 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
538 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
539 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
540 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
541 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
542 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
543 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
544 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
545 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
546 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
547 }TIM_TypeDef;
548
549
550 /**
551 * @brief Universal Synchronous Asynchronous Receiver Transmitter
552 */
553
554 typedef struct
555 {
556 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
557 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
558 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
559 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
560 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
561 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
562 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
563 } USART_TypeDef;
564
565 /**
566 * @brief Universal Serial Bus Full Speed Device
567 */
568
569 typedef struct
570 {
571 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
572 __IO uint16_t RESERVED0; /*!< Reserved */
573 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
574 __IO uint16_t RESERVED1; /*!< Reserved */
575 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
576 __IO uint16_t RESERVED2; /*!< Reserved */
577 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
578 __IO uint16_t RESERVED3; /*!< Reserved */
579 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
580 __IO uint16_t RESERVED4; /*!< Reserved */
581 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
582 __IO uint16_t RESERVED5; /*!< Reserved */
583 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
584 __IO uint16_t RESERVED6; /*!< Reserved */
585 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
586 __IO uint16_t RESERVED7[17]; /*!< Reserved */
587 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
588 __IO uint16_t RESERVED8; /*!< Reserved */
589 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
590 __IO uint16_t RESERVED9; /*!< Reserved */
591 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
592 __IO uint16_t RESERVEDA; /*!< Reserved */
593 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
594 __IO uint16_t RESERVEDB; /*!< Reserved */
595 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
596 __IO uint16_t RESERVEDC; /*!< Reserved */
597 } USB_TypeDef;
598
599
600 /**
601 * @brief Window WATCHDOG
602 */
603
604 typedef struct
605 {
606 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
607 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
608 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
609 } WWDG_TypeDef;
610
611 /**
612 * @}
613 */
614
615 /** @addtogroup Peripheral_memory_map
616 * @{
617 */
618
619
620 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
621 #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
622 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
623 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
624
625 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
626 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
627
628
629 /*!< Peripheral memory map */
630 #define APB1PERIPH_BASE PERIPH_BASE
631 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
632 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
633
634 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
635 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
636 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
637 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
638 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
639 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
640 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
641 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
642 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
643 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
644 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
645 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
646 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
647 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
648 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
649 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
650 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
651 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
652 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
653 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
654 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
655 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
656 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
657 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
658 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
659 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
660
661 #define SDIO_BASE (PERIPH_BASE + 0x18000)
662
663 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
664 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
665 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
666 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
667 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
668 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
669 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
670 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
671 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
672 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
673
674 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
675 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
676 #define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
677 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
678
679
680
681 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
682
683 /* USB device FS */
684 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
685 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
686
687
688 /**
689 * @}
690 */
691
692 /** @addtogroup Peripheral_declaration
693 * @{
694 */
695
696 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
697 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
698 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
699 #define RTC ((RTC_TypeDef *) RTC_BASE)
700 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
701 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
702 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
703 #define USART2 ((USART_TypeDef *) USART2_BASE)
704 #define USART3 ((USART_TypeDef *) USART3_BASE)
705 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
706 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
707 #define USB ((USB_TypeDef *) USB_BASE)
708 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
709 #define BKP ((BKP_TypeDef *) BKP_BASE)
710 #define PWR ((PWR_TypeDef *) PWR_BASE)
711 #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
712 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
713 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
714 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
715 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
716 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
717 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
718 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
719 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
720 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
721 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
722 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
723 #define USART1 ((USART_TypeDef *) USART1_BASE)
724 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
725 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
726 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
727 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
728 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
729 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
730 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
731 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
732 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
733 #define RCC ((RCC_TypeDef *) RCC_BASE)
734 #define CRC ((CRC_TypeDef *) CRC_BASE)
735 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
736 #define OB ((OB_TypeDef *) OB_BASE)
737 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
738
739
740 /**
741 * @}
742 */
743
744 /** @addtogroup Exported_constants
745 * @{
746 */
747
748 /** @addtogroup Peripheral_Registers_Bits_Definition
749 * @{
750 */
751
752 /******************************************************************************/
753 /* Peripheral Registers_Bits_Definition */
754 /******************************************************************************/
755
756 /******************************************************************************/
757 /* */
758 /* CRC calculation unit (CRC) */
759 /* */
760 /******************************************************************************/
761
762 /******************* Bit definition for CRC_DR register *********************/
763 #define CRC_DR_DR_Pos (0U)
764 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
765 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
766
767 /******************* Bit definition for CRC_IDR register ********************/
768 #define CRC_IDR_IDR_Pos (0U)
769 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
770 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
771
772 /******************** Bit definition for CRC_CR register ********************/
773 #define CRC_CR_RESET_Pos (0U)
774 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
775 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
776
777 /******************************************************************************/
778 /* */
779 /* Power Control */
780 /* */
781 /******************************************************************************/
782
783 /******************** Bit definition for PWR_CR register ********************/
784 #define PWR_CR_LPDS_Pos (0U)
785 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
786 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
787 #define PWR_CR_PDDS_Pos (1U)
788 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
789 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
790 #define PWR_CR_CWUF_Pos (2U)
791 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
792 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
793 #define PWR_CR_CSBF_Pos (3U)
794 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
795 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
796 #define PWR_CR_PVDE_Pos (4U)
797 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
798 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
799
800 #define PWR_CR_PLS_Pos (5U)
801 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
802 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
803 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
804 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
805 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
806
807 /*!< PVD level configuration */
808 #define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
809 #define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
810 #define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
811 #define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
812 #define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
813 #define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
814 #define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
815 #define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
816
817 #define PWR_CR_DBP_Pos (8U)
818 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
819 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
820
821
822 /******************* Bit definition for PWR_CSR register ********************/
823 #define PWR_CSR_WUF_Pos (0U)
824 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
825 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
826 #define PWR_CSR_SBF_Pos (1U)
827 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
828 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
829 #define PWR_CSR_PVDO_Pos (2U)
830 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
831 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
832 #define PWR_CSR_EWUP_Pos (8U)
833 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
834 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
835
836 /******************************************************************************/
837 /* */
838 /* Backup registers */
839 /* */
840 /******************************************************************************/
841
842 /******************* Bit definition for BKP_DR1 register ********************/
843 #define BKP_DR1_D_Pos (0U)
844 #define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
845 #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
846
847 /******************* Bit definition for BKP_DR2 register ********************/
848 #define BKP_DR2_D_Pos (0U)
849 #define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
850 #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
851
852 /******************* Bit definition for BKP_DR3 register ********************/
853 #define BKP_DR3_D_Pos (0U)
854 #define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
855 #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
856
857 /******************* Bit definition for BKP_DR4 register ********************/
858 #define BKP_DR4_D_Pos (0U)
859 #define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
860 #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
861
862 /******************* Bit definition for BKP_DR5 register ********************/
863 #define BKP_DR5_D_Pos (0U)
864 #define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
865 #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
866
867 /******************* Bit definition for BKP_DR6 register ********************/
868 #define BKP_DR6_D_Pos (0U)
869 #define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
870 #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
871
872 /******************* Bit definition for BKP_DR7 register ********************/
873 #define BKP_DR7_D_Pos (0U)
874 #define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
875 #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
876
877 /******************* Bit definition for BKP_DR8 register ********************/
878 #define BKP_DR8_D_Pos (0U)
879 #define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
880 #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
881
882 /******************* Bit definition for BKP_DR9 register ********************/
883 #define BKP_DR9_D_Pos (0U)
884 #define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
885 #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
886
887 /******************* Bit definition for BKP_DR10 register *******************/
888 #define BKP_DR10_D_Pos (0U)
889 #define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
890 #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
891
892 #define RTC_BKP_NUMBER 10
893
894 /****************** Bit definition for BKP_RTCCR register *******************/
895 #define BKP_RTCCR_CAL_Pos (0U)
896 #define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
897 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
898 #define BKP_RTCCR_CCO_Pos (7U)
899 #define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
900 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
901 #define BKP_RTCCR_ASOE_Pos (8U)
902 #define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
903 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
904 #define BKP_RTCCR_ASOS_Pos (9U)
905 #define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
906 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
907
908 /******************** Bit definition for BKP_CR register ********************/
909 #define BKP_CR_TPE_Pos (0U)
910 #define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
911 #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
912 #define BKP_CR_TPAL_Pos (1U)
913 #define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
914 #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
915
916 /******************* Bit definition for BKP_CSR register ********************/
917 #define BKP_CSR_CTE_Pos (0U)
918 #define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
919 #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
920 #define BKP_CSR_CTI_Pos (1U)
921 #define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
922 #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
923 #define BKP_CSR_TPIE_Pos (2U)
924 #define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
925 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
926 #define BKP_CSR_TEF_Pos (8U)
927 #define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
928 #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
929 #define BKP_CSR_TIF_Pos (9U)
930 #define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
931 #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
932
933 /******************************************************************************/
934 /* */
935 /* Reset and Clock Control */
936 /* */
937 /******************************************************************************/
938
939 /******************** Bit definition for RCC_CR register ********************/
940 #define RCC_CR_HSION_Pos (0U)
941 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
942 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
943 #define RCC_CR_HSIRDY_Pos (1U)
944 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
945 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
946 #define RCC_CR_HSITRIM_Pos (3U)
947 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
948 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
949 #define RCC_CR_HSICAL_Pos (8U)
950 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
951 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
952 #define RCC_CR_HSEON_Pos (16U)
953 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
954 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
955 #define RCC_CR_HSERDY_Pos (17U)
956 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
957 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
958 #define RCC_CR_HSEBYP_Pos (18U)
959 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
960 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
961 #define RCC_CR_CSSON_Pos (19U)
962 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
963 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
964 #define RCC_CR_PLLON_Pos (24U)
965 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
966 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
967 #define RCC_CR_PLLRDY_Pos (25U)
968 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
969 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
970
971
972 /******************* Bit definition for RCC_CFGR register *******************/
973 /*!< SW configuration */
974 #define RCC_CFGR_SW_Pos (0U)
975 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
976 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
977 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
978 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
979
980 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
981 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
982 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
983
984 /*!< SWS configuration */
985 #define RCC_CFGR_SWS_Pos (2U)
986 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
987 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
988 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
989 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
990
991 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
992 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
993 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
994
995 /*!< HPRE configuration */
996 #define RCC_CFGR_HPRE_Pos (4U)
997 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
998 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
999 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
1000 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
1001 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
1002 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
1003
1004 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
1005 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
1006 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
1007 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
1008 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
1009 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
1010 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
1011 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
1012 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
1013
1014 /*!< PPRE1 configuration */
1015 #define RCC_CFGR_PPRE1_Pos (8U)
1016 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
1017 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
1018 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
1019 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
1020 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
1021
1022 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
1023 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
1024 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
1025 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
1026 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
1027
1028 /*!< PPRE2 configuration */
1029 #define RCC_CFGR_PPRE2_Pos (11U)
1030 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
1031 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
1032 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
1033 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
1034 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
1035
1036 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
1037 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
1038 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
1039 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
1040 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
1041
1042 /*!< ADCPPRE configuration */
1043 #define RCC_CFGR_ADCPRE_Pos (14U)
1044 #define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
1045 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
1046 #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
1047 #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
1048
1049 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
1050 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
1051 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
1052 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
1053
1054 #define RCC_CFGR_PLLSRC_Pos (16U)
1055 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
1056 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
1057
1058 #define RCC_CFGR_PLLXTPRE_Pos (17U)
1059 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
1060 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
1061
1062 /*!< PLLMUL configuration */
1063 #define RCC_CFGR_PLLMULL_Pos (18U)
1064 #define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
1065 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
1066 #define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
1067 #define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
1068 #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
1069 #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
1070
1071 #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
1072 #define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
1073
1074 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
1075 #define RCC_CFGR_PLLMULL3_Pos (18U)
1076 #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
1077 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
1078 #define RCC_CFGR_PLLMULL4_Pos (19U)
1079 #define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
1080 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
1081 #define RCC_CFGR_PLLMULL5_Pos (18U)
1082 #define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
1083 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
1084 #define RCC_CFGR_PLLMULL6_Pos (20U)
1085 #define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
1086 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
1087 #define RCC_CFGR_PLLMULL7_Pos (18U)
1088 #define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
1089 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
1090 #define RCC_CFGR_PLLMULL8_Pos (19U)
1091 #define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
1092 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
1093 #define RCC_CFGR_PLLMULL9_Pos (18U)
1094 #define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
1095 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
1096 #define RCC_CFGR_PLLMULL10_Pos (21U)
1097 #define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
1098 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
1099 #define RCC_CFGR_PLLMULL11_Pos (18U)
1100 #define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
1101 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
1102 #define RCC_CFGR_PLLMULL12_Pos (19U)
1103 #define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
1104 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
1105 #define RCC_CFGR_PLLMULL13_Pos (18U)
1106 #define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
1107 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
1108 #define RCC_CFGR_PLLMULL14_Pos (20U)
1109 #define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
1110 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
1111 #define RCC_CFGR_PLLMULL15_Pos (18U)
1112 #define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
1113 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
1114 #define RCC_CFGR_PLLMULL16_Pos (19U)
1115 #define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
1116 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
1117 #define RCC_CFGR_USBPRE_Pos (22U)
1118 #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
1119 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
1120
1121 /*!< MCO configuration */
1122 #define RCC_CFGR_MCO_Pos (24U)
1123 #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
1124 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
1125 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
1126 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
1127 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
1128
1129 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
1130 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
1131 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
1132 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
1133 #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
1134
1135 /* Reference defines */
1136 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
1137 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
1138 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
1139 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
1140 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
1141 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
1142 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
1143 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
1144 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
1145
1146 /*!<****************** Bit definition for RCC_CIR register ********************/
1147 #define RCC_CIR_LSIRDYF_Pos (0U)
1148 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
1149 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
1150 #define RCC_CIR_LSERDYF_Pos (1U)
1151 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
1152 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
1153 #define RCC_CIR_HSIRDYF_Pos (2U)
1154 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
1155 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
1156 #define RCC_CIR_HSERDYF_Pos (3U)
1157 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
1158 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
1159 #define RCC_CIR_PLLRDYF_Pos (4U)
1160 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
1161 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
1162 #define RCC_CIR_CSSF_Pos (7U)
1163 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
1164 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
1165 #define RCC_CIR_LSIRDYIE_Pos (8U)
1166 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
1167 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
1168 #define RCC_CIR_LSERDYIE_Pos (9U)
1169 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
1170 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
1171 #define RCC_CIR_HSIRDYIE_Pos (10U)
1172 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
1173 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
1174 #define RCC_CIR_HSERDYIE_Pos (11U)
1175 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
1176 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
1177 #define RCC_CIR_PLLRDYIE_Pos (12U)
1178 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
1179 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
1180 #define RCC_CIR_LSIRDYC_Pos (16U)
1181 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
1182 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
1183 #define RCC_CIR_LSERDYC_Pos (17U)
1184 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
1185 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
1186 #define RCC_CIR_HSIRDYC_Pos (18U)
1187 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
1188 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
1189 #define RCC_CIR_HSERDYC_Pos (19U)
1190 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
1191 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
1192 #define RCC_CIR_PLLRDYC_Pos (20U)
1193 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
1194 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
1195 #define RCC_CIR_CSSC_Pos (23U)
1196 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
1197 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
1198
1199
1200 /***************** Bit definition for RCC_APB2RSTR register *****************/
1201 #define RCC_APB2RSTR_AFIORST_Pos (0U)
1202 #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
1203 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
1204 #define RCC_APB2RSTR_IOPARST_Pos (2U)
1205 #define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
1206 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
1207 #define RCC_APB2RSTR_IOPBRST_Pos (3U)
1208 #define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
1209 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
1210 #define RCC_APB2RSTR_IOPCRST_Pos (4U)
1211 #define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
1212 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
1213 #define RCC_APB2RSTR_IOPDRST_Pos (5U)
1214 #define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
1215 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
1216 #define RCC_APB2RSTR_ADC1RST_Pos (9U)
1217 #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
1218 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
1219
1220 #define RCC_APB2RSTR_ADC2RST_Pos (10U)
1221 #define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
1222 #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
1223
1224 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
1225 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
1226 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
1227 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
1228 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
1229 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
1230 #define RCC_APB2RSTR_USART1RST_Pos (14U)
1231 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
1232 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
1233
1234
1235 #define RCC_APB2RSTR_IOPERST_Pos (6U)
1236 #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
1237 #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
1238
1239
1240
1241
1242 /***************** Bit definition for RCC_APB1RSTR register *****************/
1243 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
1244 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
1245 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
1246 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
1247 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
1248 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
1249 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
1250 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
1251 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
1252 #define RCC_APB1RSTR_USART2RST_Pos (17U)
1253 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
1254 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
1255 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
1256 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
1257 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
1258
1259 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
1260 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
1261 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
1262
1263 #define RCC_APB1RSTR_BKPRST_Pos (27U)
1264 #define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
1265 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
1266 #define RCC_APB1RSTR_PWRRST_Pos (28U)
1267 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
1268 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
1269
1270 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
1271 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
1272 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
1273 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
1274 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
1275 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
1276 #define RCC_APB1RSTR_USART3RST_Pos (18U)
1277 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
1278 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
1279 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
1280 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
1281 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
1282
1283 #define RCC_APB1RSTR_USBRST_Pos (23U)
1284 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
1285 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
1286
1287
1288
1289
1290
1291
1292 /****************** Bit definition for RCC_AHBENR register ******************/
1293 #define RCC_AHBENR_DMA1EN_Pos (0U)
1294 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
1295 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
1296 #define RCC_AHBENR_SRAMEN_Pos (2U)
1297 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
1298 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
1299 #define RCC_AHBENR_FLITFEN_Pos (4U)
1300 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
1301 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
1302 #define RCC_AHBENR_CRCEN_Pos (6U)
1303 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
1304 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
1305
1306
1307
1308
1309 /****************** Bit definition for RCC_APB2ENR register *****************/
1310 #define RCC_APB2ENR_AFIOEN_Pos (0U)
1311 #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
1312 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
1313 #define RCC_APB2ENR_IOPAEN_Pos (2U)
1314 #define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
1315 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
1316 #define RCC_APB2ENR_IOPBEN_Pos (3U)
1317 #define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
1318 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
1319 #define RCC_APB2ENR_IOPCEN_Pos (4U)
1320 #define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
1321 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
1322 #define RCC_APB2ENR_IOPDEN_Pos (5U)
1323 #define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
1324 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
1325 #define RCC_APB2ENR_ADC1EN_Pos (9U)
1326 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
1327 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
1328
1329 #define RCC_APB2ENR_ADC2EN_Pos (10U)
1330 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
1331 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
1332
1333 #define RCC_APB2ENR_TIM1EN_Pos (11U)
1334 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
1335 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
1336 #define RCC_APB2ENR_SPI1EN_Pos (12U)
1337 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
1338 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
1339 #define RCC_APB2ENR_USART1EN_Pos (14U)
1340 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
1341 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
1342
1343
1344 #define RCC_APB2ENR_IOPEEN_Pos (6U)
1345 #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
1346 #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
1347
1348
1349
1350
1351 /***************** Bit definition for RCC_APB1ENR register ******************/
1352 #define RCC_APB1ENR_TIM2EN_Pos (0U)
1353 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
1354 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
1355 #define RCC_APB1ENR_TIM3EN_Pos (1U)
1356 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
1357 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
1358 #define RCC_APB1ENR_WWDGEN_Pos (11U)
1359 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
1360 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
1361 #define RCC_APB1ENR_USART2EN_Pos (17U)
1362 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
1363 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
1364 #define RCC_APB1ENR_I2C1EN_Pos (21U)
1365 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
1366 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
1367
1368 #define RCC_APB1ENR_CAN1EN_Pos (25U)
1369 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
1370 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
1371
1372 #define RCC_APB1ENR_BKPEN_Pos (27U)
1373 #define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
1374 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
1375 #define RCC_APB1ENR_PWREN_Pos (28U)
1376 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
1377 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
1378
1379 #define RCC_APB1ENR_TIM4EN_Pos (2U)
1380 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
1381 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
1382 #define RCC_APB1ENR_SPI2EN_Pos (14U)
1383 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
1384 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
1385 #define RCC_APB1ENR_USART3EN_Pos (18U)
1386 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
1387 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
1388 #define RCC_APB1ENR_I2C2EN_Pos (22U)
1389 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
1390 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
1391
1392 #define RCC_APB1ENR_USBEN_Pos (23U)
1393 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
1394 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
1395
1396
1397
1398
1399
1400
1401 /******************* Bit definition for RCC_BDCR register *******************/
1402 #define RCC_BDCR_LSEON_Pos (0U)
1403 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
1404 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
1405 #define RCC_BDCR_LSERDY_Pos (1U)
1406 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
1407 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
1408 #define RCC_BDCR_LSEBYP_Pos (2U)
1409 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
1410 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
1411
1412 #define RCC_BDCR_RTCSEL_Pos (8U)
1413 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
1414 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
1415 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
1416 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
1417
1418 /*!< RTC congiguration */
1419 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
1420 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
1421 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
1422 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
1423
1424 #define RCC_BDCR_RTCEN_Pos (15U)
1425 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
1426 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
1427 #define RCC_BDCR_BDRST_Pos (16U)
1428 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
1429 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
1430
1431 /******************* Bit definition for RCC_CSR register ********************/
1432 #define RCC_CSR_LSION_Pos (0U)
1433 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
1434 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
1435 #define RCC_CSR_LSIRDY_Pos (1U)
1436 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
1437 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
1438 #define RCC_CSR_RMVF_Pos (24U)
1439 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
1440 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
1441 #define RCC_CSR_PINRSTF_Pos (26U)
1442 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
1443 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
1444 #define RCC_CSR_PORRSTF_Pos (27U)
1445 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
1446 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
1447 #define RCC_CSR_SFTRSTF_Pos (28U)
1448 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
1449 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
1450 #define RCC_CSR_IWDGRSTF_Pos (29U)
1451 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
1452 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
1453 #define RCC_CSR_WWDGRSTF_Pos (30U)
1454 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
1455 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
1456 #define RCC_CSR_LPWRRSTF_Pos (31U)
1457 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
1458 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
1459
1460
1461
1462 /******************************************************************************/
1463 /* */
1464 /* General Purpose and Alternate Function I/O */
1465 /* */
1466 /******************************************************************************/
1467
1468 /******************* Bit definition for GPIO_CRL register *******************/
1469 #define GPIO_CRL_MODE_Pos (0U)
1470 #define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
1471 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
1472
1473 #define GPIO_CRL_MODE0_Pos (0U)
1474 #define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
1475 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
1476 #define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
1477 #define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
1478
1479 #define GPIO_CRL_MODE1_Pos (4U)
1480 #define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
1481 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
1482 #define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
1483 #define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
1484
1485 #define GPIO_CRL_MODE2_Pos (8U)
1486 #define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
1487 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
1488 #define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
1489 #define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
1490
1491 #define GPIO_CRL_MODE3_Pos (12U)
1492 #define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
1493 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
1494 #define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
1495 #define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
1496
1497 #define GPIO_CRL_MODE4_Pos (16U)
1498 #define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
1499 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
1500 #define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
1501 #define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
1502
1503 #define GPIO_CRL_MODE5_Pos (20U)
1504 #define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
1505 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
1506 #define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
1507 #define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
1508
1509 #define GPIO_CRL_MODE6_Pos (24U)
1510 #define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
1511 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
1512 #define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
1513 #define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
1514
1515 #define GPIO_CRL_MODE7_Pos (28U)
1516 #define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
1517 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
1518 #define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
1519 #define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
1520
1521 #define GPIO_CRL_CNF_Pos (2U)
1522 #define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
1523 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
1524
1525 #define GPIO_CRL_CNF0_Pos (2U)
1526 #define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
1527 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
1528 #define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
1529 #define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
1530
1531 #define GPIO_CRL_CNF1_Pos (6U)
1532 #define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
1533 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
1534 #define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
1535 #define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
1536
1537 #define GPIO_CRL_CNF2_Pos (10U)
1538 #define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
1539 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
1540 #define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
1541 #define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
1542
1543 #define GPIO_CRL_CNF3_Pos (14U)
1544 #define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
1545 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
1546 #define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
1547 #define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
1548
1549 #define GPIO_CRL_CNF4_Pos (18U)
1550 #define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
1551 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
1552 #define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
1553 #define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
1554
1555 #define GPIO_CRL_CNF5_Pos (22U)
1556 #define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
1557 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
1558 #define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
1559 #define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
1560
1561 #define GPIO_CRL_CNF6_Pos (26U)
1562 #define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
1563 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
1564 #define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
1565 #define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
1566
1567 #define GPIO_CRL_CNF7_Pos (30U)
1568 #define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
1569 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
1570 #define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
1571 #define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
1572
1573 /******************* Bit definition for GPIO_CRH register *******************/
1574 #define GPIO_CRH_MODE_Pos (0U)
1575 #define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
1576 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
1577
1578 #define GPIO_CRH_MODE8_Pos (0U)
1579 #define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
1580 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
1581 #define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
1582 #define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
1583
1584 #define GPIO_CRH_MODE9_Pos (4U)
1585 #define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
1586 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
1587 #define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
1588 #define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
1589
1590 #define GPIO_CRH_MODE10_Pos (8U)
1591 #define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
1592 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
1593 #define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
1594 #define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
1595
1596 #define GPIO_CRH_MODE11_Pos (12U)
1597 #define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
1598 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
1599 #define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
1600 #define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
1601
1602 #define GPIO_CRH_MODE12_Pos (16U)
1603 #define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
1604 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
1605 #define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
1606 #define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
1607
1608 #define GPIO_CRH_MODE13_Pos (20U)
1609 #define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
1610 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
1611 #define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
1612 #define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
1613
1614 #define GPIO_CRH_MODE14_Pos (24U)
1615 #define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
1616 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
1617 #define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
1618 #define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
1619
1620 #define GPIO_CRH_MODE15_Pos (28U)
1621 #define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
1622 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
1623 #define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
1624 #define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
1625
1626 #define GPIO_CRH_CNF_Pos (2U)
1627 #define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
1628 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
1629
1630 #define GPIO_CRH_CNF8_Pos (2U)
1631 #define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
1632 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
1633 #define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
1634 #define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
1635
1636 #define GPIO_CRH_CNF9_Pos (6U)
1637 #define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
1638 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
1639 #define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
1640 #define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
1641
1642 #define GPIO_CRH_CNF10_Pos (10U)
1643 #define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
1644 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
1645 #define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
1646 #define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
1647
1648 #define GPIO_CRH_CNF11_Pos (14U)
1649 #define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
1650 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
1651 #define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
1652 #define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
1653
1654 #define GPIO_CRH_CNF12_Pos (18U)
1655 #define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
1656 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
1657 #define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
1658 #define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
1659
1660 #define GPIO_CRH_CNF13_Pos (22U)
1661 #define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
1662 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
1663 #define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
1664 #define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
1665
1666 #define GPIO_CRH_CNF14_Pos (26U)
1667 #define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
1668 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
1669 #define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
1670 #define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
1671
1672 #define GPIO_CRH_CNF15_Pos (30U)
1673 #define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
1674 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
1675 #define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
1676 #define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
1677
1678 /*!<****************** Bit definition for GPIO_IDR register *******************/
1679 #define GPIO_IDR_IDR0_Pos (0U)
1680 #define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
1681 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
1682 #define GPIO_IDR_IDR1_Pos (1U)
1683 #define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
1684 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
1685 #define GPIO_IDR_IDR2_Pos (2U)
1686 #define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
1687 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
1688 #define GPIO_IDR_IDR3_Pos (3U)
1689 #define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
1690 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
1691 #define GPIO_IDR_IDR4_Pos (4U)
1692 #define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
1693 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
1694 #define GPIO_IDR_IDR5_Pos (5U)
1695 #define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
1696 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
1697 #define GPIO_IDR_IDR6_Pos (6U)
1698 #define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
1699 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
1700 #define GPIO_IDR_IDR7_Pos (7U)
1701 #define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
1702 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
1703 #define GPIO_IDR_IDR8_Pos (8U)
1704 #define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
1705 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
1706 #define GPIO_IDR_IDR9_Pos (9U)
1707 #define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
1708 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
1709 #define GPIO_IDR_IDR10_Pos (10U)
1710 #define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
1711 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
1712 #define GPIO_IDR_IDR11_Pos (11U)
1713 #define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
1714 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
1715 #define GPIO_IDR_IDR12_Pos (12U)
1716 #define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
1717 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
1718 #define GPIO_IDR_IDR13_Pos (13U)
1719 #define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
1720 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
1721 #define GPIO_IDR_IDR14_Pos (14U)
1722 #define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
1723 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
1724 #define GPIO_IDR_IDR15_Pos (15U)
1725 #define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
1726 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
1727
1728 /******************* Bit definition for GPIO_ODR register *******************/
1729 #define GPIO_ODR_ODR0_Pos (0U)
1730 #define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
1731 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
1732 #define GPIO_ODR_ODR1_Pos (1U)
1733 #define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
1734 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
1735 #define GPIO_ODR_ODR2_Pos (2U)
1736 #define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
1737 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
1738 #define GPIO_ODR_ODR3_Pos (3U)
1739 #define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
1740 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
1741 #define GPIO_ODR_ODR4_Pos (4U)
1742 #define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
1743 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
1744 #define GPIO_ODR_ODR5_Pos (5U)
1745 #define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
1746 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
1747 #define GPIO_ODR_ODR6_Pos (6U)
1748 #define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
1749 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
1750 #define GPIO_ODR_ODR7_Pos (7U)
1751 #define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
1752 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
1753 #define GPIO_ODR_ODR8_Pos (8U)
1754 #define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
1755 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
1756 #define GPIO_ODR_ODR9_Pos (9U)
1757 #define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
1758 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
1759 #define GPIO_ODR_ODR10_Pos (10U)
1760 #define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
1761 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
1762 #define GPIO_ODR_ODR11_Pos (11U)
1763 #define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
1764 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
1765 #define GPIO_ODR_ODR12_Pos (12U)
1766 #define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
1767 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
1768 #define GPIO_ODR_ODR13_Pos (13U)
1769 #define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
1770 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
1771 #define GPIO_ODR_ODR14_Pos (14U)
1772 #define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
1773 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
1774 #define GPIO_ODR_ODR15_Pos (15U)
1775 #define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
1776 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
1777
1778 /****************** Bit definition for GPIO_BSRR register *******************/
1779 #define GPIO_BSRR_BS0_Pos (0U)
1780 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
1781 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
1782 #define GPIO_BSRR_BS1_Pos (1U)
1783 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
1784 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
1785 #define GPIO_BSRR_BS2_Pos (2U)
1786 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
1787 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
1788 #define GPIO_BSRR_BS3_Pos (3U)
1789 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
1790 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
1791 #define GPIO_BSRR_BS4_Pos (4U)
1792 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
1793 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
1794 #define GPIO_BSRR_BS5_Pos (5U)
1795 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
1796 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
1797 #define GPIO_BSRR_BS6_Pos (6U)
1798 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
1799 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
1800 #define GPIO_BSRR_BS7_Pos (7U)
1801 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
1802 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
1803 #define GPIO_BSRR_BS8_Pos (8U)
1804 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
1805 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
1806 #define GPIO_BSRR_BS9_Pos (9U)
1807 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
1808 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
1809 #define GPIO_BSRR_BS10_Pos (10U)
1810 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
1811 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
1812 #define GPIO_BSRR_BS11_Pos (11U)
1813 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
1814 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
1815 #define GPIO_BSRR_BS12_Pos (12U)
1816 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
1817 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
1818 #define GPIO_BSRR_BS13_Pos (13U)
1819 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
1820 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
1821 #define GPIO_BSRR_BS14_Pos (14U)
1822 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
1823 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
1824 #define GPIO_BSRR_BS15_Pos (15U)
1825 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
1826 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
1827
1828 #define GPIO_BSRR_BR0_Pos (16U)
1829 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
1830 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
1831 #define GPIO_BSRR_BR1_Pos (17U)
1832 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
1833 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
1834 #define GPIO_BSRR_BR2_Pos (18U)
1835 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
1836 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
1837 #define GPIO_BSRR_BR3_Pos (19U)
1838 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
1839 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
1840 #define GPIO_BSRR_BR4_Pos (20U)
1841 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
1842 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
1843 #define GPIO_BSRR_BR5_Pos (21U)
1844 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
1845 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
1846 #define GPIO_BSRR_BR6_Pos (22U)
1847 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
1848 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
1849 #define GPIO_BSRR_BR7_Pos (23U)
1850 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
1851 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
1852 #define GPIO_BSRR_BR8_Pos (24U)
1853 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
1854 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
1855 #define GPIO_BSRR_BR9_Pos (25U)
1856 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
1857 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
1858 #define GPIO_BSRR_BR10_Pos (26U)
1859 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
1860 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
1861 #define GPIO_BSRR_BR11_Pos (27U)
1862 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
1863 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
1864 #define GPIO_BSRR_BR12_Pos (28U)
1865 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
1866 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
1867 #define GPIO_BSRR_BR13_Pos (29U)
1868 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
1869 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
1870 #define GPIO_BSRR_BR14_Pos (30U)
1871 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
1872 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
1873 #define GPIO_BSRR_BR15_Pos (31U)
1874 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
1875 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
1876
1877 /******************* Bit definition for GPIO_BRR register *******************/
1878 #define GPIO_BRR_BR0_Pos (0U)
1879 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
1880 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
1881 #define GPIO_BRR_BR1_Pos (1U)
1882 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
1883 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
1884 #define GPIO_BRR_BR2_Pos (2U)
1885 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
1886 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
1887 #define GPIO_BRR_BR3_Pos (3U)
1888 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
1889 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
1890 #define GPIO_BRR_BR4_Pos (4U)
1891 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
1892 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
1893 #define GPIO_BRR_BR5_Pos (5U)
1894 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
1895 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
1896 #define GPIO_BRR_BR6_Pos (6U)
1897 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
1898 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
1899 #define GPIO_BRR_BR7_Pos (7U)
1900 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
1901 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
1902 #define GPIO_BRR_BR8_Pos (8U)
1903 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
1904 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
1905 #define GPIO_BRR_BR9_Pos (9U)
1906 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
1907 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
1908 #define GPIO_BRR_BR10_Pos (10U)
1909 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
1910 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
1911 #define GPIO_BRR_BR11_Pos (11U)
1912 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
1913 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
1914 #define GPIO_BRR_BR12_Pos (12U)
1915 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
1916 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
1917 #define GPIO_BRR_BR13_Pos (13U)
1918 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
1919 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
1920 #define GPIO_BRR_BR14_Pos (14U)
1921 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
1922 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
1923 #define GPIO_BRR_BR15_Pos (15U)
1924 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
1925 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
1926
1927 /****************** Bit definition for GPIO_LCKR register *******************/
1928 #define GPIO_LCKR_LCK0_Pos (0U)
1929 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
1930 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
1931 #define GPIO_LCKR_LCK1_Pos (1U)
1932 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
1933 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
1934 #define GPIO_LCKR_LCK2_Pos (2U)
1935 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
1936 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
1937 #define GPIO_LCKR_LCK3_Pos (3U)
1938 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
1939 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
1940 #define GPIO_LCKR_LCK4_Pos (4U)
1941 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
1942 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
1943 #define GPIO_LCKR_LCK5_Pos (5U)
1944 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
1945 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
1946 #define GPIO_LCKR_LCK6_Pos (6U)
1947 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
1948 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
1949 #define GPIO_LCKR_LCK7_Pos (7U)
1950 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
1951 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
1952 #define GPIO_LCKR_LCK8_Pos (8U)
1953 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
1954 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
1955 #define GPIO_LCKR_LCK9_Pos (9U)
1956 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
1957 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
1958 #define GPIO_LCKR_LCK10_Pos (10U)
1959 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
1960 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
1961 #define GPIO_LCKR_LCK11_Pos (11U)
1962 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
1963 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
1964 #define GPIO_LCKR_LCK12_Pos (12U)
1965 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
1966 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
1967 #define GPIO_LCKR_LCK13_Pos (13U)
1968 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
1969 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
1970 #define GPIO_LCKR_LCK14_Pos (14U)
1971 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
1972 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
1973 #define GPIO_LCKR_LCK15_Pos (15U)
1974 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
1975 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
1976 #define GPIO_LCKR_LCKK_Pos (16U)
1977 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
1978 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
1979
1980 /*----------------------------------------------------------------------------*/
1981
1982 /****************** Bit definition for AFIO_EVCR register *******************/
1983 #define AFIO_EVCR_PIN_Pos (0U)
1984 #define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
1985 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
1986 #define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
1987 #define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
1988 #define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
1989 #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
1990
1991 /*!< PIN configuration */
1992 #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
1993 #define AFIO_EVCR_PIN_PX1_Pos (0U)
1994 #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
1995 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
1996 #define AFIO_EVCR_PIN_PX2_Pos (1U)
1997 #define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
1998 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
1999 #define AFIO_EVCR_PIN_PX3_Pos (0U)
2000 #define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
2001 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
2002 #define AFIO_EVCR_PIN_PX4_Pos (2U)
2003 #define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
2004 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
2005 #define AFIO_EVCR_PIN_PX5_Pos (0U)
2006 #define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
2007 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
2008 #define AFIO_EVCR_PIN_PX6_Pos (1U)
2009 #define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
2010 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
2011 #define AFIO_EVCR_PIN_PX7_Pos (0U)
2012 #define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
2013 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
2014 #define AFIO_EVCR_PIN_PX8_Pos (3U)
2015 #define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
2016 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
2017 #define AFIO_EVCR_PIN_PX9_Pos (0U)
2018 #define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
2019 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
2020 #define AFIO_EVCR_PIN_PX10_Pos (1U)
2021 #define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
2022 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
2023 #define AFIO_EVCR_PIN_PX11_Pos (0U)
2024 #define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
2025 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
2026 #define AFIO_EVCR_PIN_PX12_Pos (2U)
2027 #define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
2028 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
2029 #define AFIO_EVCR_PIN_PX13_Pos (0U)
2030 #define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
2031 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
2032 #define AFIO_EVCR_PIN_PX14_Pos (1U)
2033 #define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
2034 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
2035 #define AFIO_EVCR_PIN_PX15_Pos (0U)
2036 #define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
2037 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
2038
2039 #define AFIO_EVCR_PORT_Pos (4U)
2040 #define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
2041 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
2042 #define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
2043 #define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
2044 #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
2045
2046 /*!< PORT configuration */
2047 #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
2048 #define AFIO_EVCR_PORT_PB_Pos (4U)
2049 #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
2050 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
2051 #define AFIO_EVCR_PORT_PC_Pos (5U)
2052 #define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
2053 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
2054 #define AFIO_EVCR_PORT_PD_Pos (4U)
2055 #define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
2056 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
2057 #define AFIO_EVCR_PORT_PE_Pos (6U)
2058 #define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
2059 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
2060
2061 #define AFIO_EVCR_EVOE_Pos (7U)
2062 #define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
2063 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
2064
2065 /****************** Bit definition for AFIO_MAPR register *******************/
2066 #define AFIO_MAPR_SPI1_REMAP_Pos (0U)
2067 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
2068 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
2069 #define AFIO_MAPR_I2C1_REMAP_Pos (1U)
2070 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
2071 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
2072 #define AFIO_MAPR_USART1_REMAP_Pos (2U)
2073 #define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
2074 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
2075 #define AFIO_MAPR_USART2_REMAP_Pos (3U)
2076 #define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
2077 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
2078
2079 #define AFIO_MAPR_USART3_REMAP_Pos (4U)
2080 #define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
2081 #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
2082 #define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
2083 #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
2084
2085 /* USART3_REMAP configuration */
2086 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
2087 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
2088 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
2089 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
2090 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
2091 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
2092 #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
2093
2094 #define AFIO_MAPR_TIM1_REMAP_Pos (6U)
2095 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
2096 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
2097 #define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
2098 #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
2099
2100 /*!< TIM1_REMAP configuration */
2101 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
2102 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
2103 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
2104 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
2105 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
2106 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
2107 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
2108
2109 #define AFIO_MAPR_TIM2_REMAP_Pos (8U)
2110 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
2111 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
2112 #define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
2113 #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
2114
2115 /*!< TIM2_REMAP configuration */
2116 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
2117 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
2118 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
2119 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
2120 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
2121 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
2122 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
2123 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
2124 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
2125 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
2126
2127 #define AFIO_MAPR_TIM3_REMAP_Pos (10U)
2128 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
2129 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
2130 #define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
2131 #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
2132
2133 /*!< TIM3_REMAP configuration */
2134 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
2135 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
2136 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
2137 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
2138 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
2139 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
2140 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
2141
2142 #define AFIO_MAPR_TIM4_REMAP_Pos (12U)
2143 #define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
2144 #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
2145
2146 #define AFIO_MAPR_CAN_REMAP_Pos (13U)
2147 #define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
2148 #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
2149 #define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
2150 #define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
2151
2152 /*!< CAN_REMAP configuration */
2153 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
2154 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
2155 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
2156 #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
2157 #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
2158 #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
2159 #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
2160
2161 #define AFIO_MAPR_PD01_REMAP_Pos (15U)
2162 #define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
2163 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2164
2165 /*!< SWJ_CFG configuration */
2166 #define AFIO_MAPR_SWJ_CFG_Pos (24U)
2167 #define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
2168 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
2169 #define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
2170 #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
2171 #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
2172
2173 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
2174 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
2175 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
2176 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
2177 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
2178 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
2179 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
2180 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
2181 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
2182 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
2183
2184
2185 /***************** Bit definition for AFIO_EXTICR1 register *****************/
2186 #define AFIO_EXTICR1_EXTI0_Pos (0U)
2187 #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
2188 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
2189 #define AFIO_EXTICR1_EXTI1_Pos (4U)
2190 #define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
2191 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
2192 #define AFIO_EXTICR1_EXTI2_Pos (8U)
2193 #define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
2194 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
2195 #define AFIO_EXTICR1_EXTI3_Pos (12U)
2196 #define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
2197 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
2198
2199 /*!< EXTI0 configuration */
2200 #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
2201 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
2202 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
2203 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
2204 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
2205 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
2206 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
2207 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
2208 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
2209 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
2210 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
2211 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
2212 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
2213 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
2214 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
2215 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
2216 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
2217 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
2218 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
2219
2220 /*!< EXTI1 configuration */
2221 #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
2222 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
2223 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
2224 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
2225 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
2226 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
2227 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
2228 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
2229 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
2230 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
2231 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
2232 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
2233 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
2234 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
2235 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
2236 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
2237 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
2238 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
2239 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
2240
2241 /*!< EXTI2 configuration */
2242 #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
2243 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
2244 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
2245 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
2246 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
2247 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
2248 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
2249 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
2250 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
2251 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
2252 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
2253 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
2254 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
2255 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
2256 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
2257 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
2258 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
2259 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
2260 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
2261
2262 /*!< EXTI3 configuration */
2263 #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
2264 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
2265 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
2266 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
2267 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
2268 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
2269 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
2270 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
2271 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
2272 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
2273 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
2274 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
2275 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
2276 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
2277 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
2278 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
2279 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
2280 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
2281 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
2282
2283 /***************** Bit definition for AFIO_EXTICR2 register *****************/
2284 #define AFIO_EXTICR2_EXTI4_Pos (0U)
2285 #define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
2286 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
2287 #define AFIO_EXTICR2_EXTI5_Pos (4U)
2288 #define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
2289 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
2290 #define AFIO_EXTICR2_EXTI6_Pos (8U)
2291 #define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
2292 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
2293 #define AFIO_EXTICR2_EXTI7_Pos (12U)
2294 #define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
2295 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
2296
2297 /*!< EXTI4 configuration */
2298 #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
2299 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
2300 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
2301 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
2302 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
2303 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
2304 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
2305 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
2306 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
2307 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
2308 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
2309 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
2310 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
2311 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
2312 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
2313 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
2314 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
2315 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
2316 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
2317
2318 /* EXTI5 configuration */
2319 #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
2320 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
2321 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
2322 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
2323 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
2324 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
2325 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
2326 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
2327 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
2328 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
2329 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
2330 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
2331 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
2332 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
2333 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
2334 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
2335 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
2336 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
2337 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
2338
2339 /*!< EXTI6 configuration */
2340 #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
2341 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
2342 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
2343 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
2344 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
2345 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
2346 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
2347 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
2348 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
2349 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
2350 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
2351 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
2352 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
2353 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
2354 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
2355 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
2356 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
2357 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
2358 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
2359
2360 /*!< EXTI7 configuration */
2361 #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
2362 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
2363 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
2364 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
2365 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
2366 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
2367 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
2368 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
2369 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
2370 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
2371 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
2372 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
2373 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
2374 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
2375 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
2376 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
2377 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
2378 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
2379 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
2380
2381 /***************** Bit definition for AFIO_EXTICR3 register *****************/
2382 #define AFIO_EXTICR3_EXTI8_Pos (0U)
2383 #define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
2384 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
2385 #define AFIO_EXTICR3_EXTI9_Pos (4U)
2386 #define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
2387 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
2388 #define AFIO_EXTICR3_EXTI10_Pos (8U)
2389 #define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
2390 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
2391 #define AFIO_EXTICR3_EXTI11_Pos (12U)
2392 #define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
2393 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
2394
2395 /*!< EXTI8 configuration */
2396 #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
2397 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
2398 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
2399 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
2400 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
2401 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
2402 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
2403 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
2404 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
2405 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
2406 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
2407 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
2408 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
2409 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
2410 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
2411 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
2412 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
2413 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
2414 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
2415
2416 /*!< EXTI9 configuration */
2417 #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
2418 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
2419 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
2420 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
2421 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
2422 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
2423 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
2424 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
2425 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
2426 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
2427 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
2428 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
2429 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
2430 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
2431 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
2432 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
2433 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
2434 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
2435 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
2436
2437 /*!< EXTI10 configuration */
2438 #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
2439 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
2440 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
2441 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
2442 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
2443 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
2444 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
2445 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
2446 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
2447 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
2448 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
2449 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
2450 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
2451 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
2452 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
2453 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
2454 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
2455 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
2456 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
2457
2458 /*!< EXTI11 configuration */
2459 #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
2460 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
2461 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
2462 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
2463 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
2464 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
2465 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
2466 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
2467 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
2468 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
2469 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
2470 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
2471 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
2472 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
2473 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
2474 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
2475 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
2476 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
2477 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
2478
2479 /***************** Bit definition for AFIO_EXTICR4 register *****************/
2480 #define AFIO_EXTICR4_EXTI12_Pos (0U)
2481 #define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
2482 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
2483 #define AFIO_EXTICR4_EXTI13_Pos (4U)
2484 #define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
2485 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
2486 #define AFIO_EXTICR4_EXTI14_Pos (8U)
2487 #define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
2488 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
2489 #define AFIO_EXTICR4_EXTI15_Pos (12U)
2490 #define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
2491 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
2492
2493 /* EXTI12 configuration */
2494 #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
2495 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
2496 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
2497 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
2498 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
2499 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
2500 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
2501 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
2502 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
2503 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
2504 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
2505 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
2506 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
2507 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
2508 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
2509 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
2510 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
2511 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
2512 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
2513
2514 /* EXTI13 configuration */
2515 #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
2516 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
2517 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
2518 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
2519 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
2520 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
2521 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
2522 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
2523 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
2524 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
2525 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
2526 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
2527 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
2528 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
2529 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
2530 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
2531 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
2532 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
2533 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
2534
2535 /*!< EXTI14 configuration */
2536 #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
2537 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
2538 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
2539 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
2540 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
2541 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
2542 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
2543 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
2544 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
2545 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
2546 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
2547 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
2548 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
2549 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
2550 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
2551 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
2552 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
2553 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
2554 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
2555
2556 /*!< EXTI15 configuration */
2557 #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
2558 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
2559 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
2560 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
2561 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
2562 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
2563 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
2564 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
2565 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
2566 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
2567 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
2568 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
2569 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
2570 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
2571 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
2572 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
2573 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
2574 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
2575 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
2576
2577 /****************** Bit definition for AFIO_MAPR2 register ******************/
2578
2579
2580
2581 /******************************************************************************/
2582 /* */
2583 /* SystemTick */
2584 /* */
2585 /******************************************************************************/
2586
2587 /***************** Bit definition for SysTick_CTRL register *****************/
2588 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
2589 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
2590 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
2591 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
2592
2593 /***************** Bit definition for SysTick_LOAD register *****************/
2594 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
2595
2596 /***************** Bit definition for SysTick_VAL register ******************/
2597 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
2598
2599 /***************** Bit definition for SysTick_CALIB register ****************/
2600 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
2601 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
2602 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
2603
2604 /******************************************************************************/
2605 /* */
2606 /* Nested Vectored Interrupt Controller */
2607 /* */
2608 /******************************************************************************/
2609
2610 /****************** Bit definition for NVIC_ISER register *******************/
2611 #define NVIC_ISER_SETENA_Pos (0U)
2612 #define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
2613 #define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
2614 #define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
2615 #define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
2616 #define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
2617 #define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
2618 #define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
2619 #define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
2620 #define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
2621 #define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
2622 #define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
2623 #define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
2624 #define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
2625 #define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
2626 #define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
2627 #define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
2628 #define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
2629 #define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
2630 #define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
2631 #define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
2632 #define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
2633 #define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
2634 #define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
2635 #define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
2636 #define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
2637 #define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
2638 #define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
2639 #define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
2640 #define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
2641 #define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
2642 #define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
2643 #define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
2644 #define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
2645 #define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
2646
2647 /****************** Bit definition for NVIC_ICER register *******************/
2648 #define NVIC_ICER_CLRENA_Pos (0U)
2649 #define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
2650 #define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
2651 #define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
2652 #define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
2653 #define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
2654 #define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
2655 #define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
2656 #define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
2657 #define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
2658 #define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
2659 #define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
2660 #define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
2661 #define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
2662 #define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
2663 #define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
2664 #define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
2665 #define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
2666 #define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
2667 #define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
2668 #define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
2669 #define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
2670 #define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
2671 #define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
2672 #define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
2673 #define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
2674 #define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
2675 #define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
2676 #define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
2677 #define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
2678 #define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
2679 #define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
2680 #define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
2681 #define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
2682 #define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
2683
2684 /****************** Bit definition for NVIC_ISPR register *******************/
2685 #define NVIC_ISPR_SETPEND_Pos (0U)
2686 #define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
2687 #define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
2688 #define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
2689 #define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
2690 #define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
2691 #define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
2692 #define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
2693 #define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
2694 #define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
2695 #define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
2696 #define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
2697 #define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
2698 #define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
2699 #define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
2700 #define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
2701 #define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
2702 #define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
2703 #define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
2704 #define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
2705 #define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
2706 #define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
2707 #define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
2708 #define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
2709 #define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
2710 #define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
2711 #define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
2712 #define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
2713 #define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
2714 #define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
2715 #define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
2716 #define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
2717 #define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
2718 #define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
2719 #define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
2720
2721 /****************** Bit definition for NVIC_ICPR register *******************/
2722 #define NVIC_ICPR_CLRPEND_Pos (0U)
2723 #define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
2724 #define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
2725 #define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
2726 #define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
2727 #define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
2728 #define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
2729 #define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
2730 #define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
2731 #define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
2732 #define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
2733 #define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
2734 #define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
2735 #define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
2736 #define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
2737 #define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
2738 #define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
2739 #define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
2740 #define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
2741 #define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
2742 #define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
2743 #define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
2744 #define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
2745 #define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
2746 #define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
2747 #define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
2748 #define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
2749 #define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
2750 #define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
2751 #define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
2752 #define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
2753 #define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
2754 #define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
2755 #define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
2756 #define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
2757
2758 /****************** Bit definition for NVIC_IABR register *******************/
2759 #define NVIC_IABR_ACTIVE_Pos (0U)
2760 #define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
2761 #define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
2762 #define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
2763 #define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
2764 #define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
2765 #define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
2766 #define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
2767 #define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
2768 #define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
2769 #define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
2770 #define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
2771 #define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
2772 #define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
2773 #define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
2774 #define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
2775 #define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
2776 #define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
2777 #define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
2778 #define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
2779 #define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
2780 #define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
2781 #define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
2782 #define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
2783 #define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
2784 #define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
2785 #define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
2786 #define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
2787 #define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
2788 #define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
2789 #define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
2790 #define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
2791 #define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
2792 #define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
2793 #define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
2794
2795 /****************** Bit definition for NVIC_PRI0 register *******************/
2796 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
2797 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
2798 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
2799 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
2800
2801 /****************** Bit definition for NVIC_PRI1 register *******************/
2802 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
2803 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
2804 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
2805 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
2806
2807 /****************** Bit definition for NVIC_PRI2 register *******************/
2808 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
2809 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
2810 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
2811 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
2812
2813 /****************** Bit definition for NVIC_PRI3 register *******************/
2814 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
2815 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
2816 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
2817 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
2818
2819 /****************** Bit definition for NVIC_PRI4 register *******************/
2820 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
2821 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
2822 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
2823 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
2824
2825 /****************** Bit definition for NVIC_PRI5 register *******************/
2826 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
2827 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
2828 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
2829 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
2830
2831 /****************** Bit definition for NVIC_PRI6 register *******************/
2832 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
2833 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
2834 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
2835 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
2836
2837 /****************** Bit definition for NVIC_PRI7 register *******************/
2838 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
2839 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
2840 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
2841 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
2842
2843 /****************** Bit definition for SCB_CPUID register *******************/
2844 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
2845 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
2846 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
2847 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
2848 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
2849
2850 /******************* Bit definition for SCB_ICSR register *******************/
2851 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
2852 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
2853 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
2854 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
2855 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
2856 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
2857 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
2858 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
2859 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
2860 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
2861
2862 /******************* Bit definition for SCB_VTOR register *******************/
2863 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
2864 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
2865
2866 /*!<***************** Bit definition for SCB_AIRCR register *******************/
2867 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
2868 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
2869 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
2870
2871 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
2872 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2873 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2874 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
2875
2876 /* prority group configuration */
2877 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
2878 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
2879 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
2880 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
2881 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
2882 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
2883 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
2884 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
2885
2886 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
2887 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
2888
2889 /******************* Bit definition for SCB_SCR register ********************/
2890 #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
2891 #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
2892 #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
2893
2894 /******************** Bit definition for SCB_CCR register *******************/
2895 #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
2896 #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
2897 #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
2898 #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
2899 #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
2900 #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
2901
2902 /******************* Bit definition for SCB_SHPR register ********************/
2903 #define SCB_SHPR_PRI_N_Pos (0U)
2904 #define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
2905 #define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
2906 #define SCB_SHPR_PRI_N1_Pos (8U)
2907 #define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
2908 #define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
2909 #define SCB_SHPR_PRI_N2_Pos (16U)
2910 #define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
2911 #define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
2912 #define SCB_SHPR_PRI_N3_Pos (24U)
2913 #define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
2914 #define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
2915
2916 /****************** Bit definition for SCB_SHCSR register *******************/
2917 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
2918 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
2919 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
2920 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
2921 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
2922 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
2923 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
2924 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
2925 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
2926 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
2927 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
2928 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
2929 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
2930 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
2931
2932 /******************* Bit definition for SCB_CFSR register *******************/
2933 /*!< MFSR */
2934 #define SCB_CFSR_IACCVIOL_Pos (0U)
2935 #define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
2936 #define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
2937 #define SCB_CFSR_DACCVIOL_Pos (1U)
2938 #define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
2939 #define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
2940 #define SCB_CFSR_MUNSTKERR_Pos (3U)
2941 #define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
2942 #define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
2943 #define SCB_CFSR_MSTKERR_Pos (4U)
2944 #define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
2945 #define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
2946 #define SCB_CFSR_MMARVALID_Pos (7U)
2947 #define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
2948 #define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
2949 /*!< BFSR */
2950 #define SCB_CFSR_IBUSERR_Pos (8U)
2951 #define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
2952 #define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
2953 #define SCB_CFSR_PRECISERR_Pos (9U)
2954 #define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
2955 #define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
2956 #define SCB_CFSR_IMPRECISERR_Pos (10U)
2957 #define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
2958 #define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
2959 #define SCB_CFSR_UNSTKERR_Pos (11U)
2960 #define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
2961 #define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
2962 #define SCB_CFSR_STKERR_Pos (12U)
2963 #define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
2964 #define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
2965 #define SCB_CFSR_BFARVALID_Pos (15U)
2966 #define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
2967 #define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
2968 /*!< UFSR */
2969 #define SCB_CFSR_UNDEFINSTR_Pos (16U)
2970 #define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
2971 #define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
2972 #define SCB_CFSR_INVSTATE_Pos (17U)
2973 #define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
2974 #define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
2975 #define SCB_CFSR_INVPC_Pos (18U)
2976 #define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
2977 #define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
2978 #define SCB_CFSR_NOCP_Pos (19U)
2979 #define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
2980 #define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
2981 #define SCB_CFSR_UNALIGNED_Pos (24U)
2982 #define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
2983 #define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
2984 #define SCB_CFSR_DIVBYZERO_Pos (25U)
2985 #define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
2986 #define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
2987
2988 /******************* Bit definition for SCB_HFSR register *******************/
2989 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
2990 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
2991 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
2992
2993 /******************* Bit definition for SCB_DFSR register *******************/
2994 #define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
2995 #define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
2996 #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
2997 #define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
2998 #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
2999
3000 /******************* Bit definition for SCB_MMFAR register ******************/
3001 #define SCB_MMFAR_ADDRESS_Pos (0U)
3002 #define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
3003 #define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
3004
3005 /******************* Bit definition for SCB_BFAR register *******************/
3006 #define SCB_BFAR_ADDRESS_Pos (0U)
3007 #define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
3008 #define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
3009
3010 /******************* Bit definition for SCB_afsr register *******************/
3011 #define SCB_AFSR_IMPDEF_Pos (0U)
3012 #define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
3013 #define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
3014
3015 /******************************************************************************/
3016 /* */
3017 /* External Interrupt/Event Controller */
3018 /* */
3019 /******************************************************************************/
3020
3021 /******************* Bit definition for EXTI_IMR register *******************/
3022 #define EXTI_IMR_MR0_Pos (0U)
3023 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
3024 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
3025 #define EXTI_IMR_MR1_Pos (1U)
3026 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
3027 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
3028 #define EXTI_IMR_MR2_Pos (2U)
3029 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
3030 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
3031 #define EXTI_IMR_MR3_Pos (3U)
3032 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
3033 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
3034 #define EXTI_IMR_MR4_Pos (4U)
3035 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
3036 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
3037 #define EXTI_IMR_MR5_Pos (5U)
3038 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
3039 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
3040 #define EXTI_IMR_MR6_Pos (6U)
3041 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
3042 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
3043 #define EXTI_IMR_MR7_Pos (7U)
3044 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
3045 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
3046 #define EXTI_IMR_MR8_Pos (8U)
3047 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
3048 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
3049 #define EXTI_IMR_MR9_Pos (9U)
3050 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
3051 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
3052 #define EXTI_IMR_MR10_Pos (10U)
3053 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
3054 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
3055 #define EXTI_IMR_MR11_Pos (11U)
3056 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
3057 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
3058 #define EXTI_IMR_MR12_Pos (12U)
3059 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
3060 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
3061 #define EXTI_IMR_MR13_Pos (13U)
3062 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
3063 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
3064 #define EXTI_IMR_MR14_Pos (14U)
3065 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
3066 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
3067 #define EXTI_IMR_MR15_Pos (15U)
3068 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
3069 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
3070 #define EXTI_IMR_MR16_Pos (16U)
3071 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
3072 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
3073 #define EXTI_IMR_MR17_Pos (17U)
3074 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
3075 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
3076 #define EXTI_IMR_MR18_Pos (18U)
3077 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
3078 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
3079 #define EXTI_IMR_MR19_Pos (19U)
3080 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
3081 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
3082
3083 /* References Defines */
3084 #define EXTI_IMR_IM0 EXTI_IMR_MR0
3085 #define EXTI_IMR_IM1 EXTI_IMR_MR1
3086 #define EXTI_IMR_IM2 EXTI_IMR_MR2
3087 #define EXTI_IMR_IM3 EXTI_IMR_MR3
3088 #define EXTI_IMR_IM4 EXTI_IMR_MR4
3089 #define EXTI_IMR_IM5 EXTI_IMR_MR5
3090 #define EXTI_IMR_IM6 EXTI_IMR_MR6
3091 #define EXTI_IMR_IM7 EXTI_IMR_MR7
3092 #define EXTI_IMR_IM8 EXTI_IMR_MR8
3093 #define EXTI_IMR_IM9 EXTI_IMR_MR9
3094 #define EXTI_IMR_IM10 EXTI_IMR_MR10
3095 #define EXTI_IMR_IM11 EXTI_IMR_MR11
3096 #define EXTI_IMR_IM12 EXTI_IMR_MR12
3097 #define EXTI_IMR_IM13 EXTI_IMR_MR13
3098 #define EXTI_IMR_IM14 EXTI_IMR_MR14
3099 #define EXTI_IMR_IM15 EXTI_IMR_MR15
3100 #define EXTI_IMR_IM16 EXTI_IMR_MR16
3101 #define EXTI_IMR_IM17 EXTI_IMR_MR17
3102 #define EXTI_IMR_IM18 EXTI_IMR_MR18
3103 #define EXTI_IMR_IM19 EXTI_IMR_MR19
3104
3105 /******************* Bit definition for EXTI_EMR register *******************/
3106 #define EXTI_EMR_MR0_Pos (0U)
3107 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
3108 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
3109 #define EXTI_EMR_MR1_Pos (1U)
3110 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
3111 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
3112 #define EXTI_EMR_MR2_Pos (2U)
3113 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
3114 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
3115 #define EXTI_EMR_MR3_Pos (3U)
3116 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
3117 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
3118 #define EXTI_EMR_MR4_Pos (4U)
3119 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
3120 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
3121 #define EXTI_EMR_MR5_Pos (5U)
3122 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
3123 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
3124 #define EXTI_EMR_MR6_Pos (6U)
3125 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
3126 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
3127 #define EXTI_EMR_MR7_Pos (7U)
3128 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
3129 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
3130 #define EXTI_EMR_MR8_Pos (8U)
3131 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
3132 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
3133 #define EXTI_EMR_MR9_Pos (9U)
3134 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
3135 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
3136 #define EXTI_EMR_MR10_Pos (10U)
3137 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
3138 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
3139 #define EXTI_EMR_MR11_Pos (11U)
3140 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
3141 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
3142 #define EXTI_EMR_MR12_Pos (12U)
3143 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
3144 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
3145 #define EXTI_EMR_MR13_Pos (13U)
3146 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
3147 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
3148 #define EXTI_EMR_MR14_Pos (14U)
3149 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
3150 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
3151 #define EXTI_EMR_MR15_Pos (15U)
3152 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
3153 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
3154 #define EXTI_EMR_MR16_Pos (16U)
3155 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
3156 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
3157 #define EXTI_EMR_MR17_Pos (17U)
3158 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
3159 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
3160 #define EXTI_EMR_MR18_Pos (18U)
3161 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
3162 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
3163 #define EXTI_EMR_MR19_Pos (19U)
3164 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
3165 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
3166
3167 /* References Defines */
3168 #define EXTI_EMR_EM0 EXTI_EMR_MR0
3169 #define EXTI_EMR_EM1 EXTI_EMR_MR1
3170 #define EXTI_EMR_EM2 EXTI_EMR_MR2
3171 #define EXTI_EMR_EM3 EXTI_EMR_MR3
3172 #define EXTI_EMR_EM4 EXTI_EMR_MR4
3173 #define EXTI_EMR_EM5 EXTI_EMR_MR5
3174 #define EXTI_EMR_EM6 EXTI_EMR_MR6
3175 #define EXTI_EMR_EM7 EXTI_EMR_MR7
3176 #define EXTI_EMR_EM8 EXTI_EMR_MR8
3177 #define EXTI_EMR_EM9 EXTI_EMR_MR9
3178 #define EXTI_EMR_EM10 EXTI_EMR_MR10
3179 #define EXTI_EMR_EM11 EXTI_EMR_MR11
3180 #define EXTI_EMR_EM12 EXTI_EMR_MR12
3181 #define EXTI_EMR_EM13 EXTI_EMR_MR13
3182 #define EXTI_EMR_EM14 EXTI_EMR_MR14
3183 #define EXTI_EMR_EM15 EXTI_EMR_MR15
3184 #define EXTI_EMR_EM16 EXTI_EMR_MR16
3185 #define EXTI_EMR_EM17 EXTI_EMR_MR17
3186 #define EXTI_EMR_EM18 EXTI_EMR_MR18
3187 #define EXTI_EMR_EM19 EXTI_EMR_MR19
3188
3189 /****************** Bit definition for EXTI_RTSR register *******************/
3190 #define EXTI_RTSR_TR0_Pos (0U)
3191 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
3192 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
3193 #define EXTI_RTSR_TR1_Pos (1U)
3194 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
3195 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
3196 #define EXTI_RTSR_TR2_Pos (2U)
3197 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
3198 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
3199 #define EXTI_RTSR_TR3_Pos (3U)
3200 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
3201 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
3202 #define EXTI_RTSR_TR4_Pos (4U)
3203 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
3204 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
3205 #define EXTI_RTSR_TR5_Pos (5U)
3206 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
3207 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
3208 #define EXTI_RTSR_TR6_Pos (6U)
3209 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
3210 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
3211 #define EXTI_RTSR_TR7_Pos (7U)
3212 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
3213 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
3214 #define EXTI_RTSR_TR8_Pos (8U)
3215 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
3216 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
3217 #define EXTI_RTSR_TR9_Pos (9U)
3218 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
3219 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
3220 #define EXTI_RTSR_TR10_Pos (10U)
3221 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
3222 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
3223 #define EXTI_RTSR_TR11_Pos (11U)
3224 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
3225 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
3226 #define EXTI_RTSR_TR12_Pos (12U)
3227 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
3228 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
3229 #define EXTI_RTSR_TR13_Pos (13U)
3230 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
3231 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
3232 #define EXTI_RTSR_TR14_Pos (14U)
3233 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
3234 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
3235 #define EXTI_RTSR_TR15_Pos (15U)
3236 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
3237 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
3238 #define EXTI_RTSR_TR16_Pos (16U)
3239 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
3240 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
3241 #define EXTI_RTSR_TR17_Pos (17U)
3242 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
3243 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
3244 #define EXTI_RTSR_TR18_Pos (18U)
3245 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
3246 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
3247 #define EXTI_RTSR_TR19_Pos (19U)
3248 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
3249 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
3250
3251 /* References Defines */
3252 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
3253 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
3254 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
3255 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
3256 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
3257 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
3258 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
3259 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
3260 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
3261 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
3262 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
3263 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
3264 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
3265 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
3266 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
3267 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
3268 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
3269 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
3270 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
3271 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
3272
3273 /****************** Bit definition for EXTI_FTSR register *******************/
3274 #define EXTI_FTSR_TR0_Pos (0U)
3275 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
3276 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
3277 #define EXTI_FTSR_TR1_Pos (1U)
3278 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
3279 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
3280 #define EXTI_FTSR_TR2_Pos (2U)
3281 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
3282 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
3283 #define EXTI_FTSR_TR3_Pos (3U)
3284 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
3285 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
3286 #define EXTI_FTSR_TR4_Pos (4U)
3287 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
3288 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
3289 #define EXTI_FTSR_TR5_Pos (5U)
3290 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
3291 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
3292 #define EXTI_FTSR_TR6_Pos (6U)
3293 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
3294 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
3295 #define EXTI_FTSR_TR7_Pos (7U)
3296 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
3297 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
3298 #define EXTI_FTSR_TR8_Pos (8U)
3299 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
3300 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
3301 #define EXTI_FTSR_TR9_Pos (9U)
3302 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
3303 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
3304 #define EXTI_FTSR_TR10_Pos (10U)
3305 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
3306 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
3307 #define EXTI_FTSR_TR11_Pos (11U)
3308 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
3309 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
3310 #define EXTI_FTSR_TR12_Pos (12U)
3311 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
3312 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
3313 #define EXTI_FTSR_TR13_Pos (13U)
3314 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
3315 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
3316 #define EXTI_FTSR_TR14_Pos (14U)
3317 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
3318 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
3319 #define EXTI_FTSR_TR15_Pos (15U)
3320 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
3321 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
3322 #define EXTI_FTSR_TR16_Pos (16U)
3323 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
3324 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
3325 #define EXTI_FTSR_TR17_Pos (17U)
3326 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
3327 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
3328 #define EXTI_FTSR_TR18_Pos (18U)
3329 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
3330 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
3331 #define EXTI_FTSR_TR19_Pos (19U)
3332 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
3333 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
3334
3335 /* References Defines */
3336 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
3337 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
3338 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
3339 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
3340 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
3341 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
3342 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
3343 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
3344 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
3345 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
3346 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
3347 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
3348 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
3349 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
3350 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
3351 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
3352 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
3353 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
3354 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
3355 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
3356
3357 /****************** Bit definition for EXTI_SWIER register ******************/
3358 #define EXTI_SWIER_SWIER0_Pos (0U)
3359 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
3360 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
3361 #define EXTI_SWIER_SWIER1_Pos (1U)
3362 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
3363 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
3364 #define EXTI_SWIER_SWIER2_Pos (2U)
3365 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
3366 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
3367 #define EXTI_SWIER_SWIER3_Pos (3U)
3368 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
3369 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
3370 #define EXTI_SWIER_SWIER4_Pos (4U)
3371 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
3372 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
3373 #define EXTI_SWIER_SWIER5_Pos (5U)
3374 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
3375 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
3376 #define EXTI_SWIER_SWIER6_Pos (6U)
3377 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
3378 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
3379 #define EXTI_SWIER_SWIER7_Pos (7U)
3380 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
3381 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
3382 #define EXTI_SWIER_SWIER8_Pos (8U)
3383 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
3384 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
3385 #define EXTI_SWIER_SWIER9_Pos (9U)
3386 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
3387 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
3388 #define EXTI_SWIER_SWIER10_Pos (10U)
3389 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
3390 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
3391 #define EXTI_SWIER_SWIER11_Pos (11U)
3392 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
3393 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
3394 #define EXTI_SWIER_SWIER12_Pos (12U)
3395 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
3396 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
3397 #define EXTI_SWIER_SWIER13_Pos (13U)
3398 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
3399 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
3400 #define EXTI_SWIER_SWIER14_Pos (14U)
3401 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
3402 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
3403 #define EXTI_SWIER_SWIER15_Pos (15U)
3404 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
3405 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
3406 #define EXTI_SWIER_SWIER16_Pos (16U)
3407 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
3408 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
3409 #define EXTI_SWIER_SWIER17_Pos (17U)
3410 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
3411 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
3412 #define EXTI_SWIER_SWIER18_Pos (18U)
3413 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
3414 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
3415 #define EXTI_SWIER_SWIER19_Pos (19U)
3416 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
3417 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
3418
3419 /* References Defines */
3420 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
3421 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
3422 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
3423 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
3424 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
3425 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
3426 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
3427 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
3428 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
3429 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
3430 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
3431 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
3432 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
3433 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
3434 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
3435 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
3436 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
3437 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
3438 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
3439 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
3440
3441 /******************* Bit definition for EXTI_PR register ********************/
3442 #define EXTI_PR_PR0_Pos (0U)
3443 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
3444 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
3445 #define EXTI_PR_PR1_Pos (1U)
3446 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
3447 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
3448 #define EXTI_PR_PR2_Pos (2U)
3449 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
3450 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
3451 #define EXTI_PR_PR3_Pos (3U)
3452 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
3453 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
3454 #define EXTI_PR_PR4_Pos (4U)
3455 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
3456 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
3457 #define EXTI_PR_PR5_Pos (5U)
3458 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
3459 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
3460 #define EXTI_PR_PR6_Pos (6U)
3461 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
3462 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
3463 #define EXTI_PR_PR7_Pos (7U)
3464 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
3465 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
3466 #define EXTI_PR_PR8_Pos (8U)
3467 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
3468 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
3469 #define EXTI_PR_PR9_Pos (9U)
3470 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
3471 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
3472 #define EXTI_PR_PR10_Pos (10U)
3473 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
3474 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
3475 #define EXTI_PR_PR11_Pos (11U)
3476 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
3477 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
3478 #define EXTI_PR_PR12_Pos (12U)
3479 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
3480 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
3481 #define EXTI_PR_PR13_Pos (13U)
3482 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
3483 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
3484 #define EXTI_PR_PR14_Pos (14U)
3485 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
3486 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
3487 #define EXTI_PR_PR15_Pos (15U)
3488 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
3489 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
3490 #define EXTI_PR_PR16_Pos (16U)
3491 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
3492 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
3493 #define EXTI_PR_PR17_Pos (17U)
3494 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
3495 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
3496 #define EXTI_PR_PR18_Pos (18U)
3497 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
3498 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
3499 #define EXTI_PR_PR19_Pos (19U)
3500 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
3501 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
3502
3503 /* References Defines */
3504 #define EXTI_PR_PIF0 EXTI_PR_PR0
3505 #define EXTI_PR_PIF1 EXTI_PR_PR1
3506 #define EXTI_PR_PIF2 EXTI_PR_PR2
3507 #define EXTI_PR_PIF3 EXTI_PR_PR3
3508 #define EXTI_PR_PIF4 EXTI_PR_PR4
3509 #define EXTI_PR_PIF5 EXTI_PR_PR5
3510 #define EXTI_PR_PIF6 EXTI_PR_PR6
3511 #define EXTI_PR_PIF7 EXTI_PR_PR7
3512 #define EXTI_PR_PIF8 EXTI_PR_PR8
3513 #define EXTI_PR_PIF9 EXTI_PR_PR9
3514 #define EXTI_PR_PIF10 EXTI_PR_PR10
3515 #define EXTI_PR_PIF11 EXTI_PR_PR11
3516 #define EXTI_PR_PIF12 EXTI_PR_PR12
3517 #define EXTI_PR_PIF13 EXTI_PR_PR13
3518 #define EXTI_PR_PIF14 EXTI_PR_PR14
3519 #define EXTI_PR_PIF15 EXTI_PR_PR15
3520 #define EXTI_PR_PIF16 EXTI_PR_PR16
3521 #define EXTI_PR_PIF17 EXTI_PR_PR17
3522 #define EXTI_PR_PIF18 EXTI_PR_PR18
3523 #define EXTI_PR_PIF19 EXTI_PR_PR19
3524
3525 /******************************************************************************/
3526 /* */
3527 /* DMA Controller */
3528 /* */
3529 /******************************************************************************/
3530
3531 /******************* Bit definition for DMA_ISR register ********************/
3532 #define DMA_ISR_GIF1_Pos (0U)
3533 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
3534 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
3535 #define DMA_ISR_TCIF1_Pos (1U)
3536 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
3537 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
3538 #define DMA_ISR_HTIF1_Pos (2U)
3539 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
3540 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
3541 #define DMA_ISR_TEIF1_Pos (3U)
3542 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
3543 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
3544 #define DMA_ISR_GIF2_Pos (4U)
3545 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
3546 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
3547 #define DMA_ISR_TCIF2_Pos (5U)
3548 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
3549 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
3550 #define DMA_ISR_HTIF2_Pos (6U)
3551 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
3552 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
3553 #define DMA_ISR_TEIF2_Pos (7U)
3554 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
3555 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
3556 #define DMA_ISR_GIF3_Pos (8U)
3557 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
3558 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
3559 #define DMA_ISR_TCIF3_Pos (9U)
3560 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
3561 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
3562 #define DMA_ISR_HTIF3_Pos (10U)
3563 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
3564 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
3565 #define DMA_ISR_TEIF3_Pos (11U)
3566 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
3567 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
3568 #define DMA_ISR_GIF4_Pos (12U)
3569 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
3570 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
3571 #define DMA_ISR_TCIF4_Pos (13U)
3572 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
3573 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
3574 #define DMA_ISR_HTIF4_Pos (14U)
3575 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
3576 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
3577 #define DMA_ISR_TEIF4_Pos (15U)
3578 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
3579 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
3580 #define DMA_ISR_GIF5_Pos (16U)
3581 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
3582 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
3583 #define DMA_ISR_TCIF5_Pos (17U)
3584 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
3585 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
3586 #define DMA_ISR_HTIF5_Pos (18U)
3587 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
3588 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
3589 #define DMA_ISR_TEIF5_Pos (19U)
3590 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
3591 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
3592 #define DMA_ISR_GIF6_Pos (20U)
3593 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
3594 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
3595 #define DMA_ISR_TCIF6_Pos (21U)
3596 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
3597 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
3598 #define DMA_ISR_HTIF6_Pos (22U)
3599 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
3600 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
3601 #define DMA_ISR_TEIF6_Pos (23U)
3602 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
3603 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
3604 #define DMA_ISR_GIF7_Pos (24U)
3605 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
3606 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
3607 #define DMA_ISR_TCIF7_Pos (25U)
3608 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
3609 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
3610 #define DMA_ISR_HTIF7_Pos (26U)
3611 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
3612 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
3613 #define DMA_ISR_TEIF7_Pos (27U)
3614 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
3615 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
3616
3617 /******************* Bit definition for DMA_IFCR register *******************/
3618 #define DMA_IFCR_CGIF1_Pos (0U)
3619 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
3620 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
3621 #define DMA_IFCR_CTCIF1_Pos (1U)
3622 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
3623 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
3624 #define DMA_IFCR_CHTIF1_Pos (2U)
3625 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
3626 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
3627 #define DMA_IFCR_CTEIF1_Pos (3U)
3628 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
3629 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
3630 #define DMA_IFCR_CGIF2_Pos (4U)
3631 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
3632 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
3633 #define DMA_IFCR_CTCIF2_Pos (5U)
3634 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
3635 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
3636 #define DMA_IFCR_CHTIF2_Pos (6U)
3637 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
3638 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
3639 #define DMA_IFCR_CTEIF2_Pos (7U)
3640 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
3641 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
3642 #define DMA_IFCR_CGIF3_Pos (8U)
3643 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
3644 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
3645 #define DMA_IFCR_CTCIF3_Pos (9U)
3646 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
3647 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
3648 #define DMA_IFCR_CHTIF3_Pos (10U)
3649 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
3650 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
3651 #define DMA_IFCR_CTEIF3_Pos (11U)
3652 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
3653 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
3654 #define DMA_IFCR_CGIF4_Pos (12U)
3655 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
3656 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
3657 #define DMA_IFCR_CTCIF4_Pos (13U)
3658 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
3659 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
3660 #define DMA_IFCR_CHTIF4_Pos (14U)
3661 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
3662 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
3663 #define DMA_IFCR_CTEIF4_Pos (15U)
3664 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
3665 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
3666 #define DMA_IFCR_CGIF5_Pos (16U)
3667 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
3668 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
3669 #define DMA_IFCR_CTCIF5_Pos (17U)
3670 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
3671 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
3672 #define DMA_IFCR_CHTIF5_Pos (18U)
3673 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
3674 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
3675 #define DMA_IFCR_CTEIF5_Pos (19U)
3676 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
3677 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
3678 #define DMA_IFCR_CGIF6_Pos (20U)
3679 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
3680 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
3681 #define DMA_IFCR_CTCIF6_Pos (21U)
3682 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
3683 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
3684 #define DMA_IFCR_CHTIF6_Pos (22U)
3685 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
3686 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
3687 #define DMA_IFCR_CTEIF6_Pos (23U)
3688 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
3689 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
3690 #define DMA_IFCR_CGIF7_Pos (24U)
3691 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
3692 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
3693 #define DMA_IFCR_CTCIF7_Pos (25U)
3694 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
3695 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
3696 #define DMA_IFCR_CHTIF7_Pos (26U)
3697 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
3698 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
3699 #define DMA_IFCR_CTEIF7_Pos (27U)
3700 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
3701 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
3702
3703 /******************* Bit definition for DMA_CCR register *******************/
3704 #define DMA_CCR_EN_Pos (0U)
3705 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
3706 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
3707 #define DMA_CCR_TCIE_Pos (1U)
3708 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
3709 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
3710 #define DMA_CCR_HTIE_Pos (2U)
3711 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
3712 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
3713 #define DMA_CCR_TEIE_Pos (3U)
3714 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
3715 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
3716 #define DMA_CCR_DIR_Pos (4U)
3717 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
3718 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
3719 #define DMA_CCR_CIRC_Pos (5U)
3720 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
3721 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
3722 #define DMA_CCR_PINC_Pos (6U)
3723 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
3724 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
3725 #define DMA_CCR_MINC_Pos (7U)
3726 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3727 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
3728
3729 #define DMA_CCR_PSIZE_Pos (8U)
3730 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
3731 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
3732 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
3733 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
3734
3735 #define DMA_CCR_MSIZE_Pos (10U)
3736 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
3737 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
3738 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
3739 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
3740
3741 #define DMA_CCR_PL_Pos (12U)
3742 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
3743 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
3744 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
3745 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
3746
3747 #define DMA_CCR_MEM2MEM_Pos (14U)
3748 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
3749 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
3750
3751 /****************** Bit definition for DMA_CNDTR register ******************/
3752 #define DMA_CNDTR_NDT_Pos (0U)
3753 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
3754 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
3755
3756 /****************** Bit definition for DMA_CPAR register *******************/
3757 #define DMA_CPAR_PA_Pos (0U)
3758 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
3759 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
3760
3761 /****************** Bit definition for DMA_CMAR register *******************/
3762 #define DMA_CMAR_MA_Pos (0U)
3763 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
3764 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
3765
3766 /******************************************************************************/
3767 /* */
3768 /* Analog to Digital Converter (ADC) */
3769 /* */
3770 /******************************************************************************/
3771
3772 /*
3773 * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
3774 */
3775 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
3776
3777 /******************** Bit definition for ADC_SR register ********************/
3778 #define ADC_SR_AWD_Pos (0U)
3779 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
3780 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
3781 #define ADC_SR_EOS_Pos (1U)
3782 #define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
3783 #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
3784 #define ADC_SR_JEOS_Pos (2U)
3785 #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
3786 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
3787 #define ADC_SR_JSTRT_Pos (3U)
3788 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
3789 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
3790 #define ADC_SR_STRT_Pos (4U)
3791 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
3792 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
3793
3794 /* Legacy defines */
3795 #define ADC_SR_EOC (ADC_SR_EOS)
3796 #define ADC_SR_JEOC (ADC_SR_JEOS)
3797
3798 /******************* Bit definition for ADC_CR1 register ********************/
3799 #define ADC_CR1_AWDCH_Pos (0U)
3800 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
3801 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
3802 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
3803 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
3804 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
3805 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
3806 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
3807
3808 #define ADC_CR1_EOSIE_Pos (5U)
3809 #define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
3810 #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
3811 #define ADC_CR1_AWDIE_Pos (6U)
3812 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
3813 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
3814 #define ADC_CR1_JEOSIE_Pos (7U)
3815 #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
3816 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
3817 #define ADC_CR1_SCAN_Pos (8U)
3818 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
3819 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
3820 #define ADC_CR1_AWDSGL_Pos (9U)
3821 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
3822 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
3823 #define ADC_CR1_JAUTO_Pos (10U)
3824 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
3825 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
3826 #define ADC_CR1_DISCEN_Pos (11U)
3827 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
3828 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
3829 #define ADC_CR1_JDISCEN_Pos (12U)
3830 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
3831 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
3832
3833 #define ADC_CR1_DISCNUM_Pos (13U)
3834 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
3835 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
3836 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
3837 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
3838 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
3839
3840 #define ADC_CR1_DUALMOD_Pos (16U)
3841 #define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
3842 #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
3843 #define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
3844 #define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
3845 #define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
3846 #define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
3847
3848 #define ADC_CR1_JAWDEN_Pos (22U)
3849 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
3850 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
3851 #define ADC_CR1_AWDEN_Pos (23U)
3852 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
3853 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
3854
3855 /* Legacy defines */
3856 #define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
3857 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
3858
3859 /******************* Bit definition for ADC_CR2 register ********************/
3860 #define ADC_CR2_ADON_Pos (0U)
3861 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
3862 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
3863 #define ADC_CR2_CONT_Pos (1U)
3864 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
3865 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
3866 #define ADC_CR2_CAL_Pos (2U)
3867 #define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
3868 #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
3869 #define ADC_CR2_RSTCAL_Pos (3U)
3870 #define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
3871 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
3872 #define ADC_CR2_DMA_Pos (8U)
3873 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
3874 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
3875 #define ADC_CR2_ALIGN_Pos (11U)
3876 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
3877 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
3878
3879 #define ADC_CR2_JEXTSEL_Pos (12U)
3880 #define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
3881 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
3882 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
3883 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
3884 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
3885
3886 #define ADC_CR2_JEXTTRIG_Pos (15U)
3887 #define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
3888 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
3889
3890 #define ADC_CR2_EXTSEL_Pos (17U)
3891 #define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
3892 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
3893 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
3894 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
3895 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
3896
3897 #define ADC_CR2_EXTTRIG_Pos (20U)
3898 #define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
3899 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
3900 #define ADC_CR2_JSWSTART_Pos (21U)
3901 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
3902 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
3903 #define ADC_CR2_SWSTART_Pos (22U)
3904 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
3905 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
3906 #define ADC_CR2_TSVREFE_Pos (23U)
3907 #define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
3908 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
3909
3910 /****************** Bit definition for ADC_SMPR1 register *******************/
3911 #define ADC_SMPR1_SMP10_Pos (0U)
3912 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
3913 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
3914 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
3915 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
3916 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
3917
3918 #define ADC_SMPR1_SMP11_Pos (3U)
3919 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
3920 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
3921 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
3922 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
3923 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
3924
3925 #define ADC_SMPR1_SMP12_Pos (6U)
3926 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
3927 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
3928 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
3929 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
3930 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
3931
3932 #define ADC_SMPR1_SMP13_Pos (9U)
3933 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
3934 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
3935 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
3936 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
3937 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
3938
3939 #define ADC_SMPR1_SMP14_Pos (12U)
3940 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
3941 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
3942 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
3943 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
3944 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
3945
3946 #define ADC_SMPR1_SMP15_Pos (15U)
3947 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
3948 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
3949 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
3950 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
3951 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
3952
3953 #define ADC_SMPR1_SMP16_Pos (18U)
3954 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
3955 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
3956 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
3957 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
3958 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
3959
3960 #define ADC_SMPR1_SMP17_Pos (21U)
3961 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
3962 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
3963 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
3964 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
3965 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
3966
3967 /****************** Bit definition for ADC_SMPR2 register *******************/
3968 #define ADC_SMPR2_SMP0_Pos (0U)
3969 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
3970 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
3971 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
3972 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
3973 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
3974
3975 #define ADC_SMPR2_SMP1_Pos (3U)
3976 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
3977 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
3978 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
3979 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
3980 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
3981
3982 #define ADC_SMPR2_SMP2_Pos (6U)
3983 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
3984 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
3985 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
3986 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
3987 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
3988
3989 #define ADC_SMPR2_SMP3_Pos (9U)
3990 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
3991 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
3992 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
3993 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
3994 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
3995
3996 #define ADC_SMPR2_SMP4_Pos (12U)
3997 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
3998 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
3999 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
4000 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
4001 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
4002
4003 #define ADC_SMPR2_SMP5_Pos (15U)
4004 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
4005 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
4006 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
4007 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
4008 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
4009
4010 #define ADC_SMPR2_SMP6_Pos (18U)
4011 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
4012 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
4013 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
4014 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
4015 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
4016
4017 #define ADC_SMPR2_SMP7_Pos (21U)
4018 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
4019 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
4020 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
4021 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
4022 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
4023
4024 #define ADC_SMPR2_SMP8_Pos (24U)
4025 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
4026 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
4027 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
4028 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
4029 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
4030
4031 #define ADC_SMPR2_SMP9_Pos (27U)
4032 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
4033 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
4034 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
4035 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
4036 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
4037
4038 /****************** Bit definition for ADC_JOFR1 register *******************/
4039 #define ADC_JOFR1_JOFFSET1_Pos (0U)
4040 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
4041 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
4042
4043 /****************** Bit definition for ADC_JOFR2 register *******************/
4044 #define ADC_JOFR2_JOFFSET2_Pos (0U)
4045 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
4046 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
4047
4048 /****************** Bit definition for ADC_JOFR3 register *******************/
4049 #define ADC_JOFR3_JOFFSET3_Pos (0U)
4050 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
4051 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
4052
4053 /****************** Bit definition for ADC_JOFR4 register *******************/
4054 #define ADC_JOFR4_JOFFSET4_Pos (0U)
4055 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
4056 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
4057
4058 /******************* Bit definition for ADC_HTR register ********************/
4059 #define ADC_HTR_HT_Pos (0U)
4060 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
4061 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
4062
4063 /******************* Bit definition for ADC_LTR register ********************/
4064 #define ADC_LTR_LT_Pos (0U)
4065 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
4066 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
4067
4068 /******************* Bit definition for ADC_SQR1 register *******************/
4069 #define ADC_SQR1_SQ13_Pos (0U)
4070 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
4071 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
4072 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
4073 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
4074 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
4075 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
4076 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
4077
4078 #define ADC_SQR1_SQ14_Pos (5U)
4079 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
4080 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
4081 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
4082 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
4083 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
4084 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
4085 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
4086
4087 #define ADC_SQR1_SQ15_Pos (10U)
4088 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
4089 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
4090 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
4091 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
4092 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
4093 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
4094 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
4095
4096 #define ADC_SQR1_SQ16_Pos (15U)
4097 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
4098 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
4099 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
4100 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
4101 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
4102 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
4103 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
4104
4105 #define ADC_SQR1_L_Pos (20U)
4106 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
4107 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
4108 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
4109 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
4110 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
4111 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
4112
4113 /******************* Bit definition for ADC_SQR2 register *******************/
4114 #define ADC_SQR2_SQ7_Pos (0U)
4115 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
4116 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
4117 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
4118 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
4119 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
4120 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
4121 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
4122
4123 #define ADC_SQR2_SQ8_Pos (5U)
4124 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
4125 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
4126 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
4127 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
4128 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
4129 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
4130 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
4131
4132 #define ADC_SQR2_SQ9_Pos (10U)
4133 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
4134 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
4135 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
4136 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
4137 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
4138 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
4139 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
4140
4141 #define ADC_SQR2_SQ10_Pos (15U)
4142 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
4143 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
4144 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
4145 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
4146 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
4147 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
4148 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
4149
4150 #define ADC_SQR2_SQ11_Pos (20U)
4151 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
4152 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
4153 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
4154 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
4155 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
4156 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
4157 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
4158
4159 #define ADC_SQR2_SQ12_Pos (25U)
4160 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
4161 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
4162 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
4163 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
4164 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
4165 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
4166 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
4167
4168 /******************* Bit definition for ADC_SQR3 register *******************/
4169 #define ADC_SQR3_SQ1_Pos (0U)
4170 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
4171 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
4172 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
4173 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
4174 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
4175 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
4176 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
4177
4178 #define ADC_SQR3_SQ2_Pos (5U)
4179 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
4180 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
4181 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
4182 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
4183 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
4184 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
4185 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
4186
4187 #define ADC_SQR3_SQ3_Pos (10U)
4188 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
4189 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
4190 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
4191 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
4192 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
4193 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
4194 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
4195
4196 #define ADC_SQR3_SQ4_Pos (15U)
4197 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
4198 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
4199 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
4200 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
4201 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
4202 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
4203 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
4204
4205 #define ADC_SQR3_SQ5_Pos (20U)
4206 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
4207 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
4208 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
4209 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
4210 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
4211 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
4212 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
4213
4214 #define ADC_SQR3_SQ6_Pos (25U)
4215 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
4216 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
4217 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
4218 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
4219 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
4220 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
4221 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
4222
4223 /******************* Bit definition for ADC_JSQR register *******************/
4224 #define ADC_JSQR_JSQ1_Pos (0U)
4225 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
4226 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
4227 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
4228 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
4229 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
4230 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
4231 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
4232
4233 #define ADC_JSQR_JSQ2_Pos (5U)
4234 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
4235 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
4236 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
4237 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
4238 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
4239 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
4240 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
4241
4242 #define ADC_JSQR_JSQ3_Pos (10U)
4243 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
4244 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
4245 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
4246 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
4247 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
4248 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
4249 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
4250
4251 #define ADC_JSQR_JSQ4_Pos (15U)
4252 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
4253 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
4254 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
4255 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
4256 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
4257 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
4258 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
4259
4260 #define ADC_JSQR_JL_Pos (20U)
4261 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
4262 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
4263 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
4264 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
4265
4266 /******************* Bit definition for ADC_JDR1 register *******************/
4267 #define ADC_JDR1_JDATA_Pos (0U)
4268 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
4269 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
4270
4271 /******************* Bit definition for ADC_JDR2 register *******************/
4272 #define ADC_JDR2_JDATA_Pos (0U)
4273 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
4274 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
4275
4276 /******************* Bit definition for ADC_JDR3 register *******************/
4277 #define ADC_JDR3_JDATA_Pos (0U)
4278 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
4279 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
4280
4281 /******************* Bit definition for ADC_JDR4 register *******************/
4282 #define ADC_JDR4_JDATA_Pos (0U)
4283 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
4284 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
4285
4286 /******************** Bit definition for ADC_DR register ********************/
4287 #define ADC_DR_DATA_Pos (0U)
4288 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
4289 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
4290 #define ADC_DR_ADC2DATA_Pos (16U)
4291 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
4292 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
4293
4294
4295 /*****************************************************************************/
4296 /* */
4297 /* Timers (TIM) */
4298 /* */
4299 /*****************************************************************************/
4300 /******************* Bit definition for TIM_CR1 register *******************/
4301 #define TIM_CR1_CEN_Pos (0U)
4302 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
4303 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
4304 #define TIM_CR1_UDIS_Pos (1U)
4305 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
4306 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
4307 #define TIM_CR1_URS_Pos (2U)
4308 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
4309 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
4310 #define TIM_CR1_OPM_Pos (3U)
4311 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
4312 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
4313 #define TIM_CR1_DIR_Pos (4U)
4314 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
4315 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
4316
4317 #define TIM_CR1_CMS_Pos (5U)
4318 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
4319 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
4320 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
4321 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
4322
4323 #define TIM_CR1_ARPE_Pos (7U)
4324 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
4325 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
4326
4327 #define TIM_CR1_CKD_Pos (8U)
4328 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
4329 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
4330 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
4331 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
4332
4333 /******************* Bit definition for TIM_CR2 register *******************/
4334 #define TIM_CR2_CCPC_Pos (0U)
4335 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
4336 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
4337 #define TIM_CR2_CCUS_Pos (2U)
4338 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
4339 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
4340 #define TIM_CR2_CCDS_Pos (3U)
4341 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
4342 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
4343
4344 #define TIM_CR2_MMS_Pos (4U)
4345 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
4346 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
4347 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
4348 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
4349 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
4350
4351 #define TIM_CR2_TI1S_Pos (7U)
4352 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
4353 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
4354 #define TIM_CR2_OIS1_Pos (8U)
4355 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
4356 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
4357 #define TIM_CR2_OIS1N_Pos (9U)
4358 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
4359 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
4360 #define TIM_CR2_OIS2_Pos (10U)
4361 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
4362 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
4363 #define TIM_CR2_OIS2N_Pos (11U)
4364 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
4365 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
4366 #define TIM_CR2_OIS3_Pos (12U)
4367 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
4368 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
4369 #define TIM_CR2_OIS3N_Pos (13U)
4370 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
4371 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
4372 #define TIM_CR2_OIS4_Pos (14U)
4373 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
4374 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
4375
4376 /******************* Bit definition for TIM_SMCR register ******************/
4377 #define TIM_SMCR_SMS_Pos (0U)
4378 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
4379 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
4380 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
4381 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
4382 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
4383
4384 #define TIM_SMCR_OCCS_Pos (3U)
4385 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
4386 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
4387
4388 #define TIM_SMCR_TS_Pos (4U)
4389 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
4390 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
4391 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
4392 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
4393 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
4394
4395 #define TIM_SMCR_MSM_Pos (7U)
4396 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
4397 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
4398
4399 #define TIM_SMCR_ETF_Pos (8U)
4400 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
4401 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
4402 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
4403 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
4404 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
4405 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
4406
4407 #define TIM_SMCR_ETPS_Pos (12U)
4408 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
4409 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
4410 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
4411 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
4412
4413 #define TIM_SMCR_ECE_Pos (14U)
4414 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
4415 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
4416 #define TIM_SMCR_ETP_Pos (15U)
4417 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
4418 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
4419
4420 /******************* Bit definition for TIM_DIER register ******************/
4421 #define TIM_DIER_UIE_Pos (0U)
4422 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
4423 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
4424 #define TIM_DIER_CC1IE_Pos (1U)
4425 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
4426 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
4427 #define TIM_DIER_CC2IE_Pos (2U)
4428 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
4429 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
4430 #define TIM_DIER_CC3IE_Pos (3U)
4431 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
4432 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
4433 #define TIM_DIER_CC4IE_Pos (4U)
4434 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
4435 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
4436 #define TIM_DIER_COMIE_Pos (5U)
4437 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
4438 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
4439 #define TIM_DIER_TIE_Pos (6U)
4440 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
4441 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
4442 #define TIM_DIER_BIE_Pos (7U)
4443 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
4444 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
4445 #define TIM_DIER_UDE_Pos (8U)
4446 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
4447 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
4448 #define TIM_DIER_CC1DE_Pos (9U)
4449 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
4450 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
4451 #define TIM_DIER_CC2DE_Pos (10U)
4452 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
4453 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
4454 #define TIM_DIER_CC3DE_Pos (11U)
4455 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
4456 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
4457 #define TIM_DIER_CC4DE_Pos (12U)
4458 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
4459 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
4460 #define TIM_DIER_COMDE_Pos (13U)
4461 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
4462 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
4463 #define TIM_DIER_TDE_Pos (14U)
4464 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
4465 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
4466
4467 /******************** Bit definition for TIM_SR register *******************/
4468 #define TIM_SR_UIF_Pos (0U)
4469 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
4470 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
4471 #define TIM_SR_CC1IF_Pos (1U)
4472 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
4473 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
4474 #define TIM_SR_CC2IF_Pos (2U)
4475 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
4476 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
4477 #define TIM_SR_CC3IF_Pos (3U)
4478 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
4479 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
4480 #define TIM_SR_CC4IF_Pos (4U)
4481 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
4482 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
4483 #define TIM_SR_COMIF_Pos (5U)
4484 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
4485 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
4486 #define TIM_SR_TIF_Pos (6U)
4487 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
4488 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
4489 #define TIM_SR_BIF_Pos (7U)
4490 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
4491 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
4492 #define TIM_SR_CC1OF_Pos (9U)
4493 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
4494 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
4495 #define TIM_SR_CC2OF_Pos (10U)
4496 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
4497 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
4498 #define TIM_SR_CC3OF_Pos (11U)
4499 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
4500 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
4501 #define TIM_SR_CC4OF_Pos (12U)
4502 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
4503 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
4504
4505 /******************* Bit definition for TIM_EGR register *******************/
4506 #define TIM_EGR_UG_Pos (0U)
4507 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
4508 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
4509 #define TIM_EGR_CC1G_Pos (1U)
4510 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
4511 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
4512 #define TIM_EGR_CC2G_Pos (2U)
4513 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
4514 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
4515 #define TIM_EGR_CC3G_Pos (3U)
4516 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
4517 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
4518 #define TIM_EGR_CC4G_Pos (4U)
4519 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
4520 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
4521 #define TIM_EGR_COMG_Pos (5U)
4522 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
4523 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
4524 #define TIM_EGR_TG_Pos (6U)
4525 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
4526 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
4527 #define TIM_EGR_BG_Pos (7U)
4528 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
4529 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
4530
4531 /****************** Bit definition for TIM_CCMR1 register ******************/
4532 #define TIM_CCMR1_CC1S_Pos (0U)
4533 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
4534 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
4535 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
4536 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
4537
4538 #define TIM_CCMR1_OC1FE_Pos (2U)
4539 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
4540 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
4541 #define TIM_CCMR1_OC1PE_Pos (3U)
4542 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
4543 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
4544
4545 #define TIM_CCMR1_OC1M_Pos (4U)
4546 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
4547 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
4548 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
4549 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
4550 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
4551
4552 #define TIM_CCMR1_OC1CE_Pos (7U)
4553 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
4554 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
4555
4556 #define TIM_CCMR1_CC2S_Pos (8U)
4557 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
4558 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
4559 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
4560 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
4561
4562 #define TIM_CCMR1_OC2FE_Pos (10U)
4563 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
4564 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
4565 #define TIM_CCMR1_OC2PE_Pos (11U)
4566 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
4567 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
4568
4569 #define TIM_CCMR1_OC2M_Pos (12U)
4570 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
4571 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
4572 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
4573 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
4574 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
4575
4576 #define TIM_CCMR1_OC2CE_Pos (15U)
4577 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
4578 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
4579
4580 /*---------------------------------------------------------------------------*/
4581
4582 #define TIM_CCMR1_IC1PSC_Pos (2U)
4583 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
4584 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
4585 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
4586 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
4587
4588 #define TIM_CCMR1_IC1F_Pos (4U)
4589 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
4590 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
4591 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
4592 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
4593 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
4594 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
4595
4596 #define TIM_CCMR1_IC2PSC_Pos (10U)
4597 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
4598 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
4599 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
4600 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
4601
4602 #define TIM_CCMR1_IC2F_Pos (12U)
4603 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
4604 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
4605 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
4606 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
4607 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
4608 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
4609
4610 /****************** Bit definition for TIM_CCMR2 register ******************/
4611 #define TIM_CCMR2_CC3S_Pos (0U)
4612 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
4613 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4614 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
4615 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
4616
4617 #define TIM_CCMR2_OC3FE_Pos (2U)
4618 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
4619 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
4620 #define TIM_CCMR2_OC3PE_Pos (3U)
4621 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
4622 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
4623
4624 #define TIM_CCMR2_OC3M_Pos (4U)
4625 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
4626 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4627 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
4628 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
4629 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
4630
4631 #define TIM_CCMR2_OC3CE_Pos (7U)
4632 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
4633 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
4634
4635 #define TIM_CCMR2_CC4S_Pos (8U)
4636 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
4637 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4638 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
4639 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
4640
4641 #define TIM_CCMR2_OC4FE_Pos (10U)
4642 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
4643 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
4644 #define TIM_CCMR2_OC4PE_Pos (11U)
4645 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
4646 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
4647
4648 #define TIM_CCMR2_OC4M_Pos (12U)
4649 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
4650 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4651 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
4652 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
4653 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
4654
4655 #define TIM_CCMR2_OC4CE_Pos (15U)
4656 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
4657 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
4658
4659 /*---------------------------------------------------------------------------*/
4660
4661 #define TIM_CCMR2_IC3PSC_Pos (2U)
4662 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
4663 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4664 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
4665 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
4666
4667 #define TIM_CCMR2_IC3F_Pos (4U)
4668 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
4669 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4670 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
4671 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
4672 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
4673 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
4674
4675 #define TIM_CCMR2_IC4PSC_Pos (10U)
4676 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
4677 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4678 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
4679 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
4680
4681 #define TIM_CCMR2_IC4F_Pos (12U)
4682 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
4683 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4684 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
4685 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
4686 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
4687 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
4688
4689 /******************* Bit definition for TIM_CCER register ******************/
4690 #define TIM_CCER_CC1E_Pos (0U)
4691 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
4692 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
4693 #define TIM_CCER_CC1P_Pos (1U)
4694 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
4695 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
4696 #define TIM_CCER_CC1NE_Pos (2U)
4697 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
4698 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
4699 #define TIM_CCER_CC1NP_Pos (3U)
4700 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
4701 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
4702 #define TIM_CCER_CC2E_Pos (4U)
4703 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
4704 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
4705 #define TIM_CCER_CC2P_Pos (5U)
4706 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
4707 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
4708 #define TIM_CCER_CC2NE_Pos (6U)
4709 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
4710 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
4711 #define TIM_CCER_CC2NP_Pos (7U)
4712 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
4713 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
4714 #define TIM_CCER_CC3E_Pos (8U)
4715 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
4716 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
4717 #define TIM_CCER_CC3P_Pos (9U)
4718 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
4719 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
4720 #define TIM_CCER_CC3NE_Pos (10U)
4721 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
4722 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
4723 #define TIM_CCER_CC3NP_Pos (11U)
4724 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
4725 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
4726 #define TIM_CCER_CC4E_Pos (12U)
4727 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
4728 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
4729 #define TIM_CCER_CC4P_Pos (13U)
4730 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
4731 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
4732 #define TIM_CCER_CC4NP_Pos (15U)
4733 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
4734 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
4735
4736 /******************* Bit definition for TIM_CNT register *******************/
4737 #define TIM_CNT_CNT_Pos (0U)
4738 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
4739 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
4740
4741 /******************* Bit definition for TIM_PSC register *******************/
4742 #define TIM_PSC_PSC_Pos (0U)
4743 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
4744 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
4745
4746 /******************* Bit definition for TIM_ARR register *******************/
4747 #define TIM_ARR_ARR_Pos (0U)
4748 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
4749 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
4750
4751 /******************* Bit definition for TIM_RCR register *******************/
4752 #define TIM_RCR_REP_Pos (0U)
4753 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
4754 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
4755
4756 /******************* Bit definition for TIM_CCR1 register ******************/
4757 #define TIM_CCR1_CCR1_Pos (0U)
4758 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
4759 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
4760
4761 /******************* Bit definition for TIM_CCR2 register ******************/
4762 #define TIM_CCR2_CCR2_Pos (0U)
4763 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
4764 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
4765
4766 /******************* Bit definition for TIM_CCR3 register ******************/
4767 #define TIM_CCR3_CCR3_Pos (0U)
4768 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
4769 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
4770
4771 /******************* Bit definition for TIM_CCR4 register ******************/
4772 #define TIM_CCR4_CCR4_Pos (0U)
4773 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
4774 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
4775
4776 /******************* Bit definition for TIM_BDTR register ******************/
4777 #define TIM_BDTR_DTG_Pos (0U)
4778 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
4779 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
4780 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
4781 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
4782 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
4783 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
4784 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
4785 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
4786 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
4787 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
4788
4789 #define TIM_BDTR_LOCK_Pos (8U)
4790 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
4791 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
4792 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
4793 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
4794
4795 #define TIM_BDTR_OSSI_Pos (10U)
4796 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
4797 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
4798 #define TIM_BDTR_OSSR_Pos (11U)
4799 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
4800 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
4801 #define TIM_BDTR_BKE_Pos (12U)
4802 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
4803 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
4804 #define TIM_BDTR_BKP_Pos (13U)
4805 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
4806 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
4807 #define TIM_BDTR_AOE_Pos (14U)
4808 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
4809 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
4810 #define TIM_BDTR_MOE_Pos (15U)
4811 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
4812 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
4813
4814 /******************* Bit definition for TIM_DCR register *******************/
4815 #define TIM_DCR_DBA_Pos (0U)
4816 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
4817 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
4818 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
4819 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
4820 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
4821 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
4822 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
4823
4824 #define TIM_DCR_DBL_Pos (8U)
4825 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
4826 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
4827 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
4828 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
4829 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
4830 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
4831 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
4832
4833 /******************* Bit definition for TIM_DMAR register ******************/
4834 #define TIM_DMAR_DMAB_Pos (0U)
4835 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
4836 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
4837
4838 /******************* Bit definition for TIM_OR register ********************/
4839
4840 /******************************************************************************/
4841 /* */
4842 /* Real-Time Clock */
4843 /* */
4844 /******************************************************************************/
4845
4846 /******************* Bit definition for RTC_CRH register ********************/
4847 #define RTC_CRH_SECIE_Pos (0U)
4848 #define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
4849 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
4850 #define RTC_CRH_ALRIE_Pos (1U)
4851 #define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
4852 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
4853 #define RTC_CRH_OWIE_Pos (2U)
4854 #define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
4855 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
4856
4857 /******************* Bit definition for RTC_CRL register ********************/
4858 #define RTC_CRL_SECF_Pos (0U)
4859 #define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
4860 #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
4861 #define RTC_CRL_ALRF_Pos (1U)
4862 #define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
4863 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
4864 #define RTC_CRL_OWF_Pos (2U)
4865 #define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
4866 #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
4867 #define RTC_CRL_RSF_Pos (3U)
4868 #define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
4869 #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
4870 #define RTC_CRL_CNF_Pos (4U)
4871 #define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
4872 #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
4873 #define RTC_CRL_RTOFF_Pos (5U)
4874 #define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
4875 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
4876
4877 /******************* Bit definition for RTC_PRLH register *******************/
4878 #define RTC_PRLH_PRL_Pos (0U)
4879 #define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
4880 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
4881
4882 /******************* Bit definition for RTC_PRLL register *******************/
4883 #define RTC_PRLL_PRL_Pos (0U)
4884 #define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
4885 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
4886
4887 /******************* Bit definition for RTC_DIVH register *******************/
4888 #define RTC_DIVH_RTC_DIV_Pos (0U)
4889 #define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
4890 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
4891
4892 /******************* Bit definition for RTC_DIVL register *******************/
4893 #define RTC_DIVL_RTC_DIV_Pos (0U)
4894 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
4895 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
4896
4897 /******************* Bit definition for RTC_CNTH register *******************/
4898 #define RTC_CNTH_RTC_CNT_Pos (0U)
4899 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
4900 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
4901
4902 /******************* Bit definition for RTC_CNTL register *******************/
4903 #define RTC_CNTL_RTC_CNT_Pos (0U)
4904 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
4905 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
4906
4907 /******************* Bit definition for RTC_ALRH register *******************/
4908 #define RTC_ALRH_RTC_ALR_Pos (0U)
4909 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
4910 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
4911
4912 /******************* Bit definition for RTC_ALRL register *******************/
4913 #define RTC_ALRL_RTC_ALR_Pos (0U)
4914 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
4915 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
4916
4917 /******************************************************************************/
4918 /* */
4919 /* Independent WATCHDOG (IWDG) */
4920 /* */
4921 /******************************************************************************/
4922
4923 /******************* Bit definition for IWDG_KR register ********************/
4924 #define IWDG_KR_KEY_Pos (0U)
4925 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
4926 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
4927
4928 /******************* Bit definition for IWDG_PR register ********************/
4929 #define IWDG_PR_PR_Pos (0U)
4930 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
4931 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
4932 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
4933 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
4934 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
4935
4936 /******************* Bit definition for IWDG_RLR register *******************/
4937 #define IWDG_RLR_RL_Pos (0U)
4938 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
4939 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
4940
4941 /******************* Bit definition for IWDG_SR register ********************/
4942 #define IWDG_SR_PVU_Pos (0U)
4943 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
4944 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
4945 #define IWDG_SR_RVU_Pos (1U)
4946 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
4947 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
4948
4949 /******************************************************************************/
4950 /* */
4951 /* Window WATCHDOG (WWDG) */
4952 /* */
4953 /******************************************************************************/
4954
4955 /******************* Bit definition for WWDG_CR register ********************/
4956 #define WWDG_CR_T_Pos (0U)
4957 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
4958 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
4959 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
4960 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
4961 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
4962 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
4963 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
4964 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
4965 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
4966
4967 /* Legacy defines */
4968 #define WWDG_CR_T0 WWDG_CR_T_0
4969 #define WWDG_CR_T1 WWDG_CR_T_1
4970 #define WWDG_CR_T2 WWDG_CR_T_2
4971 #define WWDG_CR_T3 WWDG_CR_T_3
4972 #define WWDG_CR_T4 WWDG_CR_T_4
4973 #define WWDG_CR_T5 WWDG_CR_T_5
4974 #define WWDG_CR_T6 WWDG_CR_T_6
4975
4976 #define WWDG_CR_WDGA_Pos (7U)
4977 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
4978 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
4979
4980 /******************* Bit definition for WWDG_CFR register *******************/
4981 #define WWDG_CFR_W_Pos (0U)
4982 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
4983 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
4984 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
4985 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
4986 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
4987 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
4988 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
4989 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
4990 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
4991
4992 /* Legacy defines */
4993 #define WWDG_CFR_W0 WWDG_CFR_W_0
4994 #define WWDG_CFR_W1 WWDG_CFR_W_1
4995 #define WWDG_CFR_W2 WWDG_CFR_W_2
4996 #define WWDG_CFR_W3 WWDG_CFR_W_3
4997 #define WWDG_CFR_W4 WWDG_CFR_W_4
4998 #define WWDG_CFR_W5 WWDG_CFR_W_5
4999 #define WWDG_CFR_W6 WWDG_CFR_W_6
5000
5001 #define WWDG_CFR_WDGTB_Pos (7U)
5002 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
5003 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
5004 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
5005 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
5006
5007 /* Legacy defines */
5008 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
5009 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
5010
5011 #define WWDG_CFR_EWI_Pos (9U)
5012 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
5013 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
5014
5015 /******************* Bit definition for WWDG_SR register ********************/
5016 #define WWDG_SR_EWIF_Pos (0U)
5017 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
5018 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
5019
5020
5021 /******************************************************************************/
5022 /* */
5023 /* SD host Interface */
5024 /* */
5025 /******************************************************************************/
5026
5027 /****************** Bit definition for SDIO_POWER register ******************/
5028 #define SDIO_POWER_PWRCTRL_Pos (0U)
5029 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
5030 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
5031 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
5032 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
5033
5034 /****************** Bit definition for SDIO_CLKCR register ******************/
5035 #define SDIO_CLKCR_CLKDIV_Pos (0U)
5036 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
5037 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
5038 #define SDIO_CLKCR_CLKEN_Pos (8U)
5039 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
5040 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
5041 #define SDIO_CLKCR_PWRSAV_Pos (9U)
5042 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
5043 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
5044 #define SDIO_CLKCR_BYPASS_Pos (10U)
5045 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
5046 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
5047
5048 #define SDIO_CLKCR_WIDBUS_Pos (11U)
5049 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
5050 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
5051 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
5052 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
5053
5054 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
5055 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
5056 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
5057 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
5058 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
5059 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
5060
5061 /******************* Bit definition for SDIO_ARG register *******************/
5062 #define SDIO_ARG_CMDARG_Pos (0U)
5063 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
5064 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
5065
5066 /******************* Bit definition for SDIO_CMD register *******************/
5067 #define SDIO_CMD_CMDINDEX_Pos (0U)
5068 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
5069 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
5070
5071 #define SDIO_CMD_WAITRESP_Pos (6U)
5072 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
5073 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
5074 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
5075 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
5076
5077 #define SDIO_CMD_WAITINT_Pos (8U)
5078 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
5079 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
5080 #define SDIO_CMD_WAITPEND_Pos (9U)
5081 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
5082 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
5083 #define SDIO_CMD_CPSMEN_Pos (10U)
5084 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
5085 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
5086 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
5087 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
5088 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
5089 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
5090 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
5091 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
5092 #define SDIO_CMD_NIEN_Pos (13U)
5093 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
5094 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
5095 #define SDIO_CMD_CEATACMD_Pos (14U)
5096 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
5097 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
5098
5099 /***************** Bit definition for SDIO_RESPCMD register *****************/
5100 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
5101 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
5102 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
5103
5104 /****************** Bit definition for SDIO_RESP0 register ******************/
5105 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
5106 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
5107 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
5108
5109 /****************** Bit definition for SDIO_RESP1 register ******************/
5110 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
5111 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
5112 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
5113
5114 /****************** Bit definition for SDIO_RESP2 register ******************/
5115 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
5116 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
5117 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
5118
5119 /****************** Bit definition for SDIO_RESP3 register ******************/
5120 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
5121 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
5122 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
5123
5124 /****************** Bit definition for SDIO_RESP4 register ******************/
5125 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
5126 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
5127 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
5128
5129 /****************** Bit definition for SDIO_DTIMER register *****************/
5130 #define SDIO_DTIMER_DATATIME_Pos (0U)
5131 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
5132 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
5133
5134 /****************** Bit definition for SDIO_DLEN register *******************/
5135 #define SDIO_DLEN_DATALENGTH_Pos (0U)
5136 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
5137 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
5138
5139 /****************** Bit definition for SDIO_DCTRL register ******************/
5140 #define SDIO_DCTRL_DTEN_Pos (0U)
5141 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
5142 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
5143 #define SDIO_DCTRL_DTDIR_Pos (1U)
5144 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
5145 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
5146 #define SDIO_DCTRL_DTMODE_Pos (2U)
5147 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
5148 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
5149 #define SDIO_DCTRL_DMAEN_Pos (3U)
5150 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
5151 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
5152
5153 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
5154 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
5155 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
5156 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
5157 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
5158 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
5159 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
5160
5161 #define SDIO_DCTRL_RWSTART_Pos (8U)
5162 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
5163 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
5164 #define SDIO_DCTRL_RWSTOP_Pos (9U)
5165 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
5166 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
5167 #define SDIO_DCTRL_RWMOD_Pos (10U)
5168 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
5169 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
5170 #define SDIO_DCTRL_SDIOEN_Pos (11U)
5171 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
5172 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
5173
5174 /****************** Bit definition for SDIO_DCOUNT register *****************/
5175 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
5176 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
5177 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
5178
5179 /****************** Bit definition for SDIO_STA register ********************/
5180 #define SDIO_STA_CCRCFAIL_Pos (0U)
5181 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
5182 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
5183 #define SDIO_STA_DCRCFAIL_Pos (1U)
5184 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
5185 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
5186 #define SDIO_STA_CTIMEOUT_Pos (2U)
5187 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
5188 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
5189 #define SDIO_STA_DTIMEOUT_Pos (3U)
5190 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
5191 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
5192 #define SDIO_STA_TXUNDERR_Pos (4U)
5193 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
5194 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
5195 #define SDIO_STA_RXOVERR_Pos (5U)
5196 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
5197 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
5198 #define SDIO_STA_CMDREND_Pos (6U)
5199 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
5200 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
5201 #define SDIO_STA_CMDSENT_Pos (7U)
5202 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
5203 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
5204 #define SDIO_STA_DATAEND_Pos (8U)
5205 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
5206 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
5207 #define SDIO_STA_STBITERR_Pos (9U)
5208 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
5209 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
5210 #define SDIO_STA_DBCKEND_Pos (10U)
5211 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
5212 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
5213 #define SDIO_STA_CMDACT_Pos (11U)
5214 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
5215 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
5216 #define SDIO_STA_TXACT_Pos (12U)
5217 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
5218 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
5219 #define SDIO_STA_RXACT_Pos (13U)
5220 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
5221 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
5222 #define SDIO_STA_TXFIFOHE_Pos (14U)
5223 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
5224 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5225 #define SDIO_STA_RXFIFOHF_Pos (15U)
5226 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
5227 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
5228 #define SDIO_STA_TXFIFOF_Pos (16U)
5229 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
5230 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
5231 #define SDIO_STA_RXFIFOF_Pos (17U)
5232 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
5233 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
5234 #define SDIO_STA_TXFIFOE_Pos (18U)
5235 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
5236 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
5237 #define SDIO_STA_RXFIFOE_Pos (19U)
5238 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
5239 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
5240 #define SDIO_STA_TXDAVL_Pos (20U)
5241 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
5242 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
5243 #define SDIO_STA_RXDAVL_Pos (21U)
5244 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
5245 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
5246 #define SDIO_STA_SDIOIT_Pos (22U)
5247 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
5248 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
5249 #define SDIO_STA_CEATAEND_Pos (23U)
5250 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
5251 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
5252
5253 /******************* Bit definition for SDIO_ICR register *******************/
5254 #define SDIO_ICR_CCRCFAILC_Pos (0U)
5255 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
5256 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
5257 #define SDIO_ICR_DCRCFAILC_Pos (1U)
5258 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
5259 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
5260 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
5261 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
5262 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
5263 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
5264 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
5265 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
5266 #define SDIO_ICR_TXUNDERRC_Pos (4U)
5267 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
5268 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
5269 #define SDIO_ICR_RXOVERRC_Pos (5U)
5270 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
5271 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
5272 #define SDIO_ICR_CMDRENDC_Pos (6U)
5273 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
5274 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
5275 #define SDIO_ICR_CMDSENTC_Pos (7U)
5276 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
5277 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
5278 #define SDIO_ICR_DATAENDC_Pos (8U)
5279 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
5280 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
5281 #define SDIO_ICR_STBITERRC_Pos (9U)
5282 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
5283 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
5284 #define SDIO_ICR_DBCKENDC_Pos (10U)
5285 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
5286 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
5287 #define SDIO_ICR_SDIOITC_Pos (22U)
5288 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
5289 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
5290 #define SDIO_ICR_CEATAENDC_Pos (23U)
5291 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
5292 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
5293
5294 /****************** Bit definition for SDIO_MASK register *******************/
5295 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
5296 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
5297 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
5298 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
5299 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
5300 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
5301 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
5302 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
5303 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
5304 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
5305 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
5306 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
5307 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
5308 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
5309 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
5310 #define SDIO_MASK_RXOVERRIE_Pos (5U)
5311 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
5312 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
5313 #define SDIO_MASK_CMDRENDIE_Pos (6U)
5314 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
5315 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
5316 #define SDIO_MASK_CMDSENTIE_Pos (7U)
5317 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
5318 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
5319 #define SDIO_MASK_DATAENDIE_Pos (8U)
5320 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
5321 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
5322 #define SDIO_MASK_STBITERRIE_Pos (9U)
5323 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
5324 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
5325 #define SDIO_MASK_DBCKENDIE_Pos (10U)
5326 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
5327 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
5328 #define SDIO_MASK_CMDACTIE_Pos (11U)
5329 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
5330 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
5331 #define SDIO_MASK_TXACTIE_Pos (12U)
5332 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
5333 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
5334 #define SDIO_MASK_RXACTIE_Pos (13U)
5335 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
5336 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
5337 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
5338 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
5339 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
5340 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
5341 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
5342 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
5343 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
5344 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
5345 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
5346 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
5347 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
5348 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
5349 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
5350 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
5351 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
5352 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
5353 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
5354 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
5355 #define SDIO_MASK_TXDAVLIE_Pos (20U)
5356 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
5357 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
5358 #define SDIO_MASK_RXDAVLIE_Pos (21U)
5359 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
5360 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
5361 #define SDIO_MASK_SDIOITIE_Pos (22U)
5362 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
5363 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
5364 #define SDIO_MASK_CEATAENDIE_Pos (23U)
5365 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
5366 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
5367
5368 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5369 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
5370 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
5371 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
5372
5373 /****************** Bit definition for SDIO_FIFO register *******************/
5374 #define SDIO_FIFO_FIFODATA_Pos (0U)
5375 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
5376 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
5377
5378 /******************************************************************************/
5379 /* */
5380 /* USB Device FS */
5381 /* */
5382 /******************************************************************************/
5383
5384 /*!< Endpoint-specific registers */
5385 #define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
5386 #define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
5387 #define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
5388 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
5389 #define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
5390 #define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
5391 #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
5392 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
5393
5394 /* bit positions */
5395 #define USB_EP_CTR_RX_Pos (15U)
5396 #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
5397 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
5398 #define USB_EP_DTOG_RX_Pos (14U)
5399 #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
5400 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
5401 #define USB_EPRX_STAT_Pos (12U)
5402 #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
5403 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
5404 #define USB_EP_SETUP_Pos (11U)
5405 #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
5406 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
5407 #define USB_EP_T_FIELD_Pos (9U)
5408 #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
5409 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
5410 #define USB_EP_KIND_Pos (8U)
5411 #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
5412 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
5413 #define USB_EP_CTR_TX_Pos (7U)
5414 #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
5415 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
5416 #define USB_EP_DTOG_TX_Pos (6U)
5417 #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
5418 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
5419 #define USB_EPTX_STAT_Pos (4U)
5420 #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
5421 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
5422 #define USB_EPADDR_FIELD_Pos (0U)
5423 #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
5424 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
5425
5426 /* EndPoint REGister MASK (no toggle fields) */
5427 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
5428 /*!< EP_TYPE[1:0] EndPoint TYPE */
5429 #define USB_EP_TYPE_MASK_Pos (9U)
5430 #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
5431 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
5432 #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
5433 #define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
5434 #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
5435 #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
5436 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
5437
5438 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
5439 /*!< STAT_TX[1:0] STATus for TX transfer */
5440 #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
5441 #define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
5442 #define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
5443 #define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
5444 #define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
5445 #define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
5446 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
5447 /*!< STAT_RX[1:0] STATus for RX transfer */
5448 #define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
5449 #define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
5450 #define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
5451 #define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
5452 #define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
5453 #define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
5454 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
5455
5456 /******************* Bit definition for USB_EP0R register *******************/
5457 #define USB_EP0R_EA_Pos (0U)
5458 #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
5459 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
5460
5461 #define USB_EP0R_STAT_TX_Pos (4U)
5462 #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
5463 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5464 #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
5465 #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
5466
5467 #define USB_EP0R_DTOG_TX_Pos (6U)
5468 #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
5469 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
5470 #define USB_EP0R_CTR_TX_Pos (7U)
5471 #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
5472 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
5473 #define USB_EP0R_EP_KIND_Pos (8U)
5474 #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
5475 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
5476
5477 #define USB_EP0R_EP_TYPE_Pos (9U)
5478 #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
5479 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
5480 #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
5481 #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
5482
5483 #define USB_EP0R_SETUP_Pos (11U)
5484 #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
5485 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
5486
5487 #define USB_EP0R_STAT_RX_Pos (12U)
5488 #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
5489 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
5490 #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
5491 #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
5492
5493 #define USB_EP0R_DTOG_RX_Pos (14U)
5494 #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
5495 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
5496 #define USB_EP0R_CTR_RX_Pos (15U)
5497 #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
5498 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
5499
5500 /******************* Bit definition for USB_EP1R register *******************/
5501 #define USB_EP1R_EA_Pos (0U)
5502 #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
5503 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
5504
5505 #define USB_EP1R_STAT_TX_Pos (4U)
5506 #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
5507 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5508 #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
5509 #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
5510
5511 #define USB_EP1R_DTOG_TX_Pos (6U)
5512 #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
5513 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
5514 #define USB_EP1R_CTR_TX_Pos (7U)
5515 #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
5516 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
5517 #define USB_EP1R_EP_KIND_Pos (8U)
5518 #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
5519 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
5520
5521 #define USB_EP1R_EP_TYPE_Pos (9U)
5522 #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
5523 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
5524 #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
5525 #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
5526
5527 #define USB_EP1R_SETUP_Pos (11U)
5528 #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
5529 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
5530
5531 #define USB_EP1R_STAT_RX_Pos (12U)
5532 #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
5533 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
5534 #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
5535 #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
5536
5537 #define USB_EP1R_DTOG_RX_Pos (14U)
5538 #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
5539 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
5540 #define USB_EP1R_CTR_RX_Pos (15U)
5541 #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
5542 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
5543
5544 /******************* Bit definition for USB_EP2R register *******************/
5545 #define USB_EP2R_EA_Pos (0U)
5546 #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
5547 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
5548
5549 #define USB_EP2R_STAT_TX_Pos (4U)
5550 #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
5551 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5552 #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
5553 #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
5554
5555 #define USB_EP2R_DTOG_TX_Pos (6U)
5556 #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
5557 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
5558 #define USB_EP2R_CTR_TX_Pos (7U)
5559 #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
5560 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
5561 #define USB_EP2R_EP_KIND_Pos (8U)
5562 #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
5563 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
5564
5565 #define USB_EP2R_EP_TYPE_Pos (9U)
5566 #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
5567 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
5568 #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
5569 #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
5570
5571 #define USB_EP2R_SETUP_Pos (11U)
5572 #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
5573 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
5574
5575 #define USB_EP2R_STAT_RX_Pos (12U)
5576 #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
5577 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
5578 #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
5579 #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
5580
5581 #define USB_EP2R_DTOG_RX_Pos (14U)
5582 #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
5583 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
5584 #define USB_EP2R_CTR_RX_Pos (15U)
5585 #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
5586 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
5587
5588 /******************* Bit definition for USB_EP3R register *******************/
5589 #define USB_EP3R_EA_Pos (0U)
5590 #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
5591 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
5592
5593 #define USB_EP3R_STAT_TX_Pos (4U)
5594 #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
5595 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5596 #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
5597 #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
5598
5599 #define USB_EP3R_DTOG_TX_Pos (6U)
5600 #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
5601 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
5602 #define USB_EP3R_CTR_TX_Pos (7U)
5603 #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
5604 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
5605 #define USB_EP3R_EP_KIND_Pos (8U)
5606 #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
5607 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
5608
5609 #define USB_EP3R_EP_TYPE_Pos (9U)
5610 #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
5611 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
5612 #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
5613 #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
5614
5615 #define USB_EP3R_SETUP_Pos (11U)
5616 #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
5617 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
5618
5619 #define USB_EP3R_STAT_RX_Pos (12U)
5620 #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
5621 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
5622 #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
5623 #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
5624
5625 #define USB_EP3R_DTOG_RX_Pos (14U)
5626 #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
5627 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
5628 #define USB_EP3R_CTR_RX_Pos (15U)
5629 #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
5630 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
5631
5632 /******************* Bit definition for USB_EP4R register *******************/
5633 #define USB_EP4R_EA_Pos (0U)
5634 #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
5635 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
5636
5637 #define USB_EP4R_STAT_TX_Pos (4U)
5638 #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
5639 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5640 #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
5641 #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
5642
5643 #define USB_EP4R_DTOG_TX_Pos (6U)
5644 #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
5645 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
5646 #define USB_EP4R_CTR_TX_Pos (7U)
5647 #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
5648 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
5649 #define USB_EP4R_EP_KIND_Pos (8U)
5650 #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
5651 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
5652
5653 #define USB_EP4R_EP_TYPE_Pos (9U)
5654 #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
5655 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
5656 #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
5657 #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
5658
5659 #define USB_EP4R_SETUP_Pos (11U)
5660 #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
5661 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
5662
5663 #define USB_EP4R_STAT_RX_Pos (12U)
5664 #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
5665 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
5666 #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
5667 #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
5668
5669 #define USB_EP4R_DTOG_RX_Pos (14U)
5670 #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
5671 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
5672 #define USB_EP4R_CTR_RX_Pos (15U)
5673 #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
5674 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
5675
5676 /******************* Bit definition for USB_EP5R register *******************/
5677 #define USB_EP5R_EA_Pos (0U)
5678 #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
5679 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
5680
5681 #define USB_EP5R_STAT_TX_Pos (4U)
5682 #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
5683 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5684 #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
5685 #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
5686
5687 #define USB_EP5R_DTOG_TX_Pos (6U)
5688 #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
5689 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
5690 #define USB_EP5R_CTR_TX_Pos (7U)
5691 #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
5692 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
5693 #define USB_EP5R_EP_KIND_Pos (8U)
5694 #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
5695 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
5696
5697 #define USB_EP5R_EP_TYPE_Pos (9U)
5698 #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
5699 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
5700 #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
5701 #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
5702
5703 #define USB_EP5R_SETUP_Pos (11U)
5704 #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
5705 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
5706
5707 #define USB_EP5R_STAT_RX_Pos (12U)
5708 #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
5709 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
5710 #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
5711 #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
5712
5713 #define USB_EP5R_DTOG_RX_Pos (14U)
5714 #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
5715 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
5716 #define USB_EP5R_CTR_RX_Pos (15U)
5717 #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
5718 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
5719
5720 /******************* Bit definition for USB_EP6R register *******************/
5721 #define USB_EP6R_EA_Pos (0U)
5722 #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
5723 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
5724
5725 #define USB_EP6R_STAT_TX_Pos (4U)
5726 #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
5727 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5728 #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
5729 #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
5730
5731 #define USB_EP6R_DTOG_TX_Pos (6U)
5732 #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
5733 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
5734 #define USB_EP6R_CTR_TX_Pos (7U)
5735 #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
5736 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
5737 #define USB_EP6R_EP_KIND_Pos (8U)
5738 #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
5739 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
5740
5741 #define USB_EP6R_EP_TYPE_Pos (9U)
5742 #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
5743 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
5744 #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
5745 #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
5746
5747 #define USB_EP6R_SETUP_Pos (11U)
5748 #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
5749 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
5750
5751 #define USB_EP6R_STAT_RX_Pos (12U)
5752 #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
5753 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
5754 #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
5755 #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
5756
5757 #define USB_EP6R_DTOG_RX_Pos (14U)
5758 #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
5759 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
5760 #define USB_EP6R_CTR_RX_Pos (15U)
5761 #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
5762 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
5763
5764 /******************* Bit definition for USB_EP7R register *******************/
5765 #define USB_EP7R_EA_Pos (0U)
5766 #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
5767 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
5768
5769 #define USB_EP7R_STAT_TX_Pos (4U)
5770 #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
5771 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5772 #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
5773 #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
5774
5775 #define USB_EP7R_DTOG_TX_Pos (6U)
5776 #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
5777 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
5778 #define USB_EP7R_CTR_TX_Pos (7U)
5779 #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
5780 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
5781 #define USB_EP7R_EP_KIND_Pos (8U)
5782 #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
5783 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
5784
5785 #define USB_EP7R_EP_TYPE_Pos (9U)
5786 #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
5787 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
5788 #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
5789 #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
5790
5791 #define USB_EP7R_SETUP_Pos (11U)
5792 #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
5793 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
5794
5795 #define USB_EP7R_STAT_RX_Pos (12U)
5796 #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
5797 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
5798 #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
5799 #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
5800
5801 #define USB_EP7R_DTOG_RX_Pos (14U)
5802 #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
5803 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
5804 #define USB_EP7R_CTR_RX_Pos (15U)
5805 #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
5806 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
5807
5808 /*!< Common registers */
5809 /******************* Bit definition for USB_CNTR register *******************/
5810 #define USB_CNTR_FRES_Pos (0U)
5811 #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
5812 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
5813 #define USB_CNTR_PDWN_Pos (1U)
5814 #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
5815 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
5816 #define USB_CNTR_LP_MODE_Pos (2U)
5817 #define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
5818 #define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
5819 #define USB_CNTR_FSUSP_Pos (3U)
5820 #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
5821 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
5822 #define USB_CNTR_RESUME_Pos (4U)
5823 #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
5824 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
5825 #define USB_CNTR_ESOFM_Pos (8U)
5826 #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
5827 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
5828 #define USB_CNTR_SOFM_Pos (9U)
5829 #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
5830 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
5831 #define USB_CNTR_RESETM_Pos (10U)
5832 #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
5833 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
5834 #define USB_CNTR_SUSPM_Pos (11U)
5835 #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
5836 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
5837 #define USB_CNTR_WKUPM_Pos (12U)
5838 #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
5839 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
5840 #define USB_CNTR_ERRM_Pos (13U)
5841 #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
5842 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
5843 #define USB_CNTR_PMAOVRM_Pos (14U)
5844 #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
5845 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
5846 #define USB_CNTR_CTRM_Pos (15U)
5847 #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
5848 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
5849
5850 /******************* Bit definition for USB_ISTR register *******************/
5851 #define USB_ISTR_EP_ID_Pos (0U)
5852 #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
5853 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
5854 #define USB_ISTR_DIR_Pos (4U)
5855 #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
5856 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
5857 #define USB_ISTR_ESOF_Pos (8U)
5858 #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
5859 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
5860 #define USB_ISTR_SOF_Pos (9U)
5861 #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
5862 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
5863 #define USB_ISTR_RESET_Pos (10U)
5864 #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
5865 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
5866 #define USB_ISTR_SUSP_Pos (11U)
5867 #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
5868 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
5869 #define USB_ISTR_WKUP_Pos (12U)
5870 #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
5871 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
5872 #define USB_ISTR_ERR_Pos (13U)
5873 #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
5874 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
5875 #define USB_ISTR_PMAOVR_Pos (14U)
5876 #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
5877 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
5878 #define USB_ISTR_CTR_Pos (15U)
5879 #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
5880 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
5881
5882 /******************* Bit definition for USB_FNR register ********************/
5883 #define USB_FNR_FN_Pos (0U)
5884 #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
5885 #define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
5886 #define USB_FNR_LSOF_Pos (11U)
5887 #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
5888 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
5889 #define USB_FNR_LCK_Pos (13U)
5890 #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
5891 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
5892 #define USB_FNR_RXDM_Pos (14U)
5893 #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
5894 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
5895 #define USB_FNR_RXDP_Pos (15U)
5896 #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
5897 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
5898
5899 /****************** Bit definition for USB_DADDR register *******************/
5900 #define USB_DADDR_ADD_Pos (0U)
5901 #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
5902 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
5903 #define USB_DADDR_ADD0_Pos (0U)
5904 #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
5905 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
5906 #define USB_DADDR_ADD1_Pos (1U)
5907 #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
5908 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
5909 #define USB_DADDR_ADD2_Pos (2U)
5910 #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
5911 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
5912 #define USB_DADDR_ADD3_Pos (3U)
5913 #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
5914 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
5915 #define USB_DADDR_ADD4_Pos (4U)
5916 #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
5917 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
5918 #define USB_DADDR_ADD5_Pos (5U)
5919 #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
5920 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
5921 #define USB_DADDR_ADD6_Pos (6U)
5922 #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
5923 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
5924
5925 #define USB_DADDR_EF_Pos (7U)
5926 #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
5927 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
5928
5929 /****************** Bit definition for USB_BTABLE register ******************/
5930 #define USB_BTABLE_BTABLE_Pos (3U)
5931 #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
5932 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
5933
5934 /*!< Buffer descriptor table */
5935 /***************** Bit definition for USB_ADDR0_TX register *****************/
5936 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
5937 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
5938 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
5939
5940 /***************** Bit definition for USB_ADDR1_TX register *****************/
5941 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
5942 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
5943 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
5944
5945 /***************** Bit definition for USB_ADDR2_TX register *****************/
5946 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
5947 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
5948 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
5949
5950 /***************** Bit definition for USB_ADDR3_TX register *****************/
5951 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
5952 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
5953 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
5954
5955 /***************** Bit definition for USB_ADDR4_TX register *****************/
5956 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
5957 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
5958 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
5959
5960 /***************** Bit definition for USB_ADDR5_TX register *****************/
5961 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
5962 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
5963 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
5964
5965 /***************** Bit definition for USB_ADDR6_TX register *****************/
5966 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
5967 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
5968 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
5969
5970 /***************** Bit definition for USB_ADDR7_TX register *****************/
5971 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
5972 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
5973 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
5974
5975 /*----------------------------------------------------------------------------*/
5976
5977 /***************** Bit definition for USB_COUNT0_TX register ****************/
5978 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
5979 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
5980 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
5981
5982 /***************** Bit definition for USB_COUNT1_TX register ****************/
5983 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
5984 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
5985 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
5986
5987 /***************** Bit definition for USB_COUNT2_TX register ****************/
5988 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
5989 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
5990 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
5991
5992 /***************** Bit definition for USB_COUNT3_TX register ****************/
5993 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
5994 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
5995 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
5996
5997 /***************** Bit definition for USB_COUNT4_TX register ****************/
5998 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
5999 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
6000 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
6001
6002 /***************** Bit definition for USB_COUNT5_TX register ****************/
6003 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
6004 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
6005 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
6006
6007 /***************** Bit definition for USB_COUNT6_TX register ****************/
6008 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
6009 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
6010 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
6011
6012 /***************** Bit definition for USB_COUNT7_TX register ****************/
6013 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
6014 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
6015 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
6016
6017 /*----------------------------------------------------------------------------*/
6018
6019 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
6020 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
6021
6022 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
6023 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
6024
6025 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
6026 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
6027
6028 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
6029 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
6030
6031 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
6032 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
6033
6034 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
6035 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
6036
6037 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
6038 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
6039
6040 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
6041 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
6042
6043 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
6044 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
6045
6046 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
6047 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
6048
6049 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
6050 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
6051
6052 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
6053 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
6054
6055 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
6056 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
6057
6058 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
6059 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
6060
6061 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
6062 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
6063
6064 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
6065 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
6066
6067 /*----------------------------------------------------------------------------*/
6068
6069 /***************** Bit definition for USB_ADDR0_RX register *****************/
6070 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
6071 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
6072 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
6073
6074 /***************** Bit definition for USB_ADDR1_RX register *****************/
6075 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
6076 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
6077 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
6078
6079 /***************** Bit definition for USB_ADDR2_RX register *****************/
6080 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
6081 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
6082 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
6083
6084 /***************** Bit definition for USB_ADDR3_RX register *****************/
6085 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
6086 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
6087 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
6088
6089 /***************** Bit definition for USB_ADDR4_RX register *****************/
6090 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
6091 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
6092 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
6093
6094 /***************** Bit definition for USB_ADDR5_RX register *****************/
6095 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
6096 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
6097 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
6098
6099 /***************** Bit definition for USB_ADDR6_RX register *****************/
6100 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
6101 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
6102 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
6103
6104 /***************** Bit definition for USB_ADDR7_RX register *****************/
6105 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
6106 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
6107 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
6108
6109 /*----------------------------------------------------------------------------*/
6110
6111 /***************** Bit definition for USB_COUNT0_RX register ****************/
6112 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
6113 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
6114 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
6115
6116 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
6117 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6118 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6119 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6120 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6121 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6122 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6123 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6124
6125 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
6126 #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
6127 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
6128
6129 /***************** Bit definition for USB_COUNT1_RX register ****************/
6130 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
6131 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
6132 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
6133
6134 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
6135 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6136 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6137 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6138 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6139 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6140 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6141 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6142
6143 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
6144 #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
6145 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
6146
6147 /***************** Bit definition for USB_COUNT2_RX register ****************/
6148 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
6149 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
6150 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
6151
6152 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
6153 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6154 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6155 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6156 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6157 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6158 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6159 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6160
6161 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
6162 #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
6163 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
6164
6165 /***************** Bit definition for USB_COUNT3_RX register ****************/
6166 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
6167 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
6168 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
6169
6170 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
6171 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6172 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6173 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6174 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6175 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6176 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6177 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6178
6179 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
6180 #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
6181 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
6182
6183 /***************** Bit definition for USB_COUNT4_RX register ****************/
6184 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
6185 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
6186 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
6187
6188 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
6189 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6190 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6191 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6192 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6193 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6194 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6195 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6196
6197 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
6198 #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
6199 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
6200
6201 /***************** Bit definition for USB_COUNT5_RX register ****************/
6202 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
6203 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
6204 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
6205
6206 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
6207 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6208 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6209 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6210 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6211 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6212 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6213 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6214
6215 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
6216 #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
6217 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
6218
6219 /***************** Bit definition for USB_COUNT6_RX register ****************/
6220 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
6221 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
6222 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
6223
6224 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
6225 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6226 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6227 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6228 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6229 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6230 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6231 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6232
6233 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
6234 #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
6235 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
6236
6237 /***************** Bit definition for USB_COUNT7_RX register ****************/
6238 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
6239 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
6240 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
6241
6242 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
6243 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6244 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6245 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6246 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6247 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6248 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6249 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6250
6251 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
6252 #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
6253 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
6254
6255 /*----------------------------------------------------------------------------*/
6256
6257 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
6258 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
6259
6260 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6261 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
6262 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
6263 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
6264 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
6265 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
6266
6267 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
6268
6269 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
6270 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
6271
6272 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6273 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
6274 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
6275 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
6276 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
6277 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
6278
6279 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
6280
6281 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
6282 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
6283
6284 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6285 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
6286 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
6287 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
6288 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
6289 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
6290
6291 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
6292
6293 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
6294 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
6295
6296 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6297 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
6298 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
6299 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
6300 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
6301 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
6302
6303 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
6304
6305 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
6306 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
6307
6308 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6309 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
6310 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
6311 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
6312 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
6313 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
6314
6315 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
6316
6317 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
6318 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
6319
6320 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6321 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
6322 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
6323 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
6324 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
6325 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
6326
6327 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
6328
6329 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
6330 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
6331
6332 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6333 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
6334 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
6335 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
6336 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
6337 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
6338
6339 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
6340
6341 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
6342 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
6343
6344 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6345 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
6346 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
6347 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
6348 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
6349 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
6350
6351 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
6352
6353 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
6354 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
6355
6356 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6357 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
6358 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
6359 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
6360 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
6361 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
6362
6363 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
6364
6365 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
6366 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
6367
6368 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6369 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
6370 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
6371 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
6372 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
6373 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
6374
6375 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
6376
6377 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
6378 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
6379
6380 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6381 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
6382 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
6383 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
6384 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
6385 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
6386
6387 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
6388
6389 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
6390 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
6391
6392 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6393 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
6394 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
6395 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
6396 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
6397 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
6398
6399 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
6400
6401 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
6402 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
6403
6404 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6405 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
6406 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
6407 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
6408 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
6409 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
6410
6411 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
6412
6413 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
6414 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
6415
6416 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6417 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
6418 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
6419 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
6420 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
6421 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
6422
6423 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
6424
6425 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
6426 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
6427
6428 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6429 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
6430 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
6431 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
6432 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
6433 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
6434
6435 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
6436
6437 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
6438 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
6439
6440 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6441 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
6442 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
6443 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
6444 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
6445 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
6446
6447 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
6448
6449 /******************************************************************************/
6450 /* */
6451 /* Controller Area Network */
6452 /* */
6453 /******************************************************************************/
6454
6455 /*!< CAN control and status registers */
6456 /******************* Bit definition for CAN_MCR register ********************/
6457 #define CAN_MCR_INRQ_Pos (0U)
6458 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
6459 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
6460 #define CAN_MCR_SLEEP_Pos (1U)
6461 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
6462 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
6463 #define CAN_MCR_TXFP_Pos (2U)
6464 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
6465 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
6466 #define CAN_MCR_RFLM_Pos (3U)
6467 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
6468 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
6469 #define CAN_MCR_NART_Pos (4U)
6470 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
6471 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
6472 #define CAN_MCR_AWUM_Pos (5U)
6473 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
6474 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
6475 #define CAN_MCR_ABOM_Pos (6U)
6476 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
6477 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
6478 #define CAN_MCR_TTCM_Pos (7U)
6479 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
6480 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
6481 #define CAN_MCR_RESET_Pos (15U)
6482 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
6483 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
6484 #define CAN_MCR_DBF_Pos (16U)
6485 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
6486 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
6487
6488 /******************* Bit definition for CAN_MSR register ********************/
6489 #define CAN_MSR_INAK_Pos (0U)
6490 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
6491 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
6492 #define CAN_MSR_SLAK_Pos (1U)
6493 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
6494 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
6495 #define CAN_MSR_ERRI_Pos (2U)
6496 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
6497 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
6498 #define CAN_MSR_WKUI_Pos (3U)
6499 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
6500 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
6501 #define CAN_MSR_SLAKI_Pos (4U)
6502 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
6503 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
6504 #define CAN_MSR_TXM_Pos (8U)
6505 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
6506 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
6507 #define CAN_MSR_RXM_Pos (9U)
6508 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
6509 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
6510 #define CAN_MSR_SAMP_Pos (10U)
6511 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
6512 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
6513 #define CAN_MSR_RX_Pos (11U)
6514 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
6515 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
6516
6517 /******************* Bit definition for CAN_TSR register ********************/
6518 #define CAN_TSR_RQCP0_Pos (0U)
6519 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
6520 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
6521 #define CAN_TSR_TXOK0_Pos (1U)
6522 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
6523 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
6524 #define CAN_TSR_ALST0_Pos (2U)
6525 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
6526 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
6527 #define CAN_TSR_TERR0_Pos (3U)
6528 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
6529 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
6530 #define CAN_TSR_ABRQ0_Pos (7U)
6531 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
6532 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
6533 #define CAN_TSR_RQCP1_Pos (8U)
6534 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
6535 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
6536 #define CAN_TSR_TXOK1_Pos (9U)
6537 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
6538 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
6539 #define CAN_TSR_ALST1_Pos (10U)
6540 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
6541 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
6542 #define CAN_TSR_TERR1_Pos (11U)
6543 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
6544 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
6545 #define CAN_TSR_ABRQ1_Pos (15U)
6546 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
6547 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
6548 #define CAN_TSR_RQCP2_Pos (16U)
6549 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
6550 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
6551 #define CAN_TSR_TXOK2_Pos (17U)
6552 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
6553 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
6554 #define CAN_TSR_ALST2_Pos (18U)
6555 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
6556 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
6557 #define CAN_TSR_TERR2_Pos (19U)
6558 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
6559 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
6560 #define CAN_TSR_ABRQ2_Pos (23U)
6561 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
6562 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
6563 #define CAN_TSR_CODE_Pos (24U)
6564 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
6565 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
6566
6567 #define CAN_TSR_TME_Pos (26U)
6568 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
6569 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
6570 #define CAN_TSR_TME0_Pos (26U)
6571 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
6572 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
6573 #define CAN_TSR_TME1_Pos (27U)
6574 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
6575 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
6576 #define CAN_TSR_TME2_Pos (28U)
6577 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
6578 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
6579
6580 #define CAN_TSR_LOW_Pos (29U)
6581 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
6582 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
6583 #define CAN_TSR_LOW0_Pos (29U)
6584 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
6585 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
6586 #define CAN_TSR_LOW1_Pos (30U)
6587 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
6588 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
6589 #define CAN_TSR_LOW2_Pos (31U)
6590 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
6591 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
6592
6593 /******************* Bit definition for CAN_RF0R register *******************/
6594 #define CAN_RF0R_FMP0_Pos (0U)
6595 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
6596 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
6597 #define CAN_RF0R_FULL0_Pos (3U)
6598 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
6599 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
6600 #define CAN_RF0R_FOVR0_Pos (4U)
6601 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
6602 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
6603 #define CAN_RF0R_RFOM0_Pos (5U)
6604 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
6605 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
6606
6607 /******************* Bit definition for CAN_RF1R register *******************/
6608 #define CAN_RF1R_FMP1_Pos (0U)
6609 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
6610 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
6611 #define CAN_RF1R_FULL1_Pos (3U)
6612 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
6613 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
6614 #define CAN_RF1R_FOVR1_Pos (4U)
6615 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
6616 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
6617 #define CAN_RF1R_RFOM1_Pos (5U)
6618 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
6619 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
6620
6621 /******************** Bit definition for CAN_IER register *******************/
6622 #define CAN_IER_TMEIE_Pos (0U)
6623 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
6624 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
6625 #define CAN_IER_FMPIE0_Pos (1U)
6626 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
6627 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
6628 #define CAN_IER_FFIE0_Pos (2U)
6629 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
6630 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
6631 #define CAN_IER_FOVIE0_Pos (3U)
6632 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
6633 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
6634 #define CAN_IER_FMPIE1_Pos (4U)
6635 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
6636 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
6637 #define CAN_IER_FFIE1_Pos (5U)
6638 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
6639 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
6640 #define CAN_IER_FOVIE1_Pos (6U)
6641 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
6642 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
6643 #define CAN_IER_EWGIE_Pos (8U)
6644 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
6645 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
6646 #define CAN_IER_EPVIE_Pos (9U)
6647 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
6648 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
6649 #define CAN_IER_BOFIE_Pos (10U)
6650 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
6651 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
6652 #define CAN_IER_LECIE_Pos (11U)
6653 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
6654 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
6655 #define CAN_IER_ERRIE_Pos (15U)
6656 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
6657 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
6658 #define CAN_IER_WKUIE_Pos (16U)
6659 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
6660 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
6661 #define CAN_IER_SLKIE_Pos (17U)
6662 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
6663 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
6664
6665 /******************** Bit definition for CAN_ESR register *******************/
6666 #define CAN_ESR_EWGF_Pos (0U)
6667 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
6668 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
6669 #define CAN_ESR_EPVF_Pos (1U)
6670 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
6671 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
6672 #define CAN_ESR_BOFF_Pos (2U)
6673 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
6674 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
6675
6676 #define CAN_ESR_LEC_Pos (4U)
6677 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
6678 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
6679 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
6680 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
6681 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
6682
6683 #define CAN_ESR_TEC_Pos (16U)
6684 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
6685 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
6686 #define CAN_ESR_REC_Pos (24U)
6687 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
6688 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
6689
6690 /******************* Bit definition for CAN_BTR register ********************/
6691 #define CAN_BTR_BRP_Pos (0U)
6692 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
6693 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
6694 #define CAN_BTR_TS1_Pos (16U)
6695 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
6696 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
6697 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
6698 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
6699 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
6700 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
6701 #define CAN_BTR_TS2_Pos (20U)
6702 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
6703 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
6704 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
6705 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
6706 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
6707 #define CAN_BTR_SJW_Pos (24U)
6708 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
6709 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
6710 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
6711 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
6712 #define CAN_BTR_LBKM_Pos (30U)
6713 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
6714 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
6715 #define CAN_BTR_SILM_Pos (31U)
6716 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
6717 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
6718
6719 /*!< Mailbox registers */
6720 /****************** Bit definition for CAN_TI0R register ********************/
6721 #define CAN_TI0R_TXRQ_Pos (0U)
6722 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
6723 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
6724 #define CAN_TI0R_RTR_Pos (1U)
6725 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
6726 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
6727 #define CAN_TI0R_IDE_Pos (2U)
6728 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
6729 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
6730 #define CAN_TI0R_EXID_Pos (3U)
6731 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
6732 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
6733 #define CAN_TI0R_STID_Pos (21U)
6734 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
6735 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
6736
6737 /****************** Bit definition for CAN_TDT0R register *******************/
6738 #define CAN_TDT0R_DLC_Pos (0U)
6739 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
6740 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
6741 #define CAN_TDT0R_TGT_Pos (8U)
6742 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
6743 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
6744 #define CAN_TDT0R_TIME_Pos (16U)
6745 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
6746 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
6747
6748 /****************** Bit definition for CAN_TDL0R register *******************/
6749 #define CAN_TDL0R_DATA0_Pos (0U)
6750 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
6751 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
6752 #define CAN_TDL0R_DATA1_Pos (8U)
6753 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
6754 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
6755 #define CAN_TDL0R_DATA2_Pos (16U)
6756 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
6757 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
6758 #define CAN_TDL0R_DATA3_Pos (24U)
6759 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
6760 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
6761
6762 /****************** Bit definition for CAN_TDH0R register *******************/
6763 #define CAN_TDH0R_DATA4_Pos (0U)
6764 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
6765 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
6766 #define CAN_TDH0R_DATA5_Pos (8U)
6767 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
6768 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
6769 #define CAN_TDH0R_DATA6_Pos (16U)
6770 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
6771 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
6772 #define CAN_TDH0R_DATA7_Pos (24U)
6773 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
6774 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
6775
6776 /******************* Bit definition for CAN_TI1R register *******************/
6777 #define CAN_TI1R_TXRQ_Pos (0U)
6778 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
6779 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
6780 #define CAN_TI1R_RTR_Pos (1U)
6781 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
6782 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
6783 #define CAN_TI1R_IDE_Pos (2U)
6784 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
6785 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
6786 #define CAN_TI1R_EXID_Pos (3U)
6787 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
6788 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
6789 #define CAN_TI1R_STID_Pos (21U)
6790 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
6791 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
6792
6793 /******************* Bit definition for CAN_TDT1R register ******************/
6794 #define CAN_TDT1R_DLC_Pos (0U)
6795 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
6796 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
6797 #define CAN_TDT1R_TGT_Pos (8U)
6798 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
6799 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
6800 #define CAN_TDT1R_TIME_Pos (16U)
6801 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
6802 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
6803
6804 /******************* Bit definition for CAN_TDL1R register ******************/
6805 #define CAN_TDL1R_DATA0_Pos (0U)
6806 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
6807 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
6808 #define CAN_TDL1R_DATA1_Pos (8U)
6809 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
6810 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
6811 #define CAN_TDL1R_DATA2_Pos (16U)
6812 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
6813 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
6814 #define CAN_TDL1R_DATA3_Pos (24U)
6815 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
6816 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
6817
6818 /******************* Bit definition for CAN_TDH1R register ******************/
6819 #define CAN_TDH1R_DATA4_Pos (0U)
6820 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
6821 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
6822 #define CAN_TDH1R_DATA5_Pos (8U)
6823 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
6824 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
6825 #define CAN_TDH1R_DATA6_Pos (16U)
6826 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
6827 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
6828 #define CAN_TDH1R_DATA7_Pos (24U)
6829 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
6830 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
6831
6832 /******************* Bit definition for CAN_TI2R register *******************/
6833 #define CAN_TI2R_TXRQ_Pos (0U)
6834 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
6835 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
6836 #define CAN_TI2R_RTR_Pos (1U)
6837 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
6838 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
6839 #define CAN_TI2R_IDE_Pos (2U)
6840 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
6841 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
6842 #define CAN_TI2R_EXID_Pos (3U)
6843 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
6844 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
6845 #define CAN_TI2R_STID_Pos (21U)
6846 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
6847 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
6848
6849 /******************* Bit definition for CAN_TDT2R register ******************/
6850 #define CAN_TDT2R_DLC_Pos (0U)
6851 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
6852 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
6853 #define CAN_TDT2R_TGT_Pos (8U)
6854 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
6855 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
6856 #define CAN_TDT2R_TIME_Pos (16U)
6857 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
6858 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
6859
6860 /******************* Bit definition for CAN_TDL2R register ******************/
6861 #define CAN_TDL2R_DATA0_Pos (0U)
6862 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
6863 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
6864 #define CAN_TDL2R_DATA1_Pos (8U)
6865 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
6866 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
6867 #define CAN_TDL2R_DATA2_Pos (16U)
6868 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
6869 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
6870 #define CAN_TDL2R_DATA3_Pos (24U)
6871 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
6872 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
6873
6874 /******************* Bit definition for CAN_TDH2R register ******************/
6875 #define CAN_TDH2R_DATA4_Pos (0U)
6876 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
6877 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
6878 #define CAN_TDH2R_DATA5_Pos (8U)
6879 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
6880 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
6881 #define CAN_TDH2R_DATA6_Pos (16U)
6882 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
6883 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
6884 #define CAN_TDH2R_DATA7_Pos (24U)
6885 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
6886 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
6887
6888 /******************* Bit definition for CAN_RI0R register *******************/
6889 #define CAN_RI0R_RTR_Pos (1U)
6890 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
6891 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
6892 #define CAN_RI0R_IDE_Pos (2U)
6893 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
6894 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
6895 #define CAN_RI0R_EXID_Pos (3U)
6896 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
6897 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
6898 #define CAN_RI0R_STID_Pos (21U)
6899 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
6900 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
6901
6902 /******************* Bit definition for CAN_RDT0R register ******************/
6903 #define CAN_RDT0R_DLC_Pos (0U)
6904 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
6905 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
6906 #define CAN_RDT0R_FMI_Pos (8U)
6907 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
6908 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
6909 #define CAN_RDT0R_TIME_Pos (16U)
6910 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
6911 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
6912
6913 /******************* Bit definition for CAN_RDL0R register ******************/
6914 #define CAN_RDL0R_DATA0_Pos (0U)
6915 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
6916 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
6917 #define CAN_RDL0R_DATA1_Pos (8U)
6918 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
6919 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
6920 #define CAN_RDL0R_DATA2_Pos (16U)
6921 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
6922 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
6923 #define CAN_RDL0R_DATA3_Pos (24U)
6924 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
6925 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
6926
6927 /******************* Bit definition for CAN_RDH0R register ******************/
6928 #define CAN_RDH0R_DATA4_Pos (0U)
6929 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
6930 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
6931 #define CAN_RDH0R_DATA5_Pos (8U)
6932 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
6933 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
6934 #define CAN_RDH0R_DATA6_Pos (16U)
6935 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
6936 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
6937 #define CAN_RDH0R_DATA7_Pos (24U)
6938 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
6939 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
6940
6941 /******************* Bit definition for CAN_RI1R register *******************/
6942 #define CAN_RI1R_RTR_Pos (1U)
6943 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
6944 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
6945 #define CAN_RI1R_IDE_Pos (2U)
6946 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
6947 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
6948 #define CAN_RI1R_EXID_Pos (3U)
6949 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
6950 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
6951 #define CAN_RI1R_STID_Pos (21U)
6952 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
6953 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
6954
6955 /******************* Bit definition for CAN_RDT1R register ******************/
6956 #define CAN_RDT1R_DLC_Pos (0U)
6957 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
6958 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
6959 #define CAN_RDT1R_FMI_Pos (8U)
6960 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
6961 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
6962 #define CAN_RDT1R_TIME_Pos (16U)
6963 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
6964 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
6965
6966 /******************* Bit definition for CAN_RDL1R register ******************/
6967 #define CAN_RDL1R_DATA0_Pos (0U)
6968 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
6969 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
6970 #define CAN_RDL1R_DATA1_Pos (8U)
6971 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
6972 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
6973 #define CAN_RDL1R_DATA2_Pos (16U)
6974 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
6975 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
6976 #define CAN_RDL1R_DATA3_Pos (24U)
6977 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
6978 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
6979
6980 /******************* Bit definition for CAN_RDH1R register ******************/
6981 #define CAN_RDH1R_DATA4_Pos (0U)
6982 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
6983 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
6984 #define CAN_RDH1R_DATA5_Pos (8U)
6985 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
6986 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
6987 #define CAN_RDH1R_DATA6_Pos (16U)
6988 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
6989 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
6990 #define CAN_RDH1R_DATA7_Pos (24U)
6991 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
6992 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
6993
6994 /*!< CAN filter registers */
6995 /******************* Bit definition for CAN_FMR register ********************/
6996 #define CAN_FMR_FINIT_Pos (0U)
6997 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
6998 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
6999 #define CAN_FMR_CAN2SB_Pos (8U)
7000 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
7001 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
7002
7003 /******************* Bit definition for CAN_FM1R register *******************/
7004 #define CAN_FM1R_FBM_Pos (0U)
7005 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
7006 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
7007 #define CAN_FM1R_FBM0_Pos (0U)
7008 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
7009 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
7010 #define CAN_FM1R_FBM1_Pos (1U)
7011 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
7012 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
7013 #define CAN_FM1R_FBM2_Pos (2U)
7014 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
7015 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
7016 #define CAN_FM1R_FBM3_Pos (3U)
7017 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
7018 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
7019 #define CAN_FM1R_FBM4_Pos (4U)
7020 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
7021 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
7022 #define CAN_FM1R_FBM5_Pos (5U)
7023 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
7024 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
7025 #define CAN_FM1R_FBM6_Pos (6U)
7026 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
7027 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
7028 #define CAN_FM1R_FBM7_Pos (7U)
7029 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
7030 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
7031 #define CAN_FM1R_FBM8_Pos (8U)
7032 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
7033 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
7034 #define CAN_FM1R_FBM9_Pos (9U)
7035 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
7036 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
7037 #define CAN_FM1R_FBM10_Pos (10U)
7038 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
7039 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
7040 #define CAN_FM1R_FBM11_Pos (11U)
7041 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
7042 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
7043 #define CAN_FM1R_FBM12_Pos (12U)
7044 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
7045 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
7046 #define CAN_FM1R_FBM13_Pos (13U)
7047 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
7048 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
7049
7050 /******************* Bit definition for CAN_FS1R register *******************/
7051 #define CAN_FS1R_FSC_Pos (0U)
7052 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
7053 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
7054 #define CAN_FS1R_FSC0_Pos (0U)
7055 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
7056 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
7057 #define CAN_FS1R_FSC1_Pos (1U)
7058 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
7059 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
7060 #define CAN_FS1R_FSC2_Pos (2U)
7061 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
7062 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
7063 #define CAN_FS1R_FSC3_Pos (3U)
7064 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
7065 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
7066 #define CAN_FS1R_FSC4_Pos (4U)
7067 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
7068 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
7069 #define CAN_FS1R_FSC5_Pos (5U)
7070 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
7071 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
7072 #define CAN_FS1R_FSC6_Pos (6U)
7073 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
7074 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
7075 #define CAN_FS1R_FSC7_Pos (7U)
7076 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
7077 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
7078 #define CAN_FS1R_FSC8_Pos (8U)
7079 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
7080 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
7081 #define CAN_FS1R_FSC9_Pos (9U)
7082 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
7083 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
7084 #define CAN_FS1R_FSC10_Pos (10U)
7085 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
7086 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
7087 #define CAN_FS1R_FSC11_Pos (11U)
7088 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
7089 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
7090 #define CAN_FS1R_FSC12_Pos (12U)
7091 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
7092 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
7093 #define CAN_FS1R_FSC13_Pos (13U)
7094 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
7095 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
7096
7097 /****************** Bit definition for CAN_FFA1R register *******************/
7098 #define CAN_FFA1R_FFA_Pos (0U)
7099 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
7100 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
7101 #define CAN_FFA1R_FFA0_Pos (0U)
7102 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
7103 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
7104 #define CAN_FFA1R_FFA1_Pos (1U)
7105 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
7106 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
7107 #define CAN_FFA1R_FFA2_Pos (2U)
7108 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
7109 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
7110 #define CAN_FFA1R_FFA3_Pos (3U)
7111 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
7112 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
7113 #define CAN_FFA1R_FFA4_Pos (4U)
7114 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
7115 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
7116 #define CAN_FFA1R_FFA5_Pos (5U)
7117 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
7118 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
7119 #define CAN_FFA1R_FFA6_Pos (6U)
7120 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
7121 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
7122 #define CAN_FFA1R_FFA7_Pos (7U)
7123 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
7124 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
7125 #define CAN_FFA1R_FFA8_Pos (8U)
7126 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
7127 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
7128 #define CAN_FFA1R_FFA9_Pos (9U)
7129 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
7130 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
7131 #define CAN_FFA1R_FFA10_Pos (10U)
7132 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
7133 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
7134 #define CAN_FFA1R_FFA11_Pos (11U)
7135 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
7136 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
7137 #define CAN_FFA1R_FFA12_Pos (12U)
7138 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
7139 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
7140 #define CAN_FFA1R_FFA13_Pos (13U)
7141 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
7142 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
7143
7144 /******************* Bit definition for CAN_FA1R register *******************/
7145 #define CAN_FA1R_FACT_Pos (0U)
7146 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
7147 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
7148 #define CAN_FA1R_FACT0_Pos (0U)
7149 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
7150 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
7151 #define CAN_FA1R_FACT1_Pos (1U)
7152 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
7153 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
7154 #define CAN_FA1R_FACT2_Pos (2U)
7155 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
7156 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
7157 #define CAN_FA1R_FACT3_Pos (3U)
7158 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
7159 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
7160 #define CAN_FA1R_FACT4_Pos (4U)
7161 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
7162 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
7163 #define CAN_FA1R_FACT5_Pos (5U)
7164 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
7165 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
7166 #define CAN_FA1R_FACT6_Pos (6U)
7167 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
7168 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
7169 #define CAN_FA1R_FACT7_Pos (7U)
7170 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
7171 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
7172 #define CAN_FA1R_FACT8_Pos (8U)
7173 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
7174 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
7175 #define CAN_FA1R_FACT9_Pos (9U)
7176 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
7177 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
7178 #define CAN_FA1R_FACT10_Pos (10U)
7179 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
7180 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
7181 #define CAN_FA1R_FACT11_Pos (11U)
7182 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
7183 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
7184 #define CAN_FA1R_FACT12_Pos (12U)
7185 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
7186 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
7187 #define CAN_FA1R_FACT13_Pos (13U)
7188 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
7189 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
7190
7191 /******************* Bit definition for CAN_F0R1 register *******************/
7192 #define CAN_F0R1_FB0_Pos (0U)
7193 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
7194 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
7195 #define CAN_F0R1_FB1_Pos (1U)
7196 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
7197 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
7198 #define CAN_F0R1_FB2_Pos (2U)
7199 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
7200 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
7201 #define CAN_F0R1_FB3_Pos (3U)
7202 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
7203 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
7204 #define CAN_F0R1_FB4_Pos (4U)
7205 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
7206 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
7207 #define CAN_F0R1_FB5_Pos (5U)
7208 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
7209 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
7210 #define CAN_F0R1_FB6_Pos (6U)
7211 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
7212 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
7213 #define CAN_F0R1_FB7_Pos (7U)
7214 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
7215 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
7216 #define CAN_F0R1_FB8_Pos (8U)
7217 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
7218 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
7219 #define CAN_F0R1_FB9_Pos (9U)
7220 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
7221 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
7222 #define CAN_F0R1_FB10_Pos (10U)
7223 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
7224 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
7225 #define CAN_F0R1_FB11_Pos (11U)
7226 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
7227 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
7228 #define CAN_F0R1_FB12_Pos (12U)
7229 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
7230 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
7231 #define CAN_F0R1_FB13_Pos (13U)
7232 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
7233 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
7234 #define CAN_F0R1_FB14_Pos (14U)
7235 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
7236 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
7237 #define CAN_F0R1_FB15_Pos (15U)
7238 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
7239 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
7240 #define CAN_F0R1_FB16_Pos (16U)
7241 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
7242 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
7243 #define CAN_F0R1_FB17_Pos (17U)
7244 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
7245 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
7246 #define CAN_F0R1_FB18_Pos (18U)
7247 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
7248 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
7249 #define CAN_F0R1_FB19_Pos (19U)
7250 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
7251 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
7252 #define CAN_F0R1_FB20_Pos (20U)
7253 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
7254 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
7255 #define CAN_F0R1_FB21_Pos (21U)
7256 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
7257 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
7258 #define CAN_F0R1_FB22_Pos (22U)
7259 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
7260 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
7261 #define CAN_F0R1_FB23_Pos (23U)
7262 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
7263 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
7264 #define CAN_F0R1_FB24_Pos (24U)
7265 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
7266 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
7267 #define CAN_F0R1_FB25_Pos (25U)
7268 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
7269 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
7270 #define CAN_F0R1_FB26_Pos (26U)
7271 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
7272 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
7273 #define CAN_F0R1_FB27_Pos (27U)
7274 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
7275 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
7276 #define CAN_F0R1_FB28_Pos (28U)
7277 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
7278 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
7279 #define CAN_F0R1_FB29_Pos (29U)
7280 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
7281 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
7282 #define CAN_F0R1_FB30_Pos (30U)
7283 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
7284 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
7285 #define CAN_F0R1_FB31_Pos (31U)
7286 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
7287 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
7288
7289 /******************* Bit definition for CAN_F1R1 register *******************/
7290 #define CAN_F1R1_FB0_Pos (0U)
7291 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
7292 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
7293 #define CAN_F1R1_FB1_Pos (1U)
7294 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
7295 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
7296 #define CAN_F1R1_FB2_Pos (2U)
7297 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
7298 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
7299 #define CAN_F1R1_FB3_Pos (3U)
7300 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
7301 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
7302 #define CAN_F1R1_FB4_Pos (4U)
7303 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
7304 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
7305 #define CAN_F1R1_FB5_Pos (5U)
7306 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
7307 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
7308 #define CAN_F1R1_FB6_Pos (6U)
7309 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
7310 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
7311 #define CAN_F1R1_FB7_Pos (7U)
7312 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
7313 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
7314 #define CAN_F1R1_FB8_Pos (8U)
7315 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
7316 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
7317 #define CAN_F1R1_FB9_Pos (9U)
7318 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
7319 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
7320 #define CAN_F1R1_FB10_Pos (10U)
7321 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
7322 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
7323 #define CAN_F1R1_FB11_Pos (11U)
7324 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
7325 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
7326 #define CAN_F1R1_FB12_Pos (12U)
7327 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
7328 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
7329 #define CAN_F1R1_FB13_Pos (13U)
7330 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
7331 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
7332 #define CAN_F1R1_FB14_Pos (14U)
7333 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
7334 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
7335 #define CAN_F1R1_FB15_Pos (15U)
7336 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
7337 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
7338 #define CAN_F1R1_FB16_Pos (16U)
7339 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
7340 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
7341 #define CAN_F1R1_FB17_Pos (17U)
7342 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
7343 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
7344 #define CAN_F1R1_FB18_Pos (18U)
7345 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
7346 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
7347 #define CAN_F1R1_FB19_Pos (19U)
7348 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
7349 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
7350 #define CAN_F1R1_FB20_Pos (20U)
7351 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
7352 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
7353 #define CAN_F1R1_FB21_Pos (21U)
7354 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
7355 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
7356 #define CAN_F1R1_FB22_Pos (22U)
7357 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
7358 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
7359 #define CAN_F1R1_FB23_Pos (23U)
7360 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
7361 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
7362 #define CAN_F1R1_FB24_Pos (24U)
7363 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
7364 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
7365 #define CAN_F1R1_FB25_Pos (25U)
7366 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
7367 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
7368 #define CAN_F1R1_FB26_Pos (26U)
7369 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
7370 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
7371 #define CAN_F1R1_FB27_Pos (27U)
7372 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
7373 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
7374 #define CAN_F1R1_FB28_Pos (28U)
7375 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
7376 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
7377 #define CAN_F1R1_FB29_Pos (29U)
7378 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
7379 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
7380 #define CAN_F1R1_FB30_Pos (30U)
7381 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
7382 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
7383 #define CAN_F1R1_FB31_Pos (31U)
7384 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
7385 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
7386
7387 /******************* Bit definition for CAN_F2R1 register *******************/
7388 #define CAN_F2R1_FB0_Pos (0U)
7389 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
7390 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
7391 #define CAN_F2R1_FB1_Pos (1U)
7392 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
7393 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
7394 #define CAN_F2R1_FB2_Pos (2U)
7395 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
7396 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
7397 #define CAN_F2R1_FB3_Pos (3U)
7398 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
7399 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
7400 #define CAN_F2R1_FB4_Pos (4U)
7401 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
7402 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
7403 #define CAN_F2R1_FB5_Pos (5U)
7404 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
7405 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
7406 #define CAN_F2R1_FB6_Pos (6U)
7407 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
7408 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
7409 #define CAN_F2R1_FB7_Pos (7U)
7410 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
7411 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
7412 #define CAN_F2R1_FB8_Pos (8U)
7413 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
7414 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
7415 #define CAN_F2R1_FB9_Pos (9U)
7416 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
7417 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
7418 #define CAN_F2R1_FB10_Pos (10U)
7419 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
7420 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
7421 #define CAN_F2R1_FB11_Pos (11U)
7422 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
7423 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
7424 #define CAN_F2R1_FB12_Pos (12U)
7425 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
7426 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
7427 #define CAN_F2R1_FB13_Pos (13U)
7428 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
7429 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
7430 #define CAN_F2R1_FB14_Pos (14U)
7431 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
7432 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
7433 #define CAN_F2R1_FB15_Pos (15U)
7434 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
7435 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
7436 #define CAN_F2R1_FB16_Pos (16U)
7437 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
7438 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
7439 #define CAN_F2R1_FB17_Pos (17U)
7440 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
7441 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
7442 #define CAN_F2R1_FB18_Pos (18U)
7443 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
7444 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
7445 #define CAN_F2R1_FB19_Pos (19U)
7446 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
7447 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
7448 #define CAN_F2R1_FB20_Pos (20U)
7449 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
7450 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
7451 #define CAN_F2R1_FB21_Pos (21U)
7452 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
7453 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
7454 #define CAN_F2R1_FB22_Pos (22U)
7455 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
7456 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
7457 #define CAN_F2R1_FB23_Pos (23U)
7458 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
7459 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
7460 #define CAN_F2R1_FB24_Pos (24U)
7461 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
7462 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
7463 #define CAN_F2R1_FB25_Pos (25U)
7464 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
7465 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
7466 #define CAN_F2R1_FB26_Pos (26U)
7467 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
7468 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
7469 #define CAN_F2R1_FB27_Pos (27U)
7470 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
7471 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
7472 #define CAN_F2R1_FB28_Pos (28U)
7473 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
7474 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
7475 #define CAN_F2R1_FB29_Pos (29U)
7476 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
7477 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
7478 #define CAN_F2R1_FB30_Pos (30U)
7479 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
7480 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
7481 #define CAN_F2R1_FB31_Pos (31U)
7482 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
7483 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
7484
7485 /******************* Bit definition for CAN_F3R1 register *******************/
7486 #define CAN_F3R1_FB0_Pos (0U)
7487 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
7488 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
7489 #define CAN_F3R1_FB1_Pos (1U)
7490 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
7491 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
7492 #define CAN_F3R1_FB2_Pos (2U)
7493 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
7494 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
7495 #define CAN_F3R1_FB3_Pos (3U)
7496 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
7497 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
7498 #define CAN_F3R1_FB4_Pos (4U)
7499 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
7500 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
7501 #define CAN_F3R1_FB5_Pos (5U)
7502 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
7503 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
7504 #define CAN_F3R1_FB6_Pos (6U)
7505 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
7506 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
7507 #define CAN_F3R1_FB7_Pos (7U)
7508 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
7509 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
7510 #define CAN_F3R1_FB8_Pos (8U)
7511 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
7512 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
7513 #define CAN_F3R1_FB9_Pos (9U)
7514 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
7515 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
7516 #define CAN_F3R1_FB10_Pos (10U)
7517 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
7518 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
7519 #define CAN_F3R1_FB11_Pos (11U)
7520 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
7521 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
7522 #define CAN_F3R1_FB12_Pos (12U)
7523 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
7524 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
7525 #define CAN_F3R1_FB13_Pos (13U)
7526 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
7527 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
7528 #define CAN_F3R1_FB14_Pos (14U)
7529 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
7530 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
7531 #define CAN_F3R1_FB15_Pos (15U)
7532 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
7533 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
7534 #define CAN_F3R1_FB16_Pos (16U)
7535 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
7536 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
7537 #define CAN_F3R1_FB17_Pos (17U)
7538 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
7539 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
7540 #define CAN_F3R1_FB18_Pos (18U)
7541 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
7542 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
7543 #define CAN_F3R1_FB19_Pos (19U)
7544 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
7545 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
7546 #define CAN_F3R1_FB20_Pos (20U)
7547 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
7548 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
7549 #define CAN_F3R1_FB21_Pos (21U)
7550 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
7551 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
7552 #define CAN_F3R1_FB22_Pos (22U)
7553 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
7554 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
7555 #define CAN_F3R1_FB23_Pos (23U)
7556 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
7557 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
7558 #define CAN_F3R1_FB24_Pos (24U)
7559 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
7560 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
7561 #define CAN_F3R1_FB25_Pos (25U)
7562 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
7563 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
7564 #define CAN_F3R1_FB26_Pos (26U)
7565 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
7566 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
7567 #define CAN_F3R1_FB27_Pos (27U)
7568 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
7569 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
7570 #define CAN_F3R1_FB28_Pos (28U)
7571 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
7572 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
7573 #define CAN_F3R1_FB29_Pos (29U)
7574 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
7575 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
7576 #define CAN_F3R1_FB30_Pos (30U)
7577 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
7578 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
7579 #define CAN_F3R1_FB31_Pos (31U)
7580 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
7581 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
7582
7583 /******************* Bit definition for CAN_F4R1 register *******************/
7584 #define CAN_F4R1_FB0_Pos (0U)
7585 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
7586 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
7587 #define CAN_F4R1_FB1_Pos (1U)
7588 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
7589 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
7590 #define CAN_F4R1_FB2_Pos (2U)
7591 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
7592 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
7593 #define CAN_F4R1_FB3_Pos (3U)
7594 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
7595 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
7596 #define CAN_F4R1_FB4_Pos (4U)
7597 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
7598 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
7599 #define CAN_F4R1_FB5_Pos (5U)
7600 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
7601 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
7602 #define CAN_F4R1_FB6_Pos (6U)
7603 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
7604 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
7605 #define CAN_F4R1_FB7_Pos (7U)
7606 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
7607 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
7608 #define CAN_F4R1_FB8_Pos (8U)
7609 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
7610 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
7611 #define CAN_F4R1_FB9_Pos (9U)
7612 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
7613 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
7614 #define CAN_F4R1_FB10_Pos (10U)
7615 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
7616 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
7617 #define CAN_F4R1_FB11_Pos (11U)
7618 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
7619 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
7620 #define CAN_F4R1_FB12_Pos (12U)
7621 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
7622 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
7623 #define CAN_F4R1_FB13_Pos (13U)
7624 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
7625 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
7626 #define CAN_F4R1_FB14_Pos (14U)
7627 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
7628 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
7629 #define CAN_F4R1_FB15_Pos (15U)
7630 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
7631 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
7632 #define CAN_F4R1_FB16_Pos (16U)
7633 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
7634 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
7635 #define CAN_F4R1_FB17_Pos (17U)
7636 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
7637 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
7638 #define CAN_F4R1_FB18_Pos (18U)
7639 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
7640 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
7641 #define CAN_F4R1_FB19_Pos (19U)
7642 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
7643 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
7644 #define CAN_F4R1_FB20_Pos (20U)
7645 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
7646 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
7647 #define CAN_F4R1_FB21_Pos (21U)
7648 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
7649 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
7650 #define CAN_F4R1_FB22_Pos (22U)
7651 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
7652 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
7653 #define CAN_F4R1_FB23_Pos (23U)
7654 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
7655 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
7656 #define CAN_F4R1_FB24_Pos (24U)
7657 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
7658 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
7659 #define CAN_F4R1_FB25_Pos (25U)
7660 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
7661 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
7662 #define CAN_F4R1_FB26_Pos (26U)
7663 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
7664 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
7665 #define CAN_F4R1_FB27_Pos (27U)
7666 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
7667 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
7668 #define CAN_F4R1_FB28_Pos (28U)
7669 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
7670 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
7671 #define CAN_F4R1_FB29_Pos (29U)
7672 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
7673 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
7674 #define CAN_F4R1_FB30_Pos (30U)
7675 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
7676 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
7677 #define CAN_F4R1_FB31_Pos (31U)
7678 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
7679 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
7680
7681 /******************* Bit definition for CAN_F5R1 register *******************/
7682 #define CAN_F5R1_FB0_Pos (0U)
7683 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
7684 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
7685 #define CAN_F5R1_FB1_Pos (1U)
7686 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
7687 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
7688 #define CAN_F5R1_FB2_Pos (2U)
7689 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
7690 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
7691 #define CAN_F5R1_FB3_Pos (3U)
7692 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
7693 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
7694 #define CAN_F5R1_FB4_Pos (4U)
7695 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
7696 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
7697 #define CAN_F5R1_FB5_Pos (5U)
7698 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
7699 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
7700 #define CAN_F5R1_FB6_Pos (6U)
7701 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
7702 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
7703 #define CAN_F5R1_FB7_Pos (7U)
7704 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
7705 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
7706 #define CAN_F5R1_FB8_Pos (8U)
7707 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
7708 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
7709 #define CAN_F5R1_FB9_Pos (9U)
7710 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
7711 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
7712 #define CAN_F5R1_FB10_Pos (10U)
7713 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
7714 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
7715 #define CAN_F5R1_FB11_Pos (11U)
7716 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
7717 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
7718 #define CAN_F5R1_FB12_Pos (12U)
7719 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
7720 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
7721 #define CAN_F5R1_FB13_Pos (13U)
7722 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
7723 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
7724 #define CAN_F5R1_FB14_Pos (14U)
7725 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
7726 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
7727 #define CAN_F5R1_FB15_Pos (15U)
7728 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
7729 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
7730 #define CAN_F5R1_FB16_Pos (16U)
7731 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
7732 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
7733 #define CAN_F5R1_FB17_Pos (17U)
7734 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
7735 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
7736 #define CAN_F5R1_FB18_Pos (18U)
7737 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
7738 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
7739 #define CAN_F5R1_FB19_Pos (19U)
7740 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
7741 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
7742 #define CAN_F5R1_FB20_Pos (20U)
7743 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
7744 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
7745 #define CAN_F5R1_FB21_Pos (21U)
7746 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
7747 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
7748 #define CAN_F5R1_FB22_Pos (22U)
7749 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
7750 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
7751 #define CAN_F5R1_FB23_Pos (23U)
7752 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
7753 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
7754 #define CAN_F5R1_FB24_Pos (24U)
7755 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
7756 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
7757 #define CAN_F5R1_FB25_Pos (25U)
7758 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
7759 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
7760 #define CAN_F5R1_FB26_Pos (26U)
7761 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
7762 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
7763 #define CAN_F5R1_FB27_Pos (27U)
7764 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
7765 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
7766 #define CAN_F5R1_FB28_Pos (28U)
7767 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
7768 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
7769 #define CAN_F5R1_FB29_Pos (29U)
7770 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
7771 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
7772 #define CAN_F5R1_FB30_Pos (30U)
7773 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
7774 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
7775 #define CAN_F5R1_FB31_Pos (31U)
7776 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
7777 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
7778
7779 /******************* Bit definition for CAN_F6R1 register *******************/
7780 #define CAN_F6R1_FB0_Pos (0U)
7781 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
7782 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
7783 #define CAN_F6R1_FB1_Pos (1U)
7784 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
7785 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
7786 #define CAN_F6R1_FB2_Pos (2U)
7787 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
7788 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
7789 #define CAN_F6R1_FB3_Pos (3U)
7790 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
7791 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
7792 #define CAN_F6R1_FB4_Pos (4U)
7793 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
7794 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
7795 #define CAN_F6R1_FB5_Pos (5U)
7796 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
7797 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
7798 #define CAN_F6R1_FB6_Pos (6U)
7799 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
7800 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
7801 #define CAN_F6R1_FB7_Pos (7U)
7802 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
7803 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
7804 #define CAN_F6R1_FB8_Pos (8U)
7805 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
7806 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
7807 #define CAN_F6R1_FB9_Pos (9U)
7808 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
7809 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
7810 #define CAN_F6R1_FB10_Pos (10U)
7811 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
7812 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
7813 #define CAN_F6R1_FB11_Pos (11U)
7814 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
7815 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
7816 #define CAN_F6R1_FB12_Pos (12U)
7817 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
7818 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
7819 #define CAN_F6R1_FB13_Pos (13U)
7820 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
7821 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
7822 #define CAN_F6R1_FB14_Pos (14U)
7823 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
7824 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
7825 #define CAN_F6R1_FB15_Pos (15U)
7826 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
7827 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
7828 #define CAN_F6R1_FB16_Pos (16U)
7829 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
7830 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
7831 #define CAN_F6R1_FB17_Pos (17U)
7832 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
7833 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
7834 #define CAN_F6R1_FB18_Pos (18U)
7835 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
7836 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
7837 #define CAN_F6R1_FB19_Pos (19U)
7838 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
7839 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
7840 #define CAN_F6R1_FB20_Pos (20U)
7841 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
7842 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
7843 #define CAN_F6R1_FB21_Pos (21U)
7844 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
7845 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
7846 #define CAN_F6R1_FB22_Pos (22U)
7847 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
7848 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
7849 #define CAN_F6R1_FB23_Pos (23U)
7850 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
7851 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
7852 #define CAN_F6R1_FB24_Pos (24U)
7853 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
7854 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
7855 #define CAN_F6R1_FB25_Pos (25U)
7856 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
7857 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
7858 #define CAN_F6R1_FB26_Pos (26U)
7859 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
7860 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
7861 #define CAN_F6R1_FB27_Pos (27U)
7862 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
7863 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
7864 #define CAN_F6R1_FB28_Pos (28U)
7865 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
7866 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
7867 #define CAN_F6R1_FB29_Pos (29U)
7868 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
7869 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
7870 #define CAN_F6R1_FB30_Pos (30U)
7871 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
7872 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
7873 #define CAN_F6R1_FB31_Pos (31U)
7874 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
7875 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
7876
7877 /******************* Bit definition for CAN_F7R1 register *******************/
7878 #define CAN_F7R1_FB0_Pos (0U)
7879 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
7880 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
7881 #define CAN_F7R1_FB1_Pos (1U)
7882 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
7883 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
7884 #define CAN_F7R1_FB2_Pos (2U)
7885 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
7886 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
7887 #define CAN_F7R1_FB3_Pos (3U)
7888 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
7889 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
7890 #define CAN_F7R1_FB4_Pos (4U)
7891 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
7892 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
7893 #define CAN_F7R1_FB5_Pos (5U)
7894 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
7895 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
7896 #define CAN_F7R1_FB6_Pos (6U)
7897 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
7898 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
7899 #define CAN_F7R1_FB7_Pos (7U)
7900 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
7901 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
7902 #define CAN_F7R1_FB8_Pos (8U)
7903 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
7904 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
7905 #define CAN_F7R1_FB9_Pos (9U)
7906 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
7907 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
7908 #define CAN_F7R1_FB10_Pos (10U)
7909 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
7910 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
7911 #define CAN_F7R1_FB11_Pos (11U)
7912 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
7913 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
7914 #define CAN_F7R1_FB12_Pos (12U)
7915 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
7916 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
7917 #define CAN_F7R1_FB13_Pos (13U)
7918 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
7919 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
7920 #define CAN_F7R1_FB14_Pos (14U)
7921 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
7922 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
7923 #define CAN_F7R1_FB15_Pos (15U)
7924 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
7925 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
7926 #define CAN_F7R1_FB16_Pos (16U)
7927 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
7928 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
7929 #define CAN_F7R1_FB17_Pos (17U)
7930 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
7931 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
7932 #define CAN_F7R1_FB18_Pos (18U)
7933 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
7934 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
7935 #define CAN_F7R1_FB19_Pos (19U)
7936 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
7937 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
7938 #define CAN_F7R1_FB20_Pos (20U)
7939 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
7940 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
7941 #define CAN_F7R1_FB21_Pos (21U)
7942 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
7943 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
7944 #define CAN_F7R1_FB22_Pos (22U)
7945 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
7946 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
7947 #define CAN_F7R1_FB23_Pos (23U)
7948 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
7949 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
7950 #define CAN_F7R1_FB24_Pos (24U)
7951 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
7952 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
7953 #define CAN_F7R1_FB25_Pos (25U)
7954 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
7955 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
7956 #define CAN_F7R1_FB26_Pos (26U)
7957 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
7958 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
7959 #define CAN_F7R1_FB27_Pos (27U)
7960 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
7961 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
7962 #define CAN_F7R1_FB28_Pos (28U)
7963 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
7964 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
7965 #define CAN_F7R1_FB29_Pos (29U)
7966 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
7967 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
7968 #define CAN_F7R1_FB30_Pos (30U)
7969 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
7970 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
7971 #define CAN_F7R1_FB31_Pos (31U)
7972 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
7973 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
7974
7975 /******************* Bit definition for CAN_F8R1 register *******************/
7976 #define CAN_F8R1_FB0_Pos (0U)
7977 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
7978 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
7979 #define CAN_F8R1_FB1_Pos (1U)
7980 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
7981 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
7982 #define CAN_F8R1_FB2_Pos (2U)
7983 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
7984 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
7985 #define CAN_F8R1_FB3_Pos (3U)
7986 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
7987 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
7988 #define CAN_F8R1_FB4_Pos (4U)
7989 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
7990 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
7991 #define CAN_F8R1_FB5_Pos (5U)
7992 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
7993 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
7994 #define CAN_F8R1_FB6_Pos (6U)
7995 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
7996 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
7997 #define CAN_F8R1_FB7_Pos (7U)
7998 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
7999 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
8000 #define CAN_F8R1_FB8_Pos (8U)
8001 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
8002 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
8003 #define CAN_F8R1_FB9_Pos (9U)
8004 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
8005 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
8006 #define CAN_F8R1_FB10_Pos (10U)
8007 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
8008 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
8009 #define CAN_F8R1_FB11_Pos (11U)
8010 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
8011 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
8012 #define CAN_F8R1_FB12_Pos (12U)
8013 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
8014 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
8015 #define CAN_F8R1_FB13_Pos (13U)
8016 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
8017 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
8018 #define CAN_F8R1_FB14_Pos (14U)
8019 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
8020 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
8021 #define CAN_F8R1_FB15_Pos (15U)
8022 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
8023 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
8024 #define CAN_F8R1_FB16_Pos (16U)
8025 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
8026 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
8027 #define CAN_F8R1_FB17_Pos (17U)
8028 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
8029 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
8030 #define CAN_F8R1_FB18_Pos (18U)
8031 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
8032 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
8033 #define CAN_F8R1_FB19_Pos (19U)
8034 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
8035 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
8036 #define CAN_F8R1_FB20_Pos (20U)
8037 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
8038 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
8039 #define CAN_F8R1_FB21_Pos (21U)
8040 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
8041 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
8042 #define CAN_F8R1_FB22_Pos (22U)
8043 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
8044 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
8045 #define CAN_F8R1_FB23_Pos (23U)
8046 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
8047 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
8048 #define CAN_F8R1_FB24_Pos (24U)
8049 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
8050 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
8051 #define CAN_F8R1_FB25_Pos (25U)
8052 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
8053 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
8054 #define CAN_F8R1_FB26_Pos (26U)
8055 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
8056 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
8057 #define CAN_F8R1_FB27_Pos (27U)
8058 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
8059 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
8060 #define CAN_F8R1_FB28_Pos (28U)
8061 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
8062 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
8063 #define CAN_F8R1_FB29_Pos (29U)
8064 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
8065 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
8066 #define CAN_F8R1_FB30_Pos (30U)
8067 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
8068 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
8069 #define CAN_F8R1_FB31_Pos (31U)
8070 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
8071 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
8072
8073 /******************* Bit definition for CAN_F9R1 register *******************/
8074 #define CAN_F9R1_FB0_Pos (0U)
8075 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
8076 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
8077 #define CAN_F9R1_FB1_Pos (1U)
8078 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
8079 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
8080 #define CAN_F9R1_FB2_Pos (2U)
8081 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
8082 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
8083 #define CAN_F9R1_FB3_Pos (3U)
8084 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
8085 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
8086 #define CAN_F9R1_FB4_Pos (4U)
8087 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
8088 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
8089 #define CAN_F9R1_FB5_Pos (5U)
8090 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
8091 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
8092 #define CAN_F9R1_FB6_Pos (6U)
8093 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
8094 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
8095 #define CAN_F9R1_FB7_Pos (7U)
8096 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
8097 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
8098 #define CAN_F9R1_FB8_Pos (8U)
8099 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
8100 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
8101 #define CAN_F9R1_FB9_Pos (9U)
8102 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
8103 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
8104 #define CAN_F9R1_FB10_Pos (10U)
8105 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
8106 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
8107 #define CAN_F9R1_FB11_Pos (11U)
8108 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
8109 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
8110 #define CAN_F9R1_FB12_Pos (12U)
8111 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
8112 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
8113 #define CAN_F9R1_FB13_Pos (13U)
8114 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
8115 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
8116 #define CAN_F9R1_FB14_Pos (14U)
8117 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
8118 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
8119 #define CAN_F9R1_FB15_Pos (15U)
8120 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
8121 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
8122 #define CAN_F9R1_FB16_Pos (16U)
8123 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
8124 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
8125 #define CAN_F9R1_FB17_Pos (17U)
8126 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
8127 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
8128 #define CAN_F9R1_FB18_Pos (18U)
8129 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
8130 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
8131 #define CAN_F9R1_FB19_Pos (19U)
8132 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
8133 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
8134 #define CAN_F9R1_FB20_Pos (20U)
8135 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
8136 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
8137 #define CAN_F9R1_FB21_Pos (21U)
8138 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
8139 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
8140 #define CAN_F9R1_FB22_Pos (22U)
8141 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
8142 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
8143 #define CAN_F9R1_FB23_Pos (23U)
8144 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
8145 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
8146 #define CAN_F9R1_FB24_Pos (24U)
8147 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
8148 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
8149 #define CAN_F9R1_FB25_Pos (25U)
8150 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
8151 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
8152 #define CAN_F9R1_FB26_Pos (26U)
8153 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
8154 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
8155 #define CAN_F9R1_FB27_Pos (27U)
8156 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
8157 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
8158 #define CAN_F9R1_FB28_Pos (28U)
8159 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
8160 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
8161 #define CAN_F9R1_FB29_Pos (29U)
8162 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
8163 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
8164 #define CAN_F9R1_FB30_Pos (30U)
8165 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
8166 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
8167 #define CAN_F9R1_FB31_Pos (31U)
8168 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
8169 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
8170
8171 /******************* Bit definition for CAN_F10R1 register ******************/
8172 #define CAN_F10R1_FB0_Pos (0U)
8173 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
8174 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
8175 #define CAN_F10R1_FB1_Pos (1U)
8176 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
8177 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
8178 #define CAN_F10R1_FB2_Pos (2U)
8179 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
8180 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
8181 #define CAN_F10R1_FB3_Pos (3U)
8182 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
8183 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
8184 #define CAN_F10R1_FB4_Pos (4U)
8185 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
8186 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
8187 #define CAN_F10R1_FB5_Pos (5U)
8188 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
8189 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
8190 #define CAN_F10R1_FB6_Pos (6U)
8191 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
8192 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
8193 #define CAN_F10R1_FB7_Pos (7U)
8194 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
8195 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
8196 #define CAN_F10R1_FB8_Pos (8U)
8197 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
8198 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
8199 #define CAN_F10R1_FB9_Pos (9U)
8200 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
8201 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
8202 #define CAN_F10R1_FB10_Pos (10U)
8203 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
8204 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
8205 #define CAN_F10R1_FB11_Pos (11U)
8206 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
8207 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
8208 #define CAN_F10R1_FB12_Pos (12U)
8209 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
8210 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
8211 #define CAN_F10R1_FB13_Pos (13U)
8212 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
8213 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
8214 #define CAN_F10R1_FB14_Pos (14U)
8215 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
8216 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
8217 #define CAN_F10R1_FB15_Pos (15U)
8218 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
8219 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
8220 #define CAN_F10R1_FB16_Pos (16U)
8221 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
8222 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
8223 #define CAN_F10R1_FB17_Pos (17U)
8224 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
8225 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
8226 #define CAN_F10R1_FB18_Pos (18U)
8227 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
8228 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
8229 #define CAN_F10R1_FB19_Pos (19U)
8230 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
8231 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
8232 #define CAN_F10R1_FB20_Pos (20U)
8233 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
8234 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
8235 #define CAN_F10R1_FB21_Pos (21U)
8236 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
8237 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
8238 #define CAN_F10R1_FB22_Pos (22U)
8239 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
8240 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
8241 #define CAN_F10R1_FB23_Pos (23U)
8242 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
8243 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
8244 #define CAN_F10R1_FB24_Pos (24U)
8245 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
8246 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
8247 #define CAN_F10R1_FB25_Pos (25U)
8248 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
8249 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
8250 #define CAN_F10R1_FB26_Pos (26U)
8251 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
8252 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
8253 #define CAN_F10R1_FB27_Pos (27U)
8254 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
8255 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
8256 #define CAN_F10R1_FB28_Pos (28U)
8257 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
8258 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
8259 #define CAN_F10R1_FB29_Pos (29U)
8260 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
8261 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
8262 #define CAN_F10R1_FB30_Pos (30U)
8263 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
8264 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
8265 #define CAN_F10R1_FB31_Pos (31U)
8266 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
8267 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
8268
8269 /******************* Bit definition for CAN_F11R1 register ******************/
8270 #define CAN_F11R1_FB0_Pos (0U)
8271 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
8272 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
8273 #define CAN_F11R1_FB1_Pos (1U)
8274 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
8275 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
8276 #define CAN_F11R1_FB2_Pos (2U)
8277 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
8278 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
8279 #define CAN_F11R1_FB3_Pos (3U)
8280 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
8281 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
8282 #define CAN_F11R1_FB4_Pos (4U)
8283 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
8284 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
8285 #define CAN_F11R1_FB5_Pos (5U)
8286 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
8287 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
8288 #define CAN_F11R1_FB6_Pos (6U)
8289 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
8290 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
8291 #define CAN_F11R1_FB7_Pos (7U)
8292 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
8293 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
8294 #define CAN_F11R1_FB8_Pos (8U)
8295 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
8296 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
8297 #define CAN_F11R1_FB9_Pos (9U)
8298 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
8299 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
8300 #define CAN_F11R1_FB10_Pos (10U)
8301 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
8302 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
8303 #define CAN_F11R1_FB11_Pos (11U)
8304 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
8305 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
8306 #define CAN_F11R1_FB12_Pos (12U)
8307 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
8308 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
8309 #define CAN_F11R1_FB13_Pos (13U)
8310 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
8311 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
8312 #define CAN_F11R1_FB14_Pos (14U)
8313 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
8314 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
8315 #define CAN_F11R1_FB15_Pos (15U)
8316 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
8317 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
8318 #define CAN_F11R1_FB16_Pos (16U)
8319 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
8320 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
8321 #define CAN_F11R1_FB17_Pos (17U)
8322 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
8323 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
8324 #define CAN_F11R1_FB18_Pos (18U)
8325 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
8326 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
8327 #define CAN_F11R1_FB19_Pos (19U)
8328 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
8329 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
8330 #define CAN_F11R1_FB20_Pos (20U)
8331 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
8332 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
8333 #define CAN_F11R1_FB21_Pos (21U)
8334 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
8335 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
8336 #define CAN_F11R1_FB22_Pos (22U)
8337 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
8338 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
8339 #define CAN_F11R1_FB23_Pos (23U)
8340 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
8341 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
8342 #define CAN_F11R1_FB24_Pos (24U)
8343 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
8344 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
8345 #define CAN_F11R1_FB25_Pos (25U)
8346 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
8347 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
8348 #define CAN_F11R1_FB26_Pos (26U)
8349 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
8350 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
8351 #define CAN_F11R1_FB27_Pos (27U)
8352 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
8353 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
8354 #define CAN_F11R1_FB28_Pos (28U)
8355 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
8356 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
8357 #define CAN_F11R1_FB29_Pos (29U)
8358 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
8359 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
8360 #define CAN_F11R1_FB30_Pos (30U)
8361 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
8362 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
8363 #define CAN_F11R1_FB31_Pos (31U)
8364 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
8365 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
8366
8367 /******************* Bit definition for CAN_F12R1 register ******************/
8368 #define CAN_F12R1_FB0_Pos (0U)
8369 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
8370 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
8371 #define CAN_F12R1_FB1_Pos (1U)
8372 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
8373 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
8374 #define CAN_F12R1_FB2_Pos (2U)
8375 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
8376 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
8377 #define CAN_F12R1_FB3_Pos (3U)
8378 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
8379 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
8380 #define CAN_F12R1_FB4_Pos (4U)
8381 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
8382 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
8383 #define CAN_F12R1_FB5_Pos (5U)
8384 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
8385 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
8386 #define CAN_F12R1_FB6_Pos (6U)
8387 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
8388 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
8389 #define CAN_F12R1_FB7_Pos (7U)
8390 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
8391 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
8392 #define CAN_F12R1_FB8_Pos (8U)
8393 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
8394 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
8395 #define CAN_F12R1_FB9_Pos (9U)
8396 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
8397 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
8398 #define CAN_F12R1_FB10_Pos (10U)
8399 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
8400 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
8401 #define CAN_F12R1_FB11_Pos (11U)
8402 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
8403 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
8404 #define CAN_F12R1_FB12_Pos (12U)
8405 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
8406 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
8407 #define CAN_F12R1_FB13_Pos (13U)
8408 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
8409 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
8410 #define CAN_F12R1_FB14_Pos (14U)
8411 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
8412 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
8413 #define CAN_F12R1_FB15_Pos (15U)
8414 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
8415 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
8416 #define CAN_F12R1_FB16_Pos (16U)
8417 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
8418 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
8419 #define CAN_F12R1_FB17_Pos (17U)
8420 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
8421 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
8422 #define CAN_F12R1_FB18_Pos (18U)
8423 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
8424 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
8425 #define CAN_F12R1_FB19_Pos (19U)
8426 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
8427 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
8428 #define CAN_F12R1_FB20_Pos (20U)
8429 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
8430 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
8431 #define CAN_F12R1_FB21_Pos (21U)
8432 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
8433 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
8434 #define CAN_F12R1_FB22_Pos (22U)
8435 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
8436 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
8437 #define CAN_F12R1_FB23_Pos (23U)
8438 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
8439 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
8440 #define CAN_F12R1_FB24_Pos (24U)
8441 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
8442 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
8443 #define CAN_F12R1_FB25_Pos (25U)
8444 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
8445 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
8446 #define CAN_F12R1_FB26_Pos (26U)
8447 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
8448 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
8449 #define CAN_F12R1_FB27_Pos (27U)
8450 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
8451 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
8452 #define CAN_F12R1_FB28_Pos (28U)
8453 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
8454 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
8455 #define CAN_F12R1_FB29_Pos (29U)
8456 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
8457 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
8458 #define CAN_F12R1_FB30_Pos (30U)
8459 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
8460 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
8461 #define CAN_F12R1_FB31_Pos (31U)
8462 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
8463 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
8464
8465 /******************* Bit definition for CAN_F13R1 register ******************/
8466 #define CAN_F13R1_FB0_Pos (0U)
8467 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
8468 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
8469 #define CAN_F13R1_FB1_Pos (1U)
8470 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
8471 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
8472 #define CAN_F13R1_FB2_Pos (2U)
8473 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
8474 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
8475 #define CAN_F13R1_FB3_Pos (3U)
8476 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
8477 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
8478 #define CAN_F13R1_FB4_Pos (4U)
8479 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
8480 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
8481 #define CAN_F13R1_FB5_Pos (5U)
8482 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
8483 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
8484 #define CAN_F13R1_FB6_Pos (6U)
8485 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
8486 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
8487 #define CAN_F13R1_FB7_Pos (7U)
8488 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
8489 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
8490 #define CAN_F13R1_FB8_Pos (8U)
8491 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
8492 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
8493 #define CAN_F13R1_FB9_Pos (9U)
8494 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
8495 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
8496 #define CAN_F13R1_FB10_Pos (10U)
8497 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
8498 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
8499 #define CAN_F13R1_FB11_Pos (11U)
8500 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
8501 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
8502 #define CAN_F13R1_FB12_Pos (12U)
8503 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
8504 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
8505 #define CAN_F13R1_FB13_Pos (13U)
8506 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
8507 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
8508 #define CAN_F13R1_FB14_Pos (14U)
8509 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
8510 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
8511 #define CAN_F13R1_FB15_Pos (15U)
8512 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
8513 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
8514 #define CAN_F13R1_FB16_Pos (16U)
8515 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
8516 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
8517 #define CAN_F13R1_FB17_Pos (17U)
8518 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
8519 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
8520 #define CAN_F13R1_FB18_Pos (18U)
8521 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
8522 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
8523 #define CAN_F13R1_FB19_Pos (19U)
8524 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
8525 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
8526 #define CAN_F13R1_FB20_Pos (20U)
8527 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
8528 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
8529 #define CAN_F13R1_FB21_Pos (21U)
8530 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
8531 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
8532 #define CAN_F13R1_FB22_Pos (22U)
8533 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
8534 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
8535 #define CAN_F13R1_FB23_Pos (23U)
8536 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
8537 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
8538 #define CAN_F13R1_FB24_Pos (24U)
8539 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
8540 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
8541 #define CAN_F13R1_FB25_Pos (25U)
8542 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
8543 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
8544 #define CAN_F13R1_FB26_Pos (26U)
8545 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
8546 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
8547 #define CAN_F13R1_FB27_Pos (27U)
8548 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
8549 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
8550 #define CAN_F13R1_FB28_Pos (28U)
8551 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
8552 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
8553 #define CAN_F13R1_FB29_Pos (29U)
8554 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
8555 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
8556 #define CAN_F13R1_FB30_Pos (30U)
8557 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
8558 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
8559 #define CAN_F13R1_FB31_Pos (31U)
8560 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
8561 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
8562
8563 /******************* Bit definition for CAN_F0R2 register *******************/
8564 #define CAN_F0R2_FB0_Pos (0U)
8565 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
8566 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
8567 #define CAN_F0R2_FB1_Pos (1U)
8568 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
8569 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
8570 #define CAN_F0R2_FB2_Pos (2U)
8571 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
8572 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
8573 #define CAN_F0R2_FB3_Pos (3U)
8574 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
8575 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
8576 #define CAN_F0R2_FB4_Pos (4U)
8577 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
8578 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
8579 #define CAN_F0R2_FB5_Pos (5U)
8580 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
8581 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
8582 #define CAN_F0R2_FB6_Pos (6U)
8583 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
8584 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
8585 #define CAN_F0R2_FB7_Pos (7U)
8586 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
8587 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
8588 #define CAN_F0R2_FB8_Pos (8U)
8589 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
8590 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
8591 #define CAN_F0R2_FB9_Pos (9U)
8592 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
8593 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
8594 #define CAN_F0R2_FB10_Pos (10U)
8595 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
8596 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
8597 #define CAN_F0R2_FB11_Pos (11U)
8598 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
8599 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
8600 #define CAN_F0R2_FB12_Pos (12U)
8601 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
8602 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
8603 #define CAN_F0R2_FB13_Pos (13U)
8604 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
8605 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
8606 #define CAN_F0R2_FB14_Pos (14U)
8607 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
8608 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
8609 #define CAN_F0R2_FB15_Pos (15U)
8610 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
8611 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
8612 #define CAN_F0R2_FB16_Pos (16U)
8613 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
8614 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
8615 #define CAN_F0R2_FB17_Pos (17U)
8616 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
8617 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
8618 #define CAN_F0R2_FB18_Pos (18U)
8619 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
8620 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
8621 #define CAN_F0R2_FB19_Pos (19U)
8622 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
8623 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
8624 #define CAN_F0R2_FB20_Pos (20U)
8625 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
8626 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
8627 #define CAN_F0R2_FB21_Pos (21U)
8628 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
8629 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
8630 #define CAN_F0R2_FB22_Pos (22U)
8631 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
8632 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
8633 #define CAN_F0R2_FB23_Pos (23U)
8634 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
8635 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
8636 #define CAN_F0R2_FB24_Pos (24U)
8637 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
8638 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
8639 #define CAN_F0R2_FB25_Pos (25U)
8640 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
8641 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
8642 #define CAN_F0R2_FB26_Pos (26U)
8643 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
8644 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
8645 #define CAN_F0R2_FB27_Pos (27U)
8646 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
8647 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
8648 #define CAN_F0R2_FB28_Pos (28U)
8649 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
8650 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
8651 #define CAN_F0R2_FB29_Pos (29U)
8652 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
8653 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
8654 #define CAN_F0R2_FB30_Pos (30U)
8655 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
8656 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
8657 #define CAN_F0R2_FB31_Pos (31U)
8658 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
8659 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
8660
8661 /******************* Bit definition for CAN_F1R2 register *******************/
8662 #define CAN_F1R2_FB0_Pos (0U)
8663 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
8664 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
8665 #define CAN_F1R2_FB1_Pos (1U)
8666 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
8667 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
8668 #define CAN_F1R2_FB2_Pos (2U)
8669 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
8670 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
8671 #define CAN_F1R2_FB3_Pos (3U)
8672 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
8673 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
8674 #define CAN_F1R2_FB4_Pos (4U)
8675 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
8676 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
8677 #define CAN_F1R2_FB5_Pos (5U)
8678 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
8679 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
8680 #define CAN_F1R2_FB6_Pos (6U)
8681 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
8682 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
8683 #define CAN_F1R2_FB7_Pos (7U)
8684 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
8685 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
8686 #define CAN_F1R2_FB8_Pos (8U)
8687 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
8688 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
8689 #define CAN_F1R2_FB9_Pos (9U)
8690 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
8691 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
8692 #define CAN_F1R2_FB10_Pos (10U)
8693 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
8694 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
8695 #define CAN_F1R2_FB11_Pos (11U)
8696 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
8697 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
8698 #define CAN_F1R2_FB12_Pos (12U)
8699 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
8700 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
8701 #define CAN_F1R2_FB13_Pos (13U)
8702 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
8703 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
8704 #define CAN_F1R2_FB14_Pos (14U)
8705 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
8706 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
8707 #define CAN_F1R2_FB15_Pos (15U)
8708 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
8709 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
8710 #define CAN_F1R2_FB16_Pos (16U)
8711 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
8712 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
8713 #define CAN_F1R2_FB17_Pos (17U)
8714 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
8715 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
8716 #define CAN_F1R2_FB18_Pos (18U)
8717 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
8718 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
8719 #define CAN_F1R2_FB19_Pos (19U)
8720 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
8721 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
8722 #define CAN_F1R2_FB20_Pos (20U)
8723 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
8724 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
8725 #define CAN_F1R2_FB21_Pos (21U)
8726 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
8727 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
8728 #define CAN_F1R2_FB22_Pos (22U)
8729 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
8730 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
8731 #define CAN_F1R2_FB23_Pos (23U)
8732 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
8733 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
8734 #define CAN_F1R2_FB24_Pos (24U)
8735 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
8736 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
8737 #define CAN_F1R2_FB25_Pos (25U)
8738 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
8739 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
8740 #define CAN_F1R2_FB26_Pos (26U)
8741 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
8742 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
8743 #define CAN_F1R2_FB27_Pos (27U)
8744 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
8745 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
8746 #define CAN_F1R2_FB28_Pos (28U)
8747 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
8748 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
8749 #define CAN_F1R2_FB29_Pos (29U)
8750 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
8751 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
8752 #define CAN_F1R2_FB30_Pos (30U)
8753 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
8754 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
8755 #define CAN_F1R2_FB31_Pos (31U)
8756 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
8757 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
8758
8759 /******************* Bit definition for CAN_F2R2 register *******************/
8760 #define CAN_F2R2_FB0_Pos (0U)
8761 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
8762 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
8763 #define CAN_F2R2_FB1_Pos (1U)
8764 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
8765 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
8766 #define CAN_F2R2_FB2_Pos (2U)
8767 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
8768 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
8769 #define CAN_F2R2_FB3_Pos (3U)
8770 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
8771 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
8772 #define CAN_F2R2_FB4_Pos (4U)
8773 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
8774 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
8775 #define CAN_F2R2_FB5_Pos (5U)
8776 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
8777 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
8778 #define CAN_F2R2_FB6_Pos (6U)
8779 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
8780 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
8781 #define CAN_F2R2_FB7_Pos (7U)
8782 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
8783 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
8784 #define CAN_F2R2_FB8_Pos (8U)
8785 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
8786 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
8787 #define CAN_F2R2_FB9_Pos (9U)
8788 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
8789 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
8790 #define CAN_F2R2_FB10_Pos (10U)
8791 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
8792 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
8793 #define CAN_F2R2_FB11_Pos (11U)
8794 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
8795 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
8796 #define CAN_F2R2_FB12_Pos (12U)
8797 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
8798 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
8799 #define CAN_F2R2_FB13_Pos (13U)
8800 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
8801 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
8802 #define CAN_F2R2_FB14_Pos (14U)
8803 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
8804 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
8805 #define CAN_F2R2_FB15_Pos (15U)
8806 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
8807 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
8808 #define CAN_F2R2_FB16_Pos (16U)
8809 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
8810 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
8811 #define CAN_F2R2_FB17_Pos (17U)
8812 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
8813 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
8814 #define CAN_F2R2_FB18_Pos (18U)
8815 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
8816 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
8817 #define CAN_F2R2_FB19_Pos (19U)
8818 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
8819 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
8820 #define CAN_F2R2_FB20_Pos (20U)
8821 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
8822 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
8823 #define CAN_F2R2_FB21_Pos (21U)
8824 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
8825 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
8826 #define CAN_F2R2_FB22_Pos (22U)
8827 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
8828 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
8829 #define CAN_F2R2_FB23_Pos (23U)
8830 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
8831 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
8832 #define CAN_F2R2_FB24_Pos (24U)
8833 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
8834 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
8835 #define CAN_F2R2_FB25_Pos (25U)
8836 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
8837 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
8838 #define CAN_F2R2_FB26_Pos (26U)
8839 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
8840 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
8841 #define CAN_F2R2_FB27_Pos (27U)
8842 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
8843 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
8844 #define CAN_F2R2_FB28_Pos (28U)
8845 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
8846 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
8847 #define CAN_F2R2_FB29_Pos (29U)
8848 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
8849 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
8850 #define CAN_F2R2_FB30_Pos (30U)
8851 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
8852 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
8853 #define CAN_F2R2_FB31_Pos (31U)
8854 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
8855 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
8856
8857 /******************* Bit definition for CAN_F3R2 register *******************/
8858 #define CAN_F3R2_FB0_Pos (0U)
8859 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
8860 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
8861 #define CAN_F3R2_FB1_Pos (1U)
8862 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
8863 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
8864 #define CAN_F3R2_FB2_Pos (2U)
8865 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
8866 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
8867 #define CAN_F3R2_FB3_Pos (3U)
8868 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
8869 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
8870 #define CAN_F3R2_FB4_Pos (4U)
8871 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
8872 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
8873 #define CAN_F3R2_FB5_Pos (5U)
8874 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
8875 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
8876 #define CAN_F3R2_FB6_Pos (6U)
8877 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
8878 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
8879 #define CAN_F3R2_FB7_Pos (7U)
8880 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
8881 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
8882 #define CAN_F3R2_FB8_Pos (8U)
8883 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
8884 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
8885 #define CAN_F3R2_FB9_Pos (9U)
8886 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
8887 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
8888 #define CAN_F3R2_FB10_Pos (10U)
8889 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
8890 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
8891 #define CAN_F3R2_FB11_Pos (11U)
8892 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
8893 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
8894 #define CAN_F3R2_FB12_Pos (12U)
8895 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
8896 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
8897 #define CAN_F3R2_FB13_Pos (13U)
8898 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
8899 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
8900 #define CAN_F3R2_FB14_Pos (14U)
8901 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
8902 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
8903 #define CAN_F3R2_FB15_Pos (15U)
8904 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
8905 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
8906 #define CAN_F3R2_FB16_Pos (16U)
8907 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
8908 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
8909 #define CAN_F3R2_FB17_Pos (17U)
8910 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
8911 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
8912 #define CAN_F3R2_FB18_Pos (18U)
8913 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
8914 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
8915 #define CAN_F3R2_FB19_Pos (19U)
8916 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
8917 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
8918 #define CAN_F3R2_FB20_Pos (20U)
8919 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
8920 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
8921 #define CAN_F3R2_FB21_Pos (21U)
8922 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
8923 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
8924 #define CAN_F3R2_FB22_Pos (22U)
8925 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
8926 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
8927 #define CAN_F3R2_FB23_Pos (23U)
8928 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
8929 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
8930 #define CAN_F3R2_FB24_Pos (24U)
8931 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
8932 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
8933 #define CAN_F3R2_FB25_Pos (25U)
8934 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
8935 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
8936 #define CAN_F3R2_FB26_Pos (26U)
8937 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
8938 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
8939 #define CAN_F3R2_FB27_Pos (27U)
8940 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
8941 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
8942 #define CAN_F3R2_FB28_Pos (28U)
8943 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
8944 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
8945 #define CAN_F3R2_FB29_Pos (29U)
8946 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
8947 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
8948 #define CAN_F3R2_FB30_Pos (30U)
8949 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
8950 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
8951 #define CAN_F3R2_FB31_Pos (31U)
8952 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
8953 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
8954
8955 /******************* Bit definition for CAN_F4R2 register *******************/
8956 #define CAN_F4R2_FB0_Pos (0U)
8957 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
8958 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
8959 #define CAN_F4R2_FB1_Pos (1U)
8960 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
8961 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
8962 #define CAN_F4R2_FB2_Pos (2U)
8963 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
8964 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
8965 #define CAN_F4R2_FB3_Pos (3U)
8966 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
8967 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
8968 #define CAN_F4R2_FB4_Pos (4U)
8969 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
8970 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
8971 #define CAN_F4R2_FB5_Pos (5U)
8972 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
8973 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
8974 #define CAN_F4R2_FB6_Pos (6U)
8975 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
8976 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
8977 #define CAN_F4R2_FB7_Pos (7U)
8978 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
8979 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
8980 #define CAN_F4R2_FB8_Pos (8U)
8981 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
8982 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
8983 #define CAN_F4R2_FB9_Pos (9U)
8984 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
8985 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
8986 #define CAN_F4R2_FB10_Pos (10U)
8987 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
8988 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
8989 #define CAN_F4R2_FB11_Pos (11U)
8990 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
8991 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
8992 #define CAN_F4R2_FB12_Pos (12U)
8993 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
8994 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
8995 #define CAN_F4R2_FB13_Pos (13U)
8996 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
8997 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
8998 #define CAN_F4R2_FB14_Pos (14U)
8999 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
9000 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
9001 #define CAN_F4R2_FB15_Pos (15U)
9002 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
9003 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
9004 #define CAN_F4R2_FB16_Pos (16U)
9005 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
9006 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
9007 #define CAN_F4R2_FB17_Pos (17U)
9008 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
9009 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
9010 #define CAN_F4R2_FB18_Pos (18U)
9011 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
9012 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
9013 #define CAN_F4R2_FB19_Pos (19U)
9014 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
9015 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
9016 #define CAN_F4R2_FB20_Pos (20U)
9017 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
9018 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
9019 #define CAN_F4R2_FB21_Pos (21U)
9020 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
9021 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
9022 #define CAN_F4R2_FB22_Pos (22U)
9023 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
9024 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
9025 #define CAN_F4R2_FB23_Pos (23U)
9026 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
9027 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
9028 #define CAN_F4R2_FB24_Pos (24U)
9029 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
9030 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
9031 #define CAN_F4R2_FB25_Pos (25U)
9032 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
9033 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
9034 #define CAN_F4R2_FB26_Pos (26U)
9035 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
9036 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
9037 #define CAN_F4R2_FB27_Pos (27U)
9038 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
9039 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
9040 #define CAN_F4R2_FB28_Pos (28U)
9041 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
9042 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
9043 #define CAN_F4R2_FB29_Pos (29U)
9044 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
9045 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
9046 #define CAN_F4R2_FB30_Pos (30U)
9047 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
9048 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
9049 #define CAN_F4R2_FB31_Pos (31U)
9050 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
9051 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
9052
9053 /******************* Bit definition for CAN_F5R2 register *******************/
9054 #define CAN_F5R2_FB0_Pos (0U)
9055 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
9056 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
9057 #define CAN_F5R2_FB1_Pos (1U)
9058 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
9059 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
9060 #define CAN_F5R2_FB2_Pos (2U)
9061 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
9062 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
9063 #define CAN_F5R2_FB3_Pos (3U)
9064 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
9065 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
9066 #define CAN_F5R2_FB4_Pos (4U)
9067 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
9068 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
9069 #define CAN_F5R2_FB5_Pos (5U)
9070 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
9071 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
9072 #define CAN_F5R2_FB6_Pos (6U)
9073 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
9074 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
9075 #define CAN_F5R2_FB7_Pos (7U)
9076 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
9077 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
9078 #define CAN_F5R2_FB8_Pos (8U)
9079 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
9080 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
9081 #define CAN_F5R2_FB9_Pos (9U)
9082 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
9083 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
9084 #define CAN_F5R2_FB10_Pos (10U)
9085 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
9086 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
9087 #define CAN_F5R2_FB11_Pos (11U)
9088 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
9089 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
9090 #define CAN_F5R2_FB12_Pos (12U)
9091 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
9092 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
9093 #define CAN_F5R2_FB13_Pos (13U)
9094 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
9095 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
9096 #define CAN_F5R2_FB14_Pos (14U)
9097 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
9098 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
9099 #define CAN_F5R2_FB15_Pos (15U)
9100 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
9101 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
9102 #define CAN_F5R2_FB16_Pos (16U)
9103 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
9104 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
9105 #define CAN_F5R2_FB17_Pos (17U)
9106 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
9107 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
9108 #define CAN_F5R2_FB18_Pos (18U)
9109 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
9110 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
9111 #define CAN_F5R2_FB19_Pos (19U)
9112 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
9113 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
9114 #define CAN_F5R2_FB20_Pos (20U)
9115 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
9116 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
9117 #define CAN_F5R2_FB21_Pos (21U)
9118 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
9119 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
9120 #define CAN_F5R2_FB22_Pos (22U)
9121 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
9122 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
9123 #define CAN_F5R2_FB23_Pos (23U)
9124 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
9125 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
9126 #define CAN_F5R2_FB24_Pos (24U)
9127 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
9128 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
9129 #define CAN_F5R2_FB25_Pos (25U)
9130 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
9131 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
9132 #define CAN_F5R2_FB26_Pos (26U)
9133 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
9134 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
9135 #define CAN_F5R2_FB27_Pos (27U)
9136 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
9137 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
9138 #define CAN_F5R2_FB28_Pos (28U)
9139 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
9140 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
9141 #define CAN_F5R2_FB29_Pos (29U)
9142 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
9143 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
9144 #define CAN_F5R2_FB30_Pos (30U)
9145 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
9146 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
9147 #define CAN_F5R2_FB31_Pos (31U)
9148 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
9149 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
9150
9151 /******************* Bit definition for CAN_F6R2 register *******************/
9152 #define CAN_F6R2_FB0_Pos (0U)
9153 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
9154 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
9155 #define CAN_F6R2_FB1_Pos (1U)
9156 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
9157 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
9158 #define CAN_F6R2_FB2_Pos (2U)
9159 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
9160 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
9161 #define CAN_F6R2_FB3_Pos (3U)
9162 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
9163 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
9164 #define CAN_F6R2_FB4_Pos (4U)
9165 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
9166 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
9167 #define CAN_F6R2_FB5_Pos (5U)
9168 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
9169 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
9170 #define CAN_F6R2_FB6_Pos (6U)
9171 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
9172 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
9173 #define CAN_F6R2_FB7_Pos (7U)
9174 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
9175 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
9176 #define CAN_F6R2_FB8_Pos (8U)
9177 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
9178 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
9179 #define CAN_F6R2_FB9_Pos (9U)
9180 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
9181 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
9182 #define CAN_F6R2_FB10_Pos (10U)
9183 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
9184 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
9185 #define CAN_F6R2_FB11_Pos (11U)
9186 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
9187 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
9188 #define CAN_F6R2_FB12_Pos (12U)
9189 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
9190 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
9191 #define CAN_F6R2_FB13_Pos (13U)
9192 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
9193 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
9194 #define CAN_F6R2_FB14_Pos (14U)
9195 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
9196 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
9197 #define CAN_F6R2_FB15_Pos (15U)
9198 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
9199 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
9200 #define CAN_F6R2_FB16_Pos (16U)
9201 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
9202 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
9203 #define CAN_F6R2_FB17_Pos (17U)
9204 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
9205 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
9206 #define CAN_F6R2_FB18_Pos (18U)
9207 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
9208 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
9209 #define CAN_F6R2_FB19_Pos (19U)
9210 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
9211 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
9212 #define CAN_F6R2_FB20_Pos (20U)
9213 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
9214 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
9215 #define CAN_F6R2_FB21_Pos (21U)
9216 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
9217 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
9218 #define CAN_F6R2_FB22_Pos (22U)
9219 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
9220 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
9221 #define CAN_F6R2_FB23_Pos (23U)
9222 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
9223 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
9224 #define CAN_F6R2_FB24_Pos (24U)
9225 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
9226 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
9227 #define CAN_F6R2_FB25_Pos (25U)
9228 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
9229 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
9230 #define CAN_F6R2_FB26_Pos (26U)
9231 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
9232 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
9233 #define CAN_F6R2_FB27_Pos (27U)
9234 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
9235 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
9236 #define CAN_F6R2_FB28_Pos (28U)
9237 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
9238 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
9239 #define CAN_F6R2_FB29_Pos (29U)
9240 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
9241 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
9242 #define CAN_F6R2_FB30_Pos (30U)
9243 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
9244 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
9245 #define CAN_F6R2_FB31_Pos (31U)
9246 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
9247 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
9248
9249 /******************* Bit definition for CAN_F7R2 register *******************/
9250 #define CAN_F7R2_FB0_Pos (0U)
9251 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
9252 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
9253 #define CAN_F7R2_FB1_Pos (1U)
9254 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
9255 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
9256 #define CAN_F7R2_FB2_Pos (2U)
9257 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
9258 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
9259 #define CAN_F7R2_FB3_Pos (3U)
9260 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
9261 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
9262 #define CAN_F7R2_FB4_Pos (4U)
9263 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
9264 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
9265 #define CAN_F7R2_FB5_Pos (5U)
9266 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
9267 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
9268 #define CAN_F7R2_FB6_Pos (6U)
9269 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
9270 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
9271 #define CAN_F7R2_FB7_Pos (7U)
9272 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
9273 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
9274 #define CAN_F7R2_FB8_Pos (8U)
9275 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
9276 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
9277 #define CAN_F7R2_FB9_Pos (9U)
9278 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
9279 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
9280 #define CAN_F7R2_FB10_Pos (10U)
9281 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
9282 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
9283 #define CAN_F7R2_FB11_Pos (11U)
9284 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
9285 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
9286 #define CAN_F7R2_FB12_Pos (12U)
9287 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
9288 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
9289 #define CAN_F7R2_FB13_Pos (13U)
9290 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
9291 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
9292 #define CAN_F7R2_FB14_Pos (14U)
9293 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
9294 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
9295 #define CAN_F7R2_FB15_Pos (15U)
9296 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
9297 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
9298 #define CAN_F7R2_FB16_Pos (16U)
9299 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
9300 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
9301 #define CAN_F7R2_FB17_Pos (17U)
9302 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
9303 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
9304 #define CAN_F7R2_FB18_Pos (18U)
9305 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
9306 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
9307 #define CAN_F7R2_FB19_Pos (19U)
9308 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
9309 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
9310 #define CAN_F7R2_FB20_Pos (20U)
9311 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
9312 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
9313 #define CAN_F7R2_FB21_Pos (21U)
9314 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
9315 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
9316 #define CAN_F7R2_FB22_Pos (22U)
9317 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
9318 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
9319 #define CAN_F7R2_FB23_Pos (23U)
9320 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
9321 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
9322 #define CAN_F7R2_FB24_Pos (24U)
9323 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
9324 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
9325 #define CAN_F7R2_FB25_Pos (25U)
9326 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
9327 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
9328 #define CAN_F7R2_FB26_Pos (26U)
9329 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
9330 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
9331 #define CAN_F7R2_FB27_Pos (27U)
9332 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
9333 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
9334 #define CAN_F7R2_FB28_Pos (28U)
9335 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
9336 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
9337 #define CAN_F7R2_FB29_Pos (29U)
9338 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
9339 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
9340 #define CAN_F7R2_FB30_Pos (30U)
9341 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
9342 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
9343 #define CAN_F7R2_FB31_Pos (31U)
9344 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
9345 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
9346
9347 /******************* Bit definition for CAN_F8R2 register *******************/
9348 #define CAN_F8R2_FB0_Pos (0U)
9349 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
9350 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
9351 #define CAN_F8R2_FB1_Pos (1U)
9352 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
9353 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
9354 #define CAN_F8R2_FB2_Pos (2U)
9355 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
9356 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
9357 #define CAN_F8R2_FB3_Pos (3U)
9358 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
9359 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
9360 #define CAN_F8R2_FB4_Pos (4U)
9361 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
9362 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
9363 #define CAN_F8R2_FB5_Pos (5U)
9364 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
9365 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
9366 #define CAN_F8R2_FB6_Pos (6U)
9367 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
9368 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
9369 #define CAN_F8R2_FB7_Pos (7U)
9370 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
9371 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
9372 #define CAN_F8R2_FB8_Pos (8U)
9373 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
9374 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
9375 #define CAN_F8R2_FB9_Pos (9U)
9376 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
9377 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
9378 #define CAN_F8R2_FB10_Pos (10U)
9379 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
9380 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
9381 #define CAN_F8R2_FB11_Pos (11U)
9382 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
9383 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
9384 #define CAN_F8R2_FB12_Pos (12U)
9385 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
9386 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
9387 #define CAN_F8R2_FB13_Pos (13U)
9388 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
9389 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
9390 #define CAN_F8R2_FB14_Pos (14U)
9391 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
9392 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
9393 #define CAN_F8R2_FB15_Pos (15U)
9394 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
9395 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
9396 #define CAN_F8R2_FB16_Pos (16U)
9397 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
9398 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
9399 #define CAN_F8R2_FB17_Pos (17U)
9400 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
9401 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
9402 #define CAN_F8R2_FB18_Pos (18U)
9403 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
9404 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
9405 #define CAN_F8R2_FB19_Pos (19U)
9406 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
9407 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
9408 #define CAN_F8R2_FB20_Pos (20U)
9409 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
9410 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
9411 #define CAN_F8R2_FB21_Pos (21U)
9412 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
9413 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
9414 #define CAN_F8R2_FB22_Pos (22U)
9415 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
9416 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
9417 #define CAN_F8R2_FB23_Pos (23U)
9418 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
9419 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
9420 #define CAN_F8R2_FB24_Pos (24U)
9421 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
9422 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
9423 #define CAN_F8R2_FB25_Pos (25U)
9424 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
9425 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
9426 #define CAN_F8R2_FB26_Pos (26U)
9427 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
9428 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
9429 #define CAN_F8R2_FB27_Pos (27U)
9430 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
9431 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
9432 #define CAN_F8R2_FB28_Pos (28U)
9433 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
9434 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
9435 #define CAN_F8R2_FB29_Pos (29U)
9436 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
9437 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
9438 #define CAN_F8R2_FB30_Pos (30U)
9439 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
9440 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
9441 #define CAN_F8R2_FB31_Pos (31U)
9442 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
9443 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
9444
9445 /******************* Bit definition for CAN_F9R2 register *******************/
9446 #define CAN_F9R2_FB0_Pos (0U)
9447 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
9448 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
9449 #define CAN_F9R2_FB1_Pos (1U)
9450 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
9451 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
9452 #define CAN_F9R2_FB2_Pos (2U)
9453 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
9454 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
9455 #define CAN_F9R2_FB3_Pos (3U)
9456 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
9457 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
9458 #define CAN_F9R2_FB4_Pos (4U)
9459 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
9460 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
9461 #define CAN_F9R2_FB5_Pos (5U)
9462 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
9463 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
9464 #define CAN_F9R2_FB6_Pos (6U)
9465 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
9466 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
9467 #define CAN_F9R2_FB7_Pos (7U)
9468 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
9469 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
9470 #define CAN_F9R2_FB8_Pos (8U)
9471 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
9472 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
9473 #define CAN_F9R2_FB9_Pos (9U)
9474 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
9475 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
9476 #define CAN_F9R2_FB10_Pos (10U)
9477 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
9478 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
9479 #define CAN_F9R2_FB11_Pos (11U)
9480 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
9481 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
9482 #define CAN_F9R2_FB12_Pos (12U)
9483 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
9484 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
9485 #define CAN_F9R2_FB13_Pos (13U)
9486 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
9487 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
9488 #define CAN_F9R2_FB14_Pos (14U)
9489 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
9490 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
9491 #define CAN_F9R2_FB15_Pos (15U)
9492 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
9493 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
9494 #define CAN_F9R2_FB16_Pos (16U)
9495 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
9496 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
9497 #define CAN_F9R2_FB17_Pos (17U)
9498 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
9499 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
9500 #define CAN_F9R2_FB18_Pos (18U)
9501 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
9502 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
9503 #define CAN_F9R2_FB19_Pos (19U)
9504 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
9505 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
9506 #define CAN_F9R2_FB20_Pos (20U)
9507 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
9508 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
9509 #define CAN_F9R2_FB21_Pos (21U)
9510 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
9511 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
9512 #define CAN_F9R2_FB22_Pos (22U)
9513 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
9514 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
9515 #define CAN_F9R2_FB23_Pos (23U)
9516 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
9517 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
9518 #define CAN_F9R2_FB24_Pos (24U)
9519 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
9520 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
9521 #define CAN_F9R2_FB25_Pos (25U)
9522 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
9523 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
9524 #define CAN_F9R2_FB26_Pos (26U)
9525 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
9526 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
9527 #define CAN_F9R2_FB27_Pos (27U)
9528 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
9529 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
9530 #define CAN_F9R2_FB28_Pos (28U)
9531 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
9532 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
9533 #define CAN_F9R2_FB29_Pos (29U)
9534 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
9535 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
9536 #define CAN_F9R2_FB30_Pos (30U)
9537 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
9538 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
9539 #define CAN_F9R2_FB31_Pos (31U)
9540 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
9541 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
9542
9543 /******************* Bit definition for CAN_F10R2 register ******************/
9544 #define CAN_F10R2_FB0_Pos (0U)
9545 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
9546 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
9547 #define CAN_F10R2_FB1_Pos (1U)
9548 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
9549 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
9550 #define CAN_F10R2_FB2_Pos (2U)
9551 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
9552 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
9553 #define CAN_F10R2_FB3_Pos (3U)
9554 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
9555 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
9556 #define CAN_F10R2_FB4_Pos (4U)
9557 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
9558 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
9559 #define CAN_F10R2_FB5_Pos (5U)
9560 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
9561 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
9562 #define CAN_F10R2_FB6_Pos (6U)
9563 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
9564 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
9565 #define CAN_F10R2_FB7_Pos (7U)
9566 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
9567 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
9568 #define CAN_F10R2_FB8_Pos (8U)
9569 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
9570 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
9571 #define CAN_F10R2_FB9_Pos (9U)
9572 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
9573 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
9574 #define CAN_F10R2_FB10_Pos (10U)
9575 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
9576 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
9577 #define CAN_F10R2_FB11_Pos (11U)
9578 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
9579 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
9580 #define CAN_F10R2_FB12_Pos (12U)
9581 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
9582 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
9583 #define CAN_F10R2_FB13_Pos (13U)
9584 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
9585 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
9586 #define CAN_F10R2_FB14_Pos (14U)
9587 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
9588 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
9589 #define CAN_F10R2_FB15_Pos (15U)
9590 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
9591 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
9592 #define CAN_F10R2_FB16_Pos (16U)
9593 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
9594 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
9595 #define CAN_F10R2_FB17_Pos (17U)
9596 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
9597 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
9598 #define CAN_F10R2_FB18_Pos (18U)
9599 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
9600 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
9601 #define CAN_F10R2_FB19_Pos (19U)
9602 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
9603 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
9604 #define CAN_F10R2_FB20_Pos (20U)
9605 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
9606 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
9607 #define CAN_F10R2_FB21_Pos (21U)
9608 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
9609 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
9610 #define CAN_F10R2_FB22_Pos (22U)
9611 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
9612 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
9613 #define CAN_F10R2_FB23_Pos (23U)
9614 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
9615 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
9616 #define CAN_F10R2_FB24_Pos (24U)
9617 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
9618 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
9619 #define CAN_F10R2_FB25_Pos (25U)
9620 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
9621 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
9622 #define CAN_F10R2_FB26_Pos (26U)
9623 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
9624 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
9625 #define CAN_F10R2_FB27_Pos (27U)
9626 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
9627 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
9628 #define CAN_F10R2_FB28_Pos (28U)
9629 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
9630 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
9631 #define CAN_F10R2_FB29_Pos (29U)
9632 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
9633 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
9634 #define CAN_F10R2_FB30_Pos (30U)
9635 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
9636 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
9637 #define CAN_F10R2_FB31_Pos (31U)
9638 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
9639 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
9640
9641 /******************* Bit definition for CAN_F11R2 register ******************/
9642 #define CAN_F11R2_FB0_Pos (0U)
9643 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
9644 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
9645 #define CAN_F11R2_FB1_Pos (1U)
9646 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
9647 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
9648 #define CAN_F11R2_FB2_Pos (2U)
9649 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
9650 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
9651 #define CAN_F11R2_FB3_Pos (3U)
9652 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
9653 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
9654 #define CAN_F11R2_FB4_Pos (4U)
9655 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
9656 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
9657 #define CAN_F11R2_FB5_Pos (5U)
9658 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
9659 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
9660 #define CAN_F11R2_FB6_Pos (6U)
9661 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
9662 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
9663 #define CAN_F11R2_FB7_Pos (7U)
9664 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
9665 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
9666 #define CAN_F11R2_FB8_Pos (8U)
9667 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
9668 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
9669 #define CAN_F11R2_FB9_Pos (9U)
9670 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
9671 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
9672 #define CAN_F11R2_FB10_Pos (10U)
9673 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
9674 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
9675 #define CAN_F11R2_FB11_Pos (11U)
9676 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
9677 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
9678 #define CAN_F11R2_FB12_Pos (12U)
9679 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
9680 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
9681 #define CAN_F11R2_FB13_Pos (13U)
9682 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
9683 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
9684 #define CAN_F11R2_FB14_Pos (14U)
9685 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
9686 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
9687 #define CAN_F11R2_FB15_Pos (15U)
9688 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
9689 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
9690 #define CAN_F11R2_FB16_Pos (16U)
9691 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
9692 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
9693 #define CAN_F11R2_FB17_Pos (17U)
9694 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
9695 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
9696 #define CAN_F11R2_FB18_Pos (18U)
9697 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
9698 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
9699 #define CAN_F11R2_FB19_Pos (19U)
9700 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
9701 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
9702 #define CAN_F11R2_FB20_Pos (20U)
9703 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
9704 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
9705 #define CAN_F11R2_FB21_Pos (21U)
9706 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
9707 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
9708 #define CAN_F11R2_FB22_Pos (22U)
9709 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
9710 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
9711 #define CAN_F11R2_FB23_Pos (23U)
9712 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
9713 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
9714 #define CAN_F11R2_FB24_Pos (24U)
9715 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
9716 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
9717 #define CAN_F11R2_FB25_Pos (25U)
9718 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
9719 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
9720 #define CAN_F11R2_FB26_Pos (26U)
9721 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
9722 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
9723 #define CAN_F11R2_FB27_Pos (27U)
9724 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
9725 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
9726 #define CAN_F11R2_FB28_Pos (28U)
9727 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
9728 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
9729 #define CAN_F11R2_FB29_Pos (29U)
9730 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
9731 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
9732 #define CAN_F11R2_FB30_Pos (30U)
9733 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
9734 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
9735 #define CAN_F11R2_FB31_Pos (31U)
9736 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
9737 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
9738
9739 /******************* Bit definition for CAN_F12R2 register ******************/
9740 #define CAN_F12R2_FB0_Pos (0U)
9741 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
9742 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
9743 #define CAN_F12R2_FB1_Pos (1U)
9744 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
9745 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
9746 #define CAN_F12R2_FB2_Pos (2U)
9747 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
9748 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
9749 #define CAN_F12R2_FB3_Pos (3U)
9750 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
9751 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
9752 #define CAN_F12R2_FB4_Pos (4U)
9753 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
9754 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
9755 #define CAN_F12R2_FB5_Pos (5U)
9756 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
9757 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
9758 #define CAN_F12R2_FB6_Pos (6U)
9759 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
9760 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
9761 #define CAN_F12R2_FB7_Pos (7U)
9762 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
9763 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
9764 #define CAN_F12R2_FB8_Pos (8U)
9765 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
9766 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
9767 #define CAN_F12R2_FB9_Pos (9U)
9768 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
9769 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
9770 #define CAN_F12R2_FB10_Pos (10U)
9771 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
9772 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
9773 #define CAN_F12R2_FB11_Pos (11U)
9774 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
9775 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
9776 #define CAN_F12R2_FB12_Pos (12U)
9777 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
9778 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
9779 #define CAN_F12R2_FB13_Pos (13U)
9780 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
9781 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
9782 #define CAN_F12R2_FB14_Pos (14U)
9783 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
9784 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
9785 #define CAN_F12R2_FB15_Pos (15U)
9786 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
9787 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
9788 #define CAN_F12R2_FB16_Pos (16U)
9789 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
9790 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
9791 #define CAN_F12R2_FB17_Pos (17U)
9792 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
9793 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
9794 #define CAN_F12R2_FB18_Pos (18U)
9795 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
9796 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
9797 #define CAN_F12R2_FB19_Pos (19U)
9798 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
9799 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
9800 #define CAN_F12R2_FB20_Pos (20U)
9801 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
9802 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
9803 #define CAN_F12R2_FB21_Pos (21U)
9804 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
9805 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
9806 #define CAN_F12R2_FB22_Pos (22U)
9807 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
9808 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
9809 #define CAN_F12R2_FB23_Pos (23U)
9810 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
9811 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
9812 #define CAN_F12R2_FB24_Pos (24U)
9813 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
9814 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
9815 #define CAN_F12R2_FB25_Pos (25U)
9816 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
9817 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
9818 #define CAN_F12R2_FB26_Pos (26U)
9819 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
9820 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
9821 #define CAN_F12R2_FB27_Pos (27U)
9822 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
9823 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
9824 #define CAN_F12R2_FB28_Pos (28U)
9825 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
9826 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
9827 #define CAN_F12R2_FB29_Pos (29U)
9828 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
9829 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
9830 #define CAN_F12R2_FB30_Pos (30U)
9831 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
9832 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
9833 #define CAN_F12R2_FB31_Pos (31U)
9834 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
9835 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
9836
9837 /******************* Bit definition for CAN_F13R2 register ******************/
9838 #define CAN_F13R2_FB0_Pos (0U)
9839 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
9840 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
9841 #define CAN_F13R2_FB1_Pos (1U)
9842 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
9843 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
9844 #define CAN_F13R2_FB2_Pos (2U)
9845 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
9846 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
9847 #define CAN_F13R2_FB3_Pos (3U)
9848 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
9849 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
9850 #define CAN_F13R2_FB4_Pos (4U)
9851 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
9852 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
9853 #define CAN_F13R2_FB5_Pos (5U)
9854 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
9855 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
9856 #define CAN_F13R2_FB6_Pos (6U)
9857 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
9858 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
9859 #define CAN_F13R2_FB7_Pos (7U)
9860 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
9861 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
9862 #define CAN_F13R2_FB8_Pos (8U)
9863 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
9864 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
9865 #define CAN_F13R2_FB9_Pos (9U)
9866 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
9867 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
9868 #define CAN_F13R2_FB10_Pos (10U)
9869 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
9870 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
9871 #define CAN_F13R2_FB11_Pos (11U)
9872 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
9873 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
9874 #define CAN_F13R2_FB12_Pos (12U)
9875 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
9876 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
9877 #define CAN_F13R2_FB13_Pos (13U)
9878 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
9879 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
9880 #define CAN_F13R2_FB14_Pos (14U)
9881 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
9882 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
9883 #define CAN_F13R2_FB15_Pos (15U)
9884 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
9885 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
9886 #define CAN_F13R2_FB16_Pos (16U)
9887 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
9888 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
9889 #define CAN_F13R2_FB17_Pos (17U)
9890 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
9891 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
9892 #define CAN_F13R2_FB18_Pos (18U)
9893 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
9894 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
9895 #define CAN_F13R2_FB19_Pos (19U)
9896 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
9897 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
9898 #define CAN_F13R2_FB20_Pos (20U)
9899 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
9900 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
9901 #define CAN_F13R2_FB21_Pos (21U)
9902 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
9903 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
9904 #define CAN_F13R2_FB22_Pos (22U)
9905 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
9906 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
9907 #define CAN_F13R2_FB23_Pos (23U)
9908 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
9909 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
9910 #define CAN_F13R2_FB24_Pos (24U)
9911 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
9912 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
9913 #define CAN_F13R2_FB25_Pos (25U)
9914 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
9915 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
9916 #define CAN_F13R2_FB26_Pos (26U)
9917 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
9918 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
9919 #define CAN_F13R2_FB27_Pos (27U)
9920 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
9921 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
9922 #define CAN_F13R2_FB28_Pos (28U)
9923 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
9924 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
9925 #define CAN_F13R2_FB29_Pos (29U)
9926 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
9927 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
9928 #define CAN_F13R2_FB30_Pos (30U)
9929 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
9930 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
9931 #define CAN_F13R2_FB31_Pos (31U)
9932 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
9933 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
9934
9935 /******************************************************************************/
9936 /* */
9937 /* Serial Peripheral Interface */
9938 /* */
9939 /******************************************************************************/
9940
9941 /******************* Bit definition for SPI_CR1 register ********************/
9942 #define SPI_CR1_CPHA_Pos (0U)
9943 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
9944 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
9945 #define SPI_CR1_CPOL_Pos (1U)
9946 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
9947 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
9948 #define SPI_CR1_MSTR_Pos (2U)
9949 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
9950 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
9951
9952 #define SPI_CR1_BR_Pos (3U)
9953 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
9954 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
9955 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
9956 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
9957 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
9958
9959 #define SPI_CR1_SPE_Pos (6U)
9960 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
9961 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
9962 #define SPI_CR1_LSBFIRST_Pos (7U)
9963 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
9964 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
9965 #define SPI_CR1_SSI_Pos (8U)
9966 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
9967 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
9968 #define SPI_CR1_SSM_Pos (9U)
9969 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
9970 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
9971 #define SPI_CR1_RXONLY_Pos (10U)
9972 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
9973 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
9974 #define SPI_CR1_DFF_Pos (11U)
9975 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
9976 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
9977 #define SPI_CR1_CRCNEXT_Pos (12U)
9978 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
9979 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
9980 #define SPI_CR1_CRCEN_Pos (13U)
9981 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
9982 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
9983 #define SPI_CR1_BIDIOE_Pos (14U)
9984 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
9985 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
9986 #define SPI_CR1_BIDIMODE_Pos (15U)
9987 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
9988 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
9989
9990 /******************* Bit definition for SPI_CR2 register ********************/
9991 #define SPI_CR2_RXDMAEN_Pos (0U)
9992 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
9993 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
9994 #define SPI_CR2_TXDMAEN_Pos (1U)
9995 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
9996 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
9997 #define SPI_CR2_SSOE_Pos (2U)
9998 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
9999 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
10000 #define SPI_CR2_ERRIE_Pos (5U)
10001 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
10002 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
10003 #define SPI_CR2_RXNEIE_Pos (6U)
10004 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
10005 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
10006 #define SPI_CR2_TXEIE_Pos (7U)
10007 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
10008 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
10009
10010 /******************** Bit definition for SPI_SR register ********************/
10011 #define SPI_SR_RXNE_Pos (0U)
10012 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
10013 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
10014 #define SPI_SR_TXE_Pos (1U)
10015 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
10016 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
10017 #define SPI_SR_CHSIDE_Pos (2U)
10018 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
10019 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
10020 #define SPI_SR_UDR_Pos (3U)
10021 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
10022 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
10023 #define SPI_SR_CRCERR_Pos (4U)
10024 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
10025 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
10026 #define SPI_SR_MODF_Pos (5U)
10027 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
10028 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
10029 #define SPI_SR_OVR_Pos (6U)
10030 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
10031 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
10032 #define SPI_SR_BSY_Pos (7U)
10033 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
10034 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
10035
10036 /******************** Bit definition for SPI_DR register ********************/
10037 #define SPI_DR_DR_Pos (0U)
10038 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
10039 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
10040
10041 /******************* Bit definition for SPI_CRCPR register ******************/
10042 #define SPI_CRCPR_CRCPOLY_Pos (0U)
10043 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
10044 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
10045
10046 /****************** Bit definition for SPI_RXCRCR register ******************/
10047 #define SPI_RXCRCR_RXCRC_Pos (0U)
10048 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
10049 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
10050
10051 /****************** Bit definition for SPI_TXCRCR register ******************/
10052 #define SPI_TXCRCR_TXCRC_Pos (0U)
10053 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
10054 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
10055
10056 /****************** Bit definition for SPI_I2SCFGR register *****************/
10057 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
10058 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
10059 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
10060
10061
10062 /******************************************************************************/
10063 /* */
10064 /* Inter-integrated Circuit Interface */
10065 /* */
10066 /******************************************************************************/
10067
10068 /******************* Bit definition for I2C_CR1 register ********************/
10069 #define I2C_CR1_PE_Pos (0U)
10070 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
10071 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
10072 #define I2C_CR1_SMBUS_Pos (1U)
10073 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
10074 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
10075 #define I2C_CR1_SMBTYPE_Pos (3U)
10076 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
10077 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
10078 #define I2C_CR1_ENARP_Pos (4U)
10079 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
10080 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
10081 #define I2C_CR1_ENPEC_Pos (5U)
10082 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
10083 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
10084 #define I2C_CR1_ENGC_Pos (6U)
10085 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
10086 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
10087 #define I2C_CR1_NOSTRETCH_Pos (7U)
10088 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
10089 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
10090 #define I2C_CR1_START_Pos (8U)
10091 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
10092 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
10093 #define I2C_CR1_STOP_Pos (9U)
10094 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
10095 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
10096 #define I2C_CR1_ACK_Pos (10U)
10097 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
10098 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
10099 #define I2C_CR1_POS_Pos (11U)
10100 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
10101 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
10102 #define I2C_CR1_PEC_Pos (12U)
10103 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
10104 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
10105 #define I2C_CR1_ALERT_Pos (13U)
10106 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
10107 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
10108 #define I2C_CR1_SWRST_Pos (15U)
10109 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
10110 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
10111
10112 /******************* Bit definition for I2C_CR2 register ********************/
10113 #define I2C_CR2_FREQ_Pos (0U)
10114 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
10115 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
10116 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
10117 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
10118 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
10119 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
10120 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
10121 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
10122
10123 #define I2C_CR2_ITERREN_Pos (8U)
10124 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
10125 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
10126 #define I2C_CR2_ITEVTEN_Pos (9U)
10127 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
10128 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
10129 #define I2C_CR2_ITBUFEN_Pos (10U)
10130 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
10131 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
10132 #define I2C_CR2_DMAEN_Pos (11U)
10133 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
10134 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
10135 #define I2C_CR2_LAST_Pos (12U)
10136 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
10137 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
10138
10139 /******************* Bit definition for I2C_OAR1 register *******************/
10140 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
10141 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
10142
10143 #define I2C_OAR1_ADD0_Pos (0U)
10144 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
10145 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
10146 #define I2C_OAR1_ADD1_Pos (1U)
10147 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
10148 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
10149 #define I2C_OAR1_ADD2_Pos (2U)
10150 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
10151 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
10152 #define I2C_OAR1_ADD3_Pos (3U)
10153 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
10154 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
10155 #define I2C_OAR1_ADD4_Pos (4U)
10156 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
10157 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
10158 #define I2C_OAR1_ADD5_Pos (5U)
10159 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
10160 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
10161 #define I2C_OAR1_ADD6_Pos (6U)
10162 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
10163 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
10164 #define I2C_OAR1_ADD7_Pos (7U)
10165 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
10166 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
10167 #define I2C_OAR1_ADD8_Pos (8U)
10168 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
10169 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
10170 #define I2C_OAR1_ADD9_Pos (9U)
10171 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
10172 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
10173
10174 #define I2C_OAR1_ADDMODE_Pos (15U)
10175 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
10176 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
10177
10178 /******************* Bit definition for I2C_OAR2 register *******************/
10179 #define I2C_OAR2_ENDUAL_Pos (0U)
10180 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
10181 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
10182 #define I2C_OAR2_ADD2_Pos (1U)
10183 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
10184 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
10185
10186 /******************* Bit definition for I2C_SR1 register ********************/
10187 #define I2C_SR1_SB_Pos (0U)
10188 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
10189 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
10190 #define I2C_SR1_ADDR_Pos (1U)
10191 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
10192 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
10193 #define I2C_SR1_BTF_Pos (2U)
10194 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
10195 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
10196 #define I2C_SR1_ADD10_Pos (3U)
10197 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
10198 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
10199 #define I2C_SR1_STOPF_Pos (4U)
10200 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
10201 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
10202 #define I2C_SR1_RXNE_Pos (6U)
10203 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
10204 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
10205 #define I2C_SR1_TXE_Pos (7U)
10206 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
10207 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
10208 #define I2C_SR1_BERR_Pos (8U)
10209 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
10210 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
10211 #define I2C_SR1_ARLO_Pos (9U)
10212 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
10213 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
10214 #define I2C_SR1_AF_Pos (10U)
10215 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
10216 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
10217 #define I2C_SR1_OVR_Pos (11U)
10218 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
10219 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
10220 #define I2C_SR1_PECERR_Pos (12U)
10221 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
10222 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
10223 #define I2C_SR1_TIMEOUT_Pos (14U)
10224 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
10225 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
10226 #define I2C_SR1_SMBALERT_Pos (15U)
10227 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
10228 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
10229
10230 /******************* Bit definition for I2C_SR2 register ********************/
10231 #define I2C_SR2_MSL_Pos (0U)
10232 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
10233 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
10234 #define I2C_SR2_BUSY_Pos (1U)
10235 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
10236 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
10237 #define I2C_SR2_TRA_Pos (2U)
10238 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
10239 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
10240 #define I2C_SR2_GENCALL_Pos (4U)
10241 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
10242 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
10243 #define I2C_SR2_SMBDEFAULT_Pos (5U)
10244 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
10245 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
10246 #define I2C_SR2_SMBHOST_Pos (6U)
10247 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
10248 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
10249 #define I2C_SR2_DUALF_Pos (7U)
10250 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
10251 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
10252 #define I2C_SR2_PEC_Pos (8U)
10253 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
10254 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
10255
10256 /******************* Bit definition for I2C_CCR register ********************/
10257 #define I2C_CCR_CCR_Pos (0U)
10258 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
10259 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
10260 #define I2C_CCR_DUTY_Pos (14U)
10261 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
10262 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
10263 #define I2C_CCR_FS_Pos (15U)
10264 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
10265 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
10266
10267 /****************** Bit definition for I2C_TRISE register *******************/
10268 #define I2C_TRISE_TRISE_Pos (0U)
10269 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
10270 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
10271
10272 /******************************************************************************/
10273 /* */
10274 /* Universal Synchronous Asynchronous Receiver Transmitter */
10275 /* */
10276 /******************************************************************************/
10277
10278 /******************* Bit definition for USART_SR register *******************/
10279 #define USART_SR_PE_Pos (0U)
10280 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
10281 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
10282 #define USART_SR_FE_Pos (1U)
10283 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
10284 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
10285 #define USART_SR_NE_Pos (2U)
10286 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
10287 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
10288 #define USART_SR_ORE_Pos (3U)
10289 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
10290 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
10291 #define USART_SR_IDLE_Pos (4U)
10292 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
10293 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
10294 #define USART_SR_RXNE_Pos (5U)
10295 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
10296 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
10297 #define USART_SR_TC_Pos (6U)
10298 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
10299 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
10300 #define USART_SR_TXE_Pos (7U)
10301 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
10302 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
10303 #define USART_SR_LBD_Pos (8U)
10304 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
10305 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
10306 #define USART_SR_CTS_Pos (9U)
10307 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
10308 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
10309
10310 /******************* Bit definition for USART_DR register *******************/
10311 #define USART_DR_DR_Pos (0U)
10312 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
10313 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
10314
10315 /****************** Bit definition for USART_BRR register *******************/
10316 #define USART_BRR_DIV_Fraction_Pos (0U)
10317 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
10318 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
10319 #define USART_BRR_DIV_Mantissa_Pos (4U)
10320 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
10321 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
10322
10323 /****************** Bit definition for USART_CR1 register *******************/
10324 #define USART_CR1_SBK_Pos (0U)
10325 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
10326 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
10327 #define USART_CR1_RWU_Pos (1U)
10328 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
10329 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
10330 #define USART_CR1_RE_Pos (2U)
10331 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
10332 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
10333 #define USART_CR1_TE_Pos (3U)
10334 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
10335 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
10336 #define USART_CR1_IDLEIE_Pos (4U)
10337 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
10338 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
10339 #define USART_CR1_RXNEIE_Pos (5U)
10340 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
10341 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
10342 #define USART_CR1_TCIE_Pos (6U)
10343 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
10344 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
10345 #define USART_CR1_TXEIE_Pos (7U)
10346 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
10347 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
10348 #define USART_CR1_PEIE_Pos (8U)
10349 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
10350 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
10351 #define USART_CR1_PS_Pos (9U)
10352 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
10353 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
10354 #define USART_CR1_PCE_Pos (10U)
10355 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
10356 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
10357 #define USART_CR1_WAKE_Pos (11U)
10358 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
10359 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
10360 #define USART_CR1_M_Pos (12U)
10361 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
10362 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
10363 #define USART_CR1_UE_Pos (13U)
10364 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
10365 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
10366
10367 /****************** Bit definition for USART_CR2 register *******************/
10368 #define USART_CR2_ADD_Pos (0U)
10369 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
10370 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
10371 #define USART_CR2_LBDL_Pos (5U)
10372 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
10373 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
10374 #define USART_CR2_LBDIE_Pos (6U)
10375 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
10376 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
10377 #define USART_CR2_LBCL_Pos (8U)
10378 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
10379 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
10380 #define USART_CR2_CPHA_Pos (9U)
10381 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
10382 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
10383 #define USART_CR2_CPOL_Pos (10U)
10384 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
10385 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
10386 #define USART_CR2_CLKEN_Pos (11U)
10387 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
10388 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
10389
10390 #define USART_CR2_STOP_Pos (12U)
10391 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
10392 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
10393 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
10394 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
10395
10396 #define USART_CR2_LINEN_Pos (14U)
10397 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
10398 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
10399
10400 /****************** Bit definition for USART_CR3 register *******************/
10401 #define USART_CR3_EIE_Pos (0U)
10402 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
10403 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
10404 #define USART_CR3_IREN_Pos (1U)
10405 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
10406 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
10407 #define USART_CR3_IRLP_Pos (2U)
10408 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
10409 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
10410 #define USART_CR3_HDSEL_Pos (3U)
10411 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
10412 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
10413 #define USART_CR3_NACK_Pos (4U)
10414 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
10415 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
10416 #define USART_CR3_SCEN_Pos (5U)
10417 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
10418 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
10419 #define USART_CR3_DMAR_Pos (6U)
10420 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
10421 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
10422 #define USART_CR3_DMAT_Pos (7U)
10423 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
10424 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
10425 #define USART_CR3_RTSE_Pos (8U)
10426 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
10427 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
10428 #define USART_CR3_CTSE_Pos (9U)
10429 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
10430 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
10431 #define USART_CR3_CTSIE_Pos (10U)
10432 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
10433 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
10434
10435 /****************** Bit definition for USART_GTPR register ******************/
10436 #define USART_GTPR_PSC_Pos (0U)
10437 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
10438 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
10439 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
10440 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
10441 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
10442 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
10443 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
10444 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
10445 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
10446 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
10447
10448 #define USART_GTPR_GT_Pos (8U)
10449 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
10450 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
10451
10452 /******************************************************************************/
10453 /* */
10454 /* Debug MCU */
10455 /* */
10456 /******************************************************************************/
10457
10458 /**************** Bit definition for DBGMCU_IDCODE register *****************/
10459 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
10460 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
10461 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
10462
10463 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
10464 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
10465 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
10466 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
10467 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
10468 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
10469 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
10470 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
10471 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
10472 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
10473 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
10474 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
10475 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
10476 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
10477 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
10478 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
10479 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
10480 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
10481 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
10482
10483 /****************** Bit definition for DBGMCU_CR register *******************/
10484 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
10485 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
10486 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
10487 #define DBGMCU_CR_DBG_STOP_Pos (1U)
10488 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
10489 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
10490 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
10491 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
10492 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
10493 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
10494 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
10495 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
10496
10497 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
10498 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
10499 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
10500 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
10501 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
10502
10503 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
10504 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
10505 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
10506 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
10507 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
10508 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
10509 #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
10510 #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
10511 #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
10512 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
10513 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
10514 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
10515 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
10516 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
10517 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
10518 #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
10519 #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
10520 #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
10521 #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
10522 #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
10523 #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
10524 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
10525 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
10526 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
10527 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
10528 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
10529 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
10530
10531 /******************************************************************************/
10532 /* */
10533 /* FLASH and Option Bytes Registers */
10534 /* */
10535 /******************************************************************************/
10536 /******************* Bit definition for FLASH_ACR register ******************/
10537 #define FLASH_ACR_LATENCY_Pos (0U)
10538 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
10539 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
10540 #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
10541 #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
10542 #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
10543
10544 #define FLASH_ACR_HLFCYA_Pos (3U)
10545 #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
10546 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
10547 #define FLASH_ACR_PRFTBE_Pos (4U)
10548 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
10549 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
10550 #define FLASH_ACR_PRFTBS_Pos (5U)
10551 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
10552 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
10553
10554 /****************** Bit definition for FLASH_KEYR register ******************/
10555 #define FLASH_KEYR_FKEYR_Pos (0U)
10556 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
10557 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
10558
10559 #define RDP_KEY_Pos (0U)
10560 #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
10561 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
10562 #define FLASH_KEY1_Pos (0U)
10563 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
10564 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
10565 #define FLASH_KEY2_Pos (0U)
10566 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
10567 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
10568
10569 /***************** Bit definition for FLASH_OPTKEYR register ****************/
10570 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
10571 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
10572 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
10573
10574 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
10575 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
10576
10577 /****************** Bit definition for FLASH_SR register ********************/
10578 #define FLASH_SR_BSY_Pos (0U)
10579 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
10580 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
10581 #define FLASH_SR_PGERR_Pos (2U)
10582 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
10583 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
10584 #define FLASH_SR_WRPRTERR_Pos (4U)
10585 #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
10586 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
10587 #define FLASH_SR_EOP_Pos (5U)
10588 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
10589 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
10590
10591 /******************* Bit definition for FLASH_CR register *******************/
10592 #define FLASH_CR_PG_Pos (0U)
10593 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
10594 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
10595 #define FLASH_CR_PER_Pos (1U)
10596 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
10597 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
10598 #define FLASH_CR_MER_Pos (2U)
10599 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
10600 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
10601 #define FLASH_CR_OPTPG_Pos (4U)
10602 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
10603 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
10604 #define FLASH_CR_OPTER_Pos (5U)
10605 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
10606 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
10607 #define FLASH_CR_STRT_Pos (6U)
10608 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
10609 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
10610 #define FLASH_CR_LOCK_Pos (7U)
10611 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
10612 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
10613 #define FLASH_CR_OPTWRE_Pos (9U)
10614 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
10615 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
10616 #define FLASH_CR_ERRIE_Pos (10U)
10617 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
10618 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
10619 #define FLASH_CR_EOPIE_Pos (12U)
10620 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
10621 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
10622
10623 /******************* Bit definition for FLASH_AR register *******************/
10624 #define FLASH_AR_FAR_Pos (0U)
10625 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
10626 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
10627
10628 /****************** Bit definition for FLASH_OBR register *******************/
10629 #define FLASH_OBR_OPTERR_Pos (0U)
10630 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
10631 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
10632 #define FLASH_OBR_RDPRT_Pos (1U)
10633 #define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
10634 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
10635
10636 #define FLASH_OBR_IWDG_SW_Pos (2U)
10637 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
10638 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
10639 #define FLASH_OBR_nRST_STOP_Pos (3U)
10640 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
10641 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
10642 #define FLASH_OBR_nRST_STDBY_Pos (4U)
10643 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
10644 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
10645 #define FLASH_OBR_USER_Pos (2U)
10646 #define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
10647 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
10648 #define FLASH_OBR_DATA0_Pos (10U)
10649 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
10650 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
10651 #define FLASH_OBR_DATA1_Pos (18U)
10652 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
10653 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
10654
10655 /****************** Bit definition for FLASH_WRPR register ******************/
10656 #define FLASH_WRPR_WRP_Pos (0U)
10657 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
10658 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
10659
10660 /*----------------------------------------------------------------------------*/
10661
10662 /****************** Bit definition for FLASH_RDP register *******************/
10663 #define FLASH_RDP_RDP_Pos (0U)
10664 #define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
10665 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
10666 #define FLASH_RDP_nRDP_Pos (8U)
10667 #define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
10668 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
10669
10670 /****************** Bit definition for FLASH_USER register ******************/
10671 #define FLASH_USER_USER_Pos (16U)
10672 #define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
10673 #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
10674 #define FLASH_USER_nUSER_Pos (24U)
10675 #define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
10676 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
10677
10678 /****************** Bit definition for FLASH_Data0 register *****************/
10679 #define FLASH_DATA0_DATA0_Pos (0U)
10680 #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
10681 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
10682 #define FLASH_DATA0_nDATA0_Pos (8U)
10683 #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
10684 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
10685
10686 /****************** Bit definition for FLASH_Data1 register *****************/
10687 #define FLASH_DATA1_DATA1_Pos (16U)
10688 #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
10689 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
10690 #define FLASH_DATA1_nDATA1_Pos (24U)
10691 #define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
10692 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
10693
10694 /****************** Bit definition for FLASH_WRP0 register ******************/
10695 #define FLASH_WRP0_WRP0_Pos (0U)
10696 #define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
10697 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
10698 #define FLASH_WRP0_nWRP0_Pos (8U)
10699 #define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
10700 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
10701
10702 /****************** Bit definition for FLASH_WRP1 register ******************/
10703 #define FLASH_WRP1_WRP1_Pos (16U)
10704 #define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
10705 #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
10706 #define FLASH_WRP1_nWRP1_Pos (24U)
10707 #define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
10708 #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
10709
10710 /****************** Bit definition for FLASH_WRP2 register ******************/
10711 #define FLASH_WRP2_WRP2_Pos (0U)
10712 #define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
10713 #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
10714 #define FLASH_WRP2_nWRP2_Pos (8U)
10715 #define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
10716 #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
10717
10718 /****************** Bit definition for FLASH_WRP3 register ******************/
10719 #define FLASH_WRP3_WRP3_Pos (16U)
10720 #define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
10721 #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
10722 #define FLASH_WRP3_nWRP3_Pos (24U)
10723 #define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
10724 #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
10725
10726
10727
10728 /**
10729 * @}
10730 */
10731
10732 /**
10733 * @}
10734 */
10735
10736 /** @addtogroup Exported_macro
10737 * @{
10738 */
10739
10740 /****************************** ADC Instances *********************************/
10741 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
10742 ((INSTANCE) == ADC2))
10743
10744 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
10745
10746 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
10747
10748 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
10749
10750 /****************************** CAN Instances *********************************/
10751 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
10752
10753 /****************************** CRC Instances *********************************/
10754 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
10755
10756 /****************************** DAC Instances *********************************/
10757
10758 /****************************** DMA Instances *********************************/
10759 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
10760 ((INSTANCE) == DMA1_Channel2) || \
10761 ((INSTANCE) == DMA1_Channel3) || \
10762 ((INSTANCE) == DMA1_Channel4) || \
10763 ((INSTANCE) == DMA1_Channel5) || \
10764 ((INSTANCE) == DMA1_Channel6) || \
10765 ((INSTANCE) == DMA1_Channel7))
10766
10767 /******************************* GPIO Instances *******************************/
10768 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
10769 ((INSTANCE) == GPIOB) || \
10770 ((INSTANCE) == GPIOC) || \
10771 ((INSTANCE) == GPIOD) || \
10772 ((INSTANCE) == GPIOE))
10773
10774 /**************************** GPIO Alternate Function Instances ***************/
10775 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
10776
10777 /**************************** GPIO Lock Instances *****************************/
10778 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
10779
10780 /******************************** I2C Instances *******************************/
10781 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
10782 ((INSTANCE) == I2C2))
10783
10784 /****************************** IWDG Instances ********************************/
10785 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
10786
10787 /******************************** SPI Instances *******************************/
10788 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
10789 ((INSTANCE) == SPI2))
10790
10791 /****************************** START TIM Instances ***************************/
10792 /****************************** TIM Instances *********************************/
10793 #define IS_TIM_INSTANCE(INSTANCE)\
10794 (((INSTANCE) == TIM1) || \
10795 ((INSTANCE) == TIM2) || \
10796 ((INSTANCE) == TIM3) || \
10797 ((INSTANCE) == TIM4))
10798
10799 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
10800 (((INSTANCE) == TIM1) || \
10801 ((INSTANCE) == TIM2) || \
10802 ((INSTANCE) == TIM3) || \
10803 ((INSTANCE) == TIM4))
10804
10805 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
10806 (((INSTANCE) == TIM1) || \
10807 ((INSTANCE) == TIM2) || \
10808 ((INSTANCE) == TIM3) || \
10809 ((INSTANCE) == TIM4))
10810
10811 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
10812 (((INSTANCE) == TIM1) || \
10813 ((INSTANCE) == TIM2) || \
10814 ((INSTANCE) == TIM3) || \
10815 ((INSTANCE) == TIM4))
10816
10817 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
10818 (((INSTANCE) == TIM1) || \
10819 ((INSTANCE) == TIM2) || \
10820 ((INSTANCE) == TIM3) || \
10821 ((INSTANCE) == TIM4))
10822
10823 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
10824 (((INSTANCE) == TIM1) || \
10825 ((INSTANCE) == TIM2) || \
10826 ((INSTANCE) == TIM3) || \
10827 ((INSTANCE) == TIM4))
10828
10829 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
10830 (((INSTANCE) == TIM1) || \
10831 ((INSTANCE) == TIM2) || \
10832 ((INSTANCE) == TIM3) || \
10833 ((INSTANCE) == TIM4))
10834
10835 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
10836 (((INSTANCE) == TIM1) || \
10837 ((INSTANCE) == TIM2) || \
10838 ((INSTANCE) == TIM3) || \
10839 ((INSTANCE) == TIM4))
10840
10841 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
10842 (((INSTANCE) == TIM1) || \
10843 ((INSTANCE) == TIM2) || \
10844 ((INSTANCE) == TIM3) || \
10845 ((INSTANCE) == TIM4))
10846
10847 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
10848 (((INSTANCE) == TIM1) || \
10849 ((INSTANCE) == TIM2) || \
10850 ((INSTANCE) == TIM3) || \
10851 ((INSTANCE) == TIM4))
10852
10853 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
10854 (((INSTANCE) == TIM1) || \
10855 ((INSTANCE) == TIM2) || \
10856 ((INSTANCE) == TIM3) || \
10857 ((INSTANCE) == TIM4))
10858
10859 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
10860 (((INSTANCE) == TIM1) || \
10861 ((INSTANCE) == TIM2) || \
10862 ((INSTANCE) == TIM3) || \
10863 ((INSTANCE) == TIM4))
10864
10865 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
10866 (((INSTANCE) == TIM1) || \
10867 ((INSTANCE) == TIM2) || \
10868 ((INSTANCE) == TIM3) || \
10869 ((INSTANCE) == TIM4))
10870
10871 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
10872 (((INSTANCE) == TIM1) || \
10873 ((INSTANCE) == TIM2) || \
10874 ((INSTANCE) == TIM3) || \
10875 ((INSTANCE) == TIM4))
10876
10877 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
10878 (((INSTANCE) == TIM1) || \
10879 ((INSTANCE) == TIM2) || \
10880 ((INSTANCE) == TIM3) || \
10881 ((INSTANCE) == TIM4))
10882
10883 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
10884 ((INSTANCE) == TIM1)
10885
10886 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
10887 ((((INSTANCE) == TIM1) && \
10888 (((CHANNEL) == TIM_CHANNEL_1) || \
10889 ((CHANNEL) == TIM_CHANNEL_2) || \
10890 ((CHANNEL) == TIM_CHANNEL_3) || \
10891 ((CHANNEL) == TIM_CHANNEL_4))) \
10892 || \
10893 (((INSTANCE) == TIM2) && \
10894 (((CHANNEL) == TIM_CHANNEL_1) || \
10895 ((CHANNEL) == TIM_CHANNEL_2) || \
10896 ((CHANNEL) == TIM_CHANNEL_3) || \
10897 ((CHANNEL) == TIM_CHANNEL_4))) \
10898 || \
10899 (((INSTANCE) == TIM3) && \
10900 (((CHANNEL) == TIM_CHANNEL_1) || \
10901 ((CHANNEL) == TIM_CHANNEL_2) || \
10902 ((CHANNEL) == TIM_CHANNEL_3) || \
10903 ((CHANNEL) == TIM_CHANNEL_4))) \
10904 || \
10905 (((INSTANCE) == TIM4) && \
10906 (((CHANNEL) == TIM_CHANNEL_1) || \
10907 ((CHANNEL) == TIM_CHANNEL_2) || \
10908 ((CHANNEL) == TIM_CHANNEL_3) || \
10909 ((CHANNEL) == TIM_CHANNEL_4))))
10910
10911 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
10912 (((INSTANCE) == TIM1) && \
10913 (((CHANNEL) == TIM_CHANNEL_1) || \
10914 ((CHANNEL) == TIM_CHANNEL_2) || \
10915 ((CHANNEL) == TIM_CHANNEL_3)))
10916
10917 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
10918 (((INSTANCE) == TIM1) || \
10919 ((INSTANCE) == TIM2) || \
10920 ((INSTANCE) == TIM3) || \
10921 ((INSTANCE) == TIM4))
10922
10923 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
10924 ((INSTANCE) == TIM1)
10925
10926 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
10927 (((INSTANCE) == TIM1) || \
10928 ((INSTANCE) == TIM2) || \
10929 ((INSTANCE) == TIM3) || \
10930 ((INSTANCE) == TIM4))
10931
10932 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
10933 (((INSTANCE) == TIM1) || \
10934 ((INSTANCE) == TIM2) || \
10935 ((INSTANCE) == TIM3) || \
10936 ((INSTANCE) == TIM4))
10937
10938 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
10939 (((INSTANCE) == TIM1) || \
10940 ((INSTANCE) == TIM2) || \
10941 ((INSTANCE) == TIM3) || \
10942 ((INSTANCE) == TIM4))
10943
10944 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
10945 ((INSTANCE) == TIM1)
10946
10947 /****************************** END TIM Instances *****************************/
10948
10949
10950 /******************** USART Instances : Synchronous mode **********************/
10951 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10952 ((INSTANCE) == USART2) || \
10953 ((INSTANCE) == USART3))
10954
10955 /******************** UART Instances : Asynchronous mode **********************/
10956 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10957 ((INSTANCE) == USART2) || \
10958 ((INSTANCE) == USART3))
10959
10960 /******************** UART Instances : Half-Duplex mode **********************/
10961 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10962 ((INSTANCE) == USART2) || \
10963 ((INSTANCE) == USART3))
10964
10965 /******************** UART Instances : LIN mode **********************/
10966 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10967 ((INSTANCE) == USART2) || \
10968 ((INSTANCE) == USART3))
10969
10970 /****************** UART Instances : Hardware Flow control ********************/
10971 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10972 ((INSTANCE) == USART2) || \
10973 ((INSTANCE) == USART3))
10974
10975 /********************* UART Instances : Smard card mode ***********************/
10976 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10977 ((INSTANCE) == USART2) || \
10978 ((INSTANCE) == USART3))
10979
10980 /*********************** UART Instances : IRDA mode ***************************/
10981 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10982 ((INSTANCE) == USART2) || \
10983 ((INSTANCE) == USART3))
10984
10985 /***************** UART Instances : Multi-Processor mode **********************/
10986 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10987 ((INSTANCE) == USART2) || \
10988 ((INSTANCE) == USART3))
10989
10990 /***************** UART Instances : DMA mode available **********************/
10991 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10992 ((INSTANCE) == USART2) || \
10993 ((INSTANCE) == USART3))
10994
10995 /****************************** RTC Instances *********************************/
10996 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
10997
10998 /**************************** WWDG Instances *****************************/
10999 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
11000
11001 /****************************** USB Instances ********************************/
11002 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
11003
11004
11005
11006
11007 /**
11008 * @}
11009 */
11010 /******************************************************************************/
11011 /* For a painless codes migration between the STM32F1xx device product */
11012 /* lines, the aliases defined below are put in place to overcome the */
11013 /* differences in the interrupt handlers and IRQn definitions. */
11014 /* No need to update developed interrupt code when moving across */
11015 /* product lines within the same STM32F1 Family */
11016 /******************************************************************************/
11017
11018 /* Aliases for __IRQn */
11019 #define ADC1_IRQn ADC1_2_IRQn
11020 #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
11021 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
11022 #define TIM9_IRQn TIM1_BRK_IRQn
11023 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
11024 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
11025 #define TIM11_IRQn TIM1_TRG_COM_IRQn
11026 #define TIM10_IRQn TIM1_UP_IRQn
11027 #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
11028 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
11029 #define CEC_IRQn USBWakeUp_IRQn
11030 #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
11031 #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
11032 #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
11033 #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
11034 #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
11035
11036
11037 /* Aliases for __IRQHandler */
11038 #define ADC1_IRQHandler ADC1_2_IRQHandler
11039 #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
11040 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
11041 #define TIM9_IRQHandler TIM1_BRK_IRQHandler
11042 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
11043 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
11044 #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
11045 #define TIM10_IRQHandler TIM1_UP_IRQHandler
11046 #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
11047 #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
11048 #define CEC_IRQHandler USBWakeUp_IRQHandler
11049 #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
11050 #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
11051 #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
11052 #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
11053 #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
11054
11055
11056 /**
11057 * @}
11058 */
11059
11060 /**
11061 * @}
11062 */
11063
11064
11065 #ifdef __cplusplus
11066 }
11067 #endif /* __cplusplus */
11068
11069 #endif /* __STM32F103xB_H */
11070
11071
11072
11073 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/