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comparison f103c8/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h @ 2:0c59e7a7782a

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Working on GPIO and RCC
author cin
date Mon, 16 Jan 2017 11:04:47 +0300
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1:a0b14b11ad9f 2:0c59e7a7782a
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_rcc_ex.h
4 * @author MCD Application Team
5 * @version V1.0.4
6 * @date 29-April-2016
7 * @brief Header file of RCC HAL Extension module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_RCC_EX_H
40 #define __STM32F1xx_HAL_RCC_EX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx_hal_def.h"
48
49 /** @addtogroup STM32F1xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup RCCEx
54 * @{
55 */
56
57 /** @addtogroup RCCEx_Private_Constants
58 * @{
59 */
60
61 #if defined(STM32F105xC) || defined(STM32F107xC)
62
63 /* Alias word address of PLLI2SON bit */
64 #define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON)
65 #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
66 /* Alias word address of PLL2ON bit */
67 #define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON)
68 #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
69
70 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
71 #define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
72
73 #endif /* STM32F105xC || STM32F107xC */
74
75
76 #define CR_REG_INDEX ((uint8_t)1)
77
78 /**
79 * @}
80 */
81
82 /** @addtogroup RCCEx_Private_Macros
83 * @{
84 */
85
86 #if defined(STM32F105xC) || defined(STM32F107xC)
87 #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
88 ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
89 #endif /* STM32F105xC || STM32F107xC */
90
91 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
92 || defined(STM32F100xE)
93 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
94 ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
95 ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
96 ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
97 ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
98 ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
99 ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
100 ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
101
102 #else
103 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
104 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
105
106 #if defined(STM32F105xC) || defined(STM32F107xC)
107 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
108 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
109 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
110 ((__MUL__) == RCC_PLL_MUL6_5))
111
112 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
113 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
114 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
115 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
116 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
117
118 #else
119 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
120 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
121 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
122 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
123 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
124 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
125 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
126 ((__MUL__) == RCC_PLL_MUL16))
127
128 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
129 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
130 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
131
132 #endif /* STM32F105xC || STM32F107xC*/
133
134 #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
135 ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
136
137 #if defined(STM32F105xC) || defined(STM32F107xC)
138 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
139
140 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
141
142 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
143
144 #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
145 ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
146 ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
147 ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
148 ((__MUL__) == RCC_PLLI2S_MUL20))
149
150 #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
151 ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
152 ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
153 ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
154 ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
155 ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
156 ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
157 ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
158
159 #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
160 ((__PLL__) == RCC_PLL2_ON))
161
162 #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
163 ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
164 ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
165 ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
166 ((__MUL__) == RCC_PLL2_MUL20))
167
168 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
169 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
170 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
171 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
172 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
173 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
174
175 #elif defined(STM32F103xE) || defined(STM32F103xG)
176
177 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
178
179 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
180
181 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
182 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
183 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
184 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
185 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
186 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
187
188
189 #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
190 || defined(STM32F103xB)
191
192 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
193 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
194 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
195 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
196
197 #else
198
199 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
200 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
201 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
202
203 #endif /* STM32F105xC || STM32F107xC */
204
205 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
206 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
207
208 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
209
210 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
211
212 /**
213 * @}
214 */
215
216 /* Exported types ------------------------------------------------------------*/
217
218 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
219 * @{
220 */
221
222 #if defined(STM32F105xC) || defined(STM32F107xC)
223 /**
224 * @brief RCC PLL2 configuration structure definition
225 */
226 typedef struct
227 {
228 uint32_t PLL2State; /*!< The new state of the PLL2.
229 This parameter can be a value of @ref RCCEx_PLL2_Config */
230
231 uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
232 This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
233
234 #if defined(STM32F105xC) || defined(STM32F107xC)
235 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
236 This parameter can be a value of @ref RCCEx_Prediv2_Factor */
237
238 #endif /* STM32F105xC || STM32F107xC */
239 } RCC_PLL2InitTypeDef;
240
241 #endif /* STM32F105xC || STM32F107xC */
242
243 /**
244 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
245 */
246 typedef struct
247 {
248 uint32_t OscillatorType; /*!< The oscillators to be configured.
249 This parameter can be a value of @ref RCC_Oscillator_Type */
250
251 #if defined(STM32F105xC) || defined(STM32F107xC)
252 uint32_t Prediv1Source; /*!< The Prediv1 source value.
253 This parameter can be a value of @ref RCCEx_Prediv1_Source */
254 #endif /* STM32F105xC || STM32F107xC */
255
256 uint32_t HSEState; /*!< The new state of the HSE.
257 This parameter can be a value of @ref RCC_HSE_Config */
258
259 uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
260 This parameter can be a value of @ref RCCEx_Prediv1_Factor */
261
262 uint32_t LSEState; /*!< The new state of the LSE.
263 This parameter can be a value of @ref RCC_LSE_Config */
264
265 uint32_t HSIState; /*!< The new state of the HSI.
266 This parameter can be a value of @ref RCC_HSI_Config */
267
268 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
269 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
270
271 uint32_t LSIState; /*!< The new state of the LSI.
272 This parameter can be a value of @ref RCC_LSI_Config */
273
274 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
275
276 #if defined(STM32F105xC) || defined(STM32F107xC)
277 RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
278 #endif /* STM32F105xC || STM32F107xC */
279 } RCC_OscInitTypeDef;
280
281 #if defined(STM32F105xC) || defined(STM32F107xC)
282 /**
283 * @brief RCC PLLI2S configuration structure definition
284 */
285 typedef struct
286 {
287 uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
288 This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
289
290 #if defined(STM32F105xC) || defined(STM32F107xC)
291 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
292 This parameter can be a value of @ref RCCEx_Prediv2_Factor */
293
294 #endif /* STM32F105xC || STM32F107xC */
295 } RCC_PLLI2SInitTypeDef;
296 #endif /* STM32F105xC || STM32F107xC */
297
298 /**
299 * @brief RCC extended clocks structure definition
300 */
301 typedef struct
302 {
303 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
304 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
305
306 uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
307 This parameter can be a value of @ref RCC_RTC_Clock_Source */
308
309 uint32_t AdcClockSelection; /*!< ADC clock source
310 This parameter can be a value of @ref RCCEx_ADC_Prescaler */
311
312 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
313 || defined(STM32F107xC)
314 uint32_t I2s2ClockSelection; /*!< I2S2 clock source
315 This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
316
317 uint32_t I2s3ClockSelection; /*!< I2S3 clock source
318 This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
319
320 #if defined(STM32F105xC) || defined(STM32F107xC)
321 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
322 This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
323
324 #endif /* STM32F105xC || STM32F107xC */
325 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
326
327 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
328 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
329 || defined(STM32F105xC) || defined(STM32F107xC)
330 uint32_t UsbClockSelection; /*!< USB clock source
331 This parameter can be a value of @ref RCCEx_USB_Prescaler */
332
333 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
334 } RCC_PeriphCLKInitTypeDef;
335
336 /**
337 * @}
338 */
339
340 /* Exported constants --------------------------------------------------------*/
341
342 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
343 * @{
344 */
345
346 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
347 * @{
348 */
349 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
350 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002)
351 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
352 || defined(STM32F107xC)
353 #define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004)
354 #define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008)
355 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
356 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
357 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
358 || defined(STM32F105xC) || defined(STM32F107xC)
359 #define RCC_PERIPHCLK_USB ((uint32_t)0x00000010)
360 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
361
362 /**
363 * @}
364 */
365
366 /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
367 * @{
368 */
369 #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
370 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
371 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
372 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
373
374 /**
375 * @}
376 */
377
378 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
379 || defined(STM32F107xC)
380 /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
381 * @{
382 */
383 #define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
384 #if defined(STM32F105xC) || defined(STM32F107xC)
385 #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
386 #endif /* STM32F105xC || STM32F107xC */
387
388 /**
389 * @}
390 */
391
392 /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
393 * @{
394 */
395 #define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
396 #if defined(STM32F105xC) || defined(STM32F107xC)
397 #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
398 #endif /* STM32F105xC || STM32F107xC */
399
400 /**
401 * @}
402 */
403
404 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
405
406 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
407 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
408
409 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
410 * @{
411 */
412 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
413 #define RCC_USBCLKSOURCE_PLL_DIV1_5 ((uint32_t)0x00000000)
414
415 /**
416 * @}
417 */
418
419 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
420
421
422 #if defined(STM32F105xC) || defined(STM32F107xC)
423 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
424 * @{
425 */
426 #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
427 #define RCC_USBCLKSOURCE_PLL_DIV3 ((uint32_t)0x00000000)
428
429 /**
430 * @}
431 */
432
433 /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
434 * @{
435 */
436
437 #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
438 #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
439 #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
440 #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
441 #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
442 #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
443 #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
444 #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
445 #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
446
447 /**
448 * @}
449 */
450 #endif /* STM32F105xC || STM32F107xC */
451
452 #if defined(STM32F105xC) || defined(STM32F107xC)
453 /** @defgroup RCCEx_Prediv1_Source Prediv1 Source
454 * @{
455 */
456
457 #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
458 #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
459
460 /**
461 * @}
462 */
463 #endif /* STM32F105xC || STM32F107xC */
464
465 /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
466 * @{
467 */
468
469 #define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000)
470
471 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
472 || defined(STM32F100xE)
473 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
474 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
475 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
476 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
477 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
478 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
479 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
480 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
481 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
482 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
483 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
484 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
485 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
486 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
487 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
488 #else
489 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
490 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
491
492 /**
493 * @}
494 */
495
496 #if defined(STM32F105xC) || defined(STM32F107xC)
497 /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
498 * @{
499 */
500
501 #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
502 #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
503 #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
504 #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
505 #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
506 #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
507 #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
508 #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
509 #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
510 #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
511 #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
512 #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
513 #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
514 #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
515 #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
516 #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
517
518 /**
519 * @}
520 */
521
522 /** @defgroup RCCEx_PLL2_Config PLL Config
523 * @{
524 */
525 #define RCC_PLL2_NONE ((uint32_t)0x00000000)
526 #define RCC_PLL2_OFF ((uint32_t)0x00000001)
527 #define RCC_PLL2_ON ((uint32_t)0x00000002)
528
529 /**
530 * @}
531 */
532
533 /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
534 * @{
535 */
536
537 #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
538 #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
539 #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
540 #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
541 #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
542 #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
543 #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
544 #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
545 #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
546
547 /**
548 * @}
549 */
550
551 #endif /* STM32F105xC || STM32F107xC */
552
553 /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
554 * @{
555 */
556
557 #if defined(STM32F105xC) || defined(STM32F107xC)
558 #else
559 #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
560 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
561 #endif /* STM32F105xC || STM32F107xC */
562 #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
563 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
564 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
565 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
566 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
567 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
568 #if defined(STM32F105xC) || defined(STM32F107xC)
569 #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
570 #else
571 #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
572 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
573 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
574 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
575 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
576 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
577 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
578 #endif /* STM32F105xC || STM32F107xC */
579
580 /**
581 * @}
582 */
583
584 /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
585 * @{
586 */
587 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
588 #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
589 #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
590 #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
591 #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
592 #if defined(STM32F105xC) || defined(STM32F107xC)
593 #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
594 #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
595 #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
596 #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
597 #endif /* STM32F105xC || STM32F107xC*/
598 /**
599 * @}
600 */
601
602 #if defined(STM32F105xC) || defined(STM32F107xC)
603 /** @defgroup RCCEx_Interrupt RCCEx Interrupt
604 * @{
605 */
606 #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
607 #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
608 /**
609 * @}
610 */
611
612 /** @defgroup RCCEx_Flag RCCEx Flag
613 * Elements values convention: 0XXYYYYYb
614 * - YYYYY : Flag position in the register
615 * - XX : Register index
616 * - 01: CR register
617 * @{
618 */
619 /* Flags in the CR register */
620 #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY)))
621 #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY)))
622 /**
623 * @}
624 */
625 #endif /* STM32F105xC || STM32F107xC*/
626
627 /**
628 * @}
629 */
630
631 /* Exported macro ------------------------------------------------------------*/
632 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
633 * @{
634 */
635
636 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
637 * @brief Enable or disable the AHB1 peripheral clock.
638 * @note After reset, the peripheral clock (used for registers read/write access)
639 * is disabled and the application software has to enable this clock before
640 * using it.
641 * @{
642 */
643
644 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
645 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
646 || defined (STM32F100xE)
647 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
648 __IO uint32_t tmpreg; \
649 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
650 /* Delay after an RCC peripheral clock enabling */ \
651 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
652 UNUSED(tmpreg); \
653 } while(0)
654
655 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
656 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
657
658 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
659 || defined(STM32F103xG) || defined (STM32F100xE)
660 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
661 __IO uint32_t tmpreg; \
662 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
663 /* Delay after an RCC peripheral clock enabling */ \
664 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
665 UNUSED(tmpreg); \
666 } while(0)
667
668 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
669 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
670
671 #if defined(STM32F103xE) || defined(STM32F103xG)
672 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
673 __IO uint32_t tmpreg; \
674 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
675 /* Delay after an RCC peripheral clock enabling */ \
676 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
677 UNUSED(tmpreg); \
678 } while(0)
679
680
681 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
682 #endif /* STM32F103xE || STM32F103xG */
683
684 #if defined(STM32F105xC) || defined(STM32F107xC)
685 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
686 __IO uint32_t tmpreg; \
687 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
688 /* Delay after an RCC peripheral clock enabling */ \
689 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
690 UNUSED(tmpreg); \
691 } while(0)
692
693
694 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
695 #endif /* STM32F105xC || STM32F107xC*/
696
697 #if defined(STM32F107xC)
698 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
699 __IO uint32_t tmpreg; \
700 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
701 /* Delay after an RCC peripheral clock enabling */ \
702 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
703 UNUSED(tmpreg); \
704 } while(0)
705
706 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
707 __IO uint32_t tmpreg; \
708 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
709 /* Delay after an RCC peripheral clock enabling */ \
710 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
711 UNUSED(tmpreg); \
712 } while(0)
713
714 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
715 __IO uint32_t tmpreg; \
716 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
717 /* Delay after an RCC peripheral clock enabling */ \
718 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
719 UNUSED(tmpreg); \
720 } while(0)
721
722 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
723 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
724 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
725
726 /**
727 * @brief Enable ETHERNET clock.
728 */
729 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
730 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
731 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
732 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
733 } while(0)
734 /**
735 * @brief Disable ETHERNET clock.
736 */
737 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
738 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
739 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
740 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
741 } while(0)
742
743 #endif /* STM32F107xC*/
744
745 /**
746 * @}
747 */
748
749 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
750 * @brief Get the enable or disable status of the AHB1 peripheral clock.
751 * @note After reset, the peripheral clock (used for registers read/write access)
752 * is disabled and the application software has to enable this clock before
753 * using it.
754 * @{
755 */
756
757 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
758 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
759 || defined (STM32F100xE)
760 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
761 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
762 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
763 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
764 || defined(STM32F103xG) || defined (STM32F100xE)
765 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
766 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
767 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
768 #if defined(STM32F103xE) || defined(STM32F103xG)
769 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
770 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
771 #endif /* STM32F103xE || STM32F103xG */
772 #if defined(STM32F105xC) || defined(STM32F107xC)
773 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
774 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
775 #endif /* STM32F105xC || STM32F107xC*/
776 #if defined(STM32F107xC)
777 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
778 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
779 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
780 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
781 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
782 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
783 #endif /* STM32F107xC*/
784
785 /**
786 * @}
787 */
788
789 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
790 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
791 * @note After reset, the peripheral clock (used for registers read/write access)
792 * is disabled and the application software has to enable this clock before
793 * using it.
794 * @{
795 */
796
797 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
798 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
799 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
800 __IO uint32_t tmpreg; \
801 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
802 /* Delay after an RCC peripheral clock enabling */ \
803 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
804 UNUSED(tmpreg); \
805 } while(0)
806
807 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
808 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
809
810 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
811 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
812 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
813 || defined(STM32F105xC) || defined(STM32F107xC)
814 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
815 __IO uint32_t tmpreg; \
816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
817 /* Delay after an RCC peripheral clock enabling */ \
818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
819 UNUSED(tmpreg); \
820 } while(0)
821
822 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
823 __IO uint32_t tmpreg; \
824 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
825 /* Delay after an RCC peripheral clock enabling */ \
826 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
827 UNUSED(tmpreg); \
828 } while(0)
829
830 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
831 __IO uint32_t tmpreg; \
832 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
833 /* Delay after an RCC peripheral clock enabling */ \
834 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
835 UNUSED(tmpreg); \
836 } while(0)
837
838 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
839 __IO uint32_t tmpreg; \
840 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
841 /* Delay after an RCC peripheral clock enabling */ \
842 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
843 UNUSED(tmpreg); \
844 } while(0)
845
846 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
847 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
848 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
849 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
850 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
851
852 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
853 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
854 #define __HAL_RCC_USB_CLK_ENABLE() do { \
855 __IO uint32_t tmpreg; \
856 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
857 /* Delay after an RCC peripheral clock enabling */ \
858 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
859 UNUSED(tmpreg); \
860 } while(0)
861
862 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
863 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
864
865 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
866 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
867 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
868 __IO uint32_t tmpreg; \
869 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
870 /* Delay after an RCC peripheral clock enabling */ \
871 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
872 UNUSED(tmpreg); \
873 } while(0)
874
875 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
876 __IO uint32_t tmpreg; \
877 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
878 /* Delay after an RCC peripheral clock enabling */ \
879 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
880 UNUSED(tmpreg); \
881 } while(0)
882
883 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
884 __IO uint32_t tmpreg; \
885 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
886 /* Delay after an RCC peripheral clock enabling */ \
887 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
888 UNUSED(tmpreg); \
889 } while(0)
890
891 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
892 __IO uint32_t tmpreg; \
893 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
894 /* Delay after an RCC peripheral clock enabling */ \
895 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
896 UNUSED(tmpreg); \
897 } while(0)
898
899 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
900 __IO uint32_t tmpreg; \
901 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
902 /* Delay after an RCC peripheral clock enabling */ \
903 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
904 UNUSED(tmpreg); \
905 } while(0)
906
907 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
908 __IO uint32_t tmpreg; \
909 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
910 /* Delay after an RCC peripheral clock enabling */ \
911 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
912 UNUSED(tmpreg); \
913 } while(0)
914
915 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
916 __IO uint32_t tmpreg; \
917 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
918 /* Delay after an RCC peripheral clock enabling */ \
919 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
920 UNUSED(tmpreg); \
921 } while(0)
922
923 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
924 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
925 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
926 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
927 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
928 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
929 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
930 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
931
932 #if defined(STM32F100xB) || defined (STM32F100xE)
933 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
934 __IO uint32_t tmpreg; \
935 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
936 /* Delay after an RCC peripheral clock enabling */ \
937 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
938 UNUSED(tmpreg); \
939 } while(0)
940
941 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
942 __IO uint32_t tmpreg; \
943 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
944 /* Delay after an RCC peripheral clock enabling */ \
945 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
946 UNUSED(tmpreg); \
947 } while(0)
948
949 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
950 __IO uint32_t tmpreg; \
951 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
952 /* Delay after an RCC peripheral clock enabling */ \
953 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
954 UNUSED(tmpreg); \
955 } while(0)
956
957 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
958 __IO uint32_t tmpreg; \
959 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
960 /* Delay after an RCC peripheral clock enabling */ \
961 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
962 UNUSED(tmpreg); \
963 } while(0)
964
965 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
966 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
967 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
968 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
969 #endif /* STM32F100xB || STM32F100xE */
970
971 #ifdef STM32F100xE
972 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
973 __IO uint32_t tmpreg; \
974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
975 /* Delay after an RCC peripheral clock enabling */ \
976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
977 UNUSED(tmpreg); \
978 } while(0)
979
980 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
981 __IO uint32_t tmpreg; \
982 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
983 /* Delay after an RCC peripheral clock enabling */ \
984 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
985 UNUSED(tmpreg); \
986 } while(0)
987
988 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
989 __IO uint32_t tmpreg; \
990 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
991 /* Delay after an RCC peripheral clock enabling */ \
992 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
993 UNUSED(tmpreg); \
994 } while(0)
995
996 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
997 __IO uint32_t tmpreg; \
998 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
999 /* Delay after an RCC peripheral clock enabling */ \
1000 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1001 UNUSED(tmpreg); \
1002 } while(0)
1003
1004 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
1005 __IO uint32_t tmpreg; \
1006 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1007 /* Delay after an RCC peripheral clock enabling */ \
1008 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1009 UNUSED(tmpreg); \
1010 } while(0)
1011
1012 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
1013 __IO uint32_t tmpreg; \
1014 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1015 /* Delay after an RCC peripheral clock enabling */ \
1016 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1017 UNUSED(tmpreg); \
1018 } while(0)
1019
1020 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
1021 __IO uint32_t tmpreg; \
1022 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1023 /* Delay after an RCC peripheral clock enabling */ \
1024 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1025 UNUSED(tmpreg); \
1026 } while(0)
1027
1028 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
1029 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1030 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1031 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1032 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1033 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
1034 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
1035 #endif /* STM32F100xE */
1036
1037 #if defined(STM32F105xC) || defined(STM32F107xC)
1038 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
1039 __IO uint32_t tmpreg; \
1040 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1041 /* Delay after an RCC peripheral clock enabling */ \
1042 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1043 UNUSED(tmpreg); \
1044 } while(0)
1045
1046 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1047 #endif /* STM32F105xC || STM32F107xC */
1048
1049 #if defined(STM32F101xG) || defined(STM32F103xG)
1050 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
1051 __IO uint32_t tmpreg; \
1052 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1053 /* Delay after an RCC peripheral clock enabling */ \
1054 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1055 UNUSED(tmpreg); \
1056 } while(0)
1057
1058 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
1059 __IO uint32_t tmpreg; \
1060 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1061 /* Delay after an RCC peripheral clock enabling */ \
1062 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1063 UNUSED(tmpreg); \
1064 } while(0)
1065
1066 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1067 __IO uint32_t tmpreg; \
1068 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1069 /* Delay after an RCC peripheral clock enabling */ \
1070 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1071 UNUSED(tmpreg); \
1072 } while(0)
1073
1074 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1075 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1076 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1077 #endif /* STM32F101xG || STM32F103xG*/
1078
1079 /**
1080 * @}
1081 */
1082
1083 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
1084 * @brief Get the enable or disable status of the APB1 peripheral clock.
1085 * @note After reset, the peripheral clock (used for registers read/write access)
1086 * is disabled and the application software has to enable this clock before
1087 * using it.
1088 * @{
1089 */
1090
1091 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
1092 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
1093 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
1094 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
1095 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1096 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
1097 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
1098 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
1099 || defined(STM32F105xC) || defined(STM32F107xC)
1100 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
1101 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
1102 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
1103 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
1104 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
1105 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
1106 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
1107 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
1108 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1109 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
1110 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
1111 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
1112 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
1113 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
1114 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1115 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1116 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1117 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
1118 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1119 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1120 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1121 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1122 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1123 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1124 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1125 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1126 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1127 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1128 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1129 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1130 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
1131 #if defined(STM32F100xB) || defined (STM32F100xE)
1132 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1133 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1134 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1135 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1136 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1137 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1138 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
1139 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
1140 #endif /* STM32F100xB || STM32F100xE */
1141 #ifdef STM32F100xE
1142 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1143 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
1144 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1145 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1146 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1147 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1148 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1149 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1150 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1151 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1152 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1153 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1154 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1155 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1156 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1157 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
1158 #endif /* STM32F100xE */
1159 #if defined(STM32F105xC) || defined(STM32F107xC)
1160 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1161 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1162 #endif /* STM32F105xC || STM32F107xC */
1163 #if defined(STM32F101xG) || defined(STM32F103xG)
1164 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1165 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1166 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1167 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1168 #endif /* STM32F101xG || STM32F103xG*/
1169
1170 /**
1171 * @}
1172 */
1173
1174 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
1175 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
1176 * @note After reset, the peripheral clock (used for registers read/write access)
1177 * is disabled and the application software has to enable this clock before
1178 * using it.
1179 * @{
1180 */
1181
1182 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
1183 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
1184 || defined(STM32F103xG)
1185 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
1186 __IO uint32_t tmpreg; \
1187 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1188 /* Delay after an RCC peripheral clock enabling */ \
1189 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1190 UNUSED(tmpreg); \
1191 } while(0)
1192
1193 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1194 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
1195
1196 #if defined(STM32F100xB) || defined(STM32F100xE)
1197 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
1198 __IO uint32_t tmpreg; \
1199 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
1200 /* Delay after an RCC peripheral clock enabling */ \
1201 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
1202 UNUSED(tmpreg); \
1203 } while(0)
1204
1205 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
1206 __IO uint32_t tmpreg; \
1207 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
1208 /* Delay after an RCC peripheral clock enabling */ \
1209 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
1210 UNUSED(tmpreg); \
1211 } while(0)
1212
1213 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
1214 __IO uint32_t tmpreg; \
1215 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
1216 /* Delay after an RCC peripheral clock enabling */ \
1217 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
1218 UNUSED(tmpreg); \
1219 } while(0)
1220
1221 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
1222 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
1223 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
1224 #endif /* STM32F100xB || STM32F100xE */
1225
1226 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
1227 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
1228 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
1229 || defined(STM32F107xC)
1230 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1231 __IO uint32_t tmpreg; \
1232 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
1233 /* Delay after an RCC peripheral clock enabling */ \
1234 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
1235 UNUSED(tmpreg); \
1236 } while(0)
1237
1238 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
1239 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1240
1241 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1242 || defined(STM32F103xG)
1243 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1244 __IO uint32_t tmpreg; \
1245 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1246 /* Delay after an RCC peripheral clock enabling */ \
1247 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1248 UNUSED(tmpreg); \
1249 } while(0)
1250
1251 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1252 __IO uint32_t tmpreg; \
1253 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1254 /* Delay after an RCC peripheral clock enabling */ \
1255 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1256 UNUSED(tmpreg); \
1257 } while(0)
1258
1259 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
1260 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
1261 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
1262
1263 #if defined(STM32F103xE) || defined(STM32F103xG)
1264 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1265 __IO uint32_t tmpreg; \
1266 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1267 /* Delay after an RCC peripheral clock enabling */ \
1268 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1269 UNUSED(tmpreg); \
1270 } while(0)
1271
1272 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1273 __IO uint32_t tmpreg; \
1274 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1275 /* Delay after an RCC peripheral clock enabling */ \
1276 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1277 UNUSED(tmpreg); \
1278 } while(0)
1279
1280 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1281 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1282 #endif /* STM32F103xE || STM32F103xG */
1283
1284 #if defined(STM32F100xE)
1285 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1286 __IO uint32_t tmpreg; \
1287 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1288 /* Delay after an RCC peripheral clock enabling */ \
1289 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1290 UNUSED(tmpreg); \
1291 } while(0)
1292
1293 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1294 __IO uint32_t tmpreg; \
1295 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1296 /* Delay after an RCC peripheral clock enabling */ \
1297 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1298 UNUSED(tmpreg); \
1299 } while(0)
1300
1301 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
1302 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
1303 #endif /* STM32F100xE */
1304
1305 #if defined(STM32F101xG) || defined(STM32F103xG)
1306 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
1307 __IO uint32_t tmpreg; \
1308 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1309 /* Delay after an RCC peripheral clock enabling */ \
1310 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1311 UNUSED(tmpreg); \
1312 } while(0)
1313
1314 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
1315 __IO uint32_t tmpreg; \
1316 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1317 /* Delay after an RCC peripheral clock enabling */ \
1318 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1319 UNUSED(tmpreg); \
1320 } while(0)
1321
1322 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
1323 __IO uint32_t tmpreg; \
1324 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1325 /* Delay after an RCC peripheral clock enabling */ \
1326 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1327 UNUSED(tmpreg); \
1328 } while(0)
1329
1330 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
1331 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1332 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
1333 #endif /* STM32F101xG || STM32F103xG */
1334
1335 /**
1336 * @}
1337 */
1338
1339 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
1340 * @brief Get the enable or disable status of the APB2 peripheral clock.
1341 * @note After reset, the peripheral clock (used for registers read/write access)
1342 * is disabled and the application software has to enable this clock before
1343 * using it.
1344 * @{
1345 */
1346
1347 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
1348 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
1349 || defined(STM32F103xG)
1350 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
1351 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
1352 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
1353 #if defined(STM32F100xB) || defined(STM32F100xE)
1354 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
1355 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
1356 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
1357 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
1358 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
1359 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
1360 #endif /* STM32F100xB || STM32F100xE */
1361 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
1362 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
1363 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
1364 || defined(STM32F107xC)
1365 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
1366 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
1367 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1368 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1369 || defined(STM32F103xG)
1370 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
1371 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
1372 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
1373 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
1374 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
1375 #if defined(STM32F103xE) || defined(STM32F103xG)
1376 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
1377 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
1378 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
1379 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
1380 #endif /* STM32F103xE || STM32F103xG */
1381 #if defined(STM32F100xE)
1382 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
1383 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
1384 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
1385 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
1386 #endif /* STM32F100xE */
1387 #if defined(STM32F101xG) || defined(STM32F103xG)
1388 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
1389 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
1390 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
1391 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
1392 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
1393 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
1394 #endif /* STM32F101xG || STM32F103xG */
1395
1396 /**
1397 * @}
1398 */
1399
1400 #if defined(STM32F105xC) || defined(STM32F107xC)
1401 /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
1402 * @brief Force or release AHB peripheral reset.
1403 * @{
1404 */
1405 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
1406 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
1407 #if defined(STM32F107xC)
1408 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
1409 #endif /* STM32F107xC */
1410
1411 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
1412 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
1413 #if defined(STM32F107xC)
1414 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
1415 #endif /* STM32F107xC */
1416
1417 /**
1418 * @}
1419 */
1420 #endif /* STM32F105xC || STM32F107xC */
1421
1422 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
1423 * @brief Force or release APB1 peripheral reset.
1424 * @{
1425 */
1426
1427 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
1428 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
1429 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
1430
1431 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
1432 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1433
1434 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
1435 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
1436 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
1437 || defined(STM32F105xC) || defined(STM32F107xC)
1438 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
1439 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
1440 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1441 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
1442
1443 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
1444 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
1445 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1446 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
1447 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1448
1449 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
1450 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
1451 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
1452 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
1453 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
1454
1455 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1456 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1457 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
1458 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1459 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1460 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1461 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1462 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1463 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1464
1465 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
1466 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1467 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1468 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1469 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1470 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1471 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1472 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
1473
1474 #if defined(STM32F100xB) || defined (STM32F100xE)
1475 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1476 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1477 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1478 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
1479
1480 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1481 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1482 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1483 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
1484 #endif /* STM32F100xB || STM32F100xE */
1485
1486 #if defined (STM32F100xE)
1487 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
1488 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1489 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1490 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1491 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1492 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1493 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1494
1495 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
1496 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1497 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1498 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1499 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1500 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1501 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1502 #endif /* STM32F100xE */
1503
1504 #if defined(STM32F105xC) || defined(STM32F107xC)
1505 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
1506
1507 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
1508 #endif /* STM32F105xC || STM32F107xC */
1509
1510 #if defined(STM32F101xG) || defined(STM32F103xG)
1511 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1512 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1513 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1514
1515 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1516 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1517 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1518 #endif /* STM32F101xG || STM32F103xG */
1519
1520 /**
1521 * @}
1522 */
1523
1524 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
1525 * @brief Force or release APB2 peripheral reset.
1526 * @{
1527 */
1528
1529 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
1530 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
1531 || defined(STM32F103xG)
1532 #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
1533
1534 #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
1535 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
1536
1537 #if defined(STM32F100xB) || defined(STM32F100xE)
1538 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
1539 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
1540 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
1541
1542 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
1543 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
1544 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
1545 #endif /* STM32F100xB || STM32F100xE */
1546
1547 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
1548 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
1549 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
1550 || defined(STM32F107xC)
1551 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
1552
1553 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
1554 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1555
1556 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1557 || defined(STM32F103xG)
1558 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
1559 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
1560
1561 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
1562 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
1563 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
1564
1565 #if defined(STM32F103xE) || defined(STM32F103xG)
1566 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
1567 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
1568
1569 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
1570 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
1571 #endif /* STM32F103xE || STM32F103xG */
1572
1573 #if defined(STM32F100xE)
1574 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
1575 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
1576
1577 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
1578 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
1579 #endif /* STM32F100xE */
1580
1581 #if defined(STM32F101xG) || defined(STM32F103xG)
1582 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
1583 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
1584 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
1585
1586 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
1587 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1588 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
1589 #endif /* STM32F101xG || STM32F103xG*/
1590
1591 /**
1592 * @}
1593 */
1594
1595 /** @defgroup RCCEx_HSE_Configuration HSE Configuration
1596 * @{
1597 */
1598
1599 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
1600 || defined(STM32F100xE)
1601 /**
1602 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
1603 * @note Predivision factor can not be changed if PLL is used as system clock
1604 * In this case, you have to select another source of the system clock, disable the PLL and
1605 * then change the HSE predivision factor.
1606 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
1607 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
1608 */
1609 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
1610 #else
1611 /**
1612 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
1613 * @note Predivision factor can not be changed if PLL is used as system clock
1614 * In this case, you have to select another source of the system clock, disable the PLL and
1615 * then change the HSE predivision factor.
1616 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
1617 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
1618 */
1619 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
1620 MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
1621
1622 #endif /* STM32F105xC || STM32F107xC */
1623
1624 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
1625 || defined(STM32F100xE)
1626 /**
1627 * @brief Macro to get prediv1 factor for PLL.
1628 */
1629 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
1630
1631 #else
1632 /**
1633 * @brief Macro to get prediv1 factor for PLL.
1634 */
1635 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
1636
1637 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
1638
1639 /**
1640 * @}
1641 */
1642
1643 #if defined(STM32F105xC) || defined(STM32F107xC)
1644 /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
1645 * @{
1646 */
1647
1648 /** @brief Macros to enable the main PLLI2S.
1649 * @note After enabling the main PLLI2S, the application software should wait on
1650 * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
1651 * be used as system clock source.
1652 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
1653 */
1654 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
1655
1656 /** @brief Macros to disable the main PLLI2S.
1657 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
1658 */
1659 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
1660
1661 /** @brief macros to configure the main PLLI2S multiplication factor.
1662 * @note This function must be used only when the main PLLI2S is disabled.
1663 *
1664 * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
1665 * This parameter can be one of the following values:
1666 * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
1667 * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
1668 * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
1669 * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
1670 * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
1671 * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
1672 * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
1673 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
1674 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
1675 *
1676 */
1677 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
1678 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
1679
1680 /**
1681 * @}
1682 */
1683
1684 #endif /* STM32F105xC || STM32F107xC */
1685
1686 /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
1687 * @brief Macros to configure clock source of different peripherals.
1688 * @{
1689 */
1690
1691 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
1692 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
1693 /** @brief Macro to configure the USB clock.
1694 * @param __USBCLKSOURCE__ specifies the USB clock source.
1695 * This parameter can be one of the following values:
1696 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
1697 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
1698 */
1699 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
1700 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
1701
1702 /** @brief Macro to get the USB clock (USBCLK).
1703 * @retval The clock source can be one of the following values:
1704 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
1705 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
1706 */
1707 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
1708
1709 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
1710
1711 #if defined(STM32F105xC) || defined(STM32F107xC)
1712
1713 /** @brief Macro to configure the USB OTSclock.
1714 * @param __USBCLKSOURCE__ specifies the USB clock source.
1715 * This parameter can be one of the following values:
1716 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
1717 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
1718 */
1719 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
1720 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
1721
1722 /** @brief Macro to get the USB clock (USBCLK).
1723 * @retval The clock source can be one of the following values:
1724 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
1725 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
1726 */
1727 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
1728
1729 #endif /* STM32F105xC || STM32F107xC */
1730
1731 /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
1732 * @param __ADCCLKSOURCE__ specifies the ADC clock source.
1733 * This parameter can be one of the following values:
1734 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
1735 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
1736 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
1737 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
1738 */
1739 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
1740 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
1741
1742 /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
1743 * @retval The clock source can be one of the following values:
1744 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
1745 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
1746 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
1747 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
1748 */
1749 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
1750
1751 /**
1752 * @}
1753 */
1754
1755 #if defined(STM32F105xC) || defined(STM32F107xC)
1756
1757 /** @addtogroup RCCEx_HSE_Configuration
1758 * @{
1759 */
1760
1761 /**
1762 * @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
1763 * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
1764 * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
1765 * then change the PREDIV2 factor.
1766 * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
1767 * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
1768 */
1769 #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
1770 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
1771
1772 /**
1773 * @brief Macro to get prediv2 factor for PLL2 & PLL3.
1774 */
1775 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
1776
1777 /**
1778 * @}
1779 */
1780
1781 /** @addtogroup RCCEx_PLLI2S_Configuration
1782 * @{
1783 */
1784
1785 /** @brief Macros to enable the main PLL2.
1786 * @note After enabling the main PLL2, the application software should wait on
1787 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can
1788 * be used as system clock source.
1789 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
1790 */
1791 #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
1792
1793 /** @brief Macros to disable the main PLL2.
1794 * @note The main PLL2 can not be disabled if it is used indirectly as system clock source
1795 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
1796 */
1797 #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
1798
1799 /** @brief macros to configure the main PLL2 multiplication factor.
1800 * @note This function must be used only when the main PLL2 is disabled.
1801 *
1802 * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
1803 * This parameter can be one of the following values:
1804 * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
1805 * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
1806 * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
1807 * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
1808 * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
1809 * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
1810 * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
1811 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
1812 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
1813 *
1814 */
1815 #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
1816 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
1817
1818 /**
1819 * @}
1820 */
1821
1822 /** @defgroup RCCEx_I2S_Configuration I2S Configuration
1823 * @brief Macros to configure clock source of I2S peripherals.
1824 * @{
1825 */
1826
1827 /** @brief Macro to configure the I2S2 clock.
1828 * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source.
1829 * This parameter can be one of the following values:
1830 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
1831 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
1832 */
1833 #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
1834 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
1835
1836 /** @brief Macro to get the I2S2 clock (I2S2CLK).
1837 * @retval The clock source can be one of the following values:
1838 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
1839 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
1840 */
1841 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
1842
1843 /** @brief Macro to configure the I2S3 clock.
1844 * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source.
1845 * This parameter can be one of the following values:
1846 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
1847 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
1848 */
1849 #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
1850 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
1851
1852 /** @brief Macro to get the I2S3 clock (I2S3CLK).
1853 * @retval The clock source can be one of the following values:
1854 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
1855 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
1856 */
1857 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
1858
1859 /**
1860 * @}
1861 */
1862
1863 #endif /* STM32F105xC || STM32F107xC */
1864 /**
1865 * @}
1866 */
1867
1868 /* Exported functions --------------------------------------------------------*/
1869 /** @addtogroup RCCEx_Exported_Functions
1870 * @{
1871 */
1872
1873 /** @addtogroup RCCEx_Exported_Functions_Group1
1874 * @{
1875 */
1876
1877 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1878 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1879 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
1880
1881 /**
1882 * @}
1883 */
1884
1885 #if defined(STM32F105xC) || defined(STM32F107xC)
1886 /** @addtogroup RCCEx_Exported_Functions_Group2
1887 * @{
1888 */
1889 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
1890 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
1891
1892 /**
1893 * @}
1894 */
1895
1896 /** @addtogroup RCCEx_Exported_Functions_Group3
1897 * @{
1898 */
1899 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
1900 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
1901
1902 /**
1903 * @}
1904 */
1905 #endif /* STM32F105xC || STM32F107xC */
1906
1907 /**
1908 * @}
1909 */
1910
1911 /**
1912 * @}
1913 */
1914
1915 /**
1916 * @}
1917 */
1918
1919 #ifdef __cplusplus
1920 }
1921 #endif
1922
1923 #endif /* __STM32F1xx_HAL_RCC_EX_H */
1924
1925 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1926