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comparison l476rg-hal-test/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h @ 0:32a3b1785697

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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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-1:000000000000 0:32a3b1785697
1 /**
2 ******************************************************************************
3 * @file stm32l451xx.h
4 * @author MCD Application Team
5 * @version V1.2.0RC2
6 * @date 29-July-2016
7 * @brief CMSIS STM32L451xx Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral�s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 /** @addtogroup CMSIS_Device
45 * @{
46 */
47
48 /** @addtogroup stm32l451xx
49 * @{
50 */
51
52 #ifndef __STM32L451xx_H
53 #define __STM32L451xx_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif /* __cplusplus */
58
59 /** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63 /**
64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
65 */
66 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
67 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
68 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
70 #define __FPU_PRESENT 1 /*!< FPU present */
71
72 /**
73 * @}
74 */
75
76 /** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80 /**
81 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
88 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
98 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
102 RCC_IRQn = 5, /*!< RCC global Interrupt */
103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
108 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
109 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
110 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
111 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
112 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
113 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
114 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
115 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
121 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
122 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
123 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
138 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
139 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
140 UART4_IRQn = 52, /*!< UART4 global Interrupt */
141 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
142 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
143 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
144 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
145 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
146 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
147 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
148 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
149 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
150 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
151 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
152 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
153 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
154 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
155 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
156 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
157 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
158 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
159 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
160 RNG_IRQn = 80, /*!< RNG global interrupt */
161 FPU_IRQn = 81, /*!< FPU global interrupt */
162 CRS_IRQn = 82, /*!< CRS global interrupt */
163 I2C4_EV_IRQn = 83, /*!< I2C4 Event interrupt */
164 I2C4_ER_IRQn = 84 /*!< I2C4 Error interrupt */
165 } IRQn_Type;
166
167 /**
168 * @}
169 */
170
171 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
172 #include "system_stm32l4xx.h"
173 #include <stdint.h>
174
175 /** @addtogroup Peripheral_registers_structures
176 * @{
177 */
178
179 /**
180 * @brief Analog to Digital Converter
181 */
182
183 typedef struct
184 {
185 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
186 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
187 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
188 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
189 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
190 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
191 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
192 uint32_t RESERVED1; /*!< Reserved, 0x1C */
193 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
194 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
195 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
196 uint32_t RESERVED2; /*!< Reserved, 0x2C */
197 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
198 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
199 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
200 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
201 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
202 uint32_t RESERVED3; /*!< Reserved, 0x44 */
203 uint32_t RESERVED4; /*!< Reserved, 0x48 */
204 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
205 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
206 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
207 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
208 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
209 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
210 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
211 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
212 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
213 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
214 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
215 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
216 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
217 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
218 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
219 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
220 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
221 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
222
223 } ADC_TypeDef;
224
225 typedef struct
226 {
227 uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
228 uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
229 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
230 uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
231 } ADC_Common_TypeDef;
232
233
234 /**
235 * @brief Controller Area Network TxMailBox
236 */
237
238 typedef struct
239 {
240 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
241 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
242 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
243 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
244 } CAN_TxMailBox_TypeDef;
245
246 /**
247 * @brief Controller Area Network FIFOMailBox
248 */
249
250 typedef struct
251 {
252 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
253 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
254 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
255 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
256 } CAN_FIFOMailBox_TypeDef;
257
258 /**
259 * @brief Controller Area Network FilterRegister
260 */
261
262 typedef struct
263 {
264 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
265 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
266 } CAN_FilterRegister_TypeDef;
267
268 /**
269 * @brief Controller Area Network
270 */
271
272 typedef struct
273 {
274 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
275 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
276 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
277 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
278 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
279 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
280 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
281 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
282 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
283 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
284 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
285 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
286 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
287 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
288 uint32_t RESERVED2; /*!< Reserved, 0x208 */
289 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
290 uint32_t RESERVED3; /*!< Reserved, 0x210 */
291 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
292 uint32_t RESERVED4; /*!< Reserved, 0x218 */
293 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
294 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
295 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
296 } CAN_TypeDef;
297
298
299 /**
300 * @brief Comparator
301 */
302
303 typedef struct
304 {
305 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
306 } COMP_TypeDef;
307
308 typedef struct
309 {
310 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
311 } COMP_Common_TypeDef;
312
313 /**
314 * @brief CRC calculation unit
315 */
316
317 typedef struct
318 {
319 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
320 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
321 uint8_t RESERVED0; /*!< Reserved, 0x05 */
322 uint16_t RESERVED1; /*!< Reserved, 0x06 */
323 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
324 uint32_t RESERVED2; /*!< Reserved, 0x0C */
325 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
326 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
327 } CRC_TypeDef;
328
329 /**
330 * @brief Clock Recovery System
331 */
332 typedef struct
333 {
334 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
335 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
336 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
337 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
338 } CRS_TypeDef;
339
340 /**
341 * @brief Digital to Analog Converter
342 */
343
344 typedef struct
345 {
346 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
347 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
348 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
349 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
350 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
351 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
352 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
353 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
354 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
355 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
356 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
357 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
358 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
359 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
360 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
361 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
362 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
363 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
364 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
365 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
366 } DAC_TypeDef;
367
368 /**
369 * @brief DFSDM module registers
370 */
371 typedef struct
372 {
373 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
374 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
375 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
376 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
377 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
378 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
379 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
380 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
381 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
382 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
383 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
384 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
385 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
386 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
387 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
388 } DFSDM_Filter_TypeDef;
389
390 /**
391 * @brief DFSDM channel configuration registers
392 */
393 typedef struct
394 {
395 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
396 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
397 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
398 short circuit detector register, Address offset: 0x08 */
399 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
400 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
401 } DFSDM_Channel_TypeDef;
402
403 /**
404 * @brief Debug MCU
405 */
406
407 typedef struct
408 {
409 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
410 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
411 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
412 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
413 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
414 } DBGMCU_TypeDef;
415
416
417 /**
418 * @brief DMA Controller
419 */
420
421 typedef struct
422 {
423 __IO uint32_t CCR; /*!< DMA channel x configuration register */
424 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
425 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
426 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
427 } DMA_Channel_TypeDef;
428
429 typedef struct
430 {
431 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
432 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
433 } DMA_TypeDef;
434
435 typedef struct
436 {
437 __IO uint32_t CSELR; /*!< DMA channel selection register */
438 } DMA_Request_TypeDef;
439
440 /* Legacy define */
441 #define DMA_request_TypeDef DMA_Request_TypeDef
442
443
444 /**
445 * @brief External Interrupt/Event Controller
446 */
447
448 typedef struct
449 {
450 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
451 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
452 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
453 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
454 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
455 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
456 uint32_t RESERVED1; /*!< Reserved, 0x18 */
457 uint32_t RESERVED2; /*!< Reserved, 0x1C */
458 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
459 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
460 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
461 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
462 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
463 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
464 } EXTI_TypeDef;
465
466
467 /**
468 * @brief Firewall
469 */
470
471 typedef struct
472 {
473 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
474 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
475 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
476 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
477 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
478 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
479 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
480 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
481 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
482 } FIREWALL_TypeDef;
483
484
485 /**
486 * @brief FLASH Registers
487 */
488
489 typedef struct
490 {
491 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
492 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
493 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
494 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
495 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
496 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
497 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
498 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
499 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
500 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
501 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
502 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
503 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
504 } FLASH_TypeDef;
505
506
507
508 /**
509 * @brief General Purpose I/O
510 */
511
512 typedef struct
513 {
514 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
515 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
516 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
517 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
518 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
519 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
520 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
521 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
522 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
523 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
524
525 } GPIO_TypeDef;
526
527
528 /**
529 * @brief Inter-integrated Circuit Interface
530 */
531
532 typedef struct
533 {
534 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
535 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
536 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
537 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
538 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
539 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
540 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
541 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
542 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
543 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
544 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
545 } I2C_TypeDef;
546
547 /**
548 * @brief Independent WATCHDOG
549 */
550
551 typedef struct
552 {
553 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
554 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
555 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
556 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
557 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
558 } IWDG_TypeDef;
559
560 /**
561 * @brief LPTIMER
562 */
563 typedef struct
564 {
565 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
566 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
567 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
568 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
569 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
570 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
571 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
572 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
573 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
574 } LPTIM_TypeDef;
575
576 /**
577 * @brief Operational Amplifier (OPAMP)
578 */
579
580 typedef struct
581 {
582 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
583 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
584 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
585 } OPAMP_TypeDef;
586
587 typedef struct
588 {
589 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
590 } OPAMP_Common_TypeDef;
591
592 /**
593 * @brief Power Control
594 */
595
596 typedef struct
597 {
598 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
599 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
600 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
601 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
602 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
603 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
604 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
605 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
606 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
607 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
608 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
609 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
610 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
611 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
612 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
613 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
614 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
615 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
616 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */
617 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */
618 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */
619 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */
620 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
621 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
622 } PWR_TypeDef;
623
624
625 /**
626 * @brief QUAD Serial Peripheral Interface
627 */
628
629 typedef struct
630 {
631 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
632 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
633 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
634 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
635 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
636 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
637 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
638 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
639 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
640 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
641 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
642 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
643 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
644 } QUADSPI_TypeDef;
645
646
647 /**
648 * @brief Reset and Clock Control
649 */
650
651 typedef struct
652 {
653 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
654 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
655 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
656 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
657 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
658 uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */
659 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
660 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
661 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
662 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
663 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
664 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
665 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
666 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
667 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
668 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
669 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
670 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
671 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
672 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
673 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
674 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
675 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
676 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
677 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
678 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
679 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
680 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
681 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
682 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
683 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
684 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
685 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
686 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
687 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
688 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
689 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
690 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
691 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
692 __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
693 } RCC_TypeDef;
694
695 /**
696 * @brief Real-Time Clock
697 */
698
699 typedef struct
700 {
701 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
702 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
703 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
704 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
705 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
706 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
707 uint32_t reserved; /*!< Reserved */
708 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
709 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
710 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
711 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
712 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
713 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
714 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
715 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
716 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
717 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
718 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
719 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
720 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
721 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
722 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
723 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
724 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
725 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
726 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
727 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
728 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
729 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
730 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
731 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
732 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
733 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
734 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
735 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
736 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
737 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
738 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
739 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
740 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
741 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
742 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
743 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
744 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
745 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
746 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
747 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
748 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
749 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
750 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
751 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
752 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
753 } RTC_TypeDef;
754
755
756 /**
757 * @brief Serial Audio Interface
758 */
759
760 typedef struct
761 {
762 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
763 } SAI_TypeDef;
764
765 typedef struct
766 {
767 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
768 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
769 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
770 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
771 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
772 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
773 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
774 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
775 } SAI_Block_TypeDef;
776
777
778 /**
779 * @brief Secure digital input/output Interface
780 */
781
782 typedef struct
783 {
784 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
785 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
786 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
787 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
788 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
789 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
790 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
791 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
792 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
793 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
794 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
795 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
796 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
797 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
798 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
799 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
800 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
801 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
802 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
803 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
804 } SDMMC_TypeDef;
805
806
807 /**
808 * @brief Serial Peripheral Interface
809 */
810
811 typedef struct
812 {
813 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
814 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
815 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
816 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
817 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
818 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
819 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
820 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
821 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
822 } SPI_TypeDef;
823
824
825 /**
826 * @brief System configuration controller
827 */
828
829 typedef struct
830 {
831 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
832 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
833 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
834 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
835 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
836 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
837 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
838 } SYSCFG_TypeDef;
839
840
841 /**
842 * @brief TIM
843 */
844
845 typedef struct
846 {
847 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
848 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
849 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
850 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
851 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
852 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
853 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
854 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
855 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
856 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
857 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
858 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
859 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
860 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
861 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
862 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
863 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
864 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
865 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
866 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
867 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
868 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
869 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
870 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
871 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
872 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
873 } TIM_TypeDef;
874
875
876 /**
877 * @brief Touch Sensing Controller (TSC)
878 */
879
880 typedef struct
881 {
882 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
883 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
884 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
885 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
886 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
887 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
888 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
889 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
890 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
891 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
892 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
893 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
894 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
895 __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
896 } TSC_TypeDef;
897
898 /**
899 * @brief Universal Synchronous Asynchronous Receiver Transmitter
900 */
901
902 typedef struct
903 {
904 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
905 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
906 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
907 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
908 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
909 uint16_t RESERVED2; /*!< Reserved, 0x12 */
910 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
911 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
912 uint16_t RESERVED3; /*!< Reserved, 0x1A */
913 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
914 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
915 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
916 uint16_t RESERVED4; /*!< Reserved, 0x26 */
917 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
918 uint16_t RESERVED5; /*!< Reserved, 0x2A */
919 } USART_TypeDef;
920
921 /**
922 * @brief VREFBUF
923 */
924
925 typedef struct
926 {
927 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
928 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
929 } VREFBUF_TypeDef;
930
931 /**
932 * @brief Window WATCHDOG
933 */
934
935 typedef struct
936 {
937 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
938 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
939 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
940 } WWDG_TypeDef;
941
942 /**
943 * @brief RNG
944 */
945
946 typedef struct
947 {
948 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
949 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
950 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
951 } RNG_TypeDef;
952
953 /**
954 * @}
955 */
956
957 /** @addtogroup Peripheral_memory_map
958 * @{
959 */
960 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
961 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 128 KB) base address */
962 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
963 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
964 #define QSPI_BASE ((uint32_t)0x90000000U) /*!< QSPI memories accessible over AHB base address */
965 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
966 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
967 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
968 #define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
969
970 /* Legacy defines */
971 #define SRAM_BASE SRAM1_BASE
972 #define SRAM_BB_BASE SRAM1_BB_BASE
973
974 #define SRAM1_SIZE_MAX ((uint32_t)0x00020000U) /*!< maximum SRAM1 size (up to 128 KBytes) */
975 #define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
976
977 /*!< Peripheral memory map */
978 #define APB1PERIPH_BASE PERIPH_BASE
979 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
980 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
981 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
982
983
984 /*!< APB1 peripherals */
985 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
986 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
987 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
988 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
989 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
990 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
991 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
992 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
993 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
994 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
995 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
996 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
997 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
998 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
999 #define CRS_BASE (APB1PERIPH_BASE + 0x6000U)
1000 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1001 #define I2C4_BASE (APB1PERIPH_BASE + 0x8400U)
1002 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1003 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1004 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
1005 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
1006 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
1007 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
1008 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
1009 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
1010
1011
1012 /*!< APB2 peripherals */
1013 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
1014 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
1015 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
1016 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
1017 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
1018 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
1019 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
1020 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
1021 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1022 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
1023 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
1024 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
1025 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
1026 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1027 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1028 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
1029 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
1030 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
1031 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
1032 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
1033 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
1034 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
1035
1036 /*!< AHB1 peripherals */
1037 #define DMA1_BASE (AHB1PERIPH_BASE)
1038 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
1039 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
1040 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
1041 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1042 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
1043
1044
1045 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
1046 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
1047 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
1048 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
1049 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
1050 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
1051 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
1052 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
1053
1054
1055 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
1056 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
1057 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
1058 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
1059 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
1060 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
1061 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
1062 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
1063
1064
1065 /*!< AHB2 peripherals */
1066 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
1067 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
1068 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
1069 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
1070 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
1071 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
1072
1073
1074 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
1075 #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
1076
1077
1078 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
1079
1080
1081
1082 /* Debug MCU registers base address */
1083 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
1084
1085
1086 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
1087 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
1088 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
1089 /**
1090 * @}
1091 */
1092
1093 /** @addtogroup Peripheral_declaration
1094 * @{
1095 */
1096 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1097 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1098 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1099 #define RTC ((RTC_TypeDef *) RTC_BASE)
1100 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1101 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1102 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1103 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1104 #define USART2 ((USART_TypeDef *) USART2_BASE)
1105 #define USART3 ((USART_TypeDef *) USART3_BASE)
1106 #define UART4 ((USART_TypeDef *) UART4_BASE)
1107 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1108 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1109 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1110 #define CRS ((CRS_TypeDef *) CRS_BASE)
1111 #define CAN ((CAN_TypeDef *) CAN1_BASE)
1112 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1113 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1114 #define PWR ((PWR_TypeDef *) PWR_BASE)
1115 #define DAC ((DAC_TypeDef *) DAC1_BASE)
1116 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1117 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1118 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1119 #define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1120 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1121 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1122 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1123
1124 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1125 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1126 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1127 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1128 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1129 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1130 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1131 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1132 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1133 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1134 #define USART1 ((USART_TypeDef *) USART1_BASE)
1135 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1136 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1137 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1138 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1139 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1140 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1141 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1142 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1143 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1144 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1145 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1146 /* Aliases to keep compatibility after DFSDM renaming */
1147 #define DFSDM_Channel0 DFSDM1_Channel0
1148 #define DFSDM_Channel1 DFSDM1_Channel1
1149 #define DFSDM_Channel2 DFSDM1_Channel2
1150 #define DFSDM_Channel3 DFSDM1_Channel3
1151 #define DFSDM_Filter0 DFSDM1_Filter0
1152 #define DFSDM_Filter1 DFSDM1_Filter1
1153 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1154 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1155 #define RCC ((RCC_TypeDef *) RCC_BASE)
1156 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1157 #define CRC ((CRC_TypeDef *) CRC_BASE)
1158 #define TSC ((TSC_TypeDef *) TSC_BASE)
1159
1160 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1161 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1162 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1163 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1164 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1165 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1166 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1167 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1168 #define RNG ((RNG_TypeDef *) RNG_BASE)
1169
1170
1171 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1172 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1173 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1174 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1175 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1176 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1177 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1178 #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
1179
1180
1181 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1182 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1183 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1184 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1185 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1186 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1187 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1188 #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
1189
1190
1191
1192 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1193
1194 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1195
1196 /**
1197 * @}
1198 */
1199
1200 /** @addtogroup Exported_constants
1201 * @{
1202 */
1203
1204 /** @addtogroup Peripheral_Registers_Bits_Definition
1205 * @{
1206 */
1207
1208 /******************************************************************************/
1209 /* Peripheral Registers_Bits_Definition */
1210 /******************************************************************************/
1211
1212 /******************************************************************************/
1213 /* */
1214 /* Analog to Digital Converter */
1215 /* */
1216 /******************************************************************************/
1217
1218 /*
1219 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1220 */
1221 /* Note: No specific macro feature on this device */
1222
1223 /******************** Bit definition for ADC_ISR register *******************/
1224 #define ADC_ISR_ADRDY_Pos (0U)
1225 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1226 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1227 #define ADC_ISR_EOSMP_Pos (1U)
1228 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1229 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1230 #define ADC_ISR_EOC_Pos (2U)
1231 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1232 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1233 #define ADC_ISR_EOS_Pos (3U)
1234 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1235 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1236 #define ADC_ISR_OVR_Pos (4U)
1237 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1238 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1239 #define ADC_ISR_JEOC_Pos (5U)
1240 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1241 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1242 #define ADC_ISR_JEOS_Pos (6U)
1243 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1244 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1245 #define ADC_ISR_AWD1_Pos (7U)
1246 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1247 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1248 #define ADC_ISR_AWD2_Pos (8U)
1249 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1250 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1251 #define ADC_ISR_AWD3_Pos (9U)
1252 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1253 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1254 #define ADC_ISR_JQOVF_Pos (10U)
1255 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1256 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1257
1258 /******************** Bit definition for ADC_IER register *******************/
1259 #define ADC_IER_ADRDYIE_Pos (0U)
1260 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1261 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1262 #define ADC_IER_EOSMPIE_Pos (1U)
1263 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1264 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1265 #define ADC_IER_EOCIE_Pos (2U)
1266 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1267 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1268 #define ADC_IER_EOSIE_Pos (3U)
1269 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1270 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1271 #define ADC_IER_OVRIE_Pos (4U)
1272 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1273 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1274 #define ADC_IER_JEOCIE_Pos (5U)
1275 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1276 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1277 #define ADC_IER_JEOSIE_Pos (6U)
1278 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1279 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1280 #define ADC_IER_AWD1IE_Pos (7U)
1281 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1282 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1283 #define ADC_IER_AWD2IE_Pos (8U)
1284 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1285 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1286 #define ADC_IER_AWD3IE_Pos (9U)
1287 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1288 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1289 #define ADC_IER_JQOVFIE_Pos (10U)
1290 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1291 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1292
1293 /* Legacy defines */
1294 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1295 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1296 #define ADC_IER_EOC (ADC_IER_EOCIE)
1297 #define ADC_IER_EOS (ADC_IER_EOSIE)
1298 #define ADC_IER_OVR (ADC_IER_OVRIE)
1299 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
1300 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
1301 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1302 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1303 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1304 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1305
1306 /******************** Bit definition for ADC_CR register ********************/
1307 #define ADC_CR_ADEN_Pos (0U)
1308 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1309 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1310 #define ADC_CR_ADDIS_Pos (1U)
1311 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1312 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1313 #define ADC_CR_ADSTART_Pos (2U)
1314 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1315 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1316 #define ADC_CR_JADSTART_Pos (3U)
1317 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1318 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1319 #define ADC_CR_ADSTP_Pos (4U)
1320 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1321 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1322 #define ADC_CR_JADSTP_Pos (5U)
1323 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1324 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1325 #define ADC_CR_ADVREGEN_Pos (28U)
1326 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1327 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1328 #define ADC_CR_DEEPPWD_Pos (29U)
1329 #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1330 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1331 #define ADC_CR_ADCALDIF_Pos (30U)
1332 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1333 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1334 #define ADC_CR_ADCAL_Pos (31U)
1335 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1336 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1337
1338 /******************** Bit definition for ADC_CFGR register ******************/
1339 #define ADC_CFGR_DMAEN_Pos (0U)
1340 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1341 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
1342 #define ADC_CFGR_DMACFG_Pos (1U)
1343 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1344 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
1345
1346 #define ADC_CFGR_DFSDMCFG_Pos (2U)
1347 #define ADC_CFGR_DFSDMCFG_Msk (0x1U << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */
1348 #define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */
1349
1350 #define ADC_CFGR_RES_Pos (3U)
1351 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1352 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1353 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1354 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1355
1356 #define ADC_CFGR_ALIGN_Pos (5U)
1357 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1358 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1359
1360 #define ADC_CFGR_EXTSEL_Pos (6U)
1361 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
1362 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1363 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1364 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1365 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1366 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1367
1368 #define ADC_CFGR_EXTEN_Pos (10U)
1369 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1370 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1371 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1372 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1373
1374 #define ADC_CFGR_OVRMOD_Pos (12U)
1375 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1376 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1377 #define ADC_CFGR_CONT_Pos (13U)
1378 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1379 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1380 #define ADC_CFGR_AUTDLY_Pos (14U)
1381 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1382 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1383
1384 #define ADC_CFGR_DISCEN_Pos (16U)
1385 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1386 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1387
1388 #define ADC_CFGR_DISCNUM_Pos (17U)
1389 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1390 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
1391 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1392 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1393 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1394
1395 #define ADC_CFGR_JDISCEN_Pos (20U)
1396 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1397 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
1398 #define ADC_CFGR_JQM_Pos (21U)
1399 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1400 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1401 #define ADC_CFGR_AWD1SGL_Pos (22U)
1402 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1403 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1404 #define ADC_CFGR_AWD1EN_Pos (23U)
1405 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1406 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1407 #define ADC_CFGR_JAWD1EN_Pos (24U)
1408 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1409 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1410 #define ADC_CFGR_JAUTO_Pos (25U)
1411 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1412 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1413
1414 #define ADC_CFGR_AWD1CH_Pos (26U)
1415 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1416 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1417 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1418 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1419 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1420 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1421 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1422
1423 #define ADC_CFGR_JQDIS_Pos (31U)
1424 #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
1425 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1426
1427 /******************** Bit definition for ADC_CFGR2 register *****************/
1428 #define ADC_CFGR2_ROVSE_Pos (0U)
1429 #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1430 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1431 #define ADC_CFGR2_JOVSE_Pos (1U)
1432 #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1433 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1434
1435 #define ADC_CFGR2_OVSR_Pos (2U)
1436 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1437 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1438 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1439 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1440 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1441
1442 #define ADC_CFGR2_OVSS_Pos (5U)
1443 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1444 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1445 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1446 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1447 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1448 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1449
1450 #define ADC_CFGR2_TROVS_Pos (9U)
1451 #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
1452 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1453 #define ADC_CFGR2_ROVSM_Pos (10U)
1454 #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
1455 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1456
1457 /******************** Bit definition for ADC_SMPR1 register *****************/
1458 #define ADC_SMPR1_SMP0_Pos (0U)
1459 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1460 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1461 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1462 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1463 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1464
1465 #define ADC_SMPR1_SMP1_Pos (3U)
1466 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1467 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1468 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1469 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1470 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1471
1472 #define ADC_SMPR1_SMP2_Pos (6U)
1473 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1474 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1475 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1476 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1477 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1478
1479 #define ADC_SMPR1_SMP3_Pos (9U)
1480 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1481 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1482 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1483 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1484 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1485
1486 #define ADC_SMPR1_SMP4_Pos (12U)
1487 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1488 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1489 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1490 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1491 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1492
1493 #define ADC_SMPR1_SMP5_Pos (15U)
1494 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1495 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1496 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1497 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1498 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1499
1500 #define ADC_SMPR1_SMP6_Pos (18U)
1501 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1502 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1503 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1504 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1505 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1506
1507 #define ADC_SMPR1_SMP7_Pos (21U)
1508 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1509 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1510 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1511 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1512 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1513
1514 #define ADC_SMPR1_SMP8_Pos (24U)
1515 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1516 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1517 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1518 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1519 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1520
1521 #define ADC_SMPR1_SMP9_Pos (27U)
1522 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1523 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
1524 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
1525 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
1526 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
1527
1528 #define ADC_SMPR1_SMPPLUS_Pos (31U)
1529 #define ADC_SMPR1_SMPPLUS_Msk (0x1U << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
1530 #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
1531
1532 /******************** Bit definition for ADC_SMPR2 register *****************/
1533 #define ADC_SMPR2_SMP10_Pos (0U)
1534 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
1535 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
1536 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
1537 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
1538 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
1539
1540 #define ADC_SMPR2_SMP11_Pos (3U)
1541 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
1542 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
1543 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
1544 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
1545 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
1546
1547 #define ADC_SMPR2_SMP12_Pos (6U)
1548 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
1549 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
1550 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
1551 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
1552 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
1553
1554 #define ADC_SMPR2_SMP13_Pos (9U)
1555 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
1556 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
1557 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
1558 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
1559 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
1560
1561 #define ADC_SMPR2_SMP14_Pos (12U)
1562 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
1563 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
1564 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
1565 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
1566 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
1567
1568 #define ADC_SMPR2_SMP15_Pos (15U)
1569 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
1570 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
1571 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
1572 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
1573 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
1574
1575 #define ADC_SMPR2_SMP16_Pos (18U)
1576 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
1577 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
1578 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
1579 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
1580 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
1581
1582 #define ADC_SMPR2_SMP17_Pos (21U)
1583 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
1584 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
1585 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
1586 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
1587 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
1588
1589 #define ADC_SMPR2_SMP18_Pos (24U)
1590 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
1591 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
1592 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
1593 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
1594 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
1595
1596 /******************** Bit definition for ADC_TR1 register *******************/
1597 #define ADC_TR1_LT1_Pos (0U)
1598 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1599 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1600 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1601 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1602 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1603 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1604 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1605 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1606 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1607 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1608 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1609 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1610 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1611 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1612
1613 #define ADC_TR1_HT1_Pos (16U)
1614 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1615 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1616 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1617 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1618 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1619 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1620 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1621 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1622 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1623 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1624 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1625 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1626 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1627 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1628
1629 /******************** Bit definition for ADC_TR2 register *******************/
1630 #define ADC_TR2_LT2_Pos (0U)
1631 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
1632 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1633 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
1634 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
1635 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
1636 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
1637 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
1638 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
1639 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
1640 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
1641
1642 #define ADC_TR2_HT2_Pos (16U)
1643 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
1644 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1645 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
1646 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
1647 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
1648 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
1649 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
1650 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
1651 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
1652 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
1653
1654 /******************** Bit definition for ADC_TR3 register *******************/
1655 #define ADC_TR3_LT3_Pos (0U)
1656 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
1657 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1658 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
1659 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
1660 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
1661 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
1662 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
1663 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
1664 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
1665 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
1666
1667 #define ADC_TR3_HT3_Pos (16U)
1668 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
1669 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1670 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
1671 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
1672 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
1673 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
1674 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
1675 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
1676 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
1677 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
1678
1679 /******************** Bit definition for ADC_SQR1 register ******************/
1680 #define ADC_SQR1_L_Pos (0U)
1681 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
1682 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
1683 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
1684 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
1685 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
1686 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
1687
1688 #define ADC_SQR1_SQ1_Pos (6U)
1689 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
1690 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
1691 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
1692 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
1693 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
1694 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
1695 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
1696
1697 #define ADC_SQR1_SQ2_Pos (12U)
1698 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
1699 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
1700 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
1701 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
1702 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
1703 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
1704 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
1705
1706 #define ADC_SQR1_SQ3_Pos (18U)
1707 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
1708 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
1709 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
1710 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
1711 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
1712 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
1713 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
1714
1715 #define ADC_SQR1_SQ4_Pos (24U)
1716 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
1717 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
1718 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
1719 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
1720 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
1721 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
1722 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
1723
1724 /******************** Bit definition for ADC_SQR2 register ******************/
1725 #define ADC_SQR2_SQ5_Pos (0U)
1726 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
1727 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
1728 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
1729 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
1730 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
1731 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
1732 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
1733
1734 #define ADC_SQR2_SQ6_Pos (6U)
1735 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
1736 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
1737 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
1738 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
1739 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
1740 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
1741 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
1742
1743 #define ADC_SQR2_SQ7_Pos (12U)
1744 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
1745 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
1746 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
1747 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
1748 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
1749 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
1750 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
1751
1752 #define ADC_SQR2_SQ8_Pos (18U)
1753 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
1754 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
1755 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
1756 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
1757 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
1758 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
1759 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
1760
1761 #define ADC_SQR2_SQ9_Pos (24U)
1762 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
1763 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
1764 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
1765 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
1766 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
1767 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
1768 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
1769
1770 /******************** Bit definition for ADC_SQR3 register ******************/
1771 #define ADC_SQR3_SQ10_Pos (0U)
1772 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
1773 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
1774 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
1775 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
1776 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
1777 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
1778 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
1779
1780 #define ADC_SQR3_SQ11_Pos (6U)
1781 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
1782 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
1783 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
1784 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
1785 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
1786 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
1787 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
1788
1789 #define ADC_SQR3_SQ12_Pos (12U)
1790 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
1791 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
1792 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
1793 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
1794 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
1795 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
1796 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
1797
1798 #define ADC_SQR3_SQ13_Pos (18U)
1799 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
1800 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
1801 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
1802 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
1803 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
1804 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
1805 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
1806
1807 #define ADC_SQR3_SQ14_Pos (24U)
1808 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
1809 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
1810 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
1811 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
1812 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
1813 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
1814 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
1815
1816 /******************** Bit definition for ADC_SQR4 register ******************/
1817 #define ADC_SQR4_SQ15_Pos (0U)
1818 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
1819 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
1820 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
1821 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
1822 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
1823 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
1824 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
1825
1826 #define ADC_SQR4_SQ16_Pos (6U)
1827 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
1828 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
1829 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
1830 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
1831 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
1832 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
1833 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
1834
1835 /******************** Bit definition for ADC_DR register ********************/
1836 #define ADC_DR_RDATA_Pos (0U)
1837 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
1838 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
1839 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
1840 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
1841 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
1842 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
1843 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
1844 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
1845 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
1846 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
1847 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
1848 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
1849 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
1850 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
1851 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
1852 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
1853 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
1854 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
1855
1856 /******************** Bit definition for ADC_JSQR register ******************/
1857 #define ADC_JSQR_JL_Pos (0U)
1858 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
1859 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
1860 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
1861 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
1862
1863 #define ADC_JSQR_JEXTSEL_Pos (2U)
1864 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
1865 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
1866 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
1867 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
1868 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
1869 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
1870
1871 #define ADC_JSQR_JEXTEN_Pos (6U)
1872 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
1873 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
1874 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
1875 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
1876
1877 #define ADC_JSQR_JSQ1_Pos (8U)
1878 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
1879 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
1880 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
1881 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
1882 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
1883 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
1884 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
1885
1886 #define ADC_JSQR_JSQ2_Pos (14U)
1887 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
1888 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
1889 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
1890 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
1891 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
1892 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
1893 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
1894
1895 #define ADC_JSQR_JSQ3_Pos (20U)
1896 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
1897 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
1898 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
1899 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
1900 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
1901 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
1902 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
1903
1904 #define ADC_JSQR_JSQ4_Pos (26U)
1905 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
1906 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
1907 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
1908 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
1909 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
1910 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
1911 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
1912
1913
1914 /******************** Bit definition for ADC_OFR1 register ******************/
1915 #define ADC_OFR1_OFFSET1_Pos (0U)
1916 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
1917 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
1918 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
1919 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
1920 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
1921 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
1922 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
1923 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
1924 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
1925 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
1926 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
1927 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
1928 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
1929 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
1930
1931 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
1932 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
1933 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
1934 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
1935 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
1936 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
1937 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
1938 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
1939
1940 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
1941 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
1942 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
1943
1944 /******************** Bit definition for ADC_OFR2 register ******************/
1945 #define ADC_OFR2_OFFSET2_Pos (0U)
1946 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
1947 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
1948 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
1949 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
1950 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
1951 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
1952 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
1953 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
1954 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
1955 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
1956 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
1957 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
1958 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
1959 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
1960
1961 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
1962 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
1963 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
1964 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
1965 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
1966 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
1967 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
1968 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
1969
1970 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
1971 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
1972 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
1973
1974 /******************** Bit definition for ADC_OFR3 register ******************/
1975 #define ADC_OFR3_OFFSET3_Pos (0U)
1976 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
1977 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
1978 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
1979 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
1980 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
1981 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
1982 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
1983 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
1984 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
1985 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
1986 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
1987 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
1988 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
1989 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
1990
1991 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
1992 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
1993 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
1994 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
1995 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
1996 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
1997 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
1998 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
1999
2000 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
2001 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
2002 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
2003
2004 /******************** Bit definition for ADC_OFR4 register ******************/
2005 #define ADC_OFR4_OFFSET4_Pos (0U)
2006 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
2007 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
2008 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
2009 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
2010 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
2011 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
2012 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
2013 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
2014 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
2015 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
2016 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
2017 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
2018 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
2019 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
2020
2021 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
2022 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
2023 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
2024 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
2025 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
2026 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
2027 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
2028 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
2029
2030 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
2031 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
2032 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
2033
2034 /******************** Bit definition for ADC_JDR1 register ******************/
2035 #define ADC_JDR1_JDATA_Pos (0U)
2036 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
2037 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
2038 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
2039 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
2040 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
2041 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
2042 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
2043 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
2044 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
2045 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
2046 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
2047 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
2048 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
2049 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
2050 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
2051 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
2052 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
2053 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
2054
2055 /******************** Bit definition for ADC_JDR2 register ******************/
2056 #define ADC_JDR2_JDATA_Pos (0U)
2057 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
2058 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
2059 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
2060 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
2061 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
2062 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
2063 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
2064 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
2065 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
2066 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
2067 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
2068 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
2069 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
2070 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
2071 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
2072 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
2073 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
2074 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
2075
2076 /******************** Bit definition for ADC_JDR3 register ******************/
2077 #define ADC_JDR3_JDATA_Pos (0U)
2078 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
2079 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
2080 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
2081 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
2082 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
2083 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
2084 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
2085 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
2086 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
2087 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
2088 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
2089 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
2090 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
2091 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
2092 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
2093 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
2094 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
2095 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
2096
2097 /******************** Bit definition for ADC_JDR4 register ******************/
2098 #define ADC_JDR4_JDATA_Pos (0U)
2099 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
2100 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
2101 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
2102 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
2103 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
2104 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
2105 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
2106 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
2107 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
2108 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
2109 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
2110 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
2111 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
2112 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
2113 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
2114 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
2115 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
2116 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
2117
2118 /******************** Bit definition for ADC_AWD2CR register ****************/
2119 #define ADC_AWD2CR_AWD2CH_Pos (0U)
2120 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
2121 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
2122 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
2123 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
2124 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
2125 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
2126 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
2127 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
2128 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
2129 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
2130 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
2131 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
2132 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
2133 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
2134 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
2135 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
2136 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
2137 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
2138 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
2139 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
2140 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
2141
2142 /******************** Bit definition for ADC_AWD3CR register ****************/
2143 #define ADC_AWD3CR_AWD3CH_Pos (0U)
2144 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
2145 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
2146 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
2147 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
2148 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
2149 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
2150 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
2151 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
2152 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
2153 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
2154 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
2155 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
2156 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
2157 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
2158 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
2159 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
2160 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
2161 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
2162 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
2163 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
2164 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
2165
2166 /******************** Bit definition for ADC_DIFSEL register ****************/
2167 #define ADC_DIFSEL_DIFSEL_Pos (0U)
2168 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
2169 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
2170 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
2171 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
2172 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
2173 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
2174 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
2175 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
2176 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
2177 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
2178 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
2179 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
2180 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
2181 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
2182 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
2183 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
2184 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
2185 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
2186 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
2187 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
2188 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
2189
2190 /******************** Bit definition for ADC_CALFACT register ***************/
2191 #define ADC_CALFACT_CALFACT_S_Pos (0U)
2192 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
2193 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2194 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
2195 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
2196 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
2197 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
2198 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
2199 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
2200 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
2201
2202 #define ADC_CALFACT_CALFACT_D_Pos (16U)
2203 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
2204 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
2205 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
2206 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
2207 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
2208 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
2209 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2210 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2211 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
2212
2213 /************************* ADC Common registers *****************************/
2214 /******************** Bit definition for ADC_CCR register *******************/
2215 #define ADC_CCR_CKMODE_Pos (16U)
2216 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2217 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2218 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2219 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2220
2221 #define ADC_CCR_PRESC_Pos (18U)
2222 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
2223 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
2224 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
2225 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
2226 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
2227 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
2228
2229 #define ADC_CCR_VREFEN_Pos (22U)
2230 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2231 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2232 #define ADC_CCR_TSEN_Pos (23U)
2233 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
2234 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
2235 #define ADC_CCR_VBATEN_Pos (24U)
2236 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
2237 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
2238
2239 /******************************************************************************/
2240 /* */
2241 /* Controller Area Network */
2242 /* */
2243 /******************************************************************************/
2244 /*!<CAN control and status registers */
2245 /******************* Bit definition for CAN_MCR register ********************/
2246 #define CAN_MCR_INRQ_Pos (0U)
2247 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2248 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2249 #define CAN_MCR_SLEEP_Pos (1U)
2250 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2251 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2252 #define CAN_MCR_TXFP_Pos (2U)
2253 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2254 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2255 #define CAN_MCR_RFLM_Pos (3U)
2256 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2257 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2258 #define CAN_MCR_NART_Pos (4U)
2259 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2260 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2261 #define CAN_MCR_AWUM_Pos (5U)
2262 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2263 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2264 #define CAN_MCR_ABOM_Pos (6U)
2265 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2266 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2267 #define CAN_MCR_TTCM_Pos (7U)
2268 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2269 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2270 #define CAN_MCR_RESET_Pos (15U)
2271 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2272 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2273
2274 /******************* Bit definition for CAN_MSR register ********************/
2275 #define CAN_MSR_INAK_Pos (0U)
2276 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2277 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2278 #define CAN_MSR_SLAK_Pos (1U)
2279 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2280 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2281 #define CAN_MSR_ERRI_Pos (2U)
2282 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2283 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2284 #define CAN_MSR_WKUI_Pos (3U)
2285 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2286 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2287 #define CAN_MSR_SLAKI_Pos (4U)
2288 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2289 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2290 #define CAN_MSR_TXM_Pos (8U)
2291 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2292 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2293 #define CAN_MSR_RXM_Pos (9U)
2294 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2295 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2296 #define CAN_MSR_SAMP_Pos (10U)
2297 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2298 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2299 #define CAN_MSR_RX_Pos (11U)
2300 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2301 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2302
2303 /******************* Bit definition for CAN_TSR register ********************/
2304 #define CAN_TSR_RQCP0_Pos (0U)
2305 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2306 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2307 #define CAN_TSR_TXOK0_Pos (1U)
2308 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2309 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2310 #define CAN_TSR_ALST0_Pos (2U)
2311 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2312 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2313 #define CAN_TSR_TERR0_Pos (3U)
2314 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2315 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2316 #define CAN_TSR_ABRQ0_Pos (7U)
2317 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2318 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2319 #define CAN_TSR_RQCP1_Pos (8U)
2320 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2321 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2322 #define CAN_TSR_TXOK1_Pos (9U)
2323 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2324 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2325 #define CAN_TSR_ALST1_Pos (10U)
2326 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2327 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2328 #define CAN_TSR_TERR1_Pos (11U)
2329 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2330 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2331 #define CAN_TSR_ABRQ1_Pos (15U)
2332 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2333 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2334 #define CAN_TSR_RQCP2_Pos (16U)
2335 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2336 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2337 #define CAN_TSR_TXOK2_Pos (17U)
2338 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2339 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2340 #define CAN_TSR_ALST2_Pos (18U)
2341 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2342 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2343 #define CAN_TSR_TERR2_Pos (19U)
2344 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2345 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2346 #define CAN_TSR_ABRQ2_Pos (23U)
2347 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2348 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2349 #define CAN_TSR_CODE_Pos (24U)
2350 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2351 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2352
2353 #define CAN_TSR_TME_Pos (26U)
2354 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2355 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2356 #define CAN_TSR_TME0_Pos (26U)
2357 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2358 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2359 #define CAN_TSR_TME1_Pos (27U)
2360 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2361 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2362 #define CAN_TSR_TME2_Pos (28U)
2363 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2364 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2365
2366 #define CAN_TSR_LOW_Pos (29U)
2367 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2368 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2369 #define CAN_TSR_LOW0_Pos (29U)
2370 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2371 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2372 #define CAN_TSR_LOW1_Pos (30U)
2373 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2374 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2375 #define CAN_TSR_LOW2_Pos (31U)
2376 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2377 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2378
2379 /******************* Bit definition for CAN_RF0R register *******************/
2380 #define CAN_RF0R_FMP0_Pos (0U)
2381 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2382 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2383 #define CAN_RF0R_FULL0_Pos (3U)
2384 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2385 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2386 #define CAN_RF0R_FOVR0_Pos (4U)
2387 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2388 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2389 #define CAN_RF0R_RFOM0_Pos (5U)
2390 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2391 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2392
2393 /******************* Bit definition for CAN_RF1R register *******************/
2394 #define CAN_RF1R_FMP1_Pos (0U)
2395 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2396 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2397 #define CAN_RF1R_FULL1_Pos (3U)
2398 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2399 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2400 #define CAN_RF1R_FOVR1_Pos (4U)
2401 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2402 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2403 #define CAN_RF1R_RFOM1_Pos (5U)
2404 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2405 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2406
2407 /******************** Bit definition for CAN_IER register *******************/
2408 #define CAN_IER_TMEIE_Pos (0U)
2409 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2410 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2411 #define CAN_IER_FMPIE0_Pos (1U)
2412 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2413 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2414 #define CAN_IER_FFIE0_Pos (2U)
2415 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2416 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2417 #define CAN_IER_FOVIE0_Pos (3U)
2418 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2419 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2420 #define CAN_IER_FMPIE1_Pos (4U)
2421 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2422 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2423 #define CAN_IER_FFIE1_Pos (5U)
2424 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2425 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2426 #define CAN_IER_FOVIE1_Pos (6U)
2427 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2428 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2429 #define CAN_IER_EWGIE_Pos (8U)
2430 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2431 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2432 #define CAN_IER_EPVIE_Pos (9U)
2433 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2434 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2435 #define CAN_IER_BOFIE_Pos (10U)
2436 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2437 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2438 #define CAN_IER_LECIE_Pos (11U)
2439 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2440 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2441 #define CAN_IER_ERRIE_Pos (15U)
2442 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2443 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2444 #define CAN_IER_WKUIE_Pos (16U)
2445 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2446 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2447 #define CAN_IER_SLKIE_Pos (17U)
2448 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2449 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2450
2451 /******************** Bit definition for CAN_ESR register *******************/
2452 #define CAN_ESR_EWGF_Pos (0U)
2453 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2454 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2455 #define CAN_ESR_EPVF_Pos (1U)
2456 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2457 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2458 #define CAN_ESR_BOFF_Pos (2U)
2459 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2460 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2461
2462 #define CAN_ESR_LEC_Pos (4U)
2463 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2464 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2465 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2466 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2467 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2468
2469 #define CAN_ESR_TEC_Pos (16U)
2470 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2471 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2472 #define CAN_ESR_REC_Pos (24U)
2473 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2474 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2475
2476 /******************* Bit definition for CAN_BTR register ********************/
2477 #define CAN_BTR_BRP_Pos (0U)
2478 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2479 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2480 #define CAN_BTR_TS1_Pos (16U)
2481 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2482 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2483 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2484 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2485 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2486 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2487 #define CAN_BTR_TS2_Pos (20U)
2488 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2489 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2490 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2491 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2492 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2493 #define CAN_BTR_SJW_Pos (24U)
2494 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2495 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2496 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2497 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2498 #define CAN_BTR_LBKM_Pos (30U)
2499 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2500 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2501 #define CAN_BTR_SILM_Pos (31U)
2502 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2503 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2504
2505 /*!<Mailbox registers */
2506 /****************** Bit definition for CAN_TI0R register ********************/
2507 #define CAN_TI0R_TXRQ_Pos (0U)
2508 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2509 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2510 #define CAN_TI0R_RTR_Pos (1U)
2511 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2512 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2513 #define CAN_TI0R_IDE_Pos (2U)
2514 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2515 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2516 #define CAN_TI0R_EXID_Pos (3U)
2517 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2518 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2519 #define CAN_TI0R_STID_Pos (21U)
2520 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2521 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2522
2523 /****************** Bit definition for CAN_TDT0R register *******************/
2524 #define CAN_TDT0R_DLC_Pos (0U)
2525 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2526 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2527 #define CAN_TDT0R_TGT_Pos (8U)
2528 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2529 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2530 #define CAN_TDT0R_TIME_Pos (16U)
2531 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2532 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2533
2534 /****************** Bit definition for CAN_TDL0R register *******************/
2535 #define CAN_TDL0R_DATA0_Pos (0U)
2536 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2537 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2538 #define CAN_TDL0R_DATA1_Pos (8U)
2539 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2540 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2541 #define CAN_TDL0R_DATA2_Pos (16U)
2542 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2543 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2544 #define CAN_TDL0R_DATA3_Pos (24U)
2545 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2546 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2547
2548 /****************** Bit definition for CAN_TDH0R register *******************/
2549 #define CAN_TDH0R_DATA4_Pos (0U)
2550 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2551 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2552 #define CAN_TDH0R_DATA5_Pos (8U)
2553 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2554 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2555 #define CAN_TDH0R_DATA6_Pos (16U)
2556 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2557 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2558 #define CAN_TDH0R_DATA7_Pos (24U)
2559 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2560 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2561
2562 /******************* Bit definition for CAN_TI1R register *******************/
2563 #define CAN_TI1R_TXRQ_Pos (0U)
2564 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2565 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2566 #define CAN_TI1R_RTR_Pos (1U)
2567 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2568 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2569 #define CAN_TI1R_IDE_Pos (2U)
2570 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2571 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2572 #define CAN_TI1R_EXID_Pos (3U)
2573 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2574 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2575 #define CAN_TI1R_STID_Pos (21U)
2576 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2577 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2578
2579 /******************* Bit definition for CAN_TDT1R register ******************/
2580 #define CAN_TDT1R_DLC_Pos (0U)
2581 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2582 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2583 #define CAN_TDT1R_TGT_Pos (8U)
2584 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2585 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2586 #define CAN_TDT1R_TIME_Pos (16U)
2587 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2588 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2589
2590 /******************* Bit definition for CAN_TDL1R register ******************/
2591 #define CAN_TDL1R_DATA0_Pos (0U)
2592 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2593 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2594 #define CAN_TDL1R_DATA1_Pos (8U)
2595 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2596 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2597 #define CAN_TDL1R_DATA2_Pos (16U)
2598 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2599 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2600 #define CAN_TDL1R_DATA3_Pos (24U)
2601 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2602 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2603
2604 /******************* Bit definition for CAN_TDH1R register ******************/
2605 #define CAN_TDH1R_DATA4_Pos (0U)
2606 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2607 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2608 #define CAN_TDH1R_DATA5_Pos (8U)
2609 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2610 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2611 #define CAN_TDH1R_DATA6_Pos (16U)
2612 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2613 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2614 #define CAN_TDH1R_DATA7_Pos (24U)
2615 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2616 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2617
2618 /******************* Bit definition for CAN_TI2R register *******************/
2619 #define CAN_TI2R_TXRQ_Pos (0U)
2620 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2621 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2622 #define CAN_TI2R_RTR_Pos (1U)
2623 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2624 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2625 #define CAN_TI2R_IDE_Pos (2U)
2626 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2627 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2628 #define CAN_TI2R_EXID_Pos (3U)
2629 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2630 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2631 #define CAN_TI2R_STID_Pos (21U)
2632 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2633 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2634
2635 /******************* Bit definition for CAN_TDT2R register ******************/
2636 #define CAN_TDT2R_DLC_Pos (0U)
2637 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2638 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2639 #define CAN_TDT2R_TGT_Pos (8U)
2640 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2641 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2642 #define CAN_TDT2R_TIME_Pos (16U)
2643 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2644 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2645
2646 /******************* Bit definition for CAN_TDL2R register ******************/
2647 #define CAN_TDL2R_DATA0_Pos (0U)
2648 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2649 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2650 #define CAN_TDL2R_DATA1_Pos (8U)
2651 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2652 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2653 #define CAN_TDL2R_DATA2_Pos (16U)
2654 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2655 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2656 #define CAN_TDL2R_DATA3_Pos (24U)
2657 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2658 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2659
2660 /******************* Bit definition for CAN_TDH2R register ******************/
2661 #define CAN_TDH2R_DATA4_Pos (0U)
2662 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2663 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2664 #define CAN_TDH2R_DATA5_Pos (8U)
2665 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2666 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2667 #define CAN_TDH2R_DATA6_Pos (16U)
2668 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2669 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2670 #define CAN_TDH2R_DATA7_Pos (24U)
2671 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2672 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2673
2674 /******************* Bit definition for CAN_RI0R register *******************/
2675 #define CAN_RI0R_RTR_Pos (1U)
2676 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2677 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2678 #define CAN_RI0R_IDE_Pos (2U)
2679 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2680 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2681 #define CAN_RI0R_EXID_Pos (3U)
2682 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2683 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2684 #define CAN_RI0R_STID_Pos (21U)
2685 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2686 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2687
2688 /******************* Bit definition for CAN_RDT0R register ******************/
2689 #define CAN_RDT0R_DLC_Pos (0U)
2690 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2691 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2692 #define CAN_RDT0R_FMI_Pos (8U)
2693 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2694 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2695 #define CAN_RDT0R_TIME_Pos (16U)
2696 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2697 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2698
2699 /******************* Bit definition for CAN_RDL0R register ******************/
2700 #define CAN_RDL0R_DATA0_Pos (0U)
2701 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2702 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2703 #define CAN_RDL0R_DATA1_Pos (8U)
2704 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2705 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2706 #define CAN_RDL0R_DATA2_Pos (16U)
2707 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2708 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2709 #define CAN_RDL0R_DATA3_Pos (24U)
2710 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2711 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2712
2713 /******************* Bit definition for CAN_RDH0R register ******************/
2714 #define CAN_RDH0R_DATA4_Pos (0U)
2715 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2716 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2717 #define CAN_RDH0R_DATA5_Pos (8U)
2718 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2719 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2720 #define CAN_RDH0R_DATA6_Pos (16U)
2721 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2722 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2723 #define CAN_RDH0R_DATA7_Pos (24U)
2724 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2725 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2726
2727 /******************* Bit definition for CAN_RI1R register *******************/
2728 #define CAN_RI1R_RTR_Pos (1U)
2729 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2730 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2731 #define CAN_RI1R_IDE_Pos (2U)
2732 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2733 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2734 #define CAN_RI1R_EXID_Pos (3U)
2735 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2736 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2737 #define CAN_RI1R_STID_Pos (21U)
2738 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2739 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2740
2741 /******************* Bit definition for CAN_RDT1R register ******************/
2742 #define CAN_RDT1R_DLC_Pos (0U)
2743 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2744 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2745 #define CAN_RDT1R_FMI_Pos (8U)
2746 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2747 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2748 #define CAN_RDT1R_TIME_Pos (16U)
2749 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2750 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2751
2752 /******************* Bit definition for CAN_RDL1R register ******************/
2753 #define CAN_RDL1R_DATA0_Pos (0U)
2754 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2755 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2756 #define CAN_RDL1R_DATA1_Pos (8U)
2757 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2758 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2759 #define CAN_RDL1R_DATA2_Pos (16U)
2760 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2761 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2762 #define CAN_RDL1R_DATA3_Pos (24U)
2763 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2764 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2765
2766 /******************* Bit definition for CAN_RDH1R register ******************/
2767 #define CAN_RDH1R_DATA4_Pos (0U)
2768 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2769 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2770 #define CAN_RDH1R_DATA5_Pos (8U)
2771 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2772 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2773 #define CAN_RDH1R_DATA6_Pos (16U)
2774 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2775 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2776 #define CAN_RDH1R_DATA7_Pos (24U)
2777 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2778 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2779
2780 /*!<CAN filter registers */
2781 /******************* Bit definition for CAN_FMR register ********************/
2782 #define CAN_FMR_FINIT_Pos (0U)
2783 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2784 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2785
2786 /******************* Bit definition for CAN_FM1R register *******************/
2787 #define CAN_FM1R_FBM_Pos (0U)
2788 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
2789 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2790 #define CAN_FM1R_FBM0_Pos (0U)
2791 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2792 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2793 #define CAN_FM1R_FBM1_Pos (1U)
2794 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2795 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2796 #define CAN_FM1R_FBM2_Pos (2U)
2797 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2798 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2799 #define CAN_FM1R_FBM3_Pos (3U)
2800 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2801 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2802 #define CAN_FM1R_FBM4_Pos (4U)
2803 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2804 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2805 #define CAN_FM1R_FBM5_Pos (5U)
2806 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2807 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2808 #define CAN_FM1R_FBM6_Pos (6U)
2809 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2810 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2811 #define CAN_FM1R_FBM7_Pos (7U)
2812 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2813 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2814 #define CAN_FM1R_FBM8_Pos (8U)
2815 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2816 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2817 #define CAN_FM1R_FBM9_Pos (9U)
2818 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2819 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2820 #define CAN_FM1R_FBM10_Pos (10U)
2821 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2822 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2823 #define CAN_FM1R_FBM11_Pos (11U)
2824 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2825 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2826 #define CAN_FM1R_FBM12_Pos (12U)
2827 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2828 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2829 #define CAN_FM1R_FBM13_Pos (13U)
2830 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2831 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2832
2833 /******************* Bit definition for CAN_FS1R register *******************/
2834 #define CAN_FS1R_FSC_Pos (0U)
2835 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
2836 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2837 #define CAN_FS1R_FSC0_Pos (0U)
2838 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2839 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2840 #define CAN_FS1R_FSC1_Pos (1U)
2841 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2842 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2843 #define CAN_FS1R_FSC2_Pos (2U)
2844 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2845 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2846 #define CAN_FS1R_FSC3_Pos (3U)
2847 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2848 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2849 #define CAN_FS1R_FSC4_Pos (4U)
2850 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2851 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2852 #define CAN_FS1R_FSC5_Pos (5U)
2853 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2854 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2855 #define CAN_FS1R_FSC6_Pos (6U)
2856 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2857 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2858 #define CAN_FS1R_FSC7_Pos (7U)
2859 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2860 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2861 #define CAN_FS1R_FSC8_Pos (8U)
2862 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2863 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2864 #define CAN_FS1R_FSC9_Pos (9U)
2865 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2866 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2867 #define CAN_FS1R_FSC10_Pos (10U)
2868 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2869 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2870 #define CAN_FS1R_FSC11_Pos (11U)
2871 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2872 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2873 #define CAN_FS1R_FSC12_Pos (12U)
2874 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2875 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2876 #define CAN_FS1R_FSC13_Pos (13U)
2877 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2878 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2879
2880 /****************** Bit definition for CAN_FFA1R register *******************/
2881 #define CAN_FFA1R_FFA_Pos (0U)
2882 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
2883 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2884 #define CAN_FFA1R_FFA0_Pos (0U)
2885 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2886 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
2887 #define CAN_FFA1R_FFA1_Pos (1U)
2888 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2889 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
2890 #define CAN_FFA1R_FFA2_Pos (2U)
2891 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2892 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
2893 #define CAN_FFA1R_FFA3_Pos (3U)
2894 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2895 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
2896 #define CAN_FFA1R_FFA4_Pos (4U)
2897 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2898 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
2899 #define CAN_FFA1R_FFA5_Pos (5U)
2900 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2901 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
2902 #define CAN_FFA1R_FFA6_Pos (6U)
2903 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2904 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
2905 #define CAN_FFA1R_FFA7_Pos (7U)
2906 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2907 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
2908 #define CAN_FFA1R_FFA8_Pos (8U)
2909 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2910 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
2911 #define CAN_FFA1R_FFA9_Pos (9U)
2912 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2913 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
2914 #define CAN_FFA1R_FFA10_Pos (10U)
2915 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2916 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
2917 #define CAN_FFA1R_FFA11_Pos (11U)
2918 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2919 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
2920 #define CAN_FFA1R_FFA12_Pos (12U)
2921 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2922 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
2923 #define CAN_FFA1R_FFA13_Pos (13U)
2924 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2925 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
2926
2927 /******************* Bit definition for CAN_FA1R register *******************/
2928 #define CAN_FA1R_FACT_Pos (0U)
2929 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
2930 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2931 #define CAN_FA1R_FACT0_Pos (0U)
2932 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2933 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
2934 #define CAN_FA1R_FACT1_Pos (1U)
2935 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2936 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
2937 #define CAN_FA1R_FACT2_Pos (2U)
2938 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2939 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
2940 #define CAN_FA1R_FACT3_Pos (3U)
2941 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2942 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
2943 #define CAN_FA1R_FACT4_Pos (4U)
2944 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2945 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
2946 #define CAN_FA1R_FACT5_Pos (5U)
2947 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2948 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
2949 #define CAN_FA1R_FACT6_Pos (6U)
2950 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2951 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
2952 #define CAN_FA1R_FACT7_Pos (7U)
2953 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2954 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
2955 #define CAN_FA1R_FACT8_Pos (8U)
2956 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2957 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
2958 #define CAN_FA1R_FACT9_Pos (9U)
2959 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2960 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
2961 #define CAN_FA1R_FACT10_Pos (10U)
2962 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2963 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
2964 #define CAN_FA1R_FACT11_Pos (11U)
2965 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2966 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
2967 #define CAN_FA1R_FACT12_Pos (12U)
2968 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2969 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
2970 #define CAN_FA1R_FACT13_Pos (13U)
2971 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2972 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
2973
2974 /******************* Bit definition for CAN_F0R1 register *******************/
2975 #define CAN_F0R1_FB0_Pos (0U)
2976 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2977 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2978 #define CAN_F0R1_FB1_Pos (1U)
2979 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2980 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2981 #define CAN_F0R1_FB2_Pos (2U)
2982 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2983 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2984 #define CAN_F0R1_FB3_Pos (3U)
2985 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2986 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2987 #define CAN_F0R1_FB4_Pos (4U)
2988 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2989 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2990 #define CAN_F0R1_FB5_Pos (5U)
2991 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2992 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2993 #define CAN_F0R1_FB6_Pos (6U)
2994 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2995 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2996 #define CAN_F0R1_FB7_Pos (7U)
2997 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2998 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2999 #define CAN_F0R1_FB8_Pos (8U)
3000 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
3001 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
3002 #define CAN_F0R1_FB9_Pos (9U)
3003 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
3004 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
3005 #define CAN_F0R1_FB10_Pos (10U)
3006 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
3007 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
3008 #define CAN_F0R1_FB11_Pos (11U)
3009 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
3010 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
3011 #define CAN_F0R1_FB12_Pos (12U)
3012 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
3013 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
3014 #define CAN_F0R1_FB13_Pos (13U)
3015 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
3016 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
3017 #define CAN_F0R1_FB14_Pos (14U)
3018 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
3019 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
3020 #define CAN_F0R1_FB15_Pos (15U)
3021 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3022 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3023 #define CAN_F0R1_FB16_Pos (16U)
3024 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3025 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3026 #define CAN_F0R1_FB17_Pos (17U)
3027 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3028 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3029 #define CAN_F0R1_FB18_Pos (18U)
3030 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3031 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3032 #define CAN_F0R1_FB19_Pos (19U)
3033 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3034 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3035 #define CAN_F0R1_FB20_Pos (20U)
3036 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3037 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3038 #define CAN_F0R1_FB21_Pos (21U)
3039 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3040 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3041 #define CAN_F0R1_FB22_Pos (22U)
3042 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3043 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3044 #define CAN_F0R1_FB23_Pos (23U)
3045 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3046 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3047 #define CAN_F0R1_FB24_Pos (24U)
3048 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3049 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3050 #define CAN_F0R1_FB25_Pos (25U)
3051 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3052 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3053 #define CAN_F0R1_FB26_Pos (26U)
3054 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3055 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3056 #define CAN_F0R1_FB27_Pos (27U)
3057 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3058 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3059 #define CAN_F0R1_FB28_Pos (28U)
3060 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3061 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3062 #define CAN_F0R1_FB29_Pos (29U)
3063 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3064 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3065 #define CAN_F0R1_FB30_Pos (30U)
3066 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3067 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3068 #define CAN_F0R1_FB31_Pos (31U)
3069 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3070 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3071
3072 /******************* Bit definition for CAN_F1R1 register *******************/
3073 #define CAN_F1R1_FB0_Pos (0U)
3074 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3075 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3076 #define CAN_F1R1_FB1_Pos (1U)
3077 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3078 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3079 #define CAN_F1R1_FB2_Pos (2U)
3080 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3081 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3082 #define CAN_F1R1_FB3_Pos (3U)
3083 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3084 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3085 #define CAN_F1R1_FB4_Pos (4U)
3086 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3087 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3088 #define CAN_F1R1_FB5_Pos (5U)
3089 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3090 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3091 #define CAN_F1R1_FB6_Pos (6U)
3092 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3093 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3094 #define CAN_F1R1_FB7_Pos (7U)
3095 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3096 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3097 #define CAN_F1R1_FB8_Pos (8U)
3098 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3099 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3100 #define CAN_F1R1_FB9_Pos (9U)
3101 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3102 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3103 #define CAN_F1R1_FB10_Pos (10U)
3104 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3105 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3106 #define CAN_F1R1_FB11_Pos (11U)
3107 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3108 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3109 #define CAN_F1R1_FB12_Pos (12U)
3110 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3111 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3112 #define CAN_F1R1_FB13_Pos (13U)
3113 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3114 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3115 #define CAN_F1R1_FB14_Pos (14U)
3116 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3117 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3118 #define CAN_F1R1_FB15_Pos (15U)
3119 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3120 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3121 #define CAN_F1R1_FB16_Pos (16U)
3122 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3123 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3124 #define CAN_F1R1_FB17_Pos (17U)
3125 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3126 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3127 #define CAN_F1R1_FB18_Pos (18U)
3128 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3129 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3130 #define CAN_F1R1_FB19_Pos (19U)
3131 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3132 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3133 #define CAN_F1R1_FB20_Pos (20U)
3134 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3135 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3136 #define CAN_F1R1_FB21_Pos (21U)
3137 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3138 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3139 #define CAN_F1R1_FB22_Pos (22U)
3140 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3141 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3142 #define CAN_F1R1_FB23_Pos (23U)
3143 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3144 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3145 #define CAN_F1R1_FB24_Pos (24U)
3146 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3147 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3148 #define CAN_F1R1_FB25_Pos (25U)
3149 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3150 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3151 #define CAN_F1R1_FB26_Pos (26U)
3152 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3153 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3154 #define CAN_F1R1_FB27_Pos (27U)
3155 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3156 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3157 #define CAN_F1R1_FB28_Pos (28U)
3158 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3159 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3160 #define CAN_F1R1_FB29_Pos (29U)
3161 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3162 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3163 #define CAN_F1R1_FB30_Pos (30U)
3164 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3165 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3166 #define CAN_F1R1_FB31_Pos (31U)
3167 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3168 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3169
3170 /******************* Bit definition for CAN_F2R1 register *******************/
3171 #define CAN_F2R1_FB0_Pos (0U)
3172 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3173 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3174 #define CAN_F2R1_FB1_Pos (1U)
3175 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3176 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3177 #define CAN_F2R1_FB2_Pos (2U)
3178 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3179 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3180 #define CAN_F2R1_FB3_Pos (3U)
3181 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3182 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3183 #define CAN_F2R1_FB4_Pos (4U)
3184 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3185 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3186 #define CAN_F2R1_FB5_Pos (5U)
3187 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3188 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3189 #define CAN_F2R1_FB6_Pos (6U)
3190 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3191 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3192 #define CAN_F2R1_FB7_Pos (7U)
3193 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3194 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3195 #define CAN_F2R1_FB8_Pos (8U)
3196 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3197 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3198 #define CAN_F2R1_FB9_Pos (9U)
3199 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3200 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3201 #define CAN_F2R1_FB10_Pos (10U)
3202 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3203 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3204 #define CAN_F2R1_FB11_Pos (11U)
3205 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3206 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3207 #define CAN_F2R1_FB12_Pos (12U)
3208 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3209 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3210 #define CAN_F2R1_FB13_Pos (13U)
3211 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3212 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3213 #define CAN_F2R1_FB14_Pos (14U)
3214 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3215 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3216 #define CAN_F2R1_FB15_Pos (15U)
3217 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3218 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3219 #define CAN_F2R1_FB16_Pos (16U)
3220 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3221 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3222 #define CAN_F2R1_FB17_Pos (17U)
3223 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3224 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3225 #define CAN_F2R1_FB18_Pos (18U)
3226 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3227 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3228 #define CAN_F2R1_FB19_Pos (19U)
3229 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3230 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3231 #define CAN_F2R1_FB20_Pos (20U)
3232 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3233 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3234 #define CAN_F2R1_FB21_Pos (21U)
3235 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3236 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3237 #define CAN_F2R1_FB22_Pos (22U)
3238 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3239 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3240 #define CAN_F2R1_FB23_Pos (23U)
3241 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3242 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3243 #define CAN_F2R1_FB24_Pos (24U)
3244 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3245 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3246 #define CAN_F2R1_FB25_Pos (25U)
3247 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3248 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3249 #define CAN_F2R1_FB26_Pos (26U)
3250 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3251 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3252 #define CAN_F2R1_FB27_Pos (27U)
3253 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3254 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3255 #define CAN_F2R1_FB28_Pos (28U)
3256 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3257 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3258 #define CAN_F2R1_FB29_Pos (29U)
3259 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3260 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3261 #define CAN_F2R1_FB30_Pos (30U)
3262 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3263 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3264 #define CAN_F2R1_FB31_Pos (31U)
3265 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3266 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3267
3268 /******************* Bit definition for CAN_F3R1 register *******************/
3269 #define CAN_F3R1_FB0_Pos (0U)
3270 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3271 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3272 #define CAN_F3R1_FB1_Pos (1U)
3273 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3274 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3275 #define CAN_F3R1_FB2_Pos (2U)
3276 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3277 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3278 #define CAN_F3R1_FB3_Pos (3U)
3279 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3280 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3281 #define CAN_F3R1_FB4_Pos (4U)
3282 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3283 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3284 #define CAN_F3R1_FB5_Pos (5U)
3285 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3286 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3287 #define CAN_F3R1_FB6_Pos (6U)
3288 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3289 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3290 #define CAN_F3R1_FB7_Pos (7U)
3291 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3292 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3293 #define CAN_F3R1_FB8_Pos (8U)
3294 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3295 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3296 #define CAN_F3R1_FB9_Pos (9U)
3297 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3298 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3299 #define CAN_F3R1_FB10_Pos (10U)
3300 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3301 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3302 #define CAN_F3R1_FB11_Pos (11U)
3303 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3304 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3305 #define CAN_F3R1_FB12_Pos (12U)
3306 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3307 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3308 #define CAN_F3R1_FB13_Pos (13U)
3309 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3310 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3311 #define CAN_F3R1_FB14_Pos (14U)
3312 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3313 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3314 #define CAN_F3R1_FB15_Pos (15U)
3315 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3316 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3317 #define CAN_F3R1_FB16_Pos (16U)
3318 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3319 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3320 #define CAN_F3R1_FB17_Pos (17U)
3321 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3322 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3323 #define CAN_F3R1_FB18_Pos (18U)
3324 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3325 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3326 #define CAN_F3R1_FB19_Pos (19U)
3327 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3328 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3329 #define CAN_F3R1_FB20_Pos (20U)
3330 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3331 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3332 #define CAN_F3R1_FB21_Pos (21U)
3333 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3334 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3335 #define CAN_F3R1_FB22_Pos (22U)
3336 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3337 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3338 #define CAN_F3R1_FB23_Pos (23U)
3339 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3340 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3341 #define CAN_F3R1_FB24_Pos (24U)
3342 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3343 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3344 #define CAN_F3R1_FB25_Pos (25U)
3345 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3346 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3347 #define CAN_F3R1_FB26_Pos (26U)
3348 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3349 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3350 #define CAN_F3R1_FB27_Pos (27U)
3351 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3352 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3353 #define CAN_F3R1_FB28_Pos (28U)
3354 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3355 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3356 #define CAN_F3R1_FB29_Pos (29U)
3357 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3358 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3359 #define CAN_F3R1_FB30_Pos (30U)
3360 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3361 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3362 #define CAN_F3R1_FB31_Pos (31U)
3363 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3364 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3365
3366 /******************* Bit definition for CAN_F4R1 register *******************/
3367 #define CAN_F4R1_FB0_Pos (0U)
3368 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3369 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3370 #define CAN_F4R1_FB1_Pos (1U)
3371 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3372 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3373 #define CAN_F4R1_FB2_Pos (2U)
3374 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3375 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3376 #define CAN_F4R1_FB3_Pos (3U)
3377 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3378 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3379 #define CAN_F4R1_FB4_Pos (4U)
3380 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3381 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3382 #define CAN_F4R1_FB5_Pos (5U)
3383 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3384 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3385 #define CAN_F4R1_FB6_Pos (6U)
3386 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3387 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3388 #define CAN_F4R1_FB7_Pos (7U)
3389 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3390 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3391 #define CAN_F4R1_FB8_Pos (8U)
3392 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3393 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3394 #define CAN_F4R1_FB9_Pos (9U)
3395 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3396 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3397 #define CAN_F4R1_FB10_Pos (10U)
3398 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3399 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3400 #define CAN_F4R1_FB11_Pos (11U)
3401 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3402 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3403 #define CAN_F4R1_FB12_Pos (12U)
3404 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3405 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3406 #define CAN_F4R1_FB13_Pos (13U)
3407 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3408 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3409 #define CAN_F4R1_FB14_Pos (14U)
3410 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3411 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3412 #define CAN_F4R1_FB15_Pos (15U)
3413 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3414 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3415 #define CAN_F4R1_FB16_Pos (16U)
3416 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3417 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3418 #define CAN_F4R1_FB17_Pos (17U)
3419 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3420 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3421 #define CAN_F4R1_FB18_Pos (18U)
3422 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3423 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3424 #define CAN_F4R1_FB19_Pos (19U)
3425 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3426 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3427 #define CAN_F4R1_FB20_Pos (20U)
3428 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3429 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3430 #define CAN_F4R1_FB21_Pos (21U)
3431 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3432 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3433 #define CAN_F4R1_FB22_Pos (22U)
3434 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3435 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3436 #define CAN_F4R1_FB23_Pos (23U)
3437 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3438 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3439 #define CAN_F4R1_FB24_Pos (24U)
3440 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3441 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3442 #define CAN_F4R1_FB25_Pos (25U)
3443 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3444 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3445 #define CAN_F4R1_FB26_Pos (26U)
3446 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3447 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3448 #define CAN_F4R1_FB27_Pos (27U)
3449 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3450 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3451 #define CAN_F4R1_FB28_Pos (28U)
3452 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3453 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3454 #define CAN_F4R1_FB29_Pos (29U)
3455 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3456 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3457 #define CAN_F4R1_FB30_Pos (30U)
3458 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3459 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3460 #define CAN_F4R1_FB31_Pos (31U)
3461 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3462 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3463
3464 /******************* Bit definition for CAN_F5R1 register *******************/
3465 #define CAN_F5R1_FB0_Pos (0U)
3466 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3467 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3468 #define CAN_F5R1_FB1_Pos (1U)
3469 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3470 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3471 #define CAN_F5R1_FB2_Pos (2U)
3472 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3473 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3474 #define CAN_F5R1_FB3_Pos (3U)
3475 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3476 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3477 #define CAN_F5R1_FB4_Pos (4U)
3478 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3479 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3480 #define CAN_F5R1_FB5_Pos (5U)
3481 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3482 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3483 #define CAN_F5R1_FB6_Pos (6U)
3484 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3485 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3486 #define CAN_F5R1_FB7_Pos (7U)
3487 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3488 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3489 #define CAN_F5R1_FB8_Pos (8U)
3490 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3491 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3492 #define CAN_F5R1_FB9_Pos (9U)
3493 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3494 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3495 #define CAN_F5R1_FB10_Pos (10U)
3496 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3497 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3498 #define CAN_F5R1_FB11_Pos (11U)
3499 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3500 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3501 #define CAN_F5R1_FB12_Pos (12U)
3502 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3503 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3504 #define CAN_F5R1_FB13_Pos (13U)
3505 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3506 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3507 #define CAN_F5R1_FB14_Pos (14U)
3508 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3509 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3510 #define CAN_F5R1_FB15_Pos (15U)
3511 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3512 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3513 #define CAN_F5R1_FB16_Pos (16U)
3514 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3515 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3516 #define CAN_F5R1_FB17_Pos (17U)
3517 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3518 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3519 #define CAN_F5R1_FB18_Pos (18U)
3520 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3521 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3522 #define CAN_F5R1_FB19_Pos (19U)
3523 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3524 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3525 #define CAN_F5R1_FB20_Pos (20U)
3526 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3527 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3528 #define CAN_F5R1_FB21_Pos (21U)
3529 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3530 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3531 #define CAN_F5R1_FB22_Pos (22U)
3532 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3533 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3534 #define CAN_F5R1_FB23_Pos (23U)
3535 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3536 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3537 #define CAN_F5R1_FB24_Pos (24U)
3538 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3539 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3540 #define CAN_F5R1_FB25_Pos (25U)
3541 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3542 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3543 #define CAN_F5R1_FB26_Pos (26U)
3544 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3545 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3546 #define CAN_F5R1_FB27_Pos (27U)
3547 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3548 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3549 #define CAN_F5R1_FB28_Pos (28U)
3550 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3551 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3552 #define CAN_F5R1_FB29_Pos (29U)
3553 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3554 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3555 #define CAN_F5R1_FB30_Pos (30U)
3556 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3557 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3558 #define CAN_F5R1_FB31_Pos (31U)
3559 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3560 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3561
3562 /******************* Bit definition for CAN_F6R1 register *******************/
3563 #define CAN_F6R1_FB0_Pos (0U)
3564 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3565 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3566 #define CAN_F6R1_FB1_Pos (1U)
3567 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3568 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3569 #define CAN_F6R1_FB2_Pos (2U)
3570 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3571 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3572 #define CAN_F6R1_FB3_Pos (3U)
3573 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3574 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3575 #define CAN_F6R1_FB4_Pos (4U)
3576 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3577 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3578 #define CAN_F6R1_FB5_Pos (5U)
3579 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3580 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3581 #define CAN_F6R1_FB6_Pos (6U)
3582 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3583 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3584 #define CAN_F6R1_FB7_Pos (7U)
3585 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3586 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3587 #define CAN_F6R1_FB8_Pos (8U)
3588 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3589 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3590 #define CAN_F6R1_FB9_Pos (9U)
3591 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3592 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3593 #define CAN_F6R1_FB10_Pos (10U)
3594 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3595 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3596 #define CAN_F6R1_FB11_Pos (11U)
3597 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3598 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3599 #define CAN_F6R1_FB12_Pos (12U)
3600 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3601 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3602 #define CAN_F6R1_FB13_Pos (13U)
3603 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3604 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3605 #define CAN_F6R1_FB14_Pos (14U)
3606 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3607 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3608 #define CAN_F6R1_FB15_Pos (15U)
3609 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3610 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3611 #define CAN_F6R1_FB16_Pos (16U)
3612 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3613 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3614 #define CAN_F6R1_FB17_Pos (17U)
3615 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3616 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3617 #define CAN_F6R1_FB18_Pos (18U)
3618 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3619 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3620 #define CAN_F6R1_FB19_Pos (19U)
3621 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3622 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3623 #define CAN_F6R1_FB20_Pos (20U)
3624 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3625 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3626 #define CAN_F6R1_FB21_Pos (21U)
3627 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3628 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3629 #define CAN_F6R1_FB22_Pos (22U)
3630 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3631 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3632 #define CAN_F6R1_FB23_Pos (23U)
3633 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3634 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3635 #define CAN_F6R1_FB24_Pos (24U)
3636 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3637 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3638 #define CAN_F6R1_FB25_Pos (25U)
3639 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3640 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3641 #define CAN_F6R1_FB26_Pos (26U)
3642 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3643 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3644 #define CAN_F6R1_FB27_Pos (27U)
3645 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3646 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3647 #define CAN_F6R1_FB28_Pos (28U)
3648 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3649 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3650 #define CAN_F6R1_FB29_Pos (29U)
3651 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3652 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3653 #define CAN_F6R1_FB30_Pos (30U)
3654 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3655 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3656 #define CAN_F6R1_FB31_Pos (31U)
3657 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3658 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3659
3660 /******************* Bit definition for CAN_F7R1 register *******************/
3661 #define CAN_F7R1_FB0_Pos (0U)
3662 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3663 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3664 #define CAN_F7R1_FB1_Pos (1U)
3665 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3666 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3667 #define CAN_F7R1_FB2_Pos (2U)
3668 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3669 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3670 #define CAN_F7R1_FB3_Pos (3U)
3671 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3672 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3673 #define CAN_F7R1_FB4_Pos (4U)
3674 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3675 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3676 #define CAN_F7R1_FB5_Pos (5U)
3677 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3678 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3679 #define CAN_F7R1_FB6_Pos (6U)
3680 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3681 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3682 #define CAN_F7R1_FB7_Pos (7U)
3683 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3684 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3685 #define CAN_F7R1_FB8_Pos (8U)
3686 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3687 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3688 #define CAN_F7R1_FB9_Pos (9U)
3689 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3690 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3691 #define CAN_F7R1_FB10_Pos (10U)
3692 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3693 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3694 #define CAN_F7R1_FB11_Pos (11U)
3695 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3696 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3697 #define CAN_F7R1_FB12_Pos (12U)
3698 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3699 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3700 #define CAN_F7R1_FB13_Pos (13U)
3701 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3702 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3703 #define CAN_F7R1_FB14_Pos (14U)
3704 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3705 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3706 #define CAN_F7R1_FB15_Pos (15U)
3707 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3708 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3709 #define CAN_F7R1_FB16_Pos (16U)
3710 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3711 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3712 #define CAN_F7R1_FB17_Pos (17U)
3713 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3714 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3715 #define CAN_F7R1_FB18_Pos (18U)
3716 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3717 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3718 #define CAN_F7R1_FB19_Pos (19U)
3719 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3720 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3721 #define CAN_F7R1_FB20_Pos (20U)
3722 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3723 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3724 #define CAN_F7R1_FB21_Pos (21U)
3725 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3726 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3727 #define CAN_F7R1_FB22_Pos (22U)
3728 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3729 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3730 #define CAN_F7R1_FB23_Pos (23U)
3731 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3732 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3733 #define CAN_F7R1_FB24_Pos (24U)
3734 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3735 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3736 #define CAN_F7R1_FB25_Pos (25U)
3737 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3738 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3739 #define CAN_F7R1_FB26_Pos (26U)
3740 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3741 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3742 #define CAN_F7R1_FB27_Pos (27U)
3743 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3744 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3745 #define CAN_F7R1_FB28_Pos (28U)
3746 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3747 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3748 #define CAN_F7R1_FB29_Pos (29U)
3749 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3750 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3751 #define CAN_F7R1_FB30_Pos (30U)
3752 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3753 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3754 #define CAN_F7R1_FB31_Pos (31U)
3755 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3756 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3757
3758 /******************* Bit definition for CAN_F8R1 register *******************/
3759 #define CAN_F8R1_FB0_Pos (0U)
3760 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3761 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3762 #define CAN_F8R1_FB1_Pos (1U)
3763 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3764 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3765 #define CAN_F8R1_FB2_Pos (2U)
3766 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3767 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3768 #define CAN_F8R1_FB3_Pos (3U)
3769 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3770 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3771 #define CAN_F8R1_FB4_Pos (4U)
3772 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3773 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3774 #define CAN_F8R1_FB5_Pos (5U)
3775 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3776 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3777 #define CAN_F8R1_FB6_Pos (6U)
3778 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3779 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3780 #define CAN_F8R1_FB7_Pos (7U)
3781 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3782 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3783 #define CAN_F8R1_FB8_Pos (8U)
3784 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3785 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3786 #define CAN_F8R1_FB9_Pos (9U)
3787 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3788 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3789 #define CAN_F8R1_FB10_Pos (10U)
3790 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3791 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3792 #define CAN_F8R1_FB11_Pos (11U)
3793 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3794 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3795 #define CAN_F8R1_FB12_Pos (12U)
3796 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3797 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3798 #define CAN_F8R1_FB13_Pos (13U)
3799 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3800 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3801 #define CAN_F8R1_FB14_Pos (14U)
3802 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3803 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3804 #define CAN_F8R1_FB15_Pos (15U)
3805 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3806 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3807 #define CAN_F8R1_FB16_Pos (16U)
3808 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3809 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3810 #define CAN_F8R1_FB17_Pos (17U)
3811 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3812 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3813 #define CAN_F8R1_FB18_Pos (18U)
3814 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3815 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3816 #define CAN_F8R1_FB19_Pos (19U)
3817 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3818 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3819 #define CAN_F8R1_FB20_Pos (20U)
3820 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3821 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3822 #define CAN_F8R1_FB21_Pos (21U)
3823 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3824 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3825 #define CAN_F8R1_FB22_Pos (22U)
3826 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3827 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3828 #define CAN_F8R1_FB23_Pos (23U)
3829 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3830 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3831 #define CAN_F8R1_FB24_Pos (24U)
3832 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3833 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3834 #define CAN_F8R1_FB25_Pos (25U)
3835 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3836 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3837 #define CAN_F8R1_FB26_Pos (26U)
3838 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3839 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3840 #define CAN_F8R1_FB27_Pos (27U)
3841 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3842 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3843 #define CAN_F8R1_FB28_Pos (28U)
3844 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3845 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3846 #define CAN_F8R1_FB29_Pos (29U)
3847 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3848 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3849 #define CAN_F8R1_FB30_Pos (30U)
3850 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3851 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3852 #define CAN_F8R1_FB31_Pos (31U)
3853 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3854 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3855
3856 /******************* Bit definition for CAN_F9R1 register *******************/
3857 #define CAN_F9R1_FB0_Pos (0U)
3858 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3859 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3860 #define CAN_F9R1_FB1_Pos (1U)
3861 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3862 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3863 #define CAN_F9R1_FB2_Pos (2U)
3864 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3865 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3866 #define CAN_F9R1_FB3_Pos (3U)
3867 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3868 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3869 #define CAN_F9R1_FB4_Pos (4U)
3870 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3871 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3872 #define CAN_F9R1_FB5_Pos (5U)
3873 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3874 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3875 #define CAN_F9R1_FB6_Pos (6U)
3876 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3877 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3878 #define CAN_F9R1_FB7_Pos (7U)
3879 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3880 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3881 #define CAN_F9R1_FB8_Pos (8U)
3882 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3883 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3884 #define CAN_F9R1_FB9_Pos (9U)
3885 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3886 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3887 #define CAN_F9R1_FB10_Pos (10U)
3888 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3889 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3890 #define CAN_F9R1_FB11_Pos (11U)
3891 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3892 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3893 #define CAN_F9R1_FB12_Pos (12U)
3894 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3895 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3896 #define CAN_F9R1_FB13_Pos (13U)
3897 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3898 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3899 #define CAN_F9R1_FB14_Pos (14U)
3900 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3901 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3902 #define CAN_F9R1_FB15_Pos (15U)
3903 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3904 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3905 #define CAN_F9R1_FB16_Pos (16U)
3906 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3907 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3908 #define CAN_F9R1_FB17_Pos (17U)
3909 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3910 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3911 #define CAN_F9R1_FB18_Pos (18U)
3912 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3913 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3914 #define CAN_F9R1_FB19_Pos (19U)
3915 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3916 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3917 #define CAN_F9R1_FB20_Pos (20U)
3918 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3919 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3920 #define CAN_F9R1_FB21_Pos (21U)
3921 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3922 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3923 #define CAN_F9R1_FB22_Pos (22U)
3924 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3925 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3926 #define CAN_F9R1_FB23_Pos (23U)
3927 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3928 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3929 #define CAN_F9R1_FB24_Pos (24U)
3930 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3931 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3932 #define CAN_F9R1_FB25_Pos (25U)
3933 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3934 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3935 #define CAN_F9R1_FB26_Pos (26U)
3936 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3937 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3938 #define CAN_F9R1_FB27_Pos (27U)
3939 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3940 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3941 #define CAN_F9R1_FB28_Pos (28U)
3942 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3943 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3944 #define CAN_F9R1_FB29_Pos (29U)
3945 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3946 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3947 #define CAN_F9R1_FB30_Pos (30U)
3948 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3949 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3950 #define CAN_F9R1_FB31_Pos (31U)
3951 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3952 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3953
3954 /******************* Bit definition for CAN_F10R1 register ******************/
3955 #define CAN_F10R1_FB0_Pos (0U)
3956 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3957 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3958 #define CAN_F10R1_FB1_Pos (1U)
3959 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3960 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3961 #define CAN_F10R1_FB2_Pos (2U)
3962 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3963 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3964 #define CAN_F10R1_FB3_Pos (3U)
3965 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3966 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3967 #define CAN_F10R1_FB4_Pos (4U)
3968 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3969 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3970 #define CAN_F10R1_FB5_Pos (5U)
3971 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3972 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3973 #define CAN_F10R1_FB6_Pos (6U)
3974 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3975 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3976 #define CAN_F10R1_FB7_Pos (7U)
3977 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3978 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3979 #define CAN_F10R1_FB8_Pos (8U)
3980 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3981 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3982 #define CAN_F10R1_FB9_Pos (9U)
3983 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3984 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3985 #define CAN_F10R1_FB10_Pos (10U)
3986 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3987 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3988 #define CAN_F10R1_FB11_Pos (11U)
3989 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3990 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3991 #define CAN_F10R1_FB12_Pos (12U)
3992 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3993 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3994 #define CAN_F10R1_FB13_Pos (13U)
3995 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3996 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3997 #define CAN_F10R1_FB14_Pos (14U)
3998 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3999 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
4000 #define CAN_F10R1_FB15_Pos (15U)
4001 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
4002 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
4003 #define CAN_F10R1_FB16_Pos (16U)
4004 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
4005 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
4006 #define CAN_F10R1_FB17_Pos (17U)
4007 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
4008 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
4009 #define CAN_F10R1_FB18_Pos (18U)
4010 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
4011 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
4012 #define CAN_F10R1_FB19_Pos (19U)
4013 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
4014 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
4015 #define CAN_F10R1_FB20_Pos (20U)
4016 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
4017 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
4018 #define CAN_F10R1_FB21_Pos (21U)
4019 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
4020 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
4021 #define CAN_F10R1_FB22_Pos (22U)
4022 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
4023 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
4024 #define CAN_F10R1_FB23_Pos (23U)
4025 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
4026 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
4027 #define CAN_F10R1_FB24_Pos (24U)
4028 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
4029 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
4030 #define CAN_F10R1_FB25_Pos (25U)
4031 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
4032 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
4033 #define CAN_F10R1_FB26_Pos (26U)
4034 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
4035 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
4036 #define CAN_F10R1_FB27_Pos (27U)
4037 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
4038 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
4039 #define CAN_F10R1_FB28_Pos (28U)
4040 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
4041 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
4042 #define CAN_F10R1_FB29_Pos (29U)
4043 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
4044 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
4045 #define CAN_F10R1_FB30_Pos (30U)
4046 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4047 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4048 #define CAN_F10R1_FB31_Pos (31U)
4049 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4050 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4051
4052 /******************* Bit definition for CAN_F11R1 register ******************/
4053 #define CAN_F11R1_FB0_Pos (0U)
4054 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4055 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4056 #define CAN_F11R1_FB1_Pos (1U)
4057 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4058 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4059 #define CAN_F11R1_FB2_Pos (2U)
4060 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4061 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4062 #define CAN_F11R1_FB3_Pos (3U)
4063 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4064 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4065 #define CAN_F11R1_FB4_Pos (4U)
4066 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4067 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4068 #define CAN_F11R1_FB5_Pos (5U)
4069 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4070 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4071 #define CAN_F11R1_FB6_Pos (6U)
4072 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4073 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4074 #define CAN_F11R1_FB7_Pos (7U)
4075 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4076 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4077 #define CAN_F11R1_FB8_Pos (8U)
4078 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4079 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4080 #define CAN_F11R1_FB9_Pos (9U)
4081 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4082 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4083 #define CAN_F11R1_FB10_Pos (10U)
4084 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4085 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4086 #define CAN_F11R1_FB11_Pos (11U)
4087 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4088 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4089 #define CAN_F11R1_FB12_Pos (12U)
4090 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4091 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4092 #define CAN_F11R1_FB13_Pos (13U)
4093 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4094 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4095 #define CAN_F11R1_FB14_Pos (14U)
4096 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4097 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4098 #define CAN_F11R1_FB15_Pos (15U)
4099 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4100 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4101 #define CAN_F11R1_FB16_Pos (16U)
4102 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4103 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4104 #define CAN_F11R1_FB17_Pos (17U)
4105 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4106 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4107 #define CAN_F11R1_FB18_Pos (18U)
4108 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4109 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4110 #define CAN_F11R1_FB19_Pos (19U)
4111 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4112 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4113 #define CAN_F11R1_FB20_Pos (20U)
4114 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4115 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4116 #define CAN_F11R1_FB21_Pos (21U)
4117 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4118 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4119 #define CAN_F11R1_FB22_Pos (22U)
4120 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4121 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4122 #define CAN_F11R1_FB23_Pos (23U)
4123 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4124 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4125 #define CAN_F11R1_FB24_Pos (24U)
4126 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4127 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4128 #define CAN_F11R1_FB25_Pos (25U)
4129 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4130 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4131 #define CAN_F11R1_FB26_Pos (26U)
4132 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4133 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4134 #define CAN_F11R1_FB27_Pos (27U)
4135 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4136 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4137 #define CAN_F11R1_FB28_Pos (28U)
4138 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4139 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4140 #define CAN_F11R1_FB29_Pos (29U)
4141 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4142 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4143 #define CAN_F11R1_FB30_Pos (30U)
4144 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4145 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4146 #define CAN_F11R1_FB31_Pos (31U)
4147 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4148 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4149
4150 /******************* Bit definition for CAN_F12R1 register ******************/
4151 #define CAN_F12R1_FB0_Pos (0U)
4152 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4153 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4154 #define CAN_F12R1_FB1_Pos (1U)
4155 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4156 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4157 #define CAN_F12R1_FB2_Pos (2U)
4158 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4159 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4160 #define CAN_F12R1_FB3_Pos (3U)
4161 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4162 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4163 #define CAN_F12R1_FB4_Pos (4U)
4164 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4165 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4166 #define CAN_F12R1_FB5_Pos (5U)
4167 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4168 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4169 #define CAN_F12R1_FB6_Pos (6U)
4170 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4171 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4172 #define CAN_F12R1_FB7_Pos (7U)
4173 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4174 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4175 #define CAN_F12R1_FB8_Pos (8U)
4176 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4177 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4178 #define CAN_F12R1_FB9_Pos (9U)
4179 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4180 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4181 #define CAN_F12R1_FB10_Pos (10U)
4182 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4183 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4184 #define CAN_F12R1_FB11_Pos (11U)
4185 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4186 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4187 #define CAN_F12R1_FB12_Pos (12U)
4188 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4189 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4190 #define CAN_F12R1_FB13_Pos (13U)
4191 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4192 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4193 #define CAN_F12R1_FB14_Pos (14U)
4194 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4195 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4196 #define CAN_F12R1_FB15_Pos (15U)
4197 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4198 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4199 #define CAN_F12R1_FB16_Pos (16U)
4200 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4201 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4202 #define CAN_F12R1_FB17_Pos (17U)
4203 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4204 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4205 #define CAN_F12R1_FB18_Pos (18U)
4206 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4207 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4208 #define CAN_F12R1_FB19_Pos (19U)
4209 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4210 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4211 #define CAN_F12R1_FB20_Pos (20U)
4212 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4213 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4214 #define CAN_F12R1_FB21_Pos (21U)
4215 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4216 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4217 #define CAN_F12R1_FB22_Pos (22U)
4218 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4219 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4220 #define CAN_F12R1_FB23_Pos (23U)
4221 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4222 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4223 #define CAN_F12R1_FB24_Pos (24U)
4224 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4225 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4226 #define CAN_F12R1_FB25_Pos (25U)
4227 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4228 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4229 #define CAN_F12R1_FB26_Pos (26U)
4230 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4231 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4232 #define CAN_F12R1_FB27_Pos (27U)
4233 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4234 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4235 #define CAN_F12R1_FB28_Pos (28U)
4236 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4237 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4238 #define CAN_F12R1_FB29_Pos (29U)
4239 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4240 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4241 #define CAN_F12R1_FB30_Pos (30U)
4242 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4243 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4244 #define CAN_F12R1_FB31_Pos (31U)
4245 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4246 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4247
4248 /******************* Bit definition for CAN_F13R1 register ******************/
4249 #define CAN_F13R1_FB0_Pos (0U)
4250 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4251 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4252 #define CAN_F13R1_FB1_Pos (1U)
4253 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4254 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4255 #define CAN_F13R1_FB2_Pos (2U)
4256 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4257 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4258 #define CAN_F13R1_FB3_Pos (3U)
4259 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4260 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4261 #define CAN_F13R1_FB4_Pos (4U)
4262 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4263 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4264 #define CAN_F13R1_FB5_Pos (5U)
4265 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4266 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4267 #define CAN_F13R1_FB6_Pos (6U)
4268 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4269 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4270 #define CAN_F13R1_FB7_Pos (7U)
4271 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4272 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4273 #define CAN_F13R1_FB8_Pos (8U)
4274 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4275 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4276 #define CAN_F13R1_FB9_Pos (9U)
4277 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4278 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4279 #define CAN_F13R1_FB10_Pos (10U)
4280 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4281 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4282 #define CAN_F13R1_FB11_Pos (11U)
4283 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4284 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4285 #define CAN_F13R1_FB12_Pos (12U)
4286 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4287 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4288 #define CAN_F13R1_FB13_Pos (13U)
4289 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4290 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4291 #define CAN_F13R1_FB14_Pos (14U)
4292 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4293 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4294 #define CAN_F13R1_FB15_Pos (15U)
4295 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4296 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4297 #define CAN_F13R1_FB16_Pos (16U)
4298 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4299 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4300 #define CAN_F13R1_FB17_Pos (17U)
4301 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4302 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4303 #define CAN_F13R1_FB18_Pos (18U)
4304 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4305 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4306 #define CAN_F13R1_FB19_Pos (19U)
4307 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4308 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4309 #define CAN_F13R1_FB20_Pos (20U)
4310 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4311 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4312 #define CAN_F13R1_FB21_Pos (21U)
4313 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4314 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4315 #define CAN_F13R1_FB22_Pos (22U)
4316 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4317 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4318 #define CAN_F13R1_FB23_Pos (23U)
4319 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4320 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4321 #define CAN_F13R1_FB24_Pos (24U)
4322 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4323 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4324 #define CAN_F13R1_FB25_Pos (25U)
4325 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4326 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4327 #define CAN_F13R1_FB26_Pos (26U)
4328 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4329 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4330 #define CAN_F13R1_FB27_Pos (27U)
4331 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4332 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4333 #define CAN_F13R1_FB28_Pos (28U)
4334 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4335 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4336 #define CAN_F13R1_FB29_Pos (29U)
4337 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4338 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4339 #define CAN_F13R1_FB30_Pos (30U)
4340 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4341 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4342 #define CAN_F13R1_FB31_Pos (31U)
4343 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4344 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4345
4346 /******************* Bit definition for CAN_F0R2 register *******************/
4347 #define CAN_F0R2_FB0_Pos (0U)
4348 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4349 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4350 #define CAN_F0R2_FB1_Pos (1U)
4351 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4352 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4353 #define CAN_F0R2_FB2_Pos (2U)
4354 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4355 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4356 #define CAN_F0R2_FB3_Pos (3U)
4357 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4358 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4359 #define CAN_F0R2_FB4_Pos (4U)
4360 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4361 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4362 #define CAN_F0R2_FB5_Pos (5U)
4363 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4364 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4365 #define CAN_F0R2_FB6_Pos (6U)
4366 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4367 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4368 #define CAN_F0R2_FB7_Pos (7U)
4369 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4370 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4371 #define CAN_F0R2_FB8_Pos (8U)
4372 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4373 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4374 #define CAN_F0R2_FB9_Pos (9U)
4375 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4376 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4377 #define CAN_F0R2_FB10_Pos (10U)
4378 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4379 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4380 #define CAN_F0R2_FB11_Pos (11U)
4381 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4382 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4383 #define CAN_F0R2_FB12_Pos (12U)
4384 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4385 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4386 #define CAN_F0R2_FB13_Pos (13U)
4387 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4388 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4389 #define CAN_F0R2_FB14_Pos (14U)
4390 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4391 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4392 #define CAN_F0R2_FB15_Pos (15U)
4393 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4394 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4395 #define CAN_F0R2_FB16_Pos (16U)
4396 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4397 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4398 #define CAN_F0R2_FB17_Pos (17U)
4399 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4400 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4401 #define CAN_F0R2_FB18_Pos (18U)
4402 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4403 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4404 #define CAN_F0R2_FB19_Pos (19U)
4405 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4406 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4407 #define CAN_F0R2_FB20_Pos (20U)
4408 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4409 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4410 #define CAN_F0R2_FB21_Pos (21U)
4411 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4412 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4413 #define CAN_F0R2_FB22_Pos (22U)
4414 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4415 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4416 #define CAN_F0R2_FB23_Pos (23U)
4417 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4418 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4419 #define CAN_F0R2_FB24_Pos (24U)
4420 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4421 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4422 #define CAN_F0R2_FB25_Pos (25U)
4423 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4424 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4425 #define CAN_F0R2_FB26_Pos (26U)
4426 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4427 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4428 #define CAN_F0R2_FB27_Pos (27U)
4429 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4430 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4431 #define CAN_F0R2_FB28_Pos (28U)
4432 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4433 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4434 #define CAN_F0R2_FB29_Pos (29U)
4435 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4436 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4437 #define CAN_F0R2_FB30_Pos (30U)
4438 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4439 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4440 #define CAN_F0R2_FB31_Pos (31U)
4441 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4442 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4443
4444 /******************* Bit definition for CAN_F1R2 register *******************/
4445 #define CAN_F1R2_FB0_Pos (0U)
4446 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4447 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4448 #define CAN_F1R2_FB1_Pos (1U)
4449 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4450 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4451 #define CAN_F1R2_FB2_Pos (2U)
4452 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4453 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4454 #define CAN_F1R2_FB3_Pos (3U)
4455 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4456 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4457 #define CAN_F1R2_FB4_Pos (4U)
4458 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4459 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4460 #define CAN_F1R2_FB5_Pos (5U)
4461 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4462 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4463 #define CAN_F1R2_FB6_Pos (6U)
4464 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4465 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4466 #define CAN_F1R2_FB7_Pos (7U)
4467 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4468 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4469 #define CAN_F1R2_FB8_Pos (8U)
4470 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4471 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4472 #define CAN_F1R2_FB9_Pos (9U)
4473 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4474 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4475 #define CAN_F1R2_FB10_Pos (10U)
4476 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4477 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4478 #define CAN_F1R2_FB11_Pos (11U)
4479 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4480 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4481 #define CAN_F1R2_FB12_Pos (12U)
4482 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4483 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4484 #define CAN_F1R2_FB13_Pos (13U)
4485 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4486 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4487 #define CAN_F1R2_FB14_Pos (14U)
4488 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4489 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4490 #define CAN_F1R2_FB15_Pos (15U)
4491 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4492 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4493 #define CAN_F1R2_FB16_Pos (16U)
4494 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4495 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4496 #define CAN_F1R2_FB17_Pos (17U)
4497 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4498 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4499 #define CAN_F1R2_FB18_Pos (18U)
4500 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4501 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4502 #define CAN_F1R2_FB19_Pos (19U)
4503 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4504 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4505 #define CAN_F1R2_FB20_Pos (20U)
4506 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4507 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4508 #define CAN_F1R2_FB21_Pos (21U)
4509 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4510 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4511 #define CAN_F1R2_FB22_Pos (22U)
4512 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4513 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4514 #define CAN_F1R2_FB23_Pos (23U)
4515 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4516 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4517 #define CAN_F1R2_FB24_Pos (24U)
4518 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4519 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4520 #define CAN_F1R2_FB25_Pos (25U)
4521 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4522 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4523 #define CAN_F1R2_FB26_Pos (26U)
4524 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4525 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4526 #define CAN_F1R2_FB27_Pos (27U)
4527 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4528 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4529 #define CAN_F1R2_FB28_Pos (28U)
4530 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4531 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4532 #define CAN_F1R2_FB29_Pos (29U)
4533 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4534 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4535 #define CAN_F1R2_FB30_Pos (30U)
4536 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4537 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4538 #define CAN_F1R2_FB31_Pos (31U)
4539 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4540 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4541
4542 /******************* Bit definition for CAN_F2R2 register *******************/
4543 #define CAN_F2R2_FB0_Pos (0U)
4544 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4545 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4546 #define CAN_F2R2_FB1_Pos (1U)
4547 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4548 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4549 #define CAN_F2R2_FB2_Pos (2U)
4550 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4551 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4552 #define CAN_F2R2_FB3_Pos (3U)
4553 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4554 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4555 #define CAN_F2R2_FB4_Pos (4U)
4556 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4557 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4558 #define CAN_F2R2_FB5_Pos (5U)
4559 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4560 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4561 #define CAN_F2R2_FB6_Pos (6U)
4562 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4563 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4564 #define CAN_F2R2_FB7_Pos (7U)
4565 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4566 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4567 #define CAN_F2R2_FB8_Pos (8U)
4568 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4569 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4570 #define CAN_F2R2_FB9_Pos (9U)
4571 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4572 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4573 #define CAN_F2R2_FB10_Pos (10U)
4574 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4575 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4576 #define CAN_F2R2_FB11_Pos (11U)
4577 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4578 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4579 #define CAN_F2R2_FB12_Pos (12U)
4580 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4581 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4582 #define CAN_F2R2_FB13_Pos (13U)
4583 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4584 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4585 #define CAN_F2R2_FB14_Pos (14U)
4586 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4587 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4588 #define CAN_F2R2_FB15_Pos (15U)
4589 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4590 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4591 #define CAN_F2R2_FB16_Pos (16U)
4592 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4593 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4594 #define CAN_F2R2_FB17_Pos (17U)
4595 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4596 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4597 #define CAN_F2R2_FB18_Pos (18U)
4598 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4599 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4600 #define CAN_F2R2_FB19_Pos (19U)
4601 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4602 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4603 #define CAN_F2R2_FB20_Pos (20U)
4604 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4605 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4606 #define CAN_F2R2_FB21_Pos (21U)
4607 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4608 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4609 #define CAN_F2R2_FB22_Pos (22U)
4610 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4611 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4612 #define CAN_F2R2_FB23_Pos (23U)
4613 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4614 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4615 #define CAN_F2R2_FB24_Pos (24U)
4616 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4617 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4618 #define CAN_F2R2_FB25_Pos (25U)
4619 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4620 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4621 #define CAN_F2R2_FB26_Pos (26U)
4622 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4623 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4624 #define CAN_F2R2_FB27_Pos (27U)
4625 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4626 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4627 #define CAN_F2R2_FB28_Pos (28U)
4628 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4629 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4630 #define CAN_F2R2_FB29_Pos (29U)
4631 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4632 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4633 #define CAN_F2R2_FB30_Pos (30U)
4634 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4635 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4636 #define CAN_F2R2_FB31_Pos (31U)
4637 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4638 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4639
4640 /******************* Bit definition for CAN_F3R2 register *******************/
4641 #define CAN_F3R2_FB0_Pos (0U)
4642 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4643 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4644 #define CAN_F3R2_FB1_Pos (1U)
4645 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4646 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4647 #define CAN_F3R2_FB2_Pos (2U)
4648 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4649 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4650 #define CAN_F3R2_FB3_Pos (3U)
4651 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4652 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4653 #define CAN_F3R2_FB4_Pos (4U)
4654 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4655 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4656 #define CAN_F3R2_FB5_Pos (5U)
4657 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4658 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4659 #define CAN_F3R2_FB6_Pos (6U)
4660 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4661 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4662 #define CAN_F3R2_FB7_Pos (7U)
4663 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4664 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4665 #define CAN_F3R2_FB8_Pos (8U)
4666 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4667 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4668 #define CAN_F3R2_FB9_Pos (9U)
4669 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4670 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4671 #define CAN_F3R2_FB10_Pos (10U)
4672 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4673 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4674 #define CAN_F3R2_FB11_Pos (11U)
4675 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4676 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4677 #define CAN_F3R2_FB12_Pos (12U)
4678 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4679 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4680 #define CAN_F3R2_FB13_Pos (13U)
4681 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4682 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4683 #define CAN_F3R2_FB14_Pos (14U)
4684 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4685 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4686 #define CAN_F3R2_FB15_Pos (15U)
4687 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4688 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4689 #define CAN_F3R2_FB16_Pos (16U)
4690 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4691 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4692 #define CAN_F3R2_FB17_Pos (17U)
4693 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4694 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4695 #define CAN_F3R2_FB18_Pos (18U)
4696 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4697 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4698 #define CAN_F3R2_FB19_Pos (19U)
4699 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4700 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4701 #define CAN_F3R2_FB20_Pos (20U)
4702 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4703 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4704 #define CAN_F3R2_FB21_Pos (21U)
4705 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4706 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4707 #define CAN_F3R2_FB22_Pos (22U)
4708 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4709 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4710 #define CAN_F3R2_FB23_Pos (23U)
4711 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4712 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4713 #define CAN_F3R2_FB24_Pos (24U)
4714 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4715 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4716 #define CAN_F3R2_FB25_Pos (25U)
4717 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4718 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4719 #define CAN_F3R2_FB26_Pos (26U)
4720 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4721 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4722 #define CAN_F3R2_FB27_Pos (27U)
4723 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4724 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4725 #define CAN_F3R2_FB28_Pos (28U)
4726 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4727 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4728 #define CAN_F3R2_FB29_Pos (29U)
4729 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4730 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4731 #define CAN_F3R2_FB30_Pos (30U)
4732 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4733 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4734 #define CAN_F3R2_FB31_Pos (31U)
4735 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4736 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4737
4738 /******************* Bit definition for CAN_F4R2 register *******************/
4739 #define CAN_F4R2_FB0_Pos (0U)
4740 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4741 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4742 #define CAN_F4R2_FB1_Pos (1U)
4743 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4744 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4745 #define CAN_F4R2_FB2_Pos (2U)
4746 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4747 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4748 #define CAN_F4R2_FB3_Pos (3U)
4749 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4750 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4751 #define CAN_F4R2_FB4_Pos (4U)
4752 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4753 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4754 #define CAN_F4R2_FB5_Pos (5U)
4755 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4756 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4757 #define CAN_F4R2_FB6_Pos (6U)
4758 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4759 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4760 #define CAN_F4R2_FB7_Pos (7U)
4761 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4762 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4763 #define CAN_F4R2_FB8_Pos (8U)
4764 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4765 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4766 #define CAN_F4R2_FB9_Pos (9U)
4767 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4768 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4769 #define CAN_F4R2_FB10_Pos (10U)
4770 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4771 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4772 #define CAN_F4R2_FB11_Pos (11U)
4773 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4774 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4775 #define CAN_F4R2_FB12_Pos (12U)
4776 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4777 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4778 #define CAN_F4R2_FB13_Pos (13U)
4779 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4780 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4781 #define CAN_F4R2_FB14_Pos (14U)
4782 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4783 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4784 #define CAN_F4R2_FB15_Pos (15U)
4785 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4786 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4787 #define CAN_F4R2_FB16_Pos (16U)
4788 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4789 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4790 #define CAN_F4R2_FB17_Pos (17U)
4791 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4792 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4793 #define CAN_F4R2_FB18_Pos (18U)
4794 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4795 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4796 #define CAN_F4R2_FB19_Pos (19U)
4797 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4798 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4799 #define CAN_F4R2_FB20_Pos (20U)
4800 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4801 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4802 #define CAN_F4R2_FB21_Pos (21U)
4803 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4804 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4805 #define CAN_F4R2_FB22_Pos (22U)
4806 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4807 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4808 #define CAN_F4R2_FB23_Pos (23U)
4809 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4810 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4811 #define CAN_F4R2_FB24_Pos (24U)
4812 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4813 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4814 #define CAN_F4R2_FB25_Pos (25U)
4815 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4816 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4817 #define CAN_F4R2_FB26_Pos (26U)
4818 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4819 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4820 #define CAN_F4R2_FB27_Pos (27U)
4821 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4822 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4823 #define CAN_F4R2_FB28_Pos (28U)
4824 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4825 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4826 #define CAN_F4R2_FB29_Pos (29U)
4827 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4828 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4829 #define CAN_F4R2_FB30_Pos (30U)
4830 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4831 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4832 #define CAN_F4R2_FB31_Pos (31U)
4833 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4834 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4835
4836 /******************* Bit definition for CAN_F5R2 register *******************/
4837 #define CAN_F5R2_FB0_Pos (0U)
4838 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4839 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4840 #define CAN_F5R2_FB1_Pos (1U)
4841 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4842 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4843 #define CAN_F5R2_FB2_Pos (2U)
4844 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4845 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4846 #define CAN_F5R2_FB3_Pos (3U)
4847 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4848 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4849 #define CAN_F5R2_FB4_Pos (4U)
4850 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4851 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4852 #define CAN_F5R2_FB5_Pos (5U)
4853 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4854 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4855 #define CAN_F5R2_FB6_Pos (6U)
4856 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4857 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4858 #define CAN_F5R2_FB7_Pos (7U)
4859 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4860 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4861 #define CAN_F5R2_FB8_Pos (8U)
4862 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4863 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4864 #define CAN_F5R2_FB9_Pos (9U)
4865 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4866 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4867 #define CAN_F5R2_FB10_Pos (10U)
4868 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4869 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4870 #define CAN_F5R2_FB11_Pos (11U)
4871 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4872 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4873 #define CAN_F5R2_FB12_Pos (12U)
4874 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4875 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4876 #define CAN_F5R2_FB13_Pos (13U)
4877 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4878 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4879 #define CAN_F5R2_FB14_Pos (14U)
4880 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4881 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4882 #define CAN_F5R2_FB15_Pos (15U)
4883 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4884 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4885 #define CAN_F5R2_FB16_Pos (16U)
4886 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4887 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4888 #define CAN_F5R2_FB17_Pos (17U)
4889 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4890 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4891 #define CAN_F5R2_FB18_Pos (18U)
4892 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4893 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4894 #define CAN_F5R2_FB19_Pos (19U)
4895 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4896 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4897 #define CAN_F5R2_FB20_Pos (20U)
4898 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4899 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4900 #define CAN_F5R2_FB21_Pos (21U)
4901 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4902 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4903 #define CAN_F5R2_FB22_Pos (22U)
4904 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4905 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4906 #define CAN_F5R2_FB23_Pos (23U)
4907 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4908 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4909 #define CAN_F5R2_FB24_Pos (24U)
4910 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4911 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4912 #define CAN_F5R2_FB25_Pos (25U)
4913 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4914 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4915 #define CAN_F5R2_FB26_Pos (26U)
4916 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4917 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4918 #define CAN_F5R2_FB27_Pos (27U)
4919 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4920 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4921 #define CAN_F5R2_FB28_Pos (28U)
4922 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4923 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4924 #define CAN_F5R2_FB29_Pos (29U)
4925 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4926 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4927 #define CAN_F5R2_FB30_Pos (30U)
4928 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4929 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4930 #define CAN_F5R2_FB31_Pos (31U)
4931 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4932 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4933
4934 /******************* Bit definition for CAN_F6R2 register *******************/
4935 #define CAN_F6R2_FB0_Pos (0U)
4936 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4937 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4938 #define CAN_F6R2_FB1_Pos (1U)
4939 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4940 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4941 #define CAN_F6R2_FB2_Pos (2U)
4942 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4943 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4944 #define CAN_F6R2_FB3_Pos (3U)
4945 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4946 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4947 #define CAN_F6R2_FB4_Pos (4U)
4948 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4949 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4950 #define CAN_F6R2_FB5_Pos (5U)
4951 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4952 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4953 #define CAN_F6R2_FB6_Pos (6U)
4954 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4955 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4956 #define CAN_F6R2_FB7_Pos (7U)
4957 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4958 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4959 #define CAN_F6R2_FB8_Pos (8U)
4960 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4961 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4962 #define CAN_F6R2_FB9_Pos (9U)
4963 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4964 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4965 #define CAN_F6R2_FB10_Pos (10U)
4966 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4967 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4968 #define CAN_F6R2_FB11_Pos (11U)
4969 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4970 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4971 #define CAN_F6R2_FB12_Pos (12U)
4972 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4973 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4974 #define CAN_F6R2_FB13_Pos (13U)
4975 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4976 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4977 #define CAN_F6R2_FB14_Pos (14U)
4978 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4979 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4980 #define CAN_F6R2_FB15_Pos (15U)
4981 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4982 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4983 #define CAN_F6R2_FB16_Pos (16U)
4984 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4985 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4986 #define CAN_F6R2_FB17_Pos (17U)
4987 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4988 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4989 #define CAN_F6R2_FB18_Pos (18U)
4990 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4991 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4992 #define CAN_F6R2_FB19_Pos (19U)
4993 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4994 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4995 #define CAN_F6R2_FB20_Pos (20U)
4996 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4997 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4998 #define CAN_F6R2_FB21_Pos (21U)
4999 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
5000 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
5001 #define CAN_F6R2_FB22_Pos (22U)
5002 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
5003 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
5004 #define CAN_F6R2_FB23_Pos (23U)
5005 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
5006 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
5007 #define CAN_F6R2_FB24_Pos (24U)
5008 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
5009 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
5010 #define CAN_F6R2_FB25_Pos (25U)
5011 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
5012 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
5013 #define CAN_F6R2_FB26_Pos (26U)
5014 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
5015 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
5016 #define CAN_F6R2_FB27_Pos (27U)
5017 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
5018 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
5019 #define CAN_F6R2_FB28_Pos (28U)
5020 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
5021 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
5022 #define CAN_F6R2_FB29_Pos (29U)
5023 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
5024 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
5025 #define CAN_F6R2_FB30_Pos (30U)
5026 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
5027 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
5028 #define CAN_F6R2_FB31_Pos (31U)
5029 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
5030 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
5031
5032 /******************* Bit definition for CAN_F7R2 register *******************/
5033 #define CAN_F7R2_FB0_Pos (0U)
5034 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
5035 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
5036 #define CAN_F7R2_FB1_Pos (1U)
5037 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
5038 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
5039 #define CAN_F7R2_FB2_Pos (2U)
5040 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
5041 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
5042 #define CAN_F7R2_FB3_Pos (3U)
5043 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
5044 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
5045 #define CAN_F7R2_FB4_Pos (4U)
5046 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5047 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5048 #define CAN_F7R2_FB5_Pos (5U)
5049 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5050 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5051 #define CAN_F7R2_FB6_Pos (6U)
5052 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5053 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5054 #define CAN_F7R2_FB7_Pos (7U)
5055 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5056 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5057 #define CAN_F7R2_FB8_Pos (8U)
5058 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5059 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5060 #define CAN_F7R2_FB9_Pos (9U)
5061 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5062 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5063 #define CAN_F7R2_FB10_Pos (10U)
5064 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5065 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5066 #define CAN_F7R2_FB11_Pos (11U)
5067 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5068 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5069 #define CAN_F7R2_FB12_Pos (12U)
5070 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5071 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5072 #define CAN_F7R2_FB13_Pos (13U)
5073 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5074 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5075 #define CAN_F7R2_FB14_Pos (14U)
5076 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5077 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5078 #define CAN_F7R2_FB15_Pos (15U)
5079 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5080 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5081 #define CAN_F7R2_FB16_Pos (16U)
5082 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5083 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5084 #define CAN_F7R2_FB17_Pos (17U)
5085 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5086 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5087 #define CAN_F7R2_FB18_Pos (18U)
5088 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5089 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5090 #define CAN_F7R2_FB19_Pos (19U)
5091 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5092 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5093 #define CAN_F7R2_FB20_Pos (20U)
5094 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5095 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5096 #define CAN_F7R2_FB21_Pos (21U)
5097 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5098 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5099 #define CAN_F7R2_FB22_Pos (22U)
5100 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5101 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5102 #define CAN_F7R2_FB23_Pos (23U)
5103 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5104 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5105 #define CAN_F7R2_FB24_Pos (24U)
5106 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5107 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5108 #define CAN_F7R2_FB25_Pos (25U)
5109 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5110 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5111 #define CAN_F7R2_FB26_Pos (26U)
5112 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5113 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5114 #define CAN_F7R2_FB27_Pos (27U)
5115 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5116 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5117 #define CAN_F7R2_FB28_Pos (28U)
5118 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5119 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5120 #define CAN_F7R2_FB29_Pos (29U)
5121 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5122 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5123 #define CAN_F7R2_FB30_Pos (30U)
5124 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5125 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5126 #define CAN_F7R2_FB31_Pos (31U)
5127 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5128 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5129
5130 /******************* Bit definition for CAN_F8R2 register *******************/
5131 #define CAN_F8R2_FB0_Pos (0U)
5132 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5133 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5134 #define CAN_F8R2_FB1_Pos (1U)
5135 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5136 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5137 #define CAN_F8R2_FB2_Pos (2U)
5138 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5139 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5140 #define CAN_F8R2_FB3_Pos (3U)
5141 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5142 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5143 #define CAN_F8R2_FB4_Pos (4U)
5144 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5145 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5146 #define CAN_F8R2_FB5_Pos (5U)
5147 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5148 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5149 #define CAN_F8R2_FB6_Pos (6U)
5150 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5151 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5152 #define CAN_F8R2_FB7_Pos (7U)
5153 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5154 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5155 #define CAN_F8R2_FB8_Pos (8U)
5156 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5157 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5158 #define CAN_F8R2_FB9_Pos (9U)
5159 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5160 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5161 #define CAN_F8R2_FB10_Pos (10U)
5162 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5163 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5164 #define CAN_F8R2_FB11_Pos (11U)
5165 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5166 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5167 #define CAN_F8R2_FB12_Pos (12U)
5168 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5169 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5170 #define CAN_F8R2_FB13_Pos (13U)
5171 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5172 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5173 #define CAN_F8R2_FB14_Pos (14U)
5174 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5175 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5176 #define CAN_F8R2_FB15_Pos (15U)
5177 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5178 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5179 #define CAN_F8R2_FB16_Pos (16U)
5180 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5181 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5182 #define CAN_F8R2_FB17_Pos (17U)
5183 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5184 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5185 #define CAN_F8R2_FB18_Pos (18U)
5186 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5187 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5188 #define CAN_F8R2_FB19_Pos (19U)
5189 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5190 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5191 #define CAN_F8R2_FB20_Pos (20U)
5192 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5193 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5194 #define CAN_F8R2_FB21_Pos (21U)
5195 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5196 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5197 #define CAN_F8R2_FB22_Pos (22U)
5198 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5199 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5200 #define CAN_F8R2_FB23_Pos (23U)
5201 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5202 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5203 #define CAN_F8R2_FB24_Pos (24U)
5204 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5205 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5206 #define CAN_F8R2_FB25_Pos (25U)
5207 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5208 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5209 #define CAN_F8R2_FB26_Pos (26U)
5210 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5211 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5212 #define CAN_F8R2_FB27_Pos (27U)
5213 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5214 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5215 #define CAN_F8R2_FB28_Pos (28U)
5216 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5217 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5218 #define CAN_F8R2_FB29_Pos (29U)
5219 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5220 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5221 #define CAN_F8R2_FB30_Pos (30U)
5222 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5223 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5224 #define CAN_F8R2_FB31_Pos (31U)
5225 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5226 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5227
5228 /******************* Bit definition for CAN_F9R2 register *******************/
5229 #define CAN_F9R2_FB0_Pos (0U)
5230 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5231 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5232 #define CAN_F9R2_FB1_Pos (1U)
5233 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5234 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5235 #define CAN_F9R2_FB2_Pos (2U)
5236 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5237 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5238 #define CAN_F9R2_FB3_Pos (3U)
5239 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5240 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5241 #define CAN_F9R2_FB4_Pos (4U)
5242 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5243 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5244 #define CAN_F9R2_FB5_Pos (5U)
5245 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5246 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5247 #define CAN_F9R2_FB6_Pos (6U)
5248 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5249 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5250 #define CAN_F9R2_FB7_Pos (7U)
5251 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5252 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5253 #define CAN_F9R2_FB8_Pos (8U)
5254 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5255 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5256 #define CAN_F9R2_FB9_Pos (9U)
5257 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5258 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5259 #define CAN_F9R2_FB10_Pos (10U)
5260 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5261 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5262 #define CAN_F9R2_FB11_Pos (11U)
5263 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5264 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5265 #define CAN_F9R2_FB12_Pos (12U)
5266 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5267 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5268 #define CAN_F9R2_FB13_Pos (13U)
5269 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5270 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5271 #define CAN_F9R2_FB14_Pos (14U)
5272 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5273 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5274 #define CAN_F9R2_FB15_Pos (15U)
5275 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5276 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5277 #define CAN_F9R2_FB16_Pos (16U)
5278 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5279 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5280 #define CAN_F9R2_FB17_Pos (17U)
5281 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5282 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5283 #define CAN_F9R2_FB18_Pos (18U)
5284 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5285 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5286 #define CAN_F9R2_FB19_Pos (19U)
5287 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5288 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5289 #define CAN_F9R2_FB20_Pos (20U)
5290 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5291 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5292 #define CAN_F9R2_FB21_Pos (21U)
5293 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5294 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5295 #define CAN_F9R2_FB22_Pos (22U)
5296 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5297 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5298 #define CAN_F9R2_FB23_Pos (23U)
5299 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5300 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5301 #define CAN_F9R2_FB24_Pos (24U)
5302 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5303 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5304 #define CAN_F9R2_FB25_Pos (25U)
5305 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5306 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5307 #define CAN_F9R2_FB26_Pos (26U)
5308 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5309 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5310 #define CAN_F9R2_FB27_Pos (27U)
5311 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5312 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5313 #define CAN_F9R2_FB28_Pos (28U)
5314 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5315 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5316 #define CAN_F9R2_FB29_Pos (29U)
5317 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5318 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5319 #define CAN_F9R2_FB30_Pos (30U)
5320 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5321 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5322 #define CAN_F9R2_FB31_Pos (31U)
5323 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5324 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5325
5326 /******************* Bit definition for CAN_F10R2 register ******************/
5327 #define CAN_F10R2_FB0_Pos (0U)
5328 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5329 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5330 #define CAN_F10R2_FB1_Pos (1U)
5331 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5332 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5333 #define CAN_F10R2_FB2_Pos (2U)
5334 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5335 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5336 #define CAN_F10R2_FB3_Pos (3U)
5337 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5338 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5339 #define CAN_F10R2_FB4_Pos (4U)
5340 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5341 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5342 #define CAN_F10R2_FB5_Pos (5U)
5343 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5344 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5345 #define CAN_F10R2_FB6_Pos (6U)
5346 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5347 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5348 #define CAN_F10R2_FB7_Pos (7U)
5349 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5350 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5351 #define CAN_F10R2_FB8_Pos (8U)
5352 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5353 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5354 #define CAN_F10R2_FB9_Pos (9U)
5355 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5356 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5357 #define CAN_F10R2_FB10_Pos (10U)
5358 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5359 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5360 #define CAN_F10R2_FB11_Pos (11U)
5361 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5362 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5363 #define CAN_F10R2_FB12_Pos (12U)
5364 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5365 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5366 #define CAN_F10R2_FB13_Pos (13U)
5367 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5368 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5369 #define CAN_F10R2_FB14_Pos (14U)
5370 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5371 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5372 #define CAN_F10R2_FB15_Pos (15U)
5373 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5374 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5375 #define CAN_F10R2_FB16_Pos (16U)
5376 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5377 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5378 #define CAN_F10R2_FB17_Pos (17U)
5379 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5380 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5381 #define CAN_F10R2_FB18_Pos (18U)
5382 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5383 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5384 #define CAN_F10R2_FB19_Pos (19U)
5385 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5386 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5387 #define CAN_F10R2_FB20_Pos (20U)
5388 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5389 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5390 #define CAN_F10R2_FB21_Pos (21U)
5391 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5392 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5393 #define CAN_F10R2_FB22_Pos (22U)
5394 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5395 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5396 #define CAN_F10R2_FB23_Pos (23U)
5397 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5398 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5399 #define CAN_F10R2_FB24_Pos (24U)
5400 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5401 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5402 #define CAN_F10R2_FB25_Pos (25U)
5403 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5404 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5405 #define CAN_F10R2_FB26_Pos (26U)
5406 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5407 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5408 #define CAN_F10R2_FB27_Pos (27U)
5409 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5410 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5411 #define CAN_F10R2_FB28_Pos (28U)
5412 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5413 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5414 #define CAN_F10R2_FB29_Pos (29U)
5415 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5416 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5417 #define CAN_F10R2_FB30_Pos (30U)
5418 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5419 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5420 #define CAN_F10R2_FB31_Pos (31U)
5421 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5422 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5423
5424 /******************* Bit definition for CAN_F11R2 register ******************/
5425 #define CAN_F11R2_FB0_Pos (0U)
5426 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5427 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5428 #define CAN_F11R2_FB1_Pos (1U)
5429 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5430 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5431 #define CAN_F11R2_FB2_Pos (2U)
5432 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5433 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5434 #define CAN_F11R2_FB3_Pos (3U)
5435 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5436 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5437 #define CAN_F11R2_FB4_Pos (4U)
5438 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5439 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5440 #define CAN_F11R2_FB5_Pos (5U)
5441 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5442 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5443 #define CAN_F11R2_FB6_Pos (6U)
5444 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5445 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5446 #define CAN_F11R2_FB7_Pos (7U)
5447 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5448 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5449 #define CAN_F11R2_FB8_Pos (8U)
5450 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5451 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5452 #define CAN_F11R2_FB9_Pos (9U)
5453 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5454 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5455 #define CAN_F11R2_FB10_Pos (10U)
5456 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5457 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5458 #define CAN_F11R2_FB11_Pos (11U)
5459 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5460 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5461 #define CAN_F11R2_FB12_Pos (12U)
5462 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5463 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5464 #define CAN_F11R2_FB13_Pos (13U)
5465 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5466 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5467 #define CAN_F11R2_FB14_Pos (14U)
5468 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5469 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5470 #define CAN_F11R2_FB15_Pos (15U)
5471 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5472 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5473 #define CAN_F11R2_FB16_Pos (16U)
5474 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5475 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5476 #define CAN_F11R2_FB17_Pos (17U)
5477 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5478 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5479 #define CAN_F11R2_FB18_Pos (18U)
5480 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5481 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5482 #define CAN_F11R2_FB19_Pos (19U)
5483 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5484 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5485 #define CAN_F11R2_FB20_Pos (20U)
5486 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5487 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5488 #define CAN_F11R2_FB21_Pos (21U)
5489 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5490 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5491 #define CAN_F11R2_FB22_Pos (22U)
5492 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5493 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5494 #define CAN_F11R2_FB23_Pos (23U)
5495 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5496 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5497 #define CAN_F11R2_FB24_Pos (24U)
5498 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5499 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5500 #define CAN_F11R2_FB25_Pos (25U)
5501 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5502 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5503 #define CAN_F11R2_FB26_Pos (26U)
5504 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5505 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5506 #define CAN_F11R2_FB27_Pos (27U)
5507 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5508 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5509 #define CAN_F11R2_FB28_Pos (28U)
5510 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5511 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5512 #define CAN_F11R2_FB29_Pos (29U)
5513 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5514 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5515 #define CAN_F11R2_FB30_Pos (30U)
5516 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5517 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5518 #define CAN_F11R2_FB31_Pos (31U)
5519 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5520 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5521
5522 /******************* Bit definition for CAN_F12R2 register ******************/
5523 #define CAN_F12R2_FB0_Pos (0U)
5524 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5525 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5526 #define CAN_F12R2_FB1_Pos (1U)
5527 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5528 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5529 #define CAN_F12R2_FB2_Pos (2U)
5530 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5531 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5532 #define CAN_F12R2_FB3_Pos (3U)
5533 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5534 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5535 #define CAN_F12R2_FB4_Pos (4U)
5536 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5537 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5538 #define CAN_F12R2_FB5_Pos (5U)
5539 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5540 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5541 #define CAN_F12R2_FB6_Pos (6U)
5542 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5543 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5544 #define CAN_F12R2_FB7_Pos (7U)
5545 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5546 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5547 #define CAN_F12R2_FB8_Pos (8U)
5548 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5549 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5550 #define CAN_F12R2_FB9_Pos (9U)
5551 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5552 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5553 #define CAN_F12R2_FB10_Pos (10U)
5554 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5555 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5556 #define CAN_F12R2_FB11_Pos (11U)
5557 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5558 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5559 #define CAN_F12R2_FB12_Pos (12U)
5560 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5561 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5562 #define CAN_F12R2_FB13_Pos (13U)
5563 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5564 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5565 #define CAN_F12R2_FB14_Pos (14U)
5566 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5567 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5568 #define CAN_F12R2_FB15_Pos (15U)
5569 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5570 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5571 #define CAN_F12R2_FB16_Pos (16U)
5572 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5573 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5574 #define CAN_F12R2_FB17_Pos (17U)
5575 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5576 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5577 #define CAN_F12R2_FB18_Pos (18U)
5578 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5579 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5580 #define CAN_F12R2_FB19_Pos (19U)
5581 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5582 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5583 #define CAN_F12R2_FB20_Pos (20U)
5584 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5585 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5586 #define CAN_F12R2_FB21_Pos (21U)
5587 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5588 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5589 #define CAN_F12R2_FB22_Pos (22U)
5590 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5591 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5592 #define CAN_F12R2_FB23_Pos (23U)
5593 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5594 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5595 #define CAN_F12R2_FB24_Pos (24U)
5596 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5597 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5598 #define CAN_F12R2_FB25_Pos (25U)
5599 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5600 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5601 #define CAN_F12R2_FB26_Pos (26U)
5602 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5603 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5604 #define CAN_F12R2_FB27_Pos (27U)
5605 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5606 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5607 #define CAN_F12R2_FB28_Pos (28U)
5608 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5609 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5610 #define CAN_F12R2_FB29_Pos (29U)
5611 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5612 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5613 #define CAN_F12R2_FB30_Pos (30U)
5614 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5615 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5616 #define CAN_F12R2_FB31_Pos (31U)
5617 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5618 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5619
5620 /******************* Bit definition for CAN_F13R2 register ******************/
5621 #define CAN_F13R2_FB0_Pos (0U)
5622 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5623 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5624 #define CAN_F13R2_FB1_Pos (1U)
5625 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5626 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5627 #define CAN_F13R2_FB2_Pos (2U)
5628 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5629 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5630 #define CAN_F13R2_FB3_Pos (3U)
5631 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5632 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5633 #define CAN_F13R2_FB4_Pos (4U)
5634 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5635 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5636 #define CAN_F13R2_FB5_Pos (5U)
5637 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5638 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5639 #define CAN_F13R2_FB6_Pos (6U)
5640 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5641 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5642 #define CAN_F13R2_FB7_Pos (7U)
5643 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5644 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5645 #define CAN_F13R2_FB8_Pos (8U)
5646 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5647 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5648 #define CAN_F13R2_FB9_Pos (9U)
5649 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5650 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5651 #define CAN_F13R2_FB10_Pos (10U)
5652 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5653 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5654 #define CAN_F13R2_FB11_Pos (11U)
5655 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5656 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5657 #define CAN_F13R2_FB12_Pos (12U)
5658 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5659 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5660 #define CAN_F13R2_FB13_Pos (13U)
5661 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5662 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5663 #define CAN_F13R2_FB14_Pos (14U)
5664 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5665 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5666 #define CAN_F13R2_FB15_Pos (15U)
5667 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5668 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5669 #define CAN_F13R2_FB16_Pos (16U)
5670 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5671 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5672 #define CAN_F13R2_FB17_Pos (17U)
5673 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5674 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5675 #define CAN_F13R2_FB18_Pos (18U)
5676 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5677 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5678 #define CAN_F13R2_FB19_Pos (19U)
5679 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5680 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5681 #define CAN_F13R2_FB20_Pos (20U)
5682 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5683 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5684 #define CAN_F13R2_FB21_Pos (21U)
5685 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5686 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5687 #define CAN_F13R2_FB22_Pos (22U)
5688 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5689 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5690 #define CAN_F13R2_FB23_Pos (23U)
5691 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5692 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5693 #define CAN_F13R2_FB24_Pos (24U)
5694 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5695 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5696 #define CAN_F13R2_FB25_Pos (25U)
5697 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5698 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5699 #define CAN_F13R2_FB26_Pos (26U)
5700 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5701 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5702 #define CAN_F13R2_FB27_Pos (27U)
5703 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5704 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5705 #define CAN_F13R2_FB28_Pos (28U)
5706 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5707 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5708 #define CAN_F13R2_FB29_Pos (29U)
5709 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5710 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5711 #define CAN_F13R2_FB30_Pos (30U)
5712 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5713 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5714 #define CAN_F13R2_FB31_Pos (31U)
5715 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5716 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5717
5718 /******************************************************************************/
5719 /* */
5720 /* CRC calculation unit */
5721 /* */
5722 /******************************************************************************/
5723 /******************* Bit definition for CRC_DR register *********************/
5724 #define CRC_DR_DR_Pos (0U)
5725 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5726 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5727
5728 /******************* Bit definition for CRC_IDR register ********************/
5729 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
5730
5731 /******************** Bit definition for CRC_CR register ********************/
5732 #define CRC_CR_RESET_Pos (0U)
5733 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5734 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5735 #define CRC_CR_POLYSIZE_Pos (3U)
5736 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5737 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5738 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5739 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5740 #define CRC_CR_REV_IN_Pos (5U)
5741 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5742 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5743 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5744 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5745 #define CRC_CR_REV_OUT_Pos (7U)
5746 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5747 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5748
5749 /******************* Bit definition for CRC_INIT register *******************/
5750 #define CRC_INIT_INIT_Pos (0U)
5751 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5752 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5753
5754 /******************* Bit definition for CRC_POL register ********************/
5755 #define CRC_POL_POL_Pos (0U)
5756 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5757 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5758
5759 /******************************************************************************/
5760 /* */
5761 /* CRS Clock Recovery System */
5762 /******************************************************************************/
5763
5764 /******************* Bit definition for CRS_CR register *********************/
5765 #define CRS_CR_SYNCOKIE_Pos (0U)
5766 #define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
5767 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
5768 #define CRS_CR_SYNCWARNIE_Pos (1U)
5769 #define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
5770 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
5771 #define CRS_CR_ERRIE_Pos (2U)
5772 #define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
5773 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
5774 #define CRS_CR_ESYNCIE_Pos (3U)
5775 #define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
5776 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
5777 #define CRS_CR_CEN_Pos (5U)
5778 #define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
5779 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
5780 #define CRS_CR_AUTOTRIMEN_Pos (6U)
5781 #define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
5782 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
5783 #define CRS_CR_SWSYNC_Pos (7U)
5784 #define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
5785 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
5786 #define CRS_CR_TRIM_Pos (8U)
5787 #define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5788 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
5789
5790 /******************* Bit definition for CRS_CFGR register *********************/
5791 #define CRS_CFGR_RELOAD_Pos (0U)
5792 #define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
5793 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
5794 #define CRS_CFGR_FELIM_Pos (16U)
5795 #define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
5796 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
5797
5798 #define CRS_CFGR_SYNCDIV_Pos (24U)
5799 #define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
5800 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
5801 #define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
5802 #define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
5803 #define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
5804
5805 #define CRS_CFGR_SYNCSRC_Pos (28U)
5806 #define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
5807 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
5808 #define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
5809 #define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
5810
5811 #define CRS_CFGR_SYNCPOL_Pos (31U)
5812 #define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
5813 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
5814
5815 /******************* Bit definition for CRS_ISR register *********************/
5816 #define CRS_ISR_SYNCOKF_Pos (0U)
5817 #define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
5818 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
5819 #define CRS_ISR_SYNCWARNF_Pos (1U)
5820 #define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
5821 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
5822 #define CRS_ISR_ERRF_Pos (2U)
5823 #define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
5824 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
5825 #define CRS_ISR_ESYNCF_Pos (3U)
5826 #define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
5827 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
5828 #define CRS_ISR_SYNCERR_Pos (8U)
5829 #define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
5830 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
5831 #define CRS_ISR_SYNCMISS_Pos (9U)
5832 #define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
5833 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
5834 #define CRS_ISR_TRIMOVF_Pos (10U)
5835 #define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
5836 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
5837 #define CRS_ISR_FEDIR_Pos (15U)
5838 #define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
5839 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
5840 #define CRS_ISR_FECAP_Pos (16U)
5841 #define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
5842 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
5843
5844 /******************* Bit definition for CRS_ICR register *********************/
5845 #define CRS_ICR_SYNCOKC_Pos (0U)
5846 #define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
5847 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
5848 #define CRS_ICR_SYNCWARNC_Pos (1U)
5849 #define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
5850 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
5851 #define CRS_ICR_ERRC_Pos (2U)
5852 #define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
5853 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
5854 #define CRS_ICR_ESYNCC_Pos (3U)
5855 #define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
5856 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
5857
5858 /******************************************************************************/
5859 /* */
5860 /* Digital to Analog Converter */
5861 /* */
5862 /******************************************************************************/
5863 /*
5864 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
5865 */
5866 /* Note: No specific macro feature on this device */
5867
5868 /******************** Bit definition for DAC_CR register ********************/
5869 #define DAC_CR_EN1_Pos (0U)
5870 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5871 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5872 #define DAC_CR_TEN1_Pos (2U)
5873 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5874 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5875
5876 #define DAC_CR_TSEL1_Pos (3U)
5877 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5878 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5879 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5880 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5881 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5882
5883 #define DAC_CR_WAVE1_Pos (6U)
5884 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5885 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5886 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5887 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5888
5889 #define DAC_CR_MAMP1_Pos (8U)
5890 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5891 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5892 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5893 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5894 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5895 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5896
5897 #define DAC_CR_DMAEN1_Pos (12U)
5898 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5899 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5900 #define DAC_CR_DMAUDRIE1_Pos (13U)
5901 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5902 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
5903 #define DAC_CR_CEN1_Pos (14U)
5904 #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
5905 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
5906
5907 #define DAC_CR_EN2_Pos (16U)
5908 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5909 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5910 #define DAC_CR_TEN2_Pos (18U)
5911 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5912 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5913
5914 #define DAC_CR_TSEL2_Pos (19U)
5915 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5916 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5917 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5918 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5919 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5920
5921 #define DAC_CR_WAVE2_Pos (22U)
5922 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5923 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5924 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5925 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5926
5927 #define DAC_CR_MAMP2_Pos (24U)
5928 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5929 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5930 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5931 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5932 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5933 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5934
5935 #define DAC_CR_DMAEN2_Pos (28U)
5936 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5937 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5938 #define DAC_CR_DMAUDRIE2_Pos (29U)
5939 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5940 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
5941 #define DAC_CR_CEN2_Pos (30U)
5942 #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
5943 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
5944
5945 /***************** Bit definition for DAC_SWTRIGR register ******************/
5946 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5947 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5948 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5949 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5950 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5951 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5952
5953 /***************** Bit definition for DAC_DHR12R1 register ******************/
5954 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5955 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5956 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5957
5958 /***************** Bit definition for DAC_DHR12L1 register ******************/
5959 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5960 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5961 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5962
5963 /****************** Bit definition for DAC_DHR8R1 register ******************/
5964 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5965 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5966 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5967
5968 /***************** Bit definition for DAC_DHR12R2 register ******************/
5969 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5970 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5971 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5972
5973 /***************** Bit definition for DAC_DHR12L2 register ******************/
5974 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5975 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5976 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5977
5978 /****************** Bit definition for DAC_DHR8R2 register ******************/
5979 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5980 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5981 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5982
5983 /***************** Bit definition for DAC_DHR12RD register ******************/
5984 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5985 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5986 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5987 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5988 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5989 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5990
5991 /***************** Bit definition for DAC_DHR12LD register ******************/
5992 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5993 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5994 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5995 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5996 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5997 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5998
5999 /****************** Bit definition for DAC_DHR8RD register ******************/
6000 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
6001 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
6002 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6003 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
6004 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
6005 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6006
6007 /******************* Bit definition for DAC_DOR1 register *******************/
6008 #define DAC_DOR1_DACC1DOR_Pos (0U)
6009 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
6010 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
6011
6012 /******************* Bit definition for DAC_DOR2 register *******************/
6013 #define DAC_DOR2_DACC2DOR_Pos (0U)
6014 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
6015 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
6016
6017 /******************** Bit definition for DAC_SR register ********************/
6018 #define DAC_SR_DMAUDR1_Pos (13U)
6019 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
6020 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
6021 #define DAC_SR_CAL_FLAG1_Pos (14U)
6022 #define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
6023 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
6024 #define DAC_SR_BWST1_Pos (15U)
6025 #define DAC_SR_BWST1_Msk (0x4001U << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
6026 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
6027
6028 #define DAC_SR_DMAUDR2_Pos (29U)
6029 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
6030 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
6031 #define DAC_SR_CAL_FLAG2_Pos (30U)
6032 #define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
6033 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
6034 #define DAC_SR_BWST2_Pos (31U)
6035 #define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
6036 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
6037
6038 /******************* Bit definition for DAC_CCR register ********************/
6039 #define DAC_CCR_OTRIM1_Pos (0U)
6040 #define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
6041 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
6042 #define DAC_CCR_OTRIM2_Pos (16U)
6043 #define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
6044 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
6045
6046 /******************* Bit definition for DAC_MCR register *******************/
6047 #define DAC_MCR_MODE1_Pos (0U)
6048 #define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
6049 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
6050 #define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
6051 #define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
6052 #define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
6053
6054 #define DAC_MCR_MODE2_Pos (16U)
6055 #define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
6056 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
6057 #define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
6058 #define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
6059 #define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
6060
6061 /****************** Bit definition for DAC_SHSR1 register ******************/
6062 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
6063 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
6064 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
6065
6066 /****************** Bit definition for DAC_SHSR2 register ******************/
6067 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
6068 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
6069 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
6070
6071 /****************** Bit definition for DAC_SHHR register ******************/
6072 #define DAC_SHHR_THOLD1_Pos (0U)
6073 #define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
6074 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
6075 #define DAC_SHHR_THOLD2_Pos (16U)
6076 #define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
6077 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
6078
6079 /****************** Bit definition for DAC_SHRR register ******************/
6080 #define DAC_SHRR_TREFRESH1_Pos (0U)
6081 #define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
6082 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
6083 #define DAC_SHRR_TREFRESH2_Pos (16U)
6084 #define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
6085 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
6086
6087 /******************************************************************************/
6088 /* */
6089 /* Digital Filter for Sigma Delta Modulators */
6090 /* */
6091 /******************************************************************************/
6092
6093 /**************** DFSDM channel configuration registers ********************/
6094
6095 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6096 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6097 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6098 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6099 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6100 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6101 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6102 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6103 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6104 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6105 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6106 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6107 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6108 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6109 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6110 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6111 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6112 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6113 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6114 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6115 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6116 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6117 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6118 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
6119 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6120 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6121 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6122 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6123 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6124 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6125 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6126 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6127 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6128 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6129 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6130 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6131 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6132 #define DFSDM_CHCFGR1_SITP_Pos (0U)
6133 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6134 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6135 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6136 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6137
6138 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6139 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6140 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6141 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6142 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6143 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6144 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6145
6146 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
6147 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6148 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6149 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6150 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6151 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6152 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6153 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6154 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6155 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6156 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6157 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6158 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6159 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6160 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6161
6162 /**************** Bit definition for DFSDM_CHWDATR register *******************/
6163 #define DFSDM_CHWDATR_WDATA_Pos (0U)
6164 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6165 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6166
6167 /**************** Bit definition for DFSDM_CHDATINR register *****************/
6168 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
6169 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6170 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6171 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
6172 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6173 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6174
6175 /************************ DFSDM module registers ****************************/
6176
6177 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
6178 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6179 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6180 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6181 #define DFSDM_FLTCR1_FAST_Pos (29U)
6182 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6183 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6184 #define DFSDM_FLTCR1_RCH_Pos (24U)
6185 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6186 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6187 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6188 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6189 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6190 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
6191 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6192 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6193 #define DFSDM_FLTCR1_RCONT_Pos (18U)
6194 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6195 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6196 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6197 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6198 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6199 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6200 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6201 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6202 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6203 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6204 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6205 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
6206 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
6207 #define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6208 #define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6209 #define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6210 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6211 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6212 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6213 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
6214 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6215 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6216 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
6217 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6218 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6219 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6220 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6221 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6222 #define DFSDM_FLTCR1_DFEN_Pos (0U)
6223 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6224 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6225
6226 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
6227 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
6228 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6229 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6230 #define DFSDM_FLTCR2_EXCH_Pos (8U)
6231 #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6232 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6233 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
6234 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6235 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6236 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
6237 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6238 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6239 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
6240 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6241 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6242 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6243 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6244 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6245 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6246 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6247 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6248 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
6249 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6250 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6251 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6252 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6253 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6254
6255 /***************** Bit definition for DFSDM_FLTISR register *******************/
6256 #define DFSDM_FLTISR_SCDF_Pos (24U)
6257 #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6258 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6259 #define DFSDM_FLTISR_CKABF_Pos (16U)
6260 #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6261 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6262 #define DFSDM_FLTISR_RCIP_Pos (14U)
6263 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6264 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6265 #define DFSDM_FLTISR_JCIP_Pos (13U)
6266 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6267 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6268 #define DFSDM_FLTISR_AWDF_Pos (4U)
6269 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6270 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6271 #define DFSDM_FLTISR_ROVRF_Pos (3U)
6272 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6273 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6274 #define DFSDM_FLTISR_JOVRF_Pos (2U)
6275 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6276 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6277 #define DFSDM_FLTISR_REOCF_Pos (1U)
6278 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6279 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6280 #define DFSDM_FLTISR_JEOCF_Pos (0U)
6281 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6282 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6283
6284 /***************** Bit definition for DFSDM_FLTICR register *******************/
6285 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
6286 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
6287 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6288 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6289 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6290 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6291 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6292 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6293 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6294 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6295 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6296 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6297
6298 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
6299 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6300 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6301 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6302
6303 /***************** Bit definition for DFSDM_FLTFCR register *******************/
6304 #define DFSDM_FLTFCR_FORD_Pos (29U)
6305 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6306 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6307 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6308 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6309 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6310 #define DFSDM_FLTFCR_FOSR_Pos (16U)
6311 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6312 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6313 #define DFSDM_FLTFCR_IOSR_Pos (0U)
6314 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6315 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6316
6317 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
6318 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6319 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6320 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6321 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6322 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6323 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6324
6325 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
6326 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6327 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6328 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6329 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6330 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6331 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6332 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6333 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6334 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6335
6336 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
6337 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6338 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6339 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6340 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6341 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6342 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6343
6344 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
6345 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6346 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6347 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
6348 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6349 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6350 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6351
6352 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
6353 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6354 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6355 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6356 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6357 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6358 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6359
6360 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
6361 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6362 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6363 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6364 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6365 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6366 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6367
6368 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
6369 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6370 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6371 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6372 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6373 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6374 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6375
6376 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
6377 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6378 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6379 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6380 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6381 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6382 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6383
6384 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
6385 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6386 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6387 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6388
6389 /******************************************************************************/
6390 /* */
6391 /* DMA Controller (DMA) */
6392 /* */
6393 /******************************************************************************/
6394
6395 /******************* Bit definition for DMA_ISR register ********************/
6396 #define DMA_ISR_GIF1_Pos (0U)
6397 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
6398 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6399 #define DMA_ISR_TCIF1_Pos (1U)
6400 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
6401 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6402 #define DMA_ISR_HTIF1_Pos (2U)
6403 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
6404 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6405 #define DMA_ISR_TEIF1_Pos (3U)
6406 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
6407 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6408 #define DMA_ISR_GIF2_Pos (4U)
6409 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
6410 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6411 #define DMA_ISR_TCIF2_Pos (5U)
6412 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
6413 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6414 #define DMA_ISR_HTIF2_Pos (6U)
6415 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
6416 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6417 #define DMA_ISR_TEIF2_Pos (7U)
6418 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
6419 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6420 #define DMA_ISR_GIF3_Pos (8U)
6421 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
6422 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6423 #define DMA_ISR_TCIF3_Pos (9U)
6424 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
6425 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6426 #define DMA_ISR_HTIF3_Pos (10U)
6427 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
6428 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6429 #define DMA_ISR_TEIF3_Pos (11U)
6430 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
6431 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6432 #define DMA_ISR_GIF4_Pos (12U)
6433 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
6434 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6435 #define DMA_ISR_TCIF4_Pos (13U)
6436 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
6437 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6438 #define DMA_ISR_HTIF4_Pos (14U)
6439 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
6440 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6441 #define DMA_ISR_TEIF4_Pos (15U)
6442 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
6443 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6444 #define DMA_ISR_GIF5_Pos (16U)
6445 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
6446 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6447 #define DMA_ISR_TCIF5_Pos (17U)
6448 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
6449 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6450 #define DMA_ISR_HTIF5_Pos (18U)
6451 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
6452 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6453 #define DMA_ISR_TEIF5_Pos (19U)
6454 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
6455 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6456 #define DMA_ISR_GIF6_Pos (20U)
6457 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
6458 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6459 #define DMA_ISR_TCIF6_Pos (21U)
6460 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
6461 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6462 #define DMA_ISR_HTIF6_Pos (22U)
6463 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
6464 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6465 #define DMA_ISR_TEIF6_Pos (23U)
6466 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
6467 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6468 #define DMA_ISR_GIF7_Pos (24U)
6469 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
6470 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6471 #define DMA_ISR_TCIF7_Pos (25U)
6472 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
6473 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6474 #define DMA_ISR_HTIF7_Pos (26U)
6475 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
6476 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6477 #define DMA_ISR_TEIF7_Pos (27U)
6478 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
6479 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6480
6481 /******************* Bit definition for DMA_IFCR register *******************/
6482 #define DMA_IFCR_CGIF1_Pos (0U)
6483 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
6484 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
6485 #define DMA_IFCR_CTCIF1_Pos (1U)
6486 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
6487 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6488 #define DMA_IFCR_CHTIF1_Pos (2U)
6489 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
6490 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6491 #define DMA_IFCR_CTEIF1_Pos (3U)
6492 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
6493 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6494 #define DMA_IFCR_CGIF2_Pos (4U)
6495 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
6496 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6497 #define DMA_IFCR_CTCIF2_Pos (5U)
6498 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
6499 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6500 #define DMA_IFCR_CHTIF2_Pos (6U)
6501 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
6502 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6503 #define DMA_IFCR_CTEIF2_Pos (7U)
6504 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
6505 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6506 #define DMA_IFCR_CGIF3_Pos (8U)
6507 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
6508 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6509 #define DMA_IFCR_CTCIF3_Pos (9U)
6510 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
6511 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6512 #define DMA_IFCR_CHTIF3_Pos (10U)
6513 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
6514 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6515 #define DMA_IFCR_CTEIF3_Pos (11U)
6516 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
6517 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6518 #define DMA_IFCR_CGIF4_Pos (12U)
6519 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
6520 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6521 #define DMA_IFCR_CTCIF4_Pos (13U)
6522 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
6523 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6524 #define DMA_IFCR_CHTIF4_Pos (14U)
6525 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
6526 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6527 #define DMA_IFCR_CTEIF4_Pos (15U)
6528 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
6529 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6530 #define DMA_IFCR_CGIF5_Pos (16U)
6531 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
6532 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6533 #define DMA_IFCR_CTCIF5_Pos (17U)
6534 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
6535 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6536 #define DMA_IFCR_CHTIF5_Pos (18U)
6537 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
6538 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6539 #define DMA_IFCR_CTEIF5_Pos (19U)
6540 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
6541 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6542 #define DMA_IFCR_CGIF6_Pos (20U)
6543 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
6544 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6545 #define DMA_IFCR_CTCIF6_Pos (21U)
6546 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
6547 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6548 #define DMA_IFCR_CHTIF6_Pos (22U)
6549 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
6550 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6551 #define DMA_IFCR_CTEIF6_Pos (23U)
6552 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
6553 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6554 #define DMA_IFCR_CGIF7_Pos (24U)
6555 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
6556 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6557 #define DMA_IFCR_CTCIF7_Pos (25U)
6558 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
6559 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6560 #define DMA_IFCR_CHTIF7_Pos (26U)
6561 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
6562 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6563 #define DMA_IFCR_CTEIF7_Pos (27U)
6564 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
6565 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6566
6567 /******************* Bit definition for DMA_CCR register ********************/
6568 #define DMA_CCR_EN_Pos (0U)
6569 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
6570 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
6571 #define DMA_CCR_TCIE_Pos (1U)
6572 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6573 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6574 #define DMA_CCR_HTIE_Pos (2U)
6575 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6576 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6577 #define DMA_CCR_TEIE_Pos (3U)
6578 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6579 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6580 #define DMA_CCR_DIR_Pos (4U)
6581 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
6582 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
6583 #define DMA_CCR_CIRC_Pos (5U)
6584 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6585 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
6586 #define DMA_CCR_PINC_Pos (6U)
6587 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
6588 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6589 #define DMA_CCR_MINC_Pos (7U)
6590 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
6591 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
6592
6593 #define DMA_CCR_PSIZE_Pos (8U)
6594 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6595 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6596 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6597 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6598
6599 #define DMA_CCR_MSIZE_Pos (10U)
6600 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6601 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6602 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6603 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6604
6605 #define DMA_CCR_PL_Pos (12U)
6606 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
6607 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6608 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
6609 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
6610
6611 #define DMA_CCR_MEM2MEM_Pos (14U)
6612 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6613 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6614
6615 /****************** Bit definition for DMA_CNDTR register *******************/
6616 #define DMA_CNDTR_NDT_Pos (0U)
6617 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6618 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6619
6620 /****************** Bit definition for DMA_CPAR register ********************/
6621 #define DMA_CPAR_PA_Pos (0U)
6622 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6623 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
6624
6625 /****************** Bit definition for DMA_CMAR register ********************/
6626 #define DMA_CMAR_MA_Pos (0U)
6627 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
6628 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
6629
6630
6631 /******************* Bit definition for DMA_CSELR register *******************/
6632 #define DMA_CSELR_C1S_Pos (0U)
6633 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
6634 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
6635 #define DMA_CSELR_C2S_Pos (4U)
6636 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
6637 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
6638 #define DMA_CSELR_C3S_Pos (8U)
6639 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
6640 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
6641 #define DMA_CSELR_C4S_Pos (12U)
6642 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
6643 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
6644 #define DMA_CSELR_C5S_Pos (16U)
6645 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
6646 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
6647 #define DMA_CSELR_C6S_Pos (20U)
6648 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
6649 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
6650 #define DMA_CSELR_C7S_Pos (24U)
6651 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
6652 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
6653
6654 /******************************************************************************/
6655 /* */
6656 /* External Interrupt/Event Controller */
6657 /* */
6658 /******************************************************************************/
6659 /******************* Bit definition for EXTI_IMR1 register ******************/
6660 #define EXTI_IMR1_IM0_Pos (0U)
6661 #define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
6662 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
6663 #define EXTI_IMR1_IM1_Pos (1U)
6664 #define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
6665 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
6666 #define EXTI_IMR1_IM2_Pos (2U)
6667 #define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
6668 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
6669 #define EXTI_IMR1_IM3_Pos (3U)
6670 #define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
6671 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
6672 #define EXTI_IMR1_IM4_Pos (4U)
6673 #define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
6674 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
6675 #define EXTI_IMR1_IM5_Pos (5U)
6676 #define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
6677 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
6678 #define EXTI_IMR1_IM6_Pos (6U)
6679 #define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
6680 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
6681 #define EXTI_IMR1_IM7_Pos (7U)
6682 #define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
6683 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
6684 #define EXTI_IMR1_IM8_Pos (8U)
6685 #define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
6686 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
6687 #define EXTI_IMR1_IM9_Pos (9U)
6688 #define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
6689 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
6690 #define EXTI_IMR1_IM10_Pos (10U)
6691 #define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
6692 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
6693 #define EXTI_IMR1_IM11_Pos (11U)
6694 #define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
6695 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
6696 #define EXTI_IMR1_IM12_Pos (12U)
6697 #define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
6698 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
6699 #define EXTI_IMR1_IM13_Pos (13U)
6700 #define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
6701 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
6702 #define EXTI_IMR1_IM14_Pos (14U)
6703 #define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
6704 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
6705 #define EXTI_IMR1_IM15_Pos (15U)
6706 #define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
6707 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
6708 #define EXTI_IMR1_IM16_Pos (16U)
6709 #define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
6710 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
6711 #define EXTI_IMR1_IM17_Pos (17U)
6712 #define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
6713 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
6714 #define EXTI_IMR1_IM18_Pos (18U)
6715 #define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
6716 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
6717 #define EXTI_IMR1_IM19_Pos (19U)
6718 #define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
6719 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
6720 #define EXTI_IMR1_IM20_Pos (20U)
6721 #define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
6722 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
6723 #define EXTI_IMR1_IM21_Pos (21U)
6724 #define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
6725 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
6726 #define EXTI_IMR1_IM22_Pos (22U)
6727 #define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
6728 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
6729 #define EXTI_IMR1_IM23_Pos (23U)
6730 #define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
6731 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
6732 #define EXTI_IMR1_IM24_Pos (24U)
6733 #define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
6734 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
6735 #define EXTI_IMR1_IM25_Pos (25U)
6736 #define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
6737 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
6738 #define EXTI_IMR1_IM26_Pos (26U)
6739 #define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
6740 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
6741 #define EXTI_IMR1_IM27_Pos (27U)
6742 #define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
6743 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
6744 #define EXTI_IMR1_IM28_Pos (28U)
6745 #define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
6746 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
6747 #define EXTI_IMR1_IM29_Pos (29U)
6748 #define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
6749 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
6750 #define EXTI_IMR1_IM31_Pos (31U)
6751 #define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
6752 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
6753 #define EXTI_IMR1_IM_Pos (0U)
6754 #define EXTI_IMR1_IM_Msk (0xBFFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0xBFFFFFFF */
6755 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
6756
6757 /******************* Bit definition for EXTI_EMR1 register ******************/
6758 #define EXTI_EMR1_EM0_Pos (0U)
6759 #define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
6760 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
6761 #define EXTI_EMR1_EM1_Pos (1U)
6762 #define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
6763 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
6764 #define EXTI_EMR1_EM2_Pos (2U)
6765 #define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
6766 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
6767 #define EXTI_EMR1_EM3_Pos (3U)
6768 #define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
6769 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
6770 #define EXTI_EMR1_EM4_Pos (4U)
6771 #define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
6772 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
6773 #define EXTI_EMR1_EM5_Pos (5U)
6774 #define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
6775 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
6776 #define EXTI_EMR1_EM6_Pos (6U)
6777 #define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
6778 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
6779 #define EXTI_EMR1_EM7_Pos (7U)
6780 #define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
6781 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
6782 #define EXTI_EMR1_EM8_Pos (8U)
6783 #define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
6784 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
6785 #define EXTI_EMR1_EM9_Pos (9U)
6786 #define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
6787 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
6788 #define EXTI_EMR1_EM10_Pos (10U)
6789 #define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
6790 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
6791 #define EXTI_EMR1_EM11_Pos (11U)
6792 #define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
6793 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
6794 #define EXTI_EMR1_EM12_Pos (12U)
6795 #define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
6796 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
6797 #define EXTI_EMR1_EM13_Pos (13U)
6798 #define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
6799 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
6800 #define EXTI_EMR1_EM14_Pos (14U)
6801 #define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
6802 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
6803 #define EXTI_EMR1_EM15_Pos (15U)
6804 #define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
6805 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
6806 #define EXTI_EMR1_EM16_Pos (16U)
6807 #define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
6808 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
6809 #define EXTI_EMR1_EM17_Pos (17U)
6810 #define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
6811 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
6812 #define EXTI_EMR1_EM18_Pos (18U)
6813 #define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
6814 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
6815 #define EXTI_EMR1_EM19_Pos (19U)
6816 #define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
6817 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
6818 #define EXTI_EMR1_EM20_Pos (20U)
6819 #define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
6820 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
6821 #define EXTI_EMR1_EM21_Pos (21U)
6822 #define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
6823 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
6824 #define EXTI_EMR1_EM22_Pos (22U)
6825 #define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
6826 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
6827 #define EXTI_EMR1_EM23_Pos (23U)
6828 #define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
6829 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
6830 #define EXTI_EMR1_EM24_Pos (24U)
6831 #define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
6832 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
6833 #define EXTI_EMR1_EM25_Pos (25U)
6834 #define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
6835 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
6836 #define EXTI_EMR1_EM26_Pos (26U)
6837 #define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
6838 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
6839 #define EXTI_EMR1_EM27_Pos (27U)
6840 #define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
6841 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
6842 #define EXTI_EMR1_EM28_Pos (28U)
6843 #define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
6844 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
6845 #define EXTI_EMR1_EM29_Pos (29U)
6846 #define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
6847 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
6848 #define EXTI_EMR1_EM31_Pos (31U)
6849 #define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
6850 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
6851
6852 /****************** Bit definition for EXTI_RTSR1 register ******************/
6853 #define EXTI_RTSR1_RT0_Pos (0U)
6854 #define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
6855 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
6856 #define EXTI_RTSR1_RT1_Pos (1U)
6857 #define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
6858 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
6859 #define EXTI_RTSR1_RT2_Pos (2U)
6860 #define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
6861 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
6862 #define EXTI_RTSR1_RT3_Pos (3U)
6863 #define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
6864 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
6865 #define EXTI_RTSR1_RT4_Pos (4U)
6866 #define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
6867 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
6868 #define EXTI_RTSR1_RT5_Pos (5U)
6869 #define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
6870 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
6871 #define EXTI_RTSR1_RT6_Pos (6U)
6872 #define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
6873 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
6874 #define EXTI_RTSR1_RT7_Pos (7U)
6875 #define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
6876 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
6877 #define EXTI_RTSR1_RT8_Pos (8U)
6878 #define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
6879 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
6880 #define EXTI_RTSR1_RT9_Pos (9U)
6881 #define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
6882 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
6883 #define EXTI_RTSR1_RT10_Pos (10U)
6884 #define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
6885 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
6886 #define EXTI_RTSR1_RT11_Pos (11U)
6887 #define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
6888 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
6889 #define EXTI_RTSR1_RT12_Pos (12U)
6890 #define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
6891 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
6892 #define EXTI_RTSR1_RT13_Pos (13U)
6893 #define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
6894 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
6895 #define EXTI_RTSR1_RT14_Pos (14U)
6896 #define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
6897 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
6898 #define EXTI_RTSR1_RT15_Pos (15U)
6899 #define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
6900 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
6901 #define EXTI_RTSR1_RT16_Pos (16U)
6902 #define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
6903 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
6904 #define EXTI_RTSR1_RT18_Pos (18U)
6905 #define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
6906 #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
6907 #define EXTI_RTSR1_RT19_Pos (19U)
6908 #define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
6909 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
6910 #define EXTI_RTSR1_RT20_Pos (20U)
6911 #define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
6912 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
6913 #define EXTI_RTSR1_RT21_Pos (21U)
6914 #define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
6915 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
6916 #define EXTI_RTSR1_RT22_Pos (22U)
6917 #define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
6918 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
6919
6920 /****************** Bit definition for EXTI_FTSR1 register ******************/
6921 #define EXTI_FTSR1_FT0_Pos (0U)
6922 #define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
6923 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
6924 #define EXTI_FTSR1_FT1_Pos (1U)
6925 #define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
6926 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
6927 #define EXTI_FTSR1_FT2_Pos (2U)
6928 #define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
6929 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
6930 #define EXTI_FTSR1_FT3_Pos (3U)
6931 #define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
6932 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
6933 #define EXTI_FTSR1_FT4_Pos (4U)
6934 #define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
6935 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
6936 #define EXTI_FTSR1_FT5_Pos (5U)
6937 #define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
6938 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
6939 #define EXTI_FTSR1_FT6_Pos (6U)
6940 #define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
6941 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
6942 #define EXTI_FTSR1_FT7_Pos (7U)
6943 #define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
6944 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
6945 #define EXTI_FTSR1_FT8_Pos (8U)
6946 #define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
6947 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
6948 #define EXTI_FTSR1_FT9_Pos (9U)
6949 #define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
6950 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
6951 #define EXTI_FTSR1_FT10_Pos (10U)
6952 #define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
6953 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
6954 #define EXTI_FTSR1_FT11_Pos (11U)
6955 #define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
6956 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
6957 #define EXTI_FTSR1_FT12_Pos (12U)
6958 #define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
6959 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
6960 #define EXTI_FTSR1_FT13_Pos (13U)
6961 #define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
6962 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
6963 #define EXTI_FTSR1_FT14_Pos (14U)
6964 #define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
6965 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
6966 #define EXTI_FTSR1_FT15_Pos (15U)
6967 #define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
6968 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
6969 #define EXTI_FTSR1_FT16_Pos (16U)
6970 #define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
6971 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
6972 #define EXTI_FTSR1_FT18_Pos (18U)
6973 #define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
6974 #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
6975 #define EXTI_FTSR1_FT19_Pos (19U)
6976 #define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
6977 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
6978 #define EXTI_FTSR1_FT20_Pos (20U)
6979 #define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
6980 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
6981 #define EXTI_FTSR1_FT21_Pos (21U)
6982 #define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
6983 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
6984 #define EXTI_FTSR1_FT22_Pos (22U)
6985 #define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
6986 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
6987
6988 /****************** Bit definition for EXTI_SWIER1 register *****************/
6989 #define EXTI_SWIER1_SWI0_Pos (0U)
6990 #define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
6991 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
6992 #define EXTI_SWIER1_SWI1_Pos (1U)
6993 #define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
6994 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
6995 #define EXTI_SWIER1_SWI2_Pos (2U)
6996 #define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
6997 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
6998 #define EXTI_SWIER1_SWI3_Pos (3U)
6999 #define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
7000 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
7001 #define EXTI_SWIER1_SWI4_Pos (4U)
7002 #define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
7003 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
7004 #define EXTI_SWIER1_SWI5_Pos (5U)
7005 #define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
7006 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
7007 #define EXTI_SWIER1_SWI6_Pos (6U)
7008 #define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
7009 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
7010 #define EXTI_SWIER1_SWI7_Pos (7U)
7011 #define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
7012 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
7013 #define EXTI_SWIER1_SWI8_Pos (8U)
7014 #define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
7015 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
7016 #define EXTI_SWIER1_SWI9_Pos (9U)
7017 #define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
7018 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
7019 #define EXTI_SWIER1_SWI10_Pos (10U)
7020 #define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
7021 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
7022 #define EXTI_SWIER1_SWI11_Pos (11U)
7023 #define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
7024 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
7025 #define EXTI_SWIER1_SWI12_Pos (12U)
7026 #define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
7027 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
7028 #define EXTI_SWIER1_SWI13_Pos (13U)
7029 #define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
7030 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
7031 #define EXTI_SWIER1_SWI14_Pos (14U)
7032 #define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
7033 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
7034 #define EXTI_SWIER1_SWI15_Pos (15U)
7035 #define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
7036 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
7037 #define EXTI_SWIER1_SWI16_Pos (16U)
7038 #define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
7039 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
7040 #define EXTI_SWIER1_SWI18_Pos (18U)
7041 #define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
7042 #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
7043 #define EXTI_SWIER1_SWI19_Pos (19U)
7044 #define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
7045 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
7046 #define EXTI_SWIER1_SWI20_Pos (20U)
7047 #define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
7048 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
7049 #define EXTI_SWIER1_SWI21_Pos (21U)
7050 #define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
7051 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
7052 #define EXTI_SWIER1_SWI22_Pos (22U)
7053 #define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
7054 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
7055
7056 /******************* Bit definition for EXTI_PR1 register *******************/
7057 #define EXTI_PR1_PIF0_Pos (0U)
7058 #define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
7059 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
7060 #define EXTI_PR1_PIF1_Pos (1U)
7061 #define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
7062 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
7063 #define EXTI_PR1_PIF2_Pos (2U)
7064 #define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
7065 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
7066 #define EXTI_PR1_PIF3_Pos (3U)
7067 #define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
7068 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
7069 #define EXTI_PR1_PIF4_Pos (4U)
7070 #define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
7071 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
7072 #define EXTI_PR1_PIF5_Pos (5U)
7073 #define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
7074 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
7075 #define EXTI_PR1_PIF6_Pos (6U)
7076 #define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
7077 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
7078 #define EXTI_PR1_PIF7_Pos (7U)
7079 #define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
7080 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
7081 #define EXTI_PR1_PIF8_Pos (8U)
7082 #define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
7083 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
7084 #define EXTI_PR1_PIF9_Pos (9U)
7085 #define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
7086 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
7087 #define EXTI_PR1_PIF10_Pos (10U)
7088 #define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
7089 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
7090 #define EXTI_PR1_PIF11_Pos (11U)
7091 #define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
7092 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
7093 #define EXTI_PR1_PIF12_Pos (12U)
7094 #define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
7095 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
7096 #define EXTI_PR1_PIF13_Pos (13U)
7097 #define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
7098 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
7099 #define EXTI_PR1_PIF14_Pos (14U)
7100 #define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
7101 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
7102 #define EXTI_PR1_PIF15_Pos (15U)
7103 #define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
7104 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
7105 #define EXTI_PR1_PIF16_Pos (16U)
7106 #define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
7107 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
7108 #define EXTI_PR1_PIF18_Pos (18U)
7109 #define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
7110 #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
7111 #define EXTI_PR1_PIF19_Pos (19U)
7112 #define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
7113 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
7114 #define EXTI_PR1_PIF20_Pos (20U)
7115 #define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
7116 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
7117 #define EXTI_PR1_PIF21_Pos (21U)
7118 #define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
7119 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
7120 #define EXTI_PR1_PIF22_Pos (22U)
7121 #define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
7122 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
7123
7124 /******************* Bit definition for EXTI_IMR2 register ******************/
7125 #define EXTI_IMR2_IM32_Pos (0U)
7126 #define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
7127 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
7128 #define EXTI_IMR2_IM33_Pos (1U)
7129 #define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
7130 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
7131 #define EXTI_IMR2_IM34_Pos (2U)
7132 #define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
7133 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
7134 #define EXTI_IMR2_IM35_Pos (3U)
7135 #define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
7136 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
7137 #define EXTI_IMR2_IM36_Pos (4U)
7138 #define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
7139 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
7140 #define EXTI_IMR2_IM37_Pos (5U)
7141 #define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
7142 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
7143 #define EXTI_IMR2_IM38_Pos (6U)
7144 #define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
7145 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
7146 #define EXTI_IMR2_IM39_Pos (7U)
7147 #define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
7148 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
7149 #define EXTI_IMR2_IM40_Pos (8U)
7150 #define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
7151 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
7152 #define EXTI_IMR2_IM_Pos (0U)
7153 #define EXTI_IMR2_IM_Msk (0x1FFU << EXTI_IMR2_IM_Pos) /*!< 0x000001FF */
7154 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
7155
7156 /******************* Bit definition for EXTI_EMR2 register ******************/
7157 #define EXTI_EMR2_EM32_Pos (0U)
7158 #define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
7159 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
7160 #define EXTI_EMR2_EM33_Pos (1U)
7161 #define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
7162 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
7163 #define EXTI_EMR2_EM34_Pos (2U)
7164 #define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
7165 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
7166 #define EXTI_EMR2_EM35_Pos (3U)
7167 #define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
7168 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
7169 #define EXTI_EMR2_EM36_Pos (4U)
7170 #define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
7171 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
7172 #define EXTI_EMR2_EM37_Pos (5U)
7173 #define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
7174 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
7175 #define EXTI_EMR2_EM38_Pos (6U)
7176 #define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
7177 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
7178 #define EXTI_EMR2_EM39_Pos (7U)
7179 #define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
7180 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
7181 #define EXTI_EMR2_IM40_Pos (8U)
7182 #define EXTI_EMR2_IM40_Msk (0x1U << EXTI_EMR2_IM40_Pos) /*!< 0x00000100 */
7183 #define EXTI_EMR2_IM40 EXTI_EMR2_IM40_Msk /*!< Event Mask on line 40 */
7184
7185 /****************** Bit definition for EXTI_RTSR2 register ******************/
7186 #define EXTI_RTSR2_RT35_Pos (3U)
7187 #define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
7188 #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
7189 #define EXTI_RTSR2_RT36_Pos (4U)
7190 #define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
7191 #define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
7192 #define EXTI_RTSR2_RT37_Pos (5U)
7193 #define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
7194 #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
7195 #define EXTI_RTSR2_RT38_Pos (6U)
7196 #define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
7197 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
7198
7199 /****************** Bit definition for EXTI_FTSR2 register ******************/
7200 #define EXTI_FTSR2_FT35_Pos (3U)
7201 #define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
7202 #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
7203 #define EXTI_FTSR2_FT36_Pos (4U)
7204 #define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
7205 #define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
7206 #define EXTI_FTSR2_FT37_Pos (5U)
7207 #define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
7208 #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
7209 #define EXTI_FTSR2_FT38_Pos (6U)
7210 #define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
7211 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
7212
7213 /****************** Bit definition for EXTI_SWIER2 register *****************/
7214 #define EXTI_SWIER2_SWI35_Pos (3U)
7215 #define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
7216 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
7217 #define EXTI_SWIER2_SWI36_Pos (4U)
7218 #define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
7219 #define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
7220 #define EXTI_SWIER2_SWI37_Pos (5U)
7221 #define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
7222 #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
7223 #define EXTI_SWIER2_SWI38_Pos (6U)
7224 #define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
7225 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
7226
7227 /******************* Bit definition for EXTI_PR2 register *******************/
7228 #define EXTI_PR2_PIF35_Pos (3U)
7229 #define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
7230 #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
7231 #define EXTI_PR2_PIF36_Pos (4U)
7232 #define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
7233 #define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
7234 #define EXTI_PR2_PIF37_Pos (5U)
7235 #define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
7236 #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
7237 #define EXTI_PR2_PIF38_Pos (6U)
7238 #define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
7239 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
7240
7241
7242 /******************************************************************************/
7243 /* */
7244 /* FLASH */
7245 /* */
7246 /******************************************************************************/
7247 /******************* Bits definition for FLASH_ACR register *****************/
7248 #define FLASH_ACR_LATENCY_Pos (0U)
7249 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
7250 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7251 #define FLASH_ACR_LATENCY_0WS (0x00000000U)
7252 #define FLASH_ACR_LATENCY_1WS (0x00000001U)
7253 #define FLASH_ACR_LATENCY_2WS (0x00000002U)
7254 #define FLASH_ACR_LATENCY_3WS (0x00000003U)
7255 #define FLASH_ACR_LATENCY_4WS (0x00000004U)
7256 #define FLASH_ACR_PRFTEN_Pos (8U)
7257 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
7258 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7259 #define FLASH_ACR_ICEN_Pos (9U)
7260 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
7261 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
7262 #define FLASH_ACR_DCEN_Pos (10U)
7263 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
7264 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
7265 #define FLASH_ACR_ICRST_Pos (11U)
7266 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
7267 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
7268 #define FLASH_ACR_DCRST_Pos (12U)
7269 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
7270 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
7271 #define FLASH_ACR_RUN_PD_Pos (13U)
7272 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
7273 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
7274 #define FLASH_ACR_SLEEP_PD_Pos (14U)
7275 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
7276 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
7277
7278 /******************* Bits definition for FLASH_SR register ******************/
7279 #define FLASH_SR_EOP_Pos (0U)
7280 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
7281 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
7282 #define FLASH_SR_OPERR_Pos (1U)
7283 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
7284 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7285 #define FLASH_SR_PROGERR_Pos (3U)
7286 #define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
7287 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
7288 #define FLASH_SR_WRPERR_Pos (4U)
7289 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
7290 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7291 #define FLASH_SR_PGAERR_Pos (5U)
7292 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
7293 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7294 #define FLASH_SR_SIZERR_Pos (6U)
7295 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
7296 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
7297 #define FLASH_SR_PGSERR_Pos (7U)
7298 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
7299 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
7300 #define FLASH_SR_MISERR_Pos (8U)
7301 #define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
7302 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
7303 #define FLASH_SR_FASTERR_Pos (9U)
7304 #define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
7305 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
7306 #define FLASH_SR_RDERR_Pos (14U)
7307 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
7308 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
7309 #define FLASH_SR_OPTVERR_Pos (15U)
7310 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
7311 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
7312 #define FLASH_SR_BSY_Pos (16U)
7313 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
7314 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
7315 #define FLASH_SR_PEMPTY_Pos (17U)
7316 #define FLASH_SR_PEMPTY_Msk (0x1U << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */
7317 #define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk
7318
7319 /******************* Bits definition for FLASH_CR register ******************/
7320 #define FLASH_CR_PG_Pos (0U)
7321 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
7322 #define FLASH_CR_PG FLASH_CR_PG_Msk
7323 #define FLASH_CR_PER_Pos (1U)
7324 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
7325 #define FLASH_CR_PER FLASH_CR_PER_Msk
7326 #define FLASH_CR_MER1_Pos (2U)
7327 #define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
7328 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
7329 #define FLASH_CR_PNB_Pos (3U)
7330 #define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
7331 #define FLASH_CR_PNB FLASH_CR_PNB_Msk
7332 #define FLASH_CR_STRT_Pos (16U)
7333 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
7334 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
7335 #define FLASH_CR_OPTSTRT_Pos (17U)
7336 #define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
7337 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
7338 #define FLASH_CR_FSTPG_Pos (18U)
7339 #define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
7340 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
7341 #define FLASH_CR_EOPIE_Pos (24U)
7342 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
7343 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7344 #define FLASH_CR_ERRIE_Pos (25U)
7345 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
7346 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
7347 #define FLASH_CR_RDERRIE_Pos (26U)
7348 #define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
7349 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
7350 #define FLASH_CR_OBL_LAUNCH_Pos (27U)
7351 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
7352 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
7353 #define FLASH_CR_OPTLOCK_Pos (30U)
7354 #define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
7355 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
7356 #define FLASH_CR_LOCK_Pos (31U)
7357 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
7358 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7359
7360 /******************* Bits definition for FLASH_ECCR register ***************/
7361 #define FLASH_ECCR_ADDR_ECC_Pos (0U)
7362 #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
7363 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
7364 #define FLASH_ECCR_SYSF_ECC_Pos (20U)
7365 #define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
7366 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
7367 #define FLASH_ECCR_ECCIE_Pos (24U)
7368 #define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
7369 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
7370 #define FLASH_ECCR_ECCC_Pos (30U)
7371 #define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
7372 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
7373 #define FLASH_ECCR_ECCD_Pos (31U)
7374 #define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
7375 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
7376
7377 /******************* Bits definition for FLASH_OPTR register ***************/
7378 #define FLASH_OPTR_RDP_Pos (0U)
7379 #define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
7380 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
7381 #define FLASH_OPTR_BOR_LEV_Pos (8U)
7382 #define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
7383 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
7384 #define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
7385 #define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
7386 #define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
7387 #define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
7388 #define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
7389 #define FLASH_OPTR_nRST_STOP_Pos (12U)
7390 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
7391 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
7392 #define FLASH_OPTR_nRST_STDBY_Pos (13U)
7393 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
7394 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
7395 #define FLASH_OPTR_nRST_SHDW_Pos (14U)
7396 #define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
7397 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
7398 #define FLASH_OPTR_IWDG_SW_Pos (16U)
7399 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
7400 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
7401 #define FLASH_OPTR_IWDG_STOP_Pos (17U)
7402 #define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
7403 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
7404 #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
7405 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
7406 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
7407 #define FLASH_OPTR_WWDG_SW_Pos (19U)
7408 #define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
7409 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
7410 #define FLASH_OPTR_nBOOT1_Pos (23U)
7411 #define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
7412 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
7413 #define FLASH_OPTR_SRAM2_PE_Pos (24U)
7414 #define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
7415 #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
7416 #define FLASH_OPTR_SRAM2_RST_Pos (25U)
7417 #define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
7418 #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
7419 #define FLASH_OPTR_nSWBOOT0_Pos (26U)
7420 #define FLASH_OPTR_nSWBOOT0_Msk (0x1U << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
7421 #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
7422 #define FLASH_OPTR_nBOOT0_Pos (27U)
7423 #define FLASH_OPTR_nBOOT0_Msk (0x1U << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
7424 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
7425
7426 /****************** Bits definition for FLASH_PCROP1SR register **********/
7427 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
7428 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x00007FFF */
7429 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
7430
7431 /****************** Bits definition for FLASH_PCROP1ER register ***********/
7432 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
7433 #define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x00007FFF */
7434 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
7435 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
7436 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
7437 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
7438
7439 /****************** Bits definition for FLASH_WRP1AR register ***************/
7440 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
7441 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
7442 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
7443 #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7444 #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7445 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
7446
7447 /****************** Bits definition for FLASH_WRPB1R register ***************/
7448 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
7449 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
7450 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
7451 #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7452 #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7453 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
7454
7455
7456
7457
7458 /******************************************************************************/
7459 /* */
7460 /* General Purpose IOs (GPIO) */
7461 /* */
7462 /******************************************************************************/
7463 /****************** Bits definition for GPIO_MODER register *****************/
7464 #define GPIO_MODER_MODE0_Pos (0U)
7465 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
7466 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
7467 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
7468 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
7469 #define GPIO_MODER_MODE1_Pos (2U)
7470 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
7471 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
7472 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
7473 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
7474 #define GPIO_MODER_MODE2_Pos (4U)
7475 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
7476 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
7477 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
7478 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
7479 #define GPIO_MODER_MODE3_Pos (6U)
7480 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
7481 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
7482 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
7483 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
7484 #define GPIO_MODER_MODE4_Pos (8U)
7485 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
7486 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
7487 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
7488 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
7489 #define GPIO_MODER_MODE5_Pos (10U)
7490 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
7491 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
7492 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
7493 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
7494 #define GPIO_MODER_MODE6_Pos (12U)
7495 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
7496 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
7497 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
7498 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
7499 #define GPIO_MODER_MODE7_Pos (14U)
7500 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
7501 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
7502 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
7503 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
7504 #define GPIO_MODER_MODE8_Pos (16U)
7505 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
7506 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
7507 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
7508 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
7509 #define GPIO_MODER_MODE9_Pos (18U)
7510 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
7511 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
7512 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
7513 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
7514 #define GPIO_MODER_MODE10_Pos (20U)
7515 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
7516 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
7517 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
7518 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
7519 #define GPIO_MODER_MODE11_Pos (22U)
7520 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
7521 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
7522 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
7523 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
7524 #define GPIO_MODER_MODE12_Pos (24U)
7525 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
7526 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
7527 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
7528 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
7529 #define GPIO_MODER_MODE13_Pos (26U)
7530 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
7531 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
7532 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
7533 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
7534 #define GPIO_MODER_MODE14_Pos (28U)
7535 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
7536 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
7537 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
7538 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
7539 #define GPIO_MODER_MODE15_Pos (30U)
7540 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
7541 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
7542 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
7543 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
7544
7545 /* Legacy defines */
7546 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
7547 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
7548 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
7549 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
7550 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
7551 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
7552 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
7553 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
7554 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
7555 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
7556 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
7557 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
7558 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
7559 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
7560 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
7561 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
7562 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
7563 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
7564 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
7565 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
7566 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
7567 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
7568 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
7569 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
7570 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
7571 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
7572 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
7573 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
7574 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
7575 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
7576 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
7577 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
7578 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
7579 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
7580 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
7581 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
7582 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
7583 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
7584 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
7585 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
7586 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
7587 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
7588 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
7589 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
7590 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
7591 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
7592 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
7593 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
7594
7595 /****************** Bits definition for GPIO_OTYPER register ****************/
7596 #define GPIO_OTYPER_OT0_Pos (0U)
7597 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
7598 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
7599 #define GPIO_OTYPER_OT1_Pos (1U)
7600 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
7601 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
7602 #define GPIO_OTYPER_OT2_Pos (2U)
7603 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
7604 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
7605 #define GPIO_OTYPER_OT3_Pos (3U)
7606 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
7607 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
7608 #define GPIO_OTYPER_OT4_Pos (4U)
7609 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
7610 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
7611 #define GPIO_OTYPER_OT5_Pos (5U)
7612 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
7613 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
7614 #define GPIO_OTYPER_OT6_Pos (6U)
7615 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
7616 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
7617 #define GPIO_OTYPER_OT7_Pos (7U)
7618 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
7619 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
7620 #define GPIO_OTYPER_OT8_Pos (8U)
7621 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
7622 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
7623 #define GPIO_OTYPER_OT9_Pos (9U)
7624 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
7625 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
7626 #define GPIO_OTYPER_OT10_Pos (10U)
7627 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
7628 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
7629 #define GPIO_OTYPER_OT11_Pos (11U)
7630 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
7631 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
7632 #define GPIO_OTYPER_OT12_Pos (12U)
7633 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
7634 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
7635 #define GPIO_OTYPER_OT13_Pos (13U)
7636 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
7637 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
7638 #define GPIO_OTYPER_OT14_Pos (14U)
7639 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
7640 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
7641 #define GPIO_OTYPER_OT15_Pos (15U)
7642 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
7643 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
7644
7645 /* Legacy defines */
7646 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
7647 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
7648 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
7649 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
7650 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
7651 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
7652 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
7653 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
7654 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
7655 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
7656 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
7657 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
7658 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
7659 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
7660 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
7661 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
7662
7663 /****************** Bits definition for GPIO_OSPEEDR register ***************/
7664 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
7665 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
7666 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
7667 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
7668 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
7669 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
7670 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
7671 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
7672 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
7673 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
7674 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
7675 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
7676 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
7677 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
7678 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
7679 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
7680 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
7681 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
7682 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
7683 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
7684 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
7685 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
7686 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
7687 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
7688 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
7689 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
7690 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
7691 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
7692 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
7693 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
7694 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
7695 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
7696 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
7697 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
7698 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
7699 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
7700 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
7701 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
7702 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
7703 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
7704 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
7705 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
7706 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
7707 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
7708 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
7709 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
7710 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
7711 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
7712 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
7713 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
7714 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
7715 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
7716 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
7717 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
7718 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
7719 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
7720 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
7721 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
7722 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
7723 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
7724 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
7725 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
7726 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
7727 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
7728 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
7729 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
7730 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
7731 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
7732 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
7733 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
7734 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
7735 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
7736 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
7737 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
7738 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
7739 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
7740 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
7741 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
7742 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
7743 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
7744
7745 /* Legacy defines */
7746 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
7747 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
7748 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
7749 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
7750 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
7751 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
7752 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
7753 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
7754 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
7755 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
7756 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
7757 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
7758 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
7759 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
7760 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
7761 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
7762 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
7763 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
7764 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
7765 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
7766 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
7767 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
7768 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
7769 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
7770 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
7771 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
7772 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
7773 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
7774 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
7775 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
7776 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
7777 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
7778 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
7779 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
7780 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
7781 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
7782 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
7783 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
7784 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
7785 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
7786 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
7787 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
7788 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
7789 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
7790 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
7791 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
7792 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
7793 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
7794
7795 /****************** Bits definition for GPIO_PUPDR register *****************/
7796 #define GPIO_PUPDR_PUPD0_Pos (0U)
7797 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
7798 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
7799 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
7800 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
7801 #define GPIO_PUPDR_PUPD1_Pos (2U)
7802 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
7803 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
7804 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
7805 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
7806 #define GPIO_PUPDR_PUPD2_Pos (4U)
7807 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
7808 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
7809 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
7810 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
7811 #define GPIO_PUPDR_PUPD3_Pos (6U)
7812 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
7813 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
7814 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
7815 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
7816 #define GPIO_PUPDR_PUPD4_Pos (8U)
7817 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
7818 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
7819 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
7820 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
7821 #define GPIO_PUPDR_PUPD5_Pos (10U)
7822 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
7823 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
7824 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
7825 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
7826 #define GPIO_PUPDR_PUPD6_Pos (12U)
7827 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
7828 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
7829 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
7830 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
7831 #define GPIO_PUPDR_PUPD7_Pos (14U)
7832 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
7833 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
7834 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
7835 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
7836 #define GPIO_PUPDR_PUPD8_Pos (16U)
7837 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
7838 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
7839 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
7840 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
7841 #define GPIO_PUPDR_PUPD9_Pos (18U)
7842 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
7843 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
7844 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
7845 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
7846 #define GPIO_PUPDR_PUPD10_Pos (20U)
7847 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
7848 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
7849 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
7850 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
7851 #define GPIO_PUPDR_PUPD11_Pos (22U)
7852 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
7853 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
7854 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
7855 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
7856 #define GPIO_PUPDR_PUPD12_Pos (24U)
7857 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
7858 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
7859 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
7860 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
7861 #define GPIO_PUPDR_PUPD13_Pos (26U)
7862 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
7863 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
7864 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
7865 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
7866 #define GPIO_PUPDR_PUPD14_Pos (28U)
7867 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
7868 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
7869 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
7870 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
7871 #define GPIO_PUPDR_PUPD15_Pos (30U)
7872 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
7873 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
7874 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
7875 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
7876
7877 /* Legacy defines */
7878 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
7879 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
7880 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
7881 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
7882 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
7883 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
7884 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
7885 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
7886 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
7887 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
7888 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
7889 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
7890 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
7891 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
7892 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
7893 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
7894 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
7895 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
7896 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
7897 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
7898 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
7899 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
7900 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
7901 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
7902 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
7903 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
7904 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
7905 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
7906 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
7907 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
7908 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
7909 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
7910 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
7911 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
7912 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
7913 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
7914 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
7915 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
7916 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
7917 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
7918 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
7919 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
7920 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
7921 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
7922 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
7923 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
7924 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
7925 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
7926
7927 /****************** Bits definition for GPIO_IDR register *******************/
7928 #define GPIO_IDR_ID0_Pos (0U)
7929 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
7930 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
7931 #define GPIO_IDR_ID1_Pos (1U)
7932 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
7933 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
7934 #define GPIO_IDR_ID2_Pos (2U)
7935 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
7936 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
7937 #define GPIO_IDR_ID3_Pos (3U)
7938 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
7939 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
7940 #define GPIO_IDR_ID4_Pos (4U)
7941 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
7942 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
7943 #define GPIO_IDR_ID5_Pos (5U)
7944 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
7945 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
7946 #define GPIO_IDR_ID6_Pos (6U)
7947 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
7948 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
7949 #define GPIO_IDR_ID7_Pos (7U)
7950 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
7951 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
7952 #define GPIO_IDR_ID8_Pos (8U)
7953 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
7954 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
7955 #define GPIO_IDR_ID9_Pos (9U)
7956 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
7957 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
7958 #define GPIO_IDR_ID10_Pos (10U)
7959 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
7960 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
7961 #define GPIO_IDR_ID11_Pos (11U)
7962 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
7963 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
7964 #define GPIO_IDR_ID12_Pos (12U)
7965 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
7966 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
7967 #define GPIO_IDR_ID13_Pos (13U)
7968 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
7969 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
7970 #define GPIO_IDR_ID14_Pos (14U)
7971 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
7972 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
7973 #define GPIO_IDR_ID15_Pos (15U)
7974 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
7975 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
7976
7977 /* Legacy defines */
7978 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
7979 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
7980 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
7981 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
7982 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
7983 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
7984 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
7985 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
7986 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
7987 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
7988 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
7989 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
7990 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
7991 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
7992 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
7993 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
7994
7995 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
7996 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
7997 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
7998 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
7999 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
8000 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
8001 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
8002 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
8003 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
8004 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
8005 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
8006 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
8007 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
8008 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
8009 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
8010 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
8011 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
8012
8013 /****************** Bits definition for GPIO_ODR register *******************/
8014 #define GPIO_ODR_OD0_Pos (0U)
8015 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
8016 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8017 #define GPIO_ODR_OD1_Pos (1U)
8018 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
8019 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8020 #define GPIO_ODR_OD2_Pos (2U)
8021 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
8022 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8023 #define GPIO_ODR_OD3_Pos (3U)
8024 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
8025 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8026 #define GPIO_ODR_OD4_Pos (4U)
8027 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
8028 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8029 #define GPIO_ODR_OD5_Pos (5U)
8030 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
8031 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8032 #define GPIO_ODR_OD6_Pos (6U)
8033 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
8034 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8035 #define GPIO_ODR_OD7_Pos (7U)
8036 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
8037 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8038 #define GPIO_ODR_OD8_Pos (8U)
8039 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
8040 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8041 #define GPIO_ODR_OD9_Pos (9U)
8042 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
8043 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8044 #define GPIO_ODR_OD10_Pos (10U)
8045 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
8046 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8047 #define GPIO_ODR_OD11_Pos (11U)
8048 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
8049 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8050 #define GPIO_ODR_OD12_Pos (12U)
8051 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
8052 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8053 #define GPIO_ODR_OD13_Pos (13U)
8054 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
8055 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8056 #define GPIO_ODR_OD14_Pos (14U)
8057 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
8058 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8059 #define GPIO_ODR_OD15_Pos (15U)
8060 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
8061 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8062
8063 /* Legacy defines */
8064 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8065 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8066 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8067 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8068 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8069 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8070 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8071 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8072 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8073 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8074 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8075 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8076 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8077 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8078 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8079 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8080
8081 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
8082 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
8083 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
8084 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
8085 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
8086 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
8087 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
8088 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
8089 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
8090 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
8091 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
8092 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
8093 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
8094 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
8095 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
8096 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
8097 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
8098
8099 /****************** Bits definition for GPIO_BSRR register ******************/
8100 #define GPIO_BSRR_BS0_Pos (0U)
8101 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
8102 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8103 #define GPIO_BSRR_BS1_Pos (1U)
8104 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
8105 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8106 #define GPIO_BSRR_BS2_Pos (2U)
8107 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
8108 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8109 #define GPIO_BSRR_BS3_Pos (3U)
8110 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
8111 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8112 #define GPIO_BSRR_BS4_Pos (4U)
8113 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
8114 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8115 #define GPIO_BSRR_BS5_Pos (5U)
8116 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
8117 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8118 #define GPIO_BSRR_BS6_Pos (6U)
8119 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
8120 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8121 #define GPIO_BSRR_BS7_Pos (7U)
8122 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
8123 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8124 #define GPIO_BSRR_BS8_Pos (8U)
8125 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
8126 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8127 #define GPIO_BSRR_BS9_Pos (9U)
8128 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
8129 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8130 #define GPIO_BSRR_BS10_Pos (10U)
8131 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
8132 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8133 #define GPIO_BSRR_BS11_Pos (11U)
8134 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
8135 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8136 #define GPIO_BSRR_BS12_Pos (12U)
8137 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
8138 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8139 #define GPIO_BSRR_BS13_Pos (13U)
8140 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
8141 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8142 #define GPIO_BSRR_BS14_Pos (14U)
8143 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
8144 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8145 #define GPIO_BSRR_BS15_Pos (15U)
8146 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
8147 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8148 #define GPIO_BSRR_BR0_Pos (16U)
8149 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
8150 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8151 #define GPIO_BSRR_BR1_Pos (17U)
8152 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
8153 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8154 #define GPIO_BSRR_BR2_Pos (18U)
8155 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
8156 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8157 #define GPIO_BSRR_BR3_Pos (19U)
8158 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
8159 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8160 #define GPIO_BSRR_BR4_Pos (20U)
8161 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
8162 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8163 #define GPIO_BSRR_BR5_Pos (21U)
8164 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
8165 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8166 #define GPIO_BSRR_BR6_Pos (22U)
8167 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
8168 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8169 #define GPIO_BSRR_BR7_Pos (23U)
8170 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
8171 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8172 #define GPIO_BSRR_BR8_Pos (24U)
8173 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
8174 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8175 #define GPIO_BSRR_BR9_Pos (25U)
8176 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
8177 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8178 #define GPIO_BSRR_BR10_Pos (26U)
8179 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
8180 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8181 #define GPIO_BSRR_BR11_Pos (27U)
8182 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
8183 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8184 #define GPIO_BSRR_BR12_Pos (28U)
8185 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
8186 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8187 #define GPIO_BSRR_BR13_Pos (29U)
8188 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
8189 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8190 #define GPIO_BSRR_BR14_Pos (30U)
8191 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
8192 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8193 #define GPIO_BSRR_BR15_Pos (31U)
8194 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
8195 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8196
8197 /* Legacy defines */
8198 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8199 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8200 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8201 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8202 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8203 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8204 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8205 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8206 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8207 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8208 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8209 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8210 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8211 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8212 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8213 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8214 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8215 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8216 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8217 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8218 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8219 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8220 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8221 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8222 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8223 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8224 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8225 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8226 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8227 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8228 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8229 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8230
8231 /****************** Bit definition for GPIO_LCKR register *********************/
8232 #define GPIO_LCKR_LCK0_Pos (0U)
8233 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
8234 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8235 #define GPIO_LCKR_LCK1_Pos (1U)
8236 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
8237 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8238 #define GPIO_LCKR_LCK2_Pos (2U)
8239 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
8240 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8241 #define GPIO_LCKR_LCK3_Pos (3U)
8242 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
8243 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8244 #define GPIO_LCKR_LCK4_Pos (4U)
8245 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
8246 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8247 #define GPIO_LCKR_LCK5_Pos (5U)
8248 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
8249 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8250 #define GPIO_LCKR_LCK6_Pos (6U)
8251 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
8252 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8253 #define GPIO_LCKR_LCK7_Pos (7U)
8254 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
8255 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8256 #define GPIO_LCKR_LCK8_Pos (8U)
8257 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
8258 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8259 #define GPIO_LCKR_LCK9_Pos (9U)
8260 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
8261 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8262 #define GPIO_LCKR_LCK10_Pos (10U)
8263 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
8264 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8265 #define GPIO_LCKR_LCK11_Pos (11U)
8266 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
8267 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8268 #define GPIO_LCKR_LCK12_Pos (12U)
8269 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
8270 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8271 #define GPIO_LCKR_LCK13_Pos (13U)
8272 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
8273 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8274 #define GPIO_LCKR_LCK14_Pos (14U)
8275 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
8276 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8277 #define GPIO_LCKR_LCK15_Pos (15U)
8278 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
8279 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8280 #define GPIO_LCKR_LCKK_Pos (16U)
8281 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
8282 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8283
8284 /****************** Bit definition for GPIO_AFRL register *********************/
8285 #define GPIO_AFRL_AFSEL0_Pos (0U)
8286 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
8287 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8288 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
8289 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
8290 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
8291 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
8292 #define GPIO_AFRL_AFSEL1_Pos (4U)
8293 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
8294 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8295 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
8296 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
8297 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
8298 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
8299 #define GPIO_AFRL_AFSEL2_Pos (8U)
8300 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
8301 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8302 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
8303 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
8304 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
8305 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
8306 #define GPIO_AFRL_AFSEL3_Pos (12U)
8307 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
8308 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8309 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
8310 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
8311 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
8312 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
8313 #define GPIO_AFRL_AFSEL4_Pos (16U)
8314 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
8315 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8316 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
8317 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
8318 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
8319 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
8320 #define GPIO_AFRL_AFSEL5_Pos (20U)
8321 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
8322 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8323 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
8324 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
8325 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
8326 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
8327 #define GPIO_AFRL_AFSEL6_Pos (24U)
8328 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
8329 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8330 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
8331 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
8332 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
8333 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
8334 #define GPIO_AFRL_AFSEL7_Pos (28U)
8335 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
8336 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8337 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
8338 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
8339 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
8340 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
8341
8342 /* Legacy defines */
8343 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8344 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8345 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8346 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8347 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8348 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8349 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8350 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8351
8352 /****************** Bit definition for GPIO_AFRH register *********************/
8353 #define GPIO_AFRH_AFSEL8_Pos (0U)
8354 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
8355 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8356 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
8357 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
8358 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
8359 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
8360 #define GPIO_AFRH_AFSEL9_Pos (4U)
8361 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
8362 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8363 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
8364 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
8365 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
8366 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
8367 #define GPIO_AFRH_AFSEL10_Pos (8U)
8368 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
8369 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8370 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
8371 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
8372 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
8373 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
8374 #define GPIO_AFRH_AFSEL11_Pos (12U)
8375 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
8376 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8377 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
8378 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
8379 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
8380 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
8381 #define GPIO_AFRH_AFSEL12_Pos (16U)
8382 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
8383 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8384 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
8385 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
8386 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
8387 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
8388 #define GPIO_AFRH_AFSEL13_Pos (20U)
8389 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
8390 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
8391 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
8392 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
8393 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
8394 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
8395 #define GPIO_AFRH_AFSEL14_Pos (24U)
8396 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
8397 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
8398 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
8399 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
8400 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
8401 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
8402 #define GPIO_AFRH_AFSEL15_Pos (28U)
8403 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
8404 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8405 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
8406 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
8407 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
8408 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
8409
8410 /* Legacy defines */
8411 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8412 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8413 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8414 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8415 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8416 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8417 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8418 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8419
8420 /****************** Bits definition for GPIO_BRR register ******************/
8421 #define GPIO_BRR_BR0_Pos (0U)
8422 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
8423 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
8424 #define GPIO_BRR_BR1_Pos (1U)
8425 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
8426 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
8427 #define GPIO_BRR_BR2_Pos (2U)
8428 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
8429 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
8430 #define GPIO_BRR_BR3_Pos (3U)
8431 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
8432 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
8433 #define GPIO_BRR_BR4_Pos (4U)
8434 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
8435 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
8436 #define GPIO_BRR_BR5_Pos (5U)
8437 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
8438 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
8439 #define GPIO_BRR_BR6_Pos (6U)
8440 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
8441 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
8442 #define GPIO_BRR_BR7_Pos (7U)
8443 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
8444 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
8445 #define GPIO_BRR_BR8_Pos (8U)
8446 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
8447 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
8448 #define GPIO_BRR_BR9_Pos (9U)
8449 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
8450 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
8451 #define GPIO_BRR_BR10_Pos (10U)
8452 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
8453 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
8454 #define GPIO_BRR_BR11_Pos (11U)
8455 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
8456 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
8457 #define GPIO_BRR_BR12_Pos (12U)
8458 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
8459 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
8460 #define GPIO_BRR_BR13_Pos (13U)
8461 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
8462 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
8463 #define GPIO_BRR_BR14_Pos (14U)
8464 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
8465 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
8466 #define GPIO_BRR_BR15_Pos (15U)
8467 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
8468 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
8469
8470 /* Legacy defines */
8471 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
8472 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
8473 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
8474 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
8475 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
8476 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
8477 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
8478 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
8479 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
8480 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
8481 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
8482 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
8483 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
8484 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
8485 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
8486 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
8487
8488
8489
8490 /******************************************************************************/
8491 /* */
8492 /* Inter-integrated Circuit Interface (I2C) */
8493 /* */
8494 /******************************************************************************/
8495 /******************* Bit definition for I2C_CR1 register *******************/
8496 #define I2C_CR1_PE_Pos (0U)
8497 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
8498 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
8499 #define I2C_CR1_TXIE_Pos (1U)
8500 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
8501 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
8502 #define I2C_CR1_RXIE_Pos (2U)
8503 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
8504 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
8505 #define I2C_CR1_ADDRIE_Pos (3U)
8506 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
8507 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
8508 #define I2C_CR1_NACKIE_Pos (4U)
8509 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
8510 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
8511 #define I2C_CR1_STOPIE_Pos (5U)
8512 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
8513 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
8514 #define I2C_CR1_TCIE_Pos (6U)
8515 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
8516 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
8517 #define I2C_CR1_ERRIE_Pos (7U)
8518 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
8519 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
8520 #define I2C_CR1_DNF_Pos (8U)
8521 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
8522 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
8523 #define I2C_CR1_ANFOFF_Pos (12U)
8524 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
8525 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
8526 #define I2C_CR1_SWRST_Pos (13U)
8527 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
8528 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
8529 #define I2C_CR1_TXDMAEN_Pos (14U)
8530 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
8531 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
8532 #define I2C_CR1_RXDMAEN_Pos (15U)
8533 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
8534 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
8535 #define I2C_CR1_SBC_Pos (16U)
8536 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
8537 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
8538 #define I2C_CR1_NOSTRETCH_Pos (17U)
8539 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
8540 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
8541 #define I2C_CR1_WUPEN_Pos (18U)
8542 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
8543 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
8544 #define I2C_CR1_GCEN_Pos (19U)
8545 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
8546 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
8547 #define I2C_CR1_SMBHEN_Pos (20U)
8548 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
8549 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
8550 #define I2C_CR1_SMBDEN_Pos (21U)
8551 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
8552 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
8553 #define I2C_CR1_ALERTEN_Pos (22U)
8554 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
8555 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
8556 #define I2C_CR1_PECEN_Pos (23U)
8557 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
8558 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
8559
8560 /****************** Bit definition for I2C_CR2 register ********************/
8561 #define I2C_CR2_SADD_Pos (0U)
8562 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
8563 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
8564 #define I2C_CR2_RD_WRN_Pos (10U)
8565 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
8566 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
8567 #define I2C_CR2_ADD10_Pos (11U)
8568 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
8569 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
8570 #define I2C_CR2_HEAD10R_Pos (12U)
8571 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
8572 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
8573 #define I2C_CR2_START_Pos (13U)
8574 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
8575 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
8576 #define I2C_CR2_STOP_Pos (14U)
8577 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
8578 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
8579 #define I2C_CR2_NACK_Pos (15U)
8580 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
8581 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
8582 #define I2C_CR2_NBYTES_Pos (16U)
8583 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
8584 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
8585 #define I2C_CR2_RELOAD_Pos (24U)
8586 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
8587 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
8588 #define I2C_CR2_AUTOEND_Pos (25U)
8589 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
8590 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
8591 #define I2C_CR2_PECBYTE_Pos (26U)
8592 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
8593 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
8594
8595 /******************* Bit definition for I2C_OAR1 register ******************/
8596 #define I2C_OAR1_OA1_Pos (0U)
8597 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
8598 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
8599 #define I2C_OAR1_OA1MODE_Pos (10U)
8600 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
8601 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
8602 #define I2C_OAR1_OA1EN_Pos (15U)
8603 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
8604 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
8605
8606 /******************* Bit definition for I2C_OAR2 register ******************/
8607 #define I2C_OAR2_OA2_Pos (1U)
8608 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
8609 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
8610 #define I2C_OAR2_OA2MSK_Pos (8U)
8611 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
8612 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
8613 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
8614 #define I2C_OAR2_OA2MASK01_Pos (8U)
8615 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
8616 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
8617 #define I2C_OAR2_OA2MASK02_Pos (9U)
8618 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
8619 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
8620 #define I2C_OAR2_OA2MASK03_Pos (8U)
8621 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
8622 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
8623 #define I2C_OAR2_OA2MASK04_Pos (10U)
8624 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
8625 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
8626 #define I2C_OAR2_OA2MASK05_Pos (8U)
8627 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
8628 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
8629 #define I2C_OAR2_OA2MASK06_Pos (9U)
8630 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
8631 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
8632 #define I2C_OAR2_OA2MASK07_Pos (8U)
8633 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
8634 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
8635 #define I2C_OAR2_OA2EN_Pos (15U)
8636 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
8637 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
8638
8639 /******************* Bit definition for I2C_TIMINGR register *******************/
8640 #define I2C_TIMINGR_SCLL_Pos (0U)
8641 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
8642 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
8643 #define I2C_TIMINGR_SCLH_Pos (8U)
8644 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
8645 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
8646 #define I2C_TIMINGR_SDADEL_Pos (16U)
8647 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
8648 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
8649 #define I2C_TIMINGR_SCLDEL_Pos (20U)
8650 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
8651 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
8652 #define I2C_TIMINGR_PRESC_Pos (28U)
8653 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
8654 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
8655
8656 /******************* Bit definition for I2C_TIMEOUTR register *******************/
8657 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
8658 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
8659 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
8660 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
8661 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
8662 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
8663 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
8664 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
8665 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
8666 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
8667 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
8668 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
8669 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
8670 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
8671 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
8672
8673 /****************** Bit definition for I2C_ISR register *********************/
8674 #define I2C_ISR_TXE_Pos (0U)
8675 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
8676 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
8677 #define I2C_ISR_TXIS_Pos (1U)
8678 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
8679 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
8680 #define I2C_ISR_RXNE_Pos (2U)
8681 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
8682 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
8683 #define I2C_ISR_ADDR_Pos (3U)
8684 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
8685 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
8686 #define I2C_ISR_NACKF_Pos (4U)
8687 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
8688 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
8689 #define I2C_ISR_STOPF_Pos (5U)
8690 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
8691 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
8692 #define I2C_ISR_TC_Pos (6U)
8693 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
8694 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
8695 #define I2C_ISR_TCR_Pos (7U)
8696 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
8697 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
8698 #define I2C_ISR_BERR_Pos (8U)
8699 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
8700 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
8701 #define I2C_ISR_ARLO_Pos (9U)
8702 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
8703 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
8704 #define I2C_ISR_OVR_Pos (10U)
8705 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
8706 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
8707 #define I2C_ISR_PECERR_Pos (11U)
8708 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
8709 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
8710 #define I2C_ISR_TIMEOUT_Pos (12U)
8711 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
8712 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
8713 #define I2C_ISR_ALERT_Pos (13U)
8714 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
8715 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
8716 #define I2C_ISR_BUSY_Pos (15U)
8717 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
8718 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
8719 #define I2C_ISR_DIR_Pos (16U)
8720 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
8721 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
8722 #define I2C_ISR_ADDCODE_Pos (17U)
8723 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
8724 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
8725
8726 /****************** Bit definition for I2C_ICR register *********************/
8727 #define I2C_ICR_ADDRCF_Pos (3U)
8728 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
8729 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
8730 #define I2C_ICR_NACKCF_Pos (4U)
8731 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
8732 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
8733 #define I2C_ICR_STOPCF_Pos (5U)
8734 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
8735 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
8736 #define I2C_ICR_BERRCF_Pos (8U)
8737 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
8738 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
8739 #define I2C_ICR_ARLOCF_Pos (9U)
8740 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
8741 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
8742 #define I2C_ICR_OVRCF_Pos (10U)
8743 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
8744 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
8745 #define I2C_ICR_PECCF_Pos (11U)
8746 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
8747 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
8748 #define I2C_ICR_TIMOUTCF_Pos (12U)
8749 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
8750 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
8751 #define I2C_ICR_ALERTCF_Pos (13U)
8752 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
8753 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
8754
8755 /****************** Bit definition for I2C_PECR register *********************/
8756 #define I2C_PECR_PEC_Pos (0U)
8757 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
8758 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
8759
8760 /****************** Bit definition for I2C_RXDR register *********************/
8761 #define I2C_RXDR_RXDATA_Pos (0U)
8762 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
8763 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
8764
8765 /****************** Bit definition for I2C_TXDR register *********************/
8766 #define I2C_TXDR_TXDATA_Pos (0U)
8767 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
8768 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
8769
8770 /******************************************************************************/
8771 /* */
8772 /* Independent WATCHDOG */
8773 /* */
8774 /******************************************************************************/
8775 /******************* Bit definition for IWDG_KR register ********************/
8776 #define IWDG_KR_KEY_Pos (0U)
8777 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
8778 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
8779
8780 /******************* Bit definition for IWDG_PR register ********************/
8781 #define IWDG_PR_PR_Pos (0U)
8782 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
8783 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
8784 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
8785 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
8786 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
8787
8788 /******************* Bit definition for IWDG_RLR register *******************/
8789 #define IWDG_RLR_RL_Pos (0U)
8790 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
8791 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
8792
8793 /******************* Bit definition for IWDG_SR register ********************/
8794 #define IWDG_SR_PVU_Pos (0U)
8795 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
8796 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
8797 #define IWDG_SR_RVU_Pos (1U)
8798 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
8799 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
8800 #define IWDG_SR_WVU_Pos (2U)
8801 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
8802 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
8803
8804 /******************* Bit definition for IWDG_KR register ********************/
8805 #define IWDG_WINR_WIN_Pos (0U)
8806 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
8807 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
8808
8809 /******************************************************************************/
8810 /* */
8811 /* Firewall */
8812 /* */
8813 /******************************************************************************/
8814
8815 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */
8816 #define FW_CSSA_ADD_Pos (8U)
8817 #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
8818 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
8819 #define FW_CSL_LENG_Pos (8U)
8820 #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
8821 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
8822 #define FW_NVDSSA_ADD_Pos (8U)
8823 #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
8824 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
8825 #define FW_NVDSL_LENG_Pos (8U)
8826 #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
8827 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
8828 #define FW_VDSSA_ADD_Pos (6U)
8829 #define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
8830 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
8831 #define FW_VDSL_LENG_Pos (6U)
8832 #define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
8833 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
8834 #define FW_LSSA_ADD_Pos (7U)
8835 #define FW_LSSA_ADD_Msk (0xFFFU << FW_LSSA_ADD_Pos) /*!< 0x0007FF80 */
8836 #define FW_LSSA_ADD FW_LSSA_ADD_Msk /*!< Library Segment Start Address*/
8837 #define FW_LSL_LENG_Pos (7U)
8838 #define FW_LSL_LENG_Msk (0xFFFU << FW_LSL_LENG_Pos) /*!< 0x0007FF80 */
8839 #define FW_LSL_LENG FW_LSL_LENG_Msk /*!< Library Segment Length*/
8840
8841 /**************************Bit definition for CR register *********************/
8842 #define FW_CR_FPA_Pos (0U)
8843 #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
8844 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
8845 #define FW_CR_VDS_Pos (1U)
8846 #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
8847 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
8848 #define FW_CR_VDE_Pos (2U)
8849 #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
8850 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
8851
8852 /******************************************************************************/
8853 /* */
8854 /* Power Control */
8855 /* */
8856 /******************************************************************************/
8857
8858 /******************** Bit definition for PWR_CR1 register ********************/
8859
8860 #define PWR_CR1_LPR_Pos (14U)
8861 #define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
8862 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
8863 #define PWR_CR1_VOS_Pos (9U)
8864 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
8865 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
8866 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
8867 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
8868 #define PWR_CR1_DBP_Pos (8U)
8869 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
8870 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
8871 #define PWR_CR1_LPMS_Pos (0U)
8872 #define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
8873 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
8874 #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
8875 #define PWR_CR1_LPMS_STOP1_Pos (0U)
8876 #define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
8877 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
8878 #define PWR_CR1_LPMS_STOP2_Pos (1U)
8879 #define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
8880 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
8881 #define PWR_CR1_LPMS_STANDBY_Pos (0U)
8882 #define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
8883 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
8884 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
8885 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
8886 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
8887
8888
8889 /******************** Bit definition for PWR_CR2 register ********************/
8890 /*!< PVME Peripheral Voltage Monitor Enable */
8891 #define PWR_CR2_PVME_Pos (6U)
8892 #define PWR_CR2_PVME_Msk (0x3U << PWR_CR2_PVME_Pos) /*!< 0x000000C0 */
8893 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
8894 #define PWR_CR2_PVME4_Pos (7U)
8895 #define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
8896 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
8897 #define PWR_CR2_PVME3_Pos (6U)
8898 #define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
8899 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
8900 /*!< PVD level configuration */
8901 #define PWR_CR2_PLS_Pos (1U)
8902 #define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
8903 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
8904 #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
8905 #define PWR_CR2_PLS_LEV1_Pos (1U)
8906 #define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
8907 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
8908 #define PWR_CR2_PLS_LEV2_Pos (2U)
8909 #define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
8910 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
8911 #define PWR_CR2_PLS_LEV3_Pos (1U)
8912 #define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
8913 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
8914 #define PWR_CR2_PLS_LEV4_Pos (3U)
8915 #define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
8916 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
8917 #define PWR_CR2_PLS_LEV5_Pos (1U)
8918 #define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
8919 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
8920 #define PWR_CR2_PLS_LEV6_Pos (2U)
8921 #define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
8922 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
8923 #define PWR_CR2_PLS_LEV7_Pos (1U)
8924 #define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
8925 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
8926 #define PWR_CR2_PVDE_Pos (0U)
8927 #define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
8928 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
8929
8930 /******************** Bit definition for PWR_CR3 register ********************/
8931 #define PWR_CR3_EIWF_Pos (15U)
8932 #define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
8933 #define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
8934 #define PWR_CR3_APC_Pos (10U)
8935 #define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
8936 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
8937 #define PWR_CR3_RRS_Pos (8U)
8938 #define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
8939 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
8940 #define PWR_CR3_EWUP5_Pos (4U)
8941 #define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
8942 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
8943 #define PWR_CR3_EWUP4_Pos (3U)
8944 #define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
8945 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
8946 #define PWR_CR3_EWUP3_Pos (2U)
8947 #define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
8948 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
8949 #define PWR_CR3_EWUP2_Pos (1U)
8950 #define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
8951 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
8952 #define PWR_CR3_EWUP1_Pos (0U)
8953 #define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
8954 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
8955 #define PWR_CR3_EWUP_Pos (0U)
8956 #define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
8957 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
8958
8959 /******************** Bit definition for PWR_CR4 register ********************/
8960 #define PWR_CR4_VBRS_Pos (9U)
8961 #define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
8962 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
8963 #define PWR_CR4_VBE_Pos (8U)
8964 #define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
8965 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
8966 #define PWR_CR4_WP5_Pos (4U)
8967 #define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
8968 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
8969 #define PWR_CR4_WP4_Pos (3U)
8970 #define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
8971 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
8972 #define PWR_CR4_WP3_Pos (2U)
8973 #define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
8974 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
8975 #define PWR_CR4_WP2_Pos (1U)
8976 #define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
8977 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
8978 #define PWR_CR4_WP1_Pos (0U)
8979 #define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
8980 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
8981
8982 /******************** Bit definition for PWR_SR1 register ********************/
8983 #define PWR_SR1_WUFI_Pos (15U)
8984 #define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
8985 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
8986 #define PWR_SR1_SBF_Pos (8U)
8987 #define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
8988 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
8989 #define PWR_SR1_WUF_Pos (0U)
8990 #define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
8991 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
8992 #define PWR_SR1_WUF5_Pos (4U)
8993 #define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
8994 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
8995 #define PWR_SR1_WUF4_Pos (3U)
8996 #define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
8997 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
8998 #define PWR_SR1_WUF3_Pos (2U)
8999 #define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
9000 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
9001 #define PWR_SR1_WUF2_Pos (1U)
9002 #define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
9003 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
9004 #define PWR_SR1_WUF1_Pos (0U)
9005 #define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
9006 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
9007
9008 /******************** Bit definition for PWR_SR2 register ********************/
9009 #define PWR_SR2_PVMO4_Pos (15U)
9010 #define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
9011 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
9012 #define PWR_SR2_PVMO3_Pos (14U)
9013 #define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
9014 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
9015 #define PWR_SR2_PVDO_Pos (11U)
9016 #define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
9017 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
9018 #define PWR_SR2_VOSF_Pos (10U)
9019 #define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
9020 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
9021 #define PWR_SR2_REGLPF_Pos (9U)
9022 #define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
9023 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
9024 #define PWR_SR2_REGLPS_Pos (8U)
9025 #define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
9026 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
9027
9028 /******************** Bit definition for PWR_SCR register ********************/
9029 #define PWR_SCR_CSBF_Pos (8U)
9030 #define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
9031 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
9032 #define PWR_SCR_CWUF_Pos (0U)
9033 #define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
9034 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
9035 #define PWR_SCR_CWUF5_Pos (4U)
9036 #define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
9037 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
9038 #define PWR_SCR_CWUF4_Pos (3U)
9039 #define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
9040 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
9041 #define PWR_SCR_CWUF3_Pos (2U)
9042 #define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
9043 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
9044 #define PWR_SCR_CWUF2_Pos (1U)
9045 #define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
9046 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
9047 #define PWR_SCR_CWUF1_Pos (0U)
9048 #define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
9049 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
9050
9051 /******************** Bit definition for PWR_PUCRA register ********************/
9052 #define PWR_PUCRA_PA15_Pos (15U)
9053 #define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
9054 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
9055 #define PWR_PUCRA_PA13_Pos (13U)
9056 #define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
9057 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
9058 #define PWR_PUCRA_PA12_Pos (12U)
9059 #define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
9060 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
9061 #define PWR_PUCRA_PA11_Pos (11U)
9062 #define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
9063 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
9064 #define PWR_PUCRA_PA10_Pos (10U)
9065 #define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
9066 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
9067 #define PWR_PUCRA_PA9_Pos (9U)
9068 #define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
9069 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
9070 #define PWR_PUCRA_PA8_Pos (8U)
9071 #define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
9072 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
9073 #define PWR_PUCRA_PA7_Pos (7U)
9074 #define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
9075 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
9076 #define PWR_PUCRA_PA6_Pos (6U)
9077 #define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
9078 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
9079 #define PWR_PUCRA_PA5_Pos (5U)
9080 #define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
9081 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
9082 #define PWR_PUCRA_PA4_Pos (4U)
9083 #define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
9084 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
9085 #define PWR_PUCRA_PA3_Pos (3U)
9086 #define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
9087 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
9088 #define PWR_PUCRA_PA2_Pos (2U)
9089 #define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
9090 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
9091 #define PWR_PUCRA_PA1_Pos (1U)
9092 #define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
9093 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
9094 #define PWR_PUCRA_PA0_Pos (0U)
9095 #define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
9096 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
9097
9098 /******************** Bit definition for PWR_PDCRA register ********************/
9099 #define PWR_PDCRA_PA14_Pos (14U)
9100 #define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
9101 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
9102 #define PWR_PDCRA_PA12_Pos (12U)
9103 #define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
9104 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
9105 #define PWR_PDCRA_PA11_Pos (11U)
9106 #define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
9107 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
9108 #define PWR_PDCRA_PA10_Pos (10U)
9109 #define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
9110 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
9111 #define PWR_PDCRA_PA9_Pos (9U)
9112 #define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
9113 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
9114 #define PWR_PDCRA_PA8_Pos (8U)
9115 #define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
9116 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
9117 #define PWR_PDCRA_PA7_Pos (7U)
9118 #define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
9119 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
9120 #define PWR_PDCRA_PA6_Pos (6U)
9121 #define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
9122 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
9123 #define PWR_PDCRA_PA5_Pos (5U)
9124 #define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
9125 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
9126 #define PWR_PDCRA_PA4_Pos (4U)
9127 #define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
9128 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
9129 #define PWR_PDCRA_PA3_Pos (3U)
9130 #define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
9131 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
9132 #define PWR_PDCRA_PA2_Pos (2U)
9133 #define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
9134 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
9135 #define PWR_PDCRA_PA1_Pos (1U)
9136 #define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
9137 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
9138 #define PWR_PDCRA_PA0_Pos (0U)
9139 #define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
9140 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
9141
9142 /******************** Bit definition for PWR_PUCRB register ********************/
9143 #define PWR_PUCRB_PB15_Pos (15U)
9144 #define PWR_PUCRB_PB15_Msk (0x1U << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
9145 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
9146 #define PWR_PUCRB_PB14_Pos (14U)
9147 #define PWR_PUCRB_PB14_Msk (0x1U << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
9148 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
9149 #define PWR_PUCRB_PB13_Pos (13U)
9150 #define PWR_PUCRB_PB13_Msk (0x1U << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
9151 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
9152 #define PWR_PUCRB_PB12_Pos (12U)
9153 #define PWR_PUCRB_PB12_Msk (0x1U << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
9154 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
9155 #define PWR_PUCRB_PB11_Pos (11U)
9156 #define PWR_PUCRB_PB11_Msk (0x1U << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
9157 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
9158 #define PWR_PUCRB_PB10_Pos (10U)
9159 #define PWR_PUCRB_PB10_Msk (0x1U << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
9160 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
9161 #define PWR_PUCRB_PB9_Pos (9U)
9162 #define PWR_PUCRB_PB9_Msk (0x1U << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
9163 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
9164 #define PWR_PUCRB_PB8_Pos (8U)
9165 #define PWR_PUCRB_PB8_Msk (0x1U << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
9166 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
9167 #define PWR_PUCRB_PB7_Pos (7U)
9168 #define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
9169 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
9170 #define PWR_PUCRB_PB6_Pos (6U)
9171 #define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
9172 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
9173 #define PWR_PUCRB_PB5_Pos (5U)
9174 #define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
9175 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
9176 #define PWR_PUCRB_PB4_Pos (4U)
9177 #define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
9178 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
9179 #define PWR_PUCRB_PB3_Pos (3U)
9180 #define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
9181 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
9182 #define PWR_PUCRB_PB2_Pos (2U)
9183 #define PWR_PUCRB_PB2_Msk (0x1U << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
9184 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
9185 #define PWR_PUCRB_PB1_Pos (1U)
9186 #define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
9187 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
9188 #define PWR_PUCRB_PB0_Pos (0U)
9189 #define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
9190 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
9191
9192 /******************** Bit definition for PWR_PDCRB register ********************/
9193 #define PWR_PDCRB_PB15_Pos (15U)
9194 #define PWR_PDCRB_PB15_Msk (0x1U << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
9195 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
9196 #define PWR_PDCRB_PB14_Pos (14U)
9197 #define PWR_PDCRB_PB14_Msk (0x1U << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
9198 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
9199 #define PWR_PDCRB_PB13_Pos (13U)
9200 #define PWR_PDCRB_PB13_Msk (0x1U << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
9201 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
9202 #define PWR_PDCRB_PB12_Pos (12U)
9203 #define PWR_PDCRB_PB12_Msk (0x1U << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
9204 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
9205 #define PWR_PDCRB_PB11_Pos (11U)
9206 #define PWR_PDCRB_PB11_Msk (0x1U << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
9207 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
9208 #define PWR_PDCRB_PB10_Pos (10U)
9209 #define PWR_PDCRB_PB10_Msk (0x1U << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
9210 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
9211 #define PWR_PDCRB_PB9_Pos (9U)
9212 #define PWR_PDCRB_PB9_Msk (0x1U << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
9213 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
9214 #define PWR_PDCRB_PB8_Pos (8U)
9215 #define PWR_PDCRB_PB8_Msk (0x1U << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
9216 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
9217 #define PWR_PDCRB_PB7_Pos (7U)
9218 #define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
9219 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
9220 #define PWR_PDCRB_PB6_Pos (6U)
9221 #define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
9222 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
9223 #define PWR_PDCRB_PB5_Pos (5U)
9224 #define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
9225 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
9226 #define PWR_PDCRB_PB3_Pos (3U)
9227 #define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
9228 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
9229 #define PWR_PDCRB_PB2_Pos (2U)
9230 #define PWR_PDCRB_PB2_Msk (0x1U << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
9231 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
9232 #define PWR_PDCRB_PB1_Pos (1U)
9233 #define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
9234 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
9235 #define PWR_PDCRB_PB0_Pos (0U)
9236 #define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
9237 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
9238
9239 /******************** Bit definition for PWR_PUCRC register ********************/
9240 #define PWR_PUCRC_PC15_Pos (15U)
9241 #define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
9242 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
9243 #define PWR_PUCRC_PC14_Pos (14U)
9244 #define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
9245 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
9246 #define PWR_PUCRC_PC13_Pos (13U)
9247 #define PWR_PUCRC_PC13_Msk (0x1U << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
9248 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
9249 #define PWR_PUCRC_PC12_Pos (12U)
9250 #define PWR_PUCRC_PC12_Msk (0x1U << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
9251 #define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
9252 #define PWR_PUCRC_PC11_Pos (11U)
9253 #define PWR_PUCRC_PC11_Msk (0x1U << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
9254 #define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
9255 #define PWR_PUCRC_PC10_Pos (10U)
9256 #define PWR_PUCRC_PC10_Msk (0x1U << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
9257 #define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
9258 #define PWR_PUCRC_PC9_Pos (9U)
9259 #define PWR_PUCRC_PC9_Msk (0x1U << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
9260 #define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
9261 #define PWR_PUCRC_PC8_Pos (8U)
9262 #define PWR_PUCRC_PC8_Msk (0x1U << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
9263 #define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
9264 #define PWR_PUCRC_PC7_Pos (7U)
9265 #define PWR_PUCRC_PC7_Msk (0x1U << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
9266 #define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
9267 #define PWR_PUCRC_PC6_Pos (6U)
9268 #define PWR_PUCRC_PC6_Msk (0x1U << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
9269 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
9270 #define PWR_PUCRC_PC5_Pos (5U)
9271 #define PWR_PUCRC_PC5_Msk (0x1U << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
9272 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
9273 #define PWR_PUCRC_PC4_Pos (4U)
9274 #define PWR_PUCRC_PC4_Msk (0x1U << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
9275 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
9276 #define PWR_PUCRC_PC3_Pos (3U)
9277 #define PWR_PUCRC_PC3_Msk (0x1U << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
9278 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
9279 #define PWR_PUCRC_PC2_Pos (2U)
9280 #define PWR_PUCRC_PC2_Msk (0x1U << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
9281 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
9282 #define PWR_PUCRC_PC1_Pos (1U)
9283 #define PWR_PUCRC_PC1_Msk (0x1U << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
9284 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
9285 #define PWR_PUCRC_PC0_Pos (0U)
9286 #define PWR_PUCRC_PC0_Msk (0x1U << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
9287 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
9288
9289 /******************** Bit definition for PWR_PDCRC register ********************/
9290 #define PWR_PDCRC_PC15_Pos (15U)
9291 #define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
9292 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
9293 #define PWR_PDCRC_PC14_Pos (14U)
9294 #define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
9295 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
9296 #define PWR_PDCRC_PC13_Pos (13U)
9297 #define PWR_PDCRC_PC13_Msk (0x1U << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
9298 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
9299 #define PWR_PDCRC_PC12_Pos (12U)
9300 #define PWR_PDCRC_PC12_Msk (0x1U << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
9301 #define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
9302 #define PWR_PDCRC_PC11_Pos (11U)
9303 #define PWR_PDCRC_PC11_Msk (0x1U << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
9304 #define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
9305 #define PWR_PDCRC_PC10_Pos (10U)
9306 #define PWR_PDCRC_PC10_Msk (0x1U << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
9307 #define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
9308 #define PWR_PDCRC_PC9_Pos (9U)
9309 #define PWR_PDCRC_PC9_Msk (0x1U << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
9310 #define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
9311 #define PWR_PDCRC_PC8_Pos (8U)
9312 #define PWR_PDCRC_PC8_Msk (0x1U << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
9313 #define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
9314 #define PWR_PDCRC_PC7_Pos (7U)
9315 #define PWR_PDCRC_PC7_Msk (0x1U << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
9316 #define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
9317 #define PWR_PDCRC_PC6_Pos (6U)
9318 #define PWR_PDCRC_PC6_Msk (0x1U << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
9319 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
9320 #define PWR_PDCRC_PC5_Pos (5U)
9321 #define PWR_PDCRC_PC5_Msk (0x1U << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
9322 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
9323 #define PWR_PDCRC_PC4_Pos (4U)
9324 #define PWR_PDCRC_PC4_Msk (0x1U << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
9325 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
9326 #define PWR_PDCRC_PC3_Pos (3U)
9327 #define PWR_PDCRC_PC3_Msk (0x1U << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
9328 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
9329 #define PWR_PDCRC_PC2_Pos (2U)
9330 #define PWR_PDCRC_PC2_Msk (0x1U << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
9331 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
9332 #define PWR_PDCRC_PC1_Pos (1U)
9333 #define PWR_PDCRC_PC1_Msk (0x1U << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
9334 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
9335 #define PWR_PDCRC_PC0_Pos (0U)
9336 #define PWR_PDCRC_PC0_Msk (0x1U << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
9337 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
9338
9339 /******************** Bit definition for PWR_PUCRD register ********************/
9340 #define PWR_PUCRD_PD15_Pos (15U)
9341 #define PWR_PUCRD_PD15_Msk (0x1U << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
9342 #define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
9343 #define PWR_PUCRD_PD14_Pos (14U)
9344 #define PWR_PUCRD_PD14_Msk (0x1U << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
9345 #define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
9346 #define PWR_PUCRD_PD13_Pos (13U)
9347 #define PWR_PUCRD_PD13_Msk (0x1U << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
9348 #define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
9349 #define PWR_PUCRD_PD12_Pos (12U)
9350 #define PWR_PUCRD_PD12_Msk (0x1U << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
9351 #define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
9352 #define PWR_PUCRD_PD11_Pos (11U)
9353 #define PWR_PUCRD_PD11_Msk (0x1U << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
9354 #define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
9355 #define PWR_PUCRD_PD10_Pos (10U)
9356 #define PWR_PUCRD_PD10_Msk (0x1U << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
9357 #define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
9358 #define PWR_PUCRD_PD9_Pos (9U)
9359 #define PWR_PUCRD_PD9_Msk (0x1U << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
9360 #define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
9361 #define PWR_PUCRD_PD8_Pos (8U)
9362 #define PWR_PUCRD_PD8_Msk (0x1U << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
9363 #define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
9364 #define PWR_PUCRD_PD7_Pos (7U)
9365 #define PWR_PUCRD_PD7_Msk (0x1U << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
9366 #define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
9367 #define PWR_PUCRD_PD6_Pos (6U)
9368 #define PWR_PUCRD_PD6_Msk (0x1U << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
9369 #define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
9370 #define PWR_PUCRD_PD5_Pos (5U)
9371 #define PWR_PUCRD_PD5_Msk (0x1U << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
9372 #define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
9373 #define PWR_PUCRD_PD4_Pos (4U)
9374 #define PWR_PUCRD_PD4_Msk (0x1U << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
9375 #define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
9376 #define PWR_PUCRD_PD3_Pos (3U)
9377 #define PWR_PUCRD_PD3_Msk (0x1U << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
9378 #define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
9379 #define PWR_PUCRD_PD2_Pos (2U)
9380 #define PWR_PUCRD_PD2_Msk (0x1U << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
9381 #define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
9382 #define PWR_PUCRD_PD1_Pos (1U)
9383 #define PWR_PUCRD_PD1_Msk (0x1U << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
9384 #define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
9385 #define PWR_PUCRD_PD0_Pos (0U)
9386 #define PWR_PUCRD_PD0_Msk (0x1U << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
9387 #define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
9388
9389 /******************** Bit definition for PWR_PDCRD register ********************/
9390 #define PWR_PDCRD_PD15_Pos (15U)
9391 #define PWR_PDCRD_PD15_Msk (0x1U << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
9392 #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
9393 #define PWR_PDCRD_PD14_Pos (14U)
9394 #define PWR_PDCRD_PD14_Msk (0x1U << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
9395 #define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
9396 #define PWR_PDCRD_PD13_Pos (13U)
9397 #define PWR_PDCRD_PD13_Msk (0x1U << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
9398 #define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
9399 #define PWR_PDCRD_PD12_Pos (12U)
9400 #define PWR_PDCRD_PD12_Msk (0x1U << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
9401 #define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
9402 #define PWR_PDCRD_PD11_Pos (11U)
9403 #define PWR_PDCRD_PD11_Msk (0x1U << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
9404 #define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
9405 #define PWR_PDCRD_PD10_Pos (10U)
9406 #define PWR_PDCRD_PD10_Msk (0x1U << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
9407 #define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
9408 #define PWR_PDCRD_PD9_Pos (9U)
9409 #define PWR_PDCRD_PD9_Msk (0x1U << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
9410 #define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
9411 #define PWR_PDCRD_PD8_Pos (8U)
9412 #define PWR_PDCRD_PD8_Msk (0x1U << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
9413 #define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
9414 #define PWR_PDCRD_PD7_Pos (7U)
9415 #define PWR_PDCRD_PD7_Msk (0x1U << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
9416 #define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
9417 #define PWR_PDCRD_PD6_Pos (6U)
9418 #define PWR_PDCRD_PD6_Msk (0x1U << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
9419 #define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
9420 #define PWR_PDCRD_PD5_Pos (5U)
9421 #define PWR_PDCRD_PD5_Msk (0x1U << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
9422 #define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
9423 #define PWR_PDCRD_PD4_Pos (4U)
9424 #define PWR_PDCRD_PD4_Msk (0x1U << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
9425 #define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
9426 #define PWR_PDCRD_PD3_Pos (3U)
9427 #define PWR_PDCRD_PD3_Msk (0x1U << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
9428 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
9429 #define PWR_PDCRD_PD2_Pos (2U)
9430 #define PWR_PDCRD_PD2_Msk (0x1U << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
9431 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
9432 #define PWR_PDCRD_PD1_Pos (1U)
9433 #define PWR_PDCRD_PD1_Msk (0x1U << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
9434 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
9435 #define PWR_PDCRD_PD0_Pos (0U)
9436 #define PWR_PDCRD_PD0_Msk (0x1U << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
9437 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
9438
9439 /******************** Bit definition for PWR_PUCRE register ********************/
9440 #define PWR_PUCRE_PE15_Pos (15U)
9441 #define PWR_PUCRE_PE15_Msk (0x1U << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
9442 #define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
9443 #define PWR_PUCRE_PE14_Pos (14U)
9444 #define PWR_PUCRE_PE14_Msk (0x1U << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
9445 #define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
9446 #define PWR_PUCRE_PE13_Pos (13U)
9447 #define PWR_PUCRE_PE13_Msk (0x1U << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
9448 #define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
9449 #define PWR_PUCRE_PE12_Pos (12U)
9450 #define PWR_PUCRE_PE12_Msk (0x1U << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
9451 #define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
9452 #define PWR_PUCRE_PE11_Pos (11U)
9453 #define PWR_PUCRE_PE11_Msk (0x1U << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
9454 #define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
9455 #define PWR_PUCRE_PE10_Pos (10U)
9456 #define PWR_PUCRE_PE10_Msk (0x1U << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
9457 #define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
9458 #define PWR_PUCRE_PE9_Pos (9U)
9459 #define PWR_PUCRE_PE9_Msk (0x1U << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
9460 #define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
9461 #define PWR_PUCRE_PE8_Pos (8U)
9462 #define PWR_PUCRE_PE8_Msk (0x1U << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
9463 #define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
9464 #define PWR_PUCRE_PE7_Pos (7U)
9465 #define PWR_PUCRE_PE7_Msk (0x1U << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
9466 #define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
9467 #define PWR_PUCRE_PE6_Pos (6U)
9468 #define PWR_PUCRE_PE6_Msk (0x1U << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
9469 #define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
9470 #define PWR_PUCRE_PE5_Pos (5U)
9471 #define PWR_PUCRE_PE5_Msk (0x1U << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
9472 #define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
9473 #define PWR_PUCRE_PE4_Pos (4U)
9474 #define PWR_PUCRE_PE4_Msk (0x1U << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
9475 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
9476 #define PWR_PUCRE_PE3_Pos (3U)
9477 #define PWR_PUCRE_PE3_Msk (0x1U << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
9478 #define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
9479 #define PWR_PUCRE_PE2_Pos (2U)
9480 #define PWR_PUCRE_PE2_Msk (0x1U << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
9481 #define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
9482 #define PWR_PUCRE_PE1_Pos (1U)
9483 #define PWR_PUCRE_PE1_Msk (0x1U << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
9484 #define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
9485 #define PWR_PUCRE_PE0_Pos (0U)
9486 #define PWR_PUCRE_PE0_Msk (0x1U << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
9487 #define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
9488
9489 /******************** Bit definition for PWR_PDCRE register ********************/
9490 #define PWR_PDCRE_PE15_Pos (15U)
9491 #define PWR_PDCRE_PE15_Msk (0x1U << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
9492 #define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
9493 #define PWR_PDCRE_PE14_Pos (14U)
9494 #define PWR_PDCRE_PE14_Msk (0x1U << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
9495 #define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
9496 #define PWR_PDCRE_PE13_Pos (13U)
9497 #define PWR_PDCRE_PE13_Msk (0x1U << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
9498 #define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
9499 #define PWR_PDCRE_PE12_Pos (12U)
9500 #define PWR_PDCRE_PE12_Msk (0x1U << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
9501 #define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
9502 #define PWR_PDCRE_PE11_Pos (11U)
9503 #define PWR_PDCRE_PE11_Msk (0x1U << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
9504 #define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
9505 #define PWR_PDCRE_PE10_Pos (10U)
9506 #define PWR_PDCRE_PE10_Msk (0x1U << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
9507 #define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
9508 #define PWR_PDCRE_PE9_Pos (9U)
9509 #define PWR_PDCRE_PE9_Msk (0x1U << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
9510 #define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
9511 #define PWR_PDCRE_PE8_Pos (8U)
9512 #define PWR_PDCRE_PE8_Msk (0x1U << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
9513 #define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
9514 #define PWR_PDCRE_PE7_Pos (7U)
9515 #define PWR_PDCRE_PE7_Msk (0x1U << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
9516 #define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
9517 #define PWR_PDCRE_PE6_Pos (6U)
9518 #define PWR_PDCRE_PE6_Msk (0x1U << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
9519 #define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
9520 #define PWR_PDCRE_PE5_Pos (5U)
9521 #define PWR_PDCRE_PE5_Msk (0x1U << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
9522 #define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
9523 #define PWR_PDCRE_PE4_Pos (4U)
9524 #define PWR_PDCRE_PE4_Msk (0x1U << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
9525 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
9526 #define PWR_PDCRE_PE3_Pos (3U)
9527 #define PWR_PDCRE_PE3_Msk (0x1U << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
9528 #define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
9529 #define PWR_PDCRE_PE2_Pos (2U)
9530 #define PWR_PDCRE_PE2_Msk (0x1U << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
9531 #define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
9532 #define PWR_PDCRE_PE1_Pos (1U)
9533 #define PWR_PDCRE_PE1_Msk (0x1U << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
9534 #define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
9535 #define PWR_PDCRE_PE0_Pos (0U)
9536 #define PWR_PDCRE_PE0_Msk (0x1U << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
9537 #define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
9538
9539
9540 /******************** Bit definition for PWR_PUCRH register ********************/
9541 #define PWR_PUCRH_PH1_Pos (1U)
9542 #define PWR_PUCRH_PH1_Msk (0x1U << PWR_PUCRH_PH1_Pos) /*!< 0x00000002 */
9543 #define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk /*!< Port PH1 Pull-Up set */
9544 #define PWR_PUCRH_PH0_Pos (0U)
9545 #define PWR_PUCRH_PH0_Msk (0x1U << PWR_PUCRH_PH0_Pos) /*!< 0x00000001 */
9546 #define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk /*!< Port PH0 Pull-Up set */
9547
9548 /******************** Bit definition for PWR_PDCRH register ********************/
9549 #define PWR_PDCRH_PH1_Pos (1U)
9550 #define PWR_PDCRH_PH1_Msk (0x1U << PWR_PDCRH_PH1_Pos) /*!< 0x00000002 */
9551 #define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk /*!< Port PH1 Pull-Down set */
9552 #define PWR_PDCRH_PH0_Pos (0U)
9553 #define PWR_PDCRH_PH0_Msk (0x1U << PWR_PDCRH_PH0_Pos) /*!< 0x00000001 */
9554 #define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk /*!< Port PH0 Pull-Down set */
9555
9556
9557 /******************************************************************************/
9558 /* */
9559 /* Reset and Clock Control */
9560 /* */
9561 /******************************************************************************/
9562 /*
9563 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
9564 */
9565 #define RCC_HSI48_SUPPORT
9566 #define RCC_PLLP_DIV_2_31_SUPPORT
9567 #define RCC_PLLSAI1P_DIV_2_31_SUPPORT
9568
9569 /******************** Bit definition for RCC_CR register ********************/
9570 #define RCC_CR_MSION_Pos (0U)
9571 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
9572 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
9573 #define RCC_CR_MSIRDY_Pos (1U)
9574 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
9575 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
9576 #define RCC_CR_MSIPLLEN_Pos (2U)
9577 #define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
9578 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
9579 #define RCC_CR_MSIRGSEL_Pos (3U)
9580 #define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
9581 #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
9582
9583 /*!< MSIRANGE configuration : 12 frequency ranges available */
9584 #define RCC_CR_MSIRANGE_Pos (4U)
9585 #define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
9586 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
9587 #define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
9588 #define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
9589 #define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
9590 #define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
9591 #define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
9592 #define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
9593 #define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
9594 #define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
9595 #define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
9596 #define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
9597 #define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
9598 #define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
9599
9600 #define RCC_CR_HSION_Pos (8U)
9601 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
9602 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
9603 #define RCC_CR_HSIKERON_Pos (9U)
9604 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
9605 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
9606 #define RCC_CR_HSIRDY_Pos (10U)
9607 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
9608 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
9609 #define RCC_CR_HSIASFS_Pos (11U)
9610 #define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
9611 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
9612
9613 #define RCC_CR_HSEON_Pos (16U)
9614 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
9615 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
9616 #define RCC_CR_HSERDY_Pos (17U)
9617 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
9618 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
9619 #define RCC_CR_HSEBYP_Pos (18U)
9620 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
9621 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
9622 #define RCC_CR_CSSON_Pos (19U)
9623 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
9624 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
9625
9626 #define RCC_CR_PLLON_Pos (24U)
9627 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
9628 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
9629 #define RCC_CR_PLLRDY_Pos (25U)
9630 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
9631 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
9632 #define RCC_CR_PLLSAI1ON_Pos (26U)
9633 #define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
9634 #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
9635 #define RCC_CR_PLLSAI1RDY_Pos (27U)
9636 #define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
9637 #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
9638
9639 /******************** Bit definition for RCC_ICSCR register ***************/
9640 /*!< MSICAL configuration */
9641 #define RCC_ICSCR_MSICAL_Pos (0U)
9642 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
9643 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
9644 #define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
9645 #define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
9646 #define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
9647 #define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
9648 #define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
9649 #define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
9650 #define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
9651 #define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
9652
9653 /*!< MSITRIM configuration */
9654 #define RCC_ICSCR_MSITRIM_Pos (8U)
9655 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
9656 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
9657 #define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
9658 #define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
9659 #define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
9660 #define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
9661 #define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
9662 #define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
9663 #define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
9664 #define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
9665
9666 /*!< HSICAL configuration */
9667 #define RCC_ICSCR_HSICAL_Pos (16U)
9668 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
9669 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
9670 #define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
9671 #define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
9672 #define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
9673 #define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
9674 #define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
9675 #define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
9676 #define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
9677 #define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
9678
9679 /*!< HSITRIM configuration */
9680 #define RCC_ICSCR_HSITRIM_Pos (24U)
9681 #define RCC_ICSCR_HSITRIM_Msk (0x7FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
9682 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
9683 #define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
9684 #define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
9685 #define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
9686 #define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
9687 #define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
9688 #define RCC_ICSCR_HSITRIM_5 (0x20U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
9689 #define RCC_ICSCR_HSITRIM_6 (0x40U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
9690
9691 /******************** Bit definition for RCC_CFGR register ******************/
9692 /*!< SW configuration */
9693 #define RCC_CFGR_SW_Pos (0U)
9694 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
9695 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
9696 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
9697 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
9698
9699 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
9700 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
9701 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
9702 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
9703
9704 /*!< SWS configuration */
9705 #define RCC_CFGR_SWS_Pos (2U)
9706 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
9707 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
9708 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
9709 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
9710
9711 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
9712 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
9713 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
9714 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
9715
9716 /*!< HPRE configuration */
9717 #define RCC_CFGR_HPRE_Pos (4U)
9718 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
9719 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
9720 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
9721 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
9722 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
9723 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
9724
9725 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
9726 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
9727 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
9728 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
9729 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
9730 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
9731 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
9732 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
9733 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
9734
9735 /*!< PPRE1 configuration */
9736 #define RCC_CFGR_PPRE1_Pos (8U)
9737 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
9738 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
9739 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
9740 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
9741 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
9742
9743 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
9744 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
9745 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
9746 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
9747 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
9748
9749 /*!< PPRE2 configuration */
9750 #define RCC_CFGR_PPRE2_Pos (11U)
9751 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
9752 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
9753 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
9754 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
9755 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
9756
9757 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
9758 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
9759 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
9760 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
9761 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
9762
9763 #define RCC_CFGR_STOPWUCK_Pos (15U)
9764 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
9765 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
9766
9767 /*!< MCOSEL configuration */
9768 #define RCC_CFGR_MCOSEL_Pos (24U)
9769 #define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
9770 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
9771 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
9772 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
9773 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
9774 #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
9775
9776 #define RCC_CFGR_MCOPRE_Pos (28U)
9777 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
9778 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
9779 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
9780 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
9781 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
9782
9783 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
9784 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
9785 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
9786 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
9787 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
9788
9789 /* Legacy aliases */
9790 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
9791 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
9792 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
9793 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
9794 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
9795 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
9796
9797 /******************** Bit definition for RCC_PLLCFGR register ***************/
9798 #define RCC_PLLCFGR_PLLSRC_Pos (0U)
9799 #define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
9800 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9801
9802 #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
9803 #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
9804 #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
9805 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
9806 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
9807 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
9808 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
9809 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
9810 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
9811
9812 #define RCC_PLLCFGR_PLLM_Pos (4U)
9813 #define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
9814 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9815 #define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
9816 #define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
9817 #define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
9818
9819 #define RCC_PLLCFGR_PLLN_Pos (8U)
9820 #define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
9821 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9822 #define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
9823 #define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
9824 #define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
9825 #define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
9826 #define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
9827 #define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
9828 #define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
9829
9830 #define RCC_PLLCFGR_PLLPEN_Pos (16U)
9831 #define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
9832 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
9833 #define RCC_PLLCFGR_PLLP_Pos (17U)
9834 #define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
9835 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9836 #define RCC_PLLCFGR_PLLQEN_Pos (20U)
9837 #define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
9838 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
9839
9840 #define RCC_PLLCFGR_PLLQ_Pos (21U)
9841 #define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
9842 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9843 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
9844 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
9845
9846 #define RCC_PLLCFGR_PLLREN_Pos (24U)
9847 #define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
9848 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
9849 #define RCC_PLLCFGR_PLLR_Pos (25U)
9850 #define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
9851 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
9852 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
9853 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
9854
9855 #define RCC_PLLCFGR_PLLPDIV_Pos (27U)
9856 #define RCC_PLLCFGR_PLLPDIV_Msk (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
9857 #define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
9858 #define RCC_PLLCFGR_PLLPDIV_0 (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
9859 #define RCC_PLLCFGR_PLLPDIV_1 (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
9860 #define RCC_PLLCFGR_PLLPDIV_2 (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
9861 #define RCC_PLLCFGR_PLLPDIV_3 (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
9862 #define RCC_PLLCFGR_PLLPDIV_4 (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
9863
9864 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
9865 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
9866 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
9867 #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
9868 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
9869 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
9870 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
9871 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
9872 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
9873 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
9874 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
9875
9876 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
9877 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
9878 #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
9879 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
9880 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
9881 #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
9882
9883 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
9884 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
9885 #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
9886 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
9887 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
9888 #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
9889 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
9890 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
9891
9892 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
9893 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
9894 #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
9895 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
9896 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
9897 #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
9898 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
9899 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
9900
9901 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
9902 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
9903 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
9904 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
9905 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
9906 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
9907 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
9908 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
9909
9910 /******************** Bit definition for RCC_CIER register ******************/
9911 #define RCC_CIER_LSIRDYIE_Pos (0U)
9912 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
9913 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
9914 #define RCC_CIER_LSERDYIE_Pos (1U)
9915 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
9916 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
9917 #define RCC_CIER_MSIRDYIE_Pos (2U)
9918 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
9919 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
9920 #define RCC_CIER_HSIRDYIE_Pos (3U)
9921 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
9922 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
9923 #define RCC_CIER_HSERDYIE_Pos (4U)
9924 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
9925 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
9926 #define RCC_CIER_PLLRDYIE_Pos (5U)
9927 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
9928 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
9929 #define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
9930 #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
9931 #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
9932 #define RCC_CIER_LSECSSIE_Pos (9U)
9933 #define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
9934 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
9935 #define RCC_CIER_HSI48RDYIE_Pos (10U)
9936 #define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
9937 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
9938
9939 /******************** Bit definition for RCC_CIFR register ******************/
9940 #define RCC_CIFR_LSIRDYF_Pos (0U)
9941 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
9942 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
9943 #define RCC_CIFR_LSERDYF_Pos (1U)
9944 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
9945 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
9946 #define RCC_CIFR_MSIRDYF_Pos (2U)
9947 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
9948 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
9949 #define RCC_CIFR_HSIRDYF_Pos (3U)
9950 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
9951 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
9952 #define RCC_CIFR_HSERDYF_Pos (4U)
9953 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
9954 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
9955 #define RCC_CIFR_PLLRDYF_Pos (5U)
9956 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
9957 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
9958 #define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
9959 #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
9960 #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
9961 #define RCC_CIFR_CSSF_Pos (8U)
9962 #define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
9963 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
9964 #define RCC_CIFR_LSECSSF_Pos (9U)
9965 #define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
9966 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
9967 #define RCC_CIFR_HSI48RDYF_Pos (10U)
9968 #define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
9969 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
9970
9971 /******************** Bit definition for RCC_CICR register ******************/
9972 #define RCC_CICR_LSIRDYC_Pos (0U)
9973 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
9974 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
9975 #define RCC_CICR_LSERDYC_Pos (1U)
9976 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
9977 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
9978 #define RCC_CICR_MSIRDYC_Pos (2U)
9979 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
9980 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
9981 #define RCC_CICR_HSIRDYC_Pos (3U)
9982 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
9983 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
9984 #define RCC_CICR_HSERDYC_Pos (4U)
9985 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
9986 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
9987 #define RCC_CICR_PLLRDYC_Pos (5U)
9988 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
9989 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
9990 #define RCC_CICR_PLLSAI1RDYC_Pos (6U)
9991 #define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
9992 #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
9993 #define RCC_CICR_CSSC_Pos (8U)
9994 #define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
9995 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
9996 #define RCC_CICR_LSECSSC_Pos (9U)
9997 #define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
9998 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
9999 #define RCC_CICR_HSI48RDYC_Pos (10U)
10000 #define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
10001 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
10002
10003 /******************** Bit definition for RCC_AHB1RSTR register **************/
10004 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
10005 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
10006 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10007 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
10008 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
10009 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10010 #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
10011 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
10012 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
10013 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
10014 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
10015 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10016 #define RCC_AHB1RSTR_TSCRST_Pos (16U)
10017 #define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
10018 #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
10019
10020 /******************** Bit definition for RCC_AHB2RSTR register **************/
10021 #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
10022 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
10023 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
10024 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
10025 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
10026 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
10027 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
10028 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
10029 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
10030 #define RCC_AHB2RSTR_GPIODRST_Pos (3U)
10031 #define RCC_AHB2RSTR_GPIODRST_Msk (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
10032 #define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
10033 #define RCC_AHB2RSTR_GPIOERST_Pos (4U)
10034 #define RCC_AHB2RSTR_GPIOERST_Msk (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
10035 #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
10036 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
10037 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
10038 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
10039 #define RCC_AHB2RSTR_ADCRST_Pos (13U)
10040 #define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
10041 #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
10042 #define RCC_AHB2RSTR_RNGRST_Pos (18U)
10043 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
10044 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
10045
10046 /******************** Bit definition for RCC_AHB3RSTR register **************/
10047 #define RCC_AHB3RSTR_QSPIRST_Pos (8U)
10048 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
10049 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
10050
10051 /******************** Bit definition for RCC_APB1RSTR1 register **************/
10052 #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
10053 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
10054 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
10055 #define RCC_APB1RSTR1_TIM3RST_Pos (1U)
10056 #define RCC_APB1RSTR1_TIM3RST_Msk (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
10057 #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
10058 #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
10059 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
10060 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
10061 #define RCC_APB1RSTR1_SPI2RST_Pos (14U)
10062 #define RCC_APB1RSTR1_SPI2RST_Msk (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
10063 #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
10064 #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
10065 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
10066 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
10067 #define RCC_APB1RSTR1_USART2RST_Pos (17U)
10068 #define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
10069 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
10070 #define RCC_APB1RSTR1_USART3RST_Pos (18U)
10071 #define RCC_APB1RSTR1_USART3RST_Msk (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
10072 #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
10073 #define RCC_APB1RSTR1_UART4RST_Pos (19U)
10074 #define RCC_APB1RSTR1_UART4RST_Msk (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
10075 #define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
10076 #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
10077 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
10078 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
10079 #define RCC_APB1RSTR1_I2C2RST_Pos (22U)
10080 #define RCC_APB1RSTR1_I2C2RST_Msk (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
10081 #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
10082 #define RCC_APB1RSTR1_I2C3RST_Pos (23U)
10083 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
10084 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
10085 #define RCC_APB1RSTR1_CRSRST_Pos (24U)
10086 #define RCC_APB1RSTR1_CRSRST_Msk (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
10087 #define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
10088 #define RCC_APB1RSTR1_CAN1RST_Pos (25U)
10089 #define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
10090 #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
10091 #define RCC_APB1RSTR1_PWRRST_Pos (28U)
10092 #define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
10093 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
10094 #define RCC_APB1RSTR1_DAC1RST_Pos (29U)
10095 #define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
10096 #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
10097 #define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
10098 #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
10099 #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
10100 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
10101 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
10102 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
10103
10104 /******************** Bit definition for RCC_APB1RSTR2 register **************/
10105 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
10106 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
10107 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
10108 #define RCC_APB1RSTR2_I2C4RST_Pos (1U)
10109 #define RCC_APB1RSTR2_I2C4RST_Msk (0x1U << RCC_APB1RSTR2_I2C4RST_Pos) /*!< 0x00000002 */
10110 #define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
10111 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
10112 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
10113 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
10114
10115 /******************** Bit definition for RCC_APB2RSTR register **************/
10116 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
10117 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
10118 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10119 #define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
10120 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
10121 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
10122 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
10123 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
10124 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10125 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
10126 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
10127 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10128 #define RCC_APB2RSTR_USART1RST_Pos (14U)
10129 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
10130 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10131 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
10132 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
10133 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
10134 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
10135 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
10136 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
10137 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
10138 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
10139 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
10140 #define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
10141 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
10142 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
10143
10144 /******************** Bit definition for RCC_AHB1ENR register ***************/
10145 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
10146 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
10147 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
10148 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
10149 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
10150 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
10151 #define RCC_AHB1ENR_FLASHEN_Pos (8U)
10152 #define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
10153 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
10154 #define RCC_AHB1ENR_CRCEN_Pos (12U)
10155 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
10156 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
10157 #define RCC_AHB1ENR_TSCEN_Pos (16U)
10158 #define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
10159 #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
10160
10161 /******************** Bit definition for RCC_AHB2ENR register ***************/
10162 #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
10163 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
10164 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
10165 #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
10166 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
10167 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
10168 #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
10169 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
10170 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
10171 #define RCC_AHB2ENR_GPIODEN_Pos (3U)
10172 #define RCC_AHB2ENR_GPIODEN_Msk (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
10173 #define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
10174 #define RCC_AHB2ENR_GPIOEEN_Pos (4U)
10175 #define RCC_AHB2ENR_GPIOEEN_Msk (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
10176 #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
10177 #define RCC_AHB2ENR_GPIOHEN_Pos (7U)
10178 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
10179 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
10180 #define RCC_AHB2ENR_ADCEN_Pos (13U)
10181 #define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
10182 #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
10183 #define RCC_AHB2ENR_RNGEN_Pos (18U)
10184 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
10185 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
10186
10187 /******************** Bit definition for RCC_AHB3ENR register ***************/
10188 #define RCC_AHB3ENR_QSPIEN_Pos (8U)
10189 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
10190 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
10191
10192 /******************** Bit definition for RCC_APB1ENR1 register ***************/
10193 #define RCC_APB1ENR1_TIM2EN_Pos (0U)
10194 #define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
10195 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
10196 #define RCC_APB1ENR1_TIM3EN_Pos (1U)
10197 #define RCC_APB1ENR1_TIM3EN_Msk (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
10198 #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
10199 #define RCC_APB1ENR1_TIM6EN_Pos (4U)
10200 #define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
10201 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
10202 #define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
10203 #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
10204 #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
10205 #define RCC_APB1ENR1_WWDGEN_Pos (11U)
10206 #define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
10207 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
10208 #define RCC_APB1ENR1_SPI2EN_Pos (14U)
10209 #define RCC_APB1ENR1_SPI2EN_Msk (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
10210 #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
10211 #define RCC_APB1ENR1_SPI3EN_Pos (15U)
10212 #define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
10213 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
10214 #define RCC_APB1ENR1_USART2EN_Pos (17U)
10215 #define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
10216 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
10217 #define RCC_APB1ENR1_USART3EN_Pos (18U)
10218 #define RCC_APB1ENR1_USART3EN_Msk (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
10219 #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
10220 #define RCC_APB1ENR1_UART4EN_Pos (19U)
10221 #define RCC_APB1ENR1_UART4EN_Msk (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
10222 #define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
10223 #define RCC_APB1ENR1_I2C1EN_Pos (21U)
10224 #define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
10225 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
10226 #define RCC_APB1ENR1_I2C2EN_Pos (22U)
10227 #define RCC_APB1ENR1_I2C2EN_Msk (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
10228 #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
10229 #define RCC_APB1ENR1_I2C3EN_Pos (23U)
10230 #define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
10231 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
10232 #define RCC_APB1ENR1_CRSEN_Pos (24U)
10233 #define RCC_APB1ENR1_CRSEN_Msk (0x1U << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
10234 #define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
10235 #define RCC_APB1ENR1_CAN1EN_Pos (25U)
10236 #define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
10237 #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
10238 #define RCC_APB1ENR1_PWREN_Pos (28U)
10239 #define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
10240 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
10241 #define RCC_APB1ENR1_DAC1EN_Pos (29U)
10242 #define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
10243 #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
10244 #define RCC_APB1ENR1_OPAMPEN_Pos (30U)
10245 #define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
10246 #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
10247 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
10248 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
10249 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
10250
10251 /******************** Bit definition for RCC_APB1RSTR2 register **************/
10252 #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
10253 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
10254 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
10255 #define RCC_APB1ENR2_I2C4EN_Pos (1U)
10256 #define RCC_APB1ENR2_I2C4EN_Msk (0x1U << RCC_APB1ENR2_I2C4EN_Pos) /*!< 0x00000002 */
10257 #define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
10258 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
10259 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
10260 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
10261
10262 /******************** Bit definition for RCC_APB2ENR register ***************/
10263 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
10264 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
10265 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10266 #define RCC_APB2ENR_FWEN_Pos (7U)
10267 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
10268 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
10269 #define RCC_APB2ENR_SDMMC1EN_Pos (10U)
10270 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
10271 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
10272 #define RCC_APB2ENR_TIM1EN_Pos (11U)
10273 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
10274 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10275 #define RCC_APB2ENR_SPI1EN_Pos (12U)
10276 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
10277 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10278 #define RCC_APB2ENR_USART1EN_Pos (14U)
10279 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
10280 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10281 #define RCC_APB2ENR_TIM15EN_Pos (16U)
10282 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
10283 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
10284 #define RCC_APB2ENR_TIM16EN_Pos (17U)
10285 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
10286 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
10287 #define RCC_APB2ENR_SAI1EN_Pos (21U)
10288 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
10289 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
10290 #define RCC_APB2ENR_DFSDM1EN_Pos (24U)
10291 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
10292 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
10293
10294 /******************** Bit definition for RCC_AHB1SMENR register ***************/
10295 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
10296 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
10297 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
10298 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
10299 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
10300 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
10301 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
10302 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
10303 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
10304 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
10305 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
10306 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
10307 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
10308 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
10309 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
10310 #define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
10311 #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
10312 #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
10313
10314 /******************** Bit definition for RCC_AHB2SMENR register *************/
10315 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
10316 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
10317 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
10318 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
10319 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
10320 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
10321 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
10322 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
10323 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
10324 #define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
10325 #define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
10326 #define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
10327 #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
10328 #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
10329 #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
10330 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
10331 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
10332 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
10333 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
10334 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
10335 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
10336 #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
10337 #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
10338 #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
10339 #define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
10340 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
10341 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
10342
10343 /******************** Bit definition for RCC_AHB3SMENR register *************/
10344 #define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
10345 #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
10346 #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
10347
10348 /******************** Bit definition for RCC_APB1SMENR1 register *************/
10349 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
10350 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
10351 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
10352 #define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
10353 #define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
10354 #define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
10355 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
10356 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
10357 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
10358 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
10359 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
10360 #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
10361 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
10362 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
10363 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
10364 #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
10365 #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
10366 #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
10367 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
10368 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
10369 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
10370 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
10371 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
10372 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
10373 #define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
10374 #define RCC_APB1SMENR1_USART3SMEN_Msk (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
10375 #define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
10376 #define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
10377 #define RCC_APB1SMENR1_UART4SMEN_Msk (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
10378 #define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
10379 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
10380 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
10381 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
10382 #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
10383 #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
10384 #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
10385 #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
10386 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
10387 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
10388 #define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
10389 #define RCC_APB1SMENR1_CRSSMEN_Msk (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
10390 #define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
10391 #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
10392 #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
10393 #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
10394 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
10395 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
10396 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
10397 #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
10398 #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
10399 #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
10400 #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
10401 #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
10402 #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
10403 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
10404 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
10405 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
10406
10407 /******************** Bit definition for RCC_APB1SMENR2 register *************/
10408 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
10409 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
10410 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
10411 #define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
10412 #define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1U << RCC_APB1SMENR2_I2C4SMEN_Pos) /*!< 0x00000002 */
10413 #define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
10414 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
10415 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
10416 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
10417
10418 /******************** Bit definition for RCC_APB2SMENR register *************/
10419 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
10420 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
10421 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
10422 #define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
10423 #define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
10424 #define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
10425 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
10426 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
10427 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
10428 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
10429 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
10430 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
10431 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
10432 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
10433 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
10434 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
10435 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
10436 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
10437 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
10438 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
10439 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
10440 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
10441 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
10442 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
10443 #define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
10444 #define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
10445 #define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
10446
10447 /******************** Bit definition for RCC_CCIPR register ******************/
10448 #define RCC_CCIPR_USART1SEL_Pos (0U)
10449 #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
10450 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
10451 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
10452 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
10453
10454 #define RCC_CCIPR_USART2SEL_Pos (2U)
10455 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
10456 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
10457 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
10458 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
10459
10460 #define RCC_CCIPR_USART3SEL_Pos (4U)
10461 #define RCC_CCIPR_USART3SEL_Msk (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
10462 #define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
10463 #define RCC_CCIPR_USART3SEL_0 (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
10464 #define RCC_CCIPR_USART3SEL_1 (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
10465
10466 #define RCC_CCIPR_UART4SEL_Pos (6U)
10467 #define RCC_CCIPR_UART4SEL_Msk (0x3U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
10468 #define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
10469 #define RCC_CCIPR_UART4SEL_0 (0x1U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
10470 #define RCC_CCIPR_UART4SEL_1 (0x2U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
10471
10472 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
10473 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
10474 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
10475 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
10476 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
10477
10478 #define RCC_CCIPR_I2C1SEL_Pos (12U)
10479 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
10480 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
10481 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
10482 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
10483
10484 #define RCC_CCIPR_I2C2SEL_Pos (14U)
10485 #define RCC_CCIPR_I2C2SEL_Msk (0x3U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
10486 #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
10487 #define RCC_CCIPR_I2C2SEL_0 (0x1U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
10488 #define RCC_CCIPR_I2C2SEL_1 (0x2U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
10489
10490 #define RCC_CCIPR_I2C3SEL_Pos (16U)
10491 #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
10492 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
10493 #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
10494 #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
10495
10496 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
10497 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
10498 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
10499 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
10500 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
10501
10502 #define RCC_CCIPR_LPTIM2SEL_Pos (20U)
10503 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
10504 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
10505 #define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
10506 #define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
10507
10508 #define RCC_CCIPR_SAI1SEL_Pos (22U)
10509 #define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
10510 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
10511 #define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
10512 #define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
10513
10514 #define RCC_CCIPR_CLK48SEL_Pos (26U)
10515 #define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
10516 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
10517 #define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
10518 #define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
10519
10520 #define RCC_CCIPR_ADCSEL_Pos (28U)
10521 #define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
10522 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
10523 #define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
10524 #define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
10525
10526 #define RCC_CCIPR_DFSDM1SEL_Pos (31U)
10527 #define RCC_CCIPR_DFSDM1SEL_Msk (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
10528 #define RCC_CCIPR_DFSDM1SEL RCC_CCIPR_DFSDM1SEL_Msk
10529
10530 /******************** Bit definition for RCC_BDCR register ******************/
10531 #define RCC_BDCR_LSEON_Pos (0U)
10532 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
10533 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10534 #define RCC_BDCR_LSERDY_Pos (1U)
10535 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
10536 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10537 #define RCC_BDCR_LSEBYP_Pos (2U)
10538 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
10539 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10540
10541 #define RCC_BDCR_LSEDRV_Pos (3U)
10542 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
10543 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
10544 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
10545 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
10546
10547 #define RCC_BDCR_LSECSSON_Pos (5U)
10548 #define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
10549 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
10550 #define RCC_BDCR_LSECSSD_Pos (6U)
10551 #define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
10552 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
10553
10554 #define RCC_BDCR_RTCSEL_Pos (8U)
10555 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
10556 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10557 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
10558 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
10559
10560 #define RCC_BDCR_RTCEN_Pos (15U)
10561 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
10562 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10563 #define RCC_BDCR_BDRST_Pos (16U)
10564 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
10565 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10566 #define RCC_BDCR_LSCOEN_Pos (24U)
10567 #define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
10568 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
10569 #define RCC_BDCR_LSCOSEL_Pos (25U)
10570 #define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
10571 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
10572
10573 /******************** Bit definition for RCC_CSR register *******************/
10574 #define RCC_CSR_LSION_Pos (0U)
10575 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
10576 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
10577 #define RCC_CSR_LSIRDY_Pos (1U)
10578 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
10579 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10580
10581 #define RCC_CSR_MSISRANGE_Pos (8U)
10582 #define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
10583 #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
10584 #define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
10585 #define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
10586 #define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
10587 #define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
10588
10589 #define RCC_CSR_RMVF_Pos (23U)
10590 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
10591 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10592 #define RCC_CSR_FWRSTF_Pos (24U)
10593 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
10594 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
10595 #define RCC_CSR_OBLRSTF_Pos (25U)
10596 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
10597 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
10598 #define RCC_CSR_PINRSTF_Pos (26U)
10599 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
10600 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10601 #define RCC_CSR_BORRSTF_Pos (27U)
10602 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
10603 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10604 #define RCC_CSR_SFTRSTF_Pos (28U)
10605 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
10606 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10607 #define RCC_CSR_IWDGRSTF_Pos (29U)
10608 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
10609 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10610 #define RCC_CSR_WWDGRSTF_Pos (30U)
10611 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
10612 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10613 #define RCC_CSR_LPWRRSTF_Pos (31U)
10614 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
10615 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10616
10617 /******************** Bit definition for RCC_CRRCR register *****************/
10618 #define RCC_CRRCR_HSI48ON_Pos (0U)
10619 #define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
10620 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
10621 #define RCC_CRRCR_HSI48RDY_Pos (1U)
10622 #define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
10623 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
10624
10625 /*!< HSI48CAL configuration */
10626 #define RCC_CRRCR_HSI48CAL_Pos (15U)
10627 #define RCC_CRRCR_HSI48CAL_Msk (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00FF8000 */
10628 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
10629 #define RCC_CRRCR_HSI48CAL_0 (0x000U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
10630 #define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00010000 */
10631 #define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00020000 */
10632 #define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00040000 */
10633 #define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00080000 */
10634 #define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00100000 */
10635 #define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00200000 */
10636 #define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00400000 */
10637 #define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00800000 */
10638
10639 /******************** Bit definition for RCC_CCIPR2 register ******************/
10640 #define RCC_CCIPR2_I2C4SEL_Pos (0U)
10641 #define RCC_CCIPR2_I2C4SEL_Msk (0x3U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
10642 #define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
10643 #define RCC_CCIPR2_I2C4SEL_0 (0x1U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
10644 #define RCC_CCIPR2_I2C4SEL_1 (0x2U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
10645
10646 /******************************************************************************/
10647 /* */
10648 /* RNG */
10649 /* */
10650 /******************************************************************************/
10651 /******************** Bits definition for RNG_CR register *******************/
10652 #define RNG_CR_RNGEN_Pos (2U)
10653 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
10654 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10655 #define RNG_CR_IE_Pos (3U)
10656 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
10657 #define RNG_CR_IE RNG_CR_IE_Msk
10658
10659 /******************** Bits definition for RNG_SR register *******************/
10660 #define RNG_SR_DRDY_Pos (0U)
10661 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
10662 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
10663 #define RNG_SR_CECS_Pos (1U)
10664 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
10665 #define RNG_SR_CECS RNG_SR_CECS_Msk
10666 #define RNG_SR_SECS_Pos (2U)
10667 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
10668 #define RNG_SR_SECS RNG_SR_SECS_Msk
10669 #define RNG_SR_CEIS_Pos (5U)
10670 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
10671 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
10672 #define RNG_SR_SEIS_Pos (6U)
10673 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
10674 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
10675
10676 /******************************************************************************/
10677 /* */
10678 /* Real-Time Clock (RTC) */
10679 /* */
10680 /******************************************************************************/
10681 /*
10682 * @brief Specific device feature definitions
10683 */
10684 #define RTC_TAMPER1_SUPPORT
10685 #define RTC_TAMPER2_SUPPORT
10686 #define RTC_TAMPER3_SUPPORT
10687 #define RTC_WAKEUP_SUPPORT
10688 #define RTC_BACKUP_SUPPORT
10689
10690 /******************** Bits definition for RTC_TR register *******************/
10691 #define RTC_TR_PM_Pos (22U)
10692 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
10693 #define RTC_TR_PM RTC_TR_PM_Msk
10694 #define RTC_TR_HT_Pos (20U)
10695 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
10696 #define RTC_TR_HT RTC_TR_HT_Msk
10697 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
10698 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
10699 #define RTC_TR_HU_Pos (16U)
10700 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
10701 #define RTC_TR_HU RTC_TR_HU_Msk
10702 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
10703 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
10704 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
10705 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
10706 #define RTC_TR_MNT_Pos (12U)
10707 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
10708 #define RTC_TR_MNT RTC_TR_MNT_Msk
10709 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
10710 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
10711 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
10712 #define RTC_TR_MNU_Pos (8U)
10713 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
10714 #define RTC_TR_MNU RTC_TR_MNU_Msk
10715 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
10716 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
10717 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
10718 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
10719 #define RTC_TR_ST_Pos (4U)
10720 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
10721 #define RTC_TR_ST RTC_TR_ST_Msk
10722 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
10723 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
10724 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
10725 #define RTC_TR_SU_Pos (0U)
10726 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
10727 #define RTC_TR_SU RTC_TR_SU_Msk
10728 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
10729 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
10730 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
10731 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
10732
10733 /******************** Bits definition for RTC_DR register *******************/
10734 #define RTC_DR_YT_Pos (20U)
10735 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
10736 #define RTC_DR_YT RTC_DR_YT_Msk
10737 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
10738 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
10739 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
10740 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
10741 #define RTC_DR_YU_Pos (16U)
10742 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
10743 #define RTC_DR_YU RTC_DR_YU_Msk
10744 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
10745 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
10746 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
10747 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
10748 #define RTC_DR_WDU_Pos (13U)
10749 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
10750 #define RTC_DR_WDU RTC_DR_WDU_Msk
10751 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
10752 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
10753 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
10754 #define RTC_DR_MT_Pos (12U)
10755 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
10756 #define RTC_DR_MT RTC_DR_MT_Msk
10757 #define RTC_DR_MU_Pos (8U)
10758 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
10759 #define RTC_DR_MU RTC_DR_MU_Msk
10760 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
10761 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
10762 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
10763 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
10764 #define RTC_DR_DT_Pos (4U)
10765 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
10766 #define RTC_DR_DT RTC_DR_DT_Msk
10767 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
10768 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
10769 #define RTC_DR_DU_Pos (0U)
10770 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
10771 #define RTC_DR_DU RTC_DR_DU_Msk
10772 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
10773 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
10774 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
10775 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
10776
10777 /******************** Bits definition for RTC_CR register *******************/
10778 #define RTC_CR_ITSE_Pos (24U)
10779 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
10780 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
10781 #define RTC_CR_COE_Pos (23U)
10782 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
10783 #define RTC_CR_COE RTC_CR_COE_Msk
10784 #define RTC_CR_OSEL_Pos (21U)
10785 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
10786 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
10787 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
10788 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
10789 #define RTC_CR_POL_Pos (20U)
10790 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
10791 #define RTC_CR_POL RTC_CR_POL_Msk
10792 #define RTC_CR_COSEL_Pos (19U)
10793 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
10794 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
10795 #define RTC_CR_BCK_Pos (18U)
10796 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
10797 #define RTC_CR_BCK RTC_CR_BCK_Msk
10798 #define RTC_CR_SUB1H_Pos (17U)
10799 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
10800 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10801 #define RTC_CR_ADD1H_Pos (16U)
10802 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
10803 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10804 #define RTC_CR_TSIE_Pos (15U)
10805 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
10806 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
10807 #define RTC_CR_WUTIE_Pos (14U)
10808 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
10809 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10810 #define RTC_CR_ALRBIE_Pos (13U)
10811 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
10812 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10813 #define RTC_CR_ALRAIE_Pos (12U)
10814 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
10815 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10816 #define RTC_CR_TSE_Pos (11U)
10817 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
10818 #define RTC_CR_TSE RTC_CR_TSE_Msk
10819 #define RTC_CR_WUTE_Pos (10U)
10820 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
10821 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
10822 #define RTC_CR_ALRBE_Pos (9U)
10823 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
10824 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10825 #define RTC_CR_ALRAE_Pos (8U)
10826 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
10827 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10828 #define RTC_CR_FMT_Pos (6U)
10829 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
10830 #define RTC_CR_FMT RTC_CR_FMT_Msk
10831 #define RTC_CR_BYPSHAD_Pos (5U)
10832 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
10833 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10834 #define RTC_CR_REFCKON_Pos (4U)
10835 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
10836 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10837 #define RTC_CR_TSEDGE_Pos (3U)
10838 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
10839 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10840 #define RTC_CR_WUCKSEL_Pos (0U)
10841 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
10842 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10843 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
10844 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
10845 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
10846
10847 /******************** Bits definition for RTC_ISR register ******************/
10848 #define RTC_ISR_ITSF_Pos (17U)
10849 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
10850 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
10851 #define RTC_ISR_RECALPF_Pos (16U)
10852 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
10853 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10854 #define RTC_ISR_TAMP3F_Pos (15U)
10855 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
10856 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
10857 #define RTC_ISR_TAMP2F_Pos (14U)
10858 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
10859 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10860 #define RTC_ISR_TAMP1F_Pos (13U)
10861 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
10862 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10863 #define RTC_ISR_TSOVF_Pos (12U)
10864 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
10865 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10866 #define RTC_ISR_TSF_Pos (11U)
10867 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
10868 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
10869 #define RTC_ISR_WUTF_Pos (10U)
10870 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
10871 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10872 #define RTC_ISR_ALRBF_Pos (9U)
10873 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
10874 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10875 #define RTC_ISR_ALRAF_Pos (8U)
10876 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
10877 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10878 #define RTC_ISR_INIT_Pos (7U)
10879 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
10880 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
10881 #define RTC_ISR_INITF_Pos (6U)
10882 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
10883 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
10884 #define RTC_ISR_RSF_Pos (5U)
10885 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
10886 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
10887 #define RTC_ISR_INITS_Pos (4U)
10888 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
10889 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
10890 #define RTC_ISR_SHPF_Pos (3U)
10891 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
10892 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10893 #define RTC_ISR_WUTWF_Pos (2U)
10894 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
10895 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10896 #define RTC_ISR_ALRBWF_Pos (1U)
10897 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
10898 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10899 #define RTC_ISR_ALRAWF_Pos (0U)
10900 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
10901 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10902
10903 /******************** Bits definition for RTC_PRER register *****************/
10904 #define RTC_PRER_PREDIV_A_Pos (16U)
10905 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
10906 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10907 #define RTC_PRER_PREDIV_S_Pos (0U)
10908 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
10909 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10910
10911 /******************** Bits definition for RTC_WUTR register *****************/
10912 #define RTC_WUTR_WUT_Pos (0U)
10913 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
10914 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10915
10916 /******************** Bits definition for RTC_ALRMAR register ***************/
10917 #define RTC_ALRMAR_MSK4_Pos (31U)
10918 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
10919 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10920 #define RTC_ALRMAR_WDSEL_Pos (30U)
10921 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
10922 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10923 #define RTC_ALRMAR_DT_Pos (28U)
10924 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
10925 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10926 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
10927 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
10928 #define RTC_ALRMAR_DU_Pos (24U)
10929 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
10930 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10931 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
10932 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
10933 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
10934 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
10935 #define RTC_ALRMAR_MSK3_Pos (23U)
10936 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
10937 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10938 #define RTC_ALRMAR_PM_Pos (22U)
10939 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
10940 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10941 #define RTC_ALRMAR_HT_Pos (20U)
10942 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
10943 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10944 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
10945 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
10946 #define RTC_ALRMAR_HU_Pos (16U)
10947 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
10948 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10949 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
10950 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
10951 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
10952 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
10953 #define RTC_ALRMAR_MSK2_Pos (15U)
10954 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
10955 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10956 #define RTC_ALRMAR_MNT_Pos (12U)
10957 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
10958 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10959 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
10960 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
10961 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
10962 #define RTC_ALRMAR_MNU_Pos (8U)
10963 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
10964 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10965 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
10966 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
10967 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
10968 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
10969 #define RTC_ALRMAR_MSK1_Pos (7U)
10970 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
10971 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10972 #define RTC_ALRMAR_ST_Pos (4U)
10973 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
10974 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10975 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
10976 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
10977 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
10978 #define RTC_ALRMAR_SU_Pos (0U)
10979 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
10980 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10981 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
10982 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
10983 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
10984 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
10985
10986 /******************** Bits definition for RTC_ALRMBR register ***************/
10987 #define RTC_ALRMBR_MSK4_Pos (31U)
10988 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
10989 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10990 #define RTC_ALRMBR_WDSEL_Pos (30U)
10991 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
10992 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10993 #define RTC_ALRMBR_DT_Pos (28U)
10994 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
10995 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10996 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
10997 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
10998 #define RTC_ALRMBR_DU_Pos (24U)
10999 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
11000 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11001 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
11002 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
11003 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
11004 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
11005 #define RTC_ALRMBR_MSK3_Pos (23U)
11006 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
11007 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11008 #define RTC_ALRMBR_PM_Pos (22U)
11009 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
11010 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11011 #define RTC_ALRMBR_HT_Pos (20U)
11012 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
11013 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11014 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
11015 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
11016 #define RTC_ALRMBR_HU_Pos (16U)
11017 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
11018 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11019 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
11020 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
11021 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
11022 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
11023 #define RTC_ALRMBR_MSK2_Pos (15U)
11024 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
11025 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
11026 #define RTC_ALRMBR_MNT_Pos (12U)
11027 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
11028 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
11029 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
11030 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
11031 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
11032 #define RTC_ALRMBR_MNU_Pos (8U)
11033 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
11034 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
11035 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
11036 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
11037 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
11038 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
11039 #define RTC_ALRMBR_MSK1_Pos (7U)
11040 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
11041 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
11042 #define RTC_ALRMBR_ST_Pos (4U)
11043 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
11044 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
11045 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
11046 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
11047 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
11048 #define RTC_ALRMBR_SU_Pos (0U)
11049 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
11050 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
11051 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
11052 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
11053 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
11054 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
11055
11056 /******************** Bits definition for RTC_WPR register ******************/
11057 #define RTC_WPR_KEY_Pos (0U)
11058 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
11059 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
11060
11061 /******************** Bits definition for RTC_SSR register ******************/
11062 #define RTC_SSR_SS_Pos (0U)
11063 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
11064 #define RTC_SSR_SS RTC_SSR_SS_Msk
11065
11066 /******************** Bits definition for RTC_SHIFTR register ***************/
11067 #define RTC_SHIFTR_SUBFS_Pos (0U)
11068 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
11069 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11070 #define RTC_SHIFTR_ADD1S_Pos (31U)
11071 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
11072 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11073
11074 /******************** Bits definition for RTC_TSTR register *****************/
11075 #define RTC_TSTR_PM_Pos (22U)
11076 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
11077 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
11078 #define RTC_TSTR_HT_Pos (20U)
11079 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
11080 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
11081 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
11082 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
11083 #define RTC_TSTR_HU_Pos (16U)
11084 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
11085 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
11086 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
11087 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
11088 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
11089 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
11090 #define RTC_TSTR_MNT_Pos (12U)
11091 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
11092 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
11093 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
11094 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
11095 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
11096 #define RTC_TSTR_MNU_Pos (8U)
11097 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
11098 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
11099 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
11100 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
11101 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
11102 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
11103 #define RTC_TSTR_ST_Pos (4U)
11104 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
11105 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
11106 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
11107 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
11108 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
11109 #define RTC_TSTR_SU_Pos (0U)
11110 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
11111 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
11112 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
11113 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
11114 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
11115 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
11116
11117 /******************** Bits definition for RTC_TSDR register *****************/
11118 #define RTC_TSDR_WDU_Pos (13U)
11119 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
11120 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
11121 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
11122 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
11123 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
11124 #define RTC_TSDR_MT_Pos (12U)
11125 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
11126 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
11127 #define RTC_TSDR_MU_Pos (8U)
11128 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
11129 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
11130 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
11131 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
11132 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
11133 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
11134 #define RTC_TSDR_DT_Pos (4U)
11135 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
11136 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
11137 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
11138 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
11139 #define RTC_TSDR_DU_Pos (0U)
11140 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
11141 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
11142 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
11143 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
11144 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
11145 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
11146
11147 /******************** Bits definition for RTC_TSSSR register ****************/
11148 #define RTC_TSSSR_SS_Pos (0U)
11149 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
11150 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
11151
11152 /******************** Bits definition for RTC_CAL register *****************/
11153 #define RTC_CALR_CALP_Pos (15U)
11154 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
11155 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
11156 #define RTC_CALR_CALW8_Pos (14U)
11157 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
11158 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
11159 #define RTC_CALR_CALW16_Pos (13U)
11160 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
11161 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
11162 #define RTC_CALR_CALM_Pos (0U)
11163 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
11164 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
11165 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
11166 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
11167 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
11168 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
11169 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
11170 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
11171 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
11172 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
11173 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
11174
11175 /******************** Bits definition for RTC_TAMPCR register ***************/
11176 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
11177 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
11178 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
11179 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
11180 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
11181 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
11182 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
11183 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
11184 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
11185 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
11186 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
11187 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
11188 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
11189 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
11190 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
11191 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
11192 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
11193 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
11194 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
11195 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
11196 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
11197 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
11198 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
11199 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
11200 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
11201 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
11202 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
11203 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
11204 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
11205 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
11206 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
11207 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
11208 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
11209 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
11210 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
11211 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
11212 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
11213 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
11214 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
11215 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
11216 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
11217 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
11218 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
11219 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
11220 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
11221 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
11222 #define RTC_TAMPCR_TAMPTS_Pos (7U)
11223 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
11224 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
11225 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
11226 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
11227 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
11228 #define RTC_TAMPCR_TAMP3E_Pos (5U)
11229 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
11230 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
11231 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
11232 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
11233 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
11234 #define RTC_TAMPCR_TAMP2E_Pos (3U)
11235 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
11236 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
11237 #define RTC_TAMPCR_TAMPIE_Pos (2U)
11238 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
11239 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
11240 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
11241 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
11242 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
11243 #define RTC_TAMPCR_TAMP1E_Pos (0U)
11244 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
11245 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
11246
11247 /******************** Bits definition for RTC_ALRMASSR register *************/
11248 #define RTC_ALRMASSR_MASKSS_Pos (24U)
11249 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
11250 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
11251 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
11252 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
11253 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
11254 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
11255 #define RTC_ALRMASSR_SS_Pos (0U)
11256 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
11257 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
11258
11259 /******************** Bits definition for RTC_ALRMBSSR register *************/
11260 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
11261 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
11262 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
11263 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
11264 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
11265 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
11266 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
11267 #define RTC_ALRMBSSR_SS_Pos (0U)
11268 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
11269 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
11270
11271 /******************** Bits definition for RTC_0R register *******************/
11272 #define RTC_OR_OUT_RMP_Pos (1U)
11273 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
11274 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
11275 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
11276 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
11277 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
11278
11279
11280 /******************** Bits definition for RTC_BKP0R register ****************/
11281 #define RTC_BKP0R_Pos (0U)
11282 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
11283 #define RTC_BKP0R RTC_BKP0R_Msk
11284
11285 /******************** Bits definition for RTC_BKP1R register ****************/
11286 #define RTC_BKP1R_Pos (0U)
11287 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
11288 #define RTC_BKP1R RTC_BKP1R_Msk
11289
11290 /******************** Bits definition for RTC_BKP2R register ****************/
11291 #define RTC_BKP2R_Pos (0U)
11292 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
11293 #define RTC_BKP2R RTC_BKP2R_Msk
11294
11295 /******************** Bits definition for RTC_BKP3R register ****************/
11296 #define RTC_BKP3R_Pos (0U)
11297 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
11298 #define RTC_BKP3R RTC_BKP3R_Msk
11299
11300 /******************** Bits definition for RTC_BKP4R register ****************/
11301 #define RTC_BKP4R_Pos (0U)
11302 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
11303 #define RTC_BKP4R RTC_BKP4R_Msk
11304
11305 /******************** Bits definition for RTC_BKP5R register ****************/
11306 #define RTC_BKP5R_Pos (0U)
11307 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
11308 #define RTC_BKP5R RTC_BKP5R_Msk
11309
11310 /******************** Bits definition for RTC_BKP6R register ****************/
11311 #define RTC_BKP6R_Pos (0U)
11312 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
11313 #define RTC_BKP6R RTC_BKP6R_Msk
11314
11315 /******************** Bits definition for RTC_BKP7R register ****************/
11316 #define RTC_BKP7R_Pos (0U)
11317 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
11318 #define RTC_BKP7R RTC_BKP7R_Msk
11319
11320 /******************** Bits definition for RTC_BKP8R register ****************/
11321 #define RTC_BKP8R_Pos (0U)
11322 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
11323 #define RTC_BKP8R RTC_BKP8R_Msk
11324
11325 /******************** Bits definition for RTC_BKP9R register ****************/
11326 #define RTC_BKP9R_Pos (0U)
11327 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
11328 #define RTC_BKP9R RTC_BKP9R_Msk
11329
11330 /******************** Bits definition for RTC_BKP10R register ***************/
11331 #define RTC_BKP10R_Pos (0U)
11332 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
11333 #define RTC_BKP10R RTC_BKP10R_Msk
11334
11335 /******************** Bits definition for RTC_BKP11R register ***************/
11336 #define RTC_BKP11R_Pos (0U)
11337 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
11338 #define RTC_BKP11R RTC_BKP11R_Msk
11339
11340 /******************** Bits definition for RTC_BKP12R register ***************/
11341 #define RTC_BKP12R_Pos (0U)
11342 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
11343 #define RTC_BKP12R RTC_BKP12R_Msk
11344
11345 /******************** Bits definition for RTC_BKP13R register ***************/
11346 #define RTC_BKP13R_Pos (0U)
11347 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
11348 #define RTC_BKP13R RTC_BKP13R_Msk
11349
11350 /******************** Bits definition for RTC_BKP14R register ***************/
11351 #define RTC_BKP14R_Pos (0U)
11352 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
11353 #define RTC_BKP14R RTC_BKP14R_Msk
11354
11355 /******************** Bits definition for RTC_BKP15R register ***************/
11356 #define RTC_BKP15R_Pos (0U)
11357 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
11358 #define RTC_BKP15R RTC_BKP15R_Msk
11359
11360 /******************** Bits definition for RTC_BKP16R register ***************/
11361 #define RTC_BKP16R_Pos (0U)
11362 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
11363 #define RTC_BKP16R RTC_BKP16R_Msk
11364
11365 /******************** Bits definition for RTC_BKP17R register ***************/
11366 #define RTC_BKP17R_Pos (0U)
11367 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
11368 #define RTC_BKP17R RTC_BKP17R_Msk
11369
11370 /******************** Bits definition for RTC_BKP18R register ***************/
11371 #define RTC_BKP18R_Pos (0U)
11372 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
11373 #define RTC_BKP18R RTC_BKP18R_Msk
11374
11375 /******************** Bits definition for RTC_BKP19R register ***************/
11376 #define RTC_BKP19R_Pos (0U)
11377 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
11378 #define RTC_BKP19R RTC_BKP19R_Msk
11379
11380 /******************** Bits definition for RTC_BKP20R register ***************/
11381 #define RTC_BKP20R_Pos (0U)
11382 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
11383 #define RTC_BKP20R RTC_BKP20R_Msk
11384
11385 /******************** Bits definition for RTC_BKP21R register ***************/
11386 #define RTC_BKP21R_Pos (0U)
11387 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
11388 #define RTC_BKP21R RTC_BKP21R_Msk
11389
11390 /******************** Bits definition for RTC_BKP22R register ***************/
11391 #define RTC_BKP22R_Pos (0U)
11392 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
11393 #define RTC_BKP22R RTC_BKP22R_Msk
11394
11395 /******************** Bits definition for RTC_BKP23R register ***************/
11396 #define RTC_BKP23R_Pos (0U)
11397 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
11398 #define RTC_BKP23R RTC_BKP23R_Msk
11399
11400 /******************** Bits definition for RTC_BKP24R register ***************/
11401 #define RTC_BKP24R_Pos (0U)
11402 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
11403 #define RTC_BKP24R RTC_BKP24R_Msk
11404
11405 /******************** Bits definition for RTC_BKP25R register ***************/
11406 #define RTC_BKP25R_Pos (0U)
11407 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
11408 #define RTC_BKP25R RTC_BKP25R_Msk
11409
11410 /******************** Bits definition for RTC_BKP26R register ***************/
11411 #define RTC_BKP26R_Pos (0U)
11412 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
11413 #define RTC_BKP26R RTC_BKP26R_Msk
11414
11415 /******************** Bits definition for RTC_BKP27R register ***************/
11416 #define RTC_BKP27R_Pos (0U)
11417 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
11418 #define RTC_BKP27R RTC_BKP27R_Msk
11419
11420 /******************** Bits definition for RTC_BKP28R register ***************/
11421 #define RTC_BKP28R_Pos (0U)
11422 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
11423 #define RTC_BKP28R RTC_BKP28R_Msk
11424
11425 /******************** Bits definition for RTC_BKP29R register ***************/
11426 #define RTC_BKP29R_Pos (0U)
11427 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
11428 #define RTC_BKP29R RTC_BKP29R_Msk
11429
11430 /******************** Bits definition for RTC_BKP30R register ***************/
11431 #define RTC_BKP30R_Pos (0U)
11432 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
11433 #define RTC_BKP30R RTC_BKP30R_Msk
11434
11435 /******************** Bits definition for RTC_BKP31R register ***************/
11436 #define RTC_BKP31R_Pos (0U)
11437 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
11438 #define RTC_BKP31R RTC_BKP31R_Msk
11439
11440 /******************** Number of backup registers ******************************/
11441 #define RTC_BKP_NUMBER 32U
11442
11443 /******************************************************************************/
11444 /* */
11445 /* Serial Audio Interface */
11446 /* */
11447 /******************************************************************************/
11448 /******************** Bit definition for SAI_GCR register *******************/
11449 #define SAI_GCR_SYNCIN_Pos (0U)
11450 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
11451 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
11452 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
11453 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
11454
11455 #define SAI_GCR_SYNCOUT_Pos (4U)
11456 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
11457 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
11458 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
11459 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
11460
11461 /******************* Bit definition for SAI_xCR1 register *******************/
11462 #define SAI_xCR1_MODE_Pos (0U)
11463 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
11464 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
11465 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
11466 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
11467
11468 #define SAI_xCR1_PRTCFG_Pos (2U)
11469 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
11470 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
11471 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
11472 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
11473
11474 #define SAI_xCR1_DS_Pos (5U)
11475 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
11476 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
11477 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
11478 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
11479 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
11480
11481 #define SAI_xCR1_LSBFIRST_Pos (8U)
11482 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
11483 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
11484 #define SAI_xCR1_CKSTR_Pos (9U)
11485 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
11486 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
11487
11488 #define SAI_xCR1_SYNCEN_Pos (10U)
11489 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
11490 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
11491 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
11492 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
11493
11494 #define SAI_xCR1_MONO_Pos (12U)
11495 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
11496 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
11497 #define SAI_xCR1_OUTDRIV_Pos (13U)
11498 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
11499 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
11500 #define SAI_xCR1_SAIEN_Pos (16U)
11501 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
11502 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
11503 #define SAI_xCR1_DMAEN_Pos (17U)
11504 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
11505 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
11506 #define SAI_xCR1_NODIV_Pos (19U)
11507 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
11508 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
11509
11510 #define SAI_xCR1_MCKDIV_Pos (20U)
11511 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
11512 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
11513 #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
11514 #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
11515 #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
11516 #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
11517
11518 /******************* Bit definition for SAI_xCR2 register *******************/
11519 #define SAI_xCR2_FTH_Pos (0U)
11520 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
11521 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
11522 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
11523 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
11524 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
11525
11526 #define SAI_xCR2_FFLUSH_Pos (3U)
11527 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
11528 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
11529 #define SAI_xCR2_TRIS_Pos (4U)
11530 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
11531 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
11532 #define SAI_xCR2_MUTE_Pos (5U)
11533 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
11534 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
11535 #define SAI_xCR2_MUTEVAL_Pos (6U)
11536 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
11537 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
11538
11539
11540 #define SAI_xCR2_MUTECNT_Pos (7U)
11541 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
11542 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
11543 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
11544 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
11545 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
11546 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
11547 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
11548 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
11549
11550 #define SAI_xCR2_CPL_Pos (13U)
11551 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
11552 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
11553 #define SAI_xCR2_COMP_Pos (14U)
11554 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
11555 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
11556 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
11557 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
11558
11559
11560 /****************** Bit definition for SAI_xFRCR register *******************/
11561 #define SAI_xFRCR_FRL_Pos (0U)
11562 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
11563 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
11564 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
11565 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
11566 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
11567 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
11568 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
11569 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
11570 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
11571 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
11572
11573 #define SAI_xFRCR_FSALL_Pos (8U)
11574 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
11575 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
11576 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
11577 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
11578 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
11579 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
11580 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
11581 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
11582 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
11583
11584 #define SAI_xFRCR_FSDEF_Pos (16U)
11585 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
11586 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
11587 #define SAI_xFRCR_FSPOL_Pos (17U)
11588 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
11589 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
11590 #define SAI_xFRCR_FSOFF_Pos (18U)
11591 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
11592 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
11593
11594 /****************** Bit definition for SAI_xSLOTR register *******************/
11595 #define SAI_xSLOTR_FBOFF_Pos (0U)
11596 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
11597 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
11598 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
11599 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
11600 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
11601 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
11602 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
11603
11604 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
11605 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
11606 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
11607 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
11608 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
11609
11610 #define SAI_xSLOTR_NBSLOT_Pos (8U)
11611 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
11612 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
11613 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
11614 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
11615 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
11616 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
11617
11618 #define SAI_xSLOTR_SLOTEN_Pos (16U)
11619 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
11620 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
11621
11622 /******************* Bit definition for SAI_xIMR register *******************/
11623 #define SAI_xIMR_OVRUDRIE_Pos (0U)
11624 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
11625 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
11626 #define SAI_xIMR_MUTEDETIE_Pos (1U)
11627 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
11628 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
11629 #define SAI_xIMR_WCKCFGIE_Pos (2U)
11630 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
11631 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
11632 #define SAI_xIMR_FREQIE_Pos (3U)
11633 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
11634 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
11635 #define SAI_xIMR_CNRDYIE_Pos (4U)
11636 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
11637 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
11638 #define SAI_xIMR_AFSDETIE_Pos (5U)
11639 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
11640 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
11641 #define SAI_xIMR_LFSDETIE_Pos (6U)
11642 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
11643 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
11644
11645 /******************** Bit definition for SAI_xSR register *******************/
11646 #define SAI_xSR_OVRUDR_Pos (0U)
11647 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
11648 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
11649 #define SAI_xSR_MUTEDET_Pos (1U)
11650 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
11651 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
11652 #define SAI_xSR_WCKCFG_Pos (2U)
11653 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
11654 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
11655 #define SAI_xSR_FREQ_Pos (3U)
11656 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
11657 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
11658 #define SAI_xSR_CNRDY_Pos (4U)
11659 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
11660 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
11661 #define SAI_xSR_AFSDET_Pos (5U)
11662 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
11663 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
11664 #define SAI_xSR_LFSDET_Pos (6U)
11665 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
11666 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
11667
11668 #define SAI_xSR_FLVL_Pos (16U)
11669 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
11670 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
11671 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
11672 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
11673 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
11674
11675 /****************** Bit definition for SAI_xCLRFR register ******************/
11676 #define SAI_xCLRFR_COVRUDR_Pos (0U)
11677 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
11678 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
11679 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
11680 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
11681 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
11682 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
11683 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
11684 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
11685 #define SAI_xCLRFR_CFREQ_Pos (3U)
11686 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
11687 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
11688 #define SAI_xCLRFR_CCNRDY_Pos (4U)
11689 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
11690 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
11691 #define SAI_xCLRFR_CAFSDET_Pos (5U)
11692 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
11693 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
11694 #define SAI_xCLRFR_CLFSDET_Pos (6U)
11695 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
11696 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
11697
11698 /****************** Bit definition for SAI_xDR register ******************/
11699 #define SAI_xDR_DATA_Pos (0U)
11700 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
11701 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
11702
11703 /******************************************************************************/
11704 /* */
11705 /* SDMMC Interface */
11706 /* */
11707 /******************************************************************************/
11708 /****************** Bit definition for SDMMC_POWER register ******************/
11709 #define SDMMC_POWER_PWRCTRL_Pos (0U)
11710 #define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
11711 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
11712 #define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
11713 #define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
11714
11715 /****************** Bit definition for SDMMC_CLKCR register ******************/
11716 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
11717 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
11718 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
11719 #define SDMMC_CLKCR_CLKEN_Pos (8U)
11720 #define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
11721 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
11722 #define SDMMC_CLKCR_PWRSAV_Pos (9U)
11723 #define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
11724 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
11725 #define SDMMC_CLKCR_BYPASS_Pos (10U)
11726 #define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
11727 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
11728 #define SDMMC_CLKCR_WIDBUS_Pos (11U)
11729 #define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
11730 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
11731 #define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */
11732 #define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */
11733 #define SDMMC_CLKCR_NEGEDGE_Pos (13U)
11734 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
11735 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
11736 #define SDMMC_CLKCR_HWFC_EN_Pos (14U)
11737 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
11738 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
11739
11740 /******************* Bit definition for SDMMC_ARG register *******************/
11741 #define SDMMC_ARG_CMDARG_Pos (0U)
11742 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
11743 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
11744
11745 /******************* Bit definition for SDMMC_CMD register *******************/
11746 #define SDMMC_CMD_CMDINDEX_Pos (0U)
11747 #define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
11748 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
11749 #define SDMMC_CMD_WAITRESP_Pos (6U)
11750 #define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
11751 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
11752 #define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000040 */
11753 #define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000080 */
11754 #define SDMMC_CMD_WAITINT_Pos (8U)
11755 #define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
11756 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
11757 #define SDMMC_CMD_WAITPEND_Pos (9U)
11758 #define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
11759 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
11760 #define SDMMC_CMD_CPSMEN_Pos (10U)
11761 #define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
11762 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
11763 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
11764 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
11765 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
11766
11767 /***************** Bit definition for SDMMC_RESPCMD register *****************/
11768 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
11769 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
11770 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
11771
11772 /****************** Bit definition for SDMMC_RESP0 register ******************/
11773 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
11774 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
11775 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
11776
11777 /****************** Bit definition for SDMMC_RESP1 register ******************/
11778 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
11779 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
11780 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
11781
11782 /****************** Bit definition for SDMMC_RESP2 register ******************/
11783 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
11784 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
11785 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
11786
11787 /****************** Bit definition for SDMMC_RESP3 register ******************/
11788 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
11789 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
11790 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
11791
11792 /****************** Bit definition for SDMMC_RESP4 register ******************/
11793 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
11794 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
11795 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
11796
11797 /****************** Bit definition for SDMMC_DTIMER register *****************/
11798 #define SDMMC_DTIMER_DATATIME_Pos (0U)
11799 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
11800 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
11801
11802 /****************** Bit definition for SDMMC_DLEN register *******************/
11803 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
11804 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
11805 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
11806
11807 /****************** Bit definition for SDMMC_DCTRL register ******************/
11808 #define SDMMC_DCTRL_DTEN_Pos (0U)
11809 #define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
11810 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
11811 #define SDMMC_DCTRL_DTDIR_Pos (1U)
11812 #define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
11813 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
11814 #define SDMMC_DCTRL_DTMODE_Pos (2U)
11815 #define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
11816 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
11817 #define SDMMC_DCTRL_DMAEN_Pos (3U)
11818 #define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
11819 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
11820 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
11821 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
11822 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
11823 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
11824 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
11825 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
11826 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
11827 #define SDMMC_DCTRL_RWSTART_Pos (8U)
11828 #define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
11829 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
11830 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
11831 #define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
11832 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
11833 #define SDMMC_DCTRL_RWMOD_Pos (10U)
11834 #define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
11835 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
11836 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
11837 #define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
11838 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
11839
11840 /****************** Bit definition for SDMMC_DCOUNT register *****************/
11841 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
11842 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
11843 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
11844
11845 /****************** Bit definition for SDMMC_STA register ********************/
11846 #define SDMMC_STA_CCRCFAIL_Pos (0U)
11847 #define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
11848 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
11849 #define SDMMC_STA_DCRCFAIL_Pos (1U)
11850 #define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
11851 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
11852 #define SDMMC_STA_CTIMEOUT_Pos (2U)
11853 #define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
11854 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
11855 #define SDMMC_STA_DTIMEOUT_Pos (3U)
11856 #define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
11857 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
11858 #define SDMMC_STA_TXUNDERR_Pos (4U)
11859 #define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
11860 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
11861 #define SDMMC_STA_RXOVERR_Pos (5U)
11862 #define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
11863 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
11864 #define SDMMC_STA_CMDREND_Pos (6U)
11865 #define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
11866 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
11867 #define SDMMC_STA_CMDSENT_Pos (7U)
11868 #define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
11869 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
11870 #define SDMMC_STA_DATAEND_Pos (8U)
11871 #define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
11872 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
11873 #define SDMMC_STA_STBITERR_Pos (9U)
11874 #define SDMMC_STA_STBITERR_Msk (0x1U << SDMMC_STA_STBITERR_Pos) /*!< 0x00000200 */
11875 #define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
11876 #define SDMMC_STA_DBCKEND_Pos (10U)
11877 #define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
11878 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
11879 #define SDMMC_STA_CMDACT_Pos (11U)
11880 #define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
11881 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
11882 #define SDMMC_STA_TXACT_Pos (12U)
11883 #define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
11884 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
11885 #define SDMMC_STA_RXACT_Pos (13U)
11886 #define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
11887 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
11888 #define SDMMC_STA_TXFIFOHE_Pos (14U)
11889 #define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
11890 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
11891 #define SDMMC_STA_RXFIFOHF_Pos (15U)
11892 #define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
11893 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
11894 #define SDMMC_STA_TXFIFOF_Pos (16U)
11895 #define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
11896 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
11897 #define SDMMC_STA_RXFIFOF_Pos (17U)
11898 #define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
11899 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
11900 #define SDMMC_STA_TXFIFOE_Pos (18U)
11901 #define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
11902 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
11903 #define SDMMC_STA_RXFIFOE_Pos (19U)
11904 #define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
11905 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
11906 #define SDMMC_STA_TXDAVL_Pos (20U)
11907 #define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
11908 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
11909 #define SDMMC_STA_RXDAVL_Pos (21U)
11910 #define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
11911 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
11912 #define SDMMC_STA_SDIOIT_Pos (22U)
11913 #define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
11914 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
11915
11916 /******************* Bit definition for SDMMC_ICR register *******************/
11917 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
11918 #define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
11919 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
11920 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
11921 #define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11922 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
11923 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
11924 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
11925 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
11926 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
11927 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
11928 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
11929 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
11930 #define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
11931 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
11932 #define SDMMC_ICR_RXOVERRC_Pos (5U)
11933 #define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
11934 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
11935 #define SDMMC_ICR_CMDRENDC_Pos (6U)
11936 #define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
11937 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
11938 #define SDMMC_ICR_CMDSENTC_Pos (7U)
11939 #define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
11940 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
11941 #define SDMMC_ICR_DATAENDC_Pos (8U)
11942 #define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
11943 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
11944 #define SDMMC_ICR_STBITERRC_Pos (9U)
11945 #define SDMMC_ICR_STBITERRC_Msk (0x1U << SDMMC_ICR_STBITERRC_Pos) /*!< 0x00000200 */
11946 #define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
11947 #define SDMMC_ICR_DBCKENDC_Pos (10U)
11948 #define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
11949 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
11950 #define SDMMC_ICR_SDIOITC_Pos (22U)
11951 #define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
11952 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
11953
11954 /****************** Bit definition for SDMMC_MASK register *******************/
11955 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
11956 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
11957 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
11958 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
11959 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
11960 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
11961 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
11962 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
11963 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
11964 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
11965 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
11966 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
11967 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
11968 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
11969 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
11970 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
11971 #define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
11972 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
11973 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
11974 #define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
11975 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
11976 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
11977 #define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
11978 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
11979 #define SDMMC_MASK_DATAENDIE_Pos (8U)
11980 #define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
11981 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
11982 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
11983 #define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
11984 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
11985 #define SDMMC_MASK_CMDACTIE_Pos (11U)
11986 #define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
11987 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
11988 #define SDMMC_MASK_TXACTIE_Pos (12U)
11989 #define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
11990 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
11991 #define SDMMC_MASK_RXACTIE_Pos (13U)
11992 #define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
11993 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
11994 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
11995 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
11996 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
11997 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
11998 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
11999 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
12000 #define SDMMC_MASK_TXFIFOFIE_Pos (16U)
12001 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
12002 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
12003 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
12004 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
12005 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
12006 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
12007 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
12008 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
12009 #define SDMMC_MASK_RXFIFOEIE_Pos (19U)
12010 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
12011 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
12012 #define SDMMC_MASK_TXDAVLIE_Pos (20U)
12013 #define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
12014 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
12015 #define SDMMC_MASK_RXDAVLIE_Pos (21U)
12016 #define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
12017 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
12018 #define SDMMC_MASK_SDIOITIE_Pos (22U)
12019 #define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
12020 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
12021
12022 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
12023 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
12024 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
12025 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
12026
12027 /****************** Bit definition for SDMMC_FIFO register *******************/
12028 #define SDMMC_FIFO_FIFODATA_Pos (0U)
12029 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
12030 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
12031
12032 /******************************************************************************/
12033 /* */
12034 /* Serial Peripheral Interface (SPI) */
12035 /* */
12036 /******************************************************************************/
12037 /******************* Bit definition for SPI_CR1 register ********************/
12038 #define SPI_CR1_CPHA_Pos (0U)
12039 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
12040 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
12041 #define SPI_CR1_CPOL_Pos (1U)
12042 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
12043 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
12044 #define SPI_CR1_MSTR_Pos (2U)
12045 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
12046 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
12047
12048 #define SPI_CR1_BR_Pos (3U)
12049 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
12050 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
12051 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
12052 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
12053 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
12054
12055 #define SPI_CR1_SPE_Pos (6U)
12056 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
12057 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
12058 #define SPI_CR1_LSBFIRST_Pos (7U)
12059 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
12060 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
12061 #define SPI_CR1_SSI_Pos (8U)
12062 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
12063 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
12064 #define SPI_CR1_SSM_Pos (9U)
12065 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
12066 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
12067 #define SPI_CR1_RXONLY_Pos (10U)
12068 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
12069 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
12070 #define SPI_CR1_CRCL_Pos (11U)
12071 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
12072 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
12073 #define SPI_CR1_CRCNEXT_Pos (12U)
12074 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
12075 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
12076 #define SPI_CR1_CRCEN_Pos (13U)
12077 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
12078 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
12079 #define SPI_CR1_BIDIOE_Pos (14U)
12080 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
12081 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
12082 #define SPI_CR1_BIDIMODE_Pos (15U)
12083 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
12084 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
12085
12086 /******************* Bit definition for SPI_CR2 register ********************/
12087 #define SPI_CR2_RXDMAEN_Pos (0U)
12088 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
12089 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
12090 #define SPI_CR2_TXDMAEN_Pos (1U)
12091 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
12092 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
12093 #define SPI_CR2_SSOE_Pos (2U)
12094 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
12095 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
12096 #define SPI_CR2_NSSP_Pos (3U)
12097 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
12098 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
12099 #define SPI_CR2_FRF_Pos (4U)
12100 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
12101 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
12102 #define SPI_CR2_ERRIE_Pos (5U)
12103 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
12104 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
12105 #define SPI_CR2_RXNEIE_Pos (6U)
12106 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
12107 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
12108 #define SPI_CR2_TXEIE_Pos (7U)
12109 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
12110 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
12111 #define SPI_CR2_DS_Pos (8U)
12112 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
12113 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
12114 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
12115 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
12116 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
12117 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
12118 #define SPI_CR2_FRXTH_Pos (12U)
12119 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
12120 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
12121 #define SPI_CR2_LDMARX_Pos (13U)
12122 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
12123 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
12124 #define SPI_CR2_LDMATX_Pos (14U)
12125 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
12126 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
12127
12128 /******************** Bit definition for SPI_SR register ********************/
12129 #define SPI_SR_RXNE_Pos (0U)
12130 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
12131 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
12132 #define SPI_SR_TXE_Pos (1U)
12133 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
12134 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
12135 #define SPI_SR_CHSIDE_Pos (2U)
12136 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
12137 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
12138 #define SPI_SR_UDR_Pos (3U)
12139 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
12140 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
12141 #define SPI_SR_CRCERR_Pos (4U)
12142 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
12143 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
12144 #define SPI_SR_MODF_Pos (5U)
12145 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
12146 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
12147 #define SPI_SR_OVR_Pos (6U)
12148 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
12149 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
12150 #define SPI_SR_BSY_Pos (7U)
12151 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
12152 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
12153 #define SPI_SR_FRE_Pos (8U)
12154 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
12155 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
12156 #define SPI_SR_FRLVL_Pos (9U)
12157 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
12158 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
12159 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
12160 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
12161 #define SPI_SR_FTLVL_Pos (11U)
12162 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
12163 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
12164 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
12165 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
12166
12167 /******************** Bit definition for SPI_DR register ********************/
12168 #define SPI_DR_DR_Pos (0U)
12169 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
12170 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
12171
12172 /******************* Bit definition for SPI_CRCPR register ******************/
12173 #define SPI_CRCPR_CRCPOLY_Pos (0U)
12174 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
12175 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
12176
12177 /****************** Bit definition for SPI_RXCRCR register ******************/
12178 #define SPI_RXCRCR_RXCRC_Pos (0U)
12179 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
12180 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
12181
12182 /****************** Bit definition for SPI_TXCRCR register ******************/
12183 #define SPI_TXCRCR_TXCRC_Pos (0U)
12184 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
12185 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
12186
12187 /******************************************************************************/
12188 /* */
12189 /* QUADSPI */
12190 /* */
12191 /******************************************************************************/
12192 /***************** Bit definition for QUADSPI_CR register *******************/
12193 #define QUADSPI_CR_EN_Pos (0U)
12194 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
12195 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
12196 #define QUADSPI_CR_ABORT_Pos (1U)
12197 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
12198 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
12199 #define QUADSPI_CR_DMAEN_Pos (2U)
12200 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
12201 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
12202 #define QUADSPI_CR_TCEN_Pos (3U)
12203 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
12204 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
12205 #define QUADSPI_CR_SSHIFT_Pos (4U)
12206 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
12207 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
12208 #define QUADSPI_CR_DFM_Pos (6U)
12209 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
12210 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
12211 #define QUADSPI_CR_FSEL_Pos (7U)
12212 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
12213 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
12214 #define QUADSPI_CR_FTHRES_Pos (8U)
12215 #define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
12216 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
12217 #define QUADSPI_CR_TEIE_Pos (16U)
12218 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
12219 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
12220 #define QUADSPI_CR_TCIE_Pos (17U)
12221 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
12222 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
12223 #define QUADSPI_CR_FTIE_Pos (18U)
12224 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
12225 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
12226 #define QUADSPI_CR_SMIE_Pos (19U)
12227 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
12228 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
12229 #define QUADSPI_CR_TOIE_Pos (20U)
12230 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
12231 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
12232 #define QUADSPI_CR_APMS_Pos (22U)
12233 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
12234 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
12235 #define QUADSPI_CR_PMM_Pos (23U)
12236 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
12237 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
12238 #define QUADSPI_CR_PRESCALER_Pos (24U)
12239 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
12240 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
12241
12242 /***************** Bit definition for QUADSPI_DCR register ******************/
12243 #define QUADSPI_DCR_CKMODE_Pos (0U)
12244 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
12245 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
12246 #define QUADSPI_DCR_CSHT_Pos (8U)
12247 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
12248 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
12249 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
12250 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
12251 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
12252 #define QUADSPI_DCR_FSIZE_Pos (16U)
12253 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
12254 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
12255
12256 /****************** Bit definition for QUADSPI_SR register *******************/
12257 #define QUADSPI_SR_TEF_Pos (0U)
12258 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
12259 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
12260 #define QUADSPI_SR_TCF_Pos (1U)
12261 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
12262 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
12263 #define QUADSPI_SR_FTF_Pos (2U)
12264 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
12265 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
12266 #define QUADSPI_SR_SMF_Pos (3U)
12267 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
12268 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
12269 #define QUADSPI_SR_TOF_Pos (4U)
12270 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
12271 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
12272 #define QUADSPI_SR_BUSY_Pos (5U)
12273 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
12274 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
12275 #define QUADSPI_SR_FLEVEL_Pos (8U)
12276 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
12277 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
12278
12279 /****************** Bit definition for QUADSPI_FCR register ******************/
12280 #define QUADSPI_FCR_CTEF_Pos (0U)
12281 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
12282 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
12283 #define QUADSPI_FCR_CTCF_Pos (1U)
12284 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
12285 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
12286 #define QUADSPI_FCR_CSMF_Pos (3U)
12287 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
12288 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
12289 #define QUADSPI_FCR_CTOF_Pos (4U)
12290 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
12291 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
12292
12293 /****************** Bit definition for QUADSPI_DLR register ******************/
12294 #define QUADSPI_DLR_DL_Pos (0U)
12295 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
12296 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
12297
12298 /****************** Bit definition for QUADSPI_CCR register ******************/
12299 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
12300 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
12301 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
12302 #define QUADSPI_CCR_IMODE_Pos (8U)
12303 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
12304 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
12305 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
12306 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
12307 #define QUADSPI_CCR_ADMODE_Pos (10U)
12308 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
12309 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
12310 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
12311 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
12312 #define QUADSPI_CCR_ADSIZE_Pos (12U)
12313 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
12314 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
12315 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
12316 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
12317 #define QUADSPI_CCR_ABMODE_Pos (14U)
12318 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
12319 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
12320 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
12321 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
12322 #define QUADSPI_CCR_ABSIZE_Pos (16U)
12323 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
12324 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
12325 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
12326 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
12327 #define QUADSPI_CCR_DCYC_Pos (18U)
12328 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
12329 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
12330 #define QUADSPI_CCR_DMODE_Pos (24U)
12331 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
12332 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
12333 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
12334 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
12335 #define QUADSPI_CCR_FMODE_Pos (26U)
12336 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
12337 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
12338 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
12339 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
12340 #define QUADSPI_CCR_SIOO_Pos (28U)
12341 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
12342 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
12343 #define QUADSPI_CCR_DHHC_Pos (30U)
12344 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
12345 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
12346 #define QUADSPI_CCR_DDRM_Pos (31U)
12347 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
12348 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
12349
12350 /****************** Bit definition for QUADSPI_AR register *******************/
12351 #define QUADSPI_AR_ADDRESS_Pos (0U)
12352 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
12353 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
12354
12355 /****************** Bit definition for QUADSPI_ABR register ******************/
12356 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
12357 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
12358 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
12359
12360 /****************** Bit definition for QUADSPI_DR register *******************/
12361 #define QUADSPI_DR_DATA_Pos (0U)
12362 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
12363 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
12364
12365 /****************** Bit definition for QUADSPI_PSMKR register ****************/
12366 #define QUADSPI_PSMKR_MASK_Pos (0U)
12367 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
12368 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
12369
12370 /****************** Bit definition for QUADSPI_PSMAR register ****************/
12371 #define QUADSPI_PSMAR_MATCH_Pos (0U)
12372 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
12373 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
12374
12375 /****************** Bit definition for QUADSPI_PIR register *****************/
12376 #define QUADSPI_PIR_INTERVAL_Pos (0U)
12377 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
12378 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
12379
12380 /****************** Bit definition for QUADSPI_LPTR register *****************/
12381 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
12382 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
12383 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
12384
12385 /******************************************************************************/
12386 /* */
12387 /* SYSCFG */
12388 /* */
12389 /******************************************************************************/
12390 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
12391 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
12392 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
12393 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
12394 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
12395 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
12396 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
12397
12398 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
12399 #define SYSCFG_CFGR1_FWDIS_Pos (0U)
12400 #define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
12401 #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
12402 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
12403 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
12404 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
12405 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
12406 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
12407 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
12408 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
12409 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
12410 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
12411 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
12412 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
12413 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
12414 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
12415 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
12416 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
12417 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
12418 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
12419 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
12420 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
12421 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
12422 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
12423 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
12424 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
12425 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
12426 #define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
12427 #define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C4_FMP_Pos) /*!< 0x00800000 */
12428 #define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
12429 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
12430 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
12431 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
12432 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
12433 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
12434 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
12435
12436 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
12437 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
12438 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
12439 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
12440 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
12441 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
12442 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
12443 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
12444 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
12445 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
12446 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
12447 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
12448 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
12449
12450 /**
12451 * @brief EXTI0 configuration
12452 */
12453 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
12454 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
12455 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
12456 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
12457 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
12458 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
12459
12460 /**
12461 * @brief EXTI1 configuration
12462 */
12463 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
12464 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
12465 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
12466 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
12467 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
12468 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
12469
12470 /**
12471 * @brief EXTI2 configuration
12472 */
12473 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
12474 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
12475 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
12476 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
12477 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
12478
12479 /**
12480 * @brief EXTI3 configuration
12481 */
12482 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
12483 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
12484 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
12485 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
12486 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
12487
12488 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
12489 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
12490 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
12491 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
12492 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
12493 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
12494 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
12495 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
12496 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
12497 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
12498 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
12499 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
12500 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
12501 /**
12502 * @brief EXTI4 configuration
12503 */
12504 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
12505 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
12506 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
12507 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
12508 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
12509
12510 /**
12511 * @brief EXTI5 configuration
12512 */
12513 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
12514 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
12515 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
12516 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
12517 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
12518
12519 /**
12520 * @brief EXTI6 configuration
12521 */
12522 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
12523 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
12524 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
12525 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
12526 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
12527
12528 /**
12529 * @brief EXTI7 configuration
12530 */
12531 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
12532 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
12533 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
12534 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
12535 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
12536
12537 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
12538 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
12539 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
12540 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
12541 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
12542 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
12543 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
12544 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
12545 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
12546 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
12547 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12548 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
12549 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
12550
12551 /**
12552 * @brief EXTI8 configuration
12553 */
12554 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
12555 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
12556 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
12557 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
12558 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
12559
12560 /**
12561 * @brief EXTI9 configuration
12562 */
12563 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
12564 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
12565 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
12566 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
12567 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
12568
12569 /**
12570 * @brief EXTI10 configuration
12571 */
12572 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
12573 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
12574 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
12575 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
12576 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
12577
12578 /**
12579 * @brief EXTI11 configuration
12580 */
12581 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
12582 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
12583 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
12584 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
12585 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
12586
12587 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
12588 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
12589 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
12590 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
12591 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
12592 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
12593 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
12594 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
12595 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
12596 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
12597 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
12598 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
12599 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
12600
12601 /**
12602 * @brief EXTI12 configuration
12603 */
12604 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
12605 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
12606 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
12607 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
12608 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
12609
12610 /**
12611 * @brief EXTI13 configuration
12612 */
12613 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
12614 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
12615 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
12616 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
12617 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
12618
12619 /**
12620 * @brief EXTI14 configuration
12621 */
12622 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
12623 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
12624 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
12625 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
12626 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
12627
12628 /**
12629 * @brief EXTI15 configuration
12630 */
12631 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
12632 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
12633 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
12634 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
12635 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
12636
12637 /****************** Bit definition for SYSCFG_SCSR register ****************/
12638 #define SYSCFG_SCSR_SRAM2ER_Pos (0U)
12639 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
12640 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
12641 #define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
12642 #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
12643 #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
12644
12645 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
12646 #define SYSCFG_CFGR2_CLL_Pos (0U)
12647 #define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
12648 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
12649 #define SYSCFG_CFGR2_SPL_Pos (1U)
12650 #define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
12651 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
12652 #define SYSCFG_CFGR2_PVDL_Pos (2U)
12653 #define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
12654 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
12655 #define SYSCFG_CFGR2_ECCL_Pos (3U)
12656 #define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
12657 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
12658 #define SYSCFG_CFGR2_SPF_Pos (8U)
12659 #define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
12660 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
12661
12662 /****************** Bit definition for SYSCFG_SWPR register ****************/
12663 #define SYSCFG_SWPR_PAGE0_Pos (0U)
12664 #define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
12665 #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
12666 #define SYSCFG_SWPR_PAGE1_Pos (1U)
12667 #define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
12668 #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
12669 #define SYSCFG_SWPR_PAGE2_Pos (2U)
12670 #define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
12671 #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
12672 #define SYSCFG_SWPR_PAGE3_Pos (3U)
12673 #define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
12674 #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
12675 #define SYSCFG_SWPR_PAGE4_Pos (4U)
12676 #define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
12677 #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
12678 #define SYSCFG_SWPR_PAGE5_Pos (5U)
12679 #define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
12680 #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
12681 #define SYSCFG_SWPR_PAGE6_Pos (6U)
12682 #define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
12683 #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
12684 #define SYSCFG_SWPR_PAGE7_Pos (7U)
12685 #define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
12686 #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
12687 #define SYSCFG_SWPR_PAGE8_Pos (8U)
12688 #define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
12689 #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
12690 #define SYSCFG_SWPR_PAGE9_Pos (9U)
12691 #define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
12692 #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
12693 #define SYSCFG_SWPR_PAGE10_Pos (10U)
12694 #define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
12695 #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
12696 #define SYSCFG_SWPR_PAGE11_Pos (11U)
12697 #define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
12698 #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
12699 #define SYSCFG_SWPR_PAGE12_Pos (12U)
12700 #define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
12701 #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
12702 #define SYSCFG_SWPR_PAGE13_Pos (13U)
12703 #define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
12704 #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
12705 #define SYSCFG_SWPR_PAGE14_Pos (14U)
12706 #define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
12707 #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
12708 #define SYSCFG_SWPR_PAGE15_Pos (15U)
12709 #define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
12710 #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
12711 #define SYSCFG_SWPR_PAGE16_Pos (16U)
12712 #define SYSCFG_SWPR_PAGE16_Msk (0x1U << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
12713 #define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16*/
12714 #define SYSCFG_SWPR_PAGE17_Pos (17U)
12715 #define SYSCFG_SWPR_PAGE17_Msk (0x1U << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
12716 #define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17*/
12717 #define SYSCFG_SWPR_PAGE18_Pos (18U)
12718 #define SYSCFG_SWPR_PAGE18_Msk (0x1U << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
12719 #define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18*/
12720 #define SYSCFG_SWPR_PAGE19_Pos (19U)
12721 #define SYSCFG_SWPR_PAGE19_Msk (0x1U << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
12722 #define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19*/
12723 #define SYSCFG_SWPR_PAGE20_Pos (20U)
12724 #define SYSCFG_SWPR_PAGE20_Msk (0x1U << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
12725 #define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20*/
12726 #define SYSCFG_SWPR_PAGE21_Pos (21U)
12727 #define SYSCFG_SWPR_PAGE21_Msk (0x1U << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
12728 #define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21*/
12729 #define SYSCFG_SWPR_PAGE22_Pos (22U)
12730 #define SYSCFG_SWPR_PAGE22_Msk (0x1U << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
12731 #define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22*/
12732 #define SYSCFG_SWPR_PAGE23_Pos (23U)
12733 #define SYSCFG_SWPR_PAGE23_Msk (0x1U << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
12734 #define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23*/
12735 #define SYSCFG_SWPR_PAGE24_Pos (24U)
12736 #define SYSCFG_SWPR_PAGE24_Msk (0x1U << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
12737 #define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24*/
12738 #define SYSCFG_SWPR_PAGE25_Pos (25U)
12739 #define SYSCFG_SWPR_PAGE25_Msk (0x1U << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
12740 #define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25*/
12741 #define SYSCFG_SWPR_PAGE26_Pos (26U)
12742 #define SYSCFG_SWPR_PAGE26_Msk (0x1U << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
12743 #define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26*/
12744 #define SYSCFG_SWPR_PAGE27_Pos (27U)
12745 #define SYSCFG_SWPR_PAGE27_Msk (0x1U << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
12746 #define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27*/
12747 #define SYSCFG_SWPR_PAGE28_Pos (28U)
12748 #define SYSCFG_SWPR_PAGE28_Msk (0x1U << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
12749 #define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28*/
12750 #define SYSCFG_SWPR_PAGE29_Pos (29U)
12751 #define SYSCFG_SWPR_PAGE29_Msk (0x1U << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
12752 #define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29*/
12753 #define SYSCFG_SWPR_PAGE30_Pos (30U)
12754 #define SYSCFG_SWPR_PAGE30_Msk (0x1U << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
12755 #define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30*/
12756 #define SYSCFG_SWPR_PAGE31_Pos (31U)
12757 #define SYSCFG_SWPR_PAGE31_Msk (0x1U << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
12758 #define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31*/
12759
12760 /****************** Bit definition for SYSCFG_SKR register ****************/
12761 #define SYSCFG_SKR_KEY_Pos (0U)
12762 #define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
12763 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
12764
12765
12766
12767
12768 /******************************************************************************/
12769 /* */
12770 /* TIM */
12771 /* */
12772 /******************************************************************************/
12773 /******************* Bit definition for TIM_CR1 register ********************/
12774 #define TIM_CR1_CEN_Pos (0U)
12775 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
12776 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
12777 #define TIM_CR1_UDIS_Pos (1U)
12778 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
12779 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
12780 #define TIM_CR1_URS_Pos (2U)
12781 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
12782 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
12783 #define TIM_CR1_OPM_Pos (3U)
12784 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
12785 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
12786 #define TIM_CR1_DIR_Pos (4U)
12787 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
12788 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
12789
12790 #define TIM_CR1_CMS_Pos (5U)
12791 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
12792 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
12793 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
12794 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
12795
12796 #define TIM_CR1_ARPE_Pos (7U)
12797 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
12798 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
12799
12800 #define TIM_CR1_CKD_Pos (8U)
12801 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
12802 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
12803 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
12804 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
12805
12806 #define TIM_CR1_UIFREMAP_Pos (11U)
12807 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
12808 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
12809
12810 /******************* Bit definition for TIM_CR2 register ********************/
12811 #define TIM_CR2_CCPC_Pos (0U)
12812 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
12813 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
12814 #define TIM_CR2_CCUS_Pos (2U)
12815 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
12816 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
12817 #define TIM_CR2_CCDS_Pos (3U)
12818 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
12819 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
12820
12821 #define TIM_CR2_MMS_Pos (4U)
12822 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
12823 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
12824 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
12825 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
12826 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
12827
12828 #define TIM_CR2_TI1S_Pos (7U)
12829 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
12830 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
12831 #define TIM_CR2_OIS1_Pos (8U)
12832 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
12833 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
12834 #define TIM_CR2_OIS1N_Pos (9U)
12835 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
12836 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
12837 #define TIM_CR2_OIS2_Pos (10U)
12838 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
12839 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
12840 #define TIM_CR2_OIS2N_Pos (11U)
12841 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
12842 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
12843 #define TIM_CR2_OIS3_Pos (12U)
12844 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
12845 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
12846 #define TIM_CR2_OIS3N_Pos (13U)
12847 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
12848 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
12849 #define TIM_CR2_OIS4_Pos (14U)
12850 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
12851 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
12852 #define TIM_CR2_OIS5_Pos (16U)
12853 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
12854 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
12855 #define TIM_CR2_OIS6_Pos (18U)
12856 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
12857 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
12858
12859 #define TIM_CR2_MMS2_Pos (20U)
12860 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
12861 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
12862 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
12863 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
12864 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
12865 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
12866
12867 /******************* Bit definition for TIM_SMCR register *******************/
12868 #define TIM_SMCR_SMS_Pos (0U)
12869 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
12870 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
12871 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
12872 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
12873 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
12874 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
12875
12876 #define TIM_SMCR_OCCS_Pos (3U)
12877 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
12878 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
12879
12880 #define TIM_SMCR_TS_Pos (4U)
12881 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
12882 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
12883 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
12884 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
12885 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
12886
12887 #define TIM_SMCR_MSM_Pos (7U)
12888 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
12889 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
12890
12891 #define TIM_SMCR_ETF_Pos (8U)
12892 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
12893 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
12894 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
12895 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
12896 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
12897 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
12898
12899 #define TIM_SMCR_ETPS_Pos (12U)
12900 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
12901 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
12902 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
12903 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
12904
12905 #define TIM_SMCR_ECE_Pos (14U)
12906 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
12907 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
12908 #define TIM_SMCR_ETP_Pos (15U)
12909 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
12910 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
12911
12912 /******************* Bit definition for TIM_DIER register *******************/
12913 #define TIM_DIER_UIE_Pos (0U)
12914 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
12915 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
12916 #define TIM_DIER_CC1IE_Pos (1U)
12917 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
12918 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
12919 #define TIM_DIER_CC2IE_Pos (2U)
12920 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
12921 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
12922 #define TIM_DIER_CC3IE_Pos (3U)
12923 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
12924 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
12925 #define TIM_DIER_CC4IE_Pos (4U)
12926 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
12927 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
12928 #define TIM_DIER_COMIE_Pos (5U)
12929 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
12930 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
12931 #define TIM_DIER_TIE_Pos (6U)
12932 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
12933 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
12934 #define TIM_DIER_BIE_Pos (7U)
12935 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
12936 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
12937 #define TIM_DIER_UDE_Pos (8U)
12938 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
12939 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
12940 #define TIM_DIER_CC1DE_Pos (9U)
12941 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
12942 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
12943 #define TIM_DIER_CC2DE_Pos (10U)
12944 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
12945 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
12946 #define TIM_DIER_CC3DE_Pos (11U)
12947 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
12948 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
12949 #define TIM_DIER_CC4DE_Pos (12U)
12950 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
12951 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
12952 #define TIM_DIER_COMDE_Pos (13U)
12953 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
12954 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
12955 #define TIM_DIER_TDE_Pos (14U)
12956 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
12957 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
12958
12959 /******************** Bit definition for TIM_SR register ********************/
12960 #define TIM_SR_UIF_Pos (0U)
12961 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
12962 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
12963 #define TIM_SR_CC1IF_Pos (1U)
12964 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
12965 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
12966 #define TIM_SR_CC2IF_Pos (2U)
12967 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
12968 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
12969 #define TIM_SR_CC3IF_Pos (3U)
12970 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
12971 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
12972 #define TIM_SR_CC4IF_Pos (4U)
12973 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
12974 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
12975 #define TIM_SR_COMIF_Pos (5U)
12976 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
12977 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
12978 #define TIM_SR_TIF_Pos (6U)
12979 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
12980 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
12981 #define TIM_SR_BIF_Pos (7U)
12982 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
12983 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
12984 #define TIM_SR_B2IF_Pos (8U)
12985 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
12986 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
12987 #define TIM_SR_CC1OF_Pos (9U)
12988 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
12989 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
12990 #define TIM_SR_CC2OF_Pos (10U)
12991 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
12992 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
12993 #define TIM_SR_CC3OF_Pos (11U)
12994 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
12995 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
12996 #define TIM_SR_CC4OF_Pos (12U)
12997 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
12998 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
12999 #define TIM_SR_SBIF_Pos (13U)
13000 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
13001 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
13002 #define TIM_SR_CC5IF_Pos (16U)
13003 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
13004 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
13005 #define TIM_SR_CC6IF_Pos (17U)
13006 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
13007 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
13008
13009
13010 /******************* Bit definition for TIM_EGR register ********************/
13011 #define TIM_EGR_UG_Pos (0U)
13012 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
13013 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
13014 #define TIM_EGR_CC1G_Pos (1U)
13015 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
13016 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
13017 #define TIM_EGR_CC2G_Pos (2U)
13018 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
13019 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
13020 #define TIM_EGR_CC3G_Pos (3U)
13021 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
13022 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
13023 #define TIM_EGR_CC4G_Pos (4U)
13024 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
13025 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
13026 #define TIM_EGR_COMG_Pos (5U)
13027 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
13028 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
13029 #define TIM_EGR_TG_Pos (6U)
13030 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
13031 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
13032 #define TIM_EGR_BG_Pos (7U)
13033 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
13034 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
13035 #define TIM_EGR_B2G_Pos (8U)
13036 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
13037 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
13038
13039
13040 /****************** Bit definition for TIM_CCMR1 register *******************/
13041 #define TIM_CCMR1_CC1S_Pos (0U)
13042 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
13043 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13044 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
13045 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
13046
13047 #define TIM_CCMR1_OC1FE_Pos (2U)
13048 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
13049 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
13050 #define TIM_CCMR1_OC1PE_Pos (3U)
13051 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
13052 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
13053
13054 #define TIM_CCMR1_OC1M_Pos (4U)
13055 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
13056 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
13057 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
13058 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
13059 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
13060 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
13061
13062 #define TIM_CCMR1_OC1CE_Pos (7U)
13063 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
13064 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
13065
13066 #define TIM_CCMR1_CC2S_Pos (8U)
13067 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
13068 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
13069 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
13070 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
13071
13072 #define TIM_CCMR1_OC2FE_Pos (10U)
13073 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
13074 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
13075 #define TIM_CCMR1_OC2PE_Pos (11U)
13076 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
13077 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
13078
13079 #define TIM_CCMR1_OC2M_Pos (12U)
13080 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
13081 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
13082 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
13083 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
13084 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
13085 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
13086
13087 #define TIM_CCMR1_OC2CE_Pos (15U)
13088 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
13089 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
13090
13091 /*----------------------------------------------------------------------------*/
13092 #define TIM_CCMR1_IC1PSC_Pos (2U)
13093 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
13094 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
13095 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
13096 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
13097
13098 #define TIM_CCMR1_IC1F_Pos (4U)
13099 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
13100 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
13101 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
13102 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
13103 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
13104 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
13105
13106 #define TIM_CCMR1_IC2PSC_Pos (10U)
13107 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
13108 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
13109 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
13110 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
13111
13112 #define TIM_CCMR1_IC2F_Pos (12U)
13113 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
13114 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
13115 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
13116 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
13117 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
13118 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
13119
13120 /****************** Bit definition for TIM_CCMR2 register *******************/
13121 #define TIM_CCMR2_CC3S_Pos (0U)
13122 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
13123 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
13124 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
13125 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
13126
13127 #define TIM_CCMR2_OC3FE_Pos (2U)
13128 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
13129 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
13130 #define TIM_CCMR2_OC3PE_Pos (3U)
13131 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
13132 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
13133
13134 #define TIM_CCMR2_OC3M_Pos (4U)
13135 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
13136 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
13137 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
13138 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
13139 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
13140 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
13141
13142 #define TIM_CCMR2_OC3CE_Pos (7U)
13143 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
13144 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
13145
13146 #define TIM_CCMR2_CC4S_Pos (8U)
13147 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
13148 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
13149 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
13150 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
13151
13152 #define TIM_CCMR2_OC4FE_Pos (10U)
13153 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
13154 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
13155 #define TIM_CCMR2_OC4PE_Pos (11U)
13156 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
13157 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
13158
13159 #define TIM_CCMR2_OC4M_Pos (12U)
13160 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
13161 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
13162 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
13163 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
13164 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
13165 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
13166
13167 #define TIM_CCMR2_OC4CE_Pos (15U)
13168 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
13169 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
13170
13171 /*----------------------------------------------------------------------------*/
13172 #define TIM_CCMR2_IC3PSC_Pos (2U)
13173 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
13174 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
13175 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
13176 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
13177
13178 #define TIM_CCMR2_IC3F_Pos (4U)
13179 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
13180 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
13181 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
13182 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
13183 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
13184 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
13185
13186 #define TIM_CCMR2_IC4PSC_Pos (10U)
13187 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
13188 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
13189 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
13190 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
13191
13192 #define TIM_CCMR2_IC4F_Pos (12U)
13193 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
13194 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
13195 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
13196 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
13197 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
13198 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
13199
13200 /****************** Bit definition for TIM_CCMR3 register *******************/
13201 #define TIM_CCMR3_OC5FE_Pos (2U)
13202 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
13203 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
13204 #define TIM_CCMR3_OC5PE_Pos (3U)
13205 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
13206 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
13207
13208 #define TIM_CCMR3_OC5M_Pos (4U)
13209 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
13210 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
13211 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
13212 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
13213 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
13214 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
13215
13216 #define TIM_CCMR3_OC5CE_Pos (7U)
13217 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
13218 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
13219
13220 #define TIM_CCMR3_OC6FE_Pos (10U)
13221 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
13222 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
13223 #define TIM_CCMR3_OC6PE_Pos (11U)
13224 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
13225 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
13226
13227 #define TIM_CCMR3_OC6M_Pos (12U)
13228 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
13229 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
13230 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
13231 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
13232 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
13233 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
13234
13235 #define TIM_CCMR3_OC6CE_Pos (15U)
13236 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
13237 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
13238
13239 /******************* Bit definition for TIM_CCER register *******************/
13240 #define TIM_CCER_CC1E_Pos (0U)
13241 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
13242 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
13243 #define TIM_CCER_CC1P_Pos (1U)
13244 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
13245 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
13246 #define TIM_CCER_CC1NE_Pos (2U)
13247 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
13248 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
13249 #define TIM_CCER_CC1NP_Pos (3U)
13250 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
13251 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
13252 #define TIM_CCER_CC2E_Pos (4U)
13253 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
13254 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
13255 #define TIM_CCER_CC2P_Pos (5U)
13256 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
13257 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
13258 #define TIM_CCER_CC2NE_Pos (6U)
13259 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
13260 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
13261 #define TIM_CCER_CC2NP_Pos (7U)
13262 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
13263 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
13264 #define TIM_CCER_CC3E_Pos (8U)
13265 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
13266 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
13267 #define TIM_CCER_CC3P_Pos (9U)
13268 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
13269 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
13270 #define TIM_CCER_CC3NE_Pos (10U)
13271 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
13272 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
13273 #define TIM_CCER_CC3NP_Pos (11U)
13274 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
13275 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
13276 #define TIM_CCER_CC4E_Pos (12U)
13277 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
13278 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
13279 #define TIM_CCER_CC4P_Pos (13U)
13280 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
13281 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
13282 #define TIM_CCER_CC4NP_Pos (15U)
13283 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
13284 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
13285 #define TIM_CCER_CC5E_Pos (16U)
13286 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
13287 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
13288 #define TIM_CCER_CC5P_Pos (17U)
13289 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
13290 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
13291 #define TIM_CCER_CC6E_Pos (20U)
13292 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
13293 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
13294 #define TIM_CCER_CC6P_Pos (21U)
13295 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
13296 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
13297
13298 /******************* Bit definition for TIM_CNT register ********************/
13299 #define TIM_CNT_CNT_Pos (0U)
13300 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
13301 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
13302 #define TIM_CNT_UIFCPY_Pos (31U)
13303 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
13304 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
13305
13306 /******************* Bit definition for TIM_PSC register ********************/
13307 #define TIM_PSC_PSC_Pos (0U)
13308 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
13309 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
13310
13311 /******************* Bit definition for TIM_ARR register ********************/
13312 #define TIM_ARR_ARR_Pos (0U)
13313 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
13314 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
13315
13316 /******************* Bit definition for TIM_RCR register ********************/
13317 #define TIM_RCR_REP_Pos (0U)
13318 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
13319 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
13320
13321 /******************* Bit definition for TIM_CCR1 register *******************/
13322 #define TIM_CCR1_CCR1_Pos (0U)
13323 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
13324 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
13325
13326 /******************* Bit definition for TIM_CCR2 register *******************/
13327 #define TIM_CCR2_CCR2_Pos (0U)
13328 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
13329 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
13330
13331 /******************* Bit definition for TIM_CCR3 register *******************/
13332 #define TIM_CCR3_CCR3_Pos (0U)
13333 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
13334 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
13335
13336 /******************* Bit definition for TIM_CCR4 register *******************/
13337 #define TIM_CCR4_CCR4_Pos (0U)
13338 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
13339 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
13340
13341 /******************* Bit definition for TIM_CCR5 register *******************/
13342 #define TIM_CCR5_CCR5_Pos (0U)
13343 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13344 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
13345 #define TIM_CCR5_GC5C1_Pos (29U)
13346 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
13347 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
13348 #define TIM_CCR5_GC5C2_Pos (30U)
13349 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
13350 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
13351 #define TIM_CCR5_GC5C3_Pos (31U)
13352 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
13353 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
13354
13355 /******************* Bit definition for TIM_CCR6 register *******************/
13356 #define TIM_CCR6_CCR6_Pos (0U)
13357 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
13358 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
13359
13360 /******************* Bit definition for TIM_BDTR register *******************/
13361 #define TIM_BDTR_DTG_Pos (0U)
13362 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
13363 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
13364 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
13365 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
13366 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
13367 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
13368 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
13369 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
13370 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
13371 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
13372
13373 #define TIM_BDTR_LOCK_Pos (8U)
13374 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
13375 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
13376 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
13377 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
13378
13379 #define TIM_BDTR_OSSI_Pos (10U)
13380 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
13381 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
13382 #define TIM_BDTR_OSSR_Pos (11U)
13383 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
13384 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
13385 #define TIM_BDTR_BKE_Pos (12U)
13386 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
13387 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
13388 #define TIM_BDTR_BKP_Pos (13U)
13389 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
13390 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
13391 #define TIM_BDTR_AOE_Pos (14U)
13392 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
13393 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
13394 #define TIM_BDTR_MOE_Pos (15U)
13395 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
13396 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
13397
13398 #define TIM_BDTR_BKF_Pos (16U)
13399 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
13400 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
13401 #define TIM_BDTR_BK2F_Pos (20U)
13402 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
13403 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
13404
13405 #define TIM_BDTR_BK2E_Pos (24U)
13406 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
13407 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
13408 #define TIM_BDTR_BK2P_Pos (25U)
13409 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
13410 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
13411
13412 /******************* Bit definition for TIM_DCR register ********************/
13413 #define TIM_DCR_DBA_Pos (0U)
13414 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
13415 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
13416 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
13417 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
13418 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
13419 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
13420 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
13421
13422 #define TIM_DCR_DBL_Pos (8U)
13423 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
13424 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
13425 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
13426 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
13427 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
13428 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
13429 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
13430
13431 /******************* Bit definition for TIM_DMAR register *******************/
13432 #define TIM_DMAR_DMAB_Pos (0U)
13433 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
13434 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
13435
13436 /******************* Bit definition for TIM1_OR1 register *******************/
13437 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
13438 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
13439 #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
13440 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
13441 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
13442
13443 #define TIM1_OR1_TI1_RMP_Pos (4U)
13444 #define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
13445 #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
13446
13447 /******************* Bit definition for TIM1_OR2 register *******************/
13448 #define TIM1_OR2_BKINE_Pos (0U)
13449 #define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
13450 #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
13451 #define TIM1_OR2_BKCMP1E_Pos (1U)
13452 #define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
13453 #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
13454 #define TIM1_OR2_BKCMP2E_Pos (2U)
13455 #define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
13456 #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
13457 #define TIM1_OR2_BKDF1BK0E_Pos (8U)
13458 #define TIM1_OR2_BKDF1BK0E_Msk (0x1U << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
13459 #define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
13460 #define TIM1_OR2_BKINP_Pos (9U)
13461 #define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
13462 #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
13463 #define TIM1_OR2_BKCMP1P_Pos (10U)
13464 #define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
13465 #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
13466 #define TIM1_OR2_BKCMP2P_Pos (11U)
13467 #define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
13468 #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
13469
13470 #define TIM1_OR2_ETRSEL_Pos (14U)
13471 #define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
13472 #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
13473 #define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
13474 #define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
13475 #define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
13476
13477 /******************* Bit definition for TIM1_OR3 register *******************/
13478 #define TIM1_OR3_BK2INE_Pos (0U)
13479 #define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
13480 #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
13481 #define TIM1_OR3_BK2CMP1E_Pos (1U)
13482 #define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
13483 #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
13484 #define TIM1_OR3_BK2CMP2E_Pos (2U)
13485 #define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
13486 #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
13487 #define TIM1_OR3_BK2DF1BK1E_Pos (8U)
13488 #define TIM1_OR3_BK2DF1BK1E_Msk (0x1U << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */
13489 #define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */
13490 #define TIM1_OR3_BK2INP_Pos (9U)
13491 #define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
13492 #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
13493 #define TIM1_OR3_BK2CMP1P_Pos (10U)
13494 #define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
13495 #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
13496 #define TIM1_OR3_BK2CMP2P_Pos (11U)
13497 #define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
13498 #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
13499
13500
13501 /******************* Bit definition for TIM2_OR1 register *******************/
13502 #define TIM2_OR1_ITR1_RMP_Pos (0U)
13503 #define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
13504 #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
13505 #define TIM2_OR1_ETR1_RMP_Pos (1U)
13506 #define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
13507 #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
13508
13509 #define TIM2_OR1_TI4_RMP_Pos (2U)
13510 #define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
13511 #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
13512 #define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
13513 #define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
13514
13515 /******************* Bit definition for TIM2_OR2 register *******************/
13516 #define TIM2_OR2_ETRSEL_Pos (14U)
13517 #define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
13518 #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
13519 #define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
13520 #define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
13521 #define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
13522
13523 /******************* Bit definition for TIM3_OR1 register *******************/
13524 #define TIM3_OR1_TI1_RMP_Pos (0U)
13525 #define TIM3_OR1_TI1_RMP_Msk (0x3U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
13526 #define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
13527 #define TIM3_OR1_TI1_RMP_0 (0x1U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
13528 #define TIM3_OR1_TI1_RMP_1 (0x2U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
13529
13530 /******************* Bit definition for TIM3_OR2 register *******************/
13531 #define TIM3_OR2_ETRSEL_Pos (14U)
13532 #define TIM3_OR2_ETRSEL_Msk (0x7U << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
13533 #define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
13534 #define TIM3_OR2_ETRSEL_0 (0x1U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */
13535 #define TIM3_OR2_ETRSEL_1 (0x2U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */
13536 #define TIM3_OR2_ETRSEL_2 (0x4U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */
13537
13538 /******************* Bit definition for TIM15_OR1 register ******************/
13539 #define TIM15_OR1_TI1_RMP_Pos (0U)
13540 #define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
13541 #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
13542
13543 #define TIM15_OR1_ENCODER_MODE_Pos (1U)
13544 #define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
13545 #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
13546 #define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
13547 #define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
13548
13549 /******************* Bit definition for TIM15_OR2 register ******************/
13550 #define TIM15_OR2_BKINE_Pos (0U)
13551 #define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
13552 #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
13553 #define TIM15_OR2_BKCMP1E_Pos (1U)
13554 #define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
13555 #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
13556 #define TIM15_OR2_BKCMP2E_Pos (2U)
13557 #define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
13558 #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
13559 #define TIM15_OR2_BKDF1BK0E_Pos (8U)
13560 #define TIM15_OR2_BKDF1BK0E_Msk (0x1U << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
13561 #define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
13562 #define TIM15_OR2_BKINP_Pos (9U)
13563 #define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
13564 #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
13565 #define TIM15_OR2_BKCMP1P_Pos (10U)
13566 #define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
13567 #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
13568 #define TIM15_OR2_BKCMP2P_Pos (11U)
13569 #define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
13570 #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
13571
13572 /******************* Bit definition for TIM16_OR1 register ******************/
13573 #define TIM16_OR1_TI1_RMP_Pos (0U)
13574 #define TIM16_OR1_TI1_RMP_Msk (0x3U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
13575 #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
13576 #define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
13577 #define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
13578
13579 /******************* Bit definition for TIM16_OR2 register ******************/
13580 #define TIM16_OR2_BKINE_Pos (0U)
13581 #define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
13582 #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
13583 #define TIM16_OR2_BKCMP1E_Pos (1U)
13584 #define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
13585 #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
13586 #define TIM16_OR2_BKCMP2E_Pos (2U)
13587 #define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
13588 #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
13589 #define TIM16_OR2_BKDF1BK1E_Pos (8U)
13590 #define TIM16_OR2_BKDF1BK1E_Msk (0x1U << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */
13591 #define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */
13592 #define TIM16_OR2_BKINP_Pos (9U)
13593 #define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
13594 #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
13595 #define TIM16_OR2_BKCMP1P_Pos (10U)
13596 #define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
13597 #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
13598 #define TIM16_OR2_BKCMP2P_Pos (11U)
13599 #define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
13600 #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
13601
13602
13603 /******************************************************************************/
13604 /* */
13605 /* Low Power Timer (LPTTIM) */
13606 /* */
13607 /******************************************************************************/
13608 /****************** Bit definition for LPTIM_ISR register *******************/
13609 #define LPTIM_ISR_CMPM_Pos (0U)
13610 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
13611 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
13612 #define LPTIM_ISR_ARRM_Pos (1U)
13613 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
13614 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
13615 #define LPTIM_ISR_EXTTRIG_Pos (2U)
13616 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
13617 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
13618 #define LPTIM_ISR_CMPOK_Pos (3U)
13619 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
13620 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
13621 #define LPTIM_ISR_ARROK_Pos (4U)
13622 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
13623 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
13624 #define LPTIM_ISR_UP_Pos (5U)
13625 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
13626 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
13627 #define LPTIM_ISR_DOWN_Pos (6U)
13628 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
13629 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
13630
13631 /****************** Bit definition for LPTIM_ICR register *******************/
13632 #define LPTIM_ICR_CMPMCF_Pos (0U)
13633 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
13634 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
13635 #define LPTIM_ICR_ARRMCF_Pos (1U)
13636 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
13637 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
13638 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
13639 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
13640 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
13641 #define LPTIM_ICR_CMPOKCF_Pos (3U)
13642 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
13643 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
13644 #define LPTIM_ICR_ARROKCF_Pos (4U)
13645 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
13646 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
13647 #define LPTIM_ICR_UPCF_Pos (5U)
13648 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
13649 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
13650 #define LPTIM_ICR_DOWNCF_Pos (6U)
13651 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
13652 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
13653
13654 /****************** Bit definition for LPTIM_IER register ********************/
13655 #define LPTIM_IER_CMPMIE_Pos (0U)
13656 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
13657 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
13658 #define LPTIM_IER_ARRMIE_Pos (1U)
13659 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
13660 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
13661 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
13662 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
13663 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
13664 #define LPTIM_IER_CMPOKIE_Pos (3U)
13665 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
13666 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
13667 #define LPTIM_IER_ARROKIE_Pos (4U)
13668 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
13669 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
13670 #define LPTIM_IER_UPIE_Pos (5U)
13671 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
13672 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
13673 #define LPTIM_IER_DOWNIE_Pos (6U)
13674 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
13675 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
13676
13677 /****************** Bit definition for LPTIM_CFGR register *******************/
13678 #define LPTIM_CFGR_CKSEL_Pos (0U)
13679 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
13680 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
13681
13682 #define LPTIM_CFGR_CKPOL_Pos (1U)
13683 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
13684 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
13685 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
13686 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
13687
13688 #define LPTIM_CFGR_CKFLT_Pos (3U)
13689 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
13690 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
13691 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
13692 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
13693
13694 #define LPTIM_CFGR_TRGFLT_Pos (6U)
13695 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
13696 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
13697 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
13698 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
13699
13700 #define LPTIM_CFGR_PRESC_Pos (9U)
13701 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
13702 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
13703 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
13704 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
13705 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
13706
13707 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
13708 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
13709 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
13710 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
13711 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
13712 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
13713
13714 #define LPTIM_CFGR_TRIGEN_Pos (17U)
13715 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
13716 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
13717 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
13718 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
13719
13720 #define LPTIM_CFGR_TIMOUT_Pos (19U)
13721 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
13722 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
13723 #define LPTIM_CFGR_WAVE_Pos (20U)
13724 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
13725 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
13726 #define LPTIM_CFGR_WAVPOL_Pos (21U)
13727 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
13728 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
13729 #define LPTIM_CFGR_PRELOAD_Pos (22U)
13730 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
13731 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
13732 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
13733 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
13734 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
13735 #define LPTIM_CFGR_ENC_Pos (24U)
13736 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
13737 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
13738
13739 /****************** Bit definition for LPTIM_CR register ********************/
13740 #define LPTIM_CR_ENABLE_Pos (0U)
13741 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
13742 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
13743 #define LPTIM_CR_SNGSTRT_Pos (1U)
13744 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
13745 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
13746 #define LPTIM_CR_CNTSTRT_Pos (2U)
13747 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
13748 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
13749
13750 /****************** Bit definition for LPTIM_CMP register *******************/
13751 #define LPTIM_CMP_CMP_Pos (0U)
13752 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
13753 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
13754
13755 /****************** Bit definition for LPTIM_ARR register *******************/
13756 #define LPTIM_ARR_ARR_Pos (0U)
13757 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
13758 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
13759
13760 /****************** Bit definition for LPTIM_CNT register *******************/
13761 #define LPTIM_CNT_CNT_Pos (0U)
13762 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
13763 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
13764
13765 /****************** Bit definition for LPTIM_OR register ********************/
13766 #define LPTIM_OR_OR_Pos (0U)
13767 #define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
13768 #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
13769 #define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
13770 #define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
13771
13772 /******************************************************************************/
13773 /* */
13774 /* Analog Comparators (COMP) */
13775 /* */
13776 /******************************************************************************/
13777 /********************** Bit definition for COMP_CSR register ****************/
13778 #define COMP_CSR_EN_Pos (0U)
13779 #define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
13780 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
13781
13782 #define COMP_CSR_PWRMODE_Pos (2U)
13783 #define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
13784 #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
13785 #define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
13786 #define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
13787
13788 #define COMP_CSR_INMSEL_Pos (4U)
13789 #define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
13790 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
13791 #define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
13792 #define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
13793 #define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
13794
13795 #define COMP_CSR_INPSEL_Pos (7U)
13796 #define COMP_CSR_INPSEL_Msk (0x3U << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */
13797 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
13798 #define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
13799 #define COMP_CSR_INPSEL_1 (0x2U << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
13800
13801 #define COMP_CSR_WINMODE_Pos (9U)
13802 #define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
13803 #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
13804
13805 #define COMP_CSR_POLARITY_Pos (15U)
13806 #define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
13807 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
13808
13809 #define COMP_CSR_HYST_Pos (16U)
13810 #define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
13811 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
13812 #define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
13813 #define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
13814
13815 #define COMP_CSR_BLANKING_Pos (18U)
13816 #define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
13817 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
13818 #define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
13819 #define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
13820 #define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
13821
13822 #define COMP_CSR_BRGEN_Pos (22U)
13823 #define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
13824 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
13825 #define COMP_CSR_SCALEN_Pos (23U)
13826 #define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
13827 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
13828
13829 #define COMP_CSR_INMESEL_Pos (25U)
13830 #define COMP_CSR_INMESEL_Msk (0x3U << COMP_CSR_INMESEL_Pos) /*!< 0x06000000 */
13831 #define COMP_CSR_INMESEL COMP_CSR_INMESEL_Msk /*!< Comparator inverting input (minus) extended selection */
13832 #define COMP_CSR_INMESEL_0 (0x1U << COMP_CSR_INMESEL_Pos) /*!< 0x02000000 */
13833 #define COMP_CSR_INMESEL_1 (0x2U << COMP_CSR_INMESEL_Pos) /*!< 0x04000000 */
13834
13835 #define COMP_CSR_VALUE_Pos (30U)
13836 #define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
13837 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
13838
13839 #define COMP_CSR_LOCK_Pos (31U)
13840 #define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
13841 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
13842
13843 /******************************************************************************/
13844 /* */
13845 /* Operational Amplifier (OPAMP) */
13846 /* */
13847 /******************************************************************************/
13848 /********************* Bit definition for OPAMPx_CSR register ***************/
13849 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
13850 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
13851 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
13852 #define OPAMP_CSR_OPALPM_Pos (1U)
13853 #define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
13854 #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
13855
13856 #define OPAMP_CSR_OPAMODE_Pos (2U)
13857 #define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
13858 #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
13859 #define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
13860 #define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
13861
13862 #define OPAMP_CSR_PGGAIN_Pos (4U)
13863 #define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
13864 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
13865 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
13866 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
13867
13868 #define OPAMP_CSR_VMSEL_Pos (8U)
13869 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
13870 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
13871 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
13872 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
13873
13874 #define OPAMP_CSR_VPSEL_Pos (10U)
13875 #define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
13876 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
13877 #define OPAMP_CSR_CALON_Pos (12U)
13878 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
13879 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
13880 #define OPAMP_CSR_CALSEL_Pos (13U)
13881 #define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
13882 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
13883 #define OPAMP_CSR_USERTRIM_Pos (14U)
13884 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
13885 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
13886 #define OPAMP_CSR_CALOUT_Pos (15U)
13887 #define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
13888 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
13889
13890 /********************* Bit definition for OPAMP1_CSR register ***************/
13891 #define OPAMP1_CSR_OPAEN_Pos (0U)
13892 #define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
13893 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
13894 #define OPAMP1_CSR_OPALPM_Pos (1U)
13895 #define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
13896 #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
13897
13898 #define OPAMP1_CSR_OPAMODE_Pos (2U)
13899 #define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
13900 #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
13901 #define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
13902 #define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
13903
13904 #define OPAMP1_CSR_PGAGAIN_Pos (4U)
13905 #define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
13906 #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
13907 #define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
13908 #define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
13909
13910 #define OPAMP1_CSR_VMSEL_Pos (8U)
13911 #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
13912 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
13913 #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
13914 #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
13915
13916 #define OPAMP1_CSR_VPSEL_Pos (10U)
13917 #define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
13918 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
13919 #define OPAMP1_CSR_CALON_Pos (12U)
13920 #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
13921 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
13922 #define OPAMP1_CSR_CALSEL_Pos (13U)
13923 #define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
13924 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
13925 #define OPAMP1_CSR_USERTRIM_Pos (14U)
13926 #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
13927 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
13928 #define OPAMP1_CSR_CALOUT_Pos (15U)
13929 #define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
13930 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
13931
13932 #define OPAMP1_CSR_OPARANGE_Pos (31U)
13933 #define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
13934 #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
13935
13936 /******************* Bit definition for OPAMP_OTR register ******************/
13937 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
13938 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13939 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13940 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
13941 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13942 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13943
13944 /******************* Bit definition for OPAMP1_OTR register ******************/
13945 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
13946 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13947 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13948 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
13949 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13950 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13951
13952 /******************* Bit definition for OPAMP_LPOTR register ****************/
13953 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
13954 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
13955 #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13956 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
13957 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
13958 #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13959
13960 /******************* Bit definition for OPAMP1_LPOTR register ****************/
13961 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
13962 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
13963 #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13964 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
13965 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
13966 #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13967
13968 /******************************************************************************/
13969 /* */
13970 /* Touch Sensing Controller (TSC) */
13971 /* */
13972 /******************************************************************************/
13973 /******************* Bit definition for TSC_CR register *********************/
13974 #define TSC_CR_TSCE_Pos (0U)
13975 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
13976 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
13977 #define TSC_CR_START_Pos (1U)
13978 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
13979 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
13980 #define TSC_CR_AM_Pos (2U)
13981 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
13982 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
13983 #define TSC_CR_SYNCPOL_Pos (3U)
13984 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
13985 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
13986 #define TSC_CR_IODEF_Pos (4U)
13987 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
13988 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
13989
13990 #define TSC_CR_MCV_Pos (5U)
13991 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
13992 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
13993 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
13994 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
13995 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
13996
13997 #define TSC_CR_PGPSC_Pos (12U)
13998 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
13999 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
14000 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
14001 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
14002 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
14003
14004 #define TSC_CR_SSPSC_Pos (15U)
14005 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
14006 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
14007 #define TSC_CR_SSE_Pos (16U)
14008 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
14009 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
14010
14011 #define TSC_CR_SSD_Pos (17U)
14012 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
14013 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
14014 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
14015 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
14016 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
14017 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
14018 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
14019 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
14020 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
14021
14022 #define TSC_CR_CTPL_Pos (24U)
14023 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
14024 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
14025 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
14026 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
14027 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
14028 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
14029
14030 #define TSC_CR_CTPH_Pos (28U)
14031 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
14032 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
14033 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
14034 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
14035 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
14036 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
14037
14038 /******************* Bit definition for TSC_IER register ********************/
14039 #define TSC_IER_EOAIE_Pos (0U)
14040 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
14041 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
14042 #define TSC_IER_MCEIE_Pos (1U)
14043 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
14044 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
14045
14046 /******************* Bit definition for TSC_ICR register ********************/
14047 #define TSC_ICR_EOAIC_Pos (0U)
14048 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
14049 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
14050 #define TSC_ICR_MCEIC_Pos (1U)
14051 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
14052 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
14053
14054 /******************* Bit definition for TSC_ISR register ********************/
14055 #define TSC_ISR_EOAF_Pos (0U)
14056 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
14057 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
14058 #define TSC_ISR_MCEF_Pos (1U)
14059 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
14060 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
14061
14062 /******************* Bit definition for TSC_IOHCR register ******************/
14063 #define TSC_IOHCR_G1_IO1_Pos (0U)
14064 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
14065 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
14066 #define TSC_IOHCR_G1_IO2_Pos (1U)
14067 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
14068 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
14069 #define TSC_IOHCR_G1_IO3_Pos (2U)
14070 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
14071 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
14072 #define TSC_IOHCR_G1_IO4_Pos (3U)
14073 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
14074 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
14075 #define TSC_IOHCR_G2_IO1_Pos (4U)
14076 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
14077 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
14078 #define TSC_IOHCR_G2_IO2_Pos (5U)
14079 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
14080 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
14081 #define TSC_IOHCR_G2_IO3_Pos (6U)
14082 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
14083 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
14084 #define TSC_IOHCR_G2_IO4_Pos (7U)
14085 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
14086 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
14087 #define TSC_IOHCR_G3_IO1_Pos (8U)
14088 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
14089 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
14090 #define TSC_IOHCR_G3_IO2_Pos (9U)
14091 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
14092 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
14093 #define TSC_IOHCR_G3_IO3_Pos (10U)
14094 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
14095 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
14096 #define TSC_IOHCR_G3_IO4_Pos (11U)
14097 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
14098 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
14099 #define TSC_IOHCR_G4_IO1_Pos (12U)
14100 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
14101 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
14102 #define TSC_IOHCR_G4_IO2_Pos (13U)
14103 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
14104 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
14105 #define TSC_IOHCR_G4_IO3_Pos (14U)
14106 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
14107 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
14108 #define TSC_IOHCR_G4_IO4_Pos (15U)
14109 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
14110 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
14111 #define TSC_IOHCR_G5_IO1_Pos (16U)
14112 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
14113 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
14114 #define TSC_IOHCR_G5_IO2_Pos (17U)
14115 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
14116 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
14117 #define TSC_IOHCR_G5_IO3_Pos (18U)
14118 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
14119 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
14120 #define TSC_IOHCR_G5_IO4_Pos (19U)
14121 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
14122 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
14123 #define TSC_IOHCR_G6_IO1_Pos (20U)
14124 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
14125 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
14126 #define TSC_IOHCR_G6_IO2_Pos (21U)
14127 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
14128 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
14129 #define TSC_IOHCR_G6_IO3_Pos (22U)
14130 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
14131 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
14132 #define TSC_IOHCR_G6_IO4_Pos (23U)
14133 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
14134 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
14135 #define TSC_IOHCR_G7_IO1_Pos (24U)
14136 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
14137 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
14138 #define TSC_IOHCR_G7_IO2_Pos (25U)
14139 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
14140 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
14141 #define TSC_IOHCR_G7_IO3_Pos (26U)
14142 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
14143 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
14144 #define TSC_IOHCR_G7_IO4_Pos (27U)
14145 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
14146 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
14147
14148 /******************* Bit definition for TSC_IOASCR register *****************/
14149 #define TSC_IOASCR_G1_IO1_Pos (0U)
14150 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
14151 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
14152 #define TSC_IOASCR_G1_IO2_Pos (1U)
14153 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
14154 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
14155 #define TSC_IOASCR_G1_IO3_Pos (2U)
14156 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
14157 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
14158 #define TSC_IOASCR_G1_IO4_Pos (3U)
14159 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
14160 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
14161 #define TSC_IOASCR_G2_IO1_Pos (4U)
14162 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
14163 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
14164 #define TSC_IOASCR_G2_IO2_Pos (5U)
14165 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
14166 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
14167 #define TSC_IOASCR_G2_IO3_Pos (6U)
14168 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
14169 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
14170 #define TSC_IOASCR_G2_IO4_Pos (7U)
14171 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
14172 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
14173 #define TSC_IOASCR_G3_IO1_Pos (8U)
14174 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
14175 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
14176 #define TSC_IOASCR_G3_IO2_Pos (9U)
14177 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
14178 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
14179 #define TSC_IOASCR_G3_IO3_Pos (10U)
14180 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
14181 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
14182 #define TSC_IOASCR_G3_IO4_Pos (11U)
14183 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
14184 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
14185 #define TSC_IOASCR_G4_IO1_Pos (12U)
14186 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
14187 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
14188 #define TSC_IOASCR_G4_IO2_Pos (13U)
14189 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
14190 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
14191 #define TSC_IOASCR_G4_IO3_Pos (14U)
14192 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
14193 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
14194 #define TSC_IOASCR_G4_IO4_Pos (15U)
14195 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
14196 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
14197 #define TSC_IOASCR_G5_IO1_Pos (16U)
14198 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
14199 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
14200 #define TSC_IOASCR_G5_IO2_Pos (17U)
14201 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
14202 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
14203 #define TSC_IOASCR_G5_IO3_Pos (18U)
14204 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
14205 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
14206 #define TSC_IOASCR_G5_IO4_Pos (19U)
14207 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
14208 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
14209 #define TSC_IOASCR_G6_IO1_Pos (20U)
14210 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
14211 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
14212 #define TSC_IOASCR_G6_IO2_Pos (21U)
14213 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
14214 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
14215 #define TSC_IOASCR_G6_IO3_Pos (22U)
14216 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
14217 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
14218 #define TSC_IOASCR_G6_IO4_Pos (23U)
14219 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
14220 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
14221 #define TSC_IOASCR_G7_IO1_Pos (24U)
14222 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
14223 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
14224 #define TSC_IOASCR_G7_IO2_Pos (25U)
14225 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
14226 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
14227 #define TSC_IOASCR_G7_IO3_Pos (26U)
14228 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
14229 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
14230 #define TSC_IOASCR_G7_IO4_Pos (27U)
14231 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
14232 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
14233
14234 /******************* Bit definition for TSC_IOSCR register ******************/
14235 #define TSC_IOSCR_G1_IO1_Pos (0U)
14236 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
14237 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
14238 #define TSC_IOSCR_G1_IO2_Pos (1U)
14239 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
14240 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
14241 #define TSC_IOSCR_G1_IO3_Pos (2U)
14242 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
14243 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
14244 #define TSC_IOSCR_G1_IO4_Pos (3U)
14245 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
14246 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
14247 #define TSC_IOSCR_G2_IO1_Pos (4U)
14248 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
14249 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
14250 #define TSC_IOSCR_G2_IO2_Pos (5U)
14251 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
14252 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
14253 #define TSC_IOSCR_G2_IO3_Pos (6U)
14254 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
14255 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
14256 #define TSC_IOSCR_G2_IO4_Pos (7U)
14257 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
14258 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
14259 #define TSC_IOSCR_G3_IO1_Pos (8U)
14260 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
14261 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
14262 #define TSC_IOSCR_G3_IO2_Pos (9U)
14263 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
14264 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
14265 #define TSC_IOSCR_G3_IO3_Pos (10U)
14266 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
14267 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
14268 #define TSC_IOSCR_G3_IO4_Pos (11U)
14269 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
14270 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
14271 #define TSC_IOSCR_G4_IO1_Pos (12U)
14272 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
14273 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
14274 #define TSC_IOSCR_G4_IO2_Pos (13U)
14275 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
14276 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
14277 #define TSC_IOSCR_G4_IO3_Pos (14U)
14278 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
14279 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
14280 #define TSC_IOSCR_G4_IO4_Pos (15U)
14281 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
14282 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
14283 #define TSC_IOSCR_G5_IO1_Pos (16U)
14284 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
14285 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
14286 #define TSC_IOSCR_G5_IO2_Pos (17U)
14287 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
14288 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
14289 #define TSC_IOSCR_G5_IO3_Pos (18U)
14290 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
14291 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
14292 #define TSC_IOSCR_G5_IO4_Pos (19U)
14293 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
14294 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
14295 #define TSC_IOSCR_G6_IO1_Pos (20U)
14296 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
14297 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
14298 #define TSC_IOSCR_G6_IO2_Pos (21U)
14299 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
14300 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
14301 #define TSC_IOSCR_G6_IO3_Pos (22U)
14302 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
14303 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
14304 #define TSC_IOSCR_G6_IO4_Pos (23U)
14305 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
14306 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
14307 #define TSC_IOSCR_G7_IO1_Pos (24U)
14308 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
14309 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
14310 #define TSC_IOSCR_G7_IO2_Pos (25U)
14311 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
14312 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
14313 #define TSC_IOSCR_G7_IO3_Pos (26U)
14314 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
14315 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
14316 #define TSC_IOSCR_G7_IO4_Pos (27U)
14317 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
14318 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
14319
14320 /******************* Bit definition for TSC_IOCCR register ******************/
14321 #define TSC_IOCCR_G1_IO1_Pos (0U)
14322 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
14323 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
14324 #define TSC_IOCCR_G1_IO2_Pos (1U)
14325 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
14326 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
14327 #define TSC_IOCCR_G1_IO3_Pos (2U)
14328 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
14329 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
14330 #define TSC_IOCCR_G1_IO4_Pos (3U)
14331 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
14332 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
14333 #define TSC_IOCCR_G2_IO1_Pos (4U)
14334 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
14335 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
14336 #define TSC_IOCCR_G2_IO2_Pos (5U)
14337 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
14338 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
14339 #define TSC_IOCCR_G2_IO3_Pos (6U)
14340 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
14341 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
14342 #define TSC_IOCCR_G2_IO4_Pos (7U)
14343 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
14344 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
14345 #define TSC_IOCCR_G3_IO1_Pos (8U)
14346 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
14347 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
14348 #define TSC_IOCCR_G3_IO2_Pos (9U)
14349 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
14350 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
14351 #define TSC_IOCCR_G3_IO3_Pos (10U)
14352 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
14353 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
14354 #define TSC_IOCCR_G3_IO4_Pos (11U)
14355 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
14356 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
14357 #define TSC_IOCCR_G4_IO1_Pos (12U)
14358 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
14359 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
14360 #define TSC_IOCCR_G4_IO2_Pos (13U)
14361 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
14362 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
14363 #define TSC_IOCCR_G4_IO3_Pos (14U)
14364 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
14365 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
14366 #define TSC_IOCCR_G4_IO4_Pos (15U)
14367 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
14368 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
14369 #define TSC_IOCCR_G5_IO1_Pos (16U)
14370 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
14371 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
14372 #define TSC_IOCCR_G5_IO2_Pos (17U)
14373 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
14374 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
14375 #define TSC_IOCCR_G5_IO3_Pos (18U)
14376 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
14377 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
14378 #define TSC_IOCCR_G5_IO4_Pos (19U)
14379 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
14380 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
14381 #define TSC_IOCCR_G6_IO1_Pos (20U)
14382 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
14383 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
14384 #define TSC_IOCCR_G6_IO2_Pos (21U)
14385 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
14386 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
14387 #define TSC_IOCCR_G6_IO3_Pos (22U)
14388 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
14389 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
14390 #define TSC_IOCCR_G6_IO4_Pos (23U)
14391 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
14392 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
14393 #define TSC_IOCCR_G7_IO1_Pos (24U)
14394 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
14395 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
14396 #define TSC_IOCCR_G7_IO2_Pos (25U)
14397 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
14398 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
14399 #define TSC_IOCCR_G7_IO3_Pos (26U)
14400 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
14401 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
14402 #define TSC_IOCCR_G7_IO4_Pos (27U)
14403 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
14404 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
14405
14406 /******************* Bit definition for TSC_IOGCSR register *****************/
14407 #define TSC_IOGCSR_G1E_Pos (0U)
14408 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
14409 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
14410 #define TSC_IOGCSR_G2E_Pos (1U)
14411 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
14412 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
14413 #define TSC_IOGCSR_G3E_Pos (2U)
14414 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
14415 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
14416 #define TSC_IOGCSR_G4E_Pos (3U)
14417 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
14418 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
14419 #define TSC_IOGCSR_G5E_Pos (4U)
14420 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
14421 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
14422 #define TSC_IOGCSR_G6E_Pos (5U)
14423 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
14424 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
14425 #define TSC_IOGCSR_G7E_Pos (6U)
14426 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
14427 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
14428 #define TSC_IOGCSR_G1S_Pos (16U)
14429 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
14430 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
14431 #define TSC_IOGCSR_G2S_Pos (17U)
14432 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
14433 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
14434 #define TSC_IOGCSR_G3S_Pos (18U)
14435 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
14436 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
14437 #define TSC_IOGCSR_G4S_Pos (19U)
14438 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
14439 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
14440 #define TSC_IOGCSR_G5S_Pos (20U)
14441 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
14442 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
14443 #define TSC_IOGCSR_G6S_Pos (21U)
14444 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
14445 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
14446 #define TSC_IOGCSR_G7S_Pos (22U)
14447 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
14448 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
14449
14450 /******************* Bit definition for TSC_IOGXCR register *****************/
14451 #define TSC_IOGXCR_CNT_Pos (0U)
14452 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
14453 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
14454
14455 /******************************************************************************/
14456 /* */
14457 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
14458 /* */
14459 /******************************************************************************/
14460
14461 /*
14462 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
14463 */
14464
14465 /* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
14466 #define USART_TCBGT_SUPPORT
14467
14468 /****************** Bit definition for USART_CR1 register *******************/
14469 #define USART_CR1_UE_Pos (0U)
14470 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
14471 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
14472 #define USART_CR1_UESM_Pos (1U)
14473 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
14474 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
14475 #define USART_CR1_RE_Pos (2U)
14476 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
14477 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
14478 #define USART_CR1_TE_Pos (3U)
14479 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
14480 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
14481 #define USART_CR1_IDLEIE_Pos (4U)
14482 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
14483 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
14484 #define USART_CR1_RXNEIE_Pos (5U)
14485 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
14486 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
14487 #define USART_CR1_TCIE_Pos (6U)
14488 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
14489 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
14490 #define USART_CR1_TXEIE_Pos (7U)
14491 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
14492 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
14493 #define USART_CR1_PEIE_Pos (8U)
14494 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
14495 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
14496 #define USART_CR1_PS_Pos (9U)
14497 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
14498 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
14499 #define USART_CR1_PCE_Pos (10U)
14500 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
14501 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
14502 #define USART_CR1_WAKE_Pos (11U)
14503 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
14504 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
14505 #define USART_CR1_M_Pos (12U)
14506 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
14507 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
14508 #define USART_CR1_M0_Pos (12U)
14509 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
14510 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
14511 #define USART_CR1_MME_Pos (13U)
14512 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
14513 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
14514 #define USART_CR1_CMIE_Pos (14U)
14515 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
14516 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
14517 #define USART_CR1_OVER8_Pos (15U)
14518 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
14519 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
14520 #define USART_CR1_DEDT_Pos (16U)
14521 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
14522 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
14523 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
14524 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
14525 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
14526 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
14527 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
14528 #define USART_CR1_DEAT_Pos (21U)
14529 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
14530 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
14531 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
14532 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
14533 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
14534 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
14535 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
14536 #define USART_CR1_RTOIE_Pos (26U)
14537 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
14538 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
14539 #define USART_CR1_EOBIE_Pos (27U)
14540 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
14541 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
14542 #define USART_CR1_M1_Pos (28U)
14543 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
14544 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
14545
14546 /****************** Bit definition for USART_CR2 register *******************/
14547 #define USART_CR2_ADDM7_Pos (4U)
14548 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
14549 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
14550 #define USART_CR2_LBDL_Pos (5U)
14551 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
14552 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
14553 #define USART_CR2_LBDIE_Pos (6U)
14554 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
14555 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
14556 #define USART_CR2_LBCL_Pos (8U)
14557 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
14558 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
14559 #define USART_CR2_CPHA_Pos (9U)
14560 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
14561 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
14562 #define USART_CR2_CPOL_Pos (10U)
14563 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
14564 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
14565 #define USART_CR2_CLKEN_Pos (11U)
14566 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
14567 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
14568 #define USART_CR2_STOP_Pos (12U)
14569 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
14570 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
14571 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
14572 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
14573 #define USART_CR2_LINEN_Pos (14U)
14574 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
14575 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
14576 #define USART_CR2_SWAP_Pos (15U)
14577 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
14578 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
14579 #define USART_CR2_RXINV_Pos (16U)
14580 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
14581 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
14582 #define USART_CR2_TXINV_Pos (17U)
14583 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
14584 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
14585 #define USART_CR2_DATAINV_Pos (18U)
14586 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
14587 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
14588 #define USART_CR2_MSBFIRST_Pos (19U)
14589 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
14590 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
14591 #define USART_CR2_ABREN_Pos (20U)
14592 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
14593 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
14594 #define USART_CR2_ABRMODE_Pos (21U)
14595 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
14596 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
14597 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
14598 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
14599 #define USART_CR2_RTOEN_Pos (23U)
14600 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
14601 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
14602 #define USART_CR2_ADD_Pos (24U)
14603 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
14604 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
14605
14606 /****************** Bit definition for USART_CR3 register *******************/
14607 #define USART_CR3_EIE_Pos (0U)
14608 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
14609 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
14610 #define USART_CR3_IREN_Pos (1U)
14611 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
14612 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
14613 #define USART_CR3_IRLP_Pos (2U)
14614 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
14615 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
14616 #define USART_CR3_HDSEL_Pos (3U)
14617 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
14618 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
14619 #define USART_CR3_NACK_Pos (4U)
14620 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
14621 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
14622 #define USART_CR3_SCEN_Pos (5U)
14623 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
14624 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
14625 #define USART_CR3_DMAR_Pos (6U)
14626 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
14627 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
14628 #define USART_CR3_DMAT_Pos (7U)
14629 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
14630 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
14631 #define USART_CR3_RTSE_Pos (8U)
14632 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
14633 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
14634 #define USART_CR3_CTSE_Pos (9U)
14635 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
14636 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
14637 #define USART_CR3_CTSIE_Pos (10U)
14638 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
14639 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
14640 #define USART_CR3_ONEBIT_Pos (11U)
14641 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
14642 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
14643 #define USART_CR3_OVRDIS_Pos (12U)
14644 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
14645 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
14646 #define USART_CR3_DDRE_Pos (13U)
14647 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
14648 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
14649 #define USART_CR3_DEM_Pos (14U)
14650 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
14651 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
14652 #define USART_CR3_DEP_Pos (15U)
14653 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
14654 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
14655 #define USART_CR3_SCARCNT_Pos (17U)
14656 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
14657 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
14658 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
14659 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
14660 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
14661 #define USART_CR3_WUS_Pos (20U)
14662 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
14663 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
14664 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
14665 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
14666 #define USART_CR3_WUFIE_Pos (22U)
14667 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
14668 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
14669 #define USART_CR3_TCBGTIE_Pos (24U)
14670 #define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
14671 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
14672
14673 /****************** Bit definition for USART_BRR register *******************/
14674 #define USART_BRR_DIV_FRACTION_Pos (0U)
14675 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
14676 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
14677 #define USART_BRR_DIV_MANTISSA_Pos (4U)
14678 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
14679 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
14680
14681 /****************** Bit definition for USART_GTPR register ******************/
14682 #define USART_GTPR_PSC_Pos (0U)
14683 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
14684 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
14685 #define USART_GTPR_GT_Pos (8U)
14686 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
14687 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
14688
14689
14690 /******************* Bit definition for USART_RTOR register *****************/
14691 #define USART_RTOR_RTO_Pos (0U)
14692 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
14693 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
14694 #define USART_RTOR_BLEN_Pos (24U)
14695 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
14696 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
14697
14698 /******************* Bit definition for USART_RQR register ******************/
14699 #define USART_RQR_ABRRQ_Pos (0U)
14700 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
14701 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
14702 #define USART_RQR_SBKRQ_Pos (1U)
14703 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
14704 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
14705 #define USART_RQR_MMRQ_Pos (2U)
14706 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
14707 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
14708 #define USART_RQR_RXFRQ_Pos (3U)
14709 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
14710 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
14711 #define USART_RQR_TXFRQ_Pos (4U)
14712 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
14713 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
14714
14715 /******************* Bit definition for USART_ISR register ******************/
14716 #define USART_ISR_PE_Pos (0U)
14717 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
14718 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
14719 #define USART_ISR_FE_Pos (1U)
14720 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
14721 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
14722 #define USART_ISR_NE_Pos (2U)
14723 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
14724 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
14725 #define USART_ISR_ORE_Pos (3U)
14726 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
14727 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
14728 #define USART_ISR_IDLE_Pos (4U)
14729 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
14730 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
14731 #define USART_ISR_RXNE_Pos (5U)
14732 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
14733 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
14734 #define USART_ISR_TC_Pos (6U)
14735 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
14736 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
14737 #define USART_ISR_TXE_Pos (7U)
14738 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
14739 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
14740 #define USART_ISR_LBDF_Pos (8U)
14741 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
14742 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
14743 #define USART_ISR_CTSIF_Pos (9U)
14744 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
14745 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
14746 #define USART_ISR_CTS_Pos (10U)
14747 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
14748 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
14749 #define USART_ISR_RTOF_Pos (11U)
14750 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
14751 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
14752 #define USART_ISR_EOBF_Pos (12U)
14753 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
14754 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
14755 #define USART_ISR_ABRE_Pos (14U)
14756 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
14757 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
14758 #define USART_ISR_ABRF_Pos (15U)
14759 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
14760 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
14761 #define USART_ISR_BUSY_Pos (16U)
14762 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
14763 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
14764 #define USART_ISR_CMF_Pos (17U)
14765 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
14766 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
14767 #define USART_ISR_SBKF_Pos (18U)
14768 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
14769 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
14770 #define USART_ISR_RWU_Pos (19U)
14771 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
14772 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
14773 #define USART_ISR_WUF_Pos (20U)
14774 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
14775 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
14776 #define USART_ISR_TEACK_Pos (21U)
14777 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
14778 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
14779 #define USART_ISR_REACK_Pos (22U)
14780 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
14781 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
14782 #define USART_ISR_TCBGT_Pos (25U)
14783 #define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
14784 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
14785
14786 /******************* Bit definition for USART_ICR register ******************/
14787 #define USART_ICR_PECF_Pos (0U)
14788 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
14789 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
14790 #define USART_ICR_FECF_Pos (1U)
14791 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
14792 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
14793 #define USART_ICR_NCF_Pos (2U)
14794 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
14795 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
14796 #define USART_ICR_ORECF_Pos (3U)
14797 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
14798 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
14799 #define USART_ICR_IDLECF_Pos (4U)
14800 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
14801 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
14802 #define USART_ICR_TCCF_Pos (6U)
14803 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
14804 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
14805 #define USART_ICR_TCBGTCF_Pos (7U)
14806 #define USART_ICR_TCBGTCF_Msk (0x1U << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
14807 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
14808 #define USART_ICR_LBDCF_Pos (8U)
14809 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
14810 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
14811 #define USART_ICR_CTSCF_Pos (9U)
14812 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
14813 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
14814 #define USART_ICR_RTOCF_Pos (11U)
14815 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
14816 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
14817 #define USART_ICR_EOBCF_Pos (12U)
14818 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
14819 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
14820 #define USART_ICR_CMCF_Pos (17U)
14821 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
14822 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
14823 #define USART_ICR_WUCF_Pos (20U)
14824 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
14825 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
14826
14827 /******************* Bit definition for USART_RDR register ******************/
14828 #define USART_RDR_RDR_Pos (0U)
14829 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
14830 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
14831
14832 /******************* Bit definition for USART_TDR register ******************/
14833 #define USART_TDR_TDR_Pos (0U)
14834 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
14835 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
14836
14837 /******************************************************************************/
14838 /* */
14839 /* VREFBUF */
14840 /* */
14841 /******************************************************************************/
14842 /******************* Bit definition for VREFBUF_CSR register ****************/
14843 #define VREFBUF_CSR_ENVR_Pos (0U)
14844 #define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
14845 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
14846 #define VREFBUF_CSR_HIZ_Pos (1U)
14847 #define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
14848 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
14849 #define VREFBUF_CSR_VRS_Pos (2U)
14850 #define VREFBUF_CSR_VRS_Msk (0x1U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
14851 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
14852 #define VREFBUF_CSR_VRR_Pos (3U)
14853 #define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
14854 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
14855
14856 /******************* Bit definition for VREFBUF_CCR register ******************/
14857 #define VREFBUF_CCR_TRIM_Pos (0U)
14858 #define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
14859 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
14860
14861 /******************************************************************************/
14862 /* */
14863 /* Window WATCHDOG */
14864 /* */
14865 /******************************************************************************/
14866 /******************* Bit definition for WWDG_CR register ********************/
14867 #define WWDG_CR_T_Pos (0U)
14868 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
14869 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
14870 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
14871 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
14872 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
14873 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
14874 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
14875 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
14876 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
14877
14878 #define WWDG_CR_WDGA_Pos (7U)
14879 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
14880 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
14881
14882 /******************* Bit definition for WWDG_CFR register *******************/
14883 #define WWDG_CFR_W_Pos (0U)
14884 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
14885 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
14886 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
14887 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
14888 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
14889 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
14890 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
14891 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
14892 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
14893
14894 #define WWDG_CFR_WDGTB_Pos (7U)
14895 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
14896 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
14897 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
14898 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
14899
14900 #define WWDG_CFR_EWI_Pos (9U)
14901 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
14902 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
14903
14904 /******************* Bit definition for WWDG_SR register ********************/
14905 #define WWDG_SR_EWIF_Pos (0U)
14906 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
14907 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
14908
14909
14910 /******************************************************************************/
14911 /* */
14912 /* Debug MCU */
14913 /* */
14914 /******************************************************************************/
14915 /******************** Bit definition for DBGMCU_IDCODE register *************/
14916 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
14917 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
14918 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
14919 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
14920 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
14921 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
14922
14923 /******************** Bit definition for DBGMCU_CR register *****************/
14924 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
14925 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
14926 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
14927 #define DBGMCU_CR_DBG_STOP_Pos (1U)
14928 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
14929 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
14930 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
14931 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
14932 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
14933 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
14934 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
14935 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
14936
14937 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
14938 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
14939 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
14940 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
14941 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
14942
14943 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
14944 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
14945 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
14946 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
14947 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
14948 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
14949 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
14950 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
14951 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
14952 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
14953 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
14954 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
14955 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
14956 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
14957 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
14958 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
14959 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
14960 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
14961 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
14962 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
14963 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
14964 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
14965 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
14966 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
14967 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
14968 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
14969 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
14970 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
14971 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
14972 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
14973 #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
14974 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
14975 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
14976 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
14977
14978 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
14979 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
14980 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos) /*!< 0x00000002 */
14981 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
14982 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
14983 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
14984 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
14985
14986 /******************** Bit definition for DBGMCU_APB2FZ register ************/
14987 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
14988 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
14989 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
14990 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
14991 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
14992 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
14993 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
14994 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
14995 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
14996
14997
14998 /**
14999 * @}
15000 */
15001
15002 /**
15003 * @}
15004 */
15005
15006 /** @addtogroup Exported_macros
15007 * @{
15008 */
15009
15010 /******************************* ADC Instances ********************************/
15011 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
15012
15013 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
15014
15015 /******************************** CAN Instances ******************************/
15016 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
15017
15018 /******************************** COMP Instances ******************************/
15019 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
15020 ((INSTANCE) == COMP2))
15021
15022 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
15023
15024 /******************** COMP Instances with window mode capability **************/
15025 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
15026
15027 /******************************* CRC Instances ********************************/
15028 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
15029
15030 /******************************* DAC Instances ********************************/
15031 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
15032
15033 /****************************** DFSDM Instances *******************************/
15034 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
15035 ((INSTANCE) == DFSDM1_Filter1))
15036
15037 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
15038 ((INSTANCE) == DFSDM1_Channel1) || \
15039 ((INSTANCE) == DFSDM1_Channel2) || \
15040 ((INSTANCE) == DFSDM1_Channel3))
15041
15042 /******************************** DMA Instances *******************************/
15043 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
15044 ((INSTANCE) == DMA1_Channel2) || \
15045 ((INSTANCE) == DMA1_Channel3) || \
15046 ((INSTANCE) == DMA1_Channel4) || \
15047 ((INSTANCE) == DMA1_Channel5) || \
15048 ((INSTANCE) == DMA1_Channel6) || \
15049 ((INSTANCE) == DMA1_Channel7) || \
15050 ((INSTANCE) == DMA2_Channel1) || \
15051 ((INSTANCE) == DMA2_Channel2) || \
15052 ((INSTANCE) == DMA2_Channel3) || \
15053 ((INSTANCE) == DMA2_Channel4) || \
15054 ((INSTANCE) == DMA2_Channel5) || \
15055 ((INSTANCE) == DMA2_Channel6) || \
15056 ((INSTANCE) == DMA2_Channel7))
15057
15058 /******************************* GPIO Instances *******************************/
15059 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
15060 ((INSTANCE) == GPIOB) || \
15061 ((INSTANCE) == GPIOC) || \
15062 ((INSTANCE) == GPIOD) || \
15063 ((INSTANCE) == GPIOE) || \
15064 ((INSTANCE) == GPIOH))
15065
15066 /******************************* GPIO AF Instances ****************************/
15067 /* On L4, all GPIO Bank support AF */
15068 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
15069
15070 /**************************** GPIO Lock Instances *****************************/
15071 /* On L4, all GPIO Bank support the Lock mechanism */
15072 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
15073
15074 /******************************** I2C Instances *******************************/
15075 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15076 ((INSTANCE) == I2C2) || \
15077 ((INSTANCE) == I2C3) || \
15078 ((INSTANCE) == I2C4))
15079
15080 /****************** I2C Instances : wakeup capability from stop modes *********/
15081 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
15082
15083 /****************************** OPAMP Instances *******************************/
15084 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
15085
15086 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
15087
15088 /******************************* QSPI Instances *******************************/
15089 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
15090
15091 /******************************* RNG Instances ********************************/
15092 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
15093
15094 /****************************** RTC Instances *********************************/
15095 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
15096
15097 /******************************** SAI Instances *******************************/
15098 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
15099 ((INSTANCE) == SAI1_Block_B))
15100
15101 /****************************** SDMMC Instances *******************************/
15102 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
15103
15104 /****************************** SMBUS Instances *******************************/
15105 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15106 ((INSTANCE) == I2C2) || \
15107 ((INSTANCE) == I2C3) || \
15108 ((INSTANCE) == I2C4))
15109
15110 /******************************** SPI Instances *******************************/
15111 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15112 ((INSTANCE) == SPI2) || \
15113 ((INSTANCE) == SPI3))
15114
15115 /****************** LPTIM Instances : All supported instances *****************/
15116 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
15117 ((INSTANCE) == LPTIM2))
15118
15119 /****************** TIM Instances : All supported instances *******************/
15120 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15121 ((INSTANCE) == TIM2) || \
15122 ((INSTANCE) == TIM3) || \
15123 ((INSTANCE) == TIM6) || \
15124 ((INSTANCE) == TIM15) || \
15125 ((INSTANCE) == TIM16))
15126
15127 /****************** TIM Instances : supporting 32 bits counter ****************/
15128 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
15129
15130 /****************** TIM Instances : supporting the break function *************/
15131 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15132 ((INSTANCE) == TIM15) || \
15133 ((INSTANCE) == TIM16))
15134
15135 /************** TIM Instances : supporting Break source selection *************/
15136 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15137 ((INSTANCE) == TIM15) || \
15138 ((INSTANCE) == TIM16))
15139
15140 /****************** TIM Instances : supporting 2 break inputs *****************/
15141 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
15142
15143 /************* TIM Instances : at least 1 capture/compare channel *************/
15144 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15145 ((INSTANCE) == TIM2) || \
15146 ((INSTANCE) == TIM3) || \
15147 ((INSTANCE) == TIM15) || \
15148 ((INSTANCE) == TIM16))
15149
15150 /************ TIM Instances : at least 2 capture/compare channels *************/
15151 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15152 ((INSTANCE) == TIM2) || \
15153 ((INSTANCE) == TIM3) || \
15154 ((INSTANCE) == TIM15))
15155
15156 /************ TIM Instances : at least 3 capture/compare channels *************/
15157 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15158 ((INSTANCE) == TIM2) || \
15159 ((INSTANCE) == TIM3))
15160
15161 /************ TIM Instances : at least 4 capture/compare channels *************/
15162 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15163 ((INSTANCE) == TIM2) || \
15164 ((INSTANCE) == TIM3))
15165
15166 /****************** TIM Instances : at least 5 capture/compare channels *******/
15167 #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
15168
15169 /****************** TIM Instances : at least 6 capture/compare channels *******/
15170 #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
15171
15172 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
15173 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15174 ((INSTANCE) == TIM15) || \
15175 ((INSTANCE) == TIM16))
15176
15177 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
15178 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15179 ((INSTANCE) == TIM2) || \
15180 ((INSTANCE) == TIM3) || \
15181 ((INSTANCE) == TIM6) || \
15182 ((INSTANCE) == TIM15) || \
15183 ((INSTANCE) == TIM16))
15184
15185 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
15186 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15187 ((INSTANCE) == TIM2) || \
15188 ((INSTANCE) == TIM3) || \
15189 ((INSTANCE) == TIM15) || \
15190 ((INSTANCE) == TIM16))
15191
15192 /******************** TIM Instances : DMA burst feature ***********************/
15193 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15194 ((INSTANCE) == TIM2) || \
15195 ((INSTANCE) == TIM3) || \
15196 ((INSTANCE) == TIM15) || \
15197 ((INSTANCE) == TIM16))
15198
15199 /******************* TIM Instances : output(s) available **********************/
15200 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15201 ((((INSTANCE) == TIM1) && \
15202 (((CHANNEL) == TIM_CHANNEL_1) || \
15203 ((CHANNEL) == TIM_CHANNEL_2) || \
15204 ((CHANNEL) == TIM_CHANNEL_3) || \
15205 ((CHANNEL) == TIM_CHANNEL_4) || \
15206 ((CHANNEL) == TIM_CHANNEL_5) || \
15207 ((CHANNEL) == TIM_CHANNEL_6))) \
15208 || \
15209 (((INSTANCE) == TIM2) && \
15210 (((CHANNEL) == TIM_CHANNEL_1) || \
15211 ((CHANNEL) == TIM_CHANNEL_2) || \
15212 ((CHANNEL) == TIM_CHANNEL_3) || \
15213 ((CHANNEL) == TIM_CHANNEL_4))) \
15214 || \
15215 (((INSTANCE) == TIM3) && \
15216 (((CHANNEL) == TIM_CHANNEL_1) || \
15217 ((CHANNEL) == TIM_CHANNEL_2) || \
15218 ((CHANNEL) == TIM_CHANNEL_3) || \
15219 ((CHANNEL) == TIM_CHANNEL_4))) \
15220 || \
15221 (((INSTANCE) == TIM15) && \
15222 (((CHANNEL) == TIM_CHANNEL_1) || \
15223 ((CHANNEL) == TIM_CHANNEL_2))) \
15224 || \
15225 (((INSTANCE) == TIM16) && \
15226 (((CHANNEL) == TIM_CHANNEL_1))))
15227
15228 /****************** TIM Instances : supporting complementary output(s) ********/
15229 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15230 ((((INSTANCE) == TIM1) && \
15231 (((CHANNEL) == TIM_CHANNEL_1) || \
15232 ((CHANNEL) == TIM_CHANNEL_2) || \
15233 ((CHANNEL) == TIM_CHANNEL_3))) \
15234 || \
15235 (((INSTANCE) == TIM15) && \
15236 ((CHANNEL) == TIM_CHANNEL_1)) \
15237 || \
15238 (((INSTANCE) == TIM16) && \
15239 ((CHANNEL) == TIM_CHANNEL_1)))
15240
15241 /****************** TIM Instances : supporting clock division *****************/
15242 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15243 ((INSTANCE) == TIM2) || \
15244 ((INSTANCE) == TIM3) || \
15245 ((INSTANCE) == TIM15) || \
15246 ((INSTANCE) == TIM16))
15247
15248 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15249 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15250 ((INSTANCE) == TIM2) || \
15251 ((INSTANCE) == TIM3) || \
15252 ((INSTANCE) == TIM15))
15253
15254 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15255 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15256 ((INSTANCE) == TIM2) || \
15257 ((INSTANCE) == TIM3))
15258
15259 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
15260 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15261 ((INSTANCE) == TIM2) || \
15262 ((INSTANCE) == TIM3) || \
15263 ((INSTANCE) == TIM15))
15264
15265 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
15266 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15267 ((INSTANCE) == TIM2) || \
15268 ((INSTANCE) == TIM3) || \
15269 ((INSTANCE) == TIM15))
15270
15271 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
15272 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
15273
15274 /****************** TIM Instances : supporting commutation event generation ***/
15275 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15276 ((INSTANCE) == TIM15) || \
15277 ((INSTANCE) == TIM16))
15278
15279 /****************** TIM Instances : supporting counting mode selection ********/
15280 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15281 ((INSTANCE) == TIM2) || \
15282 ((INSTANCE) == TIM3))
15283
15284 /****************** TIM Instances : supporting encoder interface **************/
15285 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15286 ((INSTANCE) == TIM2) || \
15287 ((INSTANCE) == TIM3))
15288
15289 /****************** TIM Instances : supporting Hall sensor interface **********/
15290 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15291 ((INSTANCE) == TIM2) || \
15292 ((INSTANCE) == TIM3))
15293
15294 /**************** TIM Instances : external trigger input available ************/
15295 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15296 ((INSTANCE) == TIM2) || \
15297 ((INSTANCE) == TIM3))
15298
15299 /************* TIM Instances : supporting ETR source selection ***************/
15300 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15301 ((INSTANCE) == TIM2) || \
15302 ((INSTANCE) == TIM3))
15303
15304 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
15305 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15306 ((INSTANCE) == TIM2) || \
15307 ((INSTANCE) == TIM3) || \
15308 ((INSTANCE) == TIM6) || \
15309 ((INSTANCE) == TIM15))
15310
15311 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15312 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15313 ((INSTANCE) == TIM2) || \
15314 ((INSTANCE) == TIM3) || \
15315 ((INSTANCE) == TIM15))
15316
15317 /****************** TIM Instances : supporting OCxREF clear *******************/
15318 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15319 ((INSTANCE) == TIM2) || \
15320 ((INSTANCE) == TIM3))
15321
15322 /****************** TIM Instances : remapping capability **********************/
15323 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15324 ((INSTANCE) == TIM2) || \
15325 ((INSTANCE) == TIM3) || \
15326 ((INSTANCE) == TIM15) || \
15327 ((INSTANCE) == TIM16))
15328
15329 /****************** TIM Instances : supporting repetition counter *************/
15330 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15331 ((INSTANCE) == TIM15) || \
15332 ((INSTANCE) == TIM16))
15333
15334 /****************** TIM Instances : supporting synchronization ****************/
15335 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
15336
15337 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
15338 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
15339
15340 /******************* TIM Instances : Timer input XOR function *****************/
15341 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15342 ((INSTANCE) == TIM2) || \
15343 ((INSTANCE) == TIM3) || \
15344 ((INSTANCE) == TIM15))
15345
15346 /****************************** TSC Instances *********************************/
15347 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
15348
15349 /******************** USART Instances : Synchronous mode **********************/
15350 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15351 ((INSTANCE) == USART2) || \
15352 ((INSTANCE) == USART3))
15353
15354 /******************** UART Instances : Asynchronous mode **********************/
15355 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15356 ((INSTANCE) == USART2) || \
15357 ((INSTANCE) == USART3) || \
15358 ((INSTANCE) == UART4))
15359
15360 /****************** UART Instances : Auto Baud Rate detection ****************/
15361 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15362 ((INSTANCE) == USART2) || \
15363 ((INSTANCE) == USART3) || \
15364 ((INSTANCE) == UART4))
15365
15366 /****************** UART Instances : Driver Enable *****************/
15367 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15368 ((INSTANCE) == USART2) || \
15369 ((INSTANCE) == USART3) || \
15370 ((INSTANCE) == UART4) || \
15371 ((INSTANCE) == LPUART1))
15372
15373 /******************** UART Instances : Half-Duplex mode **********************/
15374 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15375 ((INSTANCE) == USART2) || \
15376 ((INSTANCE) == USART3) || \
15377 ((INSTANCE) == UART4) || \
15378 ((INSTANCE) == LPUART1))
15379
15380 /****************** UART Instances : Hardware Flow control ********************/
15381 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15382 ((INSTANCE) == USART2) || \
15383 ((INSTANCE) == USART3) || \
15384 ((INSTANCE) == UART4) || \
15385 ((INSTANCE) == LPUART1))
15386
15387 /******************** UART Instances : LIN mode **********************/
15388 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15389 ((INSTANCE) == USART2) || \
15390 ((INSTANCE) == USART3) || \
15391 ((INSTANCE) == UART4))
15392
15393 /******************** UART Instances : Wake-up from Stop mode **********************/
15394 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15395 ((INSTANCE) == USART2) || \
15396 ((INSTANCE) == USART3) || \
15397 ((INSTANCE) == UART4) || \
15398 ((INSTANCE) == LPUART1))
15399
15400 /*********************** UART Instances : IRDA mode ***************************/
15401 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15402 ((INSTANCE) == USART2) || \
15403 ((INSTANCE) == USART3) || \
15404 ((INSTANCE) == UART4))
15405
15406 /********************* USART Instances : Smard card mode ***********************/
15407 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15408 ((INSTANCE) == USART2) || \
15409 ((INSTANCE) == USART3))
15410
15411 /******************** LPUART Instance *****************************************/
15412 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
15413
15414 /****************************** IWDG Instances ********************************/
15415 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15416
15417 /****************************** WWDG Instances ********************************/
15418 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15419
15420 /**
15421 * @}
15422 */
15423
15424
15425 /******************************************************************************/
15426 /* For a painless codes migration between the STM32L4xx device product */
15427 /* lines, the aliases defined below are put in place to overcome the */
15428 /* differences in the interrupt handlers and IRQn definitions. */
15429 /* No need to update developed interrupt code when moving across */
15430 /* product lines within the same STM32L4 Family */
15431 /******************************************************************************/
15432
15433 /* Aliases for __IRQn */
15434 #define ADC1_2_IRQn ADC1_IRQn
15435 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
15436 #define HASH_RNG_IRQn RNG_IRQn
15437 #define HASH_CRS_IRQn CRS_IRQn
15438 #define DFSDM0_IRQn DFSDM1_FLT0_IRQn
15439 #define DFSDM1_IRQn DFSDM1_FLT1_IRQn
15440
15441 /* Aliases for __IRQHandler */
15442 #define ADC1_2_IRQHandler ADC1_IRQHandler
15443 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
15444 #define HASH_RNG_IRQHandler RNG_IRQHandler
15445 #define HASH_CRS_IRQHandler CRS_IRQHandler
15446 #define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
15447 #define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
15448
15449 #ifdef __cplusplus
15450 }
15451 #endif /* __cplusplus */
15452
15453 #endif /* __STM32L451xx_H */
15454
15455 /**
15456 * @}
15457 */
15458
15459 /**
15460 * @}
15461 */
15462
15463 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/