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comparison l476rg-hal-test/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l471xx.h @ 0:32a3b1785697

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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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-1:000000000000 0:32a3b1785697
1 /**
2 ******************************************************************************
3 * @file stm32l471xx.h
4 * @author MCD Application Team
5 * @version V1.0.3
6 * @date 29-January-2016
7 * @brief CMSIS STM32L471xx Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral�s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 /** @addtogroup CMSIS_Device
45 * @{
46 */
47
48 /** @addtogroup stm32l471xx
49 * @{
50 */
51
52 #ifndef __STM32L471xx_H
53 #define __STM32L471xx_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif /* __cplusplus */
58
59 /** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63 /**
64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
65 */
66 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
67 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
68 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
70 #define __FPU_PRESENT 1 /*!< FPU present */
71
72 /**
73 * @}
74 */
75
76 /** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80 /**
81 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
88 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
98 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
102 RCC_IRQn = 5, /*!< RCC global Interrupt */
103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
108 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
109 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
110 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
111 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
112 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
113 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
114 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
115 ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */
116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
121 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
122 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
123 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
139 DFSDM3_IRQn = 42, /*!< SD Filter 3 global Interrupt */
140 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
141 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
142 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
144 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
145 FMC_IRQn = 48, /*!< FMC global Interrupt */
146 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
153 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
154 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
155 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
156 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
157 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
158 DFSDM0_IRQn = 61, /*!< SD Filter 0 global Interrupt */
159 DFSDM1_IRQn = 62, /*!< SD Filter 1 global Interrupt */
160 DFSDM2_IRQn = 63, /*!< SD Filter 2 global Interrupt */
161 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
162 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
163 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
164 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
165 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
166 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
167 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
168 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
169 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
170 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
171 SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
172 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
173 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
174 RNG_IRQn = 80, /*!< RNG global interrupt */
175 FPU_IRQn = 81 /*!< FPU global interrupt */
176 } IRQn_Type;
177
178 /**
179 * @}
180 */
181
182 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
183 #include "system_stm32l4xx.h"
184 #include <stdint.h>
185
186 /** @addtogroup Peripheral_registers_structures
187 * @{
188 */
189
190 /**
191 * @brief Analog to Digital Converter
192 */
193
194 typedef struct
195 {
196 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
197 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
198 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
199 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
200 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
201 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
202 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
203 uint32_t RESERVED1; /*!< Reserved, 0x1C */
204 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
205 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
206 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
207 uint32_t RESERVED2; /*!< Reserved, 0x2C */
208 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
209 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
210 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
211 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
212 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
213 uint32_t RESERVED3; /*!< Reserved, 0x44 */
214 uint32_t RESERVED4; /*!< Reserved, 0x48 */
215 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
216 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
217 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
218 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
219 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
220 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
221 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
222 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
223 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
224 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
225 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
226 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
227 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
228 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
229 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
230 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
231 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
232 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
233
234 } ADC_TypeDef;
235
236 typedef struct
237 {
238 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
239 uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
240 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
241 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
242 } ADC_Common_TypeDef;
243
244
245 /**
246 * @brief Controller Area Network TxMailBox
247 */
248
249 typedef struct
250 {
251 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
252 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
253 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
254 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
255 } CAN_TxMailBox_TypeDef;
256
257 /**
258 * @brief Controller Area Network FIFOMailBox
259 */
260
261 typedef struct
262 {
263 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
264 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
265 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
266 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
267 } CAN_FIFOMailBox_TypeDef;
268
269 /**
270 * @brief Controller Area Network FilterRegister
271 */
272
273 typedef struct
274 {
275 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
276 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
277 } CAN_FilterRegister_TypeDef;
278
279 /**
280 * @brief Controller Area Network
281 */
282
283 typedef struct
284 {
285 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
286 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
287 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
288 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
289 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
290 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
291 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
292 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
293 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
294 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
295 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
296 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
297 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
298 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
299 uint32_t RESERVED2; /*!< Reserved, 0x208 */
300 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
301 uint32_t RESERVED3; /*!< Reserved, 0x210 */
302 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
303 uint32_t RESERVED4; /*!< Reserved, 0x218 */
304 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
305 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
306 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
307 } CAN_TypeDef;
308
309
310 /**
311 * @brief Comparator
312 */
313
314 typedef struct
315 {
316 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
317 } COMP_TypeDef;
318
319 typedef struct
320 {
321 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
322 } COMP_Common_TypeDef;
323
324 /**
325 * @brief CRC calculation unit
326 */
327
328 typedef struct
329 {
330 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
331 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
332 uint8_t RESERVED0; /*!< Reserved, 0x05 */
333 uint16_t RESERVED1; /*!< Reserved, 0x06 */
334 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
335 uint32_t RESERVED2; /*!< Reserved, 0x0C */
336 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
337 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
338 } CRC_TypeDef;
339
340 /**
341 * @brief Digital to Analog Converter
342 */
343
344 typedef struct
345 {
346 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
347 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
348 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
349 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
350 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
351 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
352 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
353 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
354 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
355 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
356 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
357 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
358 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
359 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
360 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
361 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
362 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
363 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
364 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
365 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
366 } DAC_TypeDef;
367
368 /**
369 * @brief DFSDM module registers
370 */
371 typedef struct
372 {
373 __IO uint32_t CR1; /*!< DFSDM control register1, Address offset: 0x100 */
374 __IO uint32_t CR2; /*!< DFSDM control register2, Address offset: 0x104 */
375 __IO uint32_t ISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
376 __IO uint32_t ICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
377 __IO uint32_t JCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
378 __IO uint32_t FCR; /*!< DFSDM filter control register, Address offset: 0x114 */
379 __IO uint32_t JDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
380 __IO uint32_t RDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
381 __IO uint32_t AWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
382 __IO uint32_t AWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
383 __IO uint32_t AWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
384 __IO uint32_t AWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
385 __IO uint32_t EXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
386 __IO uint32_t EXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
387 __IO uint32_t CNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
388 } DFSDM_Filter_TypeDef;
389
390 /**
391 * @brief DFSDM channel configuration registers
392 */
393 typedef struct
394 {
395 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
396 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
397 __IO uint32_t AWSCDR; /*!< DFSDM channel analog watchdog and
398 short circuit detector register, Address offset: 0x08 */
399 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
400 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
401 } DFSDM_Channel_TypeDef;
402
403 /**
404 * @brief Debug MCU
405 */
406
407 typedef struct
408 {
409 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
410 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
411 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
412 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
413 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
414 } DBGMCU_TypeDef;
415
416
417 /**
418 * @brief DMA Controller
419 */
420
421 typedef struct
422 {
423 __IO uint32_t CCR; /*!< DMA channel x configuration register */
424 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
425 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
426 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
427 } DMA_Channel_TypeDef;
428
429 typedef struct
430 {
431 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
432 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
433 } DMA_TypeDef;
434
435 typedef struct
436 {
437 __IO uint32_t CSELR; /*!< DMA channel selection register */
438 } DMA_Request_TypeDef;
439
440 /* Legacy define */
441 #define DMA_request_TypeDef DMA_Request_TypeDef
442
443 /**
444 * @brief External Interrupt/Event Controller
445 */
446
447 typedef struct
448 {
449 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
450 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
451 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
452 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
453 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
454 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
455 uint32_t RESERVED1; /*!< Reserved, 0x18 */
456 uint32_t RESERVED2; /*!< Reserved, 0x1C */
457 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
458 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
459 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
460 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
461 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
462 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
463 } EXTI_TypeDef;
464
465
466 /**
467 * @brief Firewall
468 */
469
470 typedef struct
471 {
472 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
473 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
474 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
475 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
476 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
477 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
478 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
479 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
480 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
481 } FIREWALL_TypeDef;
482
483
484 /**
485 * @brief FLASH Registers
486 */
487
488 typedef struct
489 {
490 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
491 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
492 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
493 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
494 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
495 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
496 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
497 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
498 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
499 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
500 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
501 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
502 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
503 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
504 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
505 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
506 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
507 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
508 } FLASH_TypeDef;
509
510
511 /**
512 * @brief Flexible Memory Controller
513 */
514
515 typedef struct
516 {
517 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
518 } FMC_Bank1_TypeDef;
519
520 /**
521 * @brief Flexible Memory Controller Bank1E
522 */
523
524 typedef struct
525 {
526 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
527 } FMC_Bank1E_TypeDef;
528
529 /**
530 * @brief Flexible Memory Controller Bank3
531 */
532
533 typedef struct
534 {
535 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
536 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
537 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
538 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
539 uint32_t RESERVED0; /*!< Reserved, 0x90 */
540 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
541 } FMC_Bank3_TypeDef;
542
543 /**
544 * @brief General Purpose I/O
545 */
546
547 typedef struct
548 {
549 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
550 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
551 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
552 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
553 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
554 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
555 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
556 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
557 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
558 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
559 __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */
560
561 } GPIO_TypeDef;
562
563
564 /**
565 * @brief Inter-integrated Circuit Interface
566 */
567
568 typedef struct
569 {
570 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
571 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
572 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
573 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
574 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
575 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
576 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
577 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
578 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
579 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
580 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
581 } I2C_TypeDef;
582
583 /**
584 * @brief Independent WATCHDOG
585 */
586
587 typedef struct
588 {
589 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
590 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
591 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
592 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
593 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
594 } IWDG_TypeDef;
595
596 /**
597 * @brief LPTIMER
598 */
599 typedef struct
600 {
601 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
602 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
603 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
604 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
605 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
606 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
607 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
608 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
609 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
610 } LPTIM_TypeDef;
611
612
613 /**
614 * @brief Operational Amplifier (OPAMP)
615 */
616
617 typedef struct
618 {
619 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
620 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
621 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
622 } OPAMP_TypeDef;
623
624 typedef struct
625 {
626 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
627 } OPAMP_Common_TypeDef;
628
629 /**
630 * @brief Power Control
631 */
632
633 typedef struct
634 {
635 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
636 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
637 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
638 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
639 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
640 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
641 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
642 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
643 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
644 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
645 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
646 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
647 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
648 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
649 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
650 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
651 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
652 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
653 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
654 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
655 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
656 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
657 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
658 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
659 } PWR_TypeDef;
660
661
662 /**
663 * @brief QUAD Serial Peripheral Interface
664 */
665
666 typedef struct
667 {
668 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
669 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
670 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
671 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
672 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
673 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
674 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
675 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
676 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
677 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
678 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
679 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
680 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
681 } QUADSPI_TypeDef;
682
683
684 /**
685 * @brief Reset and Clock Control
686 */
687
688 typedef struct
689 {
690 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
691 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
692 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
693 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
694 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
695 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
696 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
697 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
698 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
699 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
700 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
701 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
702 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
703 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
704 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
705 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
706 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
707 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
708 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
709 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
710 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
711 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
712 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
713 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
714 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
715 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
716 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
717 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
718 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
719 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
720 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
721 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
722 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
723 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
724 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
725 __IO uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
726 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
727 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
728 } RCC_TypeDef;
729
730 /**
731 * @brief Real-Time Clock
732 */
733
734 typedef struct
735 {
736 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
737 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
738 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
739 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
740 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
741 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
742 uint32_t reserved; /*!< Reserved */
743 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
744 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
745 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
746 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
747 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
748 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
749 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
750 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
751 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
752 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
753 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
754 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
755 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
756 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
757 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
758 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
759 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
760 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
761 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
762 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
763 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
764 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
765 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
766 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
767 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
768 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
769 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
770 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
771 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
772 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
773 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
774 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
775 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
776 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
777 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
778 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
779 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
780 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
781 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
782 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
783 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
784 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
785 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
786 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
787 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
788 } RTC_TypeDef;
789
790
791 /**
792 * @brief Serial Audio Interface
793 */
794
795 typedef struct
796 {
797 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
798 } SAI_TypeDef;
799
800 typedef struct
801 {
802 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
803 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
804 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
805 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
806 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
807 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
808 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
809 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
810 } SAI_Block_TypeDef;
811
812
813 /**
814 * @brief Secure digital input/output Interface
815 */
816
817 typedef struct
818 {
819 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
820 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
821 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
822 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
823 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
824 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
825 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
826 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
827 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
828 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
829 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
830 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
831 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
832 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
833 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
834 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
835 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
836 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
837 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
838 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
839 } SDMMC_TypeDef;
840
841
842 /**
843 * @brief Serial Peripheral Interface
844 */
845
846 typedef struct
847 {
848 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
849 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
850 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
851 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
852 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
853 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
854 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
855 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
856 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
857 } SPI_TypeDef;
858
859
860 /**
861 * @brief Single Wire Protocol Master Interface SPWMI
862 */
863
864 typedef struct
865 {
866 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
867 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
868 uint32_t RESERVED1; /*!< Reserved, 0x08 */
869 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
870 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
871 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
872 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
873 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
874 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
875 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
876 } SWPMI_TypeDef;
877
878
879 /**
880 * @brief System configuration controller
881 */
882
883 typedef struct
884 {
885 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
886 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
887 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
888 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
889 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
890 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
891 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
892 } SYSCFG_TypeDef;
893
894
895 /**
896 * @brief TIM
897 */
898
899 typedef struct
900 {
901 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
902 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
903 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
904 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
905 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
906 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
907 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
908 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
909 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
910 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
911 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
912 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
913 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
914 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
915 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
916 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
917 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
918 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
919 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
920 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
921 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
922 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
923 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
924 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
925 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
926 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
927 } TIM_TypeDef;
928
929
930 /**
931 * @brief Touch Sensing Controller (TSC)
932 */
933
934 typedef struct
935 {
936 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
937 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
938 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
939 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
940 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
941 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
942 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
943 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
944 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
945 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
946 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
947 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
948 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
949 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
950 } TSC_TypeDef;
951
952 /**
953 * @brief Universal Synchronous Asynchronous Receiver Transmitter
954 */
955
956 typedef struct
957 {
958 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
959 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
960 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
961 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
962 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
963 uint16_t RESERVED2; /*!< Reserved, 0x12 */
964 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
965 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
966 uint16_t RESERVED3; /*!< Reserved, 0x1A */
967 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
968 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
969 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
970 uint16_t RESERVED4; /*!< Reserved, 0x26 */
971 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
972 uint16_t RESERVED5; /*!< Reserved, 0x2A */
973 } USART_TypeDef;
974
975 /**
976 * @brief VREFBUF
977 */
978
979 typedef struct
980 {
981 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
982 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
983 } VREFBUF_TypeDef;
984
985 /**
986 * @brief Window WATCHDOG
987 */
988
989 typedef struct
990 {
991 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
992 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
993 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
994 } WWDG_TypeDef;
995
996 /**
997 * @brief RNG
998 */
999
1000 typedef struct
1001 {
1002 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1003 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1004 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1005 } RNG_TypeDef;
1006
1007 /**
1008 * @}
1009 */
1010
1011 /** @addtogroup Peripheral_memory_map
1012 * @{
1013 */
1014 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
1015 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address*/
1016 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
1017 #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
1018 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address*/
1019 #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
1020 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
1021 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
1022 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
1023 #define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
1024
1025 /* Legacy defines */
1026 #define SRAM_BASE SRAM1_BASE
1027 #define SRAM_BB_BASE SRAM1_BB_BASE
1028
1029 #define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
1030 #define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
1031
1032 /*!< Peripheral memory map */
1033 #define APB1PERIPH_BASE PERIPH_BASE
1034 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1035 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1036 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
1037
1038 #define FMC_BANK1 FMC_BASE
1039 #define FMC_BANK1_1 FMC_BANK1
1040 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
1041 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
1042 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
1043 #define FMC_BANK3 (FMC_BASE + 0x20000000U)
1044
1045 /*!< APB1 peripherals */
1046 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1047 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1048 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1049 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1050 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1051 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1052 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1053 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1054 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1055 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1056 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1057 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1058 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1059 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1060 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1061 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1062 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1063 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1064 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1065 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1066 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1067 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
1068 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
1069 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
1070 #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
1071 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
1072 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
1073 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
1074 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
1075
1076
1077 /*!< APB2 peripherals */
1078 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
1079 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
1080 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
1081 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
1082 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
1083 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
1084 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
1085 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
1086 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1087 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
1088 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
1089 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
1090 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
1091 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
1092 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
1093 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1094 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1095 #define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
1096 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
1097 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
1098 #define DFSDM_BASE (APB2PERIPH_BASE + 0x6000U)
1099 #define DFSDM_Channel0_BASE (DFSDM_BASE + 0x00)
1100 #define DFSDM_Channel1_BASE (DFSDM_BASE + 0x20)
1101 #define DFSDM_Channel2_BASE (DFSDM_BASE + 0x40)
1102 #define DFSDM_Channel3_BASE (DFSDM_BASE + 0x60)
1103 #define DFSDM_Channel4_BASE (DFSDM_BASE + 0x80)
1104 #define DFSDM_Channel5_BASE (DFSDM_BASE + 0xA0)
1105 #define DFSDM_Channel6_BASE (DFSDM_BASE + 0xC0)
1106 #define DFSDM_Channel7_BASE (DFSDM_BASE + 0xE0)
1107 #define DFSDM_Filter0_BASE (DFSDM_BASE + 0x100)
1108 #define DFSDM_Filter1_BASE (DFSDM_BASE + 0x180)
1109 #define DFSDM_Filter2_BASE (DFSDM_BASE + 0x200)
1110 #define DFSDM_Filter3_BASE (DFSDM_BASE + 0x280)
1111
1112 /*!< AHB1 peripherals */
1113 #define DMA1_BASE (AHB1PERIPH_BASE)
1114 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
1115 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
1116 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
1117 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1118 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
1119
1120
1121 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
1122 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
1123 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
1124 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
1125 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
1126 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
1127 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
1128 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
1129
1130
1131 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
1132 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
1133 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
1134 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
1135 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
1136 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
1137 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
1138 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
1139
1140
1141 /*!< AHB2 peripherals */
1142 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
1143 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
1144 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
1145 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
1146 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
1147 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
1148 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
1149 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
1150
1151
1152 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
1153 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U)
1154 #define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U)
1155 #define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
1156
1157
1158 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
1159
1160 /*!< FMC Banks registers base address */
1161 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1162 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1163 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1164
1165 /* Debug MCU registers base address */
1166 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
1167
1168
1169 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
1170 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
1171 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
1172 /**
1173 * @}
1174 */
1175
1176 /** @addtogroup Peripheral_declaration
1177 * @{
1178 */
1179 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1180 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1181 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1182 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1183 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1184 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1185 #define RTC ((RTC_TypeDef *) RTC_BASE)
1186 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1187 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1188 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1189 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1190 #define USART2 ((USART_TypeDef *) USART2_BASE)
1191 #define USART3 ((USART_TypeDef *) USART3_BASE)
1192 #define UART4 ((USART_TypeDef *) UART4_BASE)
1193 #define UART5 ((USART_TypeDef *) UART5_BASE)
1194 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1195 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1196 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1197 #define CAN ((CAN_TypeDef *) CAN1_BASE)
1198 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1199 #define PWR ((PWR_TypeDef *) PWR_BASE)
1200 #define DAC ((DAC_TypeDef *) DAC1_BASE)
1201 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1202 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1203 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1204 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1205 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1206 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1207 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1208 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
1209 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1210
1211 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1212 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1213 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1214 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1215 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1216 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1217 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1218 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1219 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1220 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1221 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1222 #define USART1 ((USART_TypeDef *) USART1_BASE)
1223 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1224 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1225 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1226 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1227 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1228 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1229 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1230 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1231 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1232 #define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE)
1233 #define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE)
1234 #define DFSDM_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM_Channel2_BASE)
1235 #define DFSDM_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM_Channel3_BASE)
1236 #define DFSDM_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM_Channel4_BASE)
1237 #define DFSDM_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM_Channel5_BASE)
1238 #define DFSDM_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM_Channel6_BASE)
1239 #define DFSDM_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM_Channel7_BASE)
1240 #define DFSDM_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM_Filter0_BASE)
1241 #define DFSDM_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM_Filter1_BASE)
1242 #define DFSDM_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM_Filter2_BASE)
1243 #define DFSDM_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM_Filter3_BASE)
1244 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1245 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1246 #define RCC ((RCC_TypeDef *) RCC_BASE)
1247 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1248 #define CRC ((CRC_TypeDef *) CRC_BASE)
1249 #define TSC ((TSC_TypeDef *) TSC_BASE)
1250
1251 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1252 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1253 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1254 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1255 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1256 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1257 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1258 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1259 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1260 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1261 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1262 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1263 #define RNG ((RNG_TypeDef *) RNG_BASE)
1264
1265
1266 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1267 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1268 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1269 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1270 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1271 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1272 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1273 #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
1274
1275
1276 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1277 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1278 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1279 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1280 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1281 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1282 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1283 #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
1284
1285
1286 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1287 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1288 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1289
1290 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1291
1292 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1293
1294 /**
1295 * @}
1296 */
1297
1298 /** @addtogroup Exported_constants
1299 * @{
1300 */
1301
1302 /** @addtogroup Peripheral_Registers_Bits_Definition
1303 * @{
1304 */
1305
1306 /******************************************************************************/
1307 /* Peripheral Registers_Bits_Definition */
1308 /******************************************************************************/
1309
1310 /******************************************************************************/
1311 /* */
1312 /* Analog to Digital Converter */
1313 /* */
1314 /******************************************************************************/
1315
1316 /*
1317 * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
1318 */
1319 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1320
1321 /******************** Bit definition for ADC_ISR register *******************/
1322 #define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC ready flag */
1323 #define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling flag */
1324 #define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion flag */
1325 #define ADC_ISR_EOS ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions flag */
1326 #define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< ADC group regular overrun flag */
1327 #define ADC_ISR_JEOC ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion flag */
1328 #define ADC_ISR_JEOS ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions flag */
1329 #define ADC_ISR_AWD1 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 flag */
1330 #define ADC_ISR_AWD2 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 flag */
1331 #define ADC_ISR_AWD3 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 flag */
1332 #define ADC_ISR_JQOVF ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow flag */
1333
1334 /******************** Bit definition for ADC_IER register *******************/
1335 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC ready interrupt */
1336 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling interrupt */
1337 #define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion interrupt */
1338 #define ADC_IER_EOSIE ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions interrupt */
1339 #define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< ADC group regular overrun interrupt */
1340 #define ADC_IER_JEOCIE ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion interrupt */
1341 #define ADC_IER_JEOSIE ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions interrupt */
1342 #define ADC_IER_AWD1IE ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 interrupt */
1343 #define ADC_IER_AWD2IE ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 interrupt */
1344 #define ADC_IER_AWD3IE ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 interrupt */
1345 #define ADC_IER_JQOVFIE ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow interrupt */
1346
1347 /* Legacy defines */
1348 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1349 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1350 #define ADC_IER_EOC (ADC_IER_EOCIE)
1351 #define ADC_IER_EOS (ADC_IER_EOSIE)
1352 #define ADC_IER_OVR (ADC_IER_OVRIE)
1353 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
1354 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
1355 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1356 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1357 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1358 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1359
1360 /******************** Bit definition for ADC_CR register ********************/
1361 #define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable */
1362 #define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable */
1363 #define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC group regular conversion start */
1364 #define ADC_CR_JADSTART ((uint32_t)0x00000008U) /*!< ADC group injected conversion start */
1365 #define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC group regular conversion stop */
1366 #define ADC_CR_JADSTP ((uint32_t)0x00000020U) /*!< ADC group injected conversion stop */
1367 #define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC voltage regulator enable */
1368 #define ADC_CR_DEEPPWD ((uint32_t)0x20000000U) /*!< ADC deep power down enable */
1369 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000U) /*!< ADC differential mode for calibration */
1370 #define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */
1371
1372 /******************** Bit definition for ADC_CFGR register ******************/
1373 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001U) /*!< ADC DMA transfer enable */
1374 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002U) /*!< ADC DMA transfer configuration */
1375
1376 #define ADC_CFGR_RES ((uint32_t)0x00000018U) /*!< ADC data resolution */
1377 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008U) /*!< bit 0 */
1378 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010U) /*!< bit 1 */
1379
1380 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020U) /*!< ADC data alignement */
1381
1382 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0U) /*!< ADC group regular external trigger source */
1383 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1384 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1385 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1386 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1387
1388 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00U) /*!< ADC group regular external trigger polarity */
1389 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400U) /*!< bit 0 */
1390 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800U) /*!< bit 1 */
1391
1392 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000U) /*!< ADC group regular overrun configuration */
1393 #define ADC_CFGR_CONT ((uint32_t)0x00002000U) /*!< ADC group regular continuous conversion mode */
1394 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000U) /*!< ADC low power auto wait */
1395
1396 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000U) /*!< ADC group regular sequencer discontinuous mode */
1397
1398 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000U) /*!< ADC Discontinuous mode channel count */
1399 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000U) /*!< bit 0 */
1400 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000U) /*!< bit 1 */
1401 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000U) /*!< bit 2 */
1402
1403 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000U) /*!< ADC Discontinuous mode on injected channels */
1404 #define ADC_CFGR_JQM ((uint32_t)0x00200000U) /*!< ADC group injected contexts queue mode */
1405 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1406 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1407 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1408 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000U) /*!< ADC group injected automatic trigger mode */
1409
1410 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000U) /*!< ADC analog watchdog 1 monitored channel selection */
1411 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
1412 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
1413 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
1414 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
1415 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
1416
1417 #define ADC_CFGR_JQDIS ((uint32_t)0x80000000U) /*!< ADC group injected contexts queue disable */
1418
1419 /******************** Bit definition for ADC_CFGR2 register *****************/
1420 #define ADC_CFGR2_ROVSE ((uint32_t)0x00000001U) /*!< ADC oversampler enable on scope ADC group regular */
1421 #define ADC_CFGR2_JOVSE ((uint32_t)0x00000002U) /*!< ADC oversampler enable on scope ADC group injected */
1422
1423 #define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< ADC oversampling ratio */
1424 #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< bit 0 */
1425 #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< bit 1 */
1426 #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< bit 2 */
1427
1428 #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< ADC oversampling shift */
1429 #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< bit 0 */
1430 #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< bit 1 */
1431 #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< bit 2 */
1432 #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< bit 3 */
1433
1434 #define ADC_CFGR2_TROVS ((uint32_t)0x00000200U) /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1435 #define ADC_CFGR2_ROVSM ((uint32_t)0x00000400U) /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1436
1437 /******************** Bit definition for ADC_SMPR1 register *****************/
1438 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */
1439 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1440 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1441 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1442
1443 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */
1444 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008U) /*!< bit 0 */
1445 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010U) /*!< bit 1 */
1446 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020U) /*!< bit 2 */
1447
1448 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */
1449 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1450 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1451 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1452
1453 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */
1454 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200U) /*!< bit 0 */
1455 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400U) /*!< bit 1 */
1456 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800U) /*!< bit 2 */
1457
1458 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */
1459 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1460 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1461 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1462
1463 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */
1464 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000U) /*!< bit 0 */
1465 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000U) /*!< bit 1 */
1466 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000U) /*!< bit 2 */
1467
1468 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */
1469 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1470 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1471 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1472
1473 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */
1474 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000U) /*!< bit 0 */
1475 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000U) /*!< bit 1 */
1476 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000U) /*!< bit 2 */
1477
1478 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */
1479 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1480 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1481 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1482
1483 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */
1484 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000U) /*!< bit 0 */
1485 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000U) /*!< bit 1 */
1486 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000U) /*!< bit 2 */
1487
1488 /******************** Bit definition for ADC_SMPR2 register *****************/
1489 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */
1490 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1491 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1492 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1493
1494 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */
1495 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< bit 0 */
1496 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< bit 1 */
1497 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< bit 2 */
1498
1499 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */
1500 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1501 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1502 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1503
1504 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */
1505 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< bit 0 */
1506 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< bit 1 */
1507 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< bit 2 */
1508
1509 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */
1510 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1511 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1512 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1513
1514 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 15 sampling time selection */
1515 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< bit 0 */
1516 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< bit 1 */
1517 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< bit 2 */
1518
1519 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */
1520 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1521 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1522 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1523
1524 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */
1525 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< bit 0 */
1526 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< bit 1 */
1527 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< bit 2 */
1528
1529 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */
1530 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1531 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1532 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1533
1534 /******************** Bit definition for ADC_TR1 register *******************/
1535 #define ADC_TR1_LT1 ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */
1536 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1537 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1538 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1539 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1540 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1541 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1542 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1543 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1544 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1545 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1546 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1547 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1548
1549 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000U) /*!< ADC Analog watchdog 1 threshold high */
1550 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000U) /*!< bit 0 */
1551 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000U) /*!< bit 1 */
1552 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000U) /*!< bit 2 */
1553 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000U) /*!< bit 3 */
1554 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000U) /*!< bit 4 */
1555 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000U) /*!< bit 5 */
1556 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000U) /*!< bit 6 */
1557 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000U) /*!< bit 7 */
1558 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000U) /*!< bit 8 */
1559 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000U) /*!< bit 9 */
1560 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000U) /*!< bit 10 */
1561 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000U) /*!< bit 11 */
1562
1563 /******************** Bit definition for ADC_TR2 register *******************/
1564 #define ADC_TR2_LT2 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 2 threshold low */
1565 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1566 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1567 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1568 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1569 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1570 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1571 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1572 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1573
1574 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 2 threshold high */
1575 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000U) /*!< bit 0 */
1576 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000U) /*!< bit 1 */
1577 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000U) /*!< bit 2 */
1578 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000U) /*!< bit 3 */
1579 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000U) /*!< bit 4 */
1580 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000U) /*!< bit 5 */
1581 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000U) /*!< bit 6 */
1582 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000U) /*!< bit 7 */
1583
1584 /******************** Bit definition for ADC_TR3 register *******************/
1585 #define ADC_TR3_LT3 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 3 threshold low */
1586 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1587 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1588 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1589 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1590 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1591 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1592 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1593 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1594
1595 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 3 threshold high */
1596 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000U) /*!< bit 0 */
1597 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000U) /*!< bit 1 */
1598 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000U) /*!< bit 2 */
1599 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000U) /*!< bit 3 */
1600 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000U) /*!< bit 4 */
1601 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000U) /*!< bit 5 */
1602 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000U) /*!< bit 6 */
1603 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000U) /*!< bit 7 */
1604
1605 /******************** Bit definition for ADC_SQR1 register ******************/
1606 #define ADC_SQR1_L ((uint32_t)0x0000000FU) /*!< ADC group regular sequencer scan length */
1607 #define ADC_SQR1_L_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1608 #define ADC_SQR1_L_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1609 #define ADC_SQR1_L_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1610 #define ADC_SQR1_L_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1611
1612 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 1 */
1613 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1614 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1615 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1616 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1617 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400U) /*!< bit 4 */
1618
1619 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 2 */
1620 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1621 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1622 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1623 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000U) /*!< bit 3 */
1624 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000U) /*!< bit 4 */
1625
1626 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 3 */
1627 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1628 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1629 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1630 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000U) /*!< bit 3 */
1631 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000U) /*!< bit 4 */
1632
1633 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 4 */
1634 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1635 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1636 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1637 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000U) /*!< bit 3 */
1638 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000U) /*!< bit 4 */
1639
1640 /******************** Bit definition for ADC_SQR2 register ******************/
1641 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 5 */
1642 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1643 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1644 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1645 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1646 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1647
1648 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 6 */
1649 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1650 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1651 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1652 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1653 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400U) /*!< bit 4 */
1654
1655 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 7 */
1656 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1657 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1658 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1659 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000U) /*!< bit 3 */
1660 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000U) /*!< bit 4 */
1661
1662 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 8 */
1663 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1664 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1665 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1666 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000U) /*!< bit 3 */
1667 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000U) /*!< bit 4 */
1668
1669 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 9 */
1670 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1671 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1672 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1673 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000U) /*!< bit 3 */
1674 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000U) /*!< bit 4 */
1675
1676 /******************** Bit definition for ADC_SQR3 register ******************/
1677 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 10 */
1678 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1679 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1680 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1681 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1682 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1683
1684 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 11 */
1685 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1686 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1687 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1688 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1689 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400U) /*!< bit 4 */
1690
1691 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 12 */
1692 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1693 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1694 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1695 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000U) /*!< bit 3 */
1696 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000U) /*!< bit 4 */
1697
1698 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 13 */
1699 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1700 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1701 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1702 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000U) /*!< bit 3 */
1703 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000U) /*!< bit 4 */
1704
1705 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 14 */
1706 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1707 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1708 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1709 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000U) /*!< bit 3 */
1710 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000U) /*!< bit 4 */
1711
1712 /******************** Bit definition for ADC_SQR4 register ******************/
1713 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 15 */
1714 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1715 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1716 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1717 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1718 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010U) /*!<5 bit 4 */
1719
1720 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 16 */
1721 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1722 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1723 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1724 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1725 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400U) /*!< bit 4 */
1726
1727 /******************** Bit definition for ADC_DR register ********************/
1728 #define ADC_DR_RDATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */
1729 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1730 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1731 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1732 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1733 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1734 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1735 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1736 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1737 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1738 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1739 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1740 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1741 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
1742 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
1743 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
1744 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
1745
1746 /******************** Bit definition for ADC_JSQR register ******************/
1747 #define ADC_JSQR_JL ((uint32_t)0x00000003U) /*!< ADC group injected sequencer scan length */
1748 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1749 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1750
1751 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003CU) /*!< ADC group injected external trigger source */
1752 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004U) /*!< bit 0 */
1753 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008U) /*!< bit 1 */
1754 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010U) /*!< bit 2 */
1755 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020U) /*!< bit 3 */
1756
1757 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0U) /*!< ADC group injected external trigger polarity */
1758 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1759 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1760
1761 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00U) /*!< ADC group injected sequencer rank 1 */
1762 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100U) /*!< bit 0 */
1763 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200U) /*!< bit 1 */
1764 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400U) /*!< bit 2 */
1765 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800U) /*!< bit 3 */
1766 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000U) /*!< bit 4 */
1767
1768 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000U) /*!< ADC group injected sequencer rank 2 */
1769 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000U) /*!< bit 0 */
1770 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000U) /*!< bit 1 */
1771 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000U) /*!< bit 2 */
1772 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000U) /*!< bit 3 */
1773 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000U) /*!< bit 4 */
1774
1775 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000U) /*!< ADC group injected sequencer rank 3 */
1776 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000U) /*!< bit 0 */
1777 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000U) /*!< bit 1 */
1778 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000U) /*!< bit 2 */
1779 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000U) /*!< bit 3 */
1780 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000U) /*!< bit 4 */
1781
1782 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000U) /*!< ADC group injected sequencer rank 4 */
1783 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000U) /*!< bit 0 */
1784 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000U) /*!< bit 1 */
1785 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000U) /*!< bit 2 */
1786 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000U) /*!< bit 3 */
1787 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000U) /*!< bit 4 */
1788
1789
1790 /******************** Bit definition for ADC_OFR1 register ******************/
1791 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC offset number 1 offset level */
1792 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1793 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1794 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1795 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1796 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1797 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1798 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1799 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1800 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1801 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1802 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1803 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1804
1805 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 1 channel selection */
1806 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
1807 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
1808 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
1809 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
1810 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
1811
1812 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000U) /*!< ADC offset number 1 enable */
1813
1814 /******************** Bit definition for ADC_OFR2 register ******************/
1815 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC offset number 2 offset level */
1816 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1817 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1818 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1819 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1820 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1821 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1822 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1823 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1824 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1825 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1826 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1827 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1828
1829 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 2 channel selection */
1830 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
1831 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
1832 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
1833 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
1834 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
1835
1836 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000U) /*!< ADC offset number 2 enable */
1837
1838 /******************** Bit definition for ADC_OFR3 register ******************/
1839 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC offset number 3 offset level */
1840 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1841 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1842 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1843 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1844 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1845 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1846 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1847 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1848 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1849 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1850 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1851 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1852
1853 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 3 channel selection */
1854 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
1855 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
1856 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
1857 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
1858 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
1859
1860 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000U) /*!< ADC offset number 3 enable */
1861
1862 /******************** Bit definition for ADC_OFR4 register ******************/
1863 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC offset number 4 offset level */
1864 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1865 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1866 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1867 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1868 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1869 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1870 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1871 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1872 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1873 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1874 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1875 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1876
1877 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 4 channel selection */
1878 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
1879 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
1880 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
1881 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
1882 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
1883
1884 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000U) /*!< ADC offset number 4 enable */
1885
1886 /******************** Bit definition for ADC_JDR1 register ******************/
1887 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */
1888 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1889 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1890 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1891 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1892 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1893 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1894 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1895 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1896 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1897 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1898 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1899 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1900 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
1901 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
1902 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
1903 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
1904
1905 /******************** Bit definition for ADC_JDR2 register ******************/
1906 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */
1907 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1908 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1909 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1910 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1911 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1912 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1913 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1914 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1915 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1916 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1917 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1918 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1919 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
1920 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
1921 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
1922 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
1923
1924 /******************** Bit definition for ADC_JDR3 register ******************/
1925 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */
1926 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1927 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1928 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1929 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1930 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1931 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1932 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1933 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1934 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1935 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1936 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1937 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1938 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
1939 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
1940 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
1941 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
1942
1943 /******************** Bit definition for ADC_JDR4 register ******************/
1944 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */
1945 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1946 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1947 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1948 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1949 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1950 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1951 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1952 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1953 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1954 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1955 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1956 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1957 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
1958 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
1959 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
1960 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
1961
1962 /******************** Bit definition for ADC_AWD2CR register ****************/
1963 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 2 monitored channel selection */
1964 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 2 monitoring channel 0 */
1965 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 2 monitoring channel 1 */
1966 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 2 monitoring channel 2 */
1967 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 2 monitoring channel 3 */
1968 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 2 monitoring channel 4 */
1969 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 2 monitoring channel 5 */
1970 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 2 monitoring channel 6 */
1971 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 2 monitoring channel 7 */
1972 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 monitoring channel 8 */
1973 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 2 monitoring channel 9 */
1974 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 2 monitoring channel 10 */
1975 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 2 monitoring channel 11 */
1976 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 2 monitoring channel 12 */
1977 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 2 monitoring channel 13 */
1978 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 2 monitoring channel 14 */
1979 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 2 monitoring channel 15 */
1980 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 2 monitoring channel 16 */
1981 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 2 monitoring channel 17 */
1982 #define ADC_AWD2CR_AWD2CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 2 monitoring channel 18 */
1983
1984 /******************** Bit definition for ADC_AWD3CR register ****************/
1985 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 3 monitored channel selection */
1986 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 3 monitoring channel 0 */
1987 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 3 monitoring channel 1 */
1988 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 3 monitoring channel 2 */
1989 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 3 monitoring channel 3 */
1990 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 3 monitoring channel 4 */
1991 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 3 monitoring channel 5 */
1992 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 3 monitoring channel 6 */
1993 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 3 monitoring channel 7 */
1994 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 3 monitoring channel 8 */
1995 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 monitoring channel 9 */
1996 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 3 monitoring channel 10 */
1997 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 3 monitoring channel 11 */
1998 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 3 monitoring channel 12 */
1999 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 3 monitoring channel 13 */
2000 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 3 monitoring channel 14 */
2001 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 3 monitoring channel 15 */
2002 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 3 monitoring channel 16 */
2003 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 3 monitoring channel 17 */
2004 #define ADC_AWD3CR_AWD3CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 3 monitoring channel 18 */
2005
2006 /******************** Bit definition for ADC_DIFSEL register ****************/
2007 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFFU) /*!< ADC channel differential or single-ended mode */
2008 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2009 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2010 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2011 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2012 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2013 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2014 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2015 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2016 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2017 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2018 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2019 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2020 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00001000U) /*!< bit 12 */
2021 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00002000U) /*!< bit 13 */
2022 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00004000U) /*!< bit 14 */
2023 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00008000U) /*!< bit 15 */
2024 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00010000U) /*!< bit 16 */
2025 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00020000U) /*!< bit 17 */
2026 #define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00040000U) /*!< bit 18 */
2027
2028 /******************** Bit definition for ADC_CALFACT register ***************/
2029 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007FU) /*!< ADC calibration factor in single-ended mode */
2030 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2031 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2032 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2033 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2034 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2035 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2036 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2037
2038 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000U) /*!< ADC calibration factor in differential mode */
2039 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000U) /*!< bit 0 */
2040 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000U) /*!< bit 1 */
2041 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000U) /*!< bit 2 */
2042 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000U) /*!< bit 3 */
2043 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000U) /*!< bit 4 */
2044 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000U) /*!< bit 5 */
2045 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000U) /*!< bit 6 */
2046
2047 /************************* ADC Common registers *****************************/
2048 /******************** Bit definition for ADC_CSR register *******************/
2049 #define ADC_CSR_ADRDY_MST ((uint32_t)0x00000001U) /*!< ADC multimode master ready flag */
2050 #define ADC_CSR_EOSMP_MST ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of sampling flag */
2051 #define ADC_CSR_EOC_MST ((uint32_t)0x00000004U) /*!< ADC multimode master group regular end of unitary conversion flag */
2052 #define ADC_CSR_EOS_MST ((uint32_t)0x00000008U) /*!< ADC multimode master group regular end of sequence conversions flag */
2053 #define ADC_CSR_OVR_MST ((uint32_t)0x00000010U) /*!< ADC multimode master group regular overrun flag */
2054 #define ADC_CSR_JEOC_MST ((uint32_t)0x00000020U) /*!< ADC multimode master group injected end of unitary conversion flag */
2055 #define ADC_CSR_JEOS_MST ((uint32_t)0x00000040U) /*!< ADC multimode master group injected end of sequence conversions flag */
2056 #define ADC_CSR_AWD1_MST ((uint32_t)0x00000080U) /*!< ADC multimode master analog watchdog 1 flag */
2057 #define ADC_CSR_AWD2_MST ((uint32_t)0x00000100U) /*!< ADC multimode master analog watchdog 2 flag */
2058 #define ADC_CSR_AWD3_MST ((uint32_t)0x00000200U) /*!< ADC multimode master analog watchdog 3 flag */
2059 #define ADC_CSR_JQOVF_MST ((uint32_t)0x00000400U) /*!< ADC multimode master group injected contexts queue overflow flag */
2060
2061 #define ADC_CSR_ADRDY_SLV ((uint32_t)0x00010000U) /*!< ADC multimode slave ready flag */
2062 #define ADC_CSR_EOSMP_SLV ((uint32_t)0x00020000U) /*!< ADC multimode slave group regular end of sampling flag */
2063 #define ADC_CSR_EOC_SLV ((uint32_t)0x00040000U) /*!< ADC multimode slave group regular end of unitary conversion flag */
2064 #define ADC_CSR_EOS_SLV ((uint32_t)0x00080000U) /*!< ADC multimode slave group regular end of sequence conversions flag */
2065 #define ADC_CSR_OVR_SLV ((uint32_t)0x00100000U) /*!< ADC multimode slave group regular overrun flag */
2066 #define ADC_CSR_JEOC_SLV ((uint32_t)0x00200000U) /*!< ADC multimode slave group injected end of unitary conversion flag */
2067 #define ADC_CSR_JEOS_SLV ((uint32_t)0x00400000U) /*!< ADC multimode slave group injected end of sequence conversions flag */
2068 #define ADC_CSR_AWD1_SLV ((uint32_t)0x00800000U) /*!< ADC multimode slave analog watchdog 1 flag */
2069 #define ADC_CSR_AWD2_SLV ((uint32_t)0x01000000U) /*!< ADC multimode slave analog watchdog 2 flag */
2070 #define ADC_CSR_AWD3_SLV ((uint32_t)0x02000000U) /*!< ADC multimode slave analog watchdog 3 flag */
2071 #define ADC_CSR_JQOVF_SLV ((uint32_t)0x04000000U) /*!< ADC multimode slave group injected contexts queue overflow flag */
2072
2073 /******************** Bit definition for ADC_CCR register *******************/
2074 #define ADC_CCR_DUAL ((uint32_t)0x0000001FU) /*!< ADC multimode mode selection */
2075 #define ADC_CCR_DUAL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2076 #define ADC_CCR_DUAL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2077 #define ADC_CCR_DUAL_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2078 #define ADC_CCR_DUAL_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2079 #define ADC_CCR_DUAL_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2080
2081 #define ADC_CCR_DELAY ((uint32_t)0x00000F00U) /*!< ADC multimode delay between 2 sampling phases */
2082 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100U) /*!< bit 0 */
2083 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200U) /*!< bit 1 */
2084 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400U) /*!< bit 2 */
2085 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800U) /*!< bit 3 */
2086
2087 #define ADC_CCR_DMACFG ((uint32_t)0x00002000U) /*!< ADC multimode DMA transfer configuration */
2088
2089 #define ADC_CCR_MDMA ((uint32_t)0x0000C000U) /*!< ADC multimode DMA transfer enable */
2090 #define ADC_CCR_MDMA_0 ((uint32_t)0x00004000U) /*!< bit 0 */
2091 #define ADC_CCR_MDMA_1 ((uint32_t)0x00008000U) /*!< bit 1 */
2092
2093 #define ADC_CCR_CKMODE ((uint32_t)0x00030000U) /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2094 #define ADC_CCR_CKMODE_0 ((uint32_t)0x00010000U) /*!< bit 0 */
2095 #define ADC_CCR_CKMODE_1 ((uint32_t)0x00020000U) /*!< bit 1 */
2096
2097 #define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< ADC common clock prescaler, only for clock source asynchronous */
2098 #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< bit 0 */
2099 #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< bit 1 */
2100 #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< bit 2 */
2101 #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< bit 3 */
2102
2103 #define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< ADC internal path to VrefInt enable */
2104 #define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< ADC internal path to temperature sensor enable */
2105 #define ADC_CCR_VBATEN ((uint32_t)0x01000000U) /*!< ADC internal path to battery voltage enable */
2106
2107 /******************** Bit definition for ADC_CDR register *******************/
2108 #define ADC_CDR_RDATA_MST ((uint32_t)0x0000FFFFU) /*!< ADC multimode master group regular conversion data */
2109 #define ADC_CDR_RDATA_MST_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2110 #define ADC_CDR_RDATA_MST_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2111 #define ADC_CDR_RDATA_MST_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2112 #define ADC_CDR_RDATA_MST_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2113 #define ADC_CDR_RDATA_MST_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2114 #define ADC_CDR_RDATA_MST_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2115 #define ADC_CDR_RDATA_MST_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2116 #define ADC_CDR_RDATA_MST_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2117 #define ADC_CDR_RDATA_MST_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2118 #define ADC_CDR_RDATA_MST_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2119 #define ADC_CDR_RDATA_MST_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2120 #define ADC_CDR_RDATA_MST_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2121 #define ADC_CDR_RDATA_MST_12 ((uint32_t)0x00001000U) /*!< bit 12 */
2122 #define ADC_CDR_RDATA_MST_13 ((uint32_t)0x00002000U) /*!< bit 13 */
2123 #define ADC_CDR_RDATA_MST_14 ((uint32_t)0x00004000U) /*!< bit 14 */
2124 #define ADC_CDR_RDATA_MST_15 ((uint32_t)0x00008000U) /*!< bit 15 */
2125
2126 #define ADC_CDR_RDATA_SLV ((uint32_t)0xFFFF0000U) /*!< ADC multimode slave group regular conversion data */
2127 #define ADC_CDR_RDATA_SLV_0 ((uint32_t)0x00010000U) /*!< bit 0 */
2128 #define ADC_CDR_RDATA_SLV_1 ((uint32_t)0x00020000U) /*!< bit 1 */
2129 #define ADC_CDR_RDATA_SLV_2 ((uint32_t)0x00040000U) /*!< bit 2 */
2130 #define ADC_CDR_RDATA_SLV_3 ((uint32_t)0x00080000U) /*!< bit 3 */
2131 #define ADC_CDR_RDATA_SLV_4 ((uint32_t)0x00100000U) /*!< bit 4 */
2132 #define ADC_CDR_RDATA_SLV_5 ((uint32_t)0x00200000U) /*!< bit 5 */
2133 #define ADC_CDR_RDATA_SLV_6 ((uint32_t)0x00400000U) /*!< bit 6 */
2134 #define ADC_CDR_RDATA_SLV_7 ((uint32_t)0x00800000U) /*!< bit 7 */
2135 #define ADC_CDR_RDATA_SLV_8 ((uint32_t)0x01000000U) /*!< bit 8 */
2136 #define ADC_CDR_RDATA_SLV_9 ((uint32_t)0x02000000U) /*!< bit 9 */
2137 #define ADC_CDR_RDATA_SLV_10 ((uint32_t)0x04000000U) /*!< bit 10 */
2138 #define ADC_CDR_RDATA_SLV_11 ((uint32_t)0x08000000U) /*!< bit 11 */
2139 #define ADC_CDR_RDATA_SLV_12 ((uint32_t)0x10000000U) /*!< bit 12 */
2140 #define ADC_CDR_RDATA_SLV_13 ((uint32_t)0x20000000U) /*!< bit 13 */
2141 #define ADC_CDR_RDATA_SLV_14 ((uint32_t)0x40000000U) /*!< bit 14 */
2142 #define ADC_CDR_RDATA_SLV_15 ((uint32_t)0x80000000U) /*!< bit 15 */
2143
2144 /******************************************************************************/
2145 /* */
2146 /* Controller Area Network */
2147 /* */
2148 /******************************************************************************/
2149 /*!<CAN control and status registers */
2150 /******************* Bit definition for CAN_MCR register ********************/
2151 #define CAN_MCR_INRQ ((uint16_t)0x0001U) /*!<Initialization Request */
2152 #define CAN_MCR_SLEEP ((uint16_t)0x0002U) /*!<Sleep Mode Request */
2153 #define CAN_MCR_TXFP ((uint16_t)0x0004U) /*!<Transmit FIFO Priority */
2154 #define CAN_MCR_RFLM ((uint16_t)0x0008U) /*!<Receive FIFO Locked Mode */
2155 #define CAN_MCR_NART ((uint16_t)0x0010U) /*!<No Automatic Retransmission */
2156 #define CAN_MCR_AWUM ((uint16_t)0x0020U) /*!<Automatic Wakeup Mode */
2157 #define CAN_MCR_ABOM ((uint16_t)0x0040U) /*!<Automatic Bus-Off Management */
2158 #define CAN_MCR_TTCM ((uint16_t)0x0080U) /*!<Time Triggered Communication Mode */
2159 #define CAN_MCR_RESET ((uint16_t)0x8000U) /*!<bxCAN software master reset */
2160
2161 /******************* Bit definition for CAN_MSR register ********************/
2162 #define CAN_MSR_INAK ((uint16_t)0x0001U) /*!<Initialization Acknowledge */
2163 #define CAN_MSR_SLAK ((uint16_t)0x0002U) /*!<Sleep Acknowledge */
2164 #define CAN_MSR_ERRI ((uint16_t)0x0004U) /*!<Error Interrupt */
2165 #define CAN_MSR_WKUI ((uint16_t)0x0008U) /*!<Wakeup Interrupt */
2166 #define CAN_MSR_SLAKI ((uint16_t)0x0010U) /*!<Sleep Acknowledge Interrupt */
2167 #define CAN_MSR_TXM ((uint16_t)0x0100U) /*!<Transmit Mode */
2168 #define CAN_MSR_RXM ((uint16_t)0x0200U) /*!<Receive Mode */
2169 #define CAN_MSR_SAMP ((uint16_t)0x0400U) /*!<Last Sample Point */
2170 #define CAN_MSR_RX ((uint16_t)0x0800U) /*!<CAN Rx Signal */
2171
2172 /******************* Bit definition for CAN_TSR register ********************/
2173 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001U) /*!<Request Completed Mailbox0 */
2174 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002U) /*!<Transmission OK of Mailbox0 */
2175 #define CAN_TSR_ALST0 ((uint32_t)0x00000004U) /*!<Arbitration Lost for Mailbox0 */
2176 #define CAN_TSR_TERR0 ((uint32_t)0x00000008U) /*!<Transmission Error of Mailbox0 */
2177 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080U) /*!<Abort Request for Mailbox0 */
2178 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100U) /*!<Request Completed Mailbox1 */
2179 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200U) /*!<Transmission OK of Mailbox1 */
2180 #define CAN_TSR_ALST1 ((uint32_t)0x00000400U) /*!<Arbitration Lost for Mailbox1 */
2181 #define CAN_TSR_TERR1 ((uint32_t)0x00000800U) /*!<Transmission Error of Mailbox1 */
2182 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000U) /*!<Abort Request for Mailbox 1 */
2183 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000U) /*!<Request Completed Mailbox2 */
2184 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000U) /*!<Transmission OK of Mailbox 2 */
2185 #define CAN_TSR_ALST2 ((uint32_t)0x00040000U) /*!<Arbitration Lost for mailbox 2 */
2186 #define CAN_TSR_TERR2 ((uint32_t)0x00080000U) /*!<Transmission Error of Mailbox 2 */
2187 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000U) /*!<Abort Request for Mailbox 2 */
2188 #define CAN_TSR_CODE ((uint32_t)0x03000000U) /*!<Mailbox Code */
2189
2190 #define CAN_TSR_TME ((uint32_t)0x1C000000U) /*!<TME[2:0] bits */
2191 #define CAN_TSR_TME0 ((uint32_t)0x04000000U) /*!<Transmit Mailbox 0 Empty */
2192 #define CAN_TSR_TME1 ((uint32_t)0x08000000U) /*!<Transmit Mailbox 1 Empty */
2193 #define CAN_TSR_TME2 ((uint32_t)0x10000000U) /*!<Transmit Mailbox 2 Empty */
2194
2195 #define CAN_TSR_LOW ((uint32_t)0xE0000000U) /*!<LOW[2:0] bits */
2196 #define CAN_TSR_LOW0 ((uint32_t)0x20000000U) /*!<Lowest Priority Flag for Mailbox 0 */
2197 #define CAN_TSR_LOW1 ((uint32_t)0x40000000U) /*!<Lowest Priority Flag for Mailbox 1 */
2198 #define CAN_TSR_LOW2 ((uint32_t)0x80000000U) /*!<Lowest Priority Flag for Mailbox 2 */
2199
2200 /******************* Bit definition for CAN_RF0R register *******************/
2201 #define CAN_RF0R_FMP0 ((uint8_t)0x03U) /*!<FIFO 0 Message Pending */
2202 #define CAN_RF0R_FULL0 ((uint8_t)0x08U) /*!<FIFO 0 Full */
2203 #define CAN_RF0R_FOVR0 ((uint8_t)0x10U) /*!<FIFO 0 Overrun */
2204 #define CAN_RF0R_RFOM0 ((uint8_t)0x20U) /*!<Release FIFO 0 Output Mailbox */
2205
2206 /******************* Bit definition for CAN_RF1R register *******************/
2207 #define CAN_RF1R_FMP1 ((uint8_t)0x03U) /*!<FIFO 1 Message Pending */
2208 #define CAN_RF1R_FULL1 ((uint8_t)0x08U) /*!<FIFO 1 Full */
2209 #define CAN_RF1R_FOVR1 ((uint8_t)0x10U) /*!<FIFO 1 Overrun */
2210 #define CAN_RF1R_RFOM1 ((uint8_t)0x20U) /*!<Release FIFO 1 Output Mailbox */
2211
2212 /******************** Bit definition for CAN_IER register *******************/
2213 #define CAN_IER_TMEIE ((uint32_t)0x00000001U) /*!<Transmit Mailbox Empty Interrupt Enable */
2214 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002U) /*!<FIFO Message Pending Interrupt Enable */
2215 #define CAN_IER_FFIE0 ((uint32_t)0x00000004U) /*!<FIFO Full Interrupt Enable */
2216 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008U) /*!<FIFO Overrun Interrupt Enable */
2217 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010U) /*!<FIFO Message Pending Interrupt Enable */
2218 #define CAN_IER_FFIE1 ((uint32_t)0x00000020U) /*!<FIFO Full Interrupt Enable */
2219 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040U) /*!<FIFO Overrun Interrupt Enable */
2220 #define CAN_IER_EWGIE ((uint32_t)0x00000100U) /*!<Error Warning Interrupt Enable */
2221 #define CAN_IER_EPVIE ((uint32_t)0x00000200U) /*!<Error Passive Interrupt Enable */
2222 #define CAN_IER_BOFIE ((uint32_t)0x00000400U) /*!<Bus-Off Interrupt Enable */
2223 #define CAN_IER_LECIE ((uint32_t)0x00000800U) /*!<Last Error Code Interrupt Enable */
2224 #define CAN_IER_ERRIE ((uint32_t)0x00008000U) /*!<Error Interrupt Enable */
2225 #define CAN_IER_WKUIE ((uint32_t)0x00010000U) /*!<Wakeup Interrupt Enable */
2226 #define CAN_IER_SLKIE ((uint32_t)0x00020000U) /*!<Sleep Interrupt Enable */
2227
2228 /******************** Bit definition for CAN_ESR register *******************/
2229 #define CAN_ESR_EWGF ((uint32_t)0x00000001U) /*!<Error Warning Flag */
2230 #define CAN_ESR_EPVF ((uint32_t)0x00000002U) /*!<Error Passive Flag */
2231 #define CAN_ESR_BOFF ((uint32_t)0x00000004U) /*!<Bus-Off Flag */
2232
2233 #define CAN_ESR_LEC ((uint32_t)0x00000070U) /*!<LEC[2:0] bits (Last Error Code) */
2234 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
2235 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
2236 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
2237
2238 #define CAN_ESR_TEC ((uint32_t)0x00FF0000U) /*!<Least significant byte of the 9-bit Transmit Error Counter */
2239 #define CAN_ESR_REC ((uint32_t)0xFF000000U) /*!<Receive Error Counter */
2240
2241 /******************* Bit definition for CAN_BTR register ********************/
2242 #define CAN_BTR_BRP ((uint32_t)0x000003FFU) /*!<Baud Rate Prescaler */
2243 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000U) /*!<Time Segment 1 (Bit 0) */
2244 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000U) /*!<Time Segment 1 (Bit 1) */
2245 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000U) /*!<Time Segment 1 (Bit 2) */
2246 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000U) /*!<Time Segment 1 (Bit 3) */
2247 #define CAN_BTR_TS1 ((uint32_t)0x000F0000U) /*!<Time Segment 1 */
2248 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000U) /*!<Time Segment 2 (Bit 0) */
2249 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000U) /*!<Time Segment 2 (Bit 1) */
2250 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000U) /*!<Time Segment 2 (Bit 2) */
2251 #define CAN_BTR_TS2 ((uint32_t)0x00700000U) /*!<Time Segment 2 */
2252 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000U) /*!<Resynchronization Jump Width (Bit 0) */
2253 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000U) /*!<Resynchronization Jump Width (Bit 1) */
2254 #define CAN_BTR_SJW ((uint32_t)0x03000000U) /*!<Resynchronization Jump Width */
2255 #define CAN_BTR_LBKM ((uint32_t)0x40000000U) /*!<Loop Back Mode (Debug) */
2256 #define CAN_BTR_SILM ((uint32_t)0x80000000U) /*!<Silent Mode */
2257
2258 /*!<Mailbox registers */
2259 /****************** Bit definition for CAN_TI0R register ********************/
2260 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
2261 #define CAN_TI0R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2262 #define CAN_TI0R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2263 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
2264 #define CAN_TI0R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2265
2266 /****************** Bit definition for CAN_TDT0R register *******************/
2267 #define CAN_TDT0R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2268 #define CAN_TDT0R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
2269 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2270
2271 /****************** Bit definition for CAN_TDL0R register *******************/
2272 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2273 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2274 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2275 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2276
2277 /****************** Bit definition for CAN_TDH0R register *******************/
2278 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2279 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2280 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2281 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2282
2283 /******************* Bit definition for CAN_TI1R register *******************/
2284 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
2285 #define CAN_TI1R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2286 #define CAN_TI1R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2287 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
2288 #define CAN_TI1R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2289
2290 /******************* Bit definition for CAN_TDT1R register ******************/
2291 #define CAN_TDT1R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2292 #define CAN_TDT1R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
2293 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2294
2295 /******************* Bit definition for CAN_TDL1R register ******************/
2296 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2297 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2298 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2299 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2300
2301 /******************* Bit definition for CAN_TDH1R register ******************/
2302 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2303 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2304 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2305 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2306
2307 /******************* Bit definition for CAN_TI2R register *******************/
2308 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
2309 #define CAN_TI2R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2310 #define CAN_TI2R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2311 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended identifier */
2312 #define CAN_TI2R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2313
2314 /******************* Bit definition for CAN_TDT2R register ******************/
2315 #define CAN_TDT2R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2316 #define CAN_TDT2R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
2317 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2318
2319 /******************* Bit definition for CAN_TDL2R register ******************/
2320 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2321 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2322 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2323 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2324
2325 /******************* Bit definition for CAN_TDH2R register ******************/
2326 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2327 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2328 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2329 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2330
2331 /******************* Bit definition for CAN_RI0R register *******************/
2332 #define CAN_RI0R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2333 #define CAN_RI0R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2334 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
2335 #define CAN_RI0R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2336
2337 /******************* Bit definition for CAN_RDT0R register ******************/
2338 #define CAN_RDT0R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2339 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00U) /*!<Filter Match Index */
2340 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2341
2342 /******************* Bit definition for CAN_RDL0R register ******************/
2343 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2344 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2345 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2346 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2347
2348 /******************* Bit definition for CAN_RDH0R register ******************/
2349 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2350 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2351 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2352 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2353
2354 /******************* Bit definition for CAN_RI1R register *******************/
2355 #define CAN_RI1R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2356 #define CAN_RI1R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2357 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended identifier */
2358 #define CAN_RI1R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2359
2360 /******************* Bit definition for CAN_RDT1R register ******************/
2361 #define CAN_RDT1R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2362 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00U) /*!<Filter Match Index */
2363 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2364
2365 /******************* Bit definition for CAN_RDL1R register ******************/
2366 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2367 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2368 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2369 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2370
2371 /******************* Bit definition for CAN_RDH1R register ******************/
2372 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2373 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2374 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2375 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2376
2377 /*!<CAN filter registers */
2378 /******************* Bit definition for CAN_FMR register ********************/
2379 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
2380
2381 /******************* Bit definition for CAN_FM1R register *******************/
2382 #define CAN_FM1R_FBM ((uint16_t)0x3FFFU) /*!<Filter Mode */
2383 #define CAN_FM1R_FBM0 ((uint16_t)0x0001U) /*!<Filter Init Mode bit 0 */
2384 #define CAN_FM1R_FBM1 ((uint16_t)0x0002U) /*!<Filter Init Mode bit 1 */
2385 #define CAN_FM1R_FBM2 ((uint16_t)0x0004U) /*!<Filter Init Mode bit 2 */
2386 #define CAN_FM1R_FBM3 ((uint16_t)0x0008U) /*!<Filter Init Mode bit 3 */
2387 #define CAN_FM1R_FBM4 ((uint16_t)0x0010U) /*!<Filter Init Mode bit 4 */
2388 #define CAN_FM1R_FBM5 ((uint16_t)0x0020U) /*!<Filter Init Mode bit 5 */
2389 #define CAN_FM1R_FBM6 ((uint16_t)0x0040U) /*!<Filter Init Mode bit 6 */
2390 #define CAN_FM1R_FBM7 ((uint16_t)0x0080U) /*!<Filter Init Mode bit 7 */
2391 #define CAN_FM1R_FBM8 ((uint16_t)0x0100U) /*!<Filter Init Mode bit 8 */
2392 #define CAN_FM1R_FBM9 ((uint16_t)0x0200U) /*!<Filter Init Mode bit 9 */
2393 #define CAN_FM1R_FBM10 ((uint16_t)0x0400U) /*!<Filter Init Mode bit 10 */
2394 #define CAN_FM1R_FBM11 ((uint16_t)0x0800U) /*!<Filter Init Mode bit 11 */
2395 #define CAN_FM1R_FBM12 ((uint16_t)0x1000U) /*!<Filter Init Mode bit 12 */
2396 #define CAN_FM1R_FBM13 ((uint16_t)0x2000U) /*!<Filter Init Mode bit 13 */
2397
2398 /******************* Bit definition for CAN_FS1R register *******************/
2399 #define CAN_FS1R_FSC ((uint16_t)0x3FFFU) /*!<Filter Scale Configuration */
2400 #define CAN_FS1R_FSC0 ((uint16_t)0x0001U) /*!<Filter Scale Configuration bit 0 */
2401 #define CAN_FS1R_FSC1 ((uint16_t)0x0002U) /*!<Filter Scale Configuration bit 1 */
2402 #define CAN_FS1R_FSC2 ((uint16_t)0x0004U) /*!<Filter Scale Configuration bit 2 */
2403 #define CAN_FS1R_FSC3 ((uint16_t)0x0008U) /*!<Filter Scale Configuration bit 3 */
2404 #define CAN_FS1R_FSC4 ((uint16_t)0x0010U) /*!<Filter Scale Configuration bit 4 */
2405 #define CAN_FS1R_FSC5 ((uint16_t)0x0020U) /*!<Filter Scale Configuration bit 5 */
2406 #define CAN_FS1R_FSC6 ((uint16_t)0x0040U) /*!<Filter Scale Configuration bit 6 */
2407 #define CAN_FS1R_FSC7 ((uint16_t)0x0080U) /*!<Filter Scale Configuration bit 7 */
2408 #define CAN_FS1R_FSC8 ((uint16_t)0x0100U) /*!<Filter Scale Configuration bit 8 */
2409 #define CAN_FS1R_FSC9 ((uint16_t)0x0200U) /*!<Filter Scale Configuration bit 9 */
2410 #define CAN_FS1R_FSC10 ((uint16_t)0x0400U) /*!<Filter Scale Configuration bit 10 */
2411 #define CAN_FS1R_FSC11 ((uint16_t)0x0800U) /*!<Filter Scale Configuration bit 11 */
2412 #define CAN_FS1R_FSC12 ((uint16_t)0x1000U) /*!<Filter Scale Configuration bit 12 */
2413 #define CAN_FS1R_FSC13 ((uint16_t)0x2000U) /*!<Filter Scale Configuration bit 13 */
2414
2415 /****************** Bit definition for CAN_FFA1R register *******************/
2416 #define CAN_FFA1R_FFA ((uint16_t)0x3FFFU) /*!<Filter FIFO Assignment */
2417 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001U) /*!<Filter FIFO Assignment for Filter 0 */
2418 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002U) /*!<Filter FIFO Assignment for Filter 1 */
2419 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004U) /*!<Filter FIFO Assignment for Filter 2 */
2420 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008U) /*!<Filter FIFO Assignment for Filter 3 */
2421 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010U) /*!<Filter FIFO Assignment for Filter 4 */
2422 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020U) /*!<Filter FIFO Assignment for Filter 5 */
2423 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040U) /*!<Filter FIFO Assignment for Filter 6 */
2424 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080U) /*!<Filter FIFO Assignment for Filter 7 */
2425 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100U) /*!<Filter FIFO Assignment for Filter 8 */
2426 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200U) /*!<Filter FIFO Assignment for Filter 9 */
2427 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400U) /*!<Filter FIFO Assignment for Filter 10 */
2428 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800U) /*!<Filter FIFO Assignment for Filter 11 */
2429 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000U) /*!<Filter FIFO Assignment for Filter 12 */
2430 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000U) /*!<Filter FIFO Assignment for Filter 13 */
2431
2432 /******************* Bit definition for CAN_FA1R register *******************/
2433 #define CAN_FA1R_FACT ((uint16_t)0x3FFFU) /*!<Filter Active */
2434 #define CAN_FA1R_FACT0 ((uint16_t)0x0001U) /*!<Filter 0 Active */
2435 #define CAN_FA1R_FACT1 ((uint16_t)0x0002U) /*!<Filter 1 Active */
2436 #define CAN_FA1R_FACT2 ((uint16_t)0x0004U) /*!<Filter 2 Active */
2437 #define CAN_FA1R_FACT3 ((uint16_t)0x0008U) /*!<Filter 3 Active */
2438 #define CAN_FA1R_FACT4 ((uint16_t)0x0010U) /*!<Filter 4 Active */
2439 #define CAN_FA1R_FACT5 ((uint16_t)0x0020U) /*!<Filter 5 Active */
2440 #define CAN_FA1R_FACT6 ((uint16_t)0x0040U) /*!<Filter 6 Active */
2441 #define CAN_FA1R_FACT7 ((uint16_t)0x0080U) /*!<Filter 7 Active */
2442 #define CAN_FA1R_FACT8 ((uint16_t)0x0100U) /*!<Filter 8 Active */
2443 #define CAN_FA1R_FACT9 ((uint16_t)0x0200U) /*!<Filter 9 Active */
2444 #define CAN_FA1R_FACT10 ((uint16_t)0x0400U) /*!<Filter 10 Active */
2445 #define CAN_FA1R_FACT11 ((uint16_t)0x0800U) /*!<Filter 11 Active */
2446 #define CAN_FA1R_FACT12 ((uint16_t)0x1000U) /*!<Filter 12 Active */
2447 #define CAN_FA1R_FACT13 ((uint16_t)0x2000U) /*!<Filter 13 Active */
2448
2449 /******************* Bit definition for CAN_F0R1 register *******************/
2450 #define CAN_F0R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2451 #define CAN_F0R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2452 #define CAN_F0R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2453 #define CAN_F0R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2454 #define CAN_F0R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2455 #define CAN_F0R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2456 #define CAN_F0R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2457 #define CAN_F0R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2458 #define CAN_F0R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2459 #define CAN_F0R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2460 #define CAN_F0R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2461 #define CAN_F0R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2462 #define CAN_F0R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2463 #define CAN_F0R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2464 #define CAN_F0R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2465 #define CAN_F0R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2466 #define CAN_F0R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2467 #define CAN_F0R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2468 #define CAN_F0R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2469 #define CAN_F0R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2470 #define CAN_F0R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2471 #define CAN_F0R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2472 #define CAN_F0R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2473 #define CAN_F0R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2474 #define CAN_F0R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2475 #define CAN_F0R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2476 #define CAN_F0R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2477 #define CAN_F0R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2478 #define CAN_F0R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2479 #define CAN_F0R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2480 #define CAN_F0R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2481 #define CAN_F0R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2482
2483 /******************* Bit definition for CAN_F1R1 register *******************/
2484 #define CAN_F1R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2485 #define CAN_F1R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2486 #define CAN_F1R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2487 #define CAN_F1R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2488 #define CAN_F1R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2489 #define CAN_F1R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2490 #define CAN_F1R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2491 #define CAN_F1R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2492 #define CAN_F1R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2493 #define CAN_F1R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2494 #define CAN_F1R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2495 #define CAN_F1R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2496 #define CAN_F1R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2497 #define CAN_F1R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2498 #define CAN_F1R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2499 #define CAN_F1R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2500 #define CAN_F1R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2501 #define CAN_F1R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2502 #define CAN_F1R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2503 #define CAN_F1R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2504 #define CAN_F1R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2505 #define CAN_F1R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2506 #define CAN_F1R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2507 #define CAN_F1R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2508 #define CAN_F1R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2509 #define CAN_F1R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2510 #define CAN_F1R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2511 #define CAN_F1R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2512 #define CAN_F1R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2513 #define CAN_F1R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2514 #define CAN_F1R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2515 #define CAN_F1R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2516
2517 /******************* Bit definition for CAN_F2R1 register *******************/
2518 #define CAN_F2R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2519 #define CAN_F2R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2520 #define CAN_F2R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2521 #define CAN_F2R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2522 #define CAN_F2R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2523 #define CAN_F2R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2524 #define CAN_F2R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2525 #define CAN_F2R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2526 #define CAN_F2R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2527 #define CAN_F2R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2528 #define CAN_F2R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2529 #define CAN_F2R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2530 #define CAN_F2R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2531 #define CAN_F2R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2532 #define CAN_F2R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2533 #define CAN_F2R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2534 #define CAN_F2R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2535 #define CAN_F2R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2536 #define CAN_F2R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2537 #define CAN_F2R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2538 #define CAN_F2R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2539 #define CAN_F2R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2540 #define CAN_F2R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2541 #define CAN_F2R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2542 #define CAN_F2R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2543 #define CAN_F2R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2544 #define CAN_F2R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2545 #define CAN_F2R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2546 #define CAN_F2R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2547 #define CAN_F2R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2548 #define CAN_F2R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2549 #define CAN_F2R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2550
2551 /******************* Bit definition for CAN_F3R1 register *******************/
2552 #define CAN_F3R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2553 #define CAN_F3R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2554 #define CAN_F3R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2555 #define CAN_F3R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2556 #define CAN_F3R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2557 #define CAN_F3R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2558 #define CAN_F3R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2559 #define CAN_F3R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2560 #define CAN_F3R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2561 #define CAN_F3R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2562 #define CAN_F3R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2563 #define CAN_F3R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2564 #define CAN_F3R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2565 #define CAN_F3R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2566 #define CAN_F3R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2567 #define CAN_F3R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2568 #define CAN_F3R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2569 #define CAN_F3R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2570 #define CAN_F3R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2571 #define CAN_F3R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2572 #define CAN_F3R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2573 #define CAN_F3R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2574 #define CAN_F3R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2575 #define CAN_F3R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2576 #define CAN_F3R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2577 #define CAN_F3R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2578 #define CAN_F3R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2579 #define CAN_F3R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2580 #define CAN_F3R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2581 #define CAN_F3R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2582 #define CAN_F3R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2583 #define CAN_F3R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2584
2585 /******************* Bit definition for CAN_F4R1 register *******************/
2586 #define CAN_F4R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2587 #define CAN_F4R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2588 #define CAN_F4R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2589 #define CAN_F4R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2590 #define CAN_F4R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2591 #define CAN_F4R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2592 #define CAN_F4R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2593 #define CAN_F4R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2594 #define CAN_F4R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2595 #define CAN_F4R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2596 #define CAN_F4R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2597 #define CAN_F4R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2598 #define CAN_F4R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2599 #define CAN_F4R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2600 #define CAN_F4R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2601 #define CAN_F4R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2602 #define CAN_F4R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2603 #define CAN_F4R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2604 #define CAN_F4R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2605 #define CAN_F4R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2606 #define CAN_F4R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2607 #define CAN_F4R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2608 #define CAN_F4R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2609 #define CAN_F4R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2610 #define CAN_F4R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2611 #define CAN_F4R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2612 #define CAN_F4R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2613 #define CAN_F4R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2614 #define CAN_F4R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2615 #define CAN_F4R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2616 #define CAN_F4R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2617 #define CAN_F4R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2618
2619 /******************* Bit definition for CAN_F5R1 register *******************/
2620 #define CAN_F5R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2621 #define CAN_F5R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2622 #define CAN_F5R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2623 #define CAN_F5R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2624 #define CAN_F5R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2625 #define CAN_F5R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2626 #define CAN_F5R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2627 #define CAN_F5R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2628 #define CAN_F5R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2629 #define CAN_F5R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2630 #define CAN_F5R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2631 #define CAN_F5R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2632 #define CAN_F5R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2633 #define CAN_F5R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2634 #define CAN_F5R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2635 #define CAN_F5R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2636 #define CAN_F5R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2637 #define CAN_F5R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2638 #define CAN_F5R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2639 #define CAN_F5R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2640 #define CAN_F5R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2641 #define CAN_F5R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2642 #define CAN_F5R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2643 #define CAN_F5R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2644 #define CAN_F5R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2645 #define CAN_F5R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2646 #define CAN_F5R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2647 #define CAN_F5R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2648 #define CAN_F5R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2649 #define CAN_F5R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2650 #define CAN_F5R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2651 #define CAN_F5R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2652
2653 /******************* Bit definition for CAN_F6R1 register *******************/
2654 #define CAN_F6R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2655 #define CAN_F6R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2656 #define CAN_F6R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2657 #define CAN_F6R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2658 #define CAN_F6R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2659 #define CAN_F6R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2660 #define CAN_F6R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2661 #define CAN_F6R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2662 #define CAN_F6R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2663 #define CAN_F6R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2664 #define CAN_F6R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2665 #define CAN_F6R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2666 #define CAN_F6R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2667 #define CAN_F6R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2668 #define CAN_F6R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2669 #define CAN_F6R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2670 #define CAN_F6R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2671 #define CAN_F6R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2672 #define CAN_F6R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2673 #define CAN_F6R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2674 #define CAN_F6R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2675 #define CAN_F6R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2676 #define CAN_F6R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2677 #define CAN_F6R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2678 #define CAN_F6R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2679 #define CAN_F6R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2680 #define CAN_F6R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2681 #define CAN_F6R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2682 #define CAN_F6R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2683 #define CAN_F6R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2684 #define CAN_F6R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2685 #define CAN_F6R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2686
2687 /******************* Bit definition for CAN_F7R1 register *******************/
2688 #define CAN_F7R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2689 #define CAN_F7R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2690 #define CAN_F7R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2691 #define CAN_F7R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2692 #define CAN_F7R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2693 #define CAN_F7R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2694 #define CAN_F7R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2695 #define CAN_F7R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2696 #define CAN_F7R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2697 #define CAN_F7R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2698 #define CAN_F7R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2699 #define CAN_F7R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2700 #define CAN_F7R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2701 #define CAN_F7R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2702 #define CAN_F7R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2703 #define CAN_F7R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2704 #define CAN_F7R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2705 #define CAN_F7R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2706 #define CAN_F7R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2707 #define CAN_F7R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2708 #define CAN_F7R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2709 #define CAN_F7R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2710 #define CAN_F7R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2711 #define CAN_F7R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2712 #define CAN_F7R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2713 #define CAN_F7R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2714 #define CAN_F7R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2715 #define CAN_F7R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2716 #define CAN_F7R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2717 #define CAN_F7R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2718 #define CAN_F7R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2719 #define CAN_F7R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2720
2721 /******************* Bit definition for CAN_F8R1 register *******************/
2722 #define CAN_F8R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2723 #define CAN_F8R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2724 #define CAN_F8R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2725 #define CAN_F8R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2726 #define CAN_F8R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2727 #define CAN_F8R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2728 #define CAN_F8R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2729 #define CAN_F8R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2730 #define CAN_F8R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2731 #define CAN_F8R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2732 #define CAN_F8R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2733 #define CAN_F8R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2734 #define CAN_F8R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2735 #define CAN_F8R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2736 #define CAN_F8R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2737 #define CAN_F8R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2738 #define CAN_F8R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2739 #define CAN_F8R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2740 #define CAN_F8R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2741 #define CAN_F8R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2742 #define CAN_F8R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2743 #define CAN_F8R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2744 #define CAN_F8R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2745 #define CAN_F8R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2746 #define CAN_F8R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2747 #define CAN_F8R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2748 #define CAN_F8R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2749 #define CAN_F8R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2750 #define CAN_F8R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2751 #define CAN_F8R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2752 #define CAN_F8R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2753 #define CAN_F8R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2754
2755 /******************* Bit definition for CAN_F9R1 register *******************/
2756 #define CAN_F9R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2757 #define CAN_F9R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2758 #define CAN_F9R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2759 #define CAN_F9R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2760 #define CAN_F9R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2761 #define CAN_F9R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2762 #define CAN_F9R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2763 #define CAN_F9R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2764 #define CAN_F9R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2765 #define CAN_F9R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2766 #define CAN_F9R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2767 #define CAN_F9R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2768 #define CAN_F9R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2769 #define CAN_F9R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2770 #define CAN_F9R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2771 #define CAN_F9R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2772 #define CAN_F9R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2773 #define CAN_F9R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2774 #define CAN_F9R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2775 #define CAN_F9R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2776 #define CAN_F9R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2777 #define CAN_F9R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2778 #define CAN_F9R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2779 #define CAN_F9R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2780 #define CAN_F9R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2781 #define CAN_F9R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2782 #define CAN_F9R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2783 #define CAN_F9R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2784 #define CAN_F9R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2785 #define CAN_F9R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2786 #define CAN_F9R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2787 #define CAN_F9R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2788
2789 /******************* Bit definition for CAN_F10R1 register ******************/
2790 #define CAN_F10R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2791 #define CAN_F10R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2792 #define CAN_F10R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2793 #define CAN_F10R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2794 #define CAN_F10R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2795 #define CAN_F10R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2796 #define CAN_F10R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2797 #define CAN_F10R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2798 #define CAN_F10R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2799 #define CAN_F10R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2800 #define CAN_F10R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2801 #define CAN_F10R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2802 #define CAN_F10R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2803 #define CAN_F10R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2804 #define CAN_F10R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2805 #define CAN_F10R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2806 #define CAN_F10R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2807 #define CAN_F10R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2808 #define CAN_F10R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2809 #define CAN_F10R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2810 #define CAN_F10R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2811 #define CAN_F10R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2812 #define CAN_F10R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2813 #define CAN_F10R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2814 #define CAN_F10R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2815 #define CAN_F10R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2816 #define CAN_F10R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2817 #define CAN_F10R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2818 #define CAN_F10R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2819 #define CAN_F10R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2820 #define CAN_F10R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2821 #define CAN_F10R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2822
2823 /******************* Bit definition for CAN_F11R1 register ******************/
2824 #define CAN_F11R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2825 #define CAN_F11R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2826 #define CAN_F11R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2827 #define CAN_F11R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2828 #define CAN_F11R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2829 #define CAN_F11R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2830 #define CAN_F11R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2831 #define CAN_F11R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2832 #define CAN_F11R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2833 #define CAN_F11R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2834 #define CAN_F11R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2835 #define CAN_F11R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2836 #define CAN_F11R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2837 #define CAN_F11R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2838 #define CAN_F11R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2839 #define CAN_F11R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2840 #define CAN_F11R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2841 #define CAN_F11R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2842 #define CAN_F11R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2843 #define CAN_F11R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2844 #define CAN_F11R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2845 #define CAN_F11R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2846 #define CAN_F11R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2847 #define CAN_F11R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2848 #define CAN_F11R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2849 #define CAN_F11R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2850 #define CAN_F11R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2851 #define CAN_F11R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2852 #define CAN_F11R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2853 #define CAN_F11R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2854 #define CAN_F11R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2855 #define CAN_F11R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2856
2857 /******************* Bit definition for CAN_F12R1 register ******************/
2858 #define CAN_F12R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2859 #define CAN_F12R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2860 #define CAN_F12R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2861 #define CAN_F12R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2862 #define CAN_F12R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2863 #define CAN_F12R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2864 #define CAN_F12R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2865 #define CAN_F12R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2866 #define CAN_F12R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2867 #define CAN_F12R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2868 #define CAN_F12R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2869 #define CAN_F12R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2870 #define CAN_F12R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2871 #define CAN_F12R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2872 #define CAN_F12R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2873 #define CAN_F12R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2874 #define CAN_F12R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2875 #define CAN_F12R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2876 #define CAN_F12R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2877 #define CAN_F12R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2878 #define CAN_F12R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2879 #define CAN_F12R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2880 #define CAN_F12R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2881 #define CAN_F12R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2882 #define CAN_F12R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2883 #define CAN_F12R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2884 #define CAN_F12R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2885 #define CAN_F12R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2886 #define CAN_F12R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2887 #define CAN_F12R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2888 #define CAN_F12R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2889 #define CAN_F12R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2890
2891 /******************* Bit definition for CAN_F13R1 register ******************/
2892 #define CAN_F13R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2893 #define CAN_F13R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2894 #define CAN_F13R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2895 #define CAN_F13R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2896 #define CAN_F13R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2897 #define CAN_F13R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2898 #define CAN_F13R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2899 #define CAN_F13R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2900 #define CAN_F13R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2901 #define CAN_F13R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2902 #define CAN_F13R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2903 #define CAN_F13R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2904 #define CAN_F13R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2905 #define CAN_F13R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2906 #define CAN_F13R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2907 #define CAN_F13R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2908 #define CAN_F13R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2909 #define CAN_F13R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2910 #define CAN_F13R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2911 #define CAN_F13R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2912 #define CAN_F13R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2913 #define CAN_F13R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2914 #define CAN_F13R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2915 #define CAN_F13R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2916 #define CAN_F13R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2917 #define CAN_F13R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2918 #define CAN_F13R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2919 #define CAN_F13R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2920 #define CAN_F13R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2921 #define CAN_F13R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2922 #define CAN_F13R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2923 #define CAN_F13R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2924
2925 /******************* Bit definition for CAN_F0R2 register *******************/
2926 #define CAN_F0R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2927 #define CAN_F0R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2928 #define CAN_F0R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2929 #define CAN_F0R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2930 #define CAN_F0R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2931 #define CAN_F0R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2932 #define CAN_F0R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2933 #define CAN_F0R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2934 #define CAN_F0R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2935 #define CAN_F0R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2936 #define CAN_F0R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2937 #define CAN_F0R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2938 #define CAN_F0R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2939 #define CAN_F0R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2940 #define CAN_F0R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2941 #define CAN_F0R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2942 #define CAN_F0R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2943 #define CAN_F0R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2944 #define CAN_F0R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2945 #define CAN_F0R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2946 #define CAN_F0R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2947 #define CAN_F0R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2948 #define CAN_F0R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2949 #define CAN_F0R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2950 #define CAN_F0R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2951 #define CAN_F0R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2952 #define CAN_F0R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2953 #define CAN_F0R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2954 #define CAN_F0R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2955 #define CAN_F0R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2956 #define CAN_F0R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2957 #define CAN_F0R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2958
2959 /******************* Bit definition for CAN_F1R2 register *******************/
2960 #define CAN_F1R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2961 #define CAN_F1R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2962 #define CAN_F1R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2963 #define CAN_F1R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2964 #define CAN_F1R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2965 #define CAN_F1R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2966 #define CAN_F1R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2967 #define CAN_F1R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2968 #define CAN_F1R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2969 #define CAN_F1R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2970 #define CAN_F1R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2971 #define CAN_F1R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2972 #define CAN_F1R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2973 #define CAN_F1R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2974 #define CAN_F1R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2975 #define CAN_F1R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2976 #define CAN_F1R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2977 #define CAN_F1R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2978 #define CAN_F1R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2979 #define CAN_F1R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2980 #define CAN_F1R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2981 #define CAN_F1R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2982 #define CAN_F1R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2983 #define CAN_F1R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2984 #define CAN_F1R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2985 #define CAN_F1R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2986 #define CAN_F1R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2987 #define CAN_F1R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2988 #define CAN_F1R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2989 #define CAN_F1R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2990 #define CAN_F1R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2991 #define CAN_F1R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2992
2993 /******************* Bit definition for CAN_F2R2 register *******************/
2994 #define CAN_F2R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2995 #define CAN_F2R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2996 #define CAN_F2R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2997 #define CAN_F2R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2998 #define CAN_F2R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2999 #define CAN_F2R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3000 #define CAN_F2R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3001 #define CAN_F2R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3002 #define CAN_F2R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3003 #define CAN_F2R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3004 #define CAN_F2R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3005 #define CAN_F2R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3006 #define CAN_F2R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3007 #define CAN_F2R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3008 #define CAN_F2R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3009 #define CAN_F2R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3010 #define CAN_F2R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3011 #define CAN_F2R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3012 #define CAN_F2R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3013 #define CAN_F2R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3014 #define CAN_F2R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3015 #define CAN_F2R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3016 #define CAN_F2R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3017 #define CAN_F2R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3018 #define CAN_F2R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3019 #define CAN_F2R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3020 #define CAN_F2R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3021 #define CAN_F2R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3022 #define CAN_F2R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3023 #define CAN_F2R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3024 #define CAN_F2R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3025 #define CAN_F2R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3026
3027 /******************* Bit definition for CAN_F3R2 register *******************/
3028 #define CAN_F3R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3029 #define CAN_F3R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3030 #define CAN_F3R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3031 #define CAN_F3R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3032 #define CAN_F3R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3033 #define CAN_F3R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3034 #define CAN_F3R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3035 #define CAN_F3R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3036 #define CAN_F3R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3037 #define CAN_F3R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3038 #define CAN_F3R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3039 #define CAN_F3R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3040 #define CAN_F3R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3041 #define CAN_F3R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3042 #define CAN_F3R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3043 #define CAN_F3R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3044 #define CAN_F3R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3045 #define CAN_F3R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3046 #define CAN_F3R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3047 #define CAN_F3R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3048 #define CAN_F3R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3049 #define CAN_F3R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3050 #define CAN_F3R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3051 #define CAN_F3R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3052 #define CAN_F3R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3053 #define CAN_F3R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3054 #define CAN_F3R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3055 #define CAN_F3R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3056 #define CAN_F3R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3057 #define CAN_F3R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3058 #define CAN_F3R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3059 #define CAN_F3R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3060
3061 /******************* Bit definition for CAN_F4R2 register *******************/
3062 #define CAN_F4R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3063 #define CAN_F4R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3064 #define CAN_F4R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3065 #define CAN_F4R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3066 #define CAN_F4R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3067 #define CAN_F4R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3068 #define CAN_F4R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3069 #define CAN_F4R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3070 #define CAN_F4R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3071 #define CAN_F4R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3072 #define CAN_F4R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3073 #define CAN_F4R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3074 #define CAN_F4R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3075 #define CAN_F4R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3076 #define CAN_F4R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3077 #define CAN_F4R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3078 #define CAN_F4R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3079 #define CAN_F4R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3080 #define CAN_F4R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3081 #define CAN_F4R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3082 #define CAN_F4R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3083 #define CAN_F4R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3084 #define CAN_F4R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3085 #define CAN_F4R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3086 #define CAN_F4R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3087 #define CAN_F4R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3088 #define CAN_F4R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3089 #define CAN_F4R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3090 #define CAN_F4R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3091 #define CAN_F4R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3092 #define CAN_F4R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3093 #define CAN_F4R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3094
3095 /******************* Bit definition for CAN_F5R2 register *******************/
3096 #define CAN_F5R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3097 #define CAN_F5R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3098 #define CAN_F5R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3099 #define CAN_F5R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3100 #define CAN_F5R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3101 #define CAN_F5R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3102 #define CAN_F5R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3103 #define CAN_F5R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3104 #define CAN_F5R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3105 #define CAN_F5R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3106 #define CAN_F5R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3107 #define CAN_F5R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3108 #define CAN_F5R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3109 #define CAN_F5R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3110 #define CAN_F5R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3111 #define CAN_F5R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3112 #define CAN_F5R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3113 #define CAN_F5R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3114 #define CAN_F5R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3115 #define CAN_F5R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3116 #define CAN_F5R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3117 #define CAN_F5R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3118 #define CAN_F5R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3119 #define CAN_F5R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3120 #define CAN_F5R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3121 #define CAN_F5R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3122 #define CAN_F5R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3123 #define CAN_F5R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3124 #define CAN_F5R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3125 #define CAN_F5R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3126 #define CAN_F5R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3127 #define CAN_F5R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3128
3129 /******************* Bit definition for CAN_F6R2 register *******************/
3130 #define CAN_F6R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3131 #define CAN_F6R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3132 #define CAN_F6R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3133 #define CAN_F6R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3134 #define CAN_F6R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3135 #define CAN_F6R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3136 #define CAN_F6R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3137 #define CAN_F6R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3138 #define CAN_F6R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3139 #define CAN_F6R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3140 #define CAN_F6R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3141 #define CAN_F6R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3142 #define CAN_F6R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3143 #define CAN_F6R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3144 #define CAN_F6R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3145 #define CAN_F6R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3146 #define CAN_F6R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3147 #define CAN_F6R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3148 #define CAN_F6R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3149 #define CAN_F6R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3150 #define CAN_F6R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3151 #define CAN_F6R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3152 #define CAN_F6R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3153 #define CAN_F6R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3154 #define CAN_F6R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3155 #define CAN_F6R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3156 #define CAN_F6R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3157 #define CAN_F6R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3158 #define CAN_F6R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3159 #define CAN_F6R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3160 #define CAN_F6R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3161 #define CAN_F6R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3162
3163 /******************* Bit definition for CAN_F7R2 register *******************/
3164 #define CAN_F7R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3165 #define CAN_F7R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3166 #define CAN_F7R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3167 #define CAN_F7R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3168 #define CAN_F7R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3169 #define CAN_F7R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3170 #define CAN_F7R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3171 #define CAN_F7R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3172 #define CAN_F7R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3173 #define CAN_F7R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3174 #define CAN_F7R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3175 #define CAN_F7R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3176 #define CAN_F7R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3177 #define CAN_F7R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3178 #define CAN_F7R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3179 #define CAN_F7R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3180 #define CAN_F7R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3181 #define CAN_F7R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3182 #define CAN_F7R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3183 #define CAN_F7R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3184 #define CAN_F7R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3185 #define CAN_F7R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3186 #define CAN_F7R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3187 #define CAN_F7R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3188 #define CAN_F7R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3189 #define CAN_F7R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3190 #define CAN_F7R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3191 #define CAN_F7R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3192 #define CAN_F7R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3193 #define CAN_F7R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3194 #define CAN_F7R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3195 #define CAN_F7R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3196
3197 /******************* Bit definition for CAN_F8R2 register *******************/
3198 #define CAN_F8R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3199 #define CAN_F8R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3200 #define CAN_F8R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3201 #define CAN_F8R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3202 #define CAN_F8R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3203 #define CAN_F8R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3204 #define CAN_F8R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3205 #define CAN_F8R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3206 #define CAN_F8R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3207 #define CAN_F8R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3208 #define CAN_F8R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3209 #define CAN_F8R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3210 #define CAN_F8R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3211 #define CAN_F8R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3212 #define CAN_F8R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3213 #define CAN_F8R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3214 #define CAN_F8R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3215 #define CAN_F8R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3216 #define CAN_F8R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3217 #define CAN_F8R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3218 #define CAN_F8R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3219 #define CAN_F8R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3220 #define CAN_F8R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3221 #define CAN_F8R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3222 #define CAN_F8R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3223 #define CAN_F8R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3224 #define CAN_F8R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3225 #define CAN_F8R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3226 #define CAN_F8R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3227 #define CAN_F8R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3228 #define CAN_F8R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3229 #define CAN_F8R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3230
3231 /******************* Bit definition for CAN_F9R2 register *******************/
3232 #define CAN_F9R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3233 #define CAN_F9R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3234 #define CAN_F9R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3235 #define CAN_F9R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3236 #define CAN_F9R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3237 #define CAN_F9R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3238 #define CAN_F9R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3239 #define CAN_F9R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3240 #define CAN_F9R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3241 #define CAN_F9R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3242 #define CAN_F9R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3243 #define CAN_F9R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3244 #define CAN_F9R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3245 #define CAN_F9R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3246 #define CAN_F9R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3247 #define CAN_F9R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3248 #define CAN_F9R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3249 #define CAN_F9R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3250 #define CAN_F9R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3251 #define CAN_F9R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3252 #define CAN_F9R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3253 #define CAN_F9R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3254 #define CAN_F9R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3255 #define CAN_F9R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3256 #define CAN_F9R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3257 #define CAN_F9R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3258 #define CAN_F9R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3259 #define CAN_F9R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3260 #define CAN_F9R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3261 #define CAN_F9R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3262 #define CAN_F9R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3263 #define CAN_F9R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3264
3265 /******************* Bit definition for CAN_F10R2 register ******************/
3266 #define CAN_F10R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3267 #define CAN_F10R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3268 #define CAN_F10R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3269 #define CAN_F10R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3270 #define CAN_F10R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3271 #define CAN_F10R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3272 #define CAN_F10R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3273 #define CAN_F10R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3274 #define CAN_F10R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3275 #define CAN_F10R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3276 #define CAN_F10R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3277 #define CAN_F10R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3278 #define CAN_F10R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3279 #define CAN_F10R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3280 #define CAN_F10R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3281 #define CAN_F10R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3282 #define CAN_F10R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3283 #define CAN_F10R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3284 #define CAN_F10R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3285 #define CAN_F10R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3286 #define CAN_F10R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3287 #define CAN_F10R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3288 #define CAN_F10R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3289 #define CAN_F10R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3290 #define CAN_F10R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3291 #define CAN_F10R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3292 #define CAN_F10R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3293 #define CAN_F10R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3294 #define CAN_F10R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3295 #define CAN_F10R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3296 #define CAN_F10R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3297 #define CAN_F10R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3298
3299 /******************* Bit definition for CAN_F11R2 register ******************/
3300 #define CAN_F11R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3301 #define CAN_F11R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3302 #define CAN_F11R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3303 #define CAN_F11R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3304 #define CAN_F11R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3305 #define CAN_F11R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3306 #define CAN_F11R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3307 #define CAN_F11R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3308 #define CAN_F11R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3309 #define CAN_F11R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3310 #define CAN_F11R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3311 #define CAN_F11R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3312 #define CAN_F11R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3313 #define CAN_F11R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3314 #define CAN_F11R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3315 #define CAN_F11R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3316 #define CAN_F11R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3317 #define CAN_F11R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3318 #define CAN_F11R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3319 #define CAN_F11R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3320 #define CAN_F11R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3321 #define CAN_F11R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3322 #define CAN_F11R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3323 #define CAN_F11R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3324 #define CAN_F11R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3325 #define CAN_F11R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3326 #define CAN_F11R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3327 #define CAN_F11R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3328 #define CAN_F11R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3329 #define CAN_F11R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3330 #define CAN_F11R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3331 #define CAN_F11R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3332
3333 /******************* Bit definition for CAN_F12R2 register ******************/
3334 #define CAN_F12R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3335 #define CAN_F12R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3336 #define CAN_F12R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3337 #define CAN_F12R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3338 #define CAN_F12R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3339 #define CAN_F12R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3340 #define CAN_F12R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3341 #define CAN_F12R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3342 #define CAN_F12R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3343 #define CAN_F12R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3344 #define CAN_F12R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3345 #define CAN_F12R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3346 #define CAN_F12R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3347 #define CAN_F12R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3348 #define CAN_F12R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3349 #define CAN_F12R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3350 #define CAN_F12R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3351 #define CAN_F12R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3352 #define CAN_F12R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3353 #define CAN_F12R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3354 #define CAN_F12R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3355 #define CAN_F12R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3356 #define CAN_F12R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3357 #define CAN_F12R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3358 #define CAN_F12R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3359 #define CAN_F12R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3360 #define CAN_F12R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3361 #define CAN_F12R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3362 #define CAN_F12R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3363 #define CAN_F12R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3364 #define CAN_F12R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3365 #define CAN_F12R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3366
3367 /******************* Bit definition for CAN_F13R2 register ******************/
3368 #define CAN_F13R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3369 #define CAN_F13R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3370 #define CAN_F13R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3371 #define CAN_F13R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3372 #define CAN_F13R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3373 #define CAN_F13R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3374 #define CAN_F13R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3375 #define CAN_F13R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3376 #define CAN_F13R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3377 #define CAN_F13R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3378 #define CAN_F13R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3379 #define CAN_F13R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3380 #define CAN_F13R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3381 #define CAN_F13R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3382 #define CAN_F13R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3383 #define CAN_F13R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3384 #define CAN_F13R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3385 #define CAN_F13R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3386 #define CAN_F13R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3387 #define CAN_F13R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3388 #define CAN_F13R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3389 #define CAN_F13R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3390 #define CAN_F13R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3391 #define CAN_F13R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3392 #define CAN_F13R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3393 #define CAN_F13R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3394 #define CAN_F13R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3395 #define CAN_F13R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3396 #define CAN_F13R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3397 #define CAN_F13R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3398 #define CAN_F13R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3399 #define CAN_F13R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3400
3401 /******************************************************************************/
3402 /* */
3403 /* CRC calculation unit */
3404 /* */
3405 /******************************************************************************/
3406 /******************* Bit definition for CRC_DR register *********************/
3407 #define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
3408
3409 /******************* Bit definition for CRC_IDR register ********************/
3410 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
3411
3412 /******************** Bit definition for CRC_CR register ********************/
3413 #define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
3414 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */
3415 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
3416 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
3417 #define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
3418 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
3419 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
3420 #define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
3421
3422 /******************* Bit definition for CRC_INIT register *******************/
3423 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
3424
3425 /******************* Bit definition for CRC_POL register ********************/
3426 #define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
3427
3428 /******************************************************************************/
3429 /* */
3430 /* Digital to Analog Converter */
3431 /* */
3432 /******************************************************************************/
3433 /******************** Bit definition for DAC_CR register ********************/
3434 #define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!<DAC channel1 enable */
3435 #define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!<DAC channel1 Trigger enable */
3436
3437 #define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
3438 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
3439 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
3440 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
3441
3442 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3443 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
3444 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
3445
3446 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3447 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
3448 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
3449 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
3450 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
3451
3452 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!<DAC channel1 DMA enable */
3453 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!<DAC channel 1 DMA underrun interrupt enable >*/
3454 #define DAC_CR_CEN1 ((uint32_t)0x00004000U) /*!<DAC channel 1 calibration enable >*/
3455
3456 #define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!<DAC channel2 enable */
3457 #define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!<DAC channel2 Trigger enable */
3458
3459 #define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
3460 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!<Bit 0 */
3461 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!<Bit 1 */
3462 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!<Bit 2 */
3463
3464 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3465 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
3466 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
3467
3468 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3469 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
3470 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
3471 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
3472 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
3473
3474 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!<DAC channel2 DMA enabled */
3475 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun interrupt enable >*/
3476 #define DAC_CR_CEN2 ((uint32_t)0x40000000U) /*!<DAC channel2 calibration enable >*/
3477
3478 /***************** Bit definition for DAC_SWTRIGR register ******************/
3479 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!<DAC channel1 software trigger */
3480 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!<DAC channel2 software trigger */
3481
3482 /***************** Bit definition for DAC_DHR12R1 register ******************/
3483 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
3484
3485 /***************** Bit definition for DAC_DHR12L1 register ******************/
3486 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
3487
3488 /****************** Bit definition for DAC_DHR8R1 register ******************/
3489 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
3490
3491 /***************** Bit definition for DAC_DHR12R2 register ******************/
3492 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!<DAC channel2 12-bit Right aligned data */
3493
3494 /***************** Bit definition for DAC_DHR12L2 register ******************/
3495 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel2 12-bit Left aligned data */
3496
3497 /****************** Bit definition for DAC_DHR8R2 register ******************/
3498 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!<DAC channel2 8-bit Right aligned data */
3499
3500 /***************** Bit definition for DAC_DHR12RD register ******************/
3501 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
3502 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!<DAC channel2 12-bit Right aligned data */
3503
3504 /***************** Bit definition for DAC_DHR12LD register ******************/
3505 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
3506 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!<DAC channel2 12-bit Left aligned data */
3507
3508 /****************** Bit definition for DAC_DHR8RD register ******************/
3509 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
3510 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!<DAC channel2 8-bit Right aligned data */
3511
3512 /******************* Bit definition for DAC_DOR1 register *******************/
3513 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFFU) /*!<DAC channel1 data output */
3514
3515 /******************* Bit definition for DAC_DOR2 register *******************/
3516 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFFU) /*!<DAC channel2 data output */
3517
3518 /******************** Bit definition for DAC_SR register ********************/
3519 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!<DAC channel1 DMA underrun flag */
3520 #define DAC_SR_CAL_FLAG1 ((uint32_t)0x00004000U) /*!<DAC channel1 calibration offset status */
3521 #define DAC_SR_BWST1 ((uint32_t)0x20008000U) /*!<DAC channel1 busy writing sample time flag */
3522
3523 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun flag */
3524 #define DAC_SR_CAL_FLAG2 ((uint32_t)0x40000000U) /*!<DAC channel2 calibration offset status */
3525 #define DAC_SR_BWST2 ((uint32_t)0x80000000U) /*!<DAC channel2 busy writing sample time flag */
3526
3527 /******************* Bit definition for DAC_CCR register ********************/
3528 #define DAC_CCR_OTRIM1 ((uint32_t)0x0000001FU) /*!<DAC channel1 offset trimming value */
3529 #define DAC_CCR_OTRIM2 ((uint32_t)0x001F0000U) /*!<DAC channel2 offset trimming value */
3530
3531 /******************* Bit definition for DAC_MCR register *******************/
3532 #define DAC_MCR_MODE1 ((uint32_t)0x00000007U) /*!<MODE1[2:0] (DAC channel1 mode) */
3533 #define DAC_MCR_MODE1_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
3534 #define DAC_MCR_MODE1_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
3535 #define DAC_MCR_MODE1_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
3536
3537 #define DAC_MCR_MODE2 ((uint32_t)0x00070000U) /*!<MODE2[2:0] (DAC channel2 mode) */
3538 #define DAC_MCR_MODE2_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
3539 #define DAC_MCR_MODE2_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
3540 #define DAC_MCR_MODE2_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
3541
3542 /****************** Bit definition for DAC_SHSR1 register ******************/
3543 #define DAC_SHSR1_TSAMPLE1 ((uint32_t)0x000003FFU) /*!<DAC channel1 sample time */
3544
3545 /****************** Bit definition for DAC_SHSR2 register ******************/
3546 #define DAC_SHSR2_TSAMPLE2 ((uint32_t)0x000003FFU) /*!<DAC channel2 sample time */
3547
3548 /****************** Bit definition for DAC_SHHR register ******************/
3549 #define DAC_SHHR_THOLD1 ((uint32_t)0x000003FFU) /*!<DAC channel1 hold time */
3550 #define DAC_SHHR_THOLD2 ((uint32_t)0x03FF0000U) /*!<DAC channel2 hold time */
3551
3552 /****************** Bit definition for DAC_SHRR register ******************/
3553 #define DAC_SHRR_TREFRESH1 ((uint32_t)0x000000FFU) /*!<DAC channel1 refresh time */
3554 #define DAC_SHRR_TREFRESH2 ((uint32_t)0x00FF0000U) /*!<DAC channel2 refresh time */
3555
3556
3557 /******************************************************************************/
3558 /* */
3559 /* Digital Filter for Sigma Delta Modulators */
3560 /* */
3561 /******************************************************************************/
3562
3563 /**************** DFSDM channel configuration registers ********************/
3564
3565 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
3566 #define DFSDM_CHCFGR1_DFSDMEN ((uint32_t)0x80000000U) /*!< Global enable for DFSDM interface */
3567 #define DFSDM_CHCFGR1_CKOUTSRC ((uint32_t)0x40000000U) /*!< Output serial clock source selection */
3568 #define DFSDM_CHCFGR1_CKOUTDIV ((uint32_t)0x00FF0000U) /*!< CKOUTDIV[7:0] output serial clock divider */
3569 #define DFSDM_CHCFGR1_DATPACK ((uint32_t)0x0000C000U) /*!< DATPACK[1:0] Data packing mode */
3570 #define DFSDM_CHCFGR1_DATPACK_1 ((uint32_t)0x00008000U) /*!< Data packing mode, Bit 1 */
3571 #define DFSDM_CHCFGR1_DATPACK_0 ((uint32_t)0x00004000U) /*!< Data packing mode, Bit 0 */
3572 #define DFSDM_CHCFGR1_DATMPX ((uint32_t)0x00003000U) /*!< DATMPX[1:0] Input data multiplexer for channel y */
3573 #define DFSDM_CHCFGR1_DATMPX_1 ((uint32_t)0x00002000U) /*!< Input data multiplexer for channel y, Bit 1 */
3574 #define DFSDM_CHCFGR1_DATMPX_0 ((uint32_t)0x00001000U) /*!< Input data multiplexer for channel y, Bit 0 */
3575 #define DFSDM_CHCFGR1_CHINSEL ((uint32_t)0x00000100U) /*!< Serial inputs selection for channel y */
3576 #define DFSDM_CHCFGR1_CHEN ((uint32_t)0x00000080U) /*!< Channel y enable */
3577 #define DFSDM_CHCFGR1_CKABEN ((uint32_t)0x00000040U) /*!< Clock absence detector enable on channel y */
3578 #define DFSDM_CHCFGR1_SCDEN ((uint32_t)0x00000020U) /*!< Short circuit detector enable on channel y */
3579 #define DFSDM_CHCFGR1_SPICKSEL ((uint32_t)0x0000000CU) /*!< SPICKSEL[1:0] SPI clock select for channel y */
3580 #define DFSDM_CHCFGR1_SPICKSEL_1 ((uint32_t)0x00000008U) /*!< SPI clock select for channel y, Bit 1 */
3581 #define DFSDM_CHCFGR1_SPICKSEL_0 ((uint32_t)0x00000004U) /*!< SPI clock select for channel y, Bit 0 */
3582 #define DFSDM_CHCFGR1_SITP ((uint32_t)0x00000003U) /*!< SITP[1:0] Serial interface type for channel y */
3583 #define DFSDM_CHCFGR1_SITP_1 ((uint32_t)0x00000002U) /*!< Serial interface type for channel y, Bit 1 */
3584 #define DFSDM_CHCFGR1_SITP_0 ((uint32_t)0x00000001U) /*!< Serial interface type for channel y, Bit 0 */
3585
3586 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
3587 #define DFSDM_CHCFGR2_OFFSET ((uint32_t)0xFFFFFF00U) /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
3588 #define DFSDM_CHCFGR2_DTRBS ((uint32_t)0x000000F8U) /*!< DTRBS[4:0] Data right bit-shift for channel y */
3589
3590 /****************** Bit definition for DFSDM_AWSCDR register *****************/
3591 #define DFSDM_AWSCDR_AWFORD ((uint32_t)0x00C00000U) /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
3592 #define DFSDM_AWSCDR_AWFORD_1 ((uint32_t)0x00800000U) /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
3593 #define DFSDM_AWSCDR_AWFORD_0 ((uint32_t)0x00400000U) /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
3594 #define DFSDM_AWSCDR_AWFOSR ((uint32_t)0x001F0000U) /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
3595 #define DFSDM_AWSCDR_BKSCD ((uint32_t)0x0000F000U) /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
3596 #define DFSDM_AWSCDR_SCDT ((uint32_t)0x000000FFU) /*!< SCDT[7:0] Short circuit detector threshold for channel y */
3597
3598 /**************** Bit definition for DFSDM_CHWDATR register *******************/
3599 #define DFSDM_AWSCDR_WDATA ((uint32_t)0x0000FFFFU) /*!< WDATA[15:0] Input channel y watchdog data */
3600
3601 /**************** Bit definition for DFSDM_CHDATINR register *****************/
3602 #define DFSDM_AWSCDR_INDAT0 ((uint32_t)0x0000FFFFU) /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
3603 #define DFSDM_AWSCDR_INDAT1 ((uint32_t)0xFFFF0000U) /*!< INDAT0[15:0] Input data for channel y */
3604
3605 /************************ DFSDM module registers ****************************/
3606
3607 /******************** Bit definition for DFSDM_CR1 register *******************/
3608 #define DFSDM_CR1_AWFSEL ((uint32_t)0x40000000U) /*!< Analog watchdog fast mode select */
3609 #define DFSDM_CR1_FAST ((uint32_t)0x20000000U) /*!< Fast conversion mode selection */
3610 #define DFSDM_CR1_RCH ((uint32_t)0x07000000U) /*!< RCH[2:0] Regular channel selection */
3611 #define DFSDM_CR1_RDMAEN ((uint32_t)0x00200000U) /*!< DMA channel enabled to read data for the regular conversion */
3612 #define DFSDM_CR1_RSYNC ((uint32_t)0x00080000U) /*!< Launch regular conversion synchronously with DFSDMx */
3613 #define DFSDM_CR1_RCONT ((uint32_t)0x00040000U) /*!< Continuous mode selection for regular conversions */
3614 #define DFSDM_CR1_RSWSTART ((uint32_t)0x00020000U) /*!< Software start of a conversion on the regular channel */
3615 #define DFSDM_CR1_JEXTEN ((uint32_t)0x00006000U) /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
3616 #define DFSDM_CR1_JEXTEN_1 ((uint32_t)0x00004000U) /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
3617 #define DFSDM_CR1_JEXTEN_0 ((uint32_t)0x00002000U) /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
3618 #define DFSDM_CR1_JEXTSEL ((uint32_t)0x00000700U) /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
3619 #define DFSDM_CR1_JEXTSEL_2 ((uint32_t)0x00000400U) /*!< Trigger signal selection for launching injected conversions, Bit 2 */
3620 #define DFSDM_CR1_JEXTSEL_1 ((uint32_t)0x00000200U) /*!< Trigger signal selection for launching injected conversions, Bit 1 */
3621 #define DFSDM_CR1_JEXTSEL_0 ((uint32_t)0x00000100U) /*!< Trigger signal selection for launching injected conversions, Bit 0 */
3622 #define DFSDM_CR1_JDMAEN ((uint32_t)0x00000020U) /*!< DMA channel enabled to read data for the injected channel group */
3623 #define DFSDM_CR1_JSCAN ((uint32_t)0x00000010U) /*!< Scanning conversion in continuous mode selection for injected conversions */
3624 #define DFSDM_CR1_JSYNC ((uint32_t)0x00000008U) /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
3625 #define DFSDM_CR1_JSWSTART ((uint32_t)0x00000002U) /*!< Start the conversion of the injected group of channels */
3626 #define DFSDM_CR1_DFEN ((uint32_t)0x00000001U) /*!< DFSDM enable */
3627
3628 /******************** Bit definition for DFSDM_CR2 register *******************/
3629 #define DFSDM_CR2_AWDCH ((uint32_t)0x00FF0000U) /*!< AWDCH[7:0] Analog watchdog channel selection */
3630 #define DFSDM_CR2_EXCH ((uint32_t)0x0000FF00U) /*!< EXCH[7:0] Extreme detector channel selection */
3631 #define DFSDM_CR2_CKABIE ((uint32_t)0x00000040U) /*!< Clock absence interrupt enable */
3632 #define DFSDM_CR2_SCDIE ((uint32_t)0x00000020U) /*!< Short circuit detector interrupt enable */
3633 #define DFSDM_CR2_AWDIE ((uint32_t)0x00000010U) /*!< Analog watchdog interrupt enable */
3634 #define DFSDM_CR2_ROVRIE ((uint32_t)0x00000008U) /*!< Regular data overrun interrupt enable */
3635 #define DFSDM_CR2_JOVRIE ((uint32_t)0x00000004U) /*!< Injected data overrun interrupt enable */
3636 #define DFSDM_CR2_REOCIE ((uint32_t)0x00000002U) /*!< Regular end of conversion interrupt enable */
3637 #define DFSDM_CR2_JEOCIE ((uint32_t)0x00000001U) /*!< Injected end of conversion interrupt enable */
3638
3639 /******************** Bit definition for DFSDM_ISR register *******************/
3640 #define DFSDM_ISR_SCDF ((uint32_t)0xFF000000U) /*!< SCDF[7:0] Short circuit detector flag */
3641 #define DFSDM_ISR_CKABF ((uint32_t)0x00FF0000U) /*!< CKABF[7:0] Clock absence flag */
3642 #define DFSDM_ISR_RCIP ((uint32_t)0x00004000U) /*!< Regular conversion in progress status */
3643 #define DFSDM_ISR_JCIP ((uint32_t)0x00002000U) /*!< Injected conversion in progress status */
3644 #define DFSDM_ISR_AWDF ((uint32_t)0x00000010U) /*!< Analog watchdog */
3645 #define DFSDM_ISR_ROVRF ((uint32_t)0x00000008U) /*!< Regular conversion overrun flag */
3646 #define DFSDM_ISR_JOVRF ((uint32_t)0x00000004U) /*!< Injected conversion overrun flag */
3647 #define DFSDM_ISR_REOCF ((uint32_t)0x00000002U) /*!< End of regular conversion flag */
3648 #define DFSDM_ISR_JEOCF ((uint32_t)0x00000001U) /*!< End of injected conversion flag */
3649
3650 /******************** Bit definition for DFSDM_ICR register *******************/
3651 #define DFSDM_ICR_CLRSCSDF ((uint32_t)0xFF000000U) /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
3652 #define DFSDM_ICR_CLRCKABF ((uint32_t)0x00FF0000U) /*!< CLRCKABF[7:0] Clear the clock absence flag */
3653 #define DFSDM_ICR_CLRROVRF ((uint32_t)0x00000008U) /*!< Clear the regular conversion overrun flag */
3654 #define DFSDM_ICR_CLRJOVRF ((uint32_t)0x00000004U) /*!< Clear the injected conversion overrun flag */
3655
3656 /******************* Bit definition for DFSDM_JCHGR register ******************/
3657 #define DFSDM_JCHGR_JCHG ((uint32_t)0x000000FFU) /*!< JCHG[7:0] Injected channel group selection */
3658
3659 /******************** Bit definition for DFSDM_FCR register *******************/
3660 #define DFSDM_FCR_FORD ((uint32_t)0xE0000000U) /*!< FORD[2:0] Sinc filter order */
3661 #define DFSDM_FCR_FORD_2 ((uint32_t)0x80000000U) /*!< Sinc filter order, Bit 2 */
3662 #define DFSDM_FCR_FORD_1 ((uint32_t)0x40000000U) /*!< Sinc filter order, Bit 1 */
3663 #define DFSDM_FCR_FORD_0 ((uint32_t)0x20000000U) /*!< Sinc filter order, Bit 0 */
3664 #define DFSDM_FCR_FOSR ((uint32_t)0x03FF0000U) /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
3665 #define DFSDM_FCR_IOSR ((uint32_t)0x000000FFU) /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
3666
3667 /****************** Bit definition for DFSDM_JDATAR register *****************/
3668 #define DFSDM_JDATAR_JDATA ((uint32_t)0xFFFFFF00U) /*!< JDATA[23:0] Injected group conversion data */
3669 #define DFSDM_JDATAR_JDATACH ((uint32_t)0x00000007U) /*!< JDATACH[2:0] Injected channel most recently converted */
3670
3671 /****************** Bit definition for DFSDM_RDATAR register *****************/
3672 #define DFSDM_RDATAR_RDATA ((uint32_t)0xFFFFFF00U) /*!< RDATA[23:0] Regular channel conversion data */
3673 #define DFSDM_RDATAR_RPEND ((uint32_t)0x00000010U) /*!< RPEND Regular channel pending data */
3674 #define DFSDM_RDATAR_RDATACH ((uint32_t)0x00000007U) /*!< RDATACH[2:0] Regular channel most recently converted */
3675
3676 /****************** Bit definition for DFSDM_AWHTR register ******************/
3677 #define DFSDM_AWHTR_AWHT ((uint32_t)0xFFFFFF00U) /*!< AWHT[23:0] Analog watchdog high threshold */
3678 #define DFSDM_AWHTR_BKAWH ((uint32_t)0x0000000FU) /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
3679
3680 /****************** Bit definition for DFSDM_AWLTR register ******************/
3681 #define DFSDM_AWLTR_AWLT ((uint32_t)0xFFFFFF00U) /*!< AWHT[23:0] Analog watchdog low threshold */
3682 #define DFSDM_AWLTR_BKAWL ((uint32_t)0x0000000FU) /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
3683
3684 /****************** Bit definition for DFSDM_AWSR register ******************/
3685 #define DFSDM_AWSR_AWHTF ((uint32_t)0x0000FF00U) /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
3686 #define DFSDM_AWSR_AWLTF ((uint32_t)0x000000FFU) /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
3687
3688 /****************** Bit definition for DFSDM_AWCFR) register *****************/
3689 #define DFSDM_AWCFR_CLRAWHTF ((uint32_t)0x0000FF00U) /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
3690 #define DFSDM_AWCFR_CLRAWLTF ((uint32_t)0x000000FFU) /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
3691
3692 /****************** Bit definition for DFSDM_EXMAX register ******************/
3693 #define DFSDM_EXMAX_EXMAX ((uint32_t)0xFFFFFF00U) /*!< EXMAX[23:0] Extreme detector maximum value */
3694 #define DFSDM_EXMAX_EXMAXCH ((uint32_t)0x00000007U) /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
3695
3696 /****************** Bit definition for DFSDM_EXMIN register ******************/
3697 #define DFSDM_EXMIN_EXMIN ((uint32_t)0xFFFFFF00U) /*!< EXMIN[23:0] Extreme detector minimum value */
3698 #define DFSDM_EXMIN_EXMINCH ((uint32_t)0x00000007U) /*!< EXMINCH[2:0] Extreme detector minimum data channel */
3699
3700 /****************** Bit definition for DFSDM_EXMIN register ******************/
3701 #define DFSDM_CNVTIMR_CNVCNT ((uint32_t)0xFFFFFFF0U) /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
3702
3703 /******************************************************************************/
3704 /* */
3705 /* DMA Controller (DMA) */
3706 /* */
3707 /******************************************************************************/
3708
3709 /******************* Bit definition for DMA_ISR register ********************/
3710 #define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
3711 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
3712 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
3713 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
3714 #define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
3715 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
3716 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
3717 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
3718 #define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
3719 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
3720 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
3721 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
3722 #define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
3723 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
3724 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
3725 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
3726 #define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
3727 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
3728 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
3729 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
3730 #define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
3731 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
3732 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
3733 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
3734 #define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
3735 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
3736 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
3737 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
3738
3739 /******************* Bit definition for DMA_IFCR register *******************/
3740 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clearr */
3741 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
3742 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
3743 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
3744 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
3745 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
3746 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
3747 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
3748 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
3749 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
3750 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
3751 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
3752 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
3753 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
3754 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
3755 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
3756 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
3757 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
3758 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
3759 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
3760 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
3761 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
3762 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
3763 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
3764 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
3765 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
3766 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
3767 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
3768
3769 /******************* Bit definition for DMA_CCR register ********************/
3770 #define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */
3771 #define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
3772 #define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
3773 #define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
3774 #define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
3775 #define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
3776 #define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
3777 #define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
3778
3779 #define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
3780 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
3781 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
3782
3783 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
3784 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
3785 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
3786
3787 #define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/
3788 #define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
3789 #define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
3790
3791 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
3792
3793 /****************** Bit definition for DMA_CNDTR register *******************/
3794 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
3795
3796 /****************** Bit definition for DMA_CPAR register ********************/
3797 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
3798
3799 /****************** Bit definition for DMA_CMAR register ********************/
3800 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
3801
3802
3803 /******************* Bit definition for DMA_CSELR register *******************/
3804 #define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */
3805 #define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */
3806 #define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */
3807 #define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */
3808 #define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */
3809 #define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */
3810 #define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */
3811
3812
3813 /******************************************************************************/
3814 /* */
3815 /* External Interrupt/Event Controller */
3816 /* */
3817 /******************************************************************************/
3818 /******************* Bit definition for EXTI_IMR1 register ******************/
3819 #define EXTI_IMR1_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
3820 #define EXTI_IMR1_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
3821 #define EXTI_IMR1_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
3822 #define EXTI_IMR1_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
3823 #define EXTI_IMR1_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
3824 #define EXTI_IMR1_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
3825 #define EXTI_IMR1_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
3826 #define EXTI_IMR1_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
3827 #define EXTI_IMR1_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
3828 #define EXTI_IMR1_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
3829 #define EXTI_IMR1_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
3830 #define EXTI_IMR1_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
3831 #define EXTI_IMR1_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
3832 #define EXTI_IMR1_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
3833 #define EXTI_IMR1_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
3834 #define EXTI_IMR1_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
3835 #define EXTI_IMR1_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
3836 #define EXTI_IMR1_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
3837 #define EXTI_IMR1_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
3838 #define EXTI_IMR1_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
3839 #define EXTI_IMR1_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
3840 #define EXTI_IMR1_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
3841 #define EXTI_IMR1_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
3842 #define EXTI_IMR1_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
3843 #define EXTI_IMR1_IM24 ((uint32_t)0x01000000U) /*!< Interrupt Mask on line 24 */
3844 #define EXTI_IMR1_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */
3845 #define EXTI_IMR1_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */
3846 #define EXTI_IMR1_IM27 ((uint32_t)0x08000000U) /*!< Interrupt Mask on line 27 */
3847 #define EXTI_IMR1_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */
3848 #define EXTI_IMR1_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */
3849 #define EXTI_IMR1_IM30 ((uint32_t)0x40000000U) /*!< Interrupt Mask on line 30 */
3850 #define EXTI_IMR1_IM31 ((uint32_t)0x80000000U) /*!< Interrupt Mask on line 31 */
3851
3852 /******************* Bit definition for EXTI_EMR1 register ******************/
3853 #define EXTI_EMR1_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
3854 #define EXTI_EMR1_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
3855 #define EXTI_EMR1_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
3856 #define EXTI_EMR1_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
3857 #define EXTI_EMR1_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
3858 #define EXTI_EMR1_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
3859 #define EXTI_EMR1_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
3860 #define EXTI_EMR1_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
3861 #define EXTI_EMR1_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
3862 #define EXTI_EMR1_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
3863 #define EXTI_EMR1_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
3864 #define EXTI_EMR1_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
3865 #define EXTI_EMR1_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
3866 #define EXTI_EMR1_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
3867 #define EXTI_EMR1_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
3868 #define EXTI_EMR1_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
3869 #define EXTI_EMR1_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
3870 #define EXTI_EMR1_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
3871 #define EXTI_EMR1_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
3872 #define EXTI_EMR1_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
3873 #define EXTI_EMR1_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
3874 #define EXTI_EMR1_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
3875 #define EXTI_EMR1_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
3876 #define EXTI_EMR1_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
3877 #define EXTI_EMR1_EM24 ((uint32_t)0x01000000U) /*!< Event Mask on line 24 */
3878 #define EXTI_EMR1_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */
3879 #define EXTI_EMR1_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */
3880 #define EXTI_EMR1_EM27 ((uint32_t)0x08000000U) /*!< Event Mask on line 27 */
3881 #define EXTI_EMR1_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */
3882 #define EXTI_EMR1_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */
3883 #define EXTI_EMR1_EM30 ((uint32_t)0x40000000U) /*!< Event Mask on line 30 */
3884 #define EXTI_EMR1_EM31 ((uint32_t)0x80000000U) /*!< Event Mask on line 31 */
3885
3886 /****************** Bit definition for EXTI_RTSR1 register ******************/
3887 #define EXTI_RTSR1_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
3888 #define EXTI_RTSR1_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
3889 #define EXTI_RTSR1_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
3890 #define EXTI_RTSR1_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
3891 #define EXTI_RTSR1_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
3892 #define EXTI_RTSR1_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
3893 #define EXTI_RTSR1_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
3894 #define EXTI_RTSR1_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
3895 #define EXTI_RTSR1_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
3896 #define EXTI_RTSR1_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
3897 #define EXTI_RTSR1_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
3898 #define EXTI_RTSR1_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
3899 #define EXTI_RTSR1_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
3900 #define EXTI_RTSR1_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
3901 #define EXTI_RTSR1_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
3902 #define EXTI_RTSR1_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
3903 #define EXTI_RTSR1_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
3904 #define EXTI_RTSR1_RT18 ((uint32_t)0x00040000U) /*!< Rising trigger event configuration bit of line 18 */
3905 #define EXTI_RTSR1_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
3906 #define EXTI_RTSR1_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
3907 #define EXTI_RTSR1_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
3908 #define EXTI_RTSR1_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
3909
3910 /****************** Bit definition for EXTI_FTSR1 register ******************/
3911 #define EXTI_FTSR1_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
3912 #define EXTI_FTSR1_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
3913 #define EXTI_FTSR1_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
3914 #define EXTI_FTSR1_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
3915 #define EXTI_FTSR1_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
3916 #define EXTI_FTSR1_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
3917 #define EXTI_FTSR1_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
3918 #define EXTI_FTSR1_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
3919 #define EXTI_FTSR1_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
3920 #define EXTI_FTSR1_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
3921 #define EXTI_FTSR1_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
3922 #define EXTI_FTSR1_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
3923 #define EXTI_FTSR1_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
3924 #define EXTI_FTSR1_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
3925 #define EXTI_FTSR1_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
3926 #define EXTI_FTSR1_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
3927 #define EXTI_FTSR1_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
3928 #define EXTI_FTSR1_FT18 ((uint32_t)0x00040000U) /*!< Falling trigger event configuration bit of line 18 */
3929 #define EXTI_FTSR1_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
3930 #define EXTI_FTSR1_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
3931 #define EXTI_FTSR1_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
3932 #define EXTI_FTSR1_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
3933
3934 /****************** Bit definition for EXTI_SWIER1 register *****************/
3935 #define EXTI_SWIER1_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
3936 #define EXTI_SWIER1_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
3937 #define EXTI_SWIER1_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
3938 #define EXTI_SWIER1_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
3939 #define EXTI_SWIER1_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
3940 #define EXTI_SWIER1_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
3941 #define EXTI_SWIER1_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
3942 #define EXTI_SWIER1_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
3943 #define EXTI_SWIER1_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
3944 #define EXTI_SWIER1_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
3945 #define EXTI_SWIER1_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
3946 #define EXTI_SWIER1_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
3947 #define EXTI_SWIER1_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
3948 #define EXTI_SWIER1_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
3949 #define EXTI_SWIER1_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
3950 #define EXTI_SWIER1_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
3951 #define EXTI_SWIER1_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
3952 #define EXTI_SWIER1_SWI18 ((uint32_t)0x00040000U) /*!< Software Interrupt on line 18 */
3953 #define EXTI_SWIER1_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
3954 #define EXTI_SWIER1_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
3955 #define EXTI_SWIER1_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
3956 #define EXTI_SWIER1_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
3957
3958 /******************* Bit definition for EXTI_PR1 register *******************/
3959 #define EXTI_PR1_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit for line 0 */
3960 #define EXTI_PR1_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit for line 1 */
3961 #define EXTI_PR1_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit for line 2 */
3962 #define EXTI_PR1_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit for line 3 */
3963 #define EXTI_PR1_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit for line 4 */
3964 #define EXTI_PR1_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit for line 5 */
3965 #define EXTI_PR1_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit for line 6 */
3966 #define EXTI_PR1_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit for line 7 */
3967 #define EXTI_PR1_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit for line 8 */
3968 #define EXTI_PR1_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit for line 9 */
3969 #define EXTI_PR1_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit for line 10 */
3970 #define EXTI_PR1_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit for line 11 */
3971 #define EXTI_PR1_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit for line 12 */
3972 #define EXTI_PR1_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit for line 13 */
3973 #define EXTI_PR1_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit for line 14 */
3974 #define EXTI_PR1_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit for line 15 */
3975 #define EXTI_PR1_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit for line 16 */
3976 #define EXTI_PR1_PIF18 ((uint32_t)0x00040000U) /*!< Pending bit for line 18 */
3977 #define EXTI_PR1_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit for line 19 */
3978 #define EXTI_PR1_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit for line 20 */
3979 #define EXTI_PR1_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit for line 21 */
3980 #define EXTI_PR1_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit for line 22 */
3981
3982 /******************* Bit definition for EXTI_IMR2 register ******************/
3983 #define EXTI_IMR2_IM32 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 32 */
3984 #define EXTI_IMR2_IM33 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 33 */
3985 #define EXTI_IMR2_IM34 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 34 */
3986 #define EXTI_IMR2_IM35 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 35 */
3987 #define EXTI_IMR2_IM36 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 36 */
3988 #define EXTI_IMR2_IM37 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 37 */
3989 #define EXTI_IMR2_IM38 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 38 */
3990 #define EXTI_IMR2_IM39 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 39 */
3991
3992 /******************* Bit definition for EXTI_EMR2 register ******************/
3993 #define EXTI_EMR2_EM32 ((uint32_t)0x00000001U) /*!< Event Mask on line 32 */
3994 #define EXTI_EMR2_EM33 ((uint32_t)0x00000002U) /*!< Event Mask on line 33 */
3995 #define EXTI_EMR2_EM34 ((uint32_t)0x00000004U) /*!< Event Mask on line 34 */
3996 #define EXTI_EMR2_EM35 ((uint32_t)0x00000008U) /*!< Event Mask on line 35 */
3997 #define EXTI_EMR2_EM36 ((uint32_t)0x00000010U) /*!< Event Mask on line 36 */
3998 #define EXTI_EMR2_EM37 ((uint32_t)0x00000020U) /*!< Event Mask on line 37 */
3999 #define EXTI_EMR2_EM38 ((uint32_t)0x00000040U) /*!< Event Mask on line 38 */
4000 #define EXTI_EMR2_EM39 ((uint32_t)0x00000080U) /*!< Event Mask on line 39 */
4001
4002 /****************** Bit definition for EXTI_RTSR2 register ******************/
4003 #define EXTI_RTSR2_RT35 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 35 */
4004 #define EXTI_RTSR2_RT36 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 36 */
4005 #define EXTI_RTSR2_RT37 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 37 */
4006 #define EXTI_RTSR2_RT38 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 38 */
4007
4008 /****************** Bit definition for EXTI_FTSR2 register ******************/
4009 #define EXTI_FTSR2_FT35 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 35 */
4010 #define EXTI_FTSR2_FT36 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 36 */
4011 #define EXTI_FTSR2_FT37 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 37 */
4012 #define EXTI_FTSR2_FT38 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 38 */
4013
4014 /****************** Bit definition for EXTI_SWIER2 register *****************/
4015 #define EXTI_SWIER2_SWI35 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 35 */
4016 #define EXTI_SWIER2_SWI36 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 36 */
4017 #define EXTI_SWIER2_SWI37 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 37 */
4018 #define EXTI_SWIER2_SWI38 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 38 */
4019
4020 /******************* Bit definition for EXTI_PR2 register *******************/
4021 #define EXTI_PR2_PIF35 ((uint32_t)0x00000008U) /*!< Pending bit for line 35 */
4022 #define EXTI_PR2_PIF36 ((uint32_t)0x00000010U) /*!< Pending bit for line 36 */
4023 #define EXTI_PR2_PIF37 ((uint32_t)0x00000020U) /*!< Pending bit for line 37 */
4024 #define EXTI_PR2_PIF38 ((uint32_t)0x00000040U) /*!< Pending bit for line 38 */
4025
4026
4027 /******************************************************************************/
4028 /* */
4029 /* FLASH */
4030 /* */
4031 /******************************************************************************/
4032 /******************* Bits definition for FLASH_ACR register *****************/
4033 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007U)
4034 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000U)
4035 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001U)
4036 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002U)
4037 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003U)
4038 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004U)
4039 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100U)
4040 #define FLASH_ACR_ICEN ((uint32_t)0x00000200U)
4041 #define FLASH_ACR_DCEN ((uint32_t)0x00000400U)
4042 #define FLASH_ACR_ICRST ((uint32_t)0x00000800U)
4043 #define FLASH_ACR_DCRST ((uint32_t)0x00001000U)
4044 #define FLASH_ACR_RUN_PD ((uint32_t)0x00002000U) /*!< Flash power down mode during run */
4045 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00004000U) /*!< Flash power down mode during sleep */
4046
4047 /******************* Bits definition for FLASH_SR register ******************/
4048 #define FLASH_SR_EOP ((uint32_t)0x00000001U)
4049 #define FLASH_SR_OPERR ((uint32_t)0x00000002U)
4050 #define FLASH_SR_PROGERR ((uint32_t)0x00000008U)
4051 #define FLASH_SR_WRPERR ((uint32_t)0x00000010U)
4052 #define FLASH_SR_PGAERR ((uint32_t)0x00000020U)
4053 #define FLASH_SR_SIZERR ((uint32_t)0x00000040U)
4054 #define FLASH_SR_PGSERR ((uint32_t)0x00000080U)
4055 #define FLASH_SR_MISERR ((uint32_t)0x00000100U)
4056 #define FLASH_SR_FASTERR ((uint32_t)0x00000200U)
4057 #define FLASH_SR_RDERR ((uint32_t)0x00004000U)
4058 #define FLASH_SR_OPTVERR ((uint32_t)0x00008000U)
4059 #define FLASH_SR_BSY ((uint32_t)0x00010000U)
4060
4061 /******************* Bits definition for FLASH_CR register ******************/
4062 #define FLASH_CR_PG ((uint32_t)0x00000001U)
4063 #define FLASH_CR_PER ((uint32_t)0x00000002U)
4064 #define FLASH_CR_MER1 ((uint32_t)0x00000004U)
4065 #define FLASH_CR_PNB ((uint32_t)0x000007F8U)
4066 #define FLASH_CR_BKER ((uint32_t)0x00000800U)
4067 #define FLASH_CR_MER2 ((uint32_t)0x00008000U)
4068 #define FLASH_CR_STRT ((uint32_t)0x00010000U)
4069 #define FLASH_CR_OPTSTRT ((uint32_t)0x00020000U)
4070 #define FLASH_CR_FSTPG ((uint32_t)0x00040000U)
4071 #define FLASH_CR_EOPIE ((uint32_t)0x01000000U)
4072 #define FLASH_CR_ERRIE ((uint32_t)0x02000000U)
4073 #define FLASH_CR_RDERRIE ((uint32_t)0x04000000U)
4074 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x08000000U)
4075 #define FLASH_CR_OPTLOCK ((uint32_t)0x40000000U)
4076 #define FLASH_CR_LOCK ((uint32_t)0x80000000U)
4077
4078 /******************* Bits definition for FLASH_ECCR register ***************/
4079 #define FLASH_ECCR_ADDR_ECC ((uint32_t)0x0007FFFFU)
4080 #define FLASH_ECCR_BK_ECC ((uint32_t)0x00080000U)
4081 #define FLASH_ECCR_SYSF_ECC ((uint32_t)0x00100000U)
4082 #define FLASH_ECCR_ECCIE ((uint32_t)0x01000000U)
4083 #define FLASH_ECCR_ECCC ((uint32_t)0x40000000U)
4084 #define FLASH_ECCR_ECCD ((uint32_t)0x80000000U)
4085
4086 /******************* Bits definition for FLASH_OPTR register ***************/
4087 #define FLASH_OPTR_RDP ((uint32_t)0x000000FFU)
4088 #define FLASH_OPTR_BOR_LEV ((uint32_t)0x00000700U)
4089 #define FLASH_OPTR_BOR_LEV_0 ((uint32_t)0x00000000U)
4090 #define FLASH_OPTR_BOR_LEV_1 ((uint32_t)0x00000100U)
4091 #define FLASH_OPTR_BOR_LEV_2 ((uint32_t)0x00000200U)
4092 #define FLASH_OPTR_BOR_LEV_3 ((uint32_t)0x00000300U)
4093 #define FLASH_OPTR_BOR_LEV_4 ((uint32_t)0x00000400U)
4094 #define FLASH_OPTR_nRST_STOP ((uint32_t)0x00001000U)
4095 #define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00002000U)
4096 #define FLASH_OPTR_nRST_SHDW ((uint32_t)0x00004000U)
4097 #define FLASH_OPTR_IWDG_SW ((uint32_t)0x00010000U)
4098 #define FLASH_OPTR_IWDG_STOP ((uint32_t)0x00020000U)
4099 #define FLASH_OPTR_IWDG_STDBY ((uint32_t)0x00040000U)
4100 #define FLASH_OPTR_WWDG_SW ((uint32_t)0x00080000U)
4101 #define FLASH_OPTR_BFB2 ((uint32_t)0x00100000U)
4102 #define FLASH_OPTR_DUALBANK ((uint32_t)0x00200000U)
4103 #define FLASH_OPTR_nBOOT1 ((uint32_t)0x00800000U)
4104 #define FLASH_OPTR_SRAM2_PE ((uint32_t)0x01000000U)
4105 #define FLASH_OPTR_SRAM2_RST ((uint32_t)0x02000000U)
4106
4107 /****************** Bits definition for FLASH_PCROP1SR register **********/
4108 #define FLASH_PCROP1SR_PCROP1_STRT ((uint32_t)0x0000FFFFU)
4109
4110 /****************** Bits definition for FLASH_PCROP1ER register ***********/
4111 #define FLASH_PCROP1ER_PCROP1_END ((uint32_t)0x0000FFFFU)
4112 #define FLASH_PCROP1ER_PCROP_RDP ((uint32_t)0x80000000U)
4113
4114 /****************** Bits definition for FLASH_WRP1AR register ***************/
4115 #define FLASH_WRP1AR_WRP1A_STRT ((uint32_t)0x000000FFU)
4116 #define FLASH_WRP1AR_WRP1A_END ((uint32_t)0x00FF0000U)
4117
4118 /****************** Bits definition for FLASH_WRPB1R register ***************/
4119 #define FLASH_WRP1BR_WRP1B_STRT ((uint32_t)0x000000FFU)
4120 #define FLASH_WRP1BR_WRP1B_END ((uint32_t)0x00FF0000U)
4121
4122 /****************** Bits definition for FLASH_PCROP2SR register **********/
4123 #define FLASH_PCROP2SR_PCROP2_STRT ((uint32_t)0x0000FFFFU)
4124
4125 /****************** Bits definition for FLASH_PCROP2ER register ***********/
4126 #define FLASH_PCROP2ER_PCROP2_END ((uint32_t)0x0000FFFFU)
4127
4128 /****************** Bits definition for FLASH_WRP2AR register ***************/
4129 #define FLASH_WRP2AR_WRP2A_STRT ((uint32_t)0x000000FFU)
4130 #define FLASH_WRP2AR_WRP2A_END ((uint32_t)0x00FF0000U)
4131
4132 /****************** Bits definition for FLASH_WRP2BR register ***************/
4133 #define FLASH_WRP2BR_WRP2B_STRT ((uint32_t)0x000000FFU)
4134 #define FLASH_WRP2BR_WRP2B_END ((uint32_t)0x00FF0000U)
4135
4136
4137 /******************************************************************************/
4138 /* */
4139 /* Flexible Memory Controller */
4140 /* */
4141 /******************************************************************************/
4142 /****************** Bit definition for FMC_BCR1 register *******************/
4143 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000U) /*!<Continous clock enable */
4144
4145 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
4146 #define FMC_BCRx_MBKEN ((uint32_t)0x00000001U) /*!<Memory bank enable bit */
4147 #define FMC_BCRx_MUXEN ((uint32_t)0x00000002U) /*!<Address/data multiplexing enable bit */
4148
4149 #define FMC_BCRx_MTYP ((uint32_t)0x0000000CU) /*!<MTYP[1:0] bits (Memory type) */
4150 #define FMC_BCRx_MTYP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
4151 #define FMC_BCRx_MTYP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
4152
4153 #define FMC_BCRx_MWID ((uint32_t)0x00000030U) /*!<MWID[1:0] bits (Memory data bus width) */
4154 #define FMC_BCRx_MWID_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
4155 #define FMC_BCRx_MWID_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
4156
4157 #define FMC_BCRx_FACCEN ((uint32_t)0x00000040U) /*!<Flash access enable */
4158 #define FMC_BCRx_BURSTEN ((uint32_t)0x00000100U) /*!<Burst enable bit */
4159 #define FMC_BCRx_WAITPOL ((uint32_t)0x00000200U) /*!<Wait signal polarity bit */
4160 #define FMC_BCRx_WAITCFG ((uint32_t)0x00000800U) /*!<Wait timing configuration */
4161 #define FMC_BCRx_WREN ((uint32_t)0x00001000U) /*!<Write enable bit */
4162 #define FMC_BCRx_WAITEN ((uint32_t)0x00002000U) /*!<Wait enable bit */
4163 #define FMC_BCRx_EXTMOD ((uint32_t)0x00004000U) /*!<Extended mode enable */
4164 #define FMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000U) /*!<Asynchronous wait */
4165
4166 #define FMC_BCRx_CPSIZE ((uint32_t)0x00070000U) /*!<CRAM page size */
4167 #define FMC_BCRx_CPSIZE_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
4168 #define FMC_BCRx_CPSIZE_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
4169 #define FMC_BCRx_CPSIZE_2 ((uint32_t)0x00040000U) /*!<Bit 1 */
4170
4171 #define FMC_BCRx_CBURSTRW ((uint32_t)0x00080000U) /*!<Write burst enable */
4172
4173 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
4174 #define FMC_BTRx_ADDSET ((uint32_t)0x0000000FU) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4175 #define FMC_BTRx_ADDSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
4176 #define FMC_BTRx_ADDSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
4177 #define FMC_BTRx_ADDSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
4178 #define FMC_BTRx_ADDSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
4179
4180 #define FMC_BTRx_ADDHLD ((uint32_t)0x000000F0U) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4181 #define FMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
4182 #define FMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
4183 #define FMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
4184 #define FMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
4185
4186 #define FMC_BTRx_DATAST ((uint32_t)0x0000FF00U) /*!<DATAST [3:0] bits (Data-phase duration) */
4187 #define FMC_BTRx_DATAST_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
4188 #define FMC_BTRx_DATAST_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
4189 #define FMC_BTRx_DATAST_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
4190 #define FMC_BTRx_DATAST_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
4191 #define FMC_BTRx_DATAST_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
4192 #define FMC_BTRx_DATAST_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
4193 #define FMC_BTRx_DATAST_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
4194 #define FMC_BTRx_DATAST_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
4195
4196 #define FMC_BTRx_BUSTURN ((uint32_t)0x000F0000U) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4197 #define FMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
4198 #define FMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
4199 #define FMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
4200 #define FMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
4201
4202 #define FMC_BTRx_CLKDIV ((uint32_t)0x00F00000U) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4203 #define FMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
4204 #define FMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
4205 #define FMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
4206 #define FMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000U) /*!<Bit 3 */
4207
4208 #define FMC_BTRx_DATLAT ((uint32_t)0x0F000000U) /*!<DATLA[3:0] bits (Data latency) */
4209 #define FMC_BTRx_DATLAT_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
4210 #define FMC_BTRx_DATLAT_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
4211 #define FMC_BTRx_DATLAT_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
4212 #define FMC_BTRx_DATLAT_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
4213
4214 #define FMC_BTRx_ACCMOD ((uint32_t)0x30000000U) /*!<ACCMOD[1:0] bits (Access mode) */
4215 #define FMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
4216 #define FMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
4217
4218 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
4219 #define FMC_BWTRx_ADDSET ((uint32_t)0x0000000FU) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4220 #define FMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
4221 #define FMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
4222 #define FMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
4223 #define FMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
4224
4225 #define FMC_BWTRx_ADDHLD ((uint32_t)0x000000F0U) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4226 #define FMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
4227 #define FMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
4228 #define FMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
4229 #define FMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
4230
4231 #define FMC_BWTRx_DATAST ((uint32_t)0x0000FF00U) /*!<DATAST [3:0] bits (Data-phase duration) */
4232 #define FMC_BWTRx_DATAST_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
4233 #define FMC_BWTRx_DATAST_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
4234 #define FMC_BWTRx_DATAST_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
4235 #define FMC_BWTRx_DATAST_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
4236 #define FMC_BWTRx_DATAST_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
4237 #define FMC_BWTRx_DATAST_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
4238 #define FMC_BWTRx_DATAST_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
4239 #define FMC_BWTRx_DATAST_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
4240
4241 #define FMC_BWTRx_ACCMOD ((uint32_t)0x30000000U) /*!<ACCMOD[1:0] bits (Access mode) */
4242 #define FMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
4243 #define FMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
4244
4245 /****************** Bit definition for FMC_PCR register ********************/
4246 #define FMC_PCR_PWAITEN ((uint32_t)0x00000002U) /*!<Wait feature enable bit */
4247 #define FMC_PCR_PBKEN ((uint32_t)0x00000004U) /*!<NAND Flash memory bank enable bit */
4248 #define FMC_PCR_PTYP ((uint32_t)0x00000008U) /*!<Memory type */
4249
4250 #define FMC_PCR_PWID ((uint32_t)0x00000030U) /*!<PWID[1:0] bits (NAND Flash databus width) */
4251 #define FMC_PCR_PWID_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
4252 #define FMC_PCR_PWID_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
4253
4254 #define FMC_PCR_ECCEN ((uint32_t)0x00000040U) /*!<ECC computation logic enable bit */
4255
4256 #define FMC_PCR_TCLR ((uint32_t)0x00001E00U) /*!<TCLR[3:0] bits (CLE to RE delay) */
4257 #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
4258 #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
4259 #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800U) /*!<Bit 2 */
4260 #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000U) /*!<Bit 3 */
4261
4262 #define FMC_PCR_TAR ((uint32_t)0x0001E000U) /*!<TAR[3:0] bits (ALE to RE delay) */
4263 #define FMC_PCR_TAR_0 ((uint32_t)0x00002000U) /*!<Bit 0 */
4264 #define FMC_PCR_TAR_1 ((uint32_t)0x00004000U) /*!<Bit 1 */
4265 #define FMC_PCR_TAR_2 ((uint32_t)0x00008000U) /*!<Bit 2 */
4266 #define FMC_PCR_TAR_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
4267
4268 #define FMC_PCR_ECCPS ((uint32_t)0x000E0000U) /*!<ECCPS[1:0] bits (ECC page size) */
4269 #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
4270 #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
4271 #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
4272
4273 /******************* Bit definition for FMC_SR register ********************/
4274 #define FMC_SR_IRS ((uint32_t)0x00000001U) /*!<Interrupt Rising Edge status */
4275 #define FMC_SR_ILS ((uint32_t)0x00000002U) /*!<Interrupt Level status */
4276 #define FMC_SR_IFS ((uint32_t)0x00000004U) /*!<Interrupt Falling Edge status */
4277 #define FMC_SR_IREN ((uint32_t)0x00000008U) /*!<Interrupt Rising Edge detection Enable bit */
4278 #define FMC_SR_ILEN ((uint32_t)0x00000010U) /*!<Interrupt Level detection Enable bit */
4279 #define FMC_SR_IFEN ((uint32_t)0x00000020U) /*!<Interrupt Falling Edge detection Enable bit */
4280 #define FMC_SR_FEMPT ((uint32_t)0x00000040U) /*!<FIFO empty */
4281
4282 /****************** Bit definition for FMC_PMEM register ******************/
4283 #define FMC_PMEM_MEMSET ((uint32_t)0x000000FFU) /*!<MEMSET[7:0] bits (Common memory setup time) */
4284 #define FMC_PMEM_MEMSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
4285 #define FMC_PMEM_MEMSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
4286 #define FMC_PMEM_MEMSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
4287 #define FMC_PMEM_MEMSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
4288 #define FMC_PMEM_MEMSET_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
4289 #define FMC_PMEM_MEMSET_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
4290 #define FMC_PMEM_MEMSET_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
4291 #define FMC_PMEM_MEMSET_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
4292
4293 #define FMC_PMEM_MEMWAIT ((uint32_t)0x0000FF00U) /*!<MEMWAIT[7:0] bits (Common memory wait time) */
4294 #define FMC_PMEM_MEMWAIT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
4295 #define FMC_PMEM_MEMWAIT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
4296 #define FMC_PMEM_MEMWAIT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
4297 #define FMC_PMEM_MEMWAIT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
4298 #define FMC_PMEM_MEMWAIT_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
4299 #define FMC_PMEM_MEMWAIT_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
4300 #define FMC_PMEM_MEMWAIT_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
4301 #define FMC_PMEM_MEMWAIT_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
4302
4303 #define FMC_PMEM_MEMHOLD ((uint32_t)0x00FF0000U) /*!<MEMHOLD[7:0] bits (Common memory hold time) */
4304 #define FMC_PMEM_MEMHOLD_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
4305 #define FMC_PMEM_MEMHOLD_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
4306 #define FMC_PMEM_MEMHOLD_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
4307 #define FMC_PMEM_MEMHOLD_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
4308 #define FMC_PMEM_MEMHOLD_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
4309 #define FMC_PMEM_MEMHOLD_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
4310 #define FMC_PMEM_MEMHOLD_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
4311 #define FMC_PMEM_MEMHOLD_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
4312
4313 #define FMC_PMEM_MEMHIZ ((uint32_t)0xFF000000U) /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
4314 #define FMC_PMEM_MEMHIZ_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
4315 #define FMC_PMEM_MEMHIZ_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
4316 #define FMC_PMEM_MEMHIZ_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
4317 #define FMC_PMEM_MEMHIZ_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
4318 #define FMC_PMEM_MEMHIZ_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
4319 #define FMC_PMEM_MEMHIZ_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
4320 #define FMC_PMEM_MEMHIZ_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
4321 #define FMC_PMEM_MEMHIZ_7 ((uint32_t)0x80000000U) /*!<Bit 7 */
4322
4323 /****************** Bit definition for FMC_PATT register *******************/
4324 #define FMC_PATT_ATTSET ((uint32_t)0x000000FFU) /*!<ATTSET[7:0] bits (Attribute memory setup time) */
4325 #define FMC_PATT_ATTSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
4326 #define FMC_PATT_ATTSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
4327 #define FMC_PATT_ATTSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
4328 #define FMC_PATT_ATTSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
4329 #define FMC_PATT_ATTSET_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
4330 #define FMC_PATT_ATTSET_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
4331 #define FMC_PATT_ATTSET_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
4332 #define FMC_PATT_ATTSET_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
4333
4334 #define FMC_PATT_ATTWAIT ((uint32_t)0x0000FF00U) /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
4335 #define FMC_PATT_ATTWAIT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
4336 #define FMC_PATT_ATTWAIT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
4337 #define FMC_PATT_ATTWAIT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
4338 #define FMC_PATT_ATTWAIT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
4339 #define FMC_PATT_ATTWAIT_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
4340 #define FMC_PATT_ATTWAIT_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
4341 #define FMC_PATT_ATTWAIT_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
4342 #define FMC_PATT_ATTWAIT_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
4343
4344 #define FMC_PATT_ATTHOLD ((uint32_t)0x00FF0000U) /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
4345 #define FMC_PATT_ATTHOLD_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
4346 #define FMC_PATT_ATTHOLD_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
4347 #define FMC_PATT_ATTHOLD_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
4348 #define FMC_PATT_ATTHOLD_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
4349 #define FMC_PATT_ATTHOLD_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
4350 #define FMC_PATT_ATTHOLD_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
4351 #define FMC_PATT_ATTHOLD_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
4352 #define FMC_PATT_ATTHOLD_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
4353
4354 #define FMC_PATT_ATTHIZ ((uint32_t)0xFF000000U) /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
4355 #define FMC_PATT_ATTHIZ_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
4356 #define FMC_PATT_ATTHIZ_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
4357 #define FMC_PATT_ATTHIZ_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
4358 #define FMC_PATT_ATTHIZ_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
4359 #define FMC_PATT_ATTHIZ_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
4360 #define FMC_PATT_ATTHIZ_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
4361 #define FMC_PATT_ATTHIZ_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
4362 #define FMC_PATT_ATTHIZ_7 ((uint32_t)0x80000000U) /*!<Bit 7 */
4363
4364 /****************** Bit definition for FMC_ECCR register *******************/
4365 #define FMC_ECCR_ECC ((uint32_t)0xFFFFFFFFU) /*!<ECC result */
4366
4367 /******************************************************************************/
4368 /* */
4369 /* General Purpose IOs (GPIO) */
4370 /* */
4371 /******************************************************************************/
4372 /****************** Bits definition for GPIO_MODER register *****************/
4373 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
4374 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
4375 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
4376 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
4377 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
4378 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
4379 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
4380 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
4381 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
4382 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
4383 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
4384 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
4385 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
4386 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
4387 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
4388 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
4389 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
4390 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
4391 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
4392 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
4393 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
4394 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
4395 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
4396 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
4397 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
4398 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
4399 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
4400 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
4401 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
4402 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
4403 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
4404 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
4405 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
4406 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
4407 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
4408 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
4409 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
4410 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
4411 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
4412 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
4413 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
4414 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
4415 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
4416 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
4417 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
4418 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
4419 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
4420 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
4421
4422 /* Legacy defines */
4423 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
4424 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
4425 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
4426 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
4427 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
4428 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
4429 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
4430 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
4431 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
4432 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
4433 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
4434 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
4435 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
4436 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
4437 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
4438 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
4439 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
4440 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
4441 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
4442 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
4443 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
4444 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
4445 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
4446 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
4447 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
4448 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
4449 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
4450 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
4451 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
4452 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
4453 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
4454 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
4455 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
4456 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
4457 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
4458 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
4459 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
4460 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
4461 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
4462 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
4463 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
4464 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
4465 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
4466 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
4467 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
4468 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
4469 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
4470 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
4471
4472 /****************** Bits definition for GPIO_OTYPER register ****************/
4473 #define GPIO_OTYPER_OT0 ((uint32_t)0x00000001U)
4474 #define GPIO_OTYPER_OT1 ((uint32_t)0x00000002U)
4475 #define GPIO_OTYPER_OT2 ((uint32_t)0x00000004U)
4476 #define GPIO_OTYPER_OT3 ((uint32_t)0x00000008U)
4477 #define GPIO_OTYPER_OT4 ((uint32_t)0x00000010U)
4478 #define GPIO_OTYPER_OT5 ((uint32_t)0x00000020U)
4479 #define GPIO_OTYPER_OT6 ((uint32_t)0x00000040U)
4480 #define GPIO_OTYPER_OT7 ((uint32_t)0x00000080U)
4481 #define GPIO_OTYPER_OT8 ((uint32_t)0x00000100U)
4482 #define GPIO_OTYPER_OT9 ((uint32_t)0x00000200U)
4483 #define GPIO_OTYPER_OT10 ((uint32_t)0x00000400U)
4484 #define GPIO_OTYPER_OT11 ((uint32_t)0x00000800U)
4485 #define GPIO_OTYPER_OT12 ((uint32_t)0x00001000U)
4486 #define GPIO_OTYPER_OT13 ((uint32_t)0x00002000U)
4487 #define GPIO_OTYPER_OT14 ((uint32_t)0x00004000U)
4488 #define GPIO_OTYPER_OT15 ((uint32_t)0x00008000U)
4489
4490 /* Legacy defines */
4491 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
4492 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
4493 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
4494 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
4495 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
4496 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
4497 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
4498 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
4499 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
4500 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
4501 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
4502 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
4503 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
4504 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
4505 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
4506 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
4507
4508 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4509 #define GPIO_OSPEEDR_OSPEED0 ((uint32_t)0x00000003U)
4510 #define GPIO_OSPEEDR_OSPEED0_0 ((uint32_t)0x00000001U)
4511 #define GPIO_OSPEEDR_OSPEED0_1 ((uint32_t)0x00000002U)
4512 #define GPIO_OSPEEDR_OSPEED1 ((uint32_t)0x0000000CU)
4513 #define GPIO_OSPEEDR_OSPEED1_0 ((uint32_t)0x00000004U)
4514 #define GPIO_OSPEEDR_OSPEED1_1 ((uint32_t)0x00000008U)
4515 #define GPIO_OSPEEDR_OSPEED2 ((uint32_t)0x00000030U)
4516 #define GPIO_OSPEEDR_OSPEED2_0 ((uint32_t)0x00000010U)
4517 #define GPIO_OSPEEDR_OSPEED2_1 ((uint32_t)0x00000020U)
4518 #define GPIO_OSPEEDR_OSPEED3 ((uint32_t)0x000000C0U)
4519 #define GPIO_OSPEEDR_OSPEED3_0 ((uint32_t)0x00000040U)
4520 #define GPIO_OSPEEDR_OSPEED3_1 ((uint32_t)0x00000080U)
4521 #define GPIO_OSPEEDR_OSPEED4 ((uint32_t)0x00000300U)
4522 #define GPIO_OSPEEDR_OSPEED4_0 ((uint32_t)0x00000100U)
4523 #define GPIO_OSPEEDR_OSPEED4_1 ((uint32_t)0x00000200U)
4524 #define GPIO_OSPEEDR_OSPEED5 ((uint32_t)0x00000C00U)
4525 #define GPIO_OSPEEDR_OSPEED5_0 ((uint32_t)0x00000400U)
4526 #define GPIO_OSPEEDR_OSPEED5_1 ((uint32_t)0x00000800U)
4527 #define GPIO_OSPEEDR_OSPEED6 ((uint32_t)0x00003000U)
4528 #define GPIO_OSPEEDR_OSPEED6_0 ((uint32_t)0x00001000U)
4529 #define GPIO_OSPEEDR_OSPEED6_1 ((uint32_t)0x00002000U)
4530 #define GPIO_OSPEEDR_OSPEED7 ((uint32_t)0x0000C000U)
4531 #define GPIO_OSPEEDR_OSPEED7_0 ((uint32_t)0x00004000U)
4532 #define GPIO_OSPEEDR_OSPEED7_1 ((uint32_t)0x00008000U)
4533 #define GPIO_OSPEEDR_OSPEED8 ((uint32_t)0x00030000U)
4534 #define GPIO_OSPEEDR_OSPEED8_0 ((uint32_t)0x00010000U)
4535 #define GPIO_OSPEEDR_OSPEED8_1 ((uint32_t)0x00020000U)
4536 #define GPIO_OSPEEDR_OSPEED9 ((uint32_t)0x000C0000U)
4537 #define GPIO_OSPEEDR_OSPEED9_0 ((uint32_t)0x00040000U)
4538 #define GPIO_OSPEEDR_OSPEED9_1 ((uint32_t)0x00080000U)
4539 #define GPIO_OSPEEDR_OSPEED10 ((uint32_t)0x00300000U)
4540 #define GPIO_OSPEEDR_OSPEED10_0 ((uint32_t)0x00100000U)
4541 #define GPIO_OSPEEDR_OSPEED10_1 ((uint32_t)0x00200000U)
4542 #define GPIO_OSPEEDR_OSPEED11 ((uint32_t)0x00C00000U)
4543 #define GPIO_OSPEEDR_OSPEED11_0 ((uint32_t)0x00400000U)
4544 #define GPIO_OSPEEDR_OSPEED11_1 ((uint32_t)0x00800000U)
4545 #define GPIO_OSPEEDR_OSPEED12 ((uint32_t)0x03000000U)
4546 #define GPIO_OSPEEDR_OSPEED12_0 ((uint32_t)0x01000000U)
4547 #define GPIO_OSPEEDR_OSPEED12_1 ((uint32_t)0x02000000U)
4548 #define GPIO_OSPEEDR_OSPEED13 ((uint32_t)0x0C000000U)
4549 #define GPIO_OSPEEDR_OSPEED13_0 ((uint32_t)0x04000000U)
4550 #define GPIO_OSPEEDR_OSPEED13_1 ((uint32_t)0x08000000U)
4551 #define GPIO_OSPEEDR_OSPEED14 ((uint32_t)0x30000000U)
4552 #define GPIO_OSPEEDR_OSPEED14_0 ((uint32_t)0x10000000U)
4553 #define GPIO_OSPEEDR_OSPEED14_1 ((uint32_t)0x20000000U)
4554 #define GPIO_OSPEEDR_OSPEED15 ((uint32_t)0xC0000000U)
4555 #define GPIO_OSPEEDR_OSPEED15_0 ((uint32_t)0x40000000U)
4556 #define GPIO_OSPEEDR_OSPEED15_1 ((uint32_t)0x80000000U)
4557
4558 /* Legacy defines */
4559 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
4560 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
4561 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
4562 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
4563 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
4564 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
4565 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
4566 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
4567 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
4568 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
4569 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
4570 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
4571 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
4572 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
4573 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
4574 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
4575 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
4576 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
4577 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
4578 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
4579 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
4580 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
4581 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
4582 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
4583 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
4584 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
4585 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
4586 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
4587 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
4588 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
4589 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
4590 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
4591 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
4592 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
4593 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
4594 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
4595 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
4596 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
4597 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
4598 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
4599 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
4600 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
4601 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
4602 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
4603 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
4604 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
4605 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
4606 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
4607
4608 /****************** Bits definition for GPIO_PUPDR register *****************/
4609 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
4610 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
4611 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
4612 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
4613 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
4614 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
4615 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
4616 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
4617 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
4618 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
4619 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
4620 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
4621 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
4622 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
4623 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
4624 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
4625 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
4626 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
4627 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
4628 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
4629 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
4630 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
4631 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
4632 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
4633 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
4634 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
4635 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
4636 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
4637 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
4638 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
4639 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
4640 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
4641 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
4642 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
4643 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
4644 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
4645 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
4646 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
4647 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
4648 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
4649 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
4650 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
4651 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
4652 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
4653 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
4654 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
4655 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
4656 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
4657
4658 /* Legacy defines */
4659 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
4660 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
4661 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
4662 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
4663 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
4664 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
4665 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
4666 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
4667 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
4668 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
4669 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
4670 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
4671 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
4672 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
4673 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
4674 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
4675 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
4676 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
4677 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
4678 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
4679 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
4680 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
4681 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
4682 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
4683 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
4684 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
4685 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
4686 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
4687 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
4688 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
4689 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
4690 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
4691 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
4692 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
4693 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
4694 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
4695 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
4696 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
4697 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
4698 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
4699 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
4700 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
4701 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
4702 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
4703 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
4704 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
4705 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
4706 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
4707
4708 /****************** Bits definition for GPIO_IDR register *******************/
4709 #define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
4710 #define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
4711 #define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
4712 #define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
4713 #define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
4714 #define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
4715 #define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
4716 #define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
4717 #define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
4718 #define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
4719 #define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
4720 #define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
4721 #define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
4722 #define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
4723 #define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
4724 #define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
4725
4726 /* Legacy defines */
4727 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
4728 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
4729 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
4730 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
4731 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
4732 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
4733 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
4734 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
4735 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
4736 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
4737 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
4738 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
4739 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
4740 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
4741 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
4742 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
4743
4744 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4745 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
4746 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
4747 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
4748 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
4749 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
4750 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
4751 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
4752 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
4753 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
4754 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
4755 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
4756 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
4757 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
4758 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
4759 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
4760 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
4761
4762 /****************** Bits definition for GPIO_ODR register *******************/
4763 #define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
4764 #define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
4765 #define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
4766 #define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
4767 #define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
4768 #define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
4769 #define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
4770 #define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
4771 #define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
4772 #define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
4773 #define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
4774 #define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
4775 #define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
4776 #define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
4777 #define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
4778 #define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
4779
4780 /* Legacy defines */
4781 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
4782 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
4783 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
4784 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
4785 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
4786 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
4787 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
4788 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
4789 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
4790 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
4791 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
4792 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
4793 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
4794 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
4795 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
4796 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
4797
4798 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4799 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
4800 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
4801 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
4802 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
4803 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
4804 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
4805 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
4806 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
4807 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
4808 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
4809 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
4810 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
4811 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
4812 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
4813 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
4814 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
4815
4816 /****************** Bits definition for GPIO_BSRR register ******************/
4817 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001U)
4818 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002U)
4819 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004U)
4820 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008U)
4821 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010U)
4822 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020U)
4823 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040U)
4824 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080U)
4825 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100U)
4826 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200U)
4827 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400U)
4828 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800U)
4829 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000U)
4830 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000U)
4831 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000U)
4832 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000U)
4833 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000U)
4834 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000U)
4835 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000U)
4836 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000U)
4837 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000U)
4838 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000U)
4839 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000U)
4840 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000U)
4841 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000U)
4842 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000U)
4843 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000U)
4844 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000U)
4845 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000U)
4846 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000U)
4847 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000U)
4848 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000U)
4849
4850 /* Legacy defines */
4851 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
4852 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
4853 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
4854 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
4855 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
4856 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
4857 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
4858 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
4859 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
4860 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
4861 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
4862 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
4863 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
4864 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
4865 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
4866 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
4867 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
4868 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
4869 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
4870 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
4871 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
4872 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
4873 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
4874 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
4875 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
4876 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
4877 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
4878 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
4879 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
4880 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
4881 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
4882 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
4883
4884 /****************** Bit definition for GPIO_LCKR register *********************/
4885 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
4886 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
4887 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
4888 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
4889 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
4890 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
4891 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
4892 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
4893 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
4894 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
4895 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
4896 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
4897 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
4898 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
4899 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
4900 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
4901 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
4902
4903 /****************** Bit definition for GPIO_AFRL register *********************/
4904 #define GPIO_AFRL_AFSEL0 ((uint32_t)0x0000000FU)
4905 #define GPIO_AFRL_AFSEL0_0 ((uint32_t)0x00000001U)
4906 #define GPIO_AFRL_AFSEL0_1 ((uint32_t)0x00000002U)
4907 #define GPIO_AFRL_AFSEL0_2 ((uint32_t)0x00000004U)
4908 #define GPIO_AFRL_AFSEL0_3 ((uint32_t)0x00000008U)
4909 #define GPIO_AFRL_AFSEL1 ((uint32_t)0x000000F0U)
4910 #define GPIO_AFRL_AFSEL1_0 ((uint32_t)0x00000010U)
4911 #define GPIO_AFRL_AFSEL1_1 ((uint32_t)0x00000020U)
4912 #define GPIO_AFRL_AFSEL1_2 ((uint32_t)0x00000040U)
4913 #define GPIO_AFRL_AFSEL1_3 ((uint32_t)0x00000080U)
4914 #define GPIO_AFRL_AFSEL2 ((uint32_t)0x00000F00U)
4915 #define GPIO_AFRL_AFSEL2_0 ((uint32_t)0x00000100U)
4916 #define GPIO_AFRL_AFSEL2_1 ((uint32_t)0x00000200U)
4917 #define GPIO_AFRL_AFSEL2_2 ((uint32_t)0x00000400U)
4918 #define GPIO_AFRL_AFSEL2_3 ((uint32_t)0x00000800U)
4919 #define GPIO_AFRL_AFSEL3 ((uint32_t)0x0000F000U)
4920 #define GPIO_AFRL_AFSEL3_0 ((uint32_t)0x00001000U)
4921 #define GPIO_AFRL_AFSEL3_1 ((uint32_t)0x00002000U)
4922 #define GPIO_AFRL_AFSEL3_2 ((uint32_t)0x00004000U)
4923 #define GPIO_AFRL_AFSEL3_3 ((uint32_t)0x00008000U)
4924 #define GPIO_AFRL_AFSEL4 ((uint32_t)0x000F0000U)
4925 #define GPIO_AFRL_AFSEL4_0 ((uint32_t)0x00010000U)
4926 #define GPIO_AFRL_AFSEL4_1 ((uint32_t)0x00020000U)
4927 #define GPIO_AFRL_AFSEL4_2 ((uint32_t)0x00040000U)
4928 #define GPIO_AFRL_AFSEL4_3 ((uint32_t)0x00080000U)
4929 #define GPIO_AFRL_AFSEL5 ((uint32_t)0x00F00000U)
4930 #define GPIO_AFRL_AFSEL5_0 ((uint32_t)0x00100000U)
4931 #define GPIO_AFRL_AFSEL5_1 ((uint32_t)0x00200000U)
4932 #define GPIO_AFRL_AFSEL5_2 ((uint32_t)0x00400000U)
4933 #define GPIO_AFRL_AFSEL5_3 ((uint32_t)0x00800000U)
4934 #define GPIO_AFRL_AFSEL6 ((uint32_t)0x0F000000U)
4935 #define GPIO_AFRL_AFSEL6_0 ((uint32_t)0x01000000U)
4936 #define GPIO_AFRL_AFSEL6_1 ((uint32_t)0x02000000U)
4937 #define GPIO_AFRL_AFSEL6_2 ((uint32_t)0x04000000U)
4938 #define GPIO_AFRL_AFSEL6_3 ((uint32_t)0x08000000U)
4939 #define GPIO_AFRL_AFSEL7 ((uint32_t)0xF0000000U)
4940 #define GPIO_AFRL_AFSEL7_0 ((uint32_t)0x10000000U)
4941 #define GPIO_AFRL_AFSEL7_1 ((uint32_t)0x20000000U)
4942 #define GPIO_AFRL_AFSEL7_2 ((uint32_t)0x40000000U)
4943 #define GPIO_AFRL_AFSEL7_3 ((uint32_t)0x80000000U)
4944
4945 /* Legacy defines */
4946 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
4947 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
4948 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
4949 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
4950 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
4951 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
4952 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
4953 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
4954
4955 /****************** Bit definition for GPIO_AFRH register *********************/
4956 #define GPIO_AFRH_AFSEL8 ((uint32_t)0x0000000FU)
4957 #define GPIO_AFRH_AFSEL8_0 ((uint32_t)0x00000001U)
4958 #define GPIO_AFRH_AFSEL8_1 ((uint32_t)0x00000002U)
4959 #define GPIO_AFRH_AFSEL8_2 ((uint32_t)0x00000004U)
4960 #define GPIO_AFRH_AFSEL8_3 ((uint32_t)0x00000008U)
4961 #define GPIO_AFRH_AFSEL9 ((uint32_t)0x000000F0U)
4962 #define GPIO_AFRH_AFSEL9_0 ((uint32_t)0x00000010U)
4963 #define GPIO_AFRH_AFSEL9_1 ((uint32_t)0x00000020U)
4964 #define GPIO_AFRH_AFSEL9_2 ((uint32_t)0x00000040U)
4965 #define GPIO_AFRH_AFSEL9_3 ((uint32_t)0x00000080U)
4966 #define GPIO_AFRH_AFSEL10 ((uint32_t)0x00000F00U)
4967 #define GPIO_AFRH_AFSEL10_0 ((uint32_t)0x00000100U)
4968 #define GPIO_AFRH_AFSEL10_1 ((uint32_t)0x00000200U)
4969 #define GPIO_AFRH_AFSEL10_2 ((uint32_t)0x00000400U)
4970 #define GPIO_AFRH_AFSEL10_3 ((uint32_t)0x00000800U)
4971 #define GPIO_AFRH_AFSEL11 ((uint32_t)0x0000F000U)
4972 #define GPIO_AFRH_AFSEL11_0 ((uint32_t)0x00001000U)
4973 #define GPIO_AFRH_AFSEL11_1 ((uint32_t)0x00002000U)
4974 #define GPIO_AFRH_AFSEL11_2 ((uint32_t)0x00004000U)
4975 #define GPIO_AFRH_AFSEL11_3 ((uint32_t)0x00008000U)
4976 #define GPIO_AFRH_AFSEL12 ((uint32_t)0x000F0000U)
4977 #define GPIO_AFRH_AFSEL12_0 ((uint32_t)0x00010000U)
4978 #define GPIO_AFRH_AFSEL12_1 ((uint32_t)0x00020000U)
4979 #define GPIO_AFRH_AFSEL12_2 ((uint32_t)0x00040000U)
4980 #define GPIO_AFRH_AFSEL12_3 ((uint32_t)0x00080000U)
4981 #define GPIO_AFRH_AFSEL13 ((uint32_t)0x00F00000U)
4982 #define GPIO_AFRH_AFSEL13_0 ((uint32_t)0x00100000U)
4983 #define GPIO_AFRH_AFSEL13_1 ((uint32_t)0x00200000U)
4984 #define GPIO_AFRH_AFSEL13_2 ((uint32_t)0x00400000U)
4985 #define GPIO_AFRH_AFSEL13_3 ((uint32_t)0x00800000U)
4986 #define GPIO_AFRH_AFSEL14 ((uint32_t)0x0F000000U)
4987 #define GPIO_AFRH_AFSEL14_0 ((uint32_t)0x01000000U)
4988 #define GPIO_AFRH_AFSEL14_1 ((uint32_t)0x02000000U)
4989 #define GPIO_AFRH_AFSEL14_2 ((uint32_t)0x04000000U)
4990 #define GPIO_AFRH_AFSEL14_3 ((uint32_t)0x08000000U)
4991 #define GPIO_AFRH_AFSEL15 ((uint32_t)0xF0000000U)
4992 #define GPIO_AFRH_AFSEL15_0 ((uint32_t)0x10000000U)
4993 #define GPIO_AFRH_AFSEL15_1 ((uint32_t)0x20000000U)
4994 #define GPIO_AFRH_AFSEL15_2 ((uint32_t)0x40000000U)
4995 #define GPIO_AFRH_AFSEL15_3 ((uint32_t)0x80000000U)
4996
4997 /* Legacy defines */
4998 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
4999 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
5000 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
5001 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
5002 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
5003 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
5004 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
5005 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
5006
5007 /****************** Bits definition for GPIO_BRR register ******************/
5008 #define GPIO_BRR_BR0 ((uint32_t)0x00000001U)
5009 #define GPIO_BRR_BR1 ((uint32_t)0x00000002U)
5010 #define GPIO_BRR_BR2 ((uint32_t)0x00000004U)
5011 #define GPIO_BRR_BR3 ((uint32_t)0x00000008U)
5012 #define GPIO_BRR_BR4 ((uint32_t)0x00000010U)
5013 #define GPIO_BRR_BR5 ((uint32_t)0x00000020U)
5014 #define GPIO_BRR_BR6 ((uint32_t)0x00000040U)
5015 #define GPIO_BRR_BR7 ((uint32_t)0x00000080U)
5016 #define GPIO_BRR_BR8 ((uint32_t)0x00000100U)
5017 #define GPIO_BRR_BR9 ((uint32_t)0x00000200U)
5018 #define GPIO_BRR_BR10 ((uint32_t)0x00000400U)
5019 #define GPIO_BRR_BR11 ((uint32_t)0x00000800U)
5020 #define GPIO_BRR_BR12 ((uint32_t)0x00001000U)
5021 #define GPIO_BRR_BR13 ((uint32_t)0x00002000U)
5022 #define GPIO_BRR_BR14 ((uint32_t)0x00004000U)
5023 #define GPIO_BRR_BR15 ((uint32_t)0x00008000U)
5024
5025 /* Legacy defines */
5026 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
5027 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
5028 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
5029 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
5030 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
5031 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
5032 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
5033 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
5034 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
5035 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
5036 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
5037 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
5038 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
5039 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
5040 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
5041 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
5042
5043
5044 /****************** Bits definition for GPIO_ASCR register *******************/
5045 #define GPIO_ASCR_ASC0 ((uint32_t)0x00000001U)
5046 #define GPIO_ASCR_ASC1 ((uint32_t)0x00000002U)
5047 #define GPIO_ASCR_ASC2 ((uint32_t)0x00000004U)
5048 #define GPIO_ASCR_ASC3 ((uint32_t)0x00000008U)
5049 #define GPIO_ASCR_ASC4 ((uint32_t)0x00000010U)
5050 #define GPIO_ASCR_ASC5 ((uint32_t)0x00000020U)
5051 #define GPIO_ASCR_ASC6 ((uint32_t)0x00000040U)
5052 #define GPIO_ASCR_ASC7 ((uint32_t)0x00000080U)
5053 #define GPIO_ASCR_ASC8 ((uint32_t)0x00000100U)
5054 #define GPIO_ASCR_ASC9 ((uint32_t)0x00000200U)
5055 #define GPIO_ASCR_ASC10 ((uint32_t)0x00000400U)
5056 #define GPIO_ASCR_ASC11 ((uint32_t)0x00000800U)
5057 #define GPIO_ASCR_ASC12 ((uint32_t)0x00001000U)
5058 #define GPIO_ASCR_ASC13 ((uint32_t)0x00002000U)
5059 #define GPIO_ASCR_ASC14 ((uint32_t)0x00004000U)
5060 #define GPIO_ASCR_ASC15 ((uint32_t)0x00008000U)
5061
5062 /* Legacy defines */
5063 #define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
5064 #define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
5065 #define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
5066 #define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
5067 #define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
5068 #define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
5069 #define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
5070 #define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
5071 #define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
5072 #define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
5073 #define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
5074 #define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
5075 #define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
5076 #define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
5077 #define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
5078 #define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
5079
5080 /******************************************************************************/
5081 /* */
5082 /* Inter-integrated Circuit Interface (I2C) */
5083 /* */
5084 /******************************************************************************/
5085 /******************* Bit definition for I2C_CR1 register *******************/
5086 #define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */
5087 #define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */
5088 #define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */
5089 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */
5090 #define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */
5091 #define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */
5092 #define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */
5093 #define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */
5094 #define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */
5095 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */
5096 #define I2C_CR1_SWRST ((uint32_t)0x00002000U) /*!< Software reset */
5097 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */
5098 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */
5099 #define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */
5100 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */
5101 #define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */
5102 #define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */
5103 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */
5104 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */
5105 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */
5106 #define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */
5107
5108 /****************** Bit definition for I2C_CR2 register ********************/
5109 #define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */
5110 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */
5111 #define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */
5112 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */
5113 #define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */
5114 #define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */
5115 #define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */
5116 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */
5117 #define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */
5118 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */
5119 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */
5120
5121 /******************* Bit definition for I2C_OAR1 register ******************/
5122 #define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */
5123 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */
5124 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */
5125
5126 /******************* Bit definition for I2C_OAR2 register ******************/
5127 #define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */
5128 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */
5129 #define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */
5130 #define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
5131 #define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
5132 #define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
5133 #define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
5134 #define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
5135 #define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
5136 #define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */
5137 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */
5138
5139 /******************* Bit definition for I2C_TIMINGR register *******************/
5140 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */
5141 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */
5142 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */
5143 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */
5144 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */
5145
5146 /******************* Bit definition for I2C_TIMEOUTR register *******************/
5147 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */
5148 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */
5149 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */
5150 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B */
5151 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */
5152
5153 /****************** Bit definition for I2C_ISR register *********************/
5154 #define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */
5155 #define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */
5156 #define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */
5157 #define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode) */
5158 #define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */
5159 #define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */
5160 #define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */
5161 #define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */
5162 #define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */
5163 #define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */
5164 #define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */
5165 #define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */
5166 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */
5167 #define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */
5168 #define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */
5169 #define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */
5170 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */
5171
5172 /****************** Bit definition for I2C_ICR register *********************/
5173 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */
5174 #define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */
5175 #define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */
5176 #define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */
5177 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */
5178 #define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */
5179 #define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */
5180 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */
5181 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */
5182
5183 /****************** Bit definition for I2C_PECR register *********************/
5184 #define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */
5185
5186 /****************** Bit definition for I2C_RXDR register *********************/
5187 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */
5188
5189 /****************** Bit definition for I2C_TXDR register *********************/
5190 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */
5191
5192 /******************************************************************************/
5193 /* */
5194 /* Independent WATCHDOG */
5195 /* */
5196 /******************************************************************************/
5197 /******************* Bit definition for IWDG_KR register ********************/
5198 #define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!<Key value (write only, read 0000h) */
5199
5200 /******************* Bit definition for IWDG_PR register ********************/
5201 #define IWDG_PR_PR ((uint32_t)0x00000007U) /*!<PR[2:0] (Prescaler divider) */
5202 #define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
5203 #define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
5204 #define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
5205
5206 /******************* Bit definition for IWDG_RLR register *******************/
5207 #define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!<Watchdog counter reload value */
5208
5209 /******************* Bit definition for IWDG_SR register ********************/
5210 #define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
5211 #define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
5212 #define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */
5213
5214 /******************* Bit definition for IWDG_KR register ********************/
5215 #define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */
5216
5217 /******************************************************************************/
5218 /* */
5219 /* Firewall */
5220 /* */
5221 /******************************************************************************/
5222
5223 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */
5224 #define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */
5225 #define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */
5226 #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */
5227 #define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */
5228 #define FW_VDSSA_ADD ((uint32_t)0x0001FFC0U) /*!< Volatile Data Segment Start Address */
5229 #define FW_VDSL_LENG ((uint32_t)0x0001FFC0U) /*!< Volatile Data Segment Length */
5230 #define FW_LSSA_ADD ((uint32_t)0x0007FF80U) /*!< Library Segment Start Address*/
5231 #define FW_LSL_LENG ((uint32_t)0x0007FF80U) /*!< Library Segment Length*/
5232
5233 /**************************Bit definition for CR register *********************/
5234 #define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/
5235 #define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/
5236 #define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/
5237
5238 /******************************************************************************/
5239 /* */
5240 /* Power Control */
5241 /* */
5242 /******************************************************************************/
5243
5244 /******************** Bit definition for PWR_CR1 register ********************/
5245
5246 #define PWR_CR1_LPR ((uint32_t)0x00004000U) /*!< Regulator low-power mode */
5247 #define PWR_CR1_VOS ((uint32_t)0x00000600U) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
5248 #define PWR_CR1_VOS_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
5249 #define PWR_CR1_VOS_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
5250 #define PWR_CR1_DBP ((uint32_t)0x00000100U) /*!< Disable Back-up domain Protection */
5251 #define PWR_CR1_LPMS ((uint32_t)0x00000007U) /*!< Low-power mode selection field */
5252 #define PWR_CR1_LPMS_STOP0 ((uint32_t)0x00000000U) /*!< Stop 0 mode */
5253 #define PWR_CR1_LPMS_STOP1 ((uint32_t)0x00000001U) /*!< Stop 1 mode */
5254 #define PWR_CR1_LPMS_STOP2 ((uint32_t)0x00000002U) /*!< Stop 2 mode */
5255 #define PWR_CR1_LPMS_STANDBY ((uint32_t)0x00000003U) /*!< Stand-by mode */
5256 #define PWR_CR1_LPMS_SHUTDOWN ((uint32_t)0x00000004U) /*!< Shut-down mode */
5257
5258
5259 /******************** Bit definition for PWR_CR2 register ********************/
5260 #define PWR_CR2_IOSV ((uint32_t)0x00000200U) /*!< VDD IO2 independent I/Os Supply Valid */
5261 /*!< PVME Peripheral Voltage Monitor Enable */
5262 #define PWR_CR2_PVME ((uint32_t)0x000000E0U) /*!< PVM bits field */
5263 #define PWR_CR2_PVME4 ((uint32_t)0x00000080U) /*!< PVM 4 Enable */
5264 #define PWR_CR2_PVME3 ((uint32_t)0x00000040U) /*!< PVM 3 Enable */
5265 #define PWR_CR2_PVME2 ((uint32_t)0x00000020U) /*!< PVM 2 Enable */
5266 /*!< PVD level configuration */
5267 #define PWR_CR2_PLS ((uint32_t)0x0000000EU) /*!< PVD level selection */
5268 #define PWR_CR2_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
5269 #define PWR_CR2_PLS_LEV1 ((uint32_t)0x00000002U) /*!< PVD level 1 */
5270 #define PWR_CR2_PLS_LEV2 ((uint32_t)0x00000004U) /*!< PVD level 2 */
5271 #define PWR_CR2_PLS_LEV3 ((uint32_t)0x00000006U) /*!< PVD level 3 */
5272 #define PWR_CR2_PLS_LEV4 ((uint32_t)0x00000008U) /*!< PVD level 4 */
5273 #define PWR_CR2_PLS_LEV5 ((uint32_t)0x0000000AU) /*!< PVD level 5 */
5274 #define PWR_CR2_PLS_LEV6 ((uint32_t)0x0000000CU) /*!< PVD level 6 */
5275 #define PWR_CR2_PLS_LEV7 ((uint32_t)0x0000000EU) /*!< PVD level 7 */
5276 #define PWR_CR2_PVDE ((uint32_t)0x00000001U) /*!< Power Voltage Detector Enable */
5277
5278 /******************** Bit definition for PWR_CR3 register ********************/
5279 #define PWR_CR3_EIWF ((uint32_t)0x00008000U) /*!< Enable Internal Wake-up line */
5280 #define PWR_CR3_APC ((uint32_t)0x00000400U) /*!< Apply pull-up and pull-down configuration */
5281 #define PWR_CR3_RRS ((uint32_t)0x00000100U) /*!< SRAM2 Retention in Stand-by mode */
5282 #define PWR_CR3_EWUP5 ((uint32_t)0x00000010U) /*!< Enable Wake-Up Pin 5 */
5283 #define PWR_CR3_EWUP4 ((uint32_t)0x00000008U) /*!< Enable Wake-Up Pin 4 */
5284 #define PWR_CR3_EWUP3 ((uint32_t)0x00000004U) /*!< Enable Wake-Up Pin 3 */
5285 #define PWR_CR3_EWUP2 ((uint32_t)0x00000002U) /*!< Enable Wake-Up Pin 2 */
5286 #define PWR_CR3_EWUP1 ((uint32_t)0x00000001U) /*!< Enable Wake-Up Pin 1 */
5287 #define PWR_CR3_EWUP ((uint32_t)0x0000001FU) /*!< Enable Wake-Up Pins */
5288
5289 /******************** Bit definition for PWR_CR4 register ********************/
5290 #define PWR_CR4_VBRS ((uint32_t)0x00000200U) /*!< VBAT Battery charging Resistor Selection */
5291 #define PWR_CR4_VBE ((uint32_t)0x00000100U) /*!< VBAT Battery charging Enable */
5292 #define PWR_CR4_WP5 ((uint32_t)0x00000010U) /*!< Wake-Up Pin 5 polarity */
5293 #define PWR_CR4_WP4 ((uint32_t)0x00000008U) /*!< Wake-Up Pin 4 polarity */
5294 #define PWR_CR4_WP3 ((uint32_t)0x00000004U) /*!< Wake-Up Pin 3 polarity */
5295 #define PWR_CR4_WP2 ((uint32_t)0x00000002U) /*!< Wake-Up Pin 2 polarity */
5296 #define PWR_CR4_WP1 ((uint32_t)0x00000001U) /*!< Wake-Up Pin 1 polarity */
5297
5298 /******************** Bit definition for PWR_SR1 register ********************/
5299 #define PWR_SR1_WUFI ((uint32_t)0x00008000U) /*!< Wake-Up Flag Internal */
5300 #define PWR_SR1_SBF ((uint32_t)0x00000100U) /*!< Stand-By Flag */
5301 #define PWR_SR1_WUF ((uint32_t)0x0000001FU) /*!< Wake-up Flags */
5302 #define PWR_SR1_WUF5 ((uint32_t)0x00000010U) /*!< Wake-up Flag 5 */
5303 #define PWR_SR1_WUF4 ((uint32_t)0x00000008U) /*!< Wake-up Flag 4 */
5304 #define PWR_SR1_WUF3 ((uint32_t)0x00000004U) /*!< Wake-up Flag 3 */
5305 #define PWR_SR1_WUF2 ((uint32_t)0x00000002U) /*!< Wake-up Flag 2 */
5306 #define PWR_SR1_WUF1 ((uint32_t)0x00000001U) /*!< Wake-up Flag 1 */
5307
5308 /******************** Bit definition for PWR_SR2 register ********************/
5309 #define PWR_SR2_PVMO4 ((uint32_t)0x00008000U) /*!< Peripheral Voltage Monitoring Output 4 */
5310 #define PWR_SR2_PVMO3 ((uint32_t)0x00004000U) /*!< Peripheral Voltage Monitoring Output 3 */
5311 #define PWR_SR2_PVMO2 ((uint32_t)0x00002000U) /*!< Peripheral Voltage Monitoring Output 2 */
5312 #define PWR_SR2_PVDO ((uint32_t)0x00000800U) /*!< Power Voltage Detector Output */
5313 #define PWR_SR2_VOSF ((uint32_t)0x00000400U) /*!< Voltage Scaling Flag */
5314 #define PWR_SR2_REGLPF ((uint32_t)0x00000200U) /*!< Low-power Regulator Flag */
5315 #define PWR_SR2_REGLPS ((uint32_t)0x00000100U) /*!< Low-power Regulator Started */
5316
5317 /******************** Bit definition for PWR_SCR register ********************/
5318 #define PWR_SCR_CSBF ((uint32_t)0x00000100U) /*!< Clear Stand-By Flag */
5319 #define PWR_SCR_CWUF ((uint32_t)0x0000001FU) /*!< Clear Wake-up Flags */
5320 #define PWR_SCR_CWUF5 ((uint32_t)0x00000010U) /*!< Clear Wake-up Flag 5 */
5321 #define PWR_SCR_CWUF4 ((uint32_t)0x00000008U) /*!< Clear Wake-up Flag 4 */
5322 #define PWR_SCR_CWUF3 ((uint32_t)0x00000004U) /*!< Clear Wake-up Flag 3 */
5323 #define PWR_SCR_CWUF2 ((uint32_t)0x00000002U) /*!< Clear Wake-up Flag 2 */
5324 #define PWR_SCR_CWUF1 ((uint32_t)0x00000001U) /*!< Clear Wake-up Flag 1 */
5325
5326 /******************** Bit definition for PWR_PUCRA register ********************/
5327 #define PWR_PUCRA_PA15 ((uint32_t)0x00008000U) /*!< Port PA15 Pull-Up set */
5328 #define PWR_PUCRA_PA13 ((uint32_t)0x00002000U) /*!< Port PA13 Pull-Up set */
5329 #define PWR_PUCRA_PA12 ((uint32_t)0x00001000U) /*!< Port PA12 Pull-Up set */
5330 #define PWR_PUCRA_PA11 ((uint32_t)0x00000800U) /*!< Port PA11 Pull-Up set */
5331 #define PWR_PUCRA_PA10 ((uint32_t)0x00000400U) /*!< Port PA10 Pull-Up set */
5332 #define PWR_PUCRA_PA9 ((uint32_t)0x00000200U) /*!< Port PA9 Pull-Up set */
5333 #define PWR_PUCRA_PA8 ((uint32_t)0x00000100U) /*!< Port PA8 Pull-Up set */
5334 #define PWR_PUCRA_PA7 ((uint32_t)0x00000080U) /*!< Port PA7 Pull-Up set */
5335 #define PWR_PUCRA_PA6 ((uint32_t)0x00000040U) /*!< Port PA6 Pull-Up set */
5336 #define PWR_PUCRA_PA5 ((uint32_t)0x00000020U) /*!< Port PA5 Pull-Up set */
5337 #define PWR_PUCRA_PA4 ((uint32_t)0x00000010U) /*!< Port PA4 Pull-Up set */
5338 #define PWR_PUCRA_PA3 ((uint32_t)0x00000008U) /*!< Port PA3 Pull-Up set */
5339 #define PWR_PUCRA_PA2 ((uint32_t)0x00000004U) /*!< Port PA2 Pull-Up set */
5340 #define PWR_PUCRA_PA1 ((uint32_t)0x00000002U) /*!< Port PA1 Pull-Up set */
5341 #define PWR_PUCRA_PA0 ((uint32_t)0x00000001U) /*!< Port PA0 Pull-Up set */
5342
5343 /******************** Bit definition for PWR_PDCRA register ********************/
5344 #define PWR_PDCRA_PA14 ((uint32_t)0x00004000U) /*!< Port PA14 Pull-Down set */
5345 #define PWR_PDCRA_PA12 ((uint32_t)0x00001000U) /*!< Port PA12 Pull-Down set */
5346 #define PWR_PDCRA_PA11 ((uint32_t)0x00000800U) /*!< Port PA11 Pull-Down set */
5347 #define PWR_PDCRA_PA10 ((uint32_t)0x00000400U) /*!< Port PA10 Pull-Down set */
5348 #define PWR_PDCRA_PA9 ((uint32_t)0x00000200U) /*!< Port PA9 Pull-Down set */
5349 #define PWR_PDCRA_PA8 ((uint32_t)0x00000100U) /*!< Port PA8 Pull-Down set */
5350 #define PWR_PDCRA_PA7 ((uint32_t)0x00000080U) /*!< Port PA7 Pull-Down set */
5351 #define PWR_PDCRA_PA6 ((uint32_t)0x00000040U) /*!< Port PA6 Pull-Down set */
5352 #define PWR_PDCRA_PA5 ((uint32_t)0x00000020U) /*!< Port PA5 Pull-Down set */
5353 #define PWR_PDCRA_PA4 ((uint32_t)0x00000010U) /*!< Port PA4 Pull-Down set */
5354 #define PWR_PDCRA_PA3 ((uint32_t)0x00000008U) /*!< Port PA3 Pull-Down set */
5355 #define PWR_PDCRA_PA2 ((uint32_t)0x00000004U) /*!< Port PA2 Pull-Down set */
5356 #define PWR_PDCRA_PA1 ((uint32_t)0x00000002U) /*!< Port PA1 Pull-Down set */
5357 #define PWR_PDCRA_PA0 ((uint32_t)0x00000001U) /*!< Port PA0 Pull-Down set */
5358
5359 /******************** Bit definition for PWR_PUCRB register ********************/
5360 #define PWR_PUCRB_PB15 ((uint32_t)0x00008000U) /*!< Port PB15 Pull-Up set */
5361 #define PWR_PUCRB_PB14 ((uint32_t)0x00004000U) /*!< Port PB14 Pull-Up set */
5362 #define PWR_PUCRB_PB13 ((uint32_t)0x00002000U) /*!< Port PB13 Pull-Up set */
5363 #define PWR_PUCRB_PB12 ((uint32_t)0x00001000U) /*!< Port PB12 Pull-Up set */
5364 #define PWR_PUCRB_PB11 ((uint32_t)0x00000800U) /*!< Port PB11 Pull-Up set */
5365 #define PWR_PUCRB_PB10 ((uint32_t)0x00000400U) /*!< Port PB10 Pull-Up set */
5366 #define PWR_PUCRB_PB9 ((uint32_t)0x00000200U) /*!< Port PB9 Pull-Up set */
5367 #define PWR_PUCRB_PB8 ((uint32_t)0x00000100U) /*!< Port PB8 Pull-Up set */
5368 #define PWR_PUCRB_PB7 ((uint32_t)0x00000080U) /*!< Port PB7 Pull-Up set */
5369 #define PWR_PUCRB_PB6 ((uint32_t)0x00000040U) /*!< Port PB6 Pull-Up set */
5370 #define PWR_PUCRB_PB5 ((uint32_t)0x00000020U) /*!< Port PB5 Pull-Up set */
5371 #define PWR_PUCRB_PB4 ((uint32_t)0x00000010U) /*!< Port PB4 Pull-Up set */
5372 #define PWR_PUCRB_PB3 ((uint32_t)0x00000008U) /*!< Port PB3 Pull-Up set */
5373 #define PWR_PUCRB_PB2 ((uint32_t)0x00000004U) /*!< Port PB2 Pull-Up set */
5374 #define PWR_PUCRB_PB1 ((uint32_t)0x00000002U) /*!< Port PB1 Pull-Up set */
5375 #define PWR_PUCRB_PB0 ((uint32_t)0x00000001U) /*!< Port PB0 Pull-Up set */
5376
5377 /******************** Bit definition for PWR_PDCRB register ********************/
5378 #define PWR_PDCRB_PB15 ((uint32_t)0x00008000U) /*!< Port PB15 Pull-Down set */
5379 #define PWR_PDCRB_PB14 ((uint32_t)0x00004000U) /*!< Port PB14 Pull-Down set */
5380 #define PWR_PDCRB_PB13 ((uint32_t)0x00002000U) /*!< Port PB13 Pull-Down set */
5381 #define PWR_PDCRB_PB12 ((uint32_t)0x00001000U) /*!< Port PB12 Pull-Down set */
5382 #define PWR_PDCRB_PB11 ((uint32_t)0x00000800U) /*!< Port PB11 Pull-Down set */
5383 #define PWR_PDCRB_PB10 ((uint32_t)0x00000400U) /*!< Port PB10 Pull-Down set */
5384 #define PWR_PDCRB_PB9 ((uint32_t)0x00000200U) /*!< Port PB9 Pull-Down set */
5385 #define PWR_PDCRB_PB8 ((uint32_t)0x00000100U) /*!< Port PB8 Pull-Down set */
5386 #define PWR_PDCRB_PB7 ((uint32_t)0x00000080U) /*!< Port PB7 Pull-Down set */
5387 #define PWR_PDCRB_PB6 ((uint32_t)0x00000040U) /*!< Port PB6 Pull-Down set */
5388 #define PWR_PDCRB_PB5 ((uint32_t)0x00000020U) /*!< Port PB5 Pull-Down set */
5389 #define PWR_PDCRB_PB3 ((uint32_t)0x00000008U) /*!< Port PB3 Pull-Down set */
5390 #define PWR_PDCRB_PB2 ((uint32_t)0x00000004U) /*!< Port PB2 Pull-Down set */
5391 #define PWR_PDCRB_PB1 ((uint32_t)0x00000002U) /*!< Port PB1 Pull-Down set */
5392 #define PWR_PDCRB_PB0 ((uint32_t)0x00000001U) /*!< Port PB0 Pull-Down set */
5393
5394 /******************** Bit definition for PWR_PUCRC register ********************/
5395 #define PWR_PUCRC_PC15 ((uint32_t)0x00008000U) /*!< Port PC15 Pull-Up set */
5396 #define PWR_PUCRC_PC14 ((uint32_t)0x00004000U) /*!< Port PC14 Pull-Up set */
5397 #define PWR_PUCRC_PC13 ((uint32_t)0x00002000U) /*!< Port PC13 Pull-Up set */
5398 #define PWR_PUCRC_PC12 ((uint32_t)0x00001000U) /*!< Port PC12 Pull-Up set */
5399 #define PWR_PUCRC_PC11 ((uint32_t)0x00000800U) /*!< Port PC11 Pull-Up set */
5400 #define PWR_PUCRC_PC10 ((uint32_t)0x00000400U) /*!< Port PC10 Pull-Up set */
5401 #define PWR_PUCRC_PC9 ((uint32_t)0x00000200U) /*!< Port PC9 Pull-Up set */
5402 #define PWR_PUCRC_PC8 ((uint32_t)0x00000100U) /*!< Port PC8 Pull-Up set */
5403 #define PWR_PUCRC_PC7 ((uint32_t)0x00000080U) /*!< Port PC7 Pull-Up set */
5404 #define PWR_PUCRC_PC6 ((uint32_t)0x00000040U) /*!< Port PC6 Pull-Up set */
5405 #define PWR_PUCRC_PC5 ((uint32_t)0x00000020U) /*!< Port PC5 Pull-Up set */
5406 #define PWR_PUCRC_PC4 ((uint32_t)0x00000010U) /*!< Port PC4 Pull-Up set */
5407 #define PWR_PUCRC_PC3 ((uint32_t)0x00000008U) /*!< Port PC3 Pull-Up set */
5408 #define PWR_PUCRC_PC2 ((uint32_t)0x00000004U) /*!< Port PC2 Pull-Up set */
5409 #define PWR_PUCRC_PC1 ((uint32_t)0x00000002U) /*!< Port PC1 Pull-Up set */
5410 #define PWR_PUCRC_PC0 ((uint32_t)0x00000001U) /*!< Port PC0 Pull-Up set */
5411
5412 /******************** Bit definition for PWR_PDCRC register ********************/
5413 #define PWR_PDCRC_PC15 ((uint32_t)0x00008000U) /*!< Port PC15 Pull-Down set */
5414 #define PWR_PDCRC_PC14 ((uint32_t)0x00004000U) /*!< Port PC14 Pull-Down set */
5415 #define PWR_PDCRC_PC13 ((uint32_t)0x00002000U) /*!< Port PC13 Pull-Down set */
5416 #define PWR_PDCRC_PC12 ((uint32_t)0x00001000U) /*!< Port PC12 Pull-Down set */
5417 #define PWR_PDCRC_PC11 ((uint32_t)0x00000800U) /*!< Port PC11 Pull-Down set */
5418 #define PWR_PDCRC_PC10 ((uint32_t)0x00000400U) /*!< Port PC10 Pull-Down set */
5419 #define PWR_PDCRC_PC9 ((uint32_t)0x00000200U) /*!< Port PC9 Pull-Down set */
5420 #define PWR_PDCRC_PC8 ((uint32_t)0x00000100U) /*!< Port PC8 Pull-Down set */
5421 #define PWR_PDCRC_PC7 ((uint32_t)0x00000080U) /*!< Port PC7 Pull-Down set */
5422 #define PWR_PDCRC_PC6 ((uint32_t)0x00000040U) /*!< Port PC6 Pull-Down set */
5423 #define PWR_PDCRC_PC5 ((uint32_t)0x00000020U) /*!< Port PC5 Pull-Down set */
5424 #define PWR_PDCRC_PC4 ((uint32_t)0x00000010U) /*!< Port PC4 Pull-Down set */
5425 #define PWR_PDCRC_PC3 ((uint32_t)0x00000008U) /*!< Port PC3 Pull-Down set */
5426 #define PWR_PDCRC_PC2 ((uint32_t)0x00000004U) /*!< Port PC2 Pull-Down set */
5427 #define PWR_PDCRC_PC1 ((uint32_t)0x00000002U) /*!< Port PC1 Pull-Down set */
5428 #define PWR_PDCRC_PC0 ((uint32_t)0x00000001U) /*!< Port PC0 Pull-Down set */
5429
5430 /******************** Bit definition for PWR_PUCRD register ********************/
5431 #define PWR_PUCRD_PD15 ((uint32_t)0x00008000U) /*!< Port PD15 Pull-Up set */
5432 #define PWR_PUCRD_PD14 ((uint32_t)0x00004000U) /*!< Port PD14 Pull-Up set */
5433 #define PWR_PUCRD_PD13 ((uint32_t)0x00002000U) /*!< Port PD13 Pull-Up set */
5434 #define PWR_PUCRD_PD12 ((uint32_t)0x00001000U) /*!< Port PD12 Pull-Up set */
5435 #define PWR_PUCRD_PD11 ((uint32_t)0x00000800U) /*!< Port PD11 Pull-Up set */
5436 #define PWR_PUCRD_PD10 ((uint32_t)0x00000400U) /*!< Port PD10 Pull-Up set */
5437 #define PWR_PUCRD_PD9 ((uint32_t)0x00000200U) /*!< Port PD9 Pull-Up set */
5438 #define PWR_PUCRD_PD8 ((uint32_t)0x00000100U) /*!< Port PD8 Pull-Up set */
5439 #define PWR_PUCRD_PD7 ((uint32_t)0x00000080U) /*!< Port PD7 Pull-Up set */
5440 #define PWR_PUCRD_PD6 ((uint32_t)0x00000040U) /*!< Port PD6 Pull-Up set */
5441 #define PWR_PUCRD_PD5 ((uint32_t)0x00000020U) /*!< Port PD5 Pull-Up set */
5442 #define PWR_PUCRD_PD4 ((uint32_t)0x00000010U) /*!< Port PD4 Pull-Up set */
5443 #define PWR_PUCRD_PD3 ((uint32_t)0x00000008U) /*!< Port PD3 Pull-Up set */
5444 #define PWR_PUCRD_PD2 ((uint32_t)0x00000004U) /*!< Port PD2 Pull-Up set */
5445 #define PWR_PUCRD_PD1 ((uint32_t)0x00000002U) /*!< Port PD1 Pull-Up set */
5446 #define PWR_PUCRD_PD0 ((uint32_t)0x00000001U) /*!< Port PD0 Pull-Up set */
5447
5448 /******************** Bit definition for PWR_PDCRD register ********************/
5449 #define PWR_PDCRD_PD15 ((uint32_t)0x00008000U) /*!< Port PD15 Pull-Down set */
5450 #define PWR_PDCRD_PD14 ((uint32_t)0x00004000U) /*!< Port PD14 Pull-Down set */
5451 #define PWR_PDCRD_PD13 ((uint32_t)0x00002000U) /*!< Port PD13 Pull-Down set */
5452 #define PWR_PDCRD_PD12 ((uint32_t)0x00001000U) /*!< Port PD12 Pull-Down set */
5453 #define PWR_PDCRD_PD11 ((uint32_t)0x00000800U) /*!< Port PD11 Pull-Down set */
5454 #define PWR_PDCRD_PD10 ((uint32_t)0x00000400U) /*!< Port PD10 Pull-Down set */
5455 #define PWR_PDCRD_PD9 ((uint32_t)0x00000200U) /*!< Port PD9 Pull-Down set */
5456 #define PWR_PDCRD_PD8 ((uint32_t)0x00000100U) /*!< Port PD8 Pull-Down set */
5457 #define PWR_PDCRD_PD7 ((uint32_t)0x00000080U) /*!< Port PD7 Pull-Down set */
5458 #define PWR_PDCRD_PD6 ((uint32_t)0x00000040U) /*!< Port PD6 Pull-Down set */
5459 #define PWR_PDCRD_PD5 ((uint32_t)0x00000020U) /*!< Port PD5 Pull-Down set */
5460 #define PWR_PDCRD_PD4 ((uint32_t)0x00000010U) /*!< Port PD4 Pull-Down set */
5461 #define PWR_PDCRD_PD3 ((uint32_t)0x00000008U) /*!< Port PD3 Pull-Down set */
5462 #define PWR_PDCRD_PD2 ((uint32_t)0x00000004U) /*!< Port PD2 Pull-Down set */
5463 #define PWR_PDCRD_PD1 ((uint32_t)0x00000002U) /*!< Port PD1 Pull-Down set */
5464 #define PWR_PDCRD_PD0 ((uint32_t)0x00000001U) /*!< Port PD0 Pull-Down set */
5465
5466 /******************** Bit definition for PWR_PUCRE register ********************/
5467 #define PWR_PUCRE_PE15 ((uint32_t)0x00008000U) /*!< Port PE15 Pull-Up set */
5468 #define PWR_PUCRE_PE14 ((uint32_t)0x00004000U) /*!< Port PE14 Pull-Up set */
5469 #define PWR_PUCRE_PE13 ((uint32_t)0x00002000U) /*!< Port PE13 Pull-Up set */
5470 #define PWR_PUCRE_PE12 ((uint32_t)0x00001000U) /*!< Port PE12 Pull-Up set */
5471 #define PWR_PUCRE_PE11 ((uint32_t)0x00000800U) /*!< Port PE11 Pull-Up set */
5472 #define PWR_PUCRE_PE10 ((uint32_t)0x00000400U) /*!< Port PE10 Pull-Up set */
5473 #define PWR_PUCRE_PE9 ((uint32_t)0x00000200U) /*!< Port PE9 Pull-Up set */
5474 #define PWR_PUCRE_PE8 ((uint32_t)0x00000100U) /*!< Port PE8 Pull-Up set */
5475 #define PWR_PUCRE_PE7 ((uint32_t)0x00000080U) /*!< Port PE7 Pull-Up set */
5476 #define PWR_PUCRE_PE6 ((uint32_t)0x00000040U) /*!< Port PE6 Pull-Up set */
5477 #define PWR_PUCRE_PE5 ((uint32_t)0x00000020U) /*!< Port PE5 Pull-Up set */
5478 #define PWR_PUCRE_PE4 ((uint32_t)0x00000010U) /*!< Port PE4 Pull-Up set */
5479 #define PWR_PUCRE_PE3 ((uint32_t)0x00000008U) /*!< Port PE3 Pull-Up set */
5480 #define PWR_PUCRE_PE2 ((uint32_t)0x00000004U) /*!< Port PE2 Pull-Up set */
5481 #define PWR_PUCRE_PE1 ((uint32_t)0x00000002U) /*!< Port PE1 Pull-Up set */
5482 #define PWR_PUCRE_PE0 ((uint32_t)0x00000001U) /*!< Port PE0 Pull-Up set */
5483
5484 /******************** Bit definition for PWR_PDCRE register ********************/
5485 #define PWR_PDCRE_PE15 ((uint32_t)0x00008000U) /*!< Port PE15 Pull-Down set */
5486 #define PWR_PDCRE_PE14 ((uint32_t)0x00004000U) /*!< Port PE14 Pull-Down set */
5487 #define PWR_PDCRE_PE13 ((uint32_t)0x00002000U) /*!< Port PE13 Pull-Down set */
5488 #define PWR_PDCRE_PE12 ((uint32_t)0x00001000U) /*!< Port PE12 Pull-Down set */
5489 #define PWR_PDCRE_PE11 ((uint32_t)0x00000800U) /*!< Port PE11 Pull-Down set */
5490 #define PWR_PDCRE_PE10 ((uint32_t)0x00000400U) /*!< Port PE10 Pull-Down set */
5491 #define PWR_PDCRE_PE9 ((uint32_t)0x00000200U) /*!< Port PE9 Pull-Down set */
5492 #define PWR_PDCRE_PE8 ((uint32_t)0x00000100U) /*!< Port PE8 Pull-Down set */
5493 #define PWR_PDCRE_PE7 ((uint32_t)0x00000080U) /*!< Port PE7 Pull-Down set */
5494 #define PWR_PDCRE_PE6 ((uint32_t)0x00000040U) /*!< Port PE6 Pull-Down set */
5495 #define PWR_PDCRE_PE5 ((uint32_t)0x00000020U) /*!< Port PE5 Pull-Down set */
5496 #define PWR_PDCRE_PE4 ((uint32_t)0x00000010U) /*!< Port PE4 Pull-Down set */
5497 #define PWR_PDCRE_PE3 ((uint32_t)0x00000008U) /*!< Port PE3 Pull-Down set */
5498 #define PWR_PDCRE_PE2 ((uint32_t)0x00000004U) /*!< Port PE2 Pull-Down set */
5499 #define PWR_PDCRE_PE1 ((uint32_t)0x00000002U) /*!< Port PE1 Pull-Down set */
5500 #define PWR_PDCRE_PE0 ((uint32_t)0x00000001U) /*!< Port PE0 Pull-Down set */
5501
5502 /******************** Bit definition for PWR_PUCRF register ********************/
5503 #define PWR_PUCRF_PF15 ((uint32_t)0x00008000U) /*!< Port PF15 Pull-Up set */
5504 #define PWR_PUCRF_PF14 ((uint32_t)0x00004000U) /*!< Port PF14 Pull-Up set */
5505 #define PWR_PUCRF_PF13 ((uint32_t)0x00002000U) /*!< Port PF13 Pull-Up set */
5506 #define PWR_PUCRF_PF12 ((uint32_t)0x00001000U) /*!< Port PF12 Pull-Up set */
5507 #define PWR_PUCRF_PF11 ((uint32_t)0x00000800U) /*!< Port PF11 Pull-Up set */
5508 #define PWR_PUCRF_PF10 ((uint32_t)0x00000400U) /*!< Port PF10 Pull-Up set */
5509 #define PWR_PUCRF_PF9 ((uint32_t)0x00000200U) /*!< Port PF9 Pull-Up set */
5510 #define PWR_PUCRF_PF8 ((uint32_t)0x00000100U) /*!< Port PF8 Pull-Up set */
5511 #define PWR_PUCRF_PF7 ((uint32_t)0x00000080U) /*!< Port PF7 Pull-Up set */
5512 #define PWR_PUCRF_PF6 ((uint32_t)0x00000040U) /*!< Port PF6 Pull-Up set */
5513 #define PWR_PUCRF_PF5 ((uint32_t)0x00000020U) /*!< Port PF5 Pull-Up set */
5514 #define PWR_PUCRF_PF4 ((uint32_t)0x00000010U) /*!< Port PF4 Pull-Up set */
5515 #define PWR_PUCRF_PF3 ((uint32_t)0x00000008U) /*!< Port PF3 Pull-Up set */
5516 #define PWR_PUCRF_PF2 ((uint32_t)0x00000004U) /*!< Port PF2 Pull-Up set */
5517 #define PWR_PUCRF_PF1 ((uint32_t)0x00000002U) /*!< Port PF1 Pull-Up set */
5518 #define PWR_PUCRF_PF0 ((uint32_t)0x00000001U) /*!< Port PF0 Pull-Up set */
5519
5520 /******************** Bit definition for PWR_PDCRF register ********************/
5521 #define PWR_PDCRF_PF15 ((uint32_t)0x00008000U) /*!< Port PF15 Pull-Down set */
5522 #define PWR_PDCRF_PF14 ((uint32_t)0x00004000U) /*!< Port PF14 Pull-Down set */
5523 #define PWR_PDCRF_PF13 ((uint32_t)0x00002000U) /*!< Port PF13 Pull-Down set */
5524 #define PWR_PDCRF_PF12 ((uint32_t)0x00001000U) /*!< Port PF12 Pull-Down set */
5525 #define PWR_PDCRF_PF11 ((uint32_t)0x00000800U) /*!< Port PF11 Pull-Down set */
5526 #define PWR_PDCRF_PF10 ((uint32_t)0x00000400U) /*!< Port PF10 Pull-Down set */
5527 #define PWR_PDCRF_PF9 ((uint32_t)0x00000200U) /*!< Port PF9 Pull-Down set */
5528 #define PWR_PDCRF_PF8 ((uint32_t)0x00000100U) /*!< Port PF8 Pull-Down set */
5529 #define PWR_PDCRF_PF7 ((uint32_t)0x00000080U) /*!< Port PF7 Pull-Down set */
5530 #define PWR_PDCRF_PF6 ((uint32_t)0x00000040U) /*!< Port PF6 Pull-Down set */
5531 #define PWR_PDCRF_PF5 ((uint32_t)0x00000020U) /*!< Port PF5 Pull-Down set */
5532 #define PWR_PDCRF_PF4 ((uint32_t)0x00000010U) /*!< Port PF4 Pull-Down set */
5533 #define PWR_PDCRF_PF3 ((uint32_t)0x00000008U) /*!< Port PF3 Pull-Down set */
5534 #define PWR_PDCRF_PF2 ((uint32_t)0x00000004U) /*!< Port PF2 Pull-Down set */
5535 #define PWR_PDCRF_PF1 ((uint32_t)0x00000002U) /*!< Port PF1 Pull-Down set */
5536 #define PWR_PDCRF_PF0 ((uint32_t)0x00000001U) /*!< Port PF0 Pull-Down set */
5537
5538 /******************** Bit definition for PWR_PUCRG register ********************/
5539 #define PWR_PUCRG_PG15 ((uint32_t)0x00008000U) /*!< Port PG15 Pull-Up set */
5540 #define PWR_PUCRG_PG14 ((uint32_t)0x00004000U) /*!< Port PG14 Pull-Up set */
5541 #define PWR_PUCRG_PG13 ((uint32_t)0x00002000U) /*!< Port PG13 Pull-Up set */
5542 #define PWR_PUCRG_PG12 ((uint32_t)0x00001000U) /*!< Port PG12 Pull-Up set */
5543 #define PWR_PUCRG_PG11 ((uint32_t)0x00000800U) /*!< Port PG11 Pull-Up set */
5544 #define PWR_PUCRG_PG10 ((uint32_t)0x00000400U) /*!< Port PG10 Pull-Up set */
5545 #define PWR_PUCRG_PG9 ((uint32_t)0x00000200U) /*!< Port PG9 Pull-Up set */
5546 #define PWR_PUCRG_PG8 ((uint32_t)0x00000100U) /*!< Port PG8 Pull-Up set */
5547 #define PWR_PUCRG_PG7 ((uint32_t)0x00000080U) /*!< Port PG7 Pull-Up set */
5548 #define PWR_PUCRG_PG6 ((uint32_t)0x00000040U) /*!< Port PG6 Pull-Up set */
5549 #define PWR_PUCRG_PG5 ((uint32_t)0x00000020U) /*!< Port PG5 Pull-Up set */
5550 #define PWR_PUCRG_PG4 ((uint32_t)0x00000010U) /*!< Port PG4 Pull-Up set */
5551 #define PWR_PUCRG_PG3 ((uint32_t)0x00000008U) /*!< Port PG3 Pull-Up set */
5552 #define PWR_PUCRG_PG2 ((uint32_t)0x00000004U) /*!< Port PG2 Pull-Up set */
5553 #define PWR_PUCRG_PG1 ((uint32_t)0x00000002U) /*!< Port PG1 Pull-Up set */
5554 #define PWR_PUCRG_PG0 ((uint32_t)0x00000001U) /*!< Port PG0 Pull-Up set */
5555
5556 /******************** Bit definition for PWR_PDCRG register ********************/
5557 #define PWR_PDCRG_PG15 ((uint32_t)0x00008000U) /*!< Port PG15 Pull-Down set */
5558 #define PWR_PDCRG_PG14 ((uint32_t)0x00004000U) /*!< Port PG14 Pull-Down set */
5559 #define PWR_PDCRG_PG13 ((uint32_t)0x00002000U) /*!< Port PG13 Pull-Down set */
5560 #define PWR_PDCRG_PG12 ((uint32_t)0x00001000U) /*!< Port PG12 Pull-Down set */
5561 #define PWR_PDCRG_PG11 ((uint32_t)0x00000800U) /*!< Port PG11 Pull-Down set */
5562 #define PWR_PDCRG_PG10 ((uint32_t)0x00000400U) /*!< Port PG10 Pull-Down set */
5563 #define PWR_PDCRG_PG9 ((uint32_t)0x00000200U) /*!< Port PG9 Pull-Down set */
5564 #define PWR_PDCRG_PG8 ((uint32_t)0x00000100U) /*!< Port PG8 Pull-Down set */
5565 #define PWR_PDCRG_PG7 ((uint32_t)0x00000080U) /*!< Port PG7 Pull-Down set */
5566 #define PWR_PDCRG_PG6 ((uint32_t)0x00000040U) /*!< Port PG6 Pull-Down set */
5567 #define PWR_PDCRG_PG5 ((uint32_t)0x00000020U) /*!< Port PG5 Pull-Down set */
5568 #define PWR_PDCRG_PG4 ((uint32_t)0x00000010U) /*!< Port PG4 Pull-Down set */
5569 #define PWR_PDCRG_PG3 ((uint32_t)0x00000008U) /*!< Port PG3 Pull-Down set */
5570 #define PWR_PDCRG_PG2 ((uint32_t)0x00000004U) /*!< Port PG2 Pull-Down set */
5571 #define PWR_PDCRG_PG1 ((uint32_t)0x00000002U) /*!< Port PG1 Pull-Down set */
5572 #define PWR_PDCRG_PG0 ((uint32_t)0x00000001U) /*!< Port PG0 Pull-Down set */
5573
5574 /******************** Bit definition for PWR_PUCRH register ********************/
5575 #define PWR_PUCRH_PH1 ((uint32_t)0x00000002U) /*!< Port PH1 Pull-Up set */
5576 #define PWR_PUCRH_PH0 ((uint32_t)0x00000001U) /*!< Port PH0 Pull-Up set */
5577
5578 /******************** Bit definition for PWR_PDCRH register ********************/
5579 #define PWR_PDCRH_PH1 ((uint32_t)0x00000002U) /*!< Port PH1 Pull-Down set */
5580 #define PWR_PDCRH_PH0 ((uint32_t)0x00000001U) /*!< Port PH0 Pull-Down set */
5581
5582
5583 /******************************************************************************/
5584 /* */
5585 /* Reset and Clock Control */
5586 /* */
5587 /******************************************************************************/
5588 /*
5589 * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
5590 */
5591 #define RCC_PLLSAI2_SUPPORT
5592
5593 /******************** Bit definition for RCC_CR register ********************/
5594 #define RCC_CR_MSION ((uint32_t)0x00000001U) /*!< Internal Multi Speed oscillator (MSI) clock enable */
5595 #define RCC_CR_MSIRDY ((uint32_t)0x00000002U) /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
5596 #define RCC_CR_MSIPLLEN ((uint32_t)0x00000004U) /*!< Internal Multi Speed oscillator (MSI) PLL enable */
5597 #define RCC_CR_MSIRGSEL ((uint32_t)0x00000008U) /*!< Internal Multi Speed oscillator (MSI) range selection */
5598
5599 /*!< MSIRANGE configuration : 12 frequency ranges available */
5600 #define RCC_CR_MSIRANGE ((uint32_t)0x000000F0U) /*!< Internal Multi Speed oscillator (MSI) clock Range */
5601 #define RCC_CR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed oscillator (MSI) clock Range 100 KHz */
5602 #define RCC_CR_MSIRANGE_1 ((uint32_t)0x00000010U) /*!< Internal Multi Speed oscillator (MSI) clock Range 200 KHz */
5603 #define RCC_CR_MSIRANGE_2 ((uint32_t)0x00000020U) /*!< Internal Multi Speed oscillator (MSI) clock Range 400 KHz */
5604 #define RCC_CR_MSIRANGE_3 ((uint32_t)0x00000030U) /*!< Internal Multi Speed oscillator (MSI) clock Range 800 KHz */
5605 #define RCC_CR_MSIRANGE_4 ((uint32_t)0x00000040U) /*!< Internal Multi Speed oscillator (MSI) clock Range 1 MHz */
5606 #define RCC_CR_MSIRANGE_5 ((uint32_t)0x00000050U) /*!< Internal Multi Speed oscillator (MSI) clock Range 2 MHz */
5607 #define RCC_CR_MSIRANGE_6 ((uint32_t)0x00000060U) /*!< Internal Multi Speed oscillator (MSI) clock Range 4 MHz */
5608 #define RCC_CR_MSIRANGE_7 ((uint32_t)0x00000070U) /*!< Internal Multi Speed oscillator (MSI) clock Range 8 KHz */
5609 #define RCC_CR_MSIRANGE_8 ((uint32_t)0x00000080U) /*!< Internal Multi Speed oscillator (MSI) clock Range 16 MHz */
5610 #define RCC_CR_MSIRANGE_9 ((uint32_t)0x00000090U) /*!< Internal Multi Speed oscillator (MSI) clock Range 24 MHz */
5611 #define RCC_CR_MSIRANGE_10 ((uint32_t)0x000000A0U) /*!< Internal Multi Speed oscillator (MSI) clock Range 32 MHz */
5612 #define RCC_CR_MSIRANGE_11 ((uint32_t)0x000000B0U) /*!< Internal Multi Speed oscillator (MSI) clock Range 48 MHz */
5613
5614 #define RCC_CR_HSION ((uint32_t)0x00000100U) /*!< Internal High Speed oscillator (HSI16) clock enable */
5615 #define RCC_CR_HSIKERON ((uint32_t)0x00000200U) /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
5616 #define RCC_CR_HSIRDY ((uint32_t)0x00000400U) /*!< Internal High Speed oscillator (HSI16) clock ready flag */
5617 #define RCC_CR_HSIASFS ((uint32_t)0x00000800U) /*!< HSI16 Automatic Start from Stop */
5618
5619 #define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed oscillator (HSE) clock enable */
5620 #define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed oscillator (HSE) clock ready */
5621 #define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed oscillator (HSE) clock bypass */
5622 #define RCC_CR_CSSON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */
5623
5624 #define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< System PLL clock enable */
5625 #define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< System PLL clock ready */
5626 #define RCC_CR_PLLSAI1ON ((uint32_t)0x04000000U) /*!< SAI1 PLL enable */
5627 #define RCC_CR_PLLSAI1RDY ((uint32_t)0x08000000U) /*!< SAI1 PLL ready */
5628 #define RCC_CR_PLLSAI2ON ((uint32_t)0x10000000U) /*!< SAI2 PLL enable */
5629 #define RCC_CR_PLLSAI2RDY ((uint32_t)0x20000000U) /*!< SAI2 PLL ready */
5630
5631 /******************** Bit definition for RCC_ICSCR register ***************/
5632 /*!< MSICAL configuration */
5633 #define RCC_ICSCR_MSICAL ((uint32_t)0x000000FFU) /*!< MSICAL[7:0] bits */
5634 #define RCC_ICSCR_MSICAL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
5635 #define RCC_ICSCR_MSICAL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
5636 #define RCC_ICSCR_MSICAL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
5637 #define RCC_ICSCR_MSICAL_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
5638 #define RCC_ICSCR_MSICAL_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
5639 #define RCC_ICSCR_MSICAL_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
5640 #define RCC_ICSCR_MSICAL_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
5641 #define RCC_ICSCR_MSICAL_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
5642
5643 /*!< MSITRIM configuration */
5644 #define RCC_ICSCR_MSITRIM ((uint32_t)0x0000FF00U) /*!< MSITRIM[7:0] bits */
5645 #define RCC_ICSCR_MSITRIM_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
5646 #define RCC_ICSCR_MSITRIM_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
5647 #define RCC_ICSCR_MSITRIM_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
5648 #define RCC_ICSCR_MSITRIM_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
5649 #define RCC_ICSCR_MSITRIM_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
5650 #define RCC_ICSCR_MSITRIM_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
5651 #define RCC_ICSCR_MSITRIM_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
5652 #define RCC_ICSCR_MSITRIM_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
5653
5654 /*!< HSICAL configuration */
5655 #define RCC_ICSCR_HSICAL ((uint32_t)0x00FF0000U) /*!< HSICAL[7:0] bits */
5656 #define RCC_ICSCR_HSICAL_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
5657 #define RCC_ICSCR_HSICAL_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
5658 #define RCC_ICSCR_HSICAL_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
5659 #define RCC_ICSCR_HSICAL_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
5660 #define RCC_ICSCR_HSICAL_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
5661 #define RCC_ICSCR_HSICAL_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
5662 #define RCC_ICSCR_HSICAL_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
5663 #define RCC_ICSCR_HSICAL_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
5664
5665 /*!< HSITRIM configuration */
5666 #define RCC_ICSCR_HSITRIM ((uint32_t)0x1F000000U) /*!< HSITRIM[4:0] bits */
5667 #define RCC_ICSCR_HSITRIM_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
5668 #define RCC_ICSCR_HSITRIM_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
5669 #define RCC_ICSCR_HSITRIM_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
5670 #define RCC_ICSCR_HSITRIM_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
5671 #define RCC_ICSCR_HSITRIM_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
5672
5673 /******************** Bit definition for RCC_CFGR register ******************/
5674 /*!< SW configuration */
5675 #define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
5676 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
5677 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
5678
5679 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator selection as system clock */
5680 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI16 oscillator selection as system clock */
5681 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE oscillator selection as system clock */
5682 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selection as system clock */
5683
5684 /*!< SWS configuration */
5685 #define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
5686 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
5687 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
5688
5689 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
5690 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI16 oscillator used as system clock */
5691 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
5692 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
5693
5694 /*!< HPRE configuration */
5695 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
5696 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
5697 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
5698 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
5699 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
5700
5701 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
5702 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
5703 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
5704 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
5705 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
5706 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
5707 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
5708 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
5709 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
5710
5711 /*!< PPRE1 configuration */
5712 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB2 prescaler) */
5713 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
5714 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
5715 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
5716
5717 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
5718 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
5719 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
5720 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
5721 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
5722
5723 /*!< PPRE2 configuration */
5724 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
5725 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!<Bit 0 */
5726 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!<Bit 1 */
5727 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!<Bit 2 */
5728
5729 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
5730 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
5731 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
5732 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
5733 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
5734
5735 #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from stop and CSS backup clock selection */
5736
5737 /*!< MCOSEL configuration */
5738 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000U) /*!< MCOSEL [2:0] bits (Clock output selection) */
5739 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
5740 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
5741 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
5742
5743 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */
5744 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
5745 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
5746 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
5747
5748 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
5749 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
5750 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
5751 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
5752 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
5753
5754 /* Legacy aliases */
5755 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
5756 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
5757 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
5758 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
5759 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
5760 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
5761
5762 /******************** Bit definition for RCC_PLLCFGR register ***************/
5763 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00000003U)
5764
5765 #define RCC_PLLCFGR_PLLSRC_MSI ((uint32_t)0x00000001U) /*!< MSI oscillator source clock selected */
5766 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000002U) /*!< HSI16 oscillator source clock selected */
5767 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00000003U) /*!< HSE oscillator source clock selected */
5768
5769 #define RCC_PLLCFGR_PLLM ((uint32_t)0x00000070U)
5770 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000010U)
5771 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000020U)
5772 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000040U)
5773
5774 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007F00U)
5775 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000100U)
5776 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000200U)
5777 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000400U)
5778 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000800U)
5779 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00001000U)
5780 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00002000U)
5781 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00004000U)
5782
5783 #define RCC_PLLCFGR_PLLPEN ((uint32_t)0x00010000U)
5784 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00020000U)
5785 #define RCC_PLLCFGR_PLLQEN ((uint32_t)0x00100000U)
5786
5787 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x00600000U)
5788 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x00200000U)
5789 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x00400000U)
5790
5791 #define RCC_PLLCFGR_PLLREN ((uint32_t)0x01000000U)
5792 #define RCC_PLLCFGR_PLLR ((uint32_t)0x06000000U)
5793 #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x02000000U)
5794 #define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x04000000U)
5795
5796 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
5797 #define RCC_PLLSAI1CFGR_PLLSAI1N ((uint32_t)0x00007F00U)
5798 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 ((uint32_t)0x00000100U)
5799 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 ((uint32_t)0x00000200U)
5800 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 ((uint32_t)0x00000400U)
5801 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 ((uint32_t)0x00000800U)
5802 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 ((uint32_t)0x00001000U)
5803 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 ((uint32_t)0x00002000U)
5804 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 ((uint32_t)0x00004000U)
5805
5806 #define RCC_PLLSAI1CFGR_PLLSAI1PEN ((uint32_t)0x00010000U)
5807 #define RCC_PLLSAI1CFGR_PLLSAI1P ((uint32_t)0x00020000U)
5808
5809 #define RCC_PLLSAI1CFGR_PLLSAI1QEN ((uint32_t)0x00100000U)
5810 #define RCC_PLLSAI1CFGR_PLLSAI1Q ((uint32_t)0x00600000U)
5811 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 ((uint32_t)0x00200000U)
5812 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 ((uint32_t)0x00400000U)
5813
5814 #define RCC_PLLSAI1CFGR_PLLSAI1REN ((uint32_t)0x01000000U)
5815 #define RCC_PLLSAI1CFGR_PLLSAI1R ((uint32_t)0x06000000U)
5816 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 ((uint32_t)0x02000000U)
5817 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 ((uint32_t)0x04000000U)
5818
5819 /******************** Bit definition for RCC_PLLSAI2CFGR register ************/
5820 #define RCC_PLLSAI2CFGR_PLLSAI2N ((uint32_t)0x00007F00U)
5821 #define RCC_PLLSAI2CFGR_PLLSAI2N_0 ((uint32_t)0x00000100U)
5822 #define RCC_PLLSAI2CFGR_PLLSAI2N_1 ((uint32_t)0x00000200U)
5823 #define RCC_PLLSAI2CFGR_PLLSAI2N_2 ((uint32_t)0x00000400U)
5824 #define RCC_PLLSAI2CFGR_PLLSAI2N_3 ((uint32_t)0x00000800U)
5825 #define RCC_PLLSAI2CFGR_PLLSAI2N_4 ((uint32_t)0x00001000U)
5826 #define RCC_PLLSAI2CFGR_PLLSAI2N_5 ((uint32_t)0x00002000U)
5827 #define RCC_PLLSAI2CFGR_PLLSAI2N_6 ((uint32_t)0x00004000U)
5828
5829 #define RCC_PLLSAI2CFGR_PLLSAI2PEN ((uint32_t)0x00010000U)
5830 #define RCC_PLLSAI2CFGR_PLLSAI2P ((uint32_t)0x00020000U)
5831
5832 #define RCC_PLLSAI2CFGR_PLLSAI2REN ((uint32_t)0x01000000U)
5833 #define RCC_PLLSAI2CFGR_PLLSAI2R ((uint32_t)0x06000000U)
5834 #define RCC_PLLSAI2CFGR_PLLSAI2R_0 ((uint32_t)0x02000000U)
5835 #define RCC_PLLSAI2CFGR_PLLSAI2R_1 ((uint32_t)0x04000000U)
5836
5837 /******************** Bit definition for RCC_CIER register ******************/
5838 #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U)
5839 #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U)
5840 #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000004U)
5841 #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000008U)
5842 #define RCC_CIER_HSERDYIE ((uint32_t)0x00000010U)
5843 #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000020U)
5844 #define RCC_CIER_PLLSAI1RDYIE ((uint32_t)0x00000040U)
5845 #define RCC_CIER_PLLSAI2RDYIE ((uint32_t)0x00000080U)
5846 #define RCC_CIER_LSECSSIE ((uint32_t)0x00000200U)
5847
5848 /******************** Bit definition for RCC_CIFR register ******************/
5849 #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U)
5850 #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U)
5851 #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000004U)
5852 #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000008U)
5853 #define RCC_CIFR_HSERDYF ((uint32_t)0x00000010U)
5854 #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000020U)
5855 #define RCC_CIFR_PLLSAI1RDYF ((uint32_t)0x00000040U)
5856 #define RCC_CIFR_PLLSAI2RDYF ((uint32_t)0x00000080U)
5857 #define RCC_CIFR_CSSF ((uint32_t)0x00000100U)
5858 #define RCC_CIFR_LSECSSF ((uint32_t)0x00000200U)
5859
5860 /******************** Bit definition for RCC_CICR register ******************/
5861 #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U)
5862 #define RCC_CICR_LSERDYC ((uint32_t)0x00000002U)
5863 #define RCC_CICR_MSIRDYC ((uint32_t)0x00000004U)
5864 #define RCC_CICR_HSIRDYC ((uint32_t)0x00000008U)
5865 #define RCC_CICR_HSERDYC ((uint32_t)0x00000010U)
5866 #define RCC_CICR_PLLRDYC ((uint32_t)0x00000020U)
5867 #define RCC_CICR_PLLSAI1RDYC ((uint32_t)0x00000040U)
5868 #define RCC_CICR_PLLSAI2RDYC ((uint32_t)0x00000080U)
5869 #define RCC_CICR_CSSC ((uint32_t)0x00000100U)
5870 #define RCC_CICR_LSECSSC ((uint32_t)0x00000200U)
5871
5872 /******************** Bit definition for RCC_AHB1RSTR register **************/
5873 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00000001U)
5874 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00000002U)
5875 #define RCC_AHB1RSTR_FLASHRST ((uint32_t)0x00000100U)
5876 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000U)
5877 #define RCC_AHB1RSTR_TSCRST ((uint32_t)0x00010000U)
5878
5879 /******************** Bit definition for RCC_AHB2RSTR register **************/
5880 #define RCC_AHB2RSTR_GPIOARST ((uint32_t)0x00000001U)
5881 #define RCC_AHB2RSTR_GPIOBRST ((uint32_t)0x00000002U)
5882 #define RCC_AHB2RSTR_GPIOCRST ((uint32_t)0x00000004U)
5883 #define RCC_AHB2RSTR_GPIODRST ((uint32_t)0x00000008U)
5884 #define RCC_AHB2RSTR_GPIOERST ((uint32_t)0x00000010U)
5885 #define RCC_AHB2RSTR_GPIOFRST ((uint32_t)0x00000020U)
5886 #define RCC_AHB2RSTR_GPIOGRST ((uint32_t)0x00000040U)
5887 #define RCC_AHB2RSTR_GPIOHRST ((uint32_t)0x00000080U)
5888 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00001000U)
5889 #define RCC_AHB2RSTR_ADCRST ((uint32_t)0x00002000U)
5890 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00040000U)
5891
5892 /******************** Bit definition for RCC_AHB3RSTR register **************/
5893 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001U)
5894 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000100U)
5895
5896 /******************** Bit definition for RCC_APB1RSTR1 register **************/
5897 #define RCC_APB1RSTR1_TIM2RST ((uint32_t)0x00000001U)
5898 #define RCC_APB1RSTR1_TIM3RST ((uint32_t)0x00000002U)
5899 #define RCC_APB1RSTR1_TIM4RST ((uint32_t)0x00000004U)
5900 #define RCC_APB1RSTR1_TIM5RST ((uint32_t)0x00000008U)
5901 #define RCC_APB1RSTR1_TIM6RST ((uint32_t)0x00000010U)
5902 #define RCC_APB1RSTR1_TIM7RST ((uint32_t)0x00000020U)
5903 #define RCC_APB1RSTR1_SPI2RST ((uint32_t)0x00004000U)
5904 #define RCC_APB1RSTR1_SPI3RST ((uint32_t)0x00008000U)
5905 #define RCC_APB1RSTR1_USART2RST ((uint32_t)0x00020000U)
5906 #define RCC_APB1RSTR1_USART3RST ((uint32_t)0x00040000U)
5907 #define RCC_APB1RSTR1_UART4RST ((uint32_t)0x00080000U)
5908 #define RCC_APB1RSTR1_UART5RST ((uint32_t)0x00100000U)
5909 #define RCC_APB1RSTR1_I2C1RST ((uint32_t)0x00200000U)
5910 #define RCC_APB1RSTR1_I2C2RST ((uint32_t)0x00400000U)
5911 #define RCC_APB1RSTR1_I2C3RST ((uint32_t)0x00800000U)
5912 #define RCC_APB1RSTR1_CAN1RST ((uint32_t)0x02000000U)
5913 #define RCC_APB1RSTR1_PWRRST ((uint32_t)0x10000000U)
5914 #define RCC_APB1RSTR1_DAC1RST ((uint32_t)0x20000000U)
5915 #define RCC_APB1RSTR1_OPAMPRST ((uint32_t)0x40000000U)
5916 #define RCC_APB1RSTR1_LPTIM1RST ((uint32_t)0x80000000U)
5917
5918 /******************** Bit definition for RCC_APB1RSTR2 register **************/
5919 #define RCC_APB1RSTR2_LPUART1RST ((uint32_t)0x00000001U)
5920 #define RCC_APB1RSTR2_SWPMI1RST ((uint32_t)0x00000004U)
5921 #define RCC_APB1RSTR2_LPTIM2RST ((uint32_t)0x00000020U)
5922
5923 /******************** Bit definition for RCC_APB2RSTR register **************/
5924 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U)
5925 #define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000400U)
5926 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800U)
5927 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U)
5928 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000U)
5929 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U)
5930 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000U)
5931 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000U)
5932 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000U)
5933 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00200000U)
5934 #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00400000U)
5935 #define RCC_APB2RSTR_DFSDMRST ((uint32_t)0x01000000U)
5936
5937 /******************** Bit definition for RCC_AHB1ENR register ***************/
5938 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00000001U)
5939 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00000002U)
5940 #define RCC_AHB1ENR_FLASHEN ((uint32_t)0x00000100U)
5941 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000U)
5942 #define RCC_AHB1ENR_TSCEN ((uint32_t)0x00010000U)
5943
5944 /******************** Bit definition for RCC_AHB2ENR register ***************/
5945 #define RCC_AHB2ENR_GPIOAEN ((uint32_t)0x00000001U)
5946 #define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002U)
5947 #define RCC_AHB2ENR_GPIOCEN ((uint32_t)0x00000004U)
5948 #define RCC_AHB2ENR_GPIODEN ((uint32_t)0x00000008U)
5949 #define RCC_AHB2ENR_GPIOEEN ((uint32_t)0x00000010U)
5950 #define RCC_AHB2ENR_GPIOFEN ((uint32_t)0x00000020U)
5951 #define RCC_AHB2ENR_GPIOGEN ((uint32_t)0x00000040U)
5952 #define RCC_AHB2ENR_GPIOHEN ((uint32_t)0x00000080U)
5953 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00001000U)
5954 #define RCC_AHB2ENR_ADCEN ((uint32_t)0x00002000U)
5955 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00040000U)
5956
5957 /******************** Bit definition for RCC_AHB3ENR register ***************/
5958 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001U)
5959 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000100U)
5960
5961 /******************** Bit definition for RCC_APB1ENR1 register ***************/
5962 #define RCC_APB1ENR1_TIM2EN ((uint32_t)0x00000001U)
5963 #define RCC_APB1ENR1_TIM3EN ((uint32_t)0x00000002U)
5964 #define RCC_APB1ENR1_TIM4EN ((uint32_t)0x00000004U)
5965 #define RCC_APB1ENR1_TIM5EN ((uint32_t)0x00000008U)
5966 #define RCC_APB1ENR1_TIM6EN ((uint32_t)0x00000010U)
5967 #define RCC_APB1ENR1_TIM7EN ((uint32_t)0x00000020U)
5968 #define RCC_APB1ENR1_WWDGEN ((uint32_t)0x00000800U)
5969 #define RCC_APB1ENR1_SPI2EN ((uint32_t)0x00004000U)
5970 #define RCC_APB1ENR1_SPI3EN ((uint32_t)0x00008000U)
5971 #define RCC_APB1ENR1_USART2EN ((uint32_t)0x00020000U)
5972 #define RCC_APB1ENR1_USART3EN ((uint32_t)0x00040000U)
5973 #define RCC_APB1ENR1_UART4EN ((uint32_t)0x00080000U)
5974 #define RCC_APB1ENR1_UART5EN ((uint32_t)0x00100000U)
5975 #define RCC_APB1ENR1_I2C1EN ((uint32_t)0x00200000U)
5976 #define RCC_APB1ENR1_I2C2EN ((uint32_t)0x00400000U)
5977 #define RCC_APB1ENR1_I2C3EN ((uint32_t)0x00800000U)
5978 #define RCC_APB1ENR1_CAN1EN ((uint32_t)0x02000000U)
5979 #define RCC_APB1ENR1_PWREN ((uint32_t)0x10000000U)
5980 #define RCC_APB1ENR1_DAC1EN ((uint32_t)0x20000000U)
5981 #define RCC_APB1ENR1_OPAMPEN ((uint32_t)0x40000000U)
5982 #define RCC_APB1ENR1_LPTIM1EN ((uint32_t)0x80000000U)
5983
5984 /******************** Bit definition for RCC_APB1RSTR2 register **************/
5985 #define RCC_APB1ENR2_LPUART1EN ((uint32_t)0x00000001U)
5986 #define RCC_APB1ENR2_SWPMI1EN ((uint32_t)0x00000004U)
5987 #define RCC_APB1ENR2_LPTIM2EN ((uint32_t)0x00000020U)
5988
5989 /******************** Bit definition for RCC_APB2ENR register ***************/
5990 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U)
5991 #define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U)
5992 #define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000400U)
5993 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800U)
5994 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U)
5995 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000U)
5996 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U)
5997 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000U)
5998 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000U)
5999 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000U)
6000 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00200000U)
6001 #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00400000U)
6002 #define RCC_APB2ENR_DFSDMEN ((uint32_t)0x01000000U)
6003
6004 /******************** Bit definition for RCC_AHB1SMENR register ***************/
6005 #define RCC_AHB1SMENR_DMA1SMEN ((uint32_t)0x00000001U)
6006 #define RCC_AHB1SMENR_DMA2SMEN ((uint32_t)0x00000002U)
6007 #define RCC_AHB1SMENR_FLASHSMEN ((uint32_t)0x00000100U)
6008 #define RCC_AHB1SMENR_SRAM1SMEN ((uint32_t)0x00000200U)
6009 #define RCC_AHB1SMENR_CRCSMEN ((uint32_t)0x00001000U)
6010 #define RCC_AHB1SMENR_TSCSMEN ((uint32_t)0x00010000U)
6011
6012 /******************** Bit definition for RCC_AHB2SMENR register *************/
6013 #define RCC_AHB2SMENR_GPIOASMEN ((uint32_t)0x00000001U)
6014 #define RCC_AHB2SMENR_GPIOBSMEN ((uint32_t)0x00000002U)
6015 #define RCC_AHB2SMENR_GPIOCSMEN ((uint32_t)0x00000004U)
6016 #define RCC_AHB2SMENR_GPIODSMEN ((uint32_t)0x00000008U)
6017 #define RCC_AHB2SMENR_GPIOESMEN ((uint32_t)0x00000010U)
6018 #define RCC_AHB2SMENR_GPIOFSMEN ((uint32_t)0x00000020U)
6019 #define RCC_AHB2SMENR_GPIOGSMEN ((uint32_t)0x00000040U)
6020 #define RCC_AHB2SMENR_GPIOHSMEN ((uint32_t)0x00000080U)
6021 #define RCC_AHB2SMENR_SRAM2SMEN ((uint32_t)0x00000200U)
6022 #define RCC_AHB2SMENR_OTGFSSMEN ((uint32_t)0x00001000U)
6023 #define RCC_AHB2SMENR_ADCSMEN ((uint32_t)0x00002000U)
6024 #define RCC_AHB2SMENR_RNGSMEN ((uint32_t)0x00040000U)
6025
6026 /******************** Bit definition for RCC_AHB3SMENR register *************/
6027 #define RCC_AHB3SMENR_FMCSMEN ((uint32_t)0x00000001U)
6028 #define RCC_AHB3SMENR_QSPISMEN ((uint32_t)0x00000100U)
6029
6030 /******************** Bit definition for RCC_APB1SMENR1 register *************/
6031 #define RCC_APB1SMENR1_TIM2SMEN ((uint32_t)0x00000001U)
6032 #define RCC_APB1SMENR1_TIM3SMEN ((uint32_t)0x00000002U)
6033 #define RCC_APB1SMENR1_TIM4SMEN ((uint32_t)0x00000004U)
6034 #define RCC_APB1SMENR1_TIM5SMEN ((uint32_t)0x00000008U)
6035 #define RCC_APB1SMENR1_TIM6SMEN ((uint32_t)0x00000010U)
6036 #define RCC_APB1SMENR1_TIM7SMEN ((uint32_t)0x00000020U)
6037 #define RCC_APB1SMENR1_WWDGSMEN ((uint32_t)0x00000800U)
6038 #define RCC_APB1SMENR1_SPI2SMEN ((uint32_t)0x00004000U)
6039 #define RCC_APB1SMENR1_SPI3SMEN ((uint32_t)0x00008000U)
6040 #define RCC_APB1SMENR1_USART2SMEN ((uint32_t)0x00020000U)
6041 #define RCC_APB1SMENR1_USART3SMEN ((uint32_t)0x00040000U)
6042 #define RCC_APB1SMENR1_UART4SMEN ((uint32_t)0x00080000U)
6043 #define RCC_APB1SMENR1_UART5SMEN ((uint32_t)0x00100000U)
6044 #define RCC_APB1SMENR1_I2C1SMEN ((uint32_t)0x00200000U)
6045 #define RCC_APB1SMENR1_I2C2SMEN ((uint32_t)0x00400000U)
6046 #define RCC_APB1SMENR1_I2C3SMEN ((uint32_t)0x00800000U)
6047 #define RCC_APB1SMENR1_CAN1SMEN ((uint32_t)0x02000000U)
6048 #define RCC_APB1SMENR1_PWRSMEN ((uint32_t)0x10000000U)
6049 #define RCC_APB1SMENR1_DAC1SMEN ((uint32_t)0x20000000U)
6050 #define RCC_APB1SMENR1_OPAMPSMEN ((uint32_t)0x40000000U)
6051 #define RCC_APB1SMENR1_LPTIM1SMEN ((uint32_t)0x80000000U)
6052
6053 /******************** Bit definition for RCC_APB1SMENR2 register *************/
6054 #define RCC_APB1SMENR2_LPUART1SMEN ((uint32_t)0x00000001U)
6055 #define RCC_APB1SMENR2_SWPMI1SMEN ((uint32_t)0x00000004U)
6056 #define RCC_APB1SMENR2_LPTIM2SMEN ((uint32_t)0x00000020U)
6057
6058 /******************** Bit definition for RCC_APB2SMENR register *************/
6059 #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U)
6060 #define RCC_APB2SMENR_SDMMC1SMEN ((uint32_t)0x00000400U)
6061 #define RCC_APB2SMENR_TIM1SMEN ((uint32_t)0x00000800U)
6062 #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U)
6063 #define RCC_APB2SMENR_TIM8SMEN ((uint32_t)0x00002000U)
6064 #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U)
6065 #define RCC_APB2SMENR_TIM15SMEN ((uint32_t)0x00010000U)
6066 #define RCC_APB2SMENR_TIM16SMEN ((uint32_t)0x00020000U)
6067 #define RCC_APB2SMENR_TIM17SMEN ((uint32_t)0x00040000U)
6068 #define RCC_APB2SMENR_SAI1SMEN ((uint32_t)0x00200000U)
6069 #define RCC_APB2SMENR_SAI2SMEN ((uint32_t)0x00400000U)
6070 #define RCC_APB2SMENR_DFSDMSMEN ((uint32_t)0x01000000U)
6071
6072 /******************** Bit definition for RCC_CCIPR register ******************/
6073 #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U)
6074 #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U)
6075 #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U)
6076
6077 #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU)
6078 #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U)
6079 #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U)
6080
6081 #define RCC_CCIPR_USART3SEL ((uint32_t)0x00000030U)
6082 #define RCC_CCIPR_USART3SEL_0 ((uint32_t)0x00000010U)
6083 #define RCC_CCIPR_USART3SEL_1 ((uint32_t)0x00000020U)
6084
6085 #define RCC_CCIPR_UART4SEL ((uint32_t)0x000000C0U)
6086 #define RCC_CCIPR_UART4SEL_0 ((uint32_t)0x00000040U)
6087 #define RCC_CCIPR_UART4SEL_1 ((uint32_t)0x00000080U)
6088
6089 #define RCC_CCIPR_UART5SEL ((uint32_t)0x00000300U)
6090 #define RCC_CCIPR_UART5SEL_0 ((uint32_t)0x00000100U)
6091 #define RCC_CCIPR_UART5SEL_1 ((uint32_t)0x00000200U)
6092
6093 #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x00000C00U)
6094 #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x00000400U)
6095 #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x00000800U)
6096
6097 #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U)
6098 #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U)
6099 #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U)
6100
6101 #define RCC_CCIPR_I2C2SEL ((uint32_t)0x0000C000U)
6102 #define RCC_CCIPR_I2C2SEL_0 ((uint32_t)0x00004000U)
6103 #define RCC_CCIPR_I2C2SEL_1 ((uint32_t)0x00008000U)
6104
6105 #define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000U)
6106 #define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000U)
6107 #define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000U)
6108
6109 #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U)
6110 #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U)
6111 #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U)
6112
6113 #define RCC_CCIPR_LPTIM2SEL ((uint32_t)0x00300000U)
6114 #define RCC_CCIPR_LPTIM2SEL_0 ((uint32_t)0x00100000U)
6115 #define RCC_CCIPR_LPTIM2SEL_1 ((uint32_t)0x00200000U)
6116
6117 #define RCC_CCIPR_SAI1SEL ((uint32_t)0x00C00000U)
6118 #define RCC_CCIPR_SAI1SEL_0 ((uint32_t)0x00400000U)
6119 #define RCC_CCIPR_SAI1SEL_1 ((uint32_t)0x00800000U)
6120
6121 #define RCC_CCIPR_SAI2SEL ((uint32_t)0x03000000U)
6122 #define RCC_CCIPR_SAI2SEL_0 ((uint32_t)0x01000000U)
6123 #define RCC_CCIPR_SAI2SEL_1 ((uint32_t)0x02000000U)
6124
6125 #define RCC_CCIPR_CLK48SEL ((uint32_t)0x0C000000U)
6126 #define RCC_CCIPR_CLK48SEL_0 ((uint32_t)0x04000000U)
6127 #define RCC_CCIPR_CLK48SEL_1 ((uint32_t)0x08000000U)
6128
6129 #define RCC_CCIPR_ADCSEL ((uint32_t)0x30000000U)
6130 #define RCC_CCIPR_ADCSEL_0 ((uint32_t)0x10000000U)
6131 #define RCC_CCIPR_ADCSEL_1 ((uint32_t)0x20000000U)
6132
6133 #define RCC_CCIPR_SWPMI1SEL ((uint32_t)0x40000000U)
6134 #define RCC_CCIPR_DFSDMSEL ((uint32_t)0x80000000U)
6135
6136 /******************** Bit definition for RCC_BDCR register ******************/
6137 #define RCC_BDCR_LSEON ((uint32_t)0x00000001U)
6138 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002U)
6139 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004U)
6140
6141 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018U)
6142 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008U)
6143 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010U)
6144
6145 #define RCC_BDCR_LSECSSON ((uint32_t)0x00000020U)
6146 #define RCC_BDCR_LSECSSD ((uint32_t)0x00000040U)
6147
6148 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300U)
6149 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100U)
6150 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200U)
6151
6152 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000U)
6153 #define RCC_BDCR_BDRST ((uint32_t)0x00010000U)
6154 #define RCC_BDCR_LSCOEN ((uint32_t)0x01000000U)
6155 #define RCC_BDCR_LSCOSEL ((uint32_t)0x02000000U)
6156
6157 /******************** Bit definition for RCC_CSR register *******************/
6158 #define RCC_CSR_LSION ((uint32_t)0x00000001U)
6159 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002U)
6160
6161 #define RCC_CSR_MSISRANGE ((uint32_t)0x00000F00U)
6162 #define RCC_CSR_MSISRANGE_1 ((uint32_t)0x00000400U) /*!< MSI frequency 1MHZ */
6163 #define RCC_CSR_MSISRANGE_2 ((uint32_t)0x00000500U) /*!< MSI frequency 2MHZ */
6164 #define RCC_CSR_MSISRANGE_4 ((uint32_t)0x00000600U) /*!< The default frequency 4MHZ */
6165 #define RCC_CSR_MSISRANGE_8 ((uint32_t)0x00000700U) /*!< MSI frequency 8MHZ */
6166
6167 #define RCC_CSR_RMVF ((uint32_t)0x00800000U)
6168 #define RCC_CSR_FWRSTF ((uint32_t)0x01000000U)
6169 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U)
6170 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000U)
6171 #define RCC_CSR_BORRSTF ((uint32_t)0x08000000U)
6172 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U)
6173 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U)
6174 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U)
6175 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U)
6176
6177
6178
6179 /******************************************************************************/
6180 /* */
6181 /* RNG */
6182 /* */
6183 /******************************************************************************/
6184 /******************** Bits definition for RNG_CR register *******************/
6185 #define RNG_CR_RNGEN ((uint32_t)0x00000004U)
6186 #define RNG_CR_IE ((uint32_t)0x00000008U)
6187
6188 /******************** Bits definition for RNG_SR register *******************/
6189 #define RNG_SR_DRDY ((uint32_t)0x00000001U)
6190 #define RNG_SR_CECS ((uint32_t)0x00000002U)
6191 #define RNG_SR_SECS ((uint32_t)0x00000004U)
6192 #define RNG_SR_CEIS ((uint32_t)0x00000020U)
6193 #define RNG_SR_SEIS ((uint32_t)0x00000040U)
6194
6195 /******************************************************************************/
6196 /* */
6197 /* Real-Time Clock (RTC) */
6198 /* */
6199 /******************************************************************************/
6200 /*
6201 * @brief Specific device feature definitions
6202 */
6203 #define RTC_TAMPER1_SUPPORT
6204 #define RTC_TAMPER3_SUPPORT
6205 #define RTC_WAKEUP_SUPPORT
6206 #define RTC_BACKUP_SUPPORT
6207
6208 /******************** Bits definition for RTC_TR register *******************/
6209 #define RTC_TR_PM ((uint32_t)0x00400000U)
6210 #define RTC_TR_HT ((uint32_t)0x00300000U)
6211 #define RTC_TR_HT_0 ((uint32_t)0x00100000U)
6212 #define RTC_TR_HT_1 ((uint32_t)0x00200000U)
6213 #define RTC_TR_HU ((uint32_t)0x000F0000U)
6214 #define RTC_TR_HU_0 ((uint32_t)0x00010000U)
6215 #define RTC_TR_HU_1 ((uint32_t)0x00020000U)
6216 #define RTC_TR_HU_2 ((uint32_t)0x00040000U)
6217 #define RTC_TR_HU_3 ((uint32_t)0x00080000U)
6218 #define RTC_TR_MNT ((uint32_t)0x00007000U)
6219 #define RTC_TR_MNT_0 ((uint32_t)0x00001000U)
6220 #define RTC_TR_MNT_1 ((uint32_t)0x00002000U)
6221 #define RTC_TR_MNT_2 ((uint32_t)0x00004000U)
6222 #define RTC_TR_MNU ((uint32_t)0x00000F00U)
6223 #define RTC_TR_MNU_0 ((uint32_t)0x00000100U)
6224 #define RTC_TR_MNU_1 ((uint32_t)0x00000200U)
6225 #define RTC_TR_MNU_2 ((uint32_t)0x00000400U)
6226 #define RTC_TR_MNU_3 ((uint32_t)0x00000800U)
6227 #define RTC_TR_ST ((uint32_t)0x00000070U)
6228 #define RTC_TR_ST_0 ((uint32_t)0x00000010U)
6229 #define RTC_TR_ST_1 ((uint32_t)0x00000020U)
6230 #define RTC_TR_ST_2 ((uint32_t)0x00000040U)
6231 #define RTC_TR_SU ((uint32_t)0x0000000FU)
6232 #define RTC_TR_SU_0 ((uint32_t)0x00000001U)
6233 #define RTC_TR_SU_1 ((uint32_t)0x00000002U)
6234 #define RTC_TR_SU_2 ((uint32_t)0x00000004U)
6235 #define RTC_TR_SU_3 ((uint32_t)0x00000008U)
6236
6237 /******************** Bits definition for RTC_DR register *******************/
6238 #define RTC_DR_YT ((uint32_t)0x00F00000U)
6239 #define RTC_DR_YT_0 ((uint32_t)0x00100000U)
6240 #define RTC_DR_YT_1 ((uint32_t)0x00200000U)
6241 #define RTC_DR_YT_2 ((uint32_t)0x00400000U)
6242 #define RTC_DR_YT_3 ((uint32_t)0x00800000U)
6243 #define RTC_DR_YU ((uint32_t)0x000F0000U)
6244 #define RTC_DR_YU_0 ((uint32_t)0x00010000U)
6245 #define RTC_DR_YU_1 ((uint32_t)0x00020000U)
6246 #define RTC_DR_YU_2 ((uint32_t)0x00040000U)
6247 #define RTC_DR_YU_3 ((uint32_t)0x00080000U)
6248 #define RTC_DR_WDU ((uint32_t)0x0000E000U)
6249 #define RTC_DR_WDU_0 ((uint32_t)0x00002000U)
6250 #define RTC_DR_WDU_1 ((uint32_t)0x00004000U)
6251 #define RTC_DR_WDU_2 ((uint32_t)0x00008000U)
6252 #define RTC_DR_MT ((uint32_t)0x00001000U)
6253 #define RTC_DR_MU ((uint32_t)0x00000F00U)
6254 #define RTC_DR_MU_0 ((uint32_t)0x00000100U)
6255 #define RTC_DR_MU_1 ((uint32_t)0x00000200U)
6256 #define RTC_DR_MU_2 ((uint32_t)0x00000400U)
6257 #define RTC_DR_MU_3 ((uint32_t)0x00000800U)
6258 #define RTC_DR_DT ((uint32_t)0x00000030U)
6259 #define RTC_DR_DT_0 ((uint32_t)0x00000010U)
6260 #define RTC_DR_DT_1 ((uint32_t)0x00000020U)
6261 #define RTC_DR_DU ((uint32_t)0x0000000FU)
6262 #define RTC_DR_DU_0 ((uint32_t)0x00000001U)
6263 #define RTC_DR_DU_1 ((uint32_t)0x00000002U)
6264 #define RTC_DR_DU_2 ((uint32_t)0x00000004U)
6265 #define RTC_DR_DU_3 ((uint32_t)0x00000008U)
6266
6267 /******************** Bits definition for RTC_CR register *******************/
6268 #define RTC_CR_ITSE ((uint32_t)0x01000000U)
6269 #define RTC_CR_COE ((uint32_t)0x00800000U)
6270 #define RTC_CR_OSEL ((uint32_t)0x00600000U)
6271 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000U)
6272 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000U)
6273 #define RTC_CR_POL ((uint32_t)0x00100000U)
6274 #define RTC_CR_COSEL ((uint32_t)0x00080000U)
6275 #define RTC_CR_BCK ((uint32_t)0x00040000U)
6276 #define RTC_CR_SUB1H ((uint32_t)0x00020000U)
6277 #define RTC_CR_ADD1H ((uint32_t)0x00010000U)
6278 #define RTC_CR_TSIE ((uint32_t)0x00008000U)
6279 #define RTC_CR_WUTIE ((uint32_t)0x00004000U)
6280 #define RTC_CR_ALRBIE ((uint32_t)0x00002000U)
6281 #define RTC_CR_ALRAIE ((uint32_t)0x00001000U)
6282 #define RTC_CR_TSE ((uint32_t)0x00000800U)
6283 #define RTC_CR_WUTE ((uint32_t)0x00000400U)
6284 #define RTC_CR_ALRBE ((uint32_t)0x00000200U)
6285 #define RTC_CR_ALRAE ((uint32_t)0x00000100U)
6286 #define RTC_CR_FMT ((uint32_t)0x00000040U)
6287 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020U)
6288 #define RTC_CR_REFCKON ((uint32_t)0x00000010U)
6289 #define RTC_CR_TSEDGE ((uint32_t)0x00000008U)
6290 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007U)
6291 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U)
6292 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U)
6293 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U)
6294
6295 /******************** Bits definition for RTC_ISR register ******************/
6296 #define RTC_ISR_ITSF ((uint32_t)0x00020000U)
6297 #define RTC_ISR_RECALPF ((uint32_t)0x00010000U)
6298 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000U)
6299 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000U)
6300 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000U)
6301 #define RTC_ISR_TSOVF ((uint32_t)0x00001000U)
6302 #define RTC_ISR_TSF ((uint32_t)0x00000800U)
6303 #define RTC_ISR_WUTF ((uint32_t)0x00000400U)
6304 #define RTC_ISR_ALRBF ((uint32_t)0x00000200U)
6305 #define RTC_ISR_ALRAF ((uint32_t)0x00000100U)
6306 #define RTC_ISR_INIT ((uint32_t)0x00000080U)
6307 #define RTC_ISR_INITF ((uint32_t)0x00000040U)
6308 #define RTC_ISR_RSF ((uint32_t)0x00000020U)
6309 #define RTC_ISR_INITS ((uint32_t)0x00000010U)
6310 #define RTC_ISR_SHPF ((uint32_t)0x00000008U)
6311 #define RTC_ISR_WUTWF ((uint32_t)0x00000004U)
6312 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002U)
6313 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001U)
6314
6315 /******************** Bits definition for RTC_PRER register *****************/
6316 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U)
6317 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU)
6318
6319 /******************** Bits definition for RTC_WUTR register *****************/
6320 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
6321
6322 /******************** Bits definition for RTC_ALRMAR register ***************/
6323 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U)
6324 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U)
6325 #define RTC_ALRMAR_DT ((uint32_t)0x30000000U)
6326 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U)
6327 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U)
6328 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000U)
6329 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U)
6330 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U)
6331 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U)
6332 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U)
6333 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U)
6334 #define RTC_ALRMAR_PM ((uint32_t)0x00400000U)
6335 #define RTC_ALRMAR_HT ((uint32_t)0x00300000U)
6336 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U)
6337 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U)
6338 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000U)
6339 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U)
6340 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U)
6341 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U)
6342 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U)
6343 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U)
6344 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000U)
6345 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U)
6346 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U)
6347 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U)
6348 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U)
6349 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U)
6350 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U)
6351 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U)
6352 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U)
6353 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U)
6354 #define RTC_ALRMAR_ST ((uint32_t)0x00000070U)
6355 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U)
6356 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U)
6357 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U)
6358 #define RTC_ALRMAR_SU ((uint32_t)0x0000000FU)
6359 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U)
6360 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U)
6361 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U)
6362 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U)
6363
6364 /******************** Bits definition for RTC_ALRMBR register ***************/
6365 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U)
6366 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U)
6367 #define RTC_ALRMBR_DT ((uint32_t)0x30000000U)
6368 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U)
6369 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U)
6370 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000U)
6371 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U)
6372 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U)
6373 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U)
6374 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U)
6375 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U)
6376 #define RTC_ALRMBR_PM ((uint32_t)0x00400000U)
6377 #define RTC_ALRMBR_HT ((uint32_t)0x00300000U)
6378 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U)
6379 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U)
6380 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000U)
6381 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U)
6382 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U)
6383 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U)
6384 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U)
6385 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U)
6386 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000U)
6387 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U)
6388 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U)
6389 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U)
6390 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U)
6391 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U)
6392 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U)
6393 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U)
6394 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U)
6395 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U)
6396 #define RTC_ALRMBR_ST ((uint32_t)0x00000070U)
6397 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U)
6398 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U)
6399 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U)
6400 #define RTC_ALRMBR_SU ((uint32_t)0x0000000FU)
6401 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U)
6402 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U)
6403 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U)
6404 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U)
6405
6406 /******************** Bits definition for RTC_WPR register ******************/
6407 #define RTC_WPR_KEY ((uint32_t)0x000000FFU)
6408
6409 /******************** Bits definition for RTC_SSR register ******************/
6410 #define RTC_SSR_SS ((uint32_t)0x0000FFFFU)
6411
6412 /******************** Bits definition for RTC_SHIFTR register ***************/
6413 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU)
6414 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U)
6415
6416 /******************** Bits definition for RTC_TSTR register *****************/
6417 #define RTC_TSTR_PM ((uint32_t)0x00400000U)
6418 #define RTC_TSTR_HT ((uint32_t)0x00300000U)
6419 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000U)
6420 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000U)
6421 #define RTC_TSTR_HU ((uint32_t)0x000F0000U)
6422 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000U)
6423 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000U)
6424 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000U)
6425 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000U)
6426 #define RTC_TSTR_MNT ((uint32_t)0x00007000U)
6427 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U)
6428 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U)
6429 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U)
6430 #define RTC_TSTR_MNU ((uint32_t)0x00000F00U)
6431 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U)
6432 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U)
6433 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U)
6434 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U)
6435 #define RTC_TSTR_ST ((uint32_t)0x00000070U)
6436 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010U)
6437 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020U)
6438 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040U)
6439 #define RTC_TSTR_SU ((uint32_t)0x0000000FU)
6440 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001U)
6441 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002U)
6442 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004U)
6443 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008U)
6444
6445 /******************** Bits definition for RTC_TSDR register *****************/
6446 #define RTC_TSDR_WDU ((uint32_t)0x0000E000U)
6447 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U)
6448 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U)
6449 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U)
6450 #define RTC_TSDR_MT ((uint32_t)0x00001000U)
6451 #define RTC_TSDR_MU ((uint32_t)0x00000F00U)
6452 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100U)
6453 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200U)
6454 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400U)
6455 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800U)
6456 #define RTC_TSDR_DT ((uint32_t)0x00000030U)
6457 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010U)
6458 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020U)
6459 #define RTC_TSDR_DU ((uint32_t)0x0000000FU)
6460 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001U)
6461 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002U)
6462 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004U)
6463 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008U)
6464
6465 /******************** Bits definition for RTC_TSSSR register ****************/
6466 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
6467
6468 /******************** Bits definition for RTC_CAL register *****************/
6469 #define RTC_CALR_CALP ((uint32_t)0x00008000U)
6470 #define RTC_CALR_CALW8 ((uint32_t)0x00004000U)
6471 #define RTC_CALR_CALW16 ((uint32_t)0x00002000U)
6472 #define RTC_CALR_CALM ((uint32_t)0x000001FFU)
6473 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001U)
6474 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002U)
6475 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004U)
6476 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008U)
6477 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010U)
6478 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020U)
6479 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040U)
6480 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080U)
6481 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100U)
6482
6483 /******************** Bits definition for RTC_TAMPCR register ***************/
6484 #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U)
6485 #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U)
6486 #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U)
6487 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U)
6488 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U)
6489 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U)
6490 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U)
6491 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U)
6492 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U)
6493 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U)
6494 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U)
6495 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U)
6496 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U)
6497 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U)
6498 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U)
6499 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U)
6500 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U)
6501 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U)
6502 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U)
6503 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U)
6504 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U)
6505 #define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U)
6506 #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U)
6507 #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U)
6508 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U)
6509 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U)
6510 #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U)
6511 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U)
6512
6513 /******************** Bits definition for RTC_ALRMASSR register *************/
6514 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
6515 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
6516 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
6517 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
6518 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
6519 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
6520
6521 /******************** Bits definition for RTC_ALRMBSSR register *************/
6522 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
6523 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
6524 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
6525 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
6526 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
6527 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
6528
6529 /******************** Bits definition for RTC_0R register *******************/
6530 #define RTC_OR_OUT_RMP ((uint32_t)0x00000002U)
6531 #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U)
6532
6533
6534 /******************** Bits definition for RTC_BKP0R register ****************/
6535 #define RTC_BKP0R ((uint32_t)0xFFFFFFFFU)
6536
6537 /******************** Bits definition for RTC_BKP1R register ****************/
6538 #define RTC_BKP1R ((uint32_t)0xFFFFFFFFU)
6539
6540 /******************** Bits definition for RTC_BKP2R register ****************/
6541 #define RTC_BKP2R ((uint32_t)0xFFFFFFFFU)
6542
6543 /******************** Bits definition for RTC_BKP3R register ****************/
6544 #define RTC_BKP3R ((uint32_t)0xFFFFFFFFU)
6545
6546 /******************** Bits definition for RTC_BKP4R register ****************/
6547 #define RTC_BKP4R ((uint32_t)0xFFFFFFFFU)
6548
6549 /******************** Bits definition for RTC_BKP5R register ****************/
6550 #define RTC_BKP5R ((uint32_t)0xFFFFFFFFU)
6551
6552 /******************** Bits definition for RTC_BKP6R register ****************/
6553 #define RTC_BKP6R ((uint32_t)0xFFFFFFFFU)
6554
6555 /******************** Bits definition for RTC_BKP7R register ****************/
6556 #define RTC_BKP7R ((uint32_t)0xFFFFFFFFU)
6557
6558 /******************** Bits definition for RTC_BKP8R register ****************/
6559 #define RTC_BKP8R ((uint32_t)0xFFFFFFFFU)
6560
6561 /******************** Bits definition for RTC_BKP9R register ****************/
6562 #define RTC_BKP9R ((uint32_t)0xFFFFFFFFU)
6563
6564 /******************** Bits definition for RTC_BKP10R register ***************/
6565 #define RTC_BKP10R ((uint32_t)0xFFFFFFFFU)
6566
6567 /******************** Bits definition for RTC_BKP11R register ***************/
6568 #define RTC_BKP11R ((uint32_t)0xFFFFFFFFU)
6569
6570 /******************** Bits definition for RTC_BKP12R register ***************/
6571 #define RTC_BKP12R ((uint32_t)0xFFFFFFFFU)
6572
6573 /******************** Bits definition for RTC_BKP13R register ***************/
6574 #define RTC_BKP13R ((uint32_t)0xFFFFFFFFU)
6575
6576 /******************** Bits definition for RTC_BKP14R register ***************/
6577 #define RTC_BKP14R ((uint32_t)0xFFFFFFFFU)
6578
6579 /******************** Bits definition for RTC_BKP15R register ***************/
6580 #define RTC_BKP15R ((uint32_t)0xFFFFFFFFU)
6581
6582 /******************** Bits definition for RTC_BKP16R register ***************/
6583 #define RTC_BKP16R ((uint32_t)0xFFFFFFFFU)
6584
6585 /******************** Bits definition for RTC_BKP17R register ***************/
6586 #define RTC_BKP17R ((uint32_t)0xFFFFFFFFU)
6587
6588 /******************** Bits definition for RTC_BKP18R register ***************/
6589 #define RTC_BKP18R ((uint32_t)0xFFFFFFFFU)
6590
6591 /******************** Bits definition for RTC_BKP19R register ***************/
6592 #define RTC_BKP19R ((uint32_t)0xFFFFFFFFU)
6593
6594 /******************** Bits definition for RTC_BKP20R register ***************/
6595 #define RTC_BKP20R ((uint32_t)0xFFFFFFFFU)
6596
6597 /******************** Bits definition for RTC_BKP21R register ***************/
6598 #define RTC_BKP21R ((uint32_t)0xFFFFFFFFU)
6599
6600 /******************** Bits definition for RTC_BKP22R register ***************/
6601 #define RTC_BKP22R ((uint32_t)0xFFFFFFFFU)
6602
6603 /******************** Bits definition for RTC_BKP23R register ***************/
6604 #define RTC_BKP23R ((uint32_t)0xFFFFFFFFU)
6605
6606 /******************** Bits definition for RTC_BKP24R register ***************/
6607 #define RTC_BKP24R ((uint32_t)0xFFFFFFFFU)
6608
6609 /******************** Bits definition for RTC_BKP25R register ***************/
6610 #define RTC_BKP25R ((uint32_t)0xFFFFFFFFU)
6611
6612 /******************** Bits definition for RTC_BKP26R register ***************/
6613 #define RTC_BKP26R ((uint32_t)0xFFFFFFFFU)
6614
6615 /******************** Bits definition for RTC_BKP27R register ***************/
6616 #define RTC_BKP27R ((uint32_t)0xFFFFFFFFU)
6617
6618 /******************** Bits definition for RTC_BKP28R register ***************/
6619 #define RTC_BKP28R ((uint32_t)0xFFFFFFFFU)
6620
6621 /******************** Bits definition for RTC_BKP29R register ***************/
6622 #define RTC_BKP29R ((uint32_t)0xFFFFFFFFU)
6623
6624 /******************** Bits definition for RTC_BKP30R register ***************/
6625 #define RTC_BKP30R ((uint32_t)0xFFFFFFFFU)
6626
6627 /******************** Bits definition for RTC_BKP31R register ***************/
6628 #define RTC_BKP31R ((uint32_t)0xFFFFFFFFU)
6629
6630 /******************** Number of backup registers ******************************/
6631 #define RTC_BKP_NUMBER ((uint32_t)0x00000020U)
6632
6633 /******************************************************************************/
6634 /* */
6635 /* Serial Audio Interface */
6636 /* */
6637 /******************************************************************************/
6638 /******************** Bit definition for SAI_GCR register *******************/
6639 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003U) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
6640 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
6641 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
6642
6643 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030U) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
6644 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
6645 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
6646
6647 /******************* Bit definition for SAI_xCR1 register *******************/
6648 #define SAI_xCR1_MODE ((uint32_t)0x00000003U) /*!<MODE[1:0] bits (Audio Block Mode) */
6649 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
6650 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
6651
6652 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000CU) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
6653 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
6654 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
6655
6656 #define SAI_xCR1_DS ((uint32_t)0x000000E0U) /*!<DS[1:0] bits (Data Size) */
6657 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
6658 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
6659 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
6660
6661 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100U) /*!<LSB First Configuration */
6662 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200U) /*!<ClocK STRobing edge */
6663
6664 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00U) /*!<SYNCEN[1:0](SYNChronization ENable) */
6665 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
6666 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
6667
6668 #define SAI_xCR1_MONO ((uint32_t)0x00001000U) /*!<Mono mode */
6669 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000U) /*!<Output Drive */
6670 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000U) /*!<Audio Block enable */
6671 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000U) /*!<DMA enable */
6672 #define SAI_xCR1_NODIV ((uint32_t)0x00080000U) /*!<No Divider Configuration */
6673
6674 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000U) /*!<MCKDIV[3:0] (Master ClocK Divider) */
6675 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
6676 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
6677 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
6678 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000U) /*!<Bit 3 */
6679
6680 /******************* Bit definition for SAI_xCR2 register *******************/
6681 #define SAI_xCR2_FTH ((uint32_t)0x00000007U) /*!<FTH[2:0](Fifo THreshold) */
6682 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
6683 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
6684 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
6685
6686 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008U) /*!<Fifo FLUSH */
6687 #define SAI_xCR2_TRIS ((uint32_t)0x00000010U) /*!<TRIState Management on data line */
6688 #define SAI_xCR2_MUTE ((uint32_t)0x00000020U) /*!<Mute mode */
6689 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040U) /*!<Muate value */
6690
6691
6692 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80U) /*!<MUTECNT[5:0] (MUTE counter) */
6693 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
6694 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
6695 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200U) /*!<Bit 2 */
6696 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400U) /*!<Bit 3 */
6697 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800U) /*!<Bit 4 */
6698 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000U) /*!<Bit 5 */
6699
6700 #define SAI_xCR2_CPL ((uint32_t)0x00002000U) /*!<CPL mode */
6701 #define SAI_xCR2_COMP ((uint32_t)0x0000C000U) /*!<COMP[1:0] (Companding mode) */
6702 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
6703 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
6704
6705
6706 /****************** Bit definition for SAI_xFRCR register *******************/
6707 #define SAI_xFRCR_FRL ((uint32_t)0x000000FFU) /*!<FRL[7:0](Frame length) */
6708 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
6709 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
6710 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
6711 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
6712 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
6713 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
6714 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
6715 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
6716
6717 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00U) /*!<FRL[6:0] (Frame synchronization active level length) */
6718 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
6719 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
6720 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
6721 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
6722 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
6723 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
6724 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
6725
6726 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000U) /*!< Frame Synchronization Definition */
6727 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000U) /*!<Frame Synchronization POLarity */
6728 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000U) /*!<Frame Synchronization OFFset */
6729
6730 /****************** Bit definition for SAI_xSLOTR register *******************/
6731 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001FU) /*!<FRL[4:0](First Bit Offset) */
6732 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
6733 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
6734 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
6735 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
6736 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
6737
6738 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0U) /*!<SLOTSZ[1:0] (Slot size) */
6739 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
6740 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
6741
6742 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00U) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
6743 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
6744 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
6745 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
6746 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
6747
6748 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000U) /*!<SLOTEN[15:0] (Slot Enable) */
6749
6750 /******************* Bit definition for SAI_xIMR register *******************/
6751 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001U) /*!<Overrun underrun interrupt enable */
6752 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002U) /*!<Mute detection interrupt enable */
6753 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004U) /*!<Wrong Clock Configuration interrupt enable */
6754 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008U) /*!<FIFO request interrupt enable */
6755 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010U) /*!<Codec not ready interrupt enable */
6756 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020U) /*!<Anticipated frame synchronization detection interrupt enable */
6757 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040U) /*!<Late frame synchronization detection interrupt enable */
6758
6759 /******************** Bit definition for SAI_xSR register *******************/
6760 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001U) /*!<Overrun underrun */
6761 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002U) /*!<Mute detection */
6762 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004U) /*!<Wrong Clock Configuration */
6763 #define SAI_xSR_FREQ ((uint32_t)0x00000008U) /*!<FIFO request */
6764 #define SAI_xSR_CNRDY ((uint32_t)0x00000010U) /*!<Codec not ready */
6765 #define SAI_xSR_AFSDET ((uint32_t)0x00000020U) /*!<Anticipated frame synchronization detection */
6766 #define SAI_xSR_LFSDET ((uint32_t)0x00000040U) /*!<Late frame synchronization detection */
6767
6768 #define SAI_xSR_FLVL ((uint32_t)0x00070000U) /*!<FLVL[2:0] (FIFO Level Threshold) */
6769 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
6770 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
6771 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000U) /*!<Bit 2 */
6772
6773 /****************** Bit definition for SAI_xCLRFR register ******************/
6774 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001U) /*!<Clear Overrun underrun */
6775 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002U) /*!<Clear Mute detection */
6776 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004U) /*!<Clear Wrong Clock Configuration */
6777 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008U) /*!<Clear FIFO request */
6778 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010U) /*!<Clear Codec not ready */
6779 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020U) /*!<Clear Anticipated frame synchronization detection */
6780 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040U) /*!<Clear Late frame synchronization detection */
6781
6782 /****************** Bit definition for SAI_xDR register ******************/
6783 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFFU)
6784
6785 /******************************************************************************/
6786 /* */
6787 /* SDMMC Interface */
6788 /* */
6789 /******************************************************************************/
6790 /****************** Bit definition for SDMMC_POWER register ******************/
6791 #define SDMMC_POWER_PWRCTRL ((uint8_t)0x03U) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
6792 #define SDMMC_POWER_PWRCTRL_0 ((uint8_t)0x01U) /*!<Bit 0 */
6793 #define SDMMC_POWER_PWRCTRL_1 ((uint8_t)0x02U) /*!<Bit 1 */
6794
6795 /****************** Bit definition for SDMMC_CLKCR register ******************/
6796 #define SDMMC_CLKCR_CLKDIV ((uint16_t)0x00FFU) /*!<Clock divide factor */
6797 #define SDMMC_CLKCR_CLKEN ((uint16_t)0x0100U) /*!<Clock enable bit */
6798 #define SDMMC_CLKCR_PWRSAV ((uint16_t)0x0200U) /*!<Power saving configuration bit */
6799 #define SDMMC_CLKCR_BYPASS ((uint16_t)0x0400U) /*!<Clock divider bypass enable bit */
6800
6801 #define SDMMC_CLKCR_WIDBUS ((uint16_t)0x1800U) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
6802 #define SDMMC_CLKCR_WIDBUS_0 ((uint16_t)0x0800U) /*!<Bit 0 */
6803 #define SDMMC_CLKCR_WIDBUS_1 ((uint16_t)0x1000U) /*!<Bit 1 */
6804
6805 #define SDMMC_CLKCR_NEGEDGE ((uint16_t)0x2000U) /*!<SDMMC_CK dephasing selection bit */
6806 #define SDMMC_CLKCR_HWFC_EN ((uint16_t)0x4000U) /*!<HW Flow Control enable */
6807
6808 /******************* Bit definition for SDMMC_ARG register *******************/
6809 #define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFFU) /*!<Command argument */
6810
6811 /******************* Bit definition for SDMMC_CMD register *******************/
6812 #define SDMMC_CMD_CMDINDEX ((uint16_t)0x003FU) /*!<Command Index */
6813
6814 #define SDMMC_CMD_WAITRESP ((uint16_t)0x00C0U) /*!<WAITRESP[1:0] bits (Wait for response bits) */
6815 #define SDMMC_CMD_WAITRESP_0 ((uint16_t)0x0040U) /*!< Bit 0 */
6816 #define SDMMC_CMD_WAITRESP_1 ((uint16_t)0x0080U) /*!< Bit 1 */
6817
6818 #define SDMMC_CMD_WAITINT ((uint16_t)0x0100U) /*!<CPSM Waits for Interrupt Request */
6819 #define SDMMC_CMD_WAITPEND ((uint16_t)0x0200U) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
6820 #define SDMMC_CMD_CPSMEN ((uint16_t)0x0400U) /*!<Command path state machine (CPSM) Enable bit */
6821 #define SDMMC_CMD_SDIOSUSPEND ((uint16_t)0x0800U) /*!<SD I/O suspend command */
6822
6823 /***************** Bit definition for SDMMC_RESPCMD register *****************/
6824 #define SDMMC_RESPCMD_RESPCMD ((uint8_t)0x3FU) /*!<Response command index */
6825
6826 /****************** Bit definition for SDMMC_RESP0 register ******************/
6827 #define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
6828
6829 /****************** Bit definition for SDMMC_RESP1 register ******************/
6830 #define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
6831
6832 /****************** Bit definition for SDMMC_RESP2 register ******************/
6833 #define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
6834
6835 /****************** Bit definition for SDMMC_RESP3 register ******************/
6836 #define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
6837
6838 /****************** Bit definition for SDMMC_RESP4 register ******************/
6839 #define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
6840
6841 /****************** Bit definition for SDMMC_DTIMER register *****************/
6842 #define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFFU) /*!<Data timeout period. */
6843
6844 /****************** Bit definition for SDMMC_DLEN register *******************/
6845 #define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFFU) /*!<Data length value */
6846
6847 /****************** Bit definition for SDMMC_DCTRL register ******************/
6848 #define SDMMC_DCTRL_DTEN ((uint16_t)0x0001U) /*!<Data transfer enabled bit */
6849 #define SDMMC_DCTRL_DTDIR ((uint16_t)0x0002U) /*!<Data transfer direction selection */
6850 #define SDMMC_DCTRL_DTMODE ((uint16_t)0x0004U) /*!<Data transfer mode selection */
6851 #define SDMMC_DCTRL_DMAEN ((uint16_t)0x0008U) /*!<DMA enabled bit */
6852
6853 #define SDMMC_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0U) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
6854 #define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010U) /*!<Bit 0 */
6855 #define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020U) /*!<Bit 1 */
6856 #define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040U) /*!<Bit 2 */
6857 #define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080U) /*!<Bit 3 */
6858
6859 #define SDMMC_DCTRL_RWSTART ((uint16_t)0x0100U) /*!<Read wait start */
6860 #define SDMMC_DCTRL_RWSTOP ((uint16_t)0x0200U) /*!<Read wait stop */
6861 #define SDMMC_DCTRL_RWMOD ((uint16_t)0x0400U) /*!<Read wait mode */
6862 #define SDMMC_DCTRL_SDIOEN ((uint16_t)0x0800U) /*!<SD I/O enable functions */
6863
6864 /****************** Bit definition for SDMMC_DCOUNT register *****************/
6865 #define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFFU) /*!<Data count value */
6866
6867 /****************** Bit definition for SDMMC_STA register ********************/
6868 #define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001U) /*!<Command response received (CRC check failed) */
6869 #define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002U) /*!<Data block sent/received (CRC check failed) */
6870 #define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004U) /*!<Command response timeout */
6871 #define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008U) /*!<Data timeout */
6872 #define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010U) /*!<Transmit FIFO underrun error */
6873 #define SDMMC_STA_RXOVERR ((uint32_t)0x00000020U) /*!<Received FIFO overrun error */
6874 #define SDMMC_STA_CMDREND ((uint32_t)0x00000040U) /*!<Command response received (CRC check passed) */
6875 #define SDMMC_STA_CMDSENT ((uint32_t)0x00000080U) /*!<Command sent (no response required) */
6876 #define SDMMC_STA_DATAEND ((uint32_t)0x00000100U) /*!<Data end (data counter, SDIDCOUNT, is zero) */
6877 #define SDMMC_STA_STBITERR ((uint32_t)0x00000200U) /*!<Start bit not detected on all data signals in wide bus mode */
6878 #define SDMMC_STA_DBCKEND ((uint32_t)0x00000400U) /*!<Data block sent/received (CRC check passed) */
6879 #define SDMMC_STA_CMDACT ((uint32_t)0x00000800U) /*!<Command transfer in progress */
6880 #define SDMMC_STA_TXACT ((uint32_t)0x00001000U) /*!<Data transmit in progress */
6881 #define SDMMC_STA_RXACT ((uint32_t)0x00002000U) /*!<Data receive in progress */
6882 #define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000U) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
6883 #define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000U) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
6884 #define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000U) /*!<Transmit FIFO full */
6885 #define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000U) /*!<Receive FIFO full */
6886 #define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000U) /*!<Transmit FIFO empty */
6887 #define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000U) /*!<Receive FIFO empty */
6888 #define SDMMC_STA_TXDAVL ((uint32_t)0x00100000U) /*!<Data available in transmit FIFO */
6889 #define SDMMC_STA_RXDAVL ((uint32_t)0x00200000U) /*!<Data available in receive FIFO */
6890 #define SDMMC_STA_SDIOIT ((uint32_t)0x00400000U) /*!<SDIO interrupt received */
6891
6892 /******************* Bit definition for SDMMC_ICR register *******************/
6893 #define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001U) /*!<CCRCFAIL flag clear bit */
6894 #define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002U) /*!<DCRCFAIL flag clear bit */
6895 #define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004U) /*!<CTIMEOUT flag clear bit */
6896 #define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008U) /*!<DTIMEOUT flag clear bit */
6897 #define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010U) /*!<TXUNDERR flag clear bit */
6898 #define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020U) /*!<RXOVERR flag clear bit */
6899 #define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040U) /*!<CMDREND flag clear bit */
6900 #define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080U) /*!<CMDSENT flag clear bit */
6901 #define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100U) /*!<DATAEND flag clear bit */
6902 #define SDMMC_ICR_STBITERRC ((uint32_t)0x00000200U) /*!<STBITERR flag clear bit */
6903 #define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400U) /*!<DBCKEND flag clear bit */
6904 #define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000U) /*!<SDIOIT flag clear bit */
6905
6906 /****************** Bit definition for SDMMC_MASK register *******************/
6907 #define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001U) /*!<Command CRC Fail Interrupt Enable */
6908 #define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002U) /*!<Data CRC Fail Interrupt Enable */
6909 #define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004U) /*!<Command TimeOut Interrupt Enable */
6910 #define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008U) /*!<Data TimeOut Interrupt Enable */
6911 #define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010U) /*!<Tx FIFO UnderRun Error Interrupt Enable */
6912 #define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020U) /*!<Rx FIFO OverRun Error Interrupt Enable */
6913 #define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040U) /*!<Command Response Received Interrupt Enable */
6914 #define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080U) /*!<Command Sent Interrupt Enable */
6915 #define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100U) /*!<Data End Interrupt Enable */
6916 #define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400U) /*!<Data Block End Interrupt Enable */
6917 #define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800U) /*!<CCommand Acting Interrupt Enable */
6918 #define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000U) /*!<Data Transmit Acting Interrupt Enable */
6919 #define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000U) /*!<Data receive acting interrupt enabled */
6920 #define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000U) /*!<Tx FIFO Half Empty interrupt Enable */
6921 #define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000U) /*!<Rx FIFO Half Full interrupt Enable */
6922 #define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000U) /*!<Tx FIFO Full interrupt Enable */
6923 #define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000U) /*!<Rx FIFO Full interrupt Enable */
6924 #define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000U) /*!<Tx FIFO Empty interrupt Enable */
6925 #define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000U) /*!<Rx FIFO Empty interrupt Enable */
6926 #define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000U) /*!<Data available in Tx FIFO interrupt Enable */
6927 #define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000U) /*!<Data available in Rx FIFO interrupt Enable */
6928 #define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000U) /*!<SDIO Mode Interrupt Received interrupt Enable */
6929
6930 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
6931 #define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFFU) /*!<Remaining number of words to be written to or read from the FIFO */
6932
6933 /****************** Bit definition for SDMMC_FIFO register *******************/
6934 #define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFFU) /*!<Receive and transmit FIFO data */
6935
6936 /******************************************************************************/
6937 /* */
6938 /* Serial Peripheral Interface (SPI) */
6939 /* */
6940 /******************************************************************************/
6941 /******************* Bit definition for SPI_CR1 register ********************/
6942 #define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!<Clock Phase */
6943 #define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!<Clock Polarity */
6944 #define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!<Master Selection */
6945
6946 #define SPI_CR1_BR ((uint32_t)0x00000038U) /*!<BR[2:0] bits (Baud Rate Control) */
6947 #define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
6948 #define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
6949 #define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
6950
6951 #define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!<SPI Enable */
6952 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!<Frame Format */
6953 #define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!<Internal slave select */
6954 #define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!<Software slave management */
6955 #define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!<Receive only */
6956 #define SPI_CR1_CRCL ((uint32_t)0x00000800U) /*!< CRC Length */
6957 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!<Transmit CRC next */
6958 #define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!<Hardware CRC calculation enable */
6959 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!<Output enable in bidirectional mode */
6960 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!<Bidirectional data mode enable */
6961
6962 /******************* Bit definition for SPI_CR2 register ********************/
6963 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
6964 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
6965 #define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
6966 #define SPI_CR2_NSSP ((uint32_t)0x00000008U) /*!< NSS pulse management Enable */
6967 #define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */
6968 #define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
6969 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
6970 #define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
6971 #define SPI_CR2_DS ((uint32_t)0x00000F00U) /*!< DS[3:0] Data Size */
6972 #define SPI_CR2_DS_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
6973 #define SPI_CR2_DS_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
6974 #define SPI_CR2_DS_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
6975 #define SPI_CR2_DS_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
6976 #define SPI_CR2_FRXTH ((uint32_t)0x00001000U) /*!< FIFO reception Threshold */
6977 #define SPI_CR2_LDMARX ((uint32_t)0x00002000U) /*!< Last DMA transfer for reception */
6978 #define SPI_CR2_LDMATX ((uint32_t)0x00004000U) /*!< Last DMA transfer for transmission */
6979
6980 /******************** Bit definition for SPI_SR register ********************/
6981 #define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
6982 #define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
6983 #define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
6984 #define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
6985 #define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
6986 #define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
6987 #define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
6988 #define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
6989 #define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */
6990 #define SPI_SR_FRLVL ((uint32_t)0x00000600U) /*!< FIFO Reception Level */
6991 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
6992 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
6993 #define SPI_SR_FTLVL ((uint32_t)0x00001800U) /*!< FIFO Transmission Level */
6994 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
6995 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
6996
6997 /******************** Bit definition for SPI_DR register ********************/
6998 #define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!<Data Register */
6999
7000 /******************* Bit definition for SPI_CRCPR register ******************/
7001 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!<CRC polynomial register */
7002
7003 /****************** Bit definition for SPI_RXCRCR register ******************/
7004 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!<Rx CRC Register */
7005
7006 /****************** Bit definition for SPI_TXCRCR register ******************/
7007 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!<Tx CRC Register */
7008
7009 /******************************************************************************/
7010 /* */
7011 /* QUADSPI */
7012 /* */
7013 /******************************************************************************/
7014 /***************** Bit definition for QUADSPI_CR register *******************/
7015 #define QUADSPI_CR_EN ((uint32_t)0x00000001U) /*!< Enable */
7016 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002U) /*!< Abort request */
7017 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004U) /*!< DMA Enable */
7018 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008U) /*!< Timeout Counter Enable */
7019 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010U) /*!< Sample Shift */
7020 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00U) /*!< FTHRES[3:0] FIFO Level */
7021 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000U) /*!< Transfer Error Interrupt Enable */
7022 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000U) /*!< Transfer Complete Interrupt Enable */
7023 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000U) /*!< FIFO Threshold Interrupt Enable */
7024 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000U) /*!< Status Match Interrupt Enable */
7025 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000U) /*!< TimeOut Interrupt Enable */
7026 #define QUADSPI_CR_APMS ((uint32_t)0x00400000U) /*!< Automatic Polling Mode Stop */
7027 #define QUADSPI_CR_PMM ((uint32_t)0x00800000U) /*!< Polling Match Mode */
7028 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000U) /*!< PRESCALER[7:0] Clock prescaler */
7029
7030 /***************** Bit definition for QUADSPI_DCR register ******************/
7031 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001U) /*!< Mode 0 / Mode 3 */
7032 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700U) /*!< CSHT[2:0]: ChipSelect High Time */
7033 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
7034 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
7035 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
7036 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000U) /*!< FSIZE[4:0]: Flash Size */
7037
7038 /****************** Bit definition for QUADSPI_SR register *******************/
7039 #define QUADSPI_SR_TEF ((uint32_t)0x00000001U) /*!< Transfer Error Flag */
7040 #define QUADSPI_SR_TCF ((uint32_t)0x00000002U) /*!< Transfer Complete Flag */
7041 #define QUADSPI_SR_FTF ((uint32_t)0x00000004U) /*!< FIFO Threshlod Flag */
7042 #define QUADSPI_SR_SMF ((uint32_t)0x00000008U) /*!< Status Match Flag */
7043 #define QUADSPI_SR_TOF ((uint32_t)0x00000010U) /*!< Timeout Flag */
7044 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020U) /*!< Busy */
7045 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00U) /*!< FIFO Threshlod Flag */
7046
7047 /****************** Bit definition for QUADSPI_FCR register ******************/
7048 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001U) /*!< Clear Transfer Error Flag */
7049 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002U) /*!< Clear Transfer Complete Flag */
7050 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008U) /*!< Clear Status Match Flag */
7051 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010U) /*!< Clear Timeout Flag */
7052
7053 /****************** Bit definition for QUADSPI_DLR register ******************/
7054 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFFU) /*!< DL[31:0]: Data Length */
7055
7056 /****************** Bit definition for QUADSPI_CCR register ******************/
7057 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FFU) /*!< INSTRUCTION[7:0]: Instruction */
7058 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300U) /*!< IMODE[1:0]: Instruction Mode */
7059 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
7060 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
7061 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00U) /*!< ADMODE[1:0]: Address Mode */
7062 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
7063 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
7064 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000U) /*!< ADSIZE[1:0]: Address Size */
7065 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
7066 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
7067 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000U) /*!< ABMODE[1:0]: Alternate Bytes Mode */
7068 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000U) /*!< Bit 0 */
7069 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000U) /*!< Bit 1 */
7070 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000U) /*!< ABSIZE[1:0]: Instruction Mode */
7071 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
7072 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
7073 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000U) /*!< DCYC[4:0]: Dummy Cycles */
7074 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000U) /*!< DMODE[1:0]: Data Mode */
7075 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
7076 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
7077 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000U) /*!< FMODE[1:0]: Functional Mode */
7078 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
7079 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
7080 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000U) /*!< SIOO: Send Instruction Only Once Mode */
7081 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000U) /*!< DDRM: Double Data Rate Mode */
7082
7083 /****************** Bit definition for QUADSPI_AR register *******************/
7084 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFFU) /*!< ADDRESS[31:0]: Address */
7085
7086 /****************** Bit definition for QUADSPI_ABR register ******************/
7087 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFFU) /*!< ALTERNATE[31:0]: Alternate Bytes */
7088
7089 /****************** Bit definition for QUADSPI_DR register *******************/
7090 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFFU) /*!< DATA[31:0]: Data */
7091
7092 /****************** Bit definition for QUADSPI_PSMKR register ****************/
7093 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFFU) /*!< MASK[31:0]: Status Mask */
7094
7095 /****************** Bit definition for QUADSPI_PSMAR register ****************/
7096 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFFU) /*!< MATCH[31:0]: Status Match */
7097
7098 /****************** Bit definition for QUADSPI_PIR register *****************/
7099 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFFU) /*!< INTERVAL[15:0]: Polling Interval */
7100
7101 /****************** Bit definition for QUADSPI_LPTR register *****************/
7102 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< TIMEOUT[15:0]: Timeout period */
7103
7104 /******************************************************************************/
7105 /* */
7106 /* SYSCFG */
7107 /* */
7108 /******************************************************************************/
7109 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
7110 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
7111 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001U)
7112 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002U)
7113 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004U)
7114
7115 #define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100U) /*!< Flash Bank mode selection */
7116
7117
7118 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
7119 #define SYSCFG_CFGR1_FWDIS ((uint32_t)0x00000001U) /*!< FIREWALL access enable*/
7120 #define SYSCFG_CFGR1_BOOSTEN ((uint32_t)0x00000100U) /*!< I/O analog switch voltage booster enable */
7121 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000U) /*!< I2C PB6 Fast mode plus */
7122 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000U) /*!< I2C PB7 Fast mode plus */
7123 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000U) /*!< I2C PB8 Fast mode plus */
7124 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000U) /*!< I2C PB9 Fast mode plus */
7125 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000U) /*!< I2C1 Fast mode plus */
7126 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000U) /*!< I2C2 Fast mode plus */
7127 #define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x00400000U) /*!< I2C3 Fast mode plus */
7128 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000U) /*!< Invalid operation Interrupt enable */
7129 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000U) /*!< Divide-by-zero Interrupt enable */
7130 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000U) /*!< Underflow Interrupt enable */
7131 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000U) /*!< Overflow Interrupt enable */
7132 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000U) /*!< Input denormal Interrupt enable */
7133 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
7134
7135 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
7136 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x00000007U) /*!<EXTI 0 configuration */
7137 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00000070U) /*!<EXTI 1 configuration */
7138 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000700U) /*!<EXTI 2 configuration */
7139 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x00007000U) /*!<EXTI 3 configuration */
7140 /**
7141 * @brief EXTI0 configuration
7142 */
7143 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!<PA[0] pin */
7144 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!<PB[0] pin */
7145 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!<PC[0] pin */
7146 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003U) /*!<PD[0] pin */
7147 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004U) /*!<PE[0] pin */
7148 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005U) /*!<PF[0] pin */
7149 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006U) /*!<PG[0] pin */
7150 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007U) /*!<PH[0] pin */
7151
7152
7153 /**
7154 * @brief EXTI1 configuration
7155 */
7156 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!<PA[1] pin */
7157 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!<PB[1] pin */
7158 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!<PC[1] pin */
7159 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030U) /*!<PD[1] pin */
7160 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040U) /*!<PE[1] pin */
7161 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050U) /*!<PF[1] pin */
7162 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060U) /*!<PG[1] pin */
7163 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070U) /*!<PH[1] pin */
7164
7165 /**
7166 * @brief EXTI2 configuration
7167 */
7168 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!<PA[2] pin */
7169 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!<PB[2] pin */
7170 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!<PC[2] pin */
7171 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!<PD[2] pin */
7172 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400U) /*!<PE[2] pin */
7173 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500U) /*!<PF[2] pin */
7174 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600U) /*!<PG[2] pin */
7175
7176
7177 /**
7178 * @brief EXTI3 configuration
7179 */
7180 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!<PA[3] pin */
7181 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!<PB[3] pin */
7182 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!<PC[3] pin */
7183 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000U) /*!<PD[3] pin */
7184 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000U) /*!<PE[3] pin */
7185 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000U) /*!<PF[3] pin */
7186 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000U) /*!<PG[3] pin */
7187
7188
7189 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
7190 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x00000007U) /*!<EXTI 4 configuration */
7191 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00000070U) /*!<EXTI 5 configuration */
7192 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000700U) /*!<EXTI 6 configuration */
7193 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x00007000U) /*!<EXTI 7 configuration */
7194 /**
7195 * @brief EXTI4 configuration
7196 */
7197 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!<PA[4] pin */
7198 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!<PB[4] pin */
7199 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!<PC[4] pin */
7200 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003U) /*!<PD[4] pin */
7201 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004U) /*!<PE[4] pin */
7202 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005U) /*!<PF[4] pin */
7203 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006U) /*!<PG[4] pin */
7204
7205 /**
7206 * @brief EXTI5 configuration
7207 */
7208 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!<PA[5] pin */
7209 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!<PB[5] pin */
7210 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!<PC[5] pin */
7211 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030U) /*!<PD[5] pin */
7212 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040U) /*!<PE[5] pin */
7213 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050U) /*!<PF[5] pin */
7214 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060U) /*!<PG[5] pin */
7215
7216 /**
7217 * @brief EXTI6 configuration
7218 */
7219 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!<PA[6] pin */
7220 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!<PB[6] pin */
7221 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!<PC[6] pin */
7222 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300U) /*!<PD[6] pin */
7223 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400U) /*!<PE[6] pin */
7224 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500U) /*!<PF[6] pin */
7225 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600U) /*!<PG[6] pin */
7226
7227 /**
7228 * @brief EXTI7 configuration
7229 */
7230 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!<PA[7] pin */
7231 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!<PB[7] pin */
7232 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!<PC[7] pin */
7233 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000U) /*!<PD[7] pin */
7234 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000U) /*!<PE[7] pin */
7235 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000U) /*!<PF[7] pin */
7236 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000U) /*!<PG[7] pin */
7237
7238
7239 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
7240 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x00000007U) /*!<EXTI 8 configuration */
7241 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00000070U) /*!<EXTI 9 configuration */
7242 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000700U) /*!<EXTI 10 configuration */
7243 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x00007000U) /*!<EXTI 11 configuration */
7244
7245 /**
7246 * @brief EXTI8 configuration
7247 */
7248 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!<PA[8] pin */
7249 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!<PB[8] pin */
7250 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!<PC[8] pin */
7251 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003U) /*!<PD[8] pin */
7252 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004U) /*!<PE[8] pin */
7253 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005U) /*!<PF[8] pin */
7254 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006U) /*!<PG[8] pin */
7255
7256 /**
7257 * @brief EXTI9 configuration
7258 */
7259 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!<PA[9] pin */
7260 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!<PB[9] pin */
7261 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!<PC[9] pin */
7262 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030U) /*!<PD[9] pin */
7263 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040U) /*!<PE[9] pin */
7264 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050U) /*!<PF[9] pin */
7265 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060U) /*!<PG[9] pin */
7266
7267 /**
7268 * @brief EXTI10 configuration
7269 */
7270 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!<PA[10] pin */
7271 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!<PB[10] pin */
7272 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!<PC[10] pin */
7273 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300U) /*!<PD[10] pin */
7274 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400U) /*!<PE[10] pin */
7275 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500U) /*!<PF[10] pin */
7276 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600U) /*!<PG[10] pin */
7277
7278 /**
7279 * @brief EXTI11 configuration
7280 */
7281 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!<PA[11] pin */
7282 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!<PB[11] pin */
7283 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!<PC[11] pin */
7284 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000U) /*!<PD[11] pin */
7285 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000U) /*!<PE[11] pin */
7286 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000U) /*!<PF[11] pin */
7287 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000U) /*!<PG[11] pin */
7288
7289 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7290 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x00000007U) /*!<EXTI 12 configuration */
7291 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00000070U) /*!<EXTI 13 configuration */
7292 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000700U) /*!<EXTI 14 configuration */
7293 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x00007000U) /*!<EXTI 15 configuration */
7294 /**
7295 * @brief EXTI12 configuration
7296 */
7297 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!<PA[12] pin */
7298 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!<PB[12] pin */
7299 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!<PC[12] pin */
7300 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003U) /*!<PD[12] pin */
7301 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004U) /*!<PE[12] pin */
7302 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005U) /*!<PF[12] pin */
7303 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006U) /*!<PG[12] pin */
7304
7305 /**
7306 * @brief EXTI13 configuration
7307 */
7308 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!<PA[13] pin */
7309 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!<PB[13] pin */
7310 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!<PC[13] pin */
7311 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030U) /*!<PD[13] pin */
7312 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040U) /*!<PE[13] pin */
7313 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050U) /*!<PF[13] pin */
7314 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060U) /*!<PG[13] pin */
7315
7316 /**
7317 * @brief EXTI14 configuration
7318 */
7319 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!<PA[14] pin */
7320 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!<PB[14] pin */
7321 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!<PC[14] pin */
7322 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300U) /*!<PD[14] pin */
7323 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400U) /*!<PE[14] pin */
7324 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500U) /*!<PF[14] pin */
7325 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600U) /*!<PG[14] pin */
7326
7327 /**
7328 * @brief EXTI15 configuration
7329 */
7330 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!<PA[15] pin */
7331 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!<PB[15] pin */
7332 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!<PC[15] pin */
7333 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000U) /*!<PD[15] pin */
7334 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000U) /*!<PE[15] pin */
7335 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000U) /*!<PF[15] pin */
7336 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000U) /*!<PG[15] pin */
7337
7338 /****************** Bit definition for SYSCFG_SCSR register ****************/
7339 #define SYSCFG_SCSR_SRAM2ER ((uint32_t)0x00000001U) /*!< SRAM2 Erase Request */
7340 #define SYSCFG_SCSR_SRAM2BSY ((uint32_t)0x00000002U) /*!< SRAM2 Erase Ongoing */
7341
7342 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
7343 #define SYSCFG_CFGR2_CLL ((uint32_t)0x00000001U) /*!< Core Lockup Lock */
7344 #define SYSCFG_CFGR2_SPL ((uint32_t)0x00000002U) /*!< SRAM Parity Lock*/
7345 #define SYSCFG_CFGR2_PVDL ((uint32_t)0x00000004U) /*!< PVD Lock */
7346 #define SYSCFG_CFGR2_ECCL ((uint32_t)0x00000008U) /*!< ECC Lock*/
7347 #define SYSCFG_CFGR2_SPF ((uint32_t)0x00000100U) /*!< SRAM Parity Flag */
7348
7349 /****************** Bit definition for SYSCFG_SWPR register ****************/
7350 #define SYSCFG_SWPR_PAGE0 ((uint32_t)0x00000001U) /*!< SRAM2 Write protection page 0 */
7351 #define SYSCFG_SWPR_PAGE1 ((uint32_t)0x00000002U) /*!< SRAM2 Write protection page 1 */
7352 #define SYSCFG_SWPR_PAGE2 ((uint32_t)0x00000004U) /*!< SRAM2 Write protection page 2 */
7353 #define SYSCFG_SWPR_PAGE3 ((uint32_t)0x00000008U) /*!< SRAM2 Write protection page 3 */
7354 #define SYSCFG_SWPR_PAGE4 ((uint32_t)0x00000010U) /*!< SRAM2 Write protection page 4 */
7355 #define SYSCFG_SWPR_PAGE5 ((uint32_t)0x00000020U) /*!< SRAM2 Write protection page 5 */
7356 #define SYSCFG_SWPR_PAGE6 ((uint32_t)0x00000040U) /*!< SRAM2 Write protection page 6 */
7357 #define SYSCFG_SWPR_PAGE7 ((uint32_t)0x00000080U) /*!< SRAM2 Write protection page 7 */
7358 #define SYSCFG_SWPR_PAGE8 ((uint32_t)0x00000100U) /*!< SRAM2 Write protection page 8 */
7359 #define SYSCFG_SWPR_PAGE9 ((uint32_t)0x00000200U) /*!< SRAM2 Write protection page 9 */
7360 #define SYSCFG_SWPR_PAGE10 ((uint32_t)0x00000400U) /*!< SRAM2 Write protection page 10*/
7361 #define SYSCFG_SWPR_PAGE11 ((uint32_t)0x00000800U) /*!< SRAM2 Write protection page 11*/
7362 #define SYSCFG_SWPR_PAGE12 ((uint32_t)0x00001000U) /*!< SRAM2 Write protection page 12*/
7363 #define SYSCFG_SWPR_PAGE13 ((uint32_t)0x00002000U) /*!< SRAM2 Write protection page 13*/
7364 #define SYSCFG_SWPR_PAGE14 ((uint32_t)0x00004000U) /*!< SRAM2 Write protection page 14*/
7365 #define SYSCFG_SWPR_PAGE15 ((uint32_t)0x00008000U) /*!< SRAM2 Write protection page 15*/
7366 #define SYSCFG_SWPR_PAGE16 ((uint32_t)0x00010000U) /*!< SRAM2 Write protection page 16*/
7367 #define SYSCFG_SWPR_PAGE17 ((uint32_t)0x00020000U) /*!< SRAM2 Write protection page 17*/
7368 #define SYSCFG_SWPR_PAGE18 ((uint32_t)0x00040000U) /*!< SRAM2 Write protection page 18*/
7369 #define SYSCFG_SWPR_PAGE19 ((uint32_t)0x00080000U) /*!< SRAM2 Write protection page 19*/
7370 #define SYSCFG_SWPR_PAGE20 ((uint32_t)0x00100000U) /*!< SRAM2 Write protection page 20*/
7371 #define SYSCFG_SWPR_PAGE21 ((uint32_t)0x00200000U) /*!< SRAM2 Write protection page 21*/
7372 #define SYSCFG_SWPR_PAGE22 ((uint32_t)0x00400000U) /*!< SRAM2 Write protection page 22*/
7373 #define SYSCFG_SWPR_PAGE23 ((uint32_t)0x00800000U) /*!< SRAM2 Write protection page 23*/
7374 #define SYSCFG_SWPR_PAGE24 ((uint32_t)0x01000000U) /*!< SRAM2 Write protection page 24*/
7375 #define SYSCFG_SWPR_PAGE25 ((uint32_t)0x02000000U) /*!< SRAM2 Write protection page 25*/
7376 #define SYSCFG_SWPR_PAGE26 ((uint32_t)0x04000000U) /*!< SRAM2 Write protection page 26*/
7377 #define SYSCFG_SWPR_PAGE27 ((uint32_t)0x08000000U) /*!< SRAM2 Write protection page 27*/
7378 #define SYSCFG_SWPR_PAGE28 ((uint32_t)0x10000000U) /*!< SRAM2 Write protection page 28*/
7379 #define SYSCFG_SWPR_PAGE29 ((uint32_t)0x20000000U) /*!< SRAM2 Write protection page 29*/
7380 #define SYSCFG_SWPR_PAGE30 ((uint32_t)0x40000000U) /*!< SRAM2 Write protection page 30*/
7381 #define SYSCFG_SWPR_PAGE31 ((uint32_t)0x80000000U) /*!< SRAM2 Write protection page 31*/
7382
7383 /****************** Bit definition for SYSCFG_SKR register ****************/
7384 #define SYSCFG_SKR_KEY ((uint32_t)0x000000FFU) /*!< SRAM2 write protection key for software erase */
7385
7386
7387
7388
7389 /******************************************************************************/
7390 /* */
7391 /* TIM */
7392 /* */
7393 /******************************************************************************/
7394 /******************* Bit definition for TIM_CR1 register ********************/
7395 #define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
7396 #define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
7397 #define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
7398 #define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
7399 #define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
7400
7401 #define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
7402 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
7403 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
7404
7405 #define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
7406
7407 #define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
7408 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7409 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7410
7411 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800U) /*!<Update interrupt flag remap */
7412
7413 /******************* Bit definition for TIM_CR2 register ********************/
7414 #define TIM_CR2_CCPC ((uint32_t)0x00000001U) /*!<Capture/Compare Preloaded Control */
7415 #define TIM_CR2_CCUS ((uint32_t)0x00000004U) /*!<Capture/Compare Control Update Selection */
7416 #define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
7417
7418 #define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
7419 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7420 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7421 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7422
7423 #define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
7424 #define TIM_CR2_OIS1 ((uint32_t)0x00000100U) /*!<Output Idle state 1 (OC1 output) */
7425 #define TIM_CR2_OIS1N ((uint32_t)0x00000200U) /*!<Output Idle state 1 (OC1N output) */
7426 #define TIM_CR2_OIS2 ((uint32_t)0x00000400U) /*!<Output Idle state 2 (OC2 output) */
7427 #define TIM_CR2_OIS2N ((uint32_t)0x00000800U) /*!<Output Idle state 2 (OC2N output) */
7428 #define TIM_CR2_OIS3 ((uint32_t)0x00001000U) /*!<Output Idle state 3 (OC3 output) */
7429 #define TIM_CR2_OIS3N ((uint32_t)0x00002000U) /*!<Output Idle state 3 (OC3N output) */
7430 #define TIM_CR2_OIS4 ((uint32_t)0x00004000U) /*!<Output Idle state 4 (OC4 output) */
7431 #define TIM_CR2_OIS5 ((uint32_t)0x00010000U) /*!<Output Idle state 5 (OC5 output) */
7432 #define TIM_CR2_OIS6 ((uint32_t)0x00040000U) /*!<Output Idle state 6 (OC6 output) */
7433
7434 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000U) /*!<MMS[2:0] bits (Master Mode Selection) */
7435 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
7436 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
7437 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
7438 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000U) /*!<Bit 2 */
7439
7440 /******************* Bit definition for TIM_SMCR register *******************/
7441 #define TIM_SMCR_SMS ((uint32_t)0x00010007U) /*!<SMS[2:0] bits (Slave mode selection) */
7442 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7443 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7444 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
7445 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
7446
7447 #define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
7448
7449 #define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
7450 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7451 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7452 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7453
7454 #define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
7455
7456 #define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
7457 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7458 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7459 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
7460 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
7461
7462 #define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
7463 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7464 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7465
7466 #define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
7467 #define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
7468
7469 /******************* Bit definition for TIM_DIER register *******************/
7470 #define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
7471 #define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
7472 #define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
7473 #define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
7474 #define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
7475 #define TIM_DIER_COMIE ((uint32_t)0x00000020U) /*!<COM interrupt enable */
7476 #define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
7477 #define TIM_DIER_BIE ((uint32_t)0x00000080U) /*!<Break interrupt enable */
7478 #define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
7479 #define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
7480 #define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
7481 #define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
7482 #define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
7483 #define TIM_DIER_COMDE ((uint32_t)0x00002000U) /*!<COM DMA request enable */
7484 #define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
7485
7486 /******************** Bit definition for TIM_SR register ********************/
7487 #define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
7488 #define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
7489 #define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
7490 #define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
7491 #define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
7492 #define TIM_SR_COMIF ((uint32_t)0x00000020U) /*!<COM interrupt Flag */
7493 #define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
7494 #define TIM_SR_BIF ((uint32_t)0x00000080U) /*!<Break interrupt Flag */
7495 #define TIM_SR_B2IF ((uint32_t)0x00000100U) /*!<Break 2 interrupt Flag */
7496 #define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
7497 #define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
7498 #define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
7499 #define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
7500 #define TIM_SR_SBIF ((uint32_t)0x00002000U) /*!<System Break interrupt Flag */
7501 #define TIM_SR_CC5IF ((uint32_t)0x00010000U) /*!<Capture/Compare 5 interrupt Flag */
7502 #define TIM_SR_CC6IF ((uint32_t)0x00020000U) /*!<Capture/Compare 6 interrupt Flag */
7503
7504
7505 /******************* Bit definition for TIM_EGR register ********************/
7506 #define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
7507 #define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
7508 #define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
7509 #define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
7510 #define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
7511 #define TIM_EGR_COMG ((uint32_t)0x00000020U) /*!<Capture/Compare Control Update Generation */
7512 #define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
7513 #define TIM_EGR_BG ((uint32_t)0x00000080U) /*!<Break Generation */
7514 #define TIM_EGR_B2G ((uint32_t)0x00000100U) /*!<Break 2 Generation */
7515
7516
7517 /****************** Bit definition for TIM_CCMR1 register *******************/
7518 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7519 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7520 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7521
7522 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
7523 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
7524
7525 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7526 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7527 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7528 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7529 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
7530
7531 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1 Clear Enable */
7532
7533 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7534 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7535 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7536
7537 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
7538 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
7539
7540 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7541 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7542 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7543 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
7544 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
7545
7546 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
7547
7548 /*----------------------------------------------------------------------------*/
7549 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7550 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
7551 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
7552
7553 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7554 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7555 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7556 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7557 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
7558
7559 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7560 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
7561 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
7562
7563 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7564 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7565 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7566 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
7567 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
7568
7569 /****************** Bit definition for TIM_CCMR2 register *******************/
7570 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7571 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7572 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7573
7574 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
7575 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
7576
7577 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7578 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7579 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7580 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7581 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
7582
7583 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
7584
7585 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7586 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7587 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7588
7589 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
7590 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
7591
7592 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7593 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7594 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7595 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
7596 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
7597
7598 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
7599
7600 /*----------------------------------------------------------------------------*/
7601 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7602 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
7603 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
7604
7605 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7606 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7607 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7608 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7609 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
7610
7611 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7612 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
7613 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
7614
7615 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7616 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7617 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7618 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
7619 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
7620
7621 /****************** Bit definition for TIM_CCMR3 register *******************/
7622 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004U) /*!<Output Compare 5 Fast enable */
7623 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008U) /*!<Output Compare 5 Preload enable */
7624
7625 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070U) /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
7626 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7627 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7628 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7629 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
7630
7631 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080U) /*!<Output Compare 5 Clear Enable */
7632
7633 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400U) /*!<Output Compare 6 Fast enable */
7634 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800U) /*!<Output Compare 6 Preload enable */
7635
7636 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000U) /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
7637 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7638 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7639 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
7640 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
7641
7642 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000U) /*!<Output Compare 6 Clear Enable */
7643
7644 /******************* Bit definition for TIM_CCER register *******************/
7645 #define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
7646 #define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
7647 #define TIM_CCER_CC1NE ((uint32_t)0x00000004U) /*!<Capture/Compare 1 Complementary output enable */
7648 #define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
7649 #define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
7650 #define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
7651 #define TIM_CCER_CC2NE ((uint32_t)0x00000040U) /*!<Capture/Compare 2 Complementary output enable */
7652 #define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
7653 #define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
7654 #define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
7655 #define TIM_CCER_CC3NE ((uint32_t)0x00000400U) /*!<Capture/Compare 3 Complementary output enable */
7656 #define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
7657 #define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
7658 #define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
7659 #define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
7660 #define TIM_CCER_CC5E ((uint32_t)0x00010000U) /*!<Capture/Compare 5 output enable */
7661 #define TIM_CCER_CC5P ((uint32_t)0x00020000U) /*!<Capture/Compare 5 output Polarity */
7662 #define TIM_CCER_CC6E ((uint32_t)0x00100000U) /*!<Capture/Compare 6 output enable */
7663 #define TIM_CCER_CC6P ((uint32_t)0x00200000U) /*!<Capture/Compare 6 output Polarity */
7664
7665 /******************* Bit definition for TIM_CNT register ********************/
7666 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFFU) /*!<Counter Value */
7667 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000U) /*!<Update interrupt flag copy (if UIFREMAP=1) */
7668
7669 /******************* Bit definition for TIM_PSC register ********************/
7670 #define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
7671
7672 /******************* Bit definition for TIM_ARR register ********************/
7673 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFFU) /*!<Actual auto-reload Value */
7674
7675 /******************* Bit definition for TIM_RCR register ********************/
7676 #define TIM_RCR_REP ((uint32_t)0x0000FFFFU) /*!<Repetition Counter Value */
7677
7678 /******************* Bit definition for TIM_CCR1 register *******************/
7679 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
7680
7681 /******************* Bit definition for TIM_CCR2 register *******************/
7682 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
7683
7684 /******************* Bit definition for TIM_CCR3 register *******************/
7685 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
7686
7687 /******************* Bit definition for TIM_CCR4 register *******************/
7688 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
7689
7690 /******************* Bit definition for TIM_CCR5 register *******************/
7691 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFFU) /*!<Capture/Compare 5 Value */
7692 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000U) /*!<Group Channel 5 and Channel 1 */
7693 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000U) /*!<Group Channel 5 and Channel 2 */
7694 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000U) /*!<Group Channel 5 and Channel 3 */
7695
7696 /******************* Bit definition for TIM_CCR6 register *******************/
7697 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 6 Value */
7698
7699 /******************* Bit definition for TIM_BDTR register *******************/
7700 #define TIM_BDTR_DTG ((uint32_t)0x000000FFU) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7701 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7702 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7703 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
7704 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
7705 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
7706 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
7707 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
7708 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
7709
7710 #define TIM_BDTR_LOCK ((uint32_t)0x00000300U) /*!<LOCK[1:0] bits (Lock Configuration) */
7711 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7712 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7713
7714 #define TIM_BDTR_OSSI ((uint32_t)0x00000400U) /*!<Off-State Selection for Idle mode */
7715 #define TIM_BDTR_OSSR ((uint32_t)0x00000800U) /*!<Off-State Selection for Run mode */
7716 #define TIM_BDTR_BKE ((uint32_t)0x00001000U) /*!<Break enable for Break 1 */
7717 #define TIM_BDTR_BKP ((uint32_t)0x00002000U) /*!<Break Polarity for Break 1 */
7718 #define TIM_BDTR_AOE ((uint32_t)0x00004000U) /*!<Automatic Output enable */
7719 #define TIM_BDTR_MOE ((uint32_t)0x00008000U) /*!<Main Output enable */
7720
7721 #define TIM_BDTR_BKF ((uint32_t)0x000F0000U) /*!<Break Filter for Break 1 */
7722 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000U) /*!<Break Filter for Break 2 */
7723
7724 #define TIM_BDTR_BK2E ((uint32_t)0x01000000U) /*!<Break enable for Break 2 */
7725 #define TIM_BDTR_BK2P ((uint32_t)0x02000000U) /*!<Break Polarity for Break 2 */
7726
7727 /******************* Bit definition for TIM_DCR register ********************/
7728 #define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
7729 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7730 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7731 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
7732 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
7733 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
7734
7735 #define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
7736 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7737 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7738 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
7739 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
7740 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
7741
7742 /******************* Bit definition for TIM_DMAR register *******************/
7743 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
7744
7745 /******************* Bit definition for TIM1_OR1 register *******************/
7746 #define TIM1_OR1_ETR_ADC1_RMP ((uint32_t)0x00000003U) /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
7747 #define TIM1_OR1_ETR_ADC1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7748 #define TIM1_OR1_ETR_ADC1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7749
7750 #define TIM1_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000CU) /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
7751 #define TIM1_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
7752 #define TIM1_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
7753
7754 #define TIM1_OR1_TI1_RMP ((uint32_t)0x00000010U) /*!<TIM1 Input Capture 1 remap */
7755
7756 /******************* Bit definition for TIM1_OR2 register *******************/
7757 #define TIM1_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
7758 #define TIM1_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
7759 #define TIM1_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
7760 #define TIM1_OR2_BKDFBK0E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[0] enable */
7761 #define TIM1_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
7762 #define TIM1_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
7763 #define TIM1_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
7764
7765 #define TIM1_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
7766 #define TIM1_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
7767 #define TIM1_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
7768 #define TIM1_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
7769
7770 /******************* Bit definition for TIM1_OR3 register *******************/
7771 #define TIM1_OR3_BK2INE ((uint32_t)0x00000001U) /*!<BRK2 BKIN2 input enable */
7772 #define TIM1_OR3_BK2CMP1E ((uint32_t)0x00000002U) /*!<BRK2 COMP1 enable */
7773 #define TIM1_OR3_BK2CMP2E ((uint32_t)0x00000004U) /*!<BRK2 COMP2 enable */
7774 #define TIM1_OR3_BK2DFBK1E ((uint32_t)0x00000100U) /*!<BRK2 DFSDM_BREAK[1] enable */
7775 #define TIM1_OR3_BK2INP ((uint32_t)0x00000200U) /*!<BRK2 BKIN2 input polarity */
7776 #define TIM1_OR3_BK2CMP1P ((uint32_t)0x00000400U) /*!<BRK2 COMP1 input polarity */
7777 #define TIM1_OR3_BK2CMP2P ((uint32_t)0x00000800U) /*!<BRK2 COMP2 input polarity */
7778
7779 /******************* Bit definition for TIM8_OR1 register *******************/
7780 #define TIM8_OR1_ETR_ADC2_RMP ((uint32_t)0x00000003U) /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
7781 #define TIM8_OR1_ETR_ADC2_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7782 #define TIM8_OR1_ETR_ADC2_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7783
7784 #define TIM8_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000CU) /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
7785 #define TIM8_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
7786 #define TIM8_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
7787
7788 #define TIM8_OR1_TI1_RMP ((uint32_t)0x00000010U) /*!<TIM8 Input Capture 1 remap */
7789
7790 /******************* Bit definition for TIM8_OR2 register *******************/
7791 #define TIM8_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
7792 #define TIM8_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
7793 #define TIM8_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
7794 #define TIM8_OR2_BKDFBK2E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[2] enable */
7795 #define TIM8_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
7796 #define TIM8_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
7797 #define TIM8_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
7798
7799 #define TIM8_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
7800 #define TIM8_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
7801 #define TIM8_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
7802 #define TIM8_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
7803
7804 /******************* Bit definition for TIM8_OR3 register *******************/
7805 #define TIM8_OR3_BK2INE ((uint32_t)0x00000001U) /*!<BRK2 BKIN2 input enable */
7806 #define TIM8_OR3_BK2CMP1E ((uint32_t)0x00000002U) /*!<BRK2 COMP1 enable */
7807 #define TIM8_OR3_BK2CMP2E ((uint32_t)0x00000004U) /*!<BRK2 COMP2 enable */
7808 #define TIM8_OR3_BK2DFBK3E ((uint32_t)0x00000100U) /*!<BRK2 DFSDM_BREAK[3] enable */
7809 #define TIM8_OR3_BK2INP ((uint32_t)0x00000200U) /*!<BRK2 BKIN2 input polarity */
7810 #define TIM8_OR3_BK2CMP1P ((uint32_t)0x00000400U) /*!<BRK2 COMP1 input polarity */
7811 #define TIM8_OR3_BK2CMP2P ((uint32_t)0x00000800U) /*!<BRK2 COMP2 input polarity */
7812
7813 /******************* Bit definition for TIM2_OR1 register *******************/
7814 #define TIM2_OR1_ITR1_RMP ((uint32_t)0x00000001U) /*!<TIM2 Internal trigger 1 remap */
7815 #define TIM2_OR1_ETR1_RMP ((uint32_t)0x00000002U) /*!<TIM2 External trigger 1 remap */
7816
7817 #define TIM2_OR1_TI4_RMP ((uint32_t)0x0000000CU) /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
7818 #define TIM2_OR1_TI4_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
7819 #define TIM2_OR1_TI4_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
7820
7821 /******************* Bit definition for TIM2_OR2 register *******************/
7822 #define TIM2_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
7823 #define TIM2_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
7824 #define TIM2_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
7825 #define TIM2_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
7826
7827 /******************* Bit definition for TIM3_OR1 register *******************/
7828 #define TIM3_OR1_TI1_RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
7829 #define TIM3_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7830 #define TIM3_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7831
7832 /******************* Bit definition for TIM3_OR2 register *******************/
7833 #define TIM3_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
7834 #define TIM3_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
7835 #define TIM3_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
7836 #define TIM3_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
7837
7838 /******************* Bit definition for TIM15_OR1 register ******************/
7839 #define TIM15_OR1_TI1_RMP ((uint32_t)0x00000001U) /*!<TIM15 Input Capture 1 remap */
7840
7841 #define TIM15_OR1_ENCODER_MODE ((uint32_t)0x00000006U) /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
7842 #define TIM15_OR1_ENCODER_MODE_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
7843 #define TIM15_OR1_ENCODER_MODE_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
7844
7845 /******************* Bit definition for TIM15_OR2 register ******************/
7846 #define TIM15_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
7847 #define TIM15_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
7848 #define TIM15_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
7849 #define TIM15_OR2_BKDFBK0E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[0] enable */
7850 #define TIM15_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
7851 #define TIM15_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
7852 #define TIM15_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
7853
7854 /******************* Bit definition for TIM16_OR1 register ******************/
7855 #define TIM16_OR1_TI1_RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
7856 #define TIM16_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7857 #define TIM16_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7858
7859 /******************* Bit definition for TIM16_OR2 register ******************/
7860 #define TIM16_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
7861 #define TIM16_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
7862 #define TIM16_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
7863 #define TIM16_OR2_BKDFBK1E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[1] enable */
7864 #define TIM16_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
7865 #define TIM16_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
7866 #define TIM16_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
7867
7868 /******************* Bit definition for TIM17_OR1 register ******************/
7869 #define TIM17_OR1_TI1_RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
7870 #define TIM17_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7871 #define TIM17_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7872
7873 /******************* Bit definition for TIM17_OR2 register ******************/
7874 #define TIM17_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
7875 #define TIM17_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
7876 #define TIM17_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
7877 #define TIM17_OR2_BKDFBK2E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[2] enable */
7878 #define TIM17_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
7879 #define TIM17_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
7880 #define TIM17_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
7881
7882 /******************************************************************************/
7883 /* */
7884 /* Low Power Timer (LPTTIM) */
7885 /* */
7886 /******************************************************************************/
7887 /****************** Bit definition for LPTIM_ISR register *******************/
7888 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */
7889 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */
7890 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */
7891 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */
7892 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */
7893 #define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */
7894 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */
7895
7896 /****************** Bit definition for LPTIM_ICR register *******************/
7897 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */
7898 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */
7899 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */
7900 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */
7901 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */
7902 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */
7903 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */
7904
7905 /****************** Bit definition for LPTIM_IER register ********************/
7906 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */
7907 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */
7908 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */
7909 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */
7910 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */
7911 #define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */
7912 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */
7913
7914 /****************** Bit definition for LPTIM_CFGR register *******************/
7915 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */
7916
7917 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */
7918 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
7919 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
7920
7921 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
7922 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
7923 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
7924
7925 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
7926 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
7927 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
7928
7929 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */
7930 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
7931 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
7932 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
7933
7934 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
7935 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
7936 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
7937 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
7938
7939 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
7940 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
7941 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
7942
7943 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */
7944 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */
7945 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */
7946 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */
7947 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */
7948 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */
7949
7950 /****************** Bit definition for LPTIM_CR register ********************/
7951 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */
7952 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */
7953 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */
7954
7955 /****************** Bit definition for LPTIM_CMP register *******************/
7956 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */
7957
7958 /****************** Bit definition for LPTIM_ARR register *******************/
7959 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */
7960
7961 /****************** Bit definition for LPTIM_CNT register *******************/
7962 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */
7963
7964 /****************** Bit definition for LPTIM_OR register *******************/
7965 #define LPTIM_OR_OR ((uint32_t)0x00000003U) /*!< LPTIMER[1:0] bits (Remap selection) */
7966 #define LPTIM_OR_OR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
7967 #define LPTIM_OR_OR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
7968
7969 /******************************************************************************/
7970 /* */
7971 /* Analog Comparators (COMP) */
7972 /* */
7973 /******************************************************************************/
7974 /********************** Bit definition for COMPx_CSR register ***************/
7975 #define COMP_CSR_EN ((uint32_t)0x00000001U) /*!< COMPx enable */
7976
7977 #define COMP_CSR_PWRMODE ((uint32_t)0x0000000CU) /*!< COMPx power mode */
7978 #define COMP_CSR_PWRMODE_0 ((uint32_t)0x00000004U) /*!< COMPx power mode bit 0 */
7979 #define COMP_CSR_PWRMODE_1 ((uint32_t)0x00000008U) /*!< COMPx power mode bit 1 */
7980
7981 #define COMP_CSR_INMSEL ((uint32_t)0x00000070U) /*!< COMPx inverting input (minus) selection */
7982 #define COMP_CSR_INMSEL_0 ((uint32_t)0x00000010U) /*!< COMPx inverting input (minus) selection bit 0 */
7983 #define COMP_CSR_INMSEL_1 ((uint32_t)0x00000020U) /*!< COMPx inverting input (minus) selection bit 1 */
7984 #define COMP_CSR_INMSEL_2 ((uint32_t)0x00000040U) /*!< COMPx inverting input (minus) selection bit 2 */
7985
7986 #define COMP_CSR_INPSEL ((uint32_t)0x00000080U) /*!< COMPx non inverting input (plus) selection */
7987 #define COMP_CSR_INPSEL_0 ((uint32_t)0x00000080U) /*!< COMPx non inverting input (plus) selection bit 0*/
7988 #define COMP_CSR_WINMODE ((uint32_t)0x00000200U) /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
7989 #define COMP_CSR_POLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */
7990
7991 #define COMP_CSR_HYST ((uint32_t)0x00030000U) /*!< COMPx hysteresis */
7992 #define COMP_CSR_HYST_0 ((uint32_t)0x00010000U) /*!< COMPx hysteresis bit 0 */
7993 #define COMP_CSR_HYST_1 ((uint32_t)0x00020000U) /*!< COMPx hysteresis bit 1 */
7994
7995 #define COMP_CSR_BLANKING ((uint32_t)0x001C0000U) /*!< COMPx blanking source */
7996 #define COMP_CSR_BLANKING_0 ((uint32_t)0x00040000U) /*!< COMPx blanking source bit 0 */
7997 #define COMP_CSR_BLANKING_1 ((uint32_t)0x00080000U) /*!< COMPx blanking source bit 1 */
7998 #define COMP_CSR_BLANKING_2 ((uint32_t)0x00100000U) /*!< COMPx blanking source bit 2 */
7999
8000 #define COMP_CSR_BRGEN ((uint32_t)0x00400000U) /*!< COMPx voltage scaler enable */
8001 #define COMP_CSR_SCALEN ((uint32_t)0x00800000U) /*!< COMPx scaler bridge enable */
8002 #define COMP_CSR_VALUE ((uint32_t)0x40000000U) /*!< COMPx value */
8003 #define COMP_CSR_LOCK ((uint32_t)0x80000000U) /*!< COMPx lock */
8004
8005 /******************************************************************************/
8006 /* */
8007 /* Operational Amplifier (OPAMP) */
8008 /* */
8009 /******************************************************************************/
8010 /********************* Bit definition for OPAMPx_CSR register ***************/
8011 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001U) /*!< OPAMP enable */
8012 #define OPAMP_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier Low Power Mode */
8013
8014 #define OPAMP_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier PGA mode */
8015 #define OPAMP_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
8016 #define OPAMP_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
8017
8018 #define OPAMP_CSR_PGGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier Programmable amplifier gain value */
8019 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
8020 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
8021
8022 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
8023 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
8024 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
8025
8026 #define OPAMP_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
8027 #define OPAMP_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
8028 #define OPAMP_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
8029 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
8030 #define OPAMP_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
8031
8032 /********************* Bit definition for OPAMP1_CSR register ***************/
8033 #define OPAMP1_CSR_OPAEN ((uint32_t)0x00000001U) /*!< Operational amplifier1 Enable */
8034 #define OPAMP1_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier1 Low Power Mode */
8035
8036 #define OPAMP1_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier1 PGA mode */
8037 #define OPAMP1_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
8038 #define OPAMP1_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
8039
8040 #define OPAMP1_CSR_PGAGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier1 Programmable amplifier gain value */
8041 #define OPAMP1_CSR_PGAGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
8042 #define OPAMP1_CSR_PGAGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
8043
8044 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
8045 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
8046 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
8047
8048 #define OPAMP1_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
8049 #define OPAMP1_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
8050 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
8051 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
8052 #define OPAMP1_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
8053 #define OPAMP1_CSR_OPARANGE ((uint32_t)0x80000000U) /*!< Operational amplifiers power supply range for stability */
8054
8055 /********************* Bit definition for OPAMP2_CSR register ***************/
8056 #define OPAMP2_CSR_OPAEN ((uint32_t)0x00000001U) /*!< Operational amplifier2 Enable */
8057 #define OPAMP2_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier2 Low Power Mode */
8058
8059 #define OPAMP2_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier2 PGA mode */
8060 #define OPAMP2_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
8061 #define OPAMP2_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
8062
8063 #define OPAMP2_CSR_PGAGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier2 Programmable amplifier gain value */
8064 #define OPAMP2_CSR_PGAGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
8065 #define OPAMP2_CSR_PGAGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
8066
8067 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
8068 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
8069 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
8070
8071 #define OPAMP2_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
8072 #define OPAMP2_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
8073 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
8074 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
8075 #define OPAMP2_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier2 calibration output */
8076
8077 /******************* Bit definition for OPAMP_OTR register ******************/
8078 #define OPAMP_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8079 #define OPAMP_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8080
8081 /******************* Bit definition for OPAMP1_OTR register ******************/
8082 #define OPAMP1_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8083 #define OPAMP1_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8084
8085 /******************* Bit definition for OPAMP2_OTR register ******************/
8086 #define OPAMP2_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8087 #define OPAMP2_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8088
8089 /******************* Bit definition for OPAMP_LPOTR register ****************/
8090 #define OPAMP_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8091 #define OPAMP_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8092
8093 /******************* Bit definition for OPAMP1_LPOTR register ****************/
8094 #define OPAMP1_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8095 #define OPAMP1_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8096
8097 /******************* Bit definition for OPAMP2_LPOTR register ****************/
8098 #define OPAMP2_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8099 #define OPAMP2_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8100
8101 /******************************************************************************/
8102 /* */
8103 /* Touch Sensing Controller (TSC) */
8104 /* */
8105 /******************************************************************************/
8106 /******************* Bit definition for TSC_CR register *********************/
8107 #define TSC_CR_TSCE ((uint32_t)0x00000001U) /*!<Touch sensing controller enable */
8108 #define TSC_CR_START ((uint32_t)0x00000002U) /*!<Start acquisition */
8109 #define TSC_CR_AM ((uint32_t)0x00000004U) /*!<Acquisition mode */
8110 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /*!<Synchronization pin polarity */
8111 #define TSC_CR_IODEF ((uint32_t)0x00000010U) /*!<IO default mode */
8112
8113 #define TSC_CR_MCV ((uint32_t)0x000000E0U) /*!<MCV[2:0] bits (Max Count Value) */
8114 #define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
8115 #define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
8116 #define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
8117
8118 #define TSC_CR_PGPSC ((uint32_t)0x00007000U) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
8119 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
8120 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
8121 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
8122
8123 #define TSC_CR_SSPSC ((uint32_t)0x00008000U) /*!<Spread Spectrum Prescaler */
8124 #define TSC_CR_SSE ((uint32_t)0x00010000U) /*!<Spread Spectrum Enable */
8125
8126 #define TSC_CR_SSD ((uint32_t)0x00FE0000U) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
8127 #define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
8128 #define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
8129 #define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
8130 #define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
8131 #define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
8132 #define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
8133 #define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
8134
8135 #define TSC_CR_CTPL ((uint32_t)0x0F000000U) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
8136 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
8137 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
8138 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
8139 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
8140
8141 #define TSC_CR_CTPH ((uint32_t)0xF0000000U) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
8142 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
8143 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
8144 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
8145 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /*!<Bit 3 */
8146
8147 /******************* Bit definition for TSC_IER register ********************/
8148 #define TSC_IER_EOAIE ((uint32_t)0x00000001U) /*!<End of acquisition interrupt enable */
8149 #define TSC_IER_MCEIE ((uint32_t)0x00000002U) /*!<Max count error interrupt enable */
8150
8151 /******************* Bit definition for TSC_ICR register ********************/
8152 #define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /*!<End of acquisition interrupt clear */
8153 #define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /*!<Max count error interrupt clear */
8154
8155 /******************* Bit definition for TSC_ISR register ********************/
8156 #define TSC_ISR_EOAF ((uint32_t)0x00000001U) /*!<End of acquisition flag */
8157 #define TSC_ISR_MCEF ((uint32_t)0x00000002U) /*!<Max count error flag */
8158
8159 /******************* Bit definition for TSC_IOHCR register ******************/
8160 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
8161 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
8162 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
8163 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
8164 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
8165 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
8166 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
8167 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
8168 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
8169 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
8170 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
8171 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
8172 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
8173 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
8174 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
8175 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
8176 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
8177 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
8178 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
8179 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
8180 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
8181 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
8182 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
8183 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
8184 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
8185 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
8186 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
8187 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
8188 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
8189 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
8190 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
8191 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
8192
8193 /******************* Bit definition for TSC_IOASCR register *****************/
8194 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 analog switch enable */
8195 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 analog switch enable */
8196 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 analog switch enable */
8197 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 analog switch enable */
8198 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 analog switch enable */
8199 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 analog switch enable */
8200 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 analog switch enable */
8201 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 analog switch enable */
8202 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 analog switch enable */
8203 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 analog switch enable */
8204 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 analog switch enable */
8205 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 analog switch enable */
8206 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 analog switch enable */
8207 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 analog switch enable */
8208 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 analog switch enable */
8209 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 analog switch enable */
8210 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 analog switch enable */
8211 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 analog switch enable */
8212 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 analog switch enable */
8213 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 analog switch enable */
8214 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 analog switch enable */
8215 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 analog switch enable */
8216 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 analog switch enable */
8217 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 analog switch enable */
8218 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 analog switch enable */
8219 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 analog switch enable */
8220 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 analog switch enable */
8221 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 analog switch enable */
8222 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 analog switch enable */
8223 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 analog switch enable */
8224 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 analog switch enable */
8225 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 analog switch enable */
8226
8227 /******************* Bit definition for TSC_IOSCR register ******************/
8228 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 sampling mode */
8229 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 sampling mode */
8230 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 sampling mode */
8231 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 sampling mode */
8232 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 sampling mode */
8233 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 sampling mode */
8234 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 sampling mode */
8235 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 sampling mode */
8236 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 sampling mode */
8237 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 sampling mode */
8238 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 sampling mode */
8239 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 sampling mode */
8240 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 sampling mode */
8241 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 sampling mode */
8242 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 sampling mode */
8243 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 sampling mode */
8244 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 sampling mode */
8245 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 sampling mode */
8246 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 sampling mode */
8247 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 sampling mode */
8248 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 sampling mode */
8249 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 sampling mode */
8250 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 sampling mode */
8251 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 sampling mode */
8252 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 sampling mode */
8253 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 sampling mode */
8254 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 sampling mode */
8255 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 sampling mode */
8256 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 sampling mode */
8257 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 sampling mode */
8258 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 sampling mode */
8259 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 sampling mode */
8260
8261 /******************* Bit definition for TSC_IOCCR register ******************/
8262 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 channel mode */
8263 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 channel mode */
8264 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 channel mode */
8265 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 channel mode */
8266 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 channel mode */
8267 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 channel mode */
8268 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 channel mode */
8269 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 channel mode */
8270 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 channel mode */
8271 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 channel mode */
8272 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 channel mode */
8273 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 channel mode */
8274 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 channel mode */
8275 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 channel mode */
8276 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 channel mode */
8277 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 channel mode */
8278 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 channel mode */
8279 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 channel mode */
8280 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 channel mode */
8281 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 channel mode */
8282 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 channel mode */
8283 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 channel mode */
8284 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 channel mode */
8285 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 channel mode */
8286 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 channel mode */
8287 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 channel mode */
8288 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 channel mode */
8289 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 channel mode */
8290 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 channel mode */
8291 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 channel mode */
8292 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 channel mode */
8293 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 channel mode */
8294
8295 /******************* Bit definition for TSC_IOGCSR register *****************/
8296 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /*!<Analog IO GROUP1 enable */
8297 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /*!<Analog IO GROUP2 enable */
8298 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /*!<Analog IO GROUP3 enable */
8299 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /*!<Analog IO GROUP4 enable */
8300 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /*!<Analog IO GROUP5 enable */
8301 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /*!<Analog IO GROUP6 enable */
8302 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /*!<Analog IO GROUP7 enable */
8303 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080U) /*!<Analog IO GROUP8 enable */
8304 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /*!<Analog IO GROUP1 status */
8305 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /*!<Analog IO GROUP2 status */
8306 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /*!<Analog IO GROUP3 status */
8307 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /*!<Analog IO GROUP4 status */
8308 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /*!<Analog IO GROUP5 status */
8309 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /*!<Analog IO GROUP6 status */
8310 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /*!<Analog IO GROUP7 status */
8311 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000U) /*!<Analog IO GROUP8 status */
8312
8313 /******************* Bit definition for TSC_IOGXCR register *****************/
8314 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /*!<CNT[13:0] bits (Counter value) */
8315
8316 /******************************************************************************/
8317 /* */
8318 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
8319 /* */
8320 /******************************************************************************/
8321 /****************** Bit definition for USART_CR1 register *******************/
8322 #define USART_CR1_UE ((uint32_t)0x00000001U) /*!< USART Enable */
8323 #define USART_CR1_UESM ((uint32_t)0x00000002U) /*!< USART Enable in STOP Mode */
8324 #define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
8325 #define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
8326 #define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
8327 #define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
8328 #define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
8329 #define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< TXE Interrupt Enable */
8330 #define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
8331 #define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
8332 #define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
8333 #define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Receiver Wakeup method */
8334 #define USART_CR1_M ((uint32_t)0x10001000U) /*!< Word length */
8335 #define USART_CR1_M0 ((uint32_t)0x00001000U) /*!< Word length - Bit 0 */
8336 #define USART_CR1_MME ((uint32_t)0x00002000U) /*!< Mute Mode Enable */
8337 #define USART_CR1_CMIE ((uint32_t)0x00004000U) /*!< Character match interrupt enable */
8338 #define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit or 16-bit mode */
8339 #define USART_CR1_DEDT ((uint32_t)0x001F0000U) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
8340 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
8341 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
8342 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
8343 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
8344 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
8345 #define USART_CR1_DEAT ((uint32_t)0x03E00000U) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
8346 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
8347 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
8348 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
8349 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /*!< Bit 3 */
8350 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /*!< Bit 4 */
8351 #define USART_CR1_RTOIE ((uint32_t)0x04000000U) /*!< Receive Time Out interrupt enable */
8352 #define USART_CR1_EOBIE ((uint32_t)0x08000000U) /*!< End of Block interrupt enable */
8353 #define USART_CR1_M1 ((uint32_t)0x10000000U) /*!< Word length - Bit 1 */
8354
8355 /****************** Bit definition for USART_CR2 register *******************/
8356 #define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /*!< 7-bit or 4-bit Address Detection */
8357 #define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
8358 #define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
8359 #define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
8360 #define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
8361 #define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
8362 #define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
8363 #define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
8364 #define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
8365 #define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
8366 #define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
8367 #define USART_CR2_SWAP ((uint32_t)0x00008000U) /*!< SWAP TX/RX pins */
8368 #define USART_CR2_RXINV ((uint32_t)0x00010000U) /*!< RX pin active level inversion */
8369 #define USART_CR2_TXINV ((uint32_t)0x00020000U) /*!< TX pin active level inversion */
8370 #define USART_CR2_DATAINV ((uint32_t)0x00040000U) /*!< Binary data inversion */
8371 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /*!< Most Significant Bit First */
8372 #define USART_CR2_ABREN ((uint32_t)0x00100000U) /*!< Auto Baud-Rate Enable*/
8373 #define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
8374 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
8375 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
8376 #define USART_CR2_RTOEN ((uint32_t)0x00800000U) /*!< Receiver Time-Out enable */
8377 #define USART_CR2_ADD ((uint32_t)0xFF000000U) /*!< Address of the USART node */
8378
8379 /****************** Bit definition for USART_CR3 register *******************/
8380 #define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
8381 #define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
8382 #define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
8383 #define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
8384 #define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< SmartCard NACK enable */
8385 #define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< SmartCard mode enable */
8386 #define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
8387 #define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
8388 #define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
8389 #define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
8390 #define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
8391 #define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
8392 #define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /*!< Overrun Disable */
8393 #define USART_CR3_DDRE ((uint32_t)0x00002000U) /*!< DMA Disable on Reception Error */
8394 #define USART_CR3_DEM ((uint32_t)0x00004000U) /*!< Driver Enable Mode */
8395 #define USART_CR3_DEP ((uint32_t)0x00008000U) /*!< Driver Enable Polarity Selection */
8396 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
8397 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
8398 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
8399 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /*!< Bit 2 */
8400 #define USART_CR3_WUS ((uint32_t)0x00300000U) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
8401 #define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
8402 #define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
8403 #define USART_CR3_WUFIE ((uint32_t)0x00400000U) /*!< Wake Up Interrupt Enable */
8404
8405 /****************** Bit definition for USART_BRR register *******************/
8406 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000FU) /*!< Fraction of USARTDIV */
8407 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0U) /*!< Mantissa of USARTDIV */
8408
8409 /****************** Bit definition for USART_GTPR register ******************/
8410 #define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
8411 #define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< GT[7:0] bits (Guard time value) */
8412
8413
8414 /******************* Bit definition for USART_RTOR register *****************/
8415 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /*!< Receiver Time Out Value */
8416 #define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /*!< Block Length */
8417
8418 /******************* Bit definition for USART_RQR register ******************/
8419 #define USART_RQR_ABRRQ ((uint16_t)0x0001U) /*!< Auto-Baud Rate Request */
8420 #define USART_RQR_SBKRQ ((uint16_t)0x0002U) /*!< Send Break Request */
8421 #define USART_RQR_MMRQ ((uint16_t)0x0004U) /*!< Mute Mode Request */
8422 #define USART_RQR_RXFRQ ((uint16_t)0x0008U) /*!< Receive Data flush Request */
8423 #define USART_RQR_TXFRQ ((uint16_t)0x0010U) /*!< Transmit data flush Request */
8424
8425 /******************* Bit definition for USART_ISR register ******************/
8426 #define USART_ISR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
8427 #define USART_ISR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
8428 #define USART_ISR_NE ((uint32_t)0x00000004U) /*!< Noise detected Flag */
8429 #define USART_ISR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
8430 #define USART_ISR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
8431 #define USART_ISR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
8432 #define USART_ISR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
8433 #define USART_ISR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
8434 #define USART_ISR_LBDF ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
8435 #define USART_ISR_CTSIF ((uint32_t)0x00000200U) /*!< CTS interrupt flag */
8436 #define USART_ISR_CTS ((uint32_t)0x00000400U) /*!< CTS flag */
8437 #define USART_ISR_RTOF ((uint32_t)0x00000800U) /*!< Receiver Time Out */
8438 #define USART_ISR_EOBF ((uint32_t)0x00001000U) /*!< End Of Block Flag */
8439 #define USART_ISR_ABRE ((uint32_t)0x00004000U) /*!< Auto-Baud Rate Error */
8440 #define USART_ISR_ABRF ((uint32_t)0x00008000U) /*!< Auto-Baud Rate Flag */
8441 #define USART_ISR_BUSY ((uint32_t)0x00010000U) /*!< Busy Flag */
8442 #define USART_ISR_CMF ((uint32_t)0x00020000U) /*!< Character Match Flag */
8443 #define USART_ISR_SBKF ((uint32_t)0x00040000U) /*!< Send Break Flag */
8444 #define USART_ISR_RWU ((uint32_t)0x00080000U) /*!< Receive Wake Up from mute mode Flag */
8445 #define USART_ISR_WUF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Flag */
8446 #define USART_ISR_TEACK ((uint32_t)0x00200000U) /*!< Transmit Enable Acknowledge Flag */
8447 #define USART_ISR_REACK ((uint32_t)0x00400000U) /*!< Receive Enable Acknowledge Flag */
8448
8449 /******************* Bit definition for USART_ICR register ******************/
8450 #define USART_ICR_PECF ((uint32_t)0x00000001U) /*!< Parity Error Clear Flag */
8451 #define USART_ICR_FECF ((uint32_t)0x00000002U) /*!< Framing Error Clear Flag */
8452 #define USART_ICR_NCF ((uint32_t)0x00000004U) /*!< Noise detected Clear Flag */
8453 #define USART_ICR_ORECF ((uint32_t)0x00000008U) /*!< OverRun Error Clear Flag */
8454 #define USART_ICR_IDLECF ((uint32_t)0x00000010U) /*!< IDLE line detected Clear Flag */
8455 #define USART_ICR_TCCF ((uint32_t)0x00000040U) /*!< Transmission Complete Clear Flag */
8456 #define USART_ICR_LBDCF ((uint32_t)0x00000100U) /*!< LIN Break Detection Clear Flag */
8457 #define USART_ICR_CTSCF ((uint32_t)0x00000200U) /*!< CTS Interrupt Clear Flag */
8458 #define USART_ICR_RTOCF ((uint32_t)0x00000800U) /*!< Receiver Time Out Clear Flag */
8459 #define USART_ICR_EOBCF ((uint32_t)0x00001000U) /*!< End Of Block Clear Flag */
8460 #define USART_ICR_CMCF ((uint32_t)0x00020000U) /*!< Character Match Clear Flag */
8461 #define USART_ICR_WUCF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Clear Flag */
8462
8463 /******************* Bit definition for USART_RDR register ******************/
8464 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
8465
8466 /******************* Bit definition for USART_TDR register ******************/
8467 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
8468
8469 /******************************************************************************/
8470 /* */
8471 /* Single Wire Protocol Master Interface (SWPMI) */
8472 /* */
8473 /******************************************************************************/
8474
8475 /******************* Bit definition for SWPMI_CR register ********************/
8476 #define SWPMI_CR_RXDMA ((uint32_t)0x00000001U) /*!<Reception DMA enable */
8477 #define SWPMI_CR_TXDMA ((uint32_t)0x00000002U) /*!<Transmission DMA enable */
8478 #define SWPMI_CR_RXMODE ((uint32_t)0x00000004U) /*!<Reception buffering mode */
8479 #define SWPMI_CR_TXMODE ((uint32_t)0x00000008U) /*!<Transmission buffering mode */
8480 #define SWPMI_CR_LPBK ((uint32_t)0x00000010U) /*!<Loopback mode enable */
8481 #define SWPMI_CR_SWPACT ((uint32_t)0x00000020U) /*!<Single wire protocol master interface activate */
8482 #define SWPMI_CR_DEACT ((uint32_t)0x00000400U) /*!<Single wire protocol master interface deactivate */
8483
8484 /******************* Bit definition for SWPMI_BRR register ********************/
8485 #define SWPMI_BRR_BR ((uint32_t)0x0000003FU) /*!<BR[5:0] bits (Bitrate prescaler) */
8486
8487 /******************* Bit definition for SWPMI_ISR register ********************/
8488 #define SWPMI_ISR_RXBFF ((uint32_t)0x00000001U) /*!<Receive buffer full flag */
8489 #define SWPMI_ISR_TXBEF ((uint32_t)0x00000002U) /*!<Transmit buffer empty flag */
8490 #define SWPMI_ISR_RXBERF ((uint32_t)0x00000004U) /*!<Receive CRC error flag */
8491 #define SWPMI_ISR_RXOVRF ((uint32_t)0x00000008U) /*!<Receive overrun error flag */
8492 #define SWPMI_ISR_TXUNRF ((uint32_t)0x00000010U) /*!<Transmit underrun error flag */
8493 #define SWPMI_ISR_RXNE ((uint32_t)0x00000020U) /*!<Receive data register not empty */
8494 #define SWPMI_ISR_TXE ((uint32_t)0x00000040U) /*!<Transmit data register empty */
8495 #define SWPMI_ISR_TCF ((uint32_t)0x00000080U) /*!<Transfer complete flag */
8496 #define SWPMI_ISR_SRF ((uint32_t)0x00000100U) /*!<Slave resume flag */
8497 #define SWPMI_ISR_SUSP ((uint32_t)0x00000200U) /*!<SUSPEND flag */
8498 #define SWPMI_ISR_DEACTF ((uint32_t)0x00000400U) /*!<DEACTIVATED flag */
8499
8500 /******************* Bit definition for SWPMI_ICR register ********************/
8501 #define SWPMI_ICR_CRXBFF ((uint32_t)0x00000001U) /*!<Clear receive buffer full flag */
8502 #define SWPMI_ICR_CTXBEF ((uint32_t)0x00000002U) /*!<Clear transmit buffer empty flag */
8503 #define SWPMI_ICR_CRXBERF ((uint32_t)0x00000004U) /*!<Clear receive CRC error flag */
8504 #define SWPMI_ICR_CRXOVRF ((uint32_t)0x00000008U) /*!<Clear receive overrun error flag */
8505 #define SWPMI_ICR_CTXUNRF ((uint32_t)0x00000010U) /*!<Clear transmit underrun error flag */
8506 #define SWPMI_ICR_CTCF ((uint32_t)0x00000080U) /*!<Clear transfer complete flag */
8507 #define SWPMI_ICR_CSRF ((uint32_t)0x00000100U) /*!<Clear slave resume flag */
8508
8509 /******************* Bit definition for SWPMI_IER register ********************/
8510 #define SWPMI_IER_SRIE ((uint32_t)0x00000100U) /*!<Slave resume interrupt enable */
8511 #define SWPMI_IER_TCIE ((uint32_t)0x00000080U) /*!<Transmit complete interrupt enable */
8512 #define SWPMI_IER_TIE ((uint32_t)0x00000040U) /*!<Transmit interrupt enable */
8513 #define SWPMI_IER_RIE ((uint32_t)0x00000020U) /*!<Receive interrupt enable */
8514 #define SWPMI_IER_TXUNRIE ((uint32_t)0x00000010U) /*!<Transmit underrun error interrupt enable */
8515 #define SWPMI_IER_RXOVRIE ((uint32_t)0x00000008U) /*!<Receive overrun error interrupt enable */
8516 #define SWPMI_IER_RXBERIE ((uint32_t)0x00000004U) /*!<Receive CRC error interrupt enable */
8517 #define SWPMI_IER_TXBEIE ((uint32_t)0x00000002U) /*!<Transmit buffer empty interrupt enable */
8518 #define SWPMI_IER_RXBFIE ((uint32_t)0x00000001U) /*!<Receive buffer full interrupt enable */
8519
8520 /******************* Bit definition for SWPMI_RFL register ********************/
8521 #define SWPMI_RFL_RFL ((uint32_t)0x0000001FU) /*!<RFL[4:0] bits (Receive Frame length) */
8522 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
8523
8524 /******************* Bit definition for SWPMI_TDR register ********************/
8525 #define SWPMI_TDR_TD ((uint32_t)0xFFFFFFFFU) /*!<Transmit Data Register */
8526
8527 /******************* Bit definition for SWPMI_RDR register ********************/
8528 #define SWPMI_RDR_RD ((uint32_t)0xFFFFFFFFU) /*!<Receive Data Register */
8529
8530 /******************* Bit definition for SWPMI_OR register ********************/
8531 #define SWPMI_OR_TBYP ((uint32_t)0x00000001U) /*!<SWP Transceiver Bypass */
8532 #define SWPMI_OR_CLASS ((uint32_t)0x00000002U) /*!<SWP Voltage Class selection */
8533
8534 /******************************************************************************/
8535 /* */
8536 /* VREFBUF */
8537 /* */
8538 /******************************************************************************/
8539 /******************* Bit definition for VREFBUF_CSR register ****************/
8540 #define VREFBUF_CSR_ENVR ((uint32_t)0x00000001U) /*!<Voltage reference buffer enable */
8541 #define VREFBUF_CSR_HIZ ((uint32_t)0x00000002U) /*!<High impedance mode */
8542 #define VREFBUF_CSR_VRS ((uint32_t)0x00000004U) /*!<Voltage reference scale */
8543 #define VREFBUF_CSR_VRR ((uint32_t)0x00000008U) /*!<Voltage reference buffer ready */
8544
8545 /******************* Bit definition for VREFBUF_CCR register ******************/
8546 #define VREFBUF_CCR_TRIM ((uint32_t)0x0000003FU) /*!<TRIM[5:0] bits (Trimming code) */
8547
8548 /******************************************************************************/
8549 /* */
8550 /* Window WATCHDOG */
8551 /* */
8552 /******************************************************************************/
8553 /******************* Bit definition for WWDG_CR register ********************/
8554 #define WWDG_CR_T ((uint32_t)0x0000007FU) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
8555 #define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8556 #define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8557 #define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
8558 #define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
8559 #define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
8560 #define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
8561 #define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
8562
8563 #define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!<Activation bit */
8564
8565 /******************* Bit definition for WWDG_CFR register *******************/
8566 #define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!<W[6:0] bits (7-bit window value) */
8567 #define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8568 #define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8569 #define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
8570 #define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
8571 #define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
8572 #define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
8573 #define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
8574
8575 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!<WDGTB[1:0] bits (Timer Base) */
8576 #define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
8577 #define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
8578
8579 #define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!<Early Wakeup Interrupt */
8580
8581 /******************* Bit definition for WWDG_SR register ********************/
8582 #define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!<Early Wakeup Interrupt Flag */
8583
8584
8585 /******************************************************************************/
8586 /* */
8587 /* Debug MCU */
8588 /* */
8589 /******************************************************************************/
8590 /******************** Bit definition for DBGMCU_IDCODE register *************/
8591 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU)
8592 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U)
8593
8594 /******************** Bit definition for DBGMCU_CR register *****************/
8595 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U)
8596 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U)
8597 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U)
8598 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020U)
8599
8600 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0U)
8601 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040U)/*!<Bit 0 */
8602 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080U)/*!<Bit 1 */
8603
8604 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
8605 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP ((uint32_t)0x00000001U)
8606 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP ((uint32_t)0x00000002U)
8607 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP ((uint32_t)0x00000004U)
8608 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP ((uint32_t)0x00000008U)
8609 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP ((uint32_t)0x00000010U)
8610 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP ((uint32_t)0x00000020U)
8611 #define DBGMCU_APB1FZR1_DBG_RTC_STOP ((uint32_t)0x00000400U)
8612 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP ((uint32_t)0x00000800U)
8613 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP ((uint32_t)0x00001000U)
8614 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP ((uint32_t)0x00200000U)
8615 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP ((uint32_t)0x00400000U)
8616 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP ((uint32_t)0x00800000U)
8617 #define DBGMCU_APB1FZR1_DBG_CAN_STOP ((uint32_t)0x02000000U)
8618 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP ((uint32_t)0x80000000U)
8619
8620 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
8621 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP ((uint32_t)0x00000020U)
8622
8623 /******************** Bit definition for DBGMCU_APB2FZ register ************/
8624 #define DBGMCU_APB2FZ_DBG_TIM1_STOP ((uint32_t)0x00000800U)
8625 #define DBGMCU_APB2FZ_DBG_TIM8_STOP ((uint32_t)0x00002000U)
8626 #define DBGMCU_APB2FZ_DBG_TIM15_STOP ((uint32_t)0x00010000U)
8627 #define DBGMCU_APB2FZ_DBG_TIM16_STOP ((uint32_t)0x00020000U)
8628 #define DBGMCU_APB2FZ_DBG_TIM17_STOP ((uint32_t)0x00040000U)
8629
8630
8631 /**
8632 * @}
8633 */
8634
8635 /**
8636 * @}
8637 */
8638
8639 /** @addtogroup Exported_macros
8640 * @{
8641 */
8642
8643 /******************************* ADC Instances ********************************/
8644 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
8645 ((INSTANCE) == ADC2) || \
8646 ((INSTANCE) == ADC3))
8647
8648 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
8649
8650 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
8651
8652 /******************************** CAN Instances ******************************/
8653 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
8654
8655 /******************************** COMP Instances ******************************/
8656 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
8657 ((INSTANCE) == COMP2))
8658
8659 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
8660
8661 /******************** COMP Instances with window mode capability **************/
8662 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
8663
8664 /******************************* CRC Instances ********************************/
8665 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
8666
8667 /******************************* DAC Instances ********************************/
8668 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
8669
8670 /****************************** DFSDM Instances *******************************/
8671 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Filter0) || \
8672 ((INSTANCE) == DFSDM_Filter1) || \
8673 ((INSTANCE) == DFSDM_Filter2) || \
8674 ((INSTANCE) == DFSDM_Filter3))
8675
8676 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Channel0) || \
8677 ((INSTANCE) == DFSDM_Channel1) || \
8678 ((INSTANCE) == DFSDM_Channel2) || \
8679 ((INSTANCE) == DFSDM_Channel3) || \
8680 ((INSTANCE) == DFSDM_Channel4) || \
8681 ((INSTANCE) == DFSDM_Channel5) || \
8682 ((INSTANCE) == DFSDM_Channel6) || \
8683 ((INSTANCE) == DFSDM_Channel7))
8684
8685 /******************************** DMA Instances *******************************/
8686 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
8687 ((INSTANCE) == DMA1_Channel2) || \
8688 ((INSTANCE) == DMA1_Channel3) || \
8689 ((INSTANCE) == DMA1_Channel4) || \
8690 ((INSTANCE) == DMA1_Channel5) || \
8691 ((INSTANCE) == DMA1_Channel6) || \
8692 ((INSTANCE) == DMA1_Channel7) || \
8693 ((INSTANCE) == DMA2_Channel1) || \
8694 ((INSTANCE) == DMA2_Channel2) || \
8695 ((INSTANCE) == DMA2_Channel3) || \
8696 ((INSTANCE) == DMA2_Channel4) || \
8697 ((INSTANCE) == DMA2_Channel5) || \
8698 ((INSTANCE) == DMA2_Channel6) || \
8699 ((INSTANCE) == DMA2_Channel7))
8700
8701 /******************************* GPIO Instances *******************************/
8702 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
8703 ((INSTANCE) == GPIOB) || \
8704 ((INSTANCE) == GPIOC) || \
8705 ((INSTANCE) == GPIOD) || \
8706 ((INSTANCE) == GPIOE) || \
8707 ((INSTANCE) == GPIOF) || \
8708 ((INSTANCE) == GPIOG) || \
8709 ((INSTANCE) == GPIOH))
8710
8711 /******************************* GPIO AF Instances ****************************/
8712 /* On L4, all GPIO Bank support AF */
8713 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
8714
8715 /**************************** GPIO Lock Instances *****************************/
8716 /* On L4, all GPIO Bank support the Lock mechanism */
8717 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
8718
8719 /******************************** I2C Instances *******************************/
8720 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
8721 ((INSTANCE) == I2C2) || \
8722 ((INSTANCE) == I2C3))
8723
8724 /****************************** OPAMP Instances *******************************/
8725 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
8726 ((INSTANCE) == OPAMP2))
8727
8728 #define IS_OPAMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP12_COMMON)
8729
8730 /******************************* QSPI Instances *******************************/
8731 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
8732
8733 /******************************* RNG Instances ********************************/
8734 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
8735
8736 /****************************** RTC Instances *********************************/
8737 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
8738
8739 /******************************** SAI Instances *******************************/
8740 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
8741 ((INSTANCE) == SAI1_Block_B) || \
8742 ((INSTANCE) == SAI2_Block_A) || \
8743 ((INSTANCE) == SAI2_Block_B))
8744
8745 /****************************** SDMMC Instances *******************************/
8746 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
8747
8748 /****************************** SMBUS Instances *******************************/
8749 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
8750 ((INSTANCE) == I2C2) || \
8751 ((INSTANCE) == I2C3))
8752
8753 /******************************** SPI Instances *******************************/
8754 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8755 ((INSTANCE) == SPI2) || \
8756 ((INSTANCE) == SPI3))
8757
8758 /******************************** SWPMI Instances *****************************/
8759 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
8760
8761 /****************** LPTIM Instances : All supported instances *****************/
8762 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
8763 ((INSTANCE) == LPTIM2))
8764
8765 /****************** TIM Instances : All supported instances *******************/
8766 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8767 ((INSTANCE) == TIM2) || \
8768 ((INSTANCE) == TIM3) || \
8769 ((INSTANCE) == TIM4) || \
8770 ((INSTANCE) == TIM5) || \
8771 ((INSTANCE) == TIM6) || \
8772 ((INSTANCE) == TIM7) || \
8773 ((INSTANCE) == TIM8) || \
8774 ((INSTANCE) == TIM15) || \
8775 ((INSTANCE) == TIM16) || \
8776 ((INSTANCE) == TIM17))
8777
8778 /****************** TIM Instances : supporting 32 bits counter ****************/
8779 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
8780 ((INSTANCE) == TIM5))
8781
8782 /****************** TIM Instances : supporting the break function *************/
8783 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8784 ((INSTANCE) == TIM8) || \
8785 ((INSTANCE) == TIM15) || \
8786 ((INSTANCE) == TIM16) || \
8787 ((INSTANCE) == TIM17))
8788
8789 /************** TIM Instances : supporting Break source selection *************/
8790 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8791 ((INSTANCE) == TIM8) || \
8792 ((INSTANCE) == TIM15) || \
8793 ((INSTANCE) == TIM16) || \
8794 ((INSTANCE) == TIM17))
8795
8796 /****************** TIM Instances : supporting 2 break inputs *****************/
8797 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8798 ((INSTANCE) == TIM8))
8799
8800 /************* TIM Instances : at least 1 capture/compare channel *************/
8801 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8802 ((INSTANCE) == TIM2) || \
8803 ((INSTANCE) == TIM3) || \
8804 ((INSTANCE) == TIM4) || \
8805 ((INSTANCE) == TIM5) || \
8806 ((INSTANCE) == TIM8) || \
8807 ((INSTANCE) == TIM15) || \
8808 ((INSTANCE) == TIM16) || \
8809 ((INSTANCE) == TIM17))
8810
8811 /************ TIM Instances : at least 2 capture/compare channels *************/
8812 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8813 ((INSTANCE) == TIM2) || \
8814 ((INSTANCE) == TIM3) || \
8815 ((INSTANCE) == TIM4) || \
8816 ((INSTANCE) == TIM5) || \
8817 ((INSTANCE) == TIM8) || \
8818 ((INSTANCE) == TIM15))
8819
8820 /************ TIM Instances : at least 3 capture/compare channels *************/
8821 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8822 ((INSTANCE) == TIM2) || \
8823 ((INSTANCE) == TIM3) || \
8824 ((INSTANCE) == TIM4) || \
8825 ((INSTANCE) == TIM5) || \
8826 ((INSTANCE) == TIM8))
8827
8828 /************ TIM Instances : at least 4 capture/compare channels *************/
8829 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8830 ((INSTANCE) == TIM2) || \
8831 ((INSTANCE) == TIM3) || \
8832 ((INSTANCE) == TIM4) || \
8833 ((INSTANCE) == TIM5) || \
8834 ((INSTANCE) == TIM8))
8835
8836 /****************** TIM Instances : at least 5 capture/compare channels *******/
8837 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8838 ((INSTANCE) == TIM8))
8839
8840 /****************** TIM Instances : at least 6 capture/compare channels *******/
8841 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8842 ((INSTANCE) == TIM8))
8843
8844 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
8845 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8846 ((INSTANCE) == TIM8) || \
8847 ((INSTANCE) == TIM15) || \
8848 ((INSTANCE) == TIM16) || \
8849 ((INSTANCE) == TIM17))
8850
8851 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
8852 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8853 ((INSTANCE) == TIM2) || \
8854 ((INSTANCE) == TIM3) || \
8855 ((INSTANCE) == TIM4) || \
8856 ((INSTANCE) == TIM5) || \
8857 ((INSTANCE) == TIM6) || \
8858 ((INSTANCE) == TIM7) || \
8859 ((INSTANCE) == TIM8) || \
8860 ((INSTANCE) == TIM15) || \
8861 ((INSTANCE) == TIM16) || \
8862 ((INSTANCE) == TIM17))
8863
8864 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
8865 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8866 ((INSTANCE) == TIM2) || \
8867 ((INSTANCE) == TIM3) || \
8868 ((INSTANCE) == TIM4) || \
8869 ((INSTANCE) == TIM5) || \
8870 ((INSTANCE) == TIM8) || \
8871 ((INSTANCE) == TIM15) || \
8872 ((INSTANCE) == TIM16) || \
8873 ((INSTANCE) == TIM17))
8874
8875 /******************** TIM Instances : DMA burst feature ***********************/
8876 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8877 ((INSTANCE) == TIM2) || \
8878 ((INSTANCE) == TIM3) || \
8879 ((INSTANCE) == TIM4) || \
8880 ((INSTANCE) == TIM5) || \
8881 ((INSTANCE) == TIM8) || \
8882 ((INSTANCE) == TIM15) || \
8883 ((INSTANCE) == TIM16) || \
8884 ((INSTANCE) == TIM17))
8885
8886 /******************* TIM Instances : output(s) available **********************/
8887 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8888 ((((INSTANCE) == TIM1) && \
8889 (((CHANNEL) == TIM_CHANNEL_1) || \
8890 ((CHANNEL) == TIM_CHANNEL_2) || \
8891 ((CHANNEL) == TIM_CHANNEL_3) || \
8892 ((CHANNEL) == TIM_CHANNEL_4) || \
8893 ((CHANNEL) == TIM_CHANNEL_5) || \
8894 ((CHANNEL) == TIM_CHANNEL_6))) \
8895 || \
8896 (((INSTANCE) == TIM2) && \
8897 (((CHANNEL) == TIM_CHANNEL_1) || \
8898 ((CHANNEL) == TIM_CHANNEL_2) || \
8899 ((CHANNEL) == TIM_CHANNEL_3) || \
8900 ((CHANNEL) == TIM_CHANNEL_4))) \
8901 || \
8902 (((INSTANCE) == TIM3) && \
8903 (((CHANNEL) == TIM_CHANNEL_1) || \
8904 ((CHANNEL) == TIM_CHANNEL_2) || \
8905 ((CHANNEL) == TIM_CHANNEL_3) || \
8906 ((CHANNEL) == TIM_CHANNEL_4))) \
8907 || \
8908 (((INSTANCE) == TIM4) && \
8909 (((CHANNEL) == TIM_CHANNEL_1) || \
8910 ((CHANNEL) == TIM_CHANNEL_2) || \
8911 ((CHANNEL) == TIM_CHANNEL_3) || \
8912 ((CHANNEL) == TIM_CHANNEL_4))) \
8913 || \
8914 (((INSTANCE) == TIM5) && \
8915 (((CHANNEL) == TIM_CHANNEL_1) || \
8916 ((CHANNEL) == TIM_CHANNEL_2) || \
8917 ((CHANNEL) == TIM_CHANNEL_3) || \
8918 ((CHANNEL) == TIM_CHANNEL_4))) \
8919 || \
8920 (((INSTANCE) == TIM8) && \
8921 (((CHANNEL) == TIM_CHANNEL_1) || \
8922 ((CHANNEL) == TIM_CHANNEL_2) || \
8923 ((CHANNEL) == TIM_CHANNEL_3) || \
8924 ((CHANNEL) == TIM_CHANNEL_4) || \
8925 ((CHANNEL) == TIM_CHANNEL_5) || \
8926 ((CHANNEL) == TIM_CHANNEL_6))) \
8927 || \
8928 (((INSTANCE) == TIM15) && \
8929 (((CHANNEL) == TIM_CHANNEL_1) || \
8930 ((CHANNEL) == TIM_CHANNEL_2))) \
8931 || \
8932 (((INSTANCE) == TIM16) && \
8933 (((CHANNEL) == TIM_CHANNEL_1))) \
8934 || \
8935 (((INSTANCE) == TIM17) && \
8936 (((CHANNEL) == TIM_CHANNEL_1))))
8937
8938 /****************** TIM Instances : supporting complementary output(s) ********/
8939 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8940 ((((INSTANCE) == TIM1) && \
8941 (((CHANNEL) == TIM_CHANNEL_1) || \
8942 ((CHANNEL) == TIM_CHANNEL_2) || \
8943 ((CHANNEL) == TIM_CHANNEL_3))) \
8944 || \
8945 (((INSTANCE) == TIM8) && \
8946 (((CHANNEL) == TIM_CHANNEL_1) || \
8947 ((CHANNEL) == TIM_CHANNEL_2) || \
8948 ((CHANNEL) == TIM_CHANNEL_3))) \
8949 || \
8950 (((INSTANCE) == TIM15) && \
8951 ((CHANNEL) == TIM_CHANNEL_1)) \
8952 || \
8953 (((INSTANCE) == TIM16) && \
8954 ((CHANNEL) == TIM_CHANNEL_1)) \
8955 || \
8956 (((INSTANCE) == TIM17) && \
8957 ((CHANNEL) == TIM_CHANNEL_1)))
8958
8959 /****************** TIM Instances : supporting clock division *****************/
8960 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8961 ((INSTANCE) == TIM2) || \
8962 ((INSTANCE) == TIM3) || \
8963 ((INSTANCE) == TIM4) || \
8964 ((INSTANCE) == TIM5) || \
8965 ((INSTANCE) == TIM8) || \
8966 ((INSTANCE) == TIM15) || \
8967 ((INSTANCE) == TIM16) || \
8968 ((INSTANCE) == TIM17))
8969
8970 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
8971 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8972 ((INSTANCE) == TIM2) || \
8973 ((INSTANCE) == TIM3) || \
8974 ((INSTANCE) == TIM4) || \
8975 ((INSTANCE) == TIM5) || \
8976 ((INSTANCE) == TIM8) || \
8977 ((INSTANCE) == TIM15))
8978
8979 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
8980 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8981 ((INSTANCE) == TIM2) || \
8982 ((INSTANCE) == TIM3) || \
8983 ((INSTANCE) == TIM4) || \
8984 ((INSTANCE) == TIM5) || \
8985 ((INSTANCE) == TIM8))
8986
8987 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
8988 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8989 ((INSTANCE) == TIM2) || \
8990 ((INSTANCE) == TIM3) || \
8991 ((INSTANCE) == TIM4) || \
8992 ((INSTANCE) == TIM5) || \
8993 ((INSTANCE) == TIM8) || \
8994 ((INSTANCE) == TIM15))
8995
8996 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
8997 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8998 ((INSTANCE) == TIM2) || \
8999 ((INSTANCE) == TIM3) || \
9000 ((INSTANCE) == TIM4) || \
9001 ((INSTANCE) == TIM5) || \
9002 ((INSTANCE) == TIM8) || \
9003 ((INSTANCE) == TIM15))
9004
9005 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
9006 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9007 ((INSTANCE) == TIM8))
9008
9009 /****************** TIM Instances : supporting commutation event generation ***/
9010 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9011 ((INSTANCE) == TIM8) || \
9012 ((INSTANCE) == TIM15) || \
9013 ((INSTANCE) == TIM16) || \
9014 ((INSTANCE) == TIM17))
9015
9016 /****************** TIM Instances : supporting counting mode selection ********/
9017 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9018 ((INSTANCE) == TIM2) || \
9019 ((INSTANCE) == TIM3) || \
9020 ((INSTANCE) == TIM4) || \
9021 ((INSTANCE) == TIM5) || \
9022 ((INSTANCE) == TIM8))
9023
9024 /****************** TIM Instances : supporting encoder interface **************/
9025 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9026 ((INSTANCE) == TIM2) || \
9027 ((INSTANCE) == TIM3) || \
9028 ((INSTANCE) == TIM4) || \
9029 ((INSTANCE) == TIM5) || \
9030 ((INSTANCE) == TIM8))
9031
9032 /****************** TIM Instances : supporting Hall sensor interface **********/
9033 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9034 ((INSTANCE) == TIM2) || \
9035 ((INSTANCE) == TIM3) || \
9036 ((INSTANCE) == TIM4) || \
9037 ((INSTANCE) == TIM5))
9038
9039 /**************** TIM Instances : external trigger input available ************/
9040 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9041 ((INSTANCE) == TIM2) || \
9042 ((INSTANCE) == TIM3) || \
9043 ((INSTANCE) == TIM4) || \
9044 ((INSTANCE) == TIM5) || \
9045 ((INSTANCE) == TIM8))
9046
9047 /************* TIM Instances : supporting ETR source selection ***************/
9048 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9049 ((INSTANCE) == TIM2) || \
9050 ((INSTANCE) == TIM3) || \
9051 ((INSTANCE) == TIM8))
9052
9053 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
9054 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9055 ((INSTANCE) == TIM2) || \
9056 ((INSTANCE) == TIM3) || \
9057 ((INSTANCE) == TIM4) || \
9058 ((INSTANCE) == TIM5) || \
9059 ((INSTANCE) == TIM6) || \
9060 ((INSTANCE) == TIM7) || \
9061 ((INSTANCE) == TIM8) || \
9062 ((INSTANCE) == TIM15))
9063
9064 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
9065 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9066 ((INSTANCE) == TIM2) || \
9067 ((INSTANCE) == TIM3) || \
9068 ((INSTANCE) == TIM4) || \
9069 ((INSTANCE) == TIM5) || \
9070 ((INSTANCE) == TIM8) || \
9071 ((INSTANCE) == TIM15))
9072
9073 /****************** TIM Instances : supporting OCxREF clear *******************/
9074 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9075 ((INSTANCE) == TIM2) || \
9076 ((INSTANCE) == TIM3) || \
9077 ((INSTANCE) == TIM4) || \
9078 ((INSTANCE) == TIM5) || \
9079 ((INSTANCE) == TIM8))
9080
9081 /****************** TIM Instances : remapping capability **********************/
9082 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9083 ((INSTANCE) == TIM2) || \
9084 ((INSTANCE) == TIM3) || \
9085 ((INSTANCE) == TIM8) || \
9086 ((INSTANCE) == TIM15) || \
9087 ((INSTANCE) == TIM16) || \
9088 ((INSTANCE) == TIM17))
9089
9090 /****************** TIM Instances : supporting repetition counter *************/
9091 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9092 ((INSTANCE) == TIM8) || \
9093 ((INSTANCE) == TIM15) || \
9094 ((INSTANCE) == TIM16) || \
9095 ((INSTANCE) == TIM17))
9096
9097 /****************** TIM Instances : supporting synchronization ****************/
9098 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
9099
9100 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9101 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9102 ((INSTANCE) == TIM8))
9103
9104 /******************* TIM Instances : Timer input XOR function *****************/
9105 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9106 ((INSTANCE) == TIM2) || \
9107 ((INSTANCE) == TIM3) || \
9108 ((INSTANCE) == TIM4) || \
9109 ((INSTANCE) == TIM5) || \
9110 ((INSTANCE) == TIM8) || \
9111 ((INSTANCE) == TIM15))
9112
9113 /****************************** TSC Instances *********************************/
9114 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
9115
9116 /******************** USART Instances : Synchronous mode **********************/
9117 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9118 ((INSTANCE) == USART2) || \
9119 ((INSTANCE) == USART3))
9120
9121 /******************** UART Instances : Asynchronous mode **********************/
9122 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9123 ((INSTANCE) == USART2) || \
9124 ((INSTANCE) == USART3) || \
9125 ((INSTANCE) == UART4) || \
9126 ((INSTANCE) == UART5))
9127
9128 /****************** UART Instances : Auto Baud Rate detection ****************/
9129 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9130 ((INSTANCE) == USART2) || \
9131 ((INSTANCE) == USART3) || \
9132 ((INSTANCE) == UART4) || \
9133 ((INSTANCE) == UART5))
9134
9135 /****************** UART Instances : Driver Enable *****************/
9136 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9137 ((INSTANCE) == USART2) || \
9138 ((INSTANCE) == USART3) || \
9139 ((INSTANCE) == UART4) || \
9140 ((INSTANCE) == UART5) || \
9141 ((INSTANCE) == LPUART1))
9142
9143 /******************** UART Instances : Half-Duplex mode **********************/
9144 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9145 ((INSTANCE) == USART2) || \
9146 ((INSTANCE) == USART3) || \
9147 ((INSTANCE) == UART4) || \
9148 ((INSTANCE) == UART5) || \
9149 ((INSTANCE) == LPUART1))
9150
9151 /****************** UART Instances : Hardware Flow control ********************/
9152 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9153 ((INSTANCE) == USART2) || \
9154 ((INSTANCE) == USART3) || \
9155 ((INSTANCE) == UART4) || \
9156 ((INSTANCE) == UART5) || \
9157 ((INSTANCE) == LPUART1))
9158
9159 /******************** UART Instances : LIN mode **********************/
9160 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9161 ((INSTANCE) == USART2) || \
9162 ((INSTANCE) == USART3) || \
9163 ((INSTANCE) == UART4) || \
9164 ((INSTANCE) == UART5))
9165
9166 /******************** UART Instances : Wake-up from Stop mode **********************/
9167 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9168 ((INSTANCE) == USART2) || \
9169 ((INSTANCE) == USART3) || \
9170 ((INSTANCE) == UART4) || \
9171 ((INSTANCE) == UART5) || \
9172 ((INSTANCE) == LPUART1))
9173
9174 /*********************** UART Instances : IRDA mode ***************************/
9175 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9176 ((INSTANCE) == USART2) || \
9177 ((INSTANCE) == USART3) || \
9178 ((INSTANCE) == UART4) || \
9179 ((INSTANCE) == UART5))
9180
9181 /********************* USART Instances : Smard card mode ***********************/
9182 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9183 ((INSTANCE) == USART2) || \
9184 ((INSTANCE) == USART3))
9185
9186 /******************** LPUART Instance *****************************************/
9187 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
9188
9189 /****************************** IWDG Instances ********************************/
9190 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
9191
9192 /****************************** WWDG Instances ********************************/
9193 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
9194
9195 /**
9196 * @}
9197 */
9198
9199
9200 /******************************************************************************/
9201 /* For a painless codes migration between the STM32L4xx device product */
9202 /* lines, the aliases defined below are put in place to overcome the */
9203 /* differences in the interrupt handlers and IRQn definitions. */
9204 /* No need to update developed interrupt code when moving across */
9205 /* product lines within the same STM32L4 Family */
9206 /******************************************************************************/
9207
9208 /* Aliases for __IRQn */
9209 #define TIM8_IRQn TIM8_UP_IRQn
9210
9211 /* Aliases for __IRQHandler */
9212 #define TIM8_IRQHandler TIM8_UP_IRQHandler
9213
9214
9215 #ifdef __cplusplus
9216 }
9217 #endif /* __cplusplus */
9218
9219 #endif /* __STM32L471xx_H */
9220
9221 /**
9222 * @}
9223 */
9224
9225 /**
9226 * @}
9227 */
9228
9229 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/