Mercurial > pub > halpp

comparison l476rg-hal-test/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l486xx.h @ 0:32a3b1785697

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
parents
children
comparison
equal deleted inserted replaced
-1:000000000000 0:32a3b1785697
1 /**
2 ******************************************************************************
3 * @file stm32l486xx.h
4 * @author MCD Application Team
5 * @version V1.0.3
6 * @date 29-January-2016
7 * @brief CMSIS STM32L486xx Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral�s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 /** @addtogroup CMSIS_Device
45 * @{
46 */
47
48 /** @addtogroup stm32l486xx
49 * @{
50 */
51
52 #ifndef __STM32L486xx_H
53 #define __STM32L486xx_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif /* __cplusplus */
58
59 /** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63 /**
64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
65 */
66 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
67 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
68 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
70 #define __FPU_PRESENT 1 /*!< FPU present */
71
72 /**
73 * @}
74 */
75
76 /** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80 /**
81 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
88 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
98 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
102 RCC_IRQn = 5, /*!< RCC global Interrupt */
103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
108 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
109 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
110 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
111 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
112 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
113 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
114 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
115 ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */
116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
121 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
122 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
123 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
139 DFSDM3_IRQn = 42, /*!< SD Filter 3 global Interrupt */
140 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
141 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
142 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
144 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
145 FMC_IRQn = 48, /*!< FMC global Interrupt */
146 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
153 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
154 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
155 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
156 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
157 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
158 DFSDM0_IRQn = 61, /*!< SD Filter 0 global Interrupt */
159 DFSDM1_IRQn = 62, /*!< SD Filter 1 global Interrupt */
160 DFSDM2_IRQn = 63, /*!< SD Filter 2 global Interrupt */
161 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
162 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
163 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
165 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
166 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
167 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
168 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
171 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
172 SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
173 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
174 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
175 LCD_IRQn = 78, /*!< LCD global interrupt */
176 AES_IRQn = 79, /*!< AES global interrupt */
177 RNG_IRQn = 80, /*!< RNG global interrupt */
178 FPU_IRQn = 81 /*!< FPU global interrupt */
179 } IRQn_Type;
180
181 /**
182 * @}
183 */
184
185 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
186 #include "system_stm32l4xx.h"
187 #include <stdint.h>
188
189 /** @addtogroup Peripheral_registers_structures
190 * @{
191 */
192
193 /**
194 * @brief Analog to Digital Converter
195 */
196
197 typedef struct
198 {
199 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
200 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
201 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
202 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
203 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
204 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
205 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
206 uint32_t RESERVED1; /*!< Reserved, 0x1C */
207 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
208 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
209 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
210 uint32_t RESERVED2; /*!< Reserved, 0x2C */
211 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
212 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
213 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
214 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
215 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
216 uint32_t RESERVED3; /*!< Reserved, 0x44 */
217 uint32_t RESERVED4; /*!< Reserved, 0x48 */
218 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
219 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
220 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
221 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
222 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
223 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
224 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
225 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
226 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
227 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
228 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
229 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
230 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
231 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
232 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
233 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
234 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
235 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
236
237 } ADC_TypeDef;
238
239 typedef struct
240 {
241 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
242 uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
243 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
244 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
245 } ADC_Common_TypeDef;
246
247
248 /**
249 * @brief Controller Area Network TxMailBox
250 */
251
252 typedef struct
253 {
254 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
255 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
256 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
257 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
258 } CAN_TxMailBox_TypeDef;
259
260 /**
261 * @brief Controller Area Network FIFOMailBox
262 */
263
264 typedef struct
265 {
266 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
267 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
268 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
269 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
270 } CAN_FIFOMailBox_TypeDef;
271
272 /**
273 * @brief Controller Area Network FilterRegister
274 */
275
276 typedef struct
277 {
278 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
279 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
280 } CAN_FilterRegister_TypeDef;
281
282 /**
283 * @brief Controller Area Network
284 */
285
286 typedef struct
287 {
288 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
289 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
290 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
291 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
292 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
293 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
294 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
295 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
296 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
297 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
298 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
299 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
300 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
301 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
302 uint32_t RESERVED2; /*!< Reserved, 0x208 */
303 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
304 uint32_t RESERVED3; /*!< Reserved, 0x210 */
305 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
306 uint32_t RESERVED4; /*!< Reserved, 0x218 */
307 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
308 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
309 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
310 } CAN_TypeDef;
311
312
313 /**
314 * @brief Comparator
315 */
316
317 typedef struct
318 {
319 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
320 } COMP_TypeDef;
321
322 typedef struct
323 {
324 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
325 } COMP_Common_TypeDef;
326
327 /**
328 * @brief CRC calculation unit
329 */
330
331 typedef struct
332 {
333 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
334 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
335 uint8_t RESERVED0; /*!< Reserved, 0x05 */
336 uint16_t RESERVED1; /*!< Reserved, 0x06 */
337 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
338 uint32_t RESERVED2; /*!< Reserved, 0x0C */
339 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
340 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
341 } CRC_TypeDef;
342
343 /**
344 * @brief Digital to Analog Converter
345 */
346
347 typedef struct
348 {
349 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
350 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
351 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
352 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
353 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
354 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
355 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
356 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
357 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
358 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
359 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
360 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
361 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
362 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
363 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
364 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
365 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
366 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
367 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
368 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
369 } DAC_TypeDef;
370
371 /**
372 * @brief DFSDM module registers
373 */
374 typedef struct
375 {
376 __IO uint32_t CR1; /*!< DFSDM control register1, Address offset: 0x100 */
377 __IO uint32_t CR2; /*!< DFSDM control register2, Address offset: 0x104 */
378 __IO uint32_t ISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
379 __IO uint32_t ICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
380 __IO uint32_t JCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
381 __IO uint32_t FCR; /*!< DFSDM filter control register, Address offset: 0x114 */
382 __IO uint32_t JDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
383 __IO uint32_t RDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
384 __IO uint32_t AWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
385 __IO uint32_t AWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
386 __IO uint32_t AWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
387 __IO uint32_t AWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
388 __IO uint32_t EXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
389 __IO uint32_t EXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
390 __IO uint32_t CNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
391 } DFSDM_Filter_TypeDef;
392
393 /**
394 * @brief DFSDM channel configuration registers
395 */
396 typedef struct
397 {
398 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
399 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
400 __IO uint32_t AWSCDR; /*!< DFSDM channel analog watchdog and
401 short circuit detector register, Address offset: 0x08 */
402 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
403 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
404 } DFSDM_Channel_TypeDef;
405
406 /**
407 * @brief Debug MCU
408 */
409
410 typedef struct
411 {
412 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
413 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
414 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
415 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
416 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
417 } DBGMCU_TypeDef;
418
419
420 /**
421 * @brief DMA Controller
422 */
423
424 typedef struct
425 {
426 __IO uint32_t CCR; /*!< DMA channel x configuration register */
427 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
428 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
429 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
430 } DMA_Channel_TypeDef;
431
432 typedef struct
433 {
434 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
435 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
436 } DMA_TypeDef;
437
438 typedef struct
439 {
440 __IO uint32_t CSELR; /*!< DMA channel selection register */
441 } DMA_Request_TypeDef;
442
443 /* Legacy define */
444 #define DMA_request_TypeDef DMA_Request_TypeDef
445
446 /**
447 * @brief External Interrupt/Event Controller
448 */
449
450 typedef struct
451 {
452 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
453 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
454 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
455 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
456 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
457 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
458 uint32_t RESERVED1; /*!< Reserved, 0x18 */
459 uint32_t RESERVED2; /*!< Reserved, 0x1C */
460 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
461 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
462 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
463 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
464 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
465 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
466 } EXTI_TypeDef;
467
468
469 /**
470 * @brief Firewall
471 */
472
473 typedef struct
474 {
475 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
476 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
477 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
478 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
479 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
480 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
481 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
482 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
483 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
484 } FIREWALL_TypeDef;
485
486
487 /**
488 * @brief FLASH Registers
489 */
490
491 typedef struct
492 {
493 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
494 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
495 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
496 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
497 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
498 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
499 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
500 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
501 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
502 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
503 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
504 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
505 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
506 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
507 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
508 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
509 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
510 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
511 } FLASH_TypeDef;
512
513
514 /**
515 * @brief Flexible Memory Controller
516 */
517
518 typedef struct
519 {
520 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
521 } FMC_Bank1_TypeDef;
522
523 /**
524 * @brief Flexible Memory Controller Bank1E
525 */
526
527 typedef struct
528 {
529 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
530 } FMC_Bank1E_TypeDef;
531
532 /**
533 * @brief Flexible Memory Controller Bank3
534 */
535
536 typedef struct
537 {
538 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
539 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
540 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
541 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
542 uint32_t RESERVED0; /*!< Reserved, 0x90 */
543 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
544 } FMC_Bank3_TypeDef;
545
546 /**
547 * @brief General Purpose I/O
548 */
549
550 typedef struct
551 {
552 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
553 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
554 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
555 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
556 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
557 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
558 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
559 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
560 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
561 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
562 __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */
563
564 } GPIO_TypeDef;
565
566
567 /**
568 * @brief Inter-integrated Circuit Interface
569 */
570
571 typedef struct
572 {
573 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
574 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
575 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
576 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
577 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
578 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
579 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
580 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
581 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
582 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
583 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
584 } I2C_TypeDef;
585
586 /**
587 * @brief Independent WATCHDOG
588 */
589
590 typedef struct
591 {
592 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
593 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
594 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
595 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
596 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
597 } IWDG_TypeDef;
598
599 /**
600 * @brief LCD
601 */
602
603 typedef struct
604 {
605 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
606 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
607 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
608 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
609 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
610 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
611 } LCD_TypeDef;
612
613 /**
614 * @brief LPTIMER
615 */
616 typedef struct
617 {
618 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
619 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
620 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
621 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
622 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
623 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
624 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
625 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
626 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
627 } LPTIM_TypeDef;
628
629
630 /**
631 * @brief Operational Amplifier (OPAMP)
632 */
633
634 typedef struct
635 {
636 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
637 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
638 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
639 } OPAMP_TypeDef;
640
641 typedef struct
642 {
643 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
644 } OPAMP_Common_TypeDef;
645
646 /**
647 * @brief Power Control
648 */
649
650 typedef struct
651 {
652 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
653 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
654 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
655 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
656 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
657 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
658 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
659 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
660 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
661 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
662 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
663 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
664 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
665 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
666 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
667 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
668 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
669 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
670 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
671 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
672 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
673 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
674 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
675 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
676 } PWR_TypeDef;
677
678
679 /**
680 * @brief QUAD Serial Peripheral Interface
681 */
682
683 typedef struct
684 {
685 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
686 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
687 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
688 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
689 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
690 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
691 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
692 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
693 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
694 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
695 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
696 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
697 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
698 } QUADSPI_TypeDef;
699
700
701 /**
702 * @brief Reset and Clock Control
703 */
704
705 typedef struct
706 {
707 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
708 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
709 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
710 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
711 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
712 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
713 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
714 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
715 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
716 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
717 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
718 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
719 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
720 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
721 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
722 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
723 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
724 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
725 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
726 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
727 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
728 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
729 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
730 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
731 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
732 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
733 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
734 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
735 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
736 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
737 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
738 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
739 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
740 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
741 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
742 __IO uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
743 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
744 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
745 } RCC_TypeDef;
746
747 /**
748 * @brief Real-Time Clock
749 */
750
751 typedef struct
752 {
753 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
754 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
755 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
756 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
757 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
758 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
759 uint32_t reserved; /*!< Reserved */
760 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
761 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
762 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
763 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
764 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
765 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
766 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
767 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
768 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
769 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
770 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
771 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
772 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
773 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
774 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
775 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
776 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
777 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
778 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
779 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
780 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
781 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
782 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
783 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
784 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
785 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
786 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
787 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
788 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
789 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
790 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
791 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
792 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
793 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
794 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
795 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
796 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
797 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
798 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
799 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
800 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
801 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
802 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
803 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
804 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
805 } RTC_TypeDef;
806
807
808 /**
809 * @brief Serial Audio Interface
810 */
811
812 typedef struct
813 {
814 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
815 } SAI_TypeDef;
816
817 typedef struct
818 {
819 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
820 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
821 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
822 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
823 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
824 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
825 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
826 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
827 } SAI_Block_TypeDef;
828
829
830 /**
831 * @brief Secure digital input/output Interface
832 */
833
834 typedef struct
835 {
836 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
837 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
838 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
839 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
840 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
841 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
842 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
843 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
844 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
845 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
846 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
847 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
848 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
849 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
850 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
851 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
852 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
853 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
854 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
855 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
856 } SDMMC_TypeDef;
857
858
859 /**
860 * @brief Serial Peripheral Interface
861 */
862
863 typedef struct
864 {
865 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
866 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
867 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
868 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
869 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
870 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
871 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
872 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
873 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
874 } SPI_TypeDef;
875
876
877 /**
878 * @brief Single Wire Protocol Master Interface SPWMI
879 */
880
881 typedef struct
882 {
883 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
884 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
885 uint32_t RESERVED1; /*!< Reserved, 0x08 */
886 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
887 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
888 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
889 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
890 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
891 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
892 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
893 } SWPMI_TypeDef;
894
895
896 /**
897 * @brief System configuration controller
898 */
899
900 typedef struct
901 {
902 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
903 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
904 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
905 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
906 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
907 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
908 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
909 } SYSCFG_TypeDef;
910
911
912 /**
913 * @brief TIM
914 */
915
916 typedef struct
917 {
918 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
919 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
920 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
921 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
922 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
923 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
924 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
925 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
926 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
927 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
928 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
929 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
930 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
931 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
932 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
933 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
934 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
935 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
936 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
937 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
938 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
939 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
940 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
941 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
942 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
943 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
944 } TIM_TypeDef;
945
946
947 /**
948 * @brief Touch Sensing Controller (TSC)
949 */
950
951 typedef struct
952 {
953 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
954 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
955 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
956 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
957 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
958 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
959 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
960 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
961 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
962 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
963 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
964 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
965 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
966 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
967 } TSC_TypeDef;
968
969 /**
970 * @brief Universal Synchronous Asynchronous Receiver Transmitter
971 */
972
973 typedef struct
974 {
975 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
976 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
977 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
978 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
979 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
980 uint16_t RESERVED2; /*!< Reserved, 0x12 */
981 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
982 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
983 uint16_t RESERVED3; /*!< Reserved, 0x1A */
984 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
985 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
986 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
987 uint16_t RESERVED4; /*!< Reserved, 0x26 */
988 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
989 uint16_t RESERVED5; /*!< Reserved, 0x2A */
990 } USART_TypeDef;
991
992 /**
993 * @brief VREFBUF
994 */
995
996 typedef struct
997 {
998 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
999 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
1000 } VREFBUF_TypeDef;
1001
1002 /**
1003 * @brief Window WATCHDOG
1004 */
1005
1006 typedef struct
1007 {
1008 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1009 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1010 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1011 } WWDG_TypeDef;
1012
1013 /**
1014 * @brief AES hardware accelerator
1015 */
1016
1017 typedef struct
1018 {
1019 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
1020 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
1021 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
1022 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
1023 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
1024 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
1025 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
1026 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
1027 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
1028 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
1029 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
1030 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
1031 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
1032 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
1033 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
1034 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
1035 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
1036 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
1037 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
1038 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
1039 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
1040 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
1041 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
1042 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
1043 } AES_TypeDef;
1044
1045 /**
1046 * @brief RNG
1047 */
1048
1049 typedef struct
1050 {
1051 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1052 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1053 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1054 } RNG_TypeDef;
1055
1056 /**
1057 * @brief USB_OTG_Core_register
1058 */
1059 typedef struct
1060 {
1061 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
1062 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
1063 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
1064 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
1065 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
1066 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
1067 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
1068 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
1069 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
1070 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
1071 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
1072 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
1073 uint32_t Reserved30[2]; /* Reserved 030h*/
1074 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
1075 __IO uint32_t CID; /* User ID Register 03Ch*/
1076 uint32_t Reserved5[3]; /* Reserved 040h-048h*/
1077 __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
1078 uint32_t Reserved6; /* Reserved 050h*/
1079 __IO uint32_t GLPMCFG; /* LPM Register 054h*/
1080 __IO uint32_t GPWRDN; /* Power Down Register 058h*/
1081 __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
1082 __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
1083 uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
1084 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
1085 __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
1086 } USB_OTG_GlobalTypeDef;
1087
1088 /**
1089 * @brief USB_OTG_device_Registers
1090 */
1091 typedef struct
1092 {
1093 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
1094 __IO uint32_t DCTL; /* dev Control Register 804h*/
1095 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
1096 uint32_t Reserved0C; /* Reserved 80Ch*/
1097 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
1098 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
1099 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
1100 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
1101 uint32_t Reserved20; /* Reserved 820h*/
1102 uint32_t Reserved9; /* Reserved 824h*/
1103 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
1104 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
1105 __IO uint32_t DTHRCTL; /* dev thr 830h*/
1106 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
1107 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
1108 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
1109 uint32_t Reserved40; /* dedicated EP mask 840h*/
1110 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
1111 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
1112 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
1113 } USB_OTG_DeviceTypeDef;
1114
1115 /**
1116 * @brief USB_OTG_IN_Endpoint-Specific_Register
1117 */
1118 typedef struct
1119 {
1120 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
1121 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
1122 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
1123 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
1124 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
1125 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
1126 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
1127 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1128 } USB_OTG_INEndpointTypeDef;
1129
1130 /**
1131 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1132 */
1133 typedef struct
1134 {
1135 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1136 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1137 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1138 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1139 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1140 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1141 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1142 } USB_OTG_OUTEndpointTypeDef;
1143
1144 /**
1145 * @brief USB_OTG_Host_Mode_Register_Structures
1146 */
1147 typedef struct
1148 {
1149 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1150 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1151 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1152 uint32_t Reserved40C; /* Reserved 40Ch*/
1153 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1154 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1155 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1156 } USB_OTG_HostTypeDef;
1157
1158 /**
1159 * @brief USB_OTG_Host_Channel_Specific_Registers
1160 */
1161 typedef struct
1162 {
1163 __IO uint32_t HCCHAR;
1164 __IO uint32_t HCSPLT;
1165 __IO uint32_t HCINT;
1166 __IO uint32_t HCINTMSK;
1167 __IO uint32_t HCTSIZ;
1168 __IO uint32_t HCDMA;
1169 uint32_t Reserved[2];
1170 } USB_OTG_HostChannelTypeDef;
1171
1172 /**
1173 * @}
1174 */
1175
1176 /** @addtogroup Peripheral_memory_map
1177 * @{
1178 */
1179 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
1180 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address*/
1181 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
1182 #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
1183 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address*/
1184 #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
1185 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
1186 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
1187 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
1188 #define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
1189
1190 /* Legacy defines */
1191 #define SRAM_BASE SRAM1_BASE
1192 #define SRAM_BB_BASE SRAM1_BB_BASE
1193
1194 #define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
1195 #define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
1196
1197 /*!< Peripheral memory map */
1198 #define APB1PERIPH_BASE PERIPH_BASE
1199 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1200 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1201 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
1202
1203 #define FMC_BANK1 FMC_BASE
1204 #define FMC_BANK1_1 FMC_BANK1
1205 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
1206 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
1207 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
1208 #define FMC_BANK3 (FMC_BASE + 0x20000000U)
1209
1210 /*!< APB1 peripherals */
1211 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1212 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1213 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1214 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1215 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1216 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1217 #define LCD_BASE (APB1PERIPH_BASE + 0x2400U)
1218 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1219 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1220 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1221 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1222 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1223 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1224 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1225 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1226 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1227 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1228 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1229 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1230 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1231 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1232 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1233 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
1234 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
1235 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
1236 #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
1237 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
1238 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
1239 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
1240 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
1241
1242
1243 /*!< APB2 peripherals */
1244 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
1245 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
1246 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
1247 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
1248 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
1249 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
1250 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
1251 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
1252 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1253 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
1254 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
1255 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
1256 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
1257 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
1258 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
1259 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1260 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1261 #define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
1262 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
1263 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
1264 #define DFSDM_BASE (APB2PERIPH_BASE + 0x6000U)
1265 #define DFSDM_Channel0_BASE (DFSDM_BASE + 0x00)
1266 #define DFSDM_Channel1_BASE (DFSDM_BASE + 0x20)
1267 #define DFSDM_Channel2_BASE (DFSDM_BASE + 0x40)
1268 #define DFSDM_Channel3_BASE (DFSDM_BASE + 0x60)
1269 #define DFSDM_Channel4_BASE (DFSDM_BASE + 0x80)
1270 #define DFSDM_Channel5_BASE (DFSDM_BASE + 0xA0)
1271 #define DFSDM_Channel6_BASE (DFSDM_BASE + 0xC0)
1272 #define DFSDM_Channel7_BASE (DFSDM_BASE + 0xE0)
1273 #define DFSDM_Filter0_BASE (DFSDM_BASE + 0x100)
1274 #define DFSDM_Filter1_BASE (DFSDM_BASE + 0x180)
1275 #define DFSDM_Filter2_BASE (DFSDM_BASE + 0x200)
1276 #define DFSDM_Filter3_BASE (DFSDM_BASE + 0x280)
1277
1278 /*!< AHB1 peripherals */
1279 #define DMA1_BASE (AHB1PERIPH_BASE)
1280 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
1281 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
1282 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
1283 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1284 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
1285
1286
1287 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
1288 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
1289 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
1290 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
1291 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
1292 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
1293 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
1294 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
1295
1296
1297 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
1298 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
1299 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
1300 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
1301 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
1302 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
1303 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
1304 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
1305
1306
1307 /*!< AHB2 peripherals */
1308 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
1309 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
1310 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
1311 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
1312 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
1313 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
1314 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
1315 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
1316
1317 #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
1318
1319 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
1320 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U)
1321 #define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U)
1322 #define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
1323
1324
1325 #define AES_BASE (AHB2PERIPH_BASE + 0x08060000U)
1326 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
1327
1328 /*!< FMC Banks registers base address */
1329 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1330 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1331 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1332
1333 /* Debug MCU registers base address */
1334 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
1335
1336 /*!< USB registers base address */
1337 #define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
1338
1339 #define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
1340 #define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
1341 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
1342 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
1343 #define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
1344 #define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
1345 #define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
1346 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
1347 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
1348 #define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
1349 #define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
1350 #define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
1351
1352
1353 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
1354 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
1355 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
1356 /**
1357 * @}
1358 */
1359
1360 /** @addtogroup Peripheral_declaration
1361 * @{
1362 */
1363 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1364 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1365 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1366 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1367 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1368 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1369 #define LCD ((LCD_TypeDef *) LCD_BASE)
1370 #define RTC ((RTC_TypeDef *) RTC_BASE)
1371 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1372 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1373 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1374 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1375 #define USART2 ((USART_TypeDef *) USART2_BASE)
1376 #define USART3 ((USART_TypeDef *) USART3_BASE)
1377 #define UART4 ((USART_TypeDef *) UART4_BASE)
1378 #define UART5 ((USART_TypeDef *) UART5_BASE)
1379 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1380 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1381 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1382 #define CAN ((CAN_TypeDef *) CAN1_BASE)
1383 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1384 #define PWR ((PWR_TypeDef *) PWR_BASE)
1385 #define DAC ((DAC_TypeDef *) DAC1_BASE)
1386 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1387 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1388 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1389 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1390 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1391 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1392 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1393 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
1394 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1395
1396 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1397 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1398 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1399 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1400 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1401 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1402 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1403 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1404 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1405 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1406 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1407 #define USART1 ((USART_TypeDef *) USART1_BASE)
1408 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1409 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1410 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1411 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1412 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1413 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1414 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1415 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1416 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1417 #define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE)
1418 #define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE)
1419 #define DFSDM_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM_Channel2_BASE)
1420 #define DFSDM_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM_Channel3_BASE)
1421 #define DFSDM_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM_Channel4_BASE)
1422 #define DFSDM_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM_Channel5_BASE)
1423 #define DFSDM_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM_Channel6_BASE)
1424 #define DFSDM_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM_Channel7_BASE)
1425 #define DFSDM_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM_Filter0_BASE)
1426 #define DFSDM_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM_Filter1_BASE)
1427 #define DFSDM_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM_Filter2_BASE)
1428 #define DFSDM_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM_Filter3_BASE)
1429 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1430 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1431 #define RCC ((RCC_TypeDef *) RCC_BASE)
1432 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1433 #define CRC ((CRC_TypeDef *) CRC_BASE)
1434 #define TSC ((TSC_TypeDef *) TSC_BASE)
1435
1436 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1437 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1438 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1439 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1440 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1441 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1442 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1443 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1444 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1445 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1446 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1447 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1448 #define AES ((AES_TypeDef *) AES_BASE)
1449 #define RNG ((RNG_TypeDef *) RNG_BASE)
1450
1451
1452 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1453 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1454 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1455 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1456 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1457 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1458 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1459 #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
1460
1461
1462 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1463 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1464 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1465 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1466 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1467 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1468 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1469 #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
1470
1471
1472 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1473 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1474 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1475
1476 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1477
1478 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1479
1480 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1481 /**
1482 * @}
1483 */
1484
1485 /** @addtogroup Exported_constants
1486 * @{
1487 */
1488
1489 /** @addtogroup Peripheral_Registers_Bits_Definition
1490 * @{
1491 */
1492
1493 /******************************************************************************/
1494 /* Peripheral Registers_Bits_Definition */
1495 /******************************************************************************/
1496
1497 /******************************************************************************/
1498 /* */
1499 /* Analog to Digital Converter */
1500 /* */
1501 /******************************************************************************/
1502
1503 /*
1504 * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
1505 */
1506 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1507
1508 /******************** Bit definition for ADC_ISR register *******************/
1509 #define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC ready flag */
1510 #define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling flag */
1511 #define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion flag */
1512 #define ADC_ISR_EOS ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions flag */
1513 #define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< ADC group regular overrun flag */
1514 #define ADC_ISR_JEOC ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion flag */
1515 #define ADC_ISR_JEOS ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions flag */
1516 #define ADC_ISR_AWD1 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 flag */
1517 #define ADC_ISR_AWD2 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 flag */
1518 #define ADC_ISR_AWD3 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 flag */
1519 #define ADC_ISR_JQOVF ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow flag */
1520
1521 /******************** Bit definition for ADC_IER register *******************/
1522 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC ready interrupt */
1523 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< ADC group regular end of sampling interrupt */
1524 #define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< ADC group regular end of unitary conversion interrupt */
1525 #define ADC_IER_EOSIE ((uint32_t)0x00000008U) /*!< ADC group regular end of sequence conversions interrupt */
1526 #define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< ADC group regular overrun interrupt */
1527 #define ADC_IER_JEOCIE ((uint32_t)0x00000020U) /*!< ADC group injected end of unitary conversion interrupt */
1528 #define ADC_IER_JEOSIE ((uint32_t)0x00000040U) /*!< ADC group injected end of sequence conversions interrupt */
1529 #define ADC_IER_AWD1IE ((uint32_t)0x00000080U) /*!< ADC analog watchdog 1 interrupt */
1530 #define ADC_IER_AWD2IE ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 interrupt */
1531 #define ADC_IER_AWD3IE ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 interrupt */
1532 #define ADC_IER_JQOVFIE ((uint32_t)0x00000400U) /*!< ADC group injected contexts queue overflow interrupt */
1533
1534 /* Legacy defines */
1535 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1536 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1537 #define ADC_IER_EOC (ADC_IER_EOCIE)
1538 #define ADC_IER_EOS (ADC_IER_EOSIE)
1539 #define ADC_IER_OVR (ADC_IER_OVRIE)
1540 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
1541 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
1542 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1543 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1544 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1545 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1546
1547 /******************** Bit definition for ADC_CR register ********************/
1548 #define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable */
1549 #define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable */
1550 #define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC group regular conversion start */
1551 #define ADC_CR_JADSTART ((uint32_t)0x00000008U) /*!< ADC group injected conversion start */
1552 #define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC group regular conversion stop */
1553 #define ADC_CR_JADSTP ((uint32_t)0x00000020U) /*!< ADC group injected conversion stop */
1554 #define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC voltage regulator enable */
1555 #define ADC_CR_DEEPPWD ((uint32_t)0x20000000U) /*!< ADC deep power down enable */
1556 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000U) /*!< ADC differential mode for calibration */
1557 #define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */
1558
1559 /******************** Bit definition for ADC_CFGR register ******************/
1560 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001U) /*!< ADC DMA transfer enable */
1561 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002U) /*!< ADC DMA transfer configuration */
1562
1563 #define ADC_CFGR_RES ((uint32_t)0x00000018U) /*!< ADC data resolution */
1564 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008U) /*!< bit 0 */
1565 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010U) /*!< bit 1 */
1566
1567 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020U) /*!< ADC data alignement */
1568
1569 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0U) /*!< ADC group regular external trigger source */
1570 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1571 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1572 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1573 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1574
1575 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00U) /*!< ADC group regular external trigger polarity */
1576 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400U) /*!< bit 0 */
1577 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800U) /*!< bit 1 */
1578
1579 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000U) /*!< ADC group regular overrun configuration */
1580 #define ADC_CFGR_CONT ((uint32_t)0x00002000U) /*!< ADC group regular continuous conversion mode */
1581 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000U) /*!< ADC low power auto wait */
1582
1583 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000U) /*!< ADC group regular sequencer discontinuous mode */
1584
1585 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000U) /*!< ADC Discontinuous mode channel count */
1586 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000U) /*!< bit 0 */
1587 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000U) /*!< bit 1 */
1588 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000U) /*!< bit 2 */
1589
1590 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000U) /*!< ADC Discontinuous mode on injected channels */
1591 #define ADC_CFGR_JQM ((uint32_t)0x00200000U) /*!< ADC group injected contexts queue mode */
1592 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1593 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1594 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1595 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000U) /*!< ADC group injected automatic trigger mode */
1596
1597 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000U) /*!< ADC analog watchdog 1 monitored channel selection */
1598 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
1599 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
1600 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
1601 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
1602 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
1603
1604 #define ADC_CFGR_JQDIS ((uint32_t)0x80000000U) /*!< ADC group injected contexts queue disable */
1605
1606 /******************** Bit definition for ADC_CFGR2 register *****************/
1607 #define ADC_CFGR2_ROVSE ((uint32_t)0x00000001U) /*!< ADC oversampler enable on scope ADC group regular */
1608 #define ADC_CFGR2_JOVSE ((uint32_t)0x00000002U) /*!< ADC oversampler enable on scope ADC group injected */
1609
1610 #define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< ADC oversampling ratio */
1611 #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< bit 0 */
1612 #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< bit 1 */
1613 #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< bit 2 */
1614
1615 #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< ADC oversampling shift */
1616 #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< bit 0 */
1617 #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< bit 1 */
1618 #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< bit 2 */
1619 #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< bit 3 */
1620
1621 #define ADC_CFGR2_TROVS ((uint32_t)0x00000200U) /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1622 #define ADC_CFGR2_ROVSM ((uint32_t)0x00000400U) /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1623
1624 /******************** Bit definition for ADC_SMPR1 register *****************/
1625 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */
1626 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1627 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1628 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1629
1630 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */
1631 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008U) /*!< bit 0 */
1632 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010U) /*!< bit 1 */
1633 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020U) /*!< bit 2 */
1634
1635 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */
1636 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1637 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1638 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1639
1640 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */
1641 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200U) /*!< bit 0 */
1642 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400U) /*!< bit 1 */
1643 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800U) /*!< bit 2 */
1644
1645 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */
1646 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1647 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1648 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1649
1650 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */
1651 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000U) /*!< bit 0 */
1652 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000U) /*!< bit 1 */
1653 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000U) /*!< bit 2 */
1654
1655 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */
1656 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1657 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1658 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1659
1660 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */
1661 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000U) /*!< bit 0 */
1662 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000U) /*!< bit 1 */
1663 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000U) /*!< bit 2 */
1664
1665 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */
1666 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1667 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1668 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1669
1670 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */
1671 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000U) /*!< bit 0 */
1672 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000U) /*!< bit 1 */
1673 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000U) /*!< bit 2 */
1674
1675 /******************** Bit definition for ADC_SMPR2 register *****************/
1676 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */
1677 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1678 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1679 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1680
1681 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */
1682 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< bit 0 */
1683 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< bit 1 */
1684 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< bit 2 */
1685
1686 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */
1687 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1688 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1689 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1690
1691 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */
1692 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< bit 0 */
1693 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< bit 1 */
1694 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< bit 2 */
1695
1696 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */
1697 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1698 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1699 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1700
1701 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 15 sampling time selection */
1702 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< bit 0 */
1703 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< bit 1 */
1704 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< bit 2 */
1705
1706 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */
1707 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1708 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1709 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1710
1711 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */
1712 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< bit 0 */
1713 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< bit 1 */
1714 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< bit 2 */
1715
1716 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */
1717 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1718 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1719 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1720
1721 /******************** Bit definition for ADC_TR1 register *******************/
1722 #define ADC_TR1_LT1 ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */
1723 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1724 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1725 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1726 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1727 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1728 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1729 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1730 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1731 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1732 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1733 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1734 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1735
1736 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000U) /*!< ADC Analog watchdog 1 threshold high */
1737 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000U) /*!< bit 0 */
1738 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000U) /*!< bit 1 */
1739 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000U) /*!< bit 2 */
1740 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000U) /*!< bit 3 */
1741 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000U) /*!< bit 4 */
1742 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000U) /*!< bit 5 */
1743 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000U) /*!< bit 6 */
1744 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000U) /*!< bit 7 */
1745 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000U) /*!< bit 8 */
1746 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000U) /*!< bit 9 */
1747 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000U) /*!< bit 10 */
1748 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000U) /*!< bit 11 */
1749
1750 /******************** Bit definition for ADC_TR2 register *******************/
1751 #define ADC_TR2_LT2 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 2 threshold low */
1752 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1753 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1754 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1755 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1756 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1757 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1758 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1759 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1760
1761 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 2 threshold high */
1762 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000U) /*!< bit 0 */
1763 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000U) /*!< bit 1 */
1764 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000U) /*!< bit 2 */
1765 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000U) /*!< bit 3 */
1766 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000U) /*!< bit 4 */
1767 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000U) /*!< bit 5 */
1768 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000U) /*!< bit 6 */
1769 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000U) /*!< bit 7 */
1770
1771 /******************** Bit definition for ADC_TR3 register *******************/
1772 #define ADC_TR3_LT3 ((uint32_t)0x000000FFU) /*!< ADC analog watchdog 3 threshold low */
1773 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1774 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1775 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1776 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1777 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1778 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1779 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1780 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1781
1782 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000U) /*!< ADC analog watchdog 3 threshold high */
1783 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000U) /*!< bit 0 */
1784 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000U) /*!< bit 1 */
1785 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000U) /*!< bit 2 */
1786 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000U) /*!< bit 3 */
1787 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000U) /*!< bit 4 */
1788 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000U) /*!< bit 5 */
1789 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000U) /*!< bit 6 */
1790 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000U) /*!< bit 7 */
1791
1792 /******************** Bit definition for ADC_SQR1 register ******************/
1793 #define ADC_SQR1_L ((uint32_t)0x0000000FU) /*!< ADC group regular sequencer scan length */
1794 #define ADC_SQR1_L_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1795 #define ADC_SQR1_L_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1796 #define ADC_SQR1_L_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1797 #define ADC_SQR1_L_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1798
1799 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 1 */
1800 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1801 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1802 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1803 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1804 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400U) /*!< bit 4 */
1805
1806 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 2 */
1807 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1808 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1809 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1810 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000U) /*!< bit 3 */
1811 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000U) /*!< bit 4 */
1812
1813 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 3 */
1814 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1815 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1816 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1817 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000U) /*!< bit 3 */
1818 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000U) /*!< bit 4 */
1819
1820 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 4 */
1821 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1822 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1823 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1824 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000U) /*!< bit 3 */
1825 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000U) /*!< bit 4 */
1826
1827 /******************** Bit definition for ADC_SQR2 register ******************/
1828 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 5 */
1829 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1830 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1831 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1832 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1833 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1834
1835 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 6 */
1836 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1837 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1838 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1839 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1840 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400U) /*!< bit 4 */
1841
1842 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 7 */
1843 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1844 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1845 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1846 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000U) /*!< bit 3 */
1847 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000U) /*!< bit 4 */
1848
1849 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 8 */
1850 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1851 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1852 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1853 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000U) /*!< bit 3 */
1854 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000U) /*!< bit 4 */
1855
1856 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 9 */
1857 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1858 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1859 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1860 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000U) /*!< bit 3 */
1861 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000U) /*!< bit 4 */
1862
1863 /******************** Bit definition for ADC_SQR3 register ******************/
1864 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 10 */
1865 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1866 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1867 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1868 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1869 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1870
1871 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 11 */
1872 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1873 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1874 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1875 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1876 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400U) /*!< bit 4 */
1877
1878 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000U) /*!< ADC group regular sequencer rank 12 */
1879 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000U) /*!< bit 0 */
1880 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000U) /*!< bit 1 */
1881 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000U) /*!< bit 2 */
1882 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000U) /*!< bit 3 */
1883 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000U) /*!< bit 4 */
1884
1885 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000U) /*!< ADC group regular sequencer rank 13 */
1886 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000U) /*!< bit 0 */
1887 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000U) /*!< bit 1 */
1888 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000U) /*!< bit 2 */
1889 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000U) /*!< bit 3 */
1890 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000U) /*!< bit 4 */
1891
1892 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000U) /*!< ADC group regular sequencer rank 14 */
1893 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000U) /*!< bit 0 */
1894 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000U) /*!< bit 1 */
1895 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000U) /*!< bit 2 */
1896 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000U) /*!< bit 3 */
1897 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000U) /*!< bit 4 */
1898
1899 /******************** Bit definition for ADC_SQR4 register ******************/
1900 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 15 */
1901 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1902 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1903 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1904 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1905 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010U) /*!<5 bit 4 */
1906
1907 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0U) /*!< ADC group regular sequencer rank 16 */
1908 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1909 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1910 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100U) /*!< bit 2 */
1911 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200U) /*!< bit 3 */
1912 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400U) /*!< bit 4 */
1913
1914 /******************** Bit definition for ADC_DR register ********************/
1915 #define ADC_DR_RDATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */
1916 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1917 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1918 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1919 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1920 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1921 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1922 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1923 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1924 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1925 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1926 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1927 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1928 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
1929 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
1930 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
1931 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
1932
1933 /******************** Bit definition for ADC_JSQR register ******************/
1934 #define ADC_JSQR_JL ((uint32_t)0x00000003U) /*!< ADC group injected sequencer scan length */
1935 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1936 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1937
1938 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003CU) /*!< ADC group injected external trigger source */
1939 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004U) /*!< bit 0 */
1940 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008U) /*!< bit 1 */
1941 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010U) /*!< bit 2 */
1942 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020U) /*!< bit 3 */
1943
1944 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0U) /*!< ADC group injected external trigger polarity */
1945 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040U) /*!< bit 0 */
1946 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080U) /*!< bit 1 */
1947
1948 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00U) /*!< ADC group injected sequencer rank 1 */
1949 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100U) /*!< bit 0 */
1950 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200U) /*!< bit 1 */
1951 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400U) /*!< bit 2 */
1952 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800U) /*!< bit 3 */
1953 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000U) /*!< bit 4 */
1954
1955 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000U) /*!< ADC group injected sequencer rank 2 */
1956 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000U) /*!< bit 0 */
1957 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000U) /*!< bit 1 */
1958 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000U) /*!< bit 2 */
1959 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000U) /*!< bit 3 */
1960 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000U) /*!< bit 4 */
1961
1962 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000U) /*!< ADC group injected sequencer rank 3 */
1963 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000U) /*!< bit 0 */
1964 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000U) /*!< bit 1 */
1965 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000U) /*!< bit 2 */
1966 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000U) /*!< bit 3 */
1967 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000U) /*!< bit 4 */
1968
1969 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000U) /*!< ADC group injected sequencer rank 4 */
1970 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000U) /*!< bit 0 */
1971 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000U) /*!< bit 1 */
1972 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000U) /*!< bit 2 */
1973 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000U) /*!< bit 3 */
1974 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000U) /*!< bit 4 */
1975
1976
1977 /******************** Bit definition for ADC_OFR1 register ******************/
1978 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC offset number 1 offset level */
1979 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001U) /*!< bit 0 */
1980 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002U) /*!< bit 1 */
1981 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004U) /*!< bit 2 */
1982 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008U) /*!< bit 3 */
1983 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010U) /*!< bit 4 */
1984 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020U) /*!< bit 5 */
1985 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040U) /*!< bit 6 */
1986 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080U) /*!< bit 7 */
1987 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100U) /*!< bit 8 */
1988 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200U) /*!< bit 9 */
1989 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400U) /*!< bit 10 */
1990 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800U) /*!< bit 11 */
1991
1992 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 1 channel selection */
1993 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
1994 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
1995 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
1996 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
1997 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
1998
1999 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000U) /*!< ADC offset number 1 enable */
2000
2001 /******************** Bit definition for ADC_OFR2 register ******************/
2002 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC offset number 2 offset level */
2003 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2004 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2005 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2006 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2007 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2008 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2009 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2010 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2011 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2012 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2013 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2014 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2015
2016 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 2 channel selection */
2017 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
2018 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
2019 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
2020 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
2021 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
2022
2023 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000U) /*!< ADC offset number 2 enable */
2024
2025 /******************** Bit definition for ADC_OFR3 register ******************/
2026 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC offset number 3 offset level */
2027 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2028 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2029 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2030 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2031 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2032 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2033 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2034 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2035 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2036 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2037 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2038 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2039
2040 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 3 channel selection */
2041 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
2042 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
2043 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
2044 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
2045 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
2046
2047 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000U) /*!< ADC offset number 3 enable */
2048
2049 /******************** Bit definition for ADC_OFR4 register ******************/
2050 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC offset number 4 offset level */
2051 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2052 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2053 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2054 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2055 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2056 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2057 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2058 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2059 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2060 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2061 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2062 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2063
2064 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000U) /*!< ADC offset number 4 channel selection */
2065 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000U) /*!< bit 0 */
2066 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000U) /*!< bit 1 */
2067 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000U) /*!< bit 2 */
2068 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000U) /*!< bit 3 */
2069 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000U) /*!< bit 4 */
2070
2071 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000U) /*!< ADC offset number 4 enable */
2072
2073 /******************** Bit definition for ADC_JDR1 register ******************/
2074 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */
2075 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2076 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2077 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2078 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2079 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2080 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2081 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2082 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2083 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2084 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2085 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2086 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2087 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
2088 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
2089 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
2090 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
2091
2092 /******************** Bit definition for ADC_JDR2 register ******************/
2093 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */
2094 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2095 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2096 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2097 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2098 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2099 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2100 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2101 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2102 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2103 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2104 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2105 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2106 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
2107 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
2108 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
2109 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
2110
2111 /******************** Bit definition for ADC_JDR3 register ******************/
2112 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */
2113 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2114 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2115 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2116 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2117 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2118 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2119 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2120 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2121 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2122 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2123 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2124 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2125 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
2126 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
2127 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
2128 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
2129
2130 /******************** Bit definition for ADC_JDR4 register ******************/
2131 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */
2132 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2133 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2134 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2135 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2136 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2137 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2138 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2139 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2140 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2141 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2142 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2143 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2144 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
2145 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
2146 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
2147 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
2148
2149 /******************** Bit definition for ADC_AWD2CR register ****************/
2150 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 2 monitored channel selection */
2151 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 2 monitoring channel 0 */
2152 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 2 monitoring channel 1 */
2153 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 2 monitoring channel 2 */
2154 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 2 monitoring channel 3 */
2155 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 2 monitoring channel 4 */
2156 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 2 monitoring channel 5 */
2157 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 2 monitoring channel 6 */
2158 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 2 monitoring channel 7 */
2159 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 2 monitoring channel 8 */
2160 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 2 monitoring channel 9 */
2161 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 2 monitoring channel 10 */
2162 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 2 monitoring channel 11 */
2163 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 2 monitoring channel 12 */
2164 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 2 monitoring channel 13 */
2165 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 2 monitoring channel 14 */
2166 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 2 monitoring channel 15 */
2167 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 2 monitoring channel 16 */
2168 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 2 monitoring channel 17 */
2169 #define ADC_AWD2CR_AWD2CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 2 monitoring channel 18 */
2170
2171 /******************** Bit definition for ADC_AWD3CR register ****************/
2172 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFFU) /*!< ADC analog watchdog 3 monitored channel selection */
2173 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000001U) /*!< ADC analog watchdog 3 monitoring channel 0 */
2174 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000002U) /*!< ADC analog watchdog 3 monitoring channel 1 */
2175 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000004U) /*!< ADC analog watchdog 3 monitoring channel 2 */
2176 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000008U) /*!< ADC analog watchdog 3 monitoring channel 3 */
2177 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000010U) /*!< ADC analog watchdog 3 monitoring channel 4 */
2178 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000020U) /*!< ADC analog watchdog 3 monitoring channel 5 */
2179 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000040U) /*!< ADC analog watchdog 3 monitoring channel 6 */
2180 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000080U) /*!< ADC analog watchdog 3 monitoring channel 7 */
2181 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000100U) /*!< ADC analog watchdog 3 monitoring channel 8 */
2182 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000200U) /*!< ADC analog watchdog 3 monitoring channel 9 */
2183 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000400U) /*!< ADC analog watchdog 3 monitoring channel 10 */
2184 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00000800U) /*!< ADC analog watchdog 3 monitoring channel 11 */
2185 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00001000U) /*!< ADC analog watchdog 3 monitoring channel 12 */
2186 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00002000U) /*!< ADC analog watchdog 3 monitoring channel 13 */
2187 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00004000U) /*!< ADC analog watchdog 3 monitoring channel 14 */
2188 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00008000U) /*!< ADC analog watchdog 3 monitoring channel 15 */
2189 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00010000U) /*!< ADC analog watchdog 3 monitoring channel 16 */
2190 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00020000U) /*!< ADC analog watchdog 3 monitoring channel 17 */
2191 #define ADC_AWD3CR_AWD3CH_18 ((uint32_t)0x00040000U) /*!< ADC analog watchdog 3 monitoring channel 18 */
2192
2193 /******************** Bit definition for ADC_DIFSEL register ****************/
2194 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFFU) /*!< ADC channel differential or single-ended mode */
2195 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2196 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2197 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2198 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2199 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2200 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2201 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2202 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2203 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2204 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2205 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2206 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2207 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00001000U) /*!< bit 12 */
2208 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00002000U) /*!< bit 13 */
2209 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00004000U) /*!< bit 14 */
2210 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00008000U) /*!< bit 15 */
2211 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00010000U) /*!< bit 16 */
2212 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00020000U) /*!< bit 17 */
2213 #define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00040000U) /*!< bit 18 */
2214
2215 /******************** Bit definition for ADC_CALFACT register ***************/
2216 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007FU) /*!< ADC calibration factor in single-ended mode */
2217 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2218 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2219 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2220 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2221 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2222 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2223 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2224
2225 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000U) /*!< ADC calibration factor in differential mode */
2226 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000U) /*!< bit 0 */
2227 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000U) /*!< bit 1 */
2228 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000U) /*!< bit 2 */
2229 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000U) /*!< bit 3 */
2230 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000U) /*!< bit 4 */
2231 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000U) /*!< bit 5 */
2232 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000U) /*!< bit 6 */
2233
2234 /************************* ADC Common registers *****************************/
2235 /******************** Bit definition for ADC_CSR register *******************/
2236 #define ADC_CSR_ADRDY_MST ((uint32_t)0x00000001U) /*!< ADC multimode master ready flag */
2237 #define ADC_CSR_EOSMP_MST ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of sampling flag */
2238 #define ADC_CSR_EOC_MST ((uint32_t)0x00000004U) /*!< ADC multimode master group regular end of unitary conversion flag */
2239 #define ADC_CSR_EOS_MST ((uint32_t)0x00000008U) /*!< ADC multimode master group regular end of sequence conversions flag */
2240 #define ADC_CSR_OVR_MST ((uint32_t)0x00000010U) /*!< ADC multimode master group regular overrun flag */
2241 #define ADC_CSR_JEOC_MST ((uint32_t)0x00000020U) /*!< ADC multimode master group injected end of unitary conversion flag */
2242 #define ADC_CSR_JEOS_MST ((uint32_t)0x00000040U) /*!< ADC multimode master group injected end of sequence conversions flag */
2243 #define ADC_CSR_AWD1_MST ((uint32_t)0x00000080U) /*!< ADC multimode master analog watchdog 1 flag */
2244 #define ADC_CSR_AWD2_MST ((uint32_t)0x00000100U) /*!< ADC multimode master analog watchdog 2 flag */
2245 #define ADC_CSR_AWD3_MST ((uint32_t)0x00000200U) /*!< ADC multimode master analog watchdog 3 flag */
2246 #define ADC_CSR_JQOVF_MST ((uint32_t)0x00000400U) /*!< ADC multimode master group injected contexts queue overflow flag */
2247
2248 #define ADC_CSR_ADRDY_SLV ((uint32_t)0x00010000U) /*!< ADC multimode slave ready flag */
2249 #define ADC_CSR_EOSMP_SLV ((uint32_t)0x00020000U) /*!< ADC multimode slave group regular end of sampling flag */
2250 #define ADC_CSR_EOC_SLV ((uint32_t)0x00040000U) /*!< ADC multimode slave group regular end of unitary conversion flag */
2251 #define ADC_CSR_EOS_SLV ((uint32_t)0x00080000U) /*!< ADC multimode slave group regular end of sequence conversions flag */
2252 #define ADC_CSR_OVR_SLV ((uint32_t)0x00100000U) /*!< ADC multimode slave group regular overrun flag */
2253 #define ADC_CSR_JEOC_SLV ((uint32_t)0x00200000U) /*!< ADC multimode slave group injected end of unitary conversion flag */
2254 #define ADC_CSR_JEOS_SLV ((uint32_t)0x00400000U) /*!< ADC multimode slave group injected end of sequence conversions flag */
2255 #define ADC_CSR_AWD1_SLV ((uint32_t)0x00800000U) /*!< ADC multimode slave analog watchdog 1 flag */
2256 #define ADC_CSR_AWD2_SLV ((uint32_t)0x01000000U) /*!< ADC multimode slave analog watchdog 2 flag */
2257 #define ADC_CSR_AWD3_SLV ((uint32_t)0x02000000U) /*!< ADC multimode slave analog watchdog 3 flag */
2258 #define ADC_CSR_JQOVF_SLV ((uint32_t)0x04000000U) /*!< ADC multimode slave group injected contexts queue overflow flag */
2259
2260 /******************** Bit definition for ADC_CCR register *******************/
2261 #define ADC_CCR_DUAL ((uint32_t)0x0000001FU) /*!< ADC multimode mode selection */
2262 #define ADC_CCR_DUAL_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2263 #define ADC_CCR_DUAL_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2264 #define ADC_CCR_DUAL_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2265 #define ADC_CCR_DUAL_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2266 #define ADC_CCR_DUAL_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2267
2268 #define ADC_CCR_DELAY ((uint32_t)0x00000F00U) /*!< ADC multimode delay between 2 sampling phases */
2269 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100U) /*!< bit 0 */
2270 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200U) /*!< bit 1 */
2271 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400U) /*!< bit 2 */
2272 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800U) /*!< bit 3 */
2273
2274 #define ADC_CCR_DMACFG ((uint32_t)0x00002000U) /*!< ADC multimode DMA transfer configuration */
2275
2276 #define ADC_CCR_MDMA ((uint32_t)0x0000C000U) /*!< ADC multimode DMA transfer enable */
2277 #define ADC_CCR_MDMA_0 ((uint32_t)0x00004000U) /*!< bit 0 */
2278 #define ADC_CCR_MDMA_1 ((uint32_t)0x00008000U) /*!< bit 1 */
2279
2280 #define ADC_CCR_CKMODE ((uint32_t)0x00030000U) /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2281 #define ADC_CCR_CKMODE_0 ((uint32_t)0x00010000U) /*!< bit 0 */
2282 #define ADC_CCR_CKMODE_1 ((uint32_t)0x00020000U) /*!< bit 1 */
2283
2284 #define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< ADC common clock prescaler, only for clock source asynchronous */
2285 #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< bit 0 */
2286 #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< bit 1 */
2287 #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< bit 2 */
2288 #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< bit 3 */
2289
2290 #define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< ADC internal path to VrefInt enable */
2291 #define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< ADC internal path to temperature sensor enable */
2292 #define ADC_CCR_VBATEN ((uint32_t)0x01000000U) /*!< ADC internal path to battery voltage enable */
2293
2294 /******************** Bit definition for ADC_CDR register *******************/
2295 #define ADC_CDR_RDATA_MST ((uint32_t)0x0000FFFFU) /*!< ADC multimode master group regular conversion data */
2296 #define ADC_CDR_RDATA_MST_0 ((uint32_t)0x00000001U) /*!< bit 0 */
2297 #define ADC_CDR_RDATA_MST_1 ((uint32_t)0x00000002U) /*!< bit 1 */
2298 #define ADC_CDR_RDATA_MST_2 ((uint32_t)0x00000004U) /*!< bit 2 */
2299 #define ADC_CDR_RDATA_MST_3 ((uint32_t)0x00000008U) /*!< bit 3 */
2300 #define ADC_CDR_RDATA_MST_4 ((uint32_t)0x00000010U) /*!< bit 4 */
2301 #define ADC_CDR_RDATA_MST_5 ((uint32_t)0x00000020U) /*!< bit 5 */
2302 #define ADC_CDR_RDATA_MST_6 ((uint32_t)0x00000040U) /*!< bit 6 */
2303 #define ADC_CDR_RDATA_MST_7 ((uint32_t)0x00000080U) /*!< bit 7 */
2304 #define ADC_CDR_RDATA_MST_8 ((uint32_t)0x00000100U) /*!< bit 8 */
2305 #define ADC_CDR_RDATA_MST_9 ((uint32_t)0x00000200U) /*!< bit 9 */
2306 #define ADC_CDR_RDATA_MST_10 ((uint32_t)0x00000400U) /*!< bit 10 */
2307 #define ADC_CDR_RDATA_MST_11 ((uint32_t)0x00000800U) /*!< bit 11 */
2308 #define ADC_CDR_RDATA_MST_12 ((uint32_t)0x00001000U) /*!< bit 12 */
2309 #define ADC_CDR_RDATA_MST_13 ((uint32_t)0x00002000U) /*!< bit 13 */
2310 #define ADC_CDR_RDATA_MST_14 ((uint32_t)0x00004000U) /*!< bit 14 */
2311 #define ADC_CDR_RDATA_MST_15 ((uint32_t)0x00008000U) /*!< bit 15 */
2312
2313 #define ADC_CDR_RDATA_SLV ((uint32_t)0xFFFF0000U) /*!< ADC multimode slave group regular conversion data */
2314 #define ADC_CDR_RDATA_SLV_0 ((uint32_t)0x00010000U) /*!< bit 0 */
2315 #define ADC_CDR_RDATA_SLV_1 ((uint32_t)0x00020000U) /*!< bit 1 */
2316 #define ADC_CDR_RDATA_SLV_2 ((uint32_t)0x00040000U) /*!< bit 2 */
2317 #define ADC_CDR_RDATA_SLV_3 ((uint32_t)0x00080000U) /*!< bit 3 */
2318 #define ADC_CDR_RDATA_SLV_4 ((uint32_t)0x00100000U) /*!< bit 4 */
2319 #define ADC_CDR_RDATA_SLV_5 ((uint32_t)0x00200000U) /*!< bit 5 */
2320 #define ADC_CDR_RDATA_SLV_6 ((uint32_t)0x00400000U) /*!< bit 6 */
2321 #define ADC_CDR_RDATA_SLV_7 ((uint32_t)0x00800000U) /*!< bit 7 */
2322 #define ADC_CDR_RDATA_SLV_8 ((uint32_t)0x01000000U) /*!< bit 8 */
2323 #define ADC_CDR_RDATA_SLV_9 ((uint32_t)0x02000000U) /*!< bit 9 */
2324 #define ADC_CDR_RDATA_SLV_10 ((uint32_t)0x04000000U) /*!< bit 10 */
2325 #define ADC_CDR_RDATA_SLV_11 ((uint32_t)0x08000000U) /*!< bit 11 */
2326 #define ADC_CDR_RDATA_SLV_12 ((uint32_t)0x10000000U) /*!< bit 12 */
2327 #define ADC_CDR_RDATA_SLV_13 ((uint32_t)0x20000000U) /*!< bit 13 */
2328 #define ADC_CDR_RDATA_SLV_14 ((uint32_t)0x40000000U) /*!< bit 14 */
2329 #define ADC_CDR_RDATA_SLV_15 ((uint32_t)0x80000000U) /*!< bit 15 */
2330
2331 /******************************************************************************/
2332 /* */
2333 /* Controller Area Network */
2334 /* */
2335 /******************************************************************************/
2336 /*!<CAN control and status registers */
2337 /******************* Bit definition for CAN_MCR register ********************/
2338 #define CAN_MCR_INRQ ((uint16_t)0x0001U) /*!<Initialization Request */
2339 #define CAN_MCR_SLEEP ((uint16_t)0x0002U) /*!<Sleep Mode Request */
2340 #define CAN_MCR_TXFP ((uint16_t)0x0004U) /*!<Transmit FIFO Priority */
2341 #define CAN_MCR_RFLM ((uint16_t)0x0008U) /*!<Receive FIFO Locked Mode */
2342 #define CAN_MCR_NART ((uint16_t)0x0010U) /*!<No Automatic Retransmission */
2343 #define CAN_MCR_AWUM ((uint16_t)0x0020U) /*!<Automatic Wakeup Mode */
2344 #define CAN_MCR_ABOM ((uint16_t)0x0040U) /*!<Automatic Bus-Off Management */
2345 #define CAN_MCR_TTCM ((uint16_t)0x0080U) /*!<Time Triggered Communication Mode */
2346 #define CAN_MCR_RESET ((uint16_t)0x8000U) /*!<bxCAN software master reset */
2347
2348 /******************* Bit definition for CAN_MSR register ********************/
2349 #define CAN_MSR_INAK ((uint16_t)0x0001U) /*!<Initialization Acknowledge */
2350 #define CAN_MSR_SLAK ((uint16_t)0x0002U) /*!<Sleep Acknowledge */
2351 #define CAN_MSR_ERRI ((uint16_t)0x0004U) /*!<Error Interrupt */
2352 #define CAN_MSR_WKUI ((uint16_t)0x0008U) /*!<Wakeup Interrupt */
2353 #define CAN_MSR_SLAKI ((uint16_t)0x0010U) /*!<Sleep Acknowledge Interrupt */
2354 #define CAN_MSR_TXM ((uint16_t)0x0100U) /*!<Transmit Mode */
2355 #define CAN_MSR_RXM ((uint16_t)0x0200U) /*!<Receive Mode */
2356 #define CAN_MSR_SAMP ((uint16_t)0x0400U) /*!<Last Sample Point */
2357 #define CAN_MSR_RX ((uint16_t)0x0800U) /*!<CAN Rx Signal */
2358
2359 /******************* Bit definition for CAN_TSR register ********************/
2360 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001U) /*!<Request Completed Mailbox0 */
2361 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002U) /*!<Transmission OK of Mailbox0 */
2362 #define CAN_TSR_ALST0 ((uint32_t)0x00000004U) /*!<Arbitration Lost for Mailbox0 */
2363 #define CAN_TSR_TERR0 ((uint32_t)0x00000008U) /*!<Transmission Error of Mailbox0 */
2364 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080U) /*!<Abort Request for Mailbox0 */
2365 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100U) /*!<Request Completed Mailbox1 */
2366 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200U) /*!<Transmission OK of Mailbox1 */
2367 #define CAN_TSR_ALST1 ((uint32_t)0x00000400U) /*!<Arbitration Lost for Mailbox1 */
2368 #define CAN_TSR_TERR1 ((uint32_t)0x00000800U) /*!<Transmission Error of Mailbox1 */
2369 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000U) /*!<Abort Request for Mailbox 1 */
2370 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000U) /*!<Request Completed Mailbox2 */
2371 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000U) /*!<Transmission OK of Mailbox 2 */
2372 #define CAN_TSR_ALST2 ((uint32_t)0x00040000U) /*!<Arbitration Lost for mailbox 2 */
2373 #define CAN_TSR_TERR2 ((uint32_t)0x00080000U) /*!<Transmission Error of Mailbox 2 */
2374 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000U) /*!<Abort Request for Mailbox 2 */
2375 #define CAN_TSR_CODE ((uint32_t)0x03000000U) /*!<Mailbox Code */
2376
2377 #define CAN_TSR_TME ((uint32_t)0x1C000000U) /*!<TME[2:0] bits */
2378 #define CAN_TSR_TME0 ((uint32_t)0x04000000U) /*!<Transmit Mailbox 0 Empty */
2379 #define CAN_TSR_TME1 ((uint32_t)0x08000000U) /*!<Transmit Mailbox 1 Empty */
2380 #define CAN_TSR_TME2 ((uint32_t)0x10000000U) /*!<Transmit Mailbox 2 Empty */
2381
2382 #define CAN_TSR_LOW ((uint32_t)0xE0000000U) /*!<LOW[2:0] bits */
2383 #define CAN_TSR_LOW0 ((uint32_t)0x20000000U) /*!<Lowest Priority Flag for Mailbox 0 */
2384 #define CAN_TSR_LOW1 ((uint32_t)0x40000000U) /*!<Lowest Priority Flag for Mailbox 1 */
2385 #define CAN_TSR_LOW2 ((uint32_t)0x80000000U) /*!<Lowest Priority Flag for Mailbox 2 */
2386
2387 /******************* Bit definition for CAN_RF0R register *******************/
2388 #define CAN_RF0R_FMP0 ((uint8_t)0x03U) /*!<FIFO 0 Message Pending */
2389 #define CAN_RF0R_FULL0 ((uint8_t)0x08U) /*!<FIFO 0 Full */
2390 #define CAN_RF0R_FOVR0 ((uint8_t)0x10U) /*!<FIFO 0 Overrun */
2391 #define CAN_RF0R_RFOM0 ((uint8_t)0x20U) /*!<Release FIFO 0 Output Mailbox */
2392
2393 /******************* Bit definition for CAN_RF1R register *******************/
2394 #define CAN_RF1R_FMP1 ((uint8_t)0x03U) /*!<FIFO 1 Message Pending */
2395 #define CAN_RF1R_FULL1 ((uint8_t)0x08U) /*!<FIFO 1 Full */
2396 #define CAN_RF1R_FOVR1 ((uint8_t)0x10U) /*!<FIFO 1 Overrun */
2397 #define CAN_RF1R_RFOM1 ((uint8_t)0x20U) /*!<Release FIFO 1 Output Mailbox */
2398
2399 /******************** Bit definition for CAN_IER register *******************/
2400 #define CAN_IER_TMEIE ((uint32_t)0x00000001U) /*!<Transmit Mailbox Empty Interrupt Enable */
2401 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002U) /*!<FIFO Message Pending Interrupt Enable */
2402 #define CAN_IER_FFIE0 ((uint32_t)0x00000004U) /*!<FIFO Full Interrupt Enable */
2403 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008U) /*!<FIFO Overrun Interrupt Enable */
2404 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010U) /*!<FIFO Message Pending Interrupt Enable */
2405 #define CAN_IER_FFIE1 ((uint32_t)0x00000020U) /*!<FIFO Full Interrupt Enable */
2406 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040U) /*!<FIFO Overrun Interrupt Enable */
2407 #define CAN_IER_EWGIE ((uint32_t)0x00000100U) /*!<Error Warning Interrupt Enable */
2408 #define CAN_IER_EPVIE ((uint32_t)0x00000200U) /*!<Error Passive Interrupt Enable */
2409 #define CAN_IER_BOFIE ((uint32_t)0x00000400U) /*!<Bus-Off Interrupt Enable */
2410 #define CAN_IER_LECIE ((uint32_t)0x00000800U) /*!<Last Error Code Interrupt Enable */
2411 #define CAN_IER_ERRIE ((uint32_t)0x00008000U) /*!<Error Interrupt Enable */
2412 #define CAN_IER_WKUIE ((uint32_t)0x00010000U) /*!<Wakeup Interrupt Enable */
2413 #define CAN_IER_SLKIE ((uint32_t)0x00020000U) /*!<Sleep Interrupt Enable */
2414
2415 /******************** Bit definition for CAN_ESR register *******************/
2416 #define CAN_ESR_EWGF ((uint32_t)0x00000001U) /*!<Error Warning Flag */
2417 #define CAN_ESR_EPVF ((uint32_t)0x00000002U) /*!<Error Passive Flag */
2418 #define CAN_ESR_BOFF ((uint32_t)0x00000004U) /*!<Bus-Off Flag */
2419
2420 #define CAN_ESR_LEC ((uint32_t)0x00000070U) /*!<LEC[2:0] bits (Last Error Code) */
2421 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
2422 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
2423 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
2424
2425 #define CAN_ESR_TEC ((uint32_t)0x00FF0000U) /*!<Least significant byte of the 9-bit Transmit Error Counter */
2426 #define CAN_ESR_REC ((uint32_t)0xFF000000U) /*!<Receive Error Counter */
2427
2428 /******************* Bit definition for CAN_BTR register ********************/
2429 #define CAN_BTR_BRP ((uint32_t)0x000003FFU) /*!<Baud Rate Prescaler */
2430 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000U) /*!<Time Segment 1 (Bit 0) */
2431 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000U) /*!<Time Segment 1 (Bit 1) */
2432 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000U) /*!<Time Segment 1 (Bit 2) */
2433 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000U) /*!<Time Segment 1 (Bit 3) */
2434 #define CAN_BTR_TS1 ((uint32_t)0x000F0000U) /*!<Time Segment 1 */
2435 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000U) /*!<Time Segment 2 (Bit 0) */
2436 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000U) /*!<Time Segment 2 (Bit 1) */
2437 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000U) /*!<Time Segment 2 (Bit 2) */
2438 #define CAN_BTR_TS2 ((uint32_t)0x00700000U) /*!<Time Segment 2 */
2439 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000U) /*!<Resynchronization Jump Width (Bit 0) */
2440 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000U) /*!<Resynchronization Jump Width (Bit 1) */
2441 #define CAN_BTR_SJW ((uint32_t)0x03000000U) /*!<Resynchronization Jump Width */
2442 #define CAN_BTR_LBKM ((uint32_t)0x40000000U) /*!<Loop Back Mode (Debug) */
2443 #define CAN_BTR_SILM ((uint32_t)0x80000000U) /*!<Silent Mode */
2444
2445 /*!<Mailbox registers */
2446 /****************** Bit definition for CAN_TI0R register ********************/
2447 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
2448 #define CAN_TI0R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2449 #define CAN_TI0R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2450 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
2451 #define CAN_TI0R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2452
2453 /****************** Bit definition for CAN_TDT0R register *******************/
2454 #define CAN_TDT0R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2455 #define CAN_TDT0R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
2456 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2457
2458 /****************** Bit definition for CAN_TDL0R register *******************/
2459 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2460 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2461 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2462 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2463
2464 /****************** Bit definition for CAN_TDH0R register *******************/
2465 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2466 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2467 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2468 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2469
2470 /******************* Bit definition for CAN_TI1R register *******************/
2471 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
2472 #define CAN_TI1R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2473 #define CAN_TI1R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2474 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
2475 #define CAN_TI1R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2476
2477 /******************* Bit definition for CAN_TDT1R register ******************/
2478 #define CAN_TDT1R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2479 #define CAN_TDT1R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
2480 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2481
2482 /******************* Bit definition for CAN_TDL1R register ******************/
2483 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2484 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2485 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2486 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2487
2488 /******************* Bit definition for CAN_TDH1R register ******************/
2489 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2490 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2491 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2492 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2493
2494 /******************* Bit definition for CAN_TI2R register *******************/
2495 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001U) /*!<Transmit Mailbox Request */
2496 #define CAN_TI2R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2497 #define CAN_TI2R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2498 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended identifier */
2499 #define CAN_TI2R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2500
2501 /******************* Bit definition for CAN_TDT2R register ******************/
2502 #define CAN_TDT2R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2503 #define CAN_TDT2R_TGT ((uint32_t)0x00000100U) /*!<Transmit Global Time */
2504 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2505
2506 /******************* Bit definition for CAN_TDL2R register ******************/
2507 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2508 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2509 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2510 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2511
2512 /******************* Bit definition for CAN_TDH2R register ******************/
2513 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2514 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2515 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2516 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2517
2518 /******************* Bit definition for CAN_RI0R register *******************/
2519 #define CAN_RI0R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2520 #define CAN_RI0R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2521 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended Identifier */
2522 #define CAN_RI0R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2523
2524 /******************* Bit definition for CAN_RDT0R register ******************/
2525 #define CAN_RDT0R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2526 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00U) /*!<Filter Match Index */
2527 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2528
2529 /******************* Bit definition for CAN_RDL0R register ******************/
2530 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2531 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2532 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2533 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2534
2535 /******************* Bit definition for CAN_RDH0R register ******************/
2536 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2537 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2538 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2539 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2540
2541 /******************* Bit definition for CAN_RI1R register *******************/
2542 #define CAN_RI1R_RTR ((uint32_t)0x00000002U) /*!<Remote Transmission Request */
2543 #define CAN_RI1R_IDE ((uint32_t)0x00000004U) /*!<Identifier Extension */
2544 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8U) /*!<Extended identifier */
2545 #define CAN_RI1R_STID ((uint32_t)0xFFE00000U) /*!<Standard Identifier or Extended Identifier */
2546
2547 /******************* Bit definition for CAN_RDT1R register ******************/
2548 #define CAN_RDT1R_DLC ((uint32_t)0x0000000FU) /*!<Data Length Code */
2549 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00U) /*!<Filter Match Index */
2550 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000U) /*!<Message Time Stamp */
2551
2552 /******************* Bit definition for CAN_RDL1R register ******************/
2553 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FFU) /*!<Data byte 0 */
2554 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00U) /*!<Data byte 1 */
2555 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000U) /*!<Data byte 2 */
2556 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000U) /*!<Data byte 3 */
2557
2558 /******************* Bit definition for CAN_RDH1R register ******************/
2559 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FFU) /*!<Data byte 4 */
2560 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00U) /*!<Data byte 5 */
2561 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000U) /*!<Data byte 6 */
2562 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000U) /*!<Data byte 7 */
2563
2564 /*!<CAN filter registers */
2565 /******************* Bit definition for CAN_FMR register ********************/
2566 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
2567
2568 /******************* Bit definition for CAN_FM1R register *******************/
2569 #define CAN_FM1R_FBM ((uint16_t)0x3FFFU) /*!<Filter Mode */
2570 #define CAN_FM1R_FBM0 ((uint16_t)0x0001U) /*!<Filter Init Mode bit 0 */
2571 #define CAN_FM1R_FBM1 ((uint16_t)0x0002U) /*!<Filter Init Mode bit 1 */
2572 #define CAN_FM1R_FBM2 ((uint16_t)0x0004U) /*!<Filter Init Mode bit 2 */
2573 #define CAN_FM1R_FBM3 ((uint16_t)0x0008U) /*!<Filter Init Mode bit 3 */
2574 #define CAN_FM1R_FBM4 ((uint16_t)0x0010U) /*!<Filter Init Mode bit 4 */
2575 #define CAN_FM1R_FBM5 ((uint16_t)0x0020U) /*!<Filter Init Mode bit 5 */
2576 #define CAN_FM1R_FBM6 ((uint16_t)0x0040U) /*!<Filter Init Mode bit 6 */
2577 #define CAN_FM1R_FBM7 ((uint16_t)0x0080U) /*!<Filter Init Mode bit 7 */
2578 #define CAN_FM1R_FBM8 ((uint16_t)0x0100U) /*!<Filter Init Mode bit 8 */
2579 #define CAN_FM1R_FBM9 ((uint16_t)0x0200U) /*!<Filter Init Mode bit 9 */
2580 #define CAN_FM1R_FBM10 ((uint16_t)0x0400U) /*!<Filter Init Mode bit 10 */
2581 #define CAN_FM1R_FBM11 ((uint16_t)0x0800U) /*!<Filter Init Mode bit 11 */
2582 #define CAN_FM1R_FBM12 ((uint16_t)0x1000U) /*!<Filter Init Mode bit 12 */
2583 #define CAN_FM1R_FBM13 ((uint16_t)0x2000U) /*!<Filter Init Mode bit 13 */
2584
2585 /******************* Bit definition for CAN_FS1R register *******************/
2586 #define CAN_FS1R_FSC ((uint16_t)0x3FFFU) /*!<Filter Scale Configuration */
2587 #define CAN_FS1R_FSC0 ((uint16_t)0x0001U) /*!<Filter Scale Configuration bit 0 */
2588 #define CAN_FS1R_FSC1 ((uint16_t)0x0002U) /*!<Filter Scale Configuration bit 1 */
2589 #define CAN_FS1R_FSC2 ((uint16_t)0x0004U) /*!<Filter Scale Configuration bit 2 */
2590 #define CAN_FS1R_FSC3 ((uint16_t)0x0008U) /*!<Filter Scale Configuration bit 3 */
2591 #define CAN_FS1R_FSC4 ((uint16_t)0x0010U) /*!<Filter Scale Configuration bit 4 */
2592 #define CAN_FS1R_FSC5 ((uint16_t)0x0020U) /*!<Filter Scale Configuration bit 5 */
2593 #define CAN_FS1R_FSC6 ((uint16_t)0x0040U) /*!<Filter Scale Configuration bit 6 */
2594 #define CAN_FS1R_FSC7 ((uint16_t)0x0080U) /*!<Filter Scale Configuration bit 7 */
2595 #define CAN_FS1R_FSC8 ((uint16_t)0x0100U) /*!<Filter Scale Configuration bit 8 */
2596 #define CAN_FS1R_FSC9 ((uint16_t)0x0200U) /*!<Filter Scale Configuration bit 9 */
2597 #define CAN_FS1R_FSC10 ((uint16_t)0x0400U) /*!<Filter Scale Configuration bit 10 */
2598 #define CAN_FS1R_FSC11 ((uint16_t)0x0800U) /*!<Filter Scale Configuration bit 11 */
2599 #define CAN_FS1R_FSC12 ((uint16_t)0x1000U) /*!<Filter Scale Configuration bit 12 */
2600 #define CAN_FS1R_FSC13 ((uint16_t)0x2000U) /*!<Filter Scale Configuration bit 13 */
2601
2602 /****************** Bit definition for CAN_FFA1R register *******************/
2603 #define CAN_FFA1R_FFA ((uint16_t)0x3FFFU) /*!<Filter FIFO Assignment */
2604 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001U) /*!<Filter FIFO Assignment for Filter 0 */
2605 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002U) /*!<Filter FIFO Assignment for Filter 1 */
2606 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004U) /*!<Filter FIFO Assignment for Filter 2 */
2607 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008U) /*!<Filter FIFO Assignment for Filter 3 */
2608 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010U) /*!<Filter FIFO Assignment for Filter 4 */
2609 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020U) /*!<Filter FIFO Assignment for Filter 5 */
2610 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040U) /*!<Filter FIFO Assignment for Filter 6 */
2611 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080U) /*!<Filter FIFO Assignment for Filter 7 */
2612 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100U) /*!<Filter FIFO Assignment for Filter 8 */
2613 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200U) /*!<Filter FIFO Assignment for Filter 9 */
2614 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400U) /*!<Filter FIFO Assignment for Filter 10 */
2615 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800U) /*!<Filter FIFO Assignment for Filter 11 */
2616 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000U) /*!<Filter FIFO Assignment for Filter 12 */
2617 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000U) /*!<Filter FIFO Assignment for Filter 13 */
2618
2619 /******************* Bit definition for CAN_FA1R register *******************/
2620 #define CAN_FA1R_FACT ((uint16_t)0x3FFFU) /*!<Filter Active */
2621 #define CAN_FA1R_FACT0 ((uint16_t)0x0001U) /*!<Filter 0 Active */
2622 #define CAN_FA1R_FACT1 ((uint16_t)0x0002U) /*!<Filter 1 Active */
2623 #define CAN_FA1R_FACT2 ((uint16_t)0x0004U) /*!<Filter 2 Active */
2624 #define CAN_FA1R_FACT3 ((uint16_t)0x0008U) /*!<Filter 3 Active */
2625 #define CAN_FA1R_FACT4 ((uint16_t)0x0010U) /*!<Filter 4 Active */
2626 #define CAN_FA1R_FACT5 ((uint16_t)0x0020U) /*!<Filter 5 Active */
2627 #define CAN_FA1R_FACT6 ((uint16_t)0x0040U) /*!<Filter 6 Active */
2628 #define CAN_FA1R_FACT7 ((uint16_t)0x0080U) /*!<Filter 7 Active */
2629 #define CAN_FA1R_FACT8 ((uint16_t)0x0100U) /*!<Filter 8 Active */
2630 #define CAN_FA1R_FACT9 ((uint16_t)0x0200U) /*!<Filter 9 Active */
2631 #define CAN_FA1R_FACT10 ((uint16_t)0x0400U) /*!<Filter 10 Active */
2632 #define CAN_FA1R_FACT11 ((uint16_t)0x0800U) /*!<Filter 11 Active */
2633 #define CAN_FA1R_FACT12 ((uint16_t)0x1000U) /*!<Filter 12 Active */
2634 #define CAN_FA1R_FACT13 ((uint16_t)0x2000U) /*!<Filter 13 Active */
2635
2636 /******************* Bit definition for CAN_F0R1 register *******************/
2637 #define CAN_F0R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2638 #define CAN_F0R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2639 #define CAN_F0R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2640 #define CAN_F0R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2641 #define CAN_F0R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2642 #define CAN_F0R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2643 #define CAN_F0R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2644 #define CAN_F0R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2645 #define CAN_F0R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2646 #define CAN_F0R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2647 #define CAN_F0R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2648 #define CAN_F0R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2649 #define CAN_F0R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2650 #define CAN_F0R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2651 #define CAN_F0R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2652 #define CAN_F0R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2653 #define CAN_F0R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2654 #define CAN_F0R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2655 #define CAN_F0R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2656 #define CAN_F0R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2657 #define CAN_F0R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2658 #define CAN_F0R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2659 #define CAN_F0R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2660 #define CAN_F0R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2661 #define CAN_F0R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2662 #define CAN_F0R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2663 #define CAN_F0R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2664 #define CAN_F0R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2665 #define CAN_F0R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2666 #define CAN_F0R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2667 #define CAN_F0R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2668 #define CAN_F0R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2669
2670 /******************* Bit definition for CAN_F1R1 register *******************/
2671 #define CAN_F1R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2672 #define CAN_F1R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2673 #define CAN_F1R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2674 #define CAN_F1R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2675 #define CAN_F1R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2676 #define CAN_F1R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2677 #define CAN_F1R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2678 #define CAN_F1R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2679 #define CAN_F1R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2680 #define CAN_F1R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2681 #define CAN_F1R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2682 #define CAN_F1R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2683 #define CAN_F1R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2684 #define CAN_F1R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2685 #define CAN_F1R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2686 #define CAN_F1R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2687 #define CAN_F1R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2688 #define CAN_F1R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2689 #define CAN_F1R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2690 #define CAN_F1R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2691 #define CAN_F1R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2692 #define CAN_F1R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2693 #define CAN_F1R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2694 #define CAN_F1R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2695 #define CAN_F1R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2696 #define CAN_F1R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2697 #define CAN_F1R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2698 #define CAN_F1R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2699 #define CAN_F1R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2700 #define CAN_F1R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2701 #define CAN_F1R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2702 #define CAN_F1R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2703
2704 /******************* Bit definition for CAN_F2R1 register *******************/
2705 #define CAN_F2R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2706 #define CAN_F2R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2707 #define CAN_F2R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2708 #define CAN_F2R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2709 #define CAN_F2R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2710 #define CAN_F2R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2711 #define CAN_F2R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2712 #define CAN_F2R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2713 #define CAN_F2R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2714 #define CAN_F2R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2715 #define CAN_F2R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2716 #define CAN_F2R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2717 #define CAN_F2R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2718 #define CAN_F2R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2719 #define CAN_F2R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2720 #define CAN_F2R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2721 #define CAN_F2R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2722 #define CAN_F2R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2723 #define CAN_F2R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2724 #define CAN_F2R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2725 #define CAN_F2R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2726 #define CAN_F2R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2727 #define CAN_F2R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2728 #define CAN_F2R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2729 #define CAN_F2R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2730 #define CAN_F2R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2731 #define CAN_F2R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2732 #define CAN_F2R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2733 #define CAN_F2R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2734 #define CAN_F2R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2735 #define CAN_F2R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2736 #define CAN_F2R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2737
2738 /******************* Bit definition for CAN_F3R1 register *******************/
2739 #define CAN_F3R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2740 #define CAN_F3R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2741 #define CAN_F3R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2742 #define CAN_F3R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2743 #define CAN_F3R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2744 #define CAN_F3R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2745 #define CAN_F3R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2746 #define CAN_F3R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2747 #define CAN_F3R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2748 #define CAN_F3R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2749 #define CAN_F3R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2750 #define CAN_F3R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2751 #define CAN_F3R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2752 #define CAN_F3R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2753 #define CAN_F3R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2754 #define CAN_F3R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2755 #define CAN_F3R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2756 #define CAN_F3R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2757 #define CAN_F3R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2758 #define CAN_F3R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2759 #define CAN_F3R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2760 #define CAN_F3R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2761 #define CAN_F3R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2762 #define CAN_F3R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2763 #define CAN_F3R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2764 #define CAN_F3R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2765 #define CAN_F3R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2766 #define CAN_F3R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2767 #define CAN_F3R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2768 #define CAN_F3R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2769 #define CAN_F3R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2770 #define CAN_F3R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2771
2772 /******************* Bit definition for CAN_F4R1 register *******************/
2773 #define CAN_F4R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2774 #define CAN_F4R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2775 #define CAN_F4R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2776 #define CAN_F4R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2777 #define CAN_F4R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2778 #define CAN_F4R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2779 #define CAN_F4R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2780 #define CAN_F4R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2781 #define CAN_F4R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2782 #define CAN_F4R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2783 #define CAN_F4R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2784 #define CAN_F4R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2785 #define CAN_F4R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2786 #define CAN_F4R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2787 #define CAN_F4R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2788 #define CAN_F4R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2789 #define CAN_F4R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2790 #define CAN_F4R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2791 #define CAN_F4R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2792 #define CAN_F4R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2793 #define CAN_F4R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2794 #define CAN_F4R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2795 #define CAN_F4R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2796 #define CAN_F4R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2797 #define CAN_F4R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2798 #define CAN_F4R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2799 #define CAN_F4R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2800 #define CAN_F4R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2801 #define CAN_F4R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2802 #define CAN_F4R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2803 #define CAN_F4R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2804 #define CAN_F4R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2805
2806 /******************* Bit definition for CAN_F5R1 register *******************/
2807 #define CAN_F5R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2808 #define CAN_F5R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2809 #define CAN_F5R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2810 #define CAN_F5R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2811 #define CAN_F5R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2812 #define CAN_F5R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2813 #define CAN_F5R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2814 #define CAN_F5R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2815 #define CAN_F5R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2816 #define CAN_F5R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2817 #define CAN_F5R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2818 #define CAN_F5R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2819 #define CAN_F5R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2820 #define CAN_F5R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2821 #define CAN_F5R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2822 #define CAN_F5R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2823 #define CAN_F5R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2824 #define CAN_F5R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2825 #define CAN_F5R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2826 #define CAN_F5R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2827 #define CAN_F5R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2828 #define CAN_F5R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2829 #define CAN_F5R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2830 #define CAN_F5R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2831 #define CAN_F5R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2832 #define CAN_F5R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2833 #define CAN_F5R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2834 #define CAN_F5R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2835 #define CAN_F5R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2836 #define CAN_F5R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2837 #define CAN_F5R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2838 #define CAN_F5R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2839
2840 /******************* Bit definition for CAN_F6R1 register *******************/
2841 #define CAN_F6R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2842 #define CAN_F6R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2843 #define CAN_F6R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2844 #define CAN_F6R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2845 #define CAN_F6R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2846 #define CAN_F6R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2847 #define CAN_F6R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2848 #define CAN_F6R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2849 #define CAN_F6R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2850 #define CAN_F6R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2851 #define CAN_F6R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2852 #define CAN_F6R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2853 #define CAN_F6R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2854 #define CAN_F6R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2855 #define CAN_F6R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2856 #define CAN_F6R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2857 #define CAN_F6R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2858 #define CAN_F6R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2859 #define CAN_F6R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2860 #define CAN_F6R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2861 #define CAN_F6R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2862 #define CAN_F6R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2863 #define CAN_F6R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2864 #define CAN_F6R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2865 #define CAN_F6R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2866 #define CAN_F6R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2867 #define CAN_F6R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2868 #define CAN_F6R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2869 #define CAN_F6R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2870 #define CAN_F6R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2871 #define CAN_F6R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2872 #define CAN_F6R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2873
2874 /******************* Bit definition for CAN_F7R1 register *******************/
2875 #define CAN_F7R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2876 #define CAN_F7R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2877 #define CAN_F7R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2878 #define CAN_F7R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2879 #define CAN_F7R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2880 #define CAN_F7R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2881 #define CAN_F7R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2882 #define CAN_F7R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2883 #define CAN_F7R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2884 #define CAN_F7R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2885 #define CAN_F7R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2886 #define CAN_F7R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2887 #define CAN_F7R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2888 #define CAN_F7R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2889 #define CAN_F7R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2890 #define CAN_F7R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2891 #define CAN_F7R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2892 #define CAN_F7R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2893 #define CAN_F7R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2894 #define CAN_F7R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2895 #define CAN_F7R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2896 #define CAN_F7R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2897 #define CAN_F7R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2898 #define CAN_F7R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2899 #define CAN_F7R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2900 #define CAN_F7R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2901 #define CAN_F7R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2902 #define CAN_F7R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2903 #define CAN_F7R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2904 #define CAN_F7R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2905 #define CAN_F7R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2906 #define CAN_F7R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2907
2908 /******************* Bit definition for CAN_F8R1 register *******************/
2909 #define CAN_F8R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2910 #define CAN_F8R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2911 #define CAN_F8R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2912 #define CAN_F8R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2913 #define CAN_F8R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2914 #define CAN_F8R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2915 #define CAN_F8R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2916 #define CAN_F8R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2917 #define CAN_F8R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2918 #define CAN_F8R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2919 #define CAN_F8R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2920 #define CAN_F8R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2921 #define CAN_F8R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2922 #define CAN_F8R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2923 #define CAN_F8R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2924 #define CAN_F8R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2925 #define CAN_F8R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2926 #define CAN_F8R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2927 #define CAN_F8R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2928 #define CAN_F8R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2929 #define CAN_F8R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2930 #define CAN_F8R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2931 #define CAN_F8R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2932 #define CAN_F8R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2933 #define CAN_F8R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2934 #define CAN_F8R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2935 #define CAN_F8R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2936 #define CAN_F8R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2937 #define CAN_F8R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2938 #define CAN_F8R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2939 #define CAN_F8R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2940 #define CAN_F8R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2941
2942 /******************* Bit definition for CAN_F9R1 register *******************/
2943 #define CAN_F9R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2944 #define CAN_F9R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2945 #define CAN_F9R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2946 #define CAN_F9R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2947 #define CAN_F9R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2948 #define CAN_F9R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2949 #define CAN_F9R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2950 #define CAN_F9R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2951 #define CAN_F9R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2952 #define CAN_F9R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2953 #define CAN_F9R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2954 #define CAN_F9R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2955 #define CAN_F9R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2956 #define CAN_F9R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2957 #define CAN_F9R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2958 #define CAN_F9R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2959 #define CAN_F9R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2960 #define CAN_F9R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2961 #define CAN_F9R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2962 #define CAN_F9R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2963 #define CAN_F9R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2964 #define CAN_F9R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2965 #define CAN_F9R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
2966 #define CAN_F9R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
2967 #define CAN_F9R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
2968 #define CAN_F9R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
2969 #define CAN_F9R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
2970 #define CAN_F9R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
2971 #define CAN_F9R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
2972 #define CAN_F9R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
2973 #define CAN_F9R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
2974 #define CAN_F9R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
2975
2976 /******************* Bit definition for CAN_F10R1 register ******************/
2977 #define CAN_F10R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
2978 #define CAN_F10R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
2979 #define CAN_F10R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
2980 #define CAN_F10R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
2981 #define CAN_F10R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
2982 #define CAN_F10R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
2983 #define CAN_F10R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
2984 #define CAN_F10R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
2985 #define CAN_F10R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
2986 #define CAN_F10R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
2987 #define CAN_F10R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
2988 #define CAN_F10R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
2989 #define CAN_F10R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
2990 #define CAN_F10R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
2991 #define CAN_F10R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
2992 #define CAN_F10R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
2993 #define CAN_F10R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
2994 #define CAN_F10R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
2995 #define CAN_F10R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
2996 #define CAN_F10R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
2997 #define CAN_F10R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
2998 #define CAN_F10R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
2999 #define CAN_F10R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3000 #define CAN_F10R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3001 #define CAN_F10R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3002 #define CAN_F10R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3003 #define CAN_F10R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3004 #define CAN_F10R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3005 #define CAN_F10R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3006 #define CAN_F10R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3007 #define CAN_F10R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3008 #define CAN_F10R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3009
3010 /******************* Bit definition for CAN_F11R1 register ******************/
3011 #define CAN_F11R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3012 #define CAN_F11R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3013 #define CAN_F11R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3014 #define CAN_F11R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3015 #define CAN_F11R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3016 #define CAN_F11R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3017 #define CAN_F11R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3018 #define CAN_F11R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3019 #define CAN_F11R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3020 #define CAN_F11R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3021 #define CAN_F11R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3022 #define CAN_F11R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3023 #define CAN_F11R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3024 #define CAN_F11R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3025 #define CAN_F11R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3026 #define CAN_F11R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3027 #define CAN_F11R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3028 #define CAN_F11R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3029 #define CAN_F11R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3030 #define CAN_F11R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3031 #define CAN_F11R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3032 #define CAN_F11R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3033 #define CAN_F11R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3034 #define CAN_F11R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3035 #define CAN_F11R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3036 #define CAN_F11R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3037 #define CAN_F11R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3038 #define CAN_F11R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3039 #define CAN_F11R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3040 #define CAN_F11R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3041 #define CAN_F11R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3042 #define CAN_F11R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3043
3044 /******************* Bit definition for CAN_F12R1 register ******************/
3045 #define CAN_F12R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3046 #define CAN_F12R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3047 #define CAN_F12R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3048 #define CAN_F12R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3049 #define CAN_F12R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3050 #define CAN_F12R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3051 #define CAN_F12R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3052 #define CAN_F12R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3053 #define CAN_F12R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3054 #define CAN_F12R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3055 #define CAN_F12R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3056 #define CAN_F12R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3057 #define CAN_F12R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3058 #define CAN_F12R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3059 #define CAN_F12R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3060 #define CAN_F12R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3061 #define CAN_F12R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3062 #define CAN_F12R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3063 #define CAN_F12R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3064 #define CAN_F12R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3065 #define CAN_F12R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3066 #define CAN_F12R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3067 #define CAN_F12R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3068 #define CAN_F12R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3069 #define CAN_F12R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3070 #define CAN_F12R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3071 #define CAN_F12R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3072 #define CAN_F12R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3073 #define CAN_F12R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3074 #define CAN_F12R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3075 #define CAN_F12R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3076 #define CAN_F12R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3077
3078 /******************* Bit definition for CAN_F13R1 register ******************/
3079 #define CAN_F13R1_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3080 #define CAN_F13R1_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3081 #define CAN_F13R1_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3082 #define CAN_F13R1_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3083 #define CAN_F13R1_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3084 #define CAN_F13R1_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3085 #define CAN_F13R1_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3086 #define CAN_F13R1_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3087 #define CAN_F13R1_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3088 #define CAN_F13R1_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3089 #define CAN_F13R1_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3090 #define CAN_F13R1_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3091 #define CAN_F13R1_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3092 #define CAN_F13R1_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3093 #define CAN_F13R1_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3094 #define CAN_F13R1_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3095 #define CAN_F13R1_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3096 #define CAN_F13R1_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3097 #define CAN_F13R1_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3098 #define CAN_F13R1_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3099 #define CAN_F13R1_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3100 #define CAN_F13R1_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3101 #define CAN_F13R1_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3102 #define CAN_F13R1_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3103 #define CAN_F13R1_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3104 #define CAN_F13R1_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3105 #define CAN_F13R1_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3106 #define CAN_F13R1_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3107 #define CAN_F13R1_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3108 #define CAN_F13R1_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3109 #define CAN_F13R1_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3110 #define CAN_F13R1_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3111
3112 /******************* Bit definition for CAN_F0R2 register *******************/
3113 #define CAN_F0R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3114 #define CAN_F0R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3115 #define CAN_F0R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3116 #define CAN_F0R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3117 #define CAN_F0R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3118 #define CAN_F0R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3119 #define CAN_F0R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3120 #define CAN_F0R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3121 #define CAN_F0R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3122 #define CAN_F0R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3123 #define CAN_F0R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3124 #define CAN_F0R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3125 #define CAN_F0R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3126 #define CAN_F0R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3127 #define CAN_F0R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3128 #define CAN_F0R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3129 #define CAN_F0R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3130 #define CAN_F0R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3131 #define CAN_F0R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3132 #define CAN_F0R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3133 #define CAN_F0R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3134 #define CAN_F0R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3135 #define CAN_F0R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3136 #define CAN_F0R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3137 #define CAN_F0R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3138 #define CAN_F0R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3139 #define CAN_F0R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3140 #define CAN_F0R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3141 #define CAN_F0R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3142 #define CAN_F0R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3143 #define CAN_F0R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3144 #define CAN_F0R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3145
3146 /******************* Bit definition for CAN_F1R2 register *******************/
3147 #define CAN_F1R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3148 #define CAN_F1R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3149 #define CAN_F1R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3150 #define CAN_F1R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3151 #define CAN_F1R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3152 #define CAN_F1R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3153 #define CAN_F1R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3154 #define CAN_F1R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3155 #define CAN_F1R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3156 #define CAN_F1R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3157 #define CAN_F1R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3158 #define CAN_F1R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3159 #define CAN_F1R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3160 #define CAN_F1R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3161 #define CAN_F1R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3162 #define CAN_F1R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3163 #define CAN_F1R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3164 #define CAN_F1R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3165 #define CAN_F1R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3166 #define CAN_F1R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3167 #define CAN_F1R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3168 #define CAN_F1R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3169 #define CAN_F1R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3170 #define CAN_F1R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3171 #define CAN_F1R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3172 #define CAN_F1R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3173 #define CAN_F1R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3174 #define CAN_F1R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3175 #define CAN_F1R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3176 #define CAN_F1R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3177 #define CAN_F1R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3178 #define CAN_F1R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3179
3180 /******************* Bit definition for CAN_F2R2 register *******************/
3181 #define CAN_F2R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3182 #define CAN_F2R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3183 #define CAN_F2R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3184 #define CAN_F2R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3185 #define CAN_F2R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3186 #define CAN_F2R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3187 #define CAN_F2R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3188 #define CAN_F2R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3189 #define CAN_F2R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3190 #define CAN_F2R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3191 #define CAN_F2R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3192 #define CAN_F2R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3193 #define CAN_F2R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3194 #define CAN_F2R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3195 #define CAN_F2R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3196 #define CAN_F2R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3197 #define CAN_F2R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3198 #define CAN_F2R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3199 #define CAN_F2R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3200 #define CAN_F2R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3201 #define CAN_F2R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3202 #define CAN_F2R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3203 #define CAN_F2R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3204 #define CAN_F2R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3205 #define CAN_F2R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3206 #define CAN_F2R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3207 #define CAN_F2R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3208 #define CAN_F2R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3209 #define CAN_F2R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3210 #define CAN_F2R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3211 #define CAN_F2R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3212 #define CAN_F2R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3213
3214 /******************* Bit definition for CAN_F3R2 register *******************/
3215 #define CAN_F3R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3216 #define CAN_F3R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3217 #define CAN_F3R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3218 #define CAN_F3R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3219 #define CAN_F3R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3220 #define CAN_F3R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3221 #define CAN_F3R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3222 #define CAN_F3R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3223 #define CAN_F3R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3224 #define CAN_F3R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3225 #define CAN_F3R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3226 #define CAN_F3R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3227 #define CAN_F3R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3228 #define CAN_F3R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3229 #define CAN_F3R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3230 #define CAN_F3R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3231 #define CAN_F3R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3232 #define CAN_F3R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3233 #define CAN_F3R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3234 #define CAN_F3R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3235 #define CAN_F3R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3236 #define CAN_F3R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3237 #define CAN_F3R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3238 #define CAN_F3R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3239 #define CAN_F3R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3240 #define CAN_F3R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3241 #define CAN_F3R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3242 #define CAN_F3R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3243 #define CAN_F3R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3244 #define CAN_F3R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3245 #define CAN_F3R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3246 #define CAN_F3R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3247
3248 /******************* Bit definition for CAN_F4R2 register *******************/
3249 #define CAN_F4R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3250 #define CAN_F4R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3251 #define CAN_F4R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3252 #define CAN_F4R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3253 #define CAN_F4R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3254 #define CAN_F4R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3255 #define CAN_F4R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3256 #define CAN_F4R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3257 #define CAN_F4R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3258 #define CAN_F4R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3259 #define CAN_F4R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3260 #define CAN_F4R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3261 #define CAN_F4R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3262 #define CAN_F4R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3263 #define CAN_F4R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3264 #define CAN_F4R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3265 #define CAN_F4R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3266 #define CAN_F4R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3267 #define CAN_F4R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3268 #define CAN_F4R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3269 #define CAN_F4R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3270 #define CAN_F4R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3271 #define CAN_F4R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3272 #define CAN_F4R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3273 #define CAN_F4R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3274 #define CAN_F4R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3275 #define CAN_F4R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3276 #define CAN_F4R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3277 #define CAN_F4R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3278 #define CAN_F4R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3279 #define CAN_F4R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3280 #define CAN_F4R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3281
3282 /******************* Bit definition for CAN_F5R2 register *******************/
3283 #define CAN_F5R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3284 #define CAN_F5R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3285 #define CAN_F5R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3286 #define CAN_F5R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3287 #define CAN_F5R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3288 #define CAN_F5R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3289 #define CAN_F5R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3290 #define CAN_F5R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3291 #define CAN_F5R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3292 #define CAN_F5R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3293 #define CAN_F5R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3294 #define CAN_F5R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3295 #define CAN_F5R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3296 #define CAN_F5R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3297 #define CAN_F5R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3298 #define CAN_F5R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3299 #define CAN_F5R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3300 #define CAN_F5R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3301 #define CAN_F5R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3302 #define CAN_F5R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3303 #define CAN_F5R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3304 #define CAN_F5R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3305 #define CAN_F5R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3306 #define CAN_F5R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3307 #define CAN_F5R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3308 #define CAN_F5R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3309 #define CAN_F5R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3310 #define CAN_F5R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3311 #define CAN_F5R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3312 #define CAN_F5R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3313 #define CAN_F5R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3314 #define CAN_F5R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3315
3316 /******************* Bit definition for CAN_F6R2 register *******************/
3317 #define CAN_F6R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3318 #define CAN_F6R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3319 #define CAN_F6R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3320 #define CAN_F6R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3321 #define CAN_F6R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3322 #define CAN_F6R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3323 #define CAN_F6R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3324 #define CAN_F6R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3325 #define CAN_F6R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3326 #define CAN_F6R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3327 #define CAN_F6R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3328 #define CAN_F6R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3329 #define CAN_F6R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3330 #define CAN_F6R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3331 #define CAN_F6R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3332 #define CAN_F6R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3333 #define CAN_F6R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3334 #define CAN_F6R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3335 #define CAN_F6R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3336 #define CAN_F6R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3337 #define CAN_F6R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3338 #define CAN_F6R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3339 #define CAN_F6R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3340 #define CAN_F6R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3341 #define CAN_F6R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3342 #define CAN_F6R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3343 #define CAN_F6R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3344 #define CAN_F6R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3345 #define CAN_F6R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3346 #define CAN_F6R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3347 #define CAN_F6R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3348 #define CAN_F6R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3349
3350 /******************* Bit definition for CAN_F7R2 register *******************/
3351 #define CAN_F7R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3352 #define CAN_F7R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3353 #define CAN_F7R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3354 #define CAN_F7R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3355 #define CAN_F7R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3356 #define CAN_F7R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3357 #define CAN_F7R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3358 #define CAN_F7R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3359 #define CAN_F7R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3360 #define CAN_F7R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3361 #define CAN_F7R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3362 #define CAN_F7R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3363 #define CAN_F7R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3364 #define CAN_F7R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3365 #define CAN_F7R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3366 #define CAN_F7R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3367 #define CAN_F7R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3368 #define CAN_F7R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3369 #define CAN_F7R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3370 #define CAN_F7R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3371 #define CAN_F7R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3372 #define CAN_F7R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3373 #define CAN_F7R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3374 #define CAN_F7R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3375 #define CAN_F7R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3376 #define CAN_F7R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3377 #define CAN_F7R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3378 #define CAN_F7R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3379 #define CAN_F7R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3380 #define CAN_F7R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3381 #define CAN_F7R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3382 #define CAN_F7R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3383
3384 /******************* Bit definition for CAN_F8R2 register *******************/
3385 #define CAN_F8R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3386 #define CAN_F8R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3387 #define CAN_F8R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3388 #define CAN_F8R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3389 #define CAN_F8R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3390 #define CAN_F8R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3391 #define CAN_F8R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3392 #define CAN_F8R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3393 #define CAN_F8R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3394 #define CAN_F8R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3395 #define CAN_F8R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3396 #define CAN_F8R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3397 #define CAN_F8R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3398 #define CAN_F8R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3399 #define CAN_F8R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3400 #define CAN_F8R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3401 #define CAN_F8R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3402 #define CAN_F8R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3403 #define CAN_F8R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3404 #define CAN_F8R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3405 #define CAN_F8R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3406 #define CAN_F8R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3407 #define CAN_F8R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3408 #define CAN_F8R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3409 #define CAN_F8R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3410 #define CAN_F8R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3411 #define CAN_F8R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3412 #define CAN_F8R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3413 #define CAN_F8R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3414 #define CAN_F8R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3415 #define CAN_F8R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3416 #define CAN_F8R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3417
3418 /******************* Bit definition for CAN_F9R2 register *******************/
3419 #define CAN_F9R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3420 #define CAN_F9R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3421 #define CAN_F9R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3422 #define CAN_F9R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3423 #define CAN_F9R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3424 #define CAN_F9R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3425 #define CAN_F9R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3426 #define CAN_F9R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3427 #define CAN_F9R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3428 #define CAN_F9R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3429 #define CAN_F9R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3430 #define CAN_F9R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3431 #define CAN_F9R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3432 #define CAN_F9R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3433 #define CAN_F9R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3434 #define CAN_F9R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3435 #define CAN_F9R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3436 #define CAN_F9R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3437 #define CAN_F9R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3438 #define CAN_F9R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3439 #define CAN_F9R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3440 #define CAN_F9R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3441 #define CAN_F9R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3442 #define CAN_F9R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3443 #define CAN_F9R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3444 #define CAN_F9R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3445 #define CAN_F9R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3446 #define CAN_F9R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3447 #define CAN_F9R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3448 #define CAN_F9R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3449 #define CAN_F9R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3450 #define CAN_F9R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3451
3452 /******************* Bit definition for CAN_F10R2 register ******************/
3453 #define CAN_F10R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3454 #define CAN_F10R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3455 #define CAN_F10R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3456 #define CAN_F10R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3457 #define CAN_F10R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3458 #define CAN_F10R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3459 #define CAN_F10R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3460 #define CAN_F10R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3461 #define CAN_F10R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3462 #define CAN_F10R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3463 #define CAN_F10R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3464 #define CAN_F10R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3465 #define CAN_F10R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3466 #define CAN_F10R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3467 #define CAN_F10R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3468 #define CAN_F10R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3469 #define CAN_F10R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3470 #define CAN_F10R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3471 #define CAN_F10R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3472 #define CAN_F10R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3473 #define CAN_F10R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3474 #define CAN_F10R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3475 #define CAN_F10R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3476 #define CAN_F10R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3477 #define CAN_F10R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3478 #define CAN_F10R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3479 #define CAN_F10R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3480 #define CAN_F10R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3481 #define CAN_F10R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3482 #define CAN_F10R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3483 #define CAN_F10R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3484 #define CAN_F10R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3485
3486 /******************* Bit definition for CAN_F11R2 register ******************/
3487 #define CAN_F11R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3488 #define CAN_F11R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3489 #define CAN_F11R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3490 #define CAN_F11R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3491 #define CAN_F11R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3492 #define CAN_F11R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3493 #define CAN_F11R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3494 #define CAN_F11R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3495 #define CAN_F11R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3496 #define CAN_F11R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3497 #define CAN_F11R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3498 #define CAN_F11R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3499 #define CAN_F11R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3500 #define CAN_F11R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3501 #define CAN_F11R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3502 #define CAN_F11R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3503 #define CAN_F11R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3504 #define CAN_F11R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3505 #define CAN_F11R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3506 #define CAN_F11R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3507 #define CAN_F11R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3508 #define CAN_F11R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3509 #define CAN_F11R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3510 #define CAN_F11R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3511 #define CAN_F11R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3512 #define CAN_F11R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3513 #define CAN_F11R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3514 #define CAN_F11R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3515 #define CAN_F11R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3516 #define CAN_F11R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3517 #define CAN_F11R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3518 #define CAN_F11R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3519
3520 /******************* Bit definition for CAN_F12R2 register ******************/
3521 #define CAN_F12R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3522 #define CAN_F12R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3523 #define CAN_F12R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3524 #define CAN_F12R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3525 #define CAN_F12R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3526 #define CAN_F12R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3527 #define CAN_F12R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3528 #define CAN_F12R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3529 #define CAN_F12R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3530 #define CAN_F12R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3531 #define CAN_F12R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3532 #define CAN_F12R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3533 #define CAN_F12R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3534 #define CAN_F12R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3535 #define CAN_F12R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3536 #define CAN_F12R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3537 #define CAN_F12R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3538 #define CAN_F12R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3539 #define CAN_F12R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3540 #define CAN_F12R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3541 #define CAN_F12R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3542 #define CAN_F12R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3543 #define CAN_F12R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3544 #define CAN_F12R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3545 #define CAN_F12R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3546 #define CAN_F12R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3547 #define CAN_F12R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3548 #define CAN_F12R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3549 #define CAN_F12R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3550 #define CAN_F12R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3551 #define CAN_F12R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3552 #define CAN_F12R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3553
3554 /******************* Bit definition for CAN_F13R2 register ******************/
3555 #define CAN_F13R2_FB0 ((uint32_t)0x00000001U) /*!<Filter bit 0 */
3556 #define CAN_F13R2_FB1 ((uint32_t)0x00000002U) /*!<Filter bit 1 */
3557 #define CAN_F13R2_FB2 ((uint32_t)0x00000004U) /*!<Filter bit 2 */
3558 #define CAN_F13R2_FB3 ((uint32_t)0x00000008U) /*!<Filter bit 3 */
3559 #define CAN_F13R2_FB4 ((uint32_t)0x00000010U) /*!<Filter bit 4 */
3560 #define CAN_F13R2_FB5 ((uint32_t)0x00000020U) /*!<Filter bit 5 */
3561 #define CAN_F13R2_FB6 ((uint32_t)0x00000040U) /*!<Filter bit 6 */
3562 #define CAN_F13R2_FB7 ((uint32_t)0x00000080U) /*!<Filter bit 7 */
3563 #define CAN_F13R2_FB8 ((uint32_t)0x00000100U) /*!<Filter bit 8 */
3564 #define CAN_F13R2_FB9 ((uint32_t)0x00000200U) /*!<Filter bit 9 */
3565 #define CAN_F13R2_FB10 ((uint32_t)0x00000400U) /*!<Filter bit 10 */
3566 #define CAN_F13R2_FB11 ((uint32_t)0x00000800U) /*!<Filter bit 11 */
3567 #define CAN_F13R2_FB12 ((uint32_t)0x00001000U) /*!<Filter bit 12 */
3568 #define CAN_F13R2_FB13 ((uint32_t)0x00002000U) /*!<Filter bit 13 */
3569 #define CAN_F13R2_FB14 ((uint32_t)0x00004000U) /*!<Filter bit 14 */
3570 #define CAN_F13R2_FB15 ((uint32_t)0x00008000U) /*!<Filter bit 15 */
3571 #define CAN_F13R2_FB16 ((uint32_t)0x00010000U) /*!<Filter bit 16 */
3572 #define CAN_F13R2_FB17 ((uint32_t)0x00020000U) /*!<Filter bit 17 */
3573 #define CAN_F13R2_FB18 ((uint32_t)0x00040000U) /*!<Filter bit 18 */
3574 #define CAN_F13R2_FB19 ((uint32_t)0x00080000U) /*!<Filter bit 19 */
3575 #define CAN_F13R2_FB20 ((uint32_t)0x00100000U) /*!<Filter bit 20 */
3576 #define CAN_F13R2_FB21 ((uint32_t)0x00200000U) /*!<Filter bit 21 */
3577 #define CAN_F13R2_FB22 ((uint32_t)0x00400000U) /*!<Filter bit 22 */
3578 #define CAN_F13R2_FB23 ((uint32_t)0x00800000U) /*!<Filter bit 23 */
3579 #define CAN_F13R2_FB24 ((uint32_t)0x01000000U) /*!<Filter bit 24 */
3580 #define CAN_F13R2_FB25 ((uint32_t)0x02000000U) /*!<Filter bit 25 */
3581 #define CAN_F13R2_FB26 ((uint32_t)0x04000000U) /*!<Filter bit 26 */
3582 #define CAN_F13R2_FB27 ((uint32_t)0x08000000U) /*!<Filter bit 27 */
3583 #define CAN_F13R2_FB28 ((uint32_t)0x10000000U) /*!<Filter bit 28 */
3584 #define CAN_F13R2_FB29 ((uint32_t)0x20000000U) /*!<Filter bit 29 */
3585 #define CAN_F13R2_FB30 ((uint32_t)0x40000000U) /*!<Filter bit 30 */
3586 #define CAN_F13R2_FB31 ((uint32_t)0x80000000U) /*!<Filter bit 31 */
3587
3588 /******************************************************************************/
3589 /* */
3590 /* CRC calculation unit */
3591 /* */
3592 /******************************************************************************/
3593 /******************* Bit definition for CRC_DR register *********************/
3594 #define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
3595
3596 /******************* Bit definition for CRC_IDR register ********************/
3597 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
3598
3599 /******************** Bit definition for CRC_CR register ********************/
3600 #define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
3601 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */
3602 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
3603 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
3604 #define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
3605 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
3606 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
3607 #define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
3608
3609 /******************* Bit definition for CRC_INIT register *******************/
3610 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
3611
3612 /******************* Bit definition for CRC_POL register ********************/
3613 #define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
3614
3615 /******************************************************************************/
3616 /* */
3617 /* Advanced Encryption Standard (AES) */
3618 /* */
3619 /******************************************************************************/
3620 /******************* Bit definition for AES_CR register *********************/
3621 #define AES_CR_EN ((uint32_t)0x00000001U) /*!< AES Enable */
3622 #define AES_CR_DATATYPE ((uint32_t)0x00000006U) /*!< Data type selection */
3623 #define AES_CR_DATATYPE_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
3624 #define AES_CR_DATATYPE_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
3625
3626 #define AES_CR_MODE ((uint32_t)0x00000018U) /*!< AES Mode Of Operation */
3627 #define AES_CR_MODE_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
3628 #define AES_CR_MODE_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
3629
3630 #define AES_CR_CHMOD ((uint32_t)0x00010060U) /*!< AES Chaining Mode */
3631 #define AES_CR_CHMOD_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
3632 #define AES_CR_CHMOD_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
3633 #define AES_CR_CHMOD_2 ((uint32_t)0x00010000U) /*!< Bit 2 */
3634
3635 #define AES_CR_CCFC ((uint32_t)0x00000080U) /*!< Computation Complete Flag Clear */
3636 #define AES_CR_ERRC ((uint32_t)0x00000100U) /*!< Error Clear */
3637 #define AES_CR_CCFIE ((uint32_t)0x00000200U) /*!< Computation Complete Flag Interrupt Enable */
3638 #define AES_CR_ERRIE ((uint32_t)0x00000400U) /*!< Error Interrupt Enable */
3639 #define AES_CR_DMAINEN ((uint32_t)0x00000800U) /*!< Enable data input phase DMA management */
3640 #define AES_CR_DMAOUTEN ((uint32_t)0x00001000U) /*!< Enable data output phase DMA management */
3641
3642 #define AES_CR_GCMPH ((uint32_t)0x00006000U) /*!< GCM Phase */
3643 #define AES_CR_GCMPH_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
3644 #define AES_CR_GCMPH_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
3645
3646 #define AES_CR_KEYSIZE ((uint32_t)0x00040000U) /*!< Key size selection */
3647
3648 /******************* Bit definition for AES_SR register *********************/
3649 #define AES_SR_CCF ((uint32_t)0x00000001U) /*!< Computation Complete Flag */
3650 #define AES_SR_RDERR ((uint32_t)0x00000002U) /*!< Read Error Flag */
3651 #define AES_SR_WRERR ((uint32_t)0x00000004U) /*!< Write Error Flag */
3652 #define AES_SR_BUSY ((uint32_t)0x00000008U) /*!< Busy Flag */
3653
3654 /******************* Bit definition for AES_DINR register *******************/
3655 #define AES_DINR ((uint32_t)0xFFFFFFFFU) /*!< AES Data Input Register */
3656
3657 /******************* Bit definition for AES_DOUTR register ******************/
3658 #define AES_DOUTR ((uint32_t)0xFFFFFFFFU) /*!< AES Data Output Register */
3659
3660 /******************* Bit definition for AES_KEYR0 register ******************/
3661 #define AES_KEYR0 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 0 */
3662
3663 /******************* Bit definition for AES_KEYR1 register ******************/
3664 #define AES_KEYR1 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 1 */
3665
3666 /******************* Bit definition for AES_KEYR2 register ******************/
3667 #define AES_KEYR2 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 2 */
3668
3669 /******************* Bit definition for AES_KEYR3 register ******************/
3670 #define AES_KEYR3 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 3 */
3671
3672 /******************* Bit definition for AES_KEYR4 register ******************/
3673 #define AES_KEYR4 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 4 */
3674
3675 /******************* Bit definition for AES_KEYR5 register ******************/
3676 #define AES_KEYR5 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 5 */
3677
3678 /******************* Bit definition for AES_KEYR6 register ******************/
3679 #define AES_KEYR6 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 6 */
3680
3681 /******************* Bit definition for AES_KEYR7 register ******************/
3682 #define AES_KEYR7 ((uint32_t)0xFFFFFFFFU) /*!< AES Key Register 7 */
3683
3684 /******************* Bit definition for AES_IVR0 register ******************/
3685 #define AES_IVR0 ((uint32_t)0xFFFFFFFFU) /*!< AES Initialization Vector Register 0 */
3686
3687 /******************* Bit definition for AES_IVR1 register ******************/
3688 #define AES_IVR1 ((uint32_t)0xFFFFFFFFU) /*!< AES Initialization Vector Register 1 */
3689
3690 /******************* Bit definition for AES_IVR2 register ******************/
3691 #define AES_IVR2 ((uint32_t)0xFFFFFFFFU) /*!< AES Initialization Vector Register 2 */
3692
3693 /******************* Bit definition for AES_IVR3 register ******************/
3694 #define AES_IVR3 ((uint32_t)0xFFFFFFFFU) /*!< AES Initialization Vector Register 3 */
3695
3696 /******************* Bit definition for AES_SUSP0R register ******************/
3697 #define AES_SUSP0R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 0 */
3698
3699 /******************* Bit definition for AES_SUSP1R register ******************/
3700 #define AES_SUSP1R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 1 */
3701
3702 /******************* Bit definition for AES_SUSP2R register ******************/
3703 #define AES_SUSP2R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 2 */
3704
3705 /******************* Bit definition for AES_SUSP3R register ******************/
3706 #define AES_SUSP3R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 3 */
3707
3708 /******************* Bit definition for AES_SUSP4R register ******************/
3709 #define AES_SUSP4R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 4 */
3710
3711 /******************* Bit definition for AES_SUSP5R register ******************/
3712 #define AES_SUSP5R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 5 */
3713
3714 /******************* Bit definition for AES_SUSP6R register ******************/
3715 #define AES_SUSP6R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 6 */
3716
3717 /******************* Bit definition for AES_SUSP7R register ******************/
3718 #define AES_SUSP7R ((uint32_t)0xFFFFFFFFU) /*!< AES Suspend registers 7 */
3719
3720 /******************************************************************************/
3721 /* */
3722 /* Digital to Analog Converter */
3723 /* */
3724 /******************************************************************************/
3725 /******************** Bit definition for DAC_CR register ********************/
3726 #define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!<DAC channel1 enable */
3727 #define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!<DAC channel1 Trigger enable */
3728
3729 #define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
3730 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
3731 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
3732 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
3733
3734 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3735 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
3736 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
3737
3738 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3739 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
3740 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
3741 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
3742 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
3743
3744 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!<DAC channel1 DMA enable */
3745 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!<DAC channel 1 DMA underrun interrupt enable >*/
3746 #define DAC_CR_CEN1 ((uint32_t)0x00004000U) /*!<DAC channel 1 calibration enable >*/
3747
3748 #define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!<DAC channel2 enable */
3749 #define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!<DAC channel2 Trigger enable */
3750
3751 #define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
3752 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!<Bit 0 */
3753 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!<Bit 1 */
3754 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!<Bit 2 */
3755
3756 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3757 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
3758 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
3759
3760 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3761 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
3762 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
3763 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
3764 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
3765
3766 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!<DAC channel2 DMA enabled */
3767 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun interrupt enable >*/
3768 #define DAC_CR_CEN2 ((uint32_t)0x40000000U) /*!<DAC channel2 calibration enable >*/
3769
3770 /***************** Bit definition for DAC_SWTRIGR register ******************/
3771 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!<DAC channel1 software trigger */
3772 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!<DAC channel2 software trigger */
3773
3774 /***************** Bit definition for DAC_DHR12R1 register ******************/
3775 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
3776
3777 /***************** Bit definition for DAC_DHR12L1 register ******************/
3778 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
3779
3780 /****************** Bit definition for DAC_DHR8R1 register ******************/
3781 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
3782
3783 /***************** Bit definition for DAC_DHR12R2 register ******************/
3784 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!<DAC channel2 12-bit Right aligned data */
3785
3786 /***************** Bit definition for DAC_DHR12L2 register ******************/
3787 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel2 12-bit Left aligned data */
3788
3789 /****************** Bit definition for DAC_DHR8R2 register ******************/
3790 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!<DAC channel2 8-bit Right aligned data */
3791
3792 /***************** Bit definition for DAC_DHR12RD register ******************/
3793 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
3794 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!<DAC channel2 12-bit Right aligned data */
3795
3796 /***************** Bit definition for DAC_DHR12LD register ******************/
3797 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
3798 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!<DAC channel2 12-bit Left aligned data */
3799
3800 /****************** Bit definition for DAC_DHR8RD register ******************/
3801 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
3802 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!<DAC channel2 8-bit Right aligned data */
3803
3804 /******************* Bit definition for DAC_DOR1 register *******************/
3805 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFFU) /*!<DAC channel1 data output */
3806
3807 /******************* Bit definition for DAC_DOR2 register *******************/
3808 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFFU) /*!<DAC channel2 data output */
3809
3810 /******************** Bit definition for DAC_SR register ********************/
3811 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!<DAC channel1 DMA underrun flag */
3812 #define DAC_SR_CAL_FLAG1 ((uint32_t)0x00004000U) /*!<DAC channel1 calibration offset status */
3813 #define DAC_SR_BWST1 ((uint32_t)0x20008000U) /*!<DAC channel1 busy writing sample time flag */
3814
3815 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun flag */
3816 #define DAC_SR_CAL_FLAG2 ((uint32_t)0x40000000U) /*!<DAC channel2 calibration offset status */
3817 #define DAC_SR_BWST2 ((uint32_t)0x80000000U) /*!<DAC channel2 busy writing sample time flag */
3818
3819 /******************* Bit definition for DAC_CCR register ********************/
3820 #define DAC_CCR_OTRIM1 ((uint32_t)0x0000001FU) /*!<DAC channel1 offset trimming value */
3821 #define DAC_CCR_OTRIM2 ((uint32_t)0x001F0000U) /*!<DAC channel2 offset trimming value */
3822
3823 /******************* Bit definition for DAC_MCR register *******************/
3824 #define DAC_MCR_MODE1 ((uint32_t)0x00000007U) /*!<MODE1[2:0] (DAC channel1 mode) */
3825 #define DAC_MCR_MODE1_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
3826 #define DAC_MCR_MODE1_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
3827 #define DAC_MCR_MODE1_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
3828
3829 #define DAC_MCR_MODE2 ((uint32_t)0x00070000U) /*!<MODE2[2:0] (DAC channel2 mode) */
3830 #define DAC_MCR_MODE2_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
3831 #define DAC_MCR_MODE2_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
3832 #define DAC_MCR_MODE2_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
3833
3834 /****************** Bit definition for DAC_SHSR1 register ******************/
3835 #define DAC_SHSR1_TSAMPLE1 ((uint32_t)0x000003FFU) /*!<DAC channel1 sample time */
3836
3837 /****************** Bit definition for DAC_SHSR2 register ******************/
3838 #define DAC_SHSR2_TSAMPLE2 ((uint32_t)0x000003FFU) /*!<DAC channel2 sample time */
3839
3840 /****************** Bit definition for DAC_SHHR register ******************/
3841 #define DAC_SHHR_THOLD1 ((uint32_t)0x000003FFU) /*!<DAC channel1 hold time */
3842 #define DAC_SHHR_THOLD2 ((uint32_t)0x03FF0000U) /*!<DAC channel2 hold time */
3843
3844 /****************** Bit definition for DAC_SHRR register ******************/
3845 #define DAC_SHRR_TREFRESH1 ((uint32_t)0x000000FFU) /*!<DAC channel1 refresh time */
3846 #define DAC_SHRR_TREFRESH2 ((uint32_t)0x00FF0000U) /*!<DAC channel2 refresh time */
3847
3848
3849 /******************************************************************************/
3850 /* */
3851 /* Digital Filter for Sigma Delta Modulators */
3852 /* */
3853 /******************************************************************************/
3854
3855 /**************** DFSDM channel configuration registers ********************/
3856
3857 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
3858 #define DFSDM_CHCFGR1_DFSDMEN ((uint32_t)0x80000000U) /*!< Global enable for DFSDM interface */
3859 #define DFSDM_CHCFGR1_CKOUTSRC ((uint32_t)0x40000000U) /*!< Output serial clock source selection */
3860 #define DFSDM_CHCFGR1_CKOUTDIV ((uint32_t)0x00FF0000U) /*!< CKOUTDIV[7:0] output serial clock divider */
3861 #define DFSDM_CHCFGR1_DATPACK ((uint32_t)0x0000C000U) /*!< DATPACK[1:0] Data packing mode */
3862 #define DFSDM_CHCFGR1_DATPACK_1 ((uint32_t)0x00008000U) /*!< Data packing mode, Bit 1 */
3863 #define DFSDM_CHCFGR1_DATPACK_0 ((uint32_t)0x00004000U) /*!< Data packing mode, Bit 0 */
3864 #define DFSDM_CHCFGR1_DATMPX ((uint32_t)0x00003000U) /*!< DATMPX[1:0] Input data multiplexer for channel y */
3865 #define DFSDM_CHCFGR1_DATMPX_1 ((uint32_t)0x00002000U) /*!< Input data multiplexer for channel y, Bit 1 */
3866 #define DFSDM_CHCFGR1_DATMPX_0 ((uint32_t)0x00001000U) /*!< Input data multiplexer for channel y, Bit 0 */
3867 #define DFSDM_CHCFGR1_CHINSEL ((uint32_t)0x00000100U) /*!< Serial inputs selection for channel y */
3868 #define DFSDM_CHCFGR1_CHEN ((uint32_t)0x00000080U) /*!< Channel y enable */
3869 #define DFSDM_CHCFGR1_CKABEN ((uint32_t)0x00000040U) /*!< Clock absence detector enable on channel y */
3870 #define DFSDM_CHCFGR1_SCDEN ((uint32_t)0x00000020U) /*!< Short circuit detector enable on channel y */
3871 #define DFSDM_CHCFGR1_SPICKSEL ((uint32_t)0x0000000CU) /*!< SPICKSEL[1:0] SPI clock select for channel y */
3872 #define DFSDM_CHCFGR1_SPICKSEL_1 ((uint32_t)0x00000008U) /*!< SPI clock select for channel y, Bit 1 */
3873 #define DFSDM_CHCFGR1_SPICKSEL_0 ((uint32_t)0x00000004U) /*!< SPI clock select for channel y, Bit 0 */
3874 #define DFSDM_CHCFGR1_SITP ((uint32_t)0x00000003U) /*!< SITP[1:0] Serial interface type for channel y */
3875 #define DFSDM_CHCFGR1_SITP_1 ((uint32_t)0x00000002U) /*!< Serial interface type for channel y, Bit 1 */
3876 #define DFSDM_CHCFGR1_SITP_0 ((uint32_t)0x00000001U) /*!< Serial interface type for channel y, Bit 0 */
3877
3878 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
3879 #define DFSDM_CHCFGR2_OFFSET ((uint32_t)0xFFFFFF00U) /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
3880 #define DFSDM_CHCFGR2_DTRBS ((uint32_t)0x000000F8U) /*!< DTRBS[4:0] Data right bit-shift for channel y */
3881
3882 /****************** Bit definition for DFSDM_AWSCDR register *****************/
3883 #define DFSDM_AWSCDR_AWFORD ((uint32_t)0x00C00000U) /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
3884 #define DFSDM_AWSCDR_AWFORD_1 ((uint32_t)0x00800000U) /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
3885 #define DFSDM_AWSCDR_AWFORD_0 ((uint32_t)0x00400000U) /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
3886 #define DFSDM_AWSCDR_AWFOSR ((uint32_t)0x001F0000U) /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
3887 #define DFSDM_AWSCDR_BKSCD ((uint32_t)0x0000F000U) /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
3888 #define DFSDM_AWSCDR_SCDT ((uint32_t)0x000000FFU) /*!< SCDT[7:0] Short circuit detector threshold for channel y */
3889
3890 /**************** Bit definition for DFSDM_CHWDATR register *******************/
3891 #define DFSDM_AWSCDR_WDATA ((uint32_t)0x0000FFFFU) /*!< WDATA[15:0] Input channel y watchdog data */
3892
3893 /**************** Bit definition for DFSDM_CHDATINR register *****************/
3894 #define DFSDM_AWSCDR_INDAT0 ((uint32_t)0x0000FFFFU) /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
3895 #define DFSDM_AWSCDR_INDAT1 ((uint32_t)0xFFFF0000U) /*!< INDAT0[15:0] Input data for channel y */
3896
3897 /************************ DFSDM module registers ****************************/
3898
3899 /******************** Bit definition for DFSDM_CR1 register *******************/
3900 #define DFSDM_CR1_AWFSEL ((uint32_t)0x40000000U) /*!< Analog watchdog fast mode select */
3901 #define DFSDM_CR1_FAST ((uint32_t)0x20000000U) /*!< Fast conversion mode selection */
3902 #define DFSDM_CR1_RCH ((uint32_t)0x07000000U) /*!< RCH[2:0] Regular channel selection */
3903 #define DFSDM_CR1_RDMAEN ((uint32_t)0x00200000U) /*!< DMA channel enabled to read data for the regular conversion */
3904 #define DFSDM_CR1_RSYNC ((uint32_t)0x00080000U) /*!< Launch regular conversion synchronously with DFSDMx */
3905 #define DFSDM_CR1_RCONT ((uint32_t)0x00040000U) /*!< Continuous mode selection for regular conversions */
3906 #define DFSDM_CR1_RSWSTART ((uint32_t)0x00020000U) /*!< Software start of a conversion on the regular channel */
3907 #define DFSDM_CR1_JEXTEN ((uint32_t)0x00006000U) /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
3908 #define DFSDM_CR1_JEXTEN_1 ((uint32_t)0x00004000U) /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
3909 #define DFSDM_CR1_JEXTEN_0 ((uint32_t)0x00002000U) /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
3910 #define DFSDM_CR1_JEXTSEL ((uint32_t)0x00000700U) /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
3911 #define DFSDM_CR1_JEXTSEL_2 ((uint32_t)0x00000400U) /*!< Trigger signal selection for launching injected conversions, Bit 2 */
3912 #define DFSDM_CR1_JEXTSEL_1 ((uint32_t)0x00000200U) /*!< Trigger signal selection for launching injected conversions, Bit 1 */
3913 #define DFSDM_CR1_JEXTSEL_0 ((uint32_t)0x00000100U) /*!< Trigger signal selection for launching injected conversions, Bit 0 */
3914 #define DFSDM_CR1_JDMAEN ((uint32_t)0x00000020U) /*!< DMA channel enabled to read data for the injected channel group */
3915 #define DFSDM_CR1_JSCAN ((uint32_t)0x00000010U) /*!< Scanning conversion in continuous mode selection for injected conversions */
3916 #define DFSDM_CR1_JSYNC ((uint32_t)0x00000008U) /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
3917 #define DFSDM_CR1_JSWSTART ((uint32_t)0x00000002U) /*!< Start the conversion of the injected group of channels */
3918 #define DFSDM_CR1_DFEN ((uint32_t)0x00000001U) /*!< DFSDM enable */
3919
3920 /******************** Bit definition for DFSDM_CR2 register *******************/
3921 #define DFSDM_CR2_AWDCH ((uint32_t)0x00FF0000U) /*!< AWDCH[7:0] Analog watchdog channel selection */
3922 #define DFSDM_CR2_EXCH ((uint32_t)0x0000FF00U) /*!< EXCH[7:0] Extreme detector channel selection */
3923 #define DFSDM_CR2_CKABIE ((uint32_t)0x00000040U) /*!< Clock absence interrupt enable */
3924 #define DFSDM_CR2_SCDIE ((uint32_t)0x00000020U) /*!< Short circuit detector interrupt enable */
3925 #define DFSDM_CR2_AWDIE ((uint32_t)0x00000010U) /*!< Analog watchdog interrupt enable */
3926 #define DFSDM_CR2_ROVRIE ((uint32_t)0x00000008U) /*!< Regular data overrun interrupt enable */
3927 #define DFSDM_CR2_JOVRIE ((uint32_t)0x00000004U) /*!< Injected data overrun interrupt enable */
3928 #define DFSDM_CR2_REOCIE ((uint32_t)0x00000002U) /*!< Regular end of conversion interrupt enable */
3929 #define DFSDM_CR2_JEOCIE ((uint32_t)0x00000001U) /*!< Injected end of conversion interrupt enable */
3930
3931 /******************** Bit definition for DFSDM_ISR register *******************/
3932 #define DFSDM_ISR_SCDF ((uint32_t)0xFF000000U) /*!< SCDF[7:0] Short circuit detector flag */
3933 #define DFSDM_ISR_CKABF ((uint32_t)0x00FF0000U) /*!< CKABF[7:0] Clock absence flag */
3934 #define DFSDM_ISR_RCIP ((uint32_t)0x00004000U) /*!< Regular conversion in progress status */
3935 #define DFSDM_ISR_JCIP ((uint32_t)0x00002000U) /*!< Injected conversion in progress status */
3936 #define DFSDM_ISR_AWDF ((uint32_t)0x00000010U) /*!< Analog watchdog */
3937 #define DFSDM_ISR_ROVRF ((uint32_t)0x00000008U) /*!< Regular conversion overrun flag */
3938 #define DFSDM_ISR_JOVRF ((uint32_t)0x00000004U) /*!< Injected conversion overrun flag */
3939 #define DFSDM_ISR_REOCF ((uint32_t)0x00000002U) /*!< End of regular conversion flag */
3940 #define DFSDM_ISR_JEOCF ((uint32_t)0x00000001U) /*!< End of injected conversion flag */
3941
3942 /******************** Bit definition for DFSDM_ICR register *******************/
3943 #define DFSDM_ICR_CLRSCSDF ((uint32_t)0xFF000000U) /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
3944 #define DFSDM_ICR_CLRCKABF ((uint32_t)0x00FF0000U) /*!< CLRCKABF[7:0] Clear the clock absence flag */
3945 #define DFSDM_ICR_CLRROVRF ((uint32_t)0x00000008U) /*!< Clear the regular conversion overrun flag */
3946 #define DFSDM_ICR_CLRJOVRF ((uint32_t)0x00000004U) /*!< Clear the injected conversion overrun flag */
3947
3948 /******************* Bit definition for DFSDM_JCHGR register ******************/
3949 #define DFSDM_JCHGR_JCHG ((uint32_t)0x000000FFU) /*!< JCHG[7:0] Injected channel group selection */
3950
3951 /******************** Bit definition for DFSDM_FCR register *******************/
3952 #define DFSDM_FCR_FORD ((uint32_t)0xE0000000U) /*!< FORD[2:0] Sinc filter order */
3953 #define DFSDM_FCR_FORD_2 ((uint32_t)0x80000000U) /*!< Sinc filter order, Bit 2 */
3954 #define DFSDM_FCR_FORD_1 ((uint32_t)0x40000000U) /*!< Sinc filter order, Bit 1 */
3955 #define DFSDM_FCR_FORD_0 ((uint32_t)0x20000000U) /*!< Sinc filter order, Bit 0 */
3956 #define DFSDM_FCR_FOSR ((uint32_t)0x03FF0000U) /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
3957 #define DFSDM_FCR_IOSR ((uint32_t)0x000000FFU) /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
3958
3959 /****************** Bit definition for DFSDM_JDATAR register *****************/
3960 #define DFSDM_JDATAR_JDATA ((uint32_t)0xFFFFFF00U) /*!< JDATA[23:0] Injected group conversion data */
3961 #define DFSDM_JDATAR_JDATACH ((uint32_t)0x00000007U) /*!< JDATACH[2:0] Injected channel most recently converted */
3962
3963 /****************** Bit definition for DFSDM_RDATAR register *****************/
3964 #define DFSDM_RDATAR_RDATA ((uint32_t)0xFFFFFF00U) /*!< RDATA[23:0] Regular channel conversion data */
3965 #define DFSDM_RDATAR_RPEND ((uint32_t)0x00000010U) /*!< RPEND Regular channel pending data */
3966 #define DFSDM_RDATAR_RDATACH ((uint32_t)0x00000007U) /*!< RDATACH[2:0] Regular channel most recently converted */
3967
3968 /****************** Bit definition for DFSDM_AWHTR register ******************/
3969 #define DFSDM_AWHTR_AWHT ((uint32_t)0xFFFFFF00U) /*!< AWHT[23:0] Analog watchdog high threshold */
3970 #define DFSDM_AWHTR_BKAWH ((uint32_t)0x0000000FU) /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
3971
3972 /****************** Bit definition for DFSDM_AWLTR register ******************/
3973 #define DFSDM_AWLTR_AWLT ((uint32_t)0xFFFFFF00U) /*!< AWHT[23:0] Analog watchdog low threshold */
3974 #define DFSDM_AWLTR_BKAWL ((uint32_t)0x0000000FU) /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
3975
3976 /****************** Bit definition for DFSDM_AWSR register ******************/
3977 #define DFSDM_AWSR_AWHTF ((uint32_t)0x0000FF00U) /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
3978 #define DFSDM_AWSR_AWLTF ((uint32_t)0x000000FFU) /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
3979
3980 /****************** Bit definition for DFSDM_AWCFR) register *****************/
3981 #define DFSDM_AWCFR_CLRAWHTF ((uint32_t)0x0000FF00U) /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
3982 #define DFSDM_AWCFR_CLRAWLTF ((uint32_t)0x000000FFU) /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
3983
3984 /****************** Bit definition for DFSDM_EXMAX register ******************/
3985 #define DFSDM_EXMAX_EXMAX ((uint32_t)0xFFFFFF00U) /*!< EXMAX[23:0] Extreme detector maximum value */
3986 #define DFSDM_EXMAX_EXMAXCH ((uint32_t)0x00000007U) /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
3987
3988 /****************** Bit definition for DFSDM_EXMIN register ******************/
3989 #define DFSDM_EXMIN_EXMIN ((uint32_t)0xFFFFFF00U) /*!< EXMIN[23:0] Extreme detector minimum value */
3990 #define DFSDM_EXMIN_EXMINCH ((uint32_t)0x00000007U) /*!< EXMINCH[2:0] Extreme detector minimum data channel */
3991
3992 /****************** Bit definition for DFSDM_EXMIN register ******************/
3993 #define DFSDM_CNVTIMR_CNVCNT ((uint32_t)0xFFFFFFF0U) /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
3994
3995 /******************************************************************************/
3996 /* */
3997 /* DMA Controller (DMA) */
3998 /* */
3999 /******************************************************************************/
4000
4001 /******************* Bit definition for DMA_ISR register ********************/
4002 #define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
4003 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
4004 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
4005 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
4006 #define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
4007 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
4008 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
4009 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
4010 #define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
4011 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
4012 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
4013 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
4014 #define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
4015 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
4016 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
4017 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
4018 #define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
4019 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
4020 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
4021 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
4022 #define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
4023 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
4024 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
4025 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
4026 #define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
4027 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
4028 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
4029 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
4030
4031 /******************* Bit definition for DMA_IFCR register *******************/
4032 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clearr */
4033 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
4034 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
4035 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
4036 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
4037 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
4038 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
4039 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
4040 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
4041 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
4042 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
4043 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
4044 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
4045 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
4046 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
4047 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
4048 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
4049 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
4050 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
4051 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
4052 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
4053 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
4054 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
4055 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
4056 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
4057 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
4058 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
4059 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
4060
4061 /******************* Bit definition for DMA_CCR register ********************/
4062 #define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */
4063 #define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
4064 #define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
4065 #define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
4066 #define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
4067 #define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
4068 #define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
4069 #define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
4070
4071 #define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
4072 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
4073 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
4074
4075 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
4076 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
4077 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
4078
4079 #define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/
4080 #define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
4081 #define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
4082
4083 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
4084
4085 /****************** Bit definition for DMA_CNDTR register *******************/
4086 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
4087
4088 /****************** Bit definition for DMA_CPAR register ********************/
4089 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
4090
4091 /****************** Bit definition for DMA_CMAR register ********************/
4092 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
4093
4094
4095 /******************* Bit definition for DMA_CSELR register *******************/
4096 #define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */
4097 #define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */
4098 #define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */
4099 #define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */
4100 #define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */
4101 #define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */
4102 #define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */
4103
4104
4105 /******************************************************************************/
4106 /* */
4107 /* External Interrupt/Event Controller */
4108 /* */
4109 /******************************************************************************/
4110 /******************* Bit definition for EXTI_IMR1 register ******************/
4111 #define EXTI_IMR1_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
4112 #define EXTI_IMR1_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
4113 #define EXTI_IMR1_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
4114 #define EXTI_IMR1_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
4115 #define EXTI_IMR1_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
4116 #define EXTI_IMR1_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
4117 #define EXTI_IMR1_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
4118 #define EXTI_IMR1_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
4119 #define EXTI_IMR1_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
4120 #define EXTI_IMR1_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
4121 #define EXTI_IMR1_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
4122 #define EXTI_IMR1_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
4123 #define EXTI_IMR1_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
4124 #define EXTI_IMR1_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
4125 #define EXTI_IMR1_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
4126 #define EXTI_IMR1_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
4127 #define EXTI_IMR1_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
4128 #define EXTI_IMR1_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
4129 #define EXTI_IMR1_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
4130 #define EXTI_IMR1_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
4131 #define EXTI_IMR1_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
4132 #define EXTI_IMR1_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
4133 #define EXTI_IMR1_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
4134 #define EXTI_IMR1_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
4135 #define EXTI_IMR1_IM24 ((uint32_t)0x01000000U) /*!< Interrupt Mask on line 24 */
4136 #define EXTI_IMR1_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */
4137 #define EXTI_IMR1_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */
4138 #define EXTI_IMR1_IM27 ((uint32_t)0x08000000U) /*!< Interrupt Mask on line 27 */
4139 #define EXTI_IMR1_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */
4140 #define EXTI_IMR1_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */
4141 #define EXTI_IMR1_IM30 ((uint32_t)0x40000000U) /*!< Interrupt Mask on line 30 */
4142 #define EXTI_IMR1_IM31 ((uint32_t)0x80000000U) /*!< Interrupt Mask on line 31 */
4143
4144 /******************* Bit definition for EXTI_EMR1 register ******************/
4145 #define EXTI_EMR1_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
4146 #define EXTI_EMR1_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
4147 #define EXTI_EMR1_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
4148 #define EXTI_EMR1_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
4149 #define EXTI_EMR1_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
4150 #define EXTI_EMR1_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
4151 #define EXTI_EMR1_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
4152 #define EXTI_EMR1_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
4153 #define EXTI_EMR1_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
4154 #define EXTI_EMR1_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
4155 #define EXTI_EMR1_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
4156 #define EXTI_EMR1_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
4157 #define EXTI_EMR1_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
4158 #define EXTI_EMR1_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
4159 #define EXTI_EMR1_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
4160 #define EXTI_EMR1_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
4161 #define EXTI_EMR1_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
4162 #define EXTI_EMR1_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
4163 #define EXTI_EMR1_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
4164 #define EXTI_EMR1_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
4165 #define EXTI_EMR1_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
4166 #define EXTI_EMR1_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
4167 #define EXTI_EMR1_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
4168 #define EXTI_EMR1_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
4169 #define EXTI_EMR1_EM24 ((uint32_t)0x01000000U) /*!< Event Mask on line 24 */
4170 #define EXTI_EMR1_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */
4171 #define EXTI_EMR1_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */
4172 #define EXTI_EMR1_EM27 ((uint32_t)0x08000000U) /*!< Event Mask on line 27 */
4173 #define EXTI_EMR1_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */
4174 #define EXTI_EMR1_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */
4175 #define EXTI_EMR1_EM30 ((uint32_t)0x40000000U) /*!< Event Mask on line 30 */
4176 #define EXTI_EMR1_EM31 ((uint32_t)0x80000000U) /*!< Event Mask on line 31 */
4177
4178 /****************** Bit definition for EXTI_RTSR1 register ******************/
4179 #define EXTI_RTSR1_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
4180 #define EXTI_RTSR1_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
4181 #define EXTI_RTSR1_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
4182 #define EXTI_RTSR1_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
4183 #define EXTI_RTSR1_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
4184 #define EXTI_RTSR1_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
4185 #define EXTI_RTSR1_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
4186 #define EXTI_RTSR1_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
4187 #define EXTI_RTSR1_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
4188 #define EXTI_RTSR1_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
4189 #define EXTI_RTSR1_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
4190 #define EXTI_RTSR1_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
4191 #define EXTI_RTSR1_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
4192 #define EXTI_RTSR1_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
4193 #define EXTI_RTSR1_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
4194 #define EXTI_RTSR1_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
4195 #define EXTI_RTSR1_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
4196 #define EXTI_RTSR1_RT18 ((uint32_t)0x00040000U) /*!< Rising trigger event configuration bit of line 18 */
4197 #define EXTI_RTSR1_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
4198 #define EXTI_RTSR1_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
4199 #define EXTI_RTSR1_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
4200 #define EXTI_RTSR1_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
4201
4202 /****************** Bit definition for EXTI_FTSR1 register ******************/
4203 #define EXTI_FTSR1_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
4204 #define EXTI_FTSR1_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
4205 #define EXTI_FTSR1_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
4206 #define EXTI_FTSR1_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
4207 #define EXTI_FTSR1_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
4208 #define EXTI_FTSR1_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
4209 #define EXTI_FTSR1_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
4210 #define EXTI_FTSR1_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
4211 #define EXTI_FTSR1_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
4212 #define EXTI_FTSR1_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
4213 #define EXTI_FTSR1_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
4214 #define EXTI_FTSR1_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
4215 #define EXTI_FTSR1_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
4216 #define EXTI_FTSR1_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
4217 #define EXTI_FTSR1_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
4218 #define EXTI_FTSR1_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
4219 #define EXTI_FTSR1_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
4220 #define EXTI_FTSR1_FT18 ((uint32_t)0x00040000U) /*!< Falling trigger event configuration bit of line 18 */
4221 #define EXTI_FTSR1_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
4222 #define EXTI_FTSR1_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
4223 #define EXTI_FTSR1_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
4224 #define EXTI_FTSR1_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
4225
4226 /****************** Bit definition for EXTI_SWIER1 register *****************/
4227 #define EXTI_SWIER1_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
4228 #define EXTI_SWIER1_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
4229 #define EXTI_SWIER1_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
4230 #define EXTI_SWIER1_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
4231 #define EXTI_SWIER1_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
4232 #define EXTI_SWIER1_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
4233 #define EXTI_SWIER1_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
4234 #define EXTI_SWIER1_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
4235 #define EXTI_SWIER1_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
4236 #define EXTI_SWIER1_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
4237 #define EXTI_SWIER1_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
4238 #define EXTI_SWIER1_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
4239 #define EXTI_SWIER1_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
4240 #define EXTI_SWIER1_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
4241 #define EXTI_SWIER1_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
4242 #define EXTI_SWIER1_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
4243 #define EXTI_SWIER1_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
4244 #define EXTI_SWIER1_SWI18 ((uint32_t)0x00040000U) /*!< Software Interrupt on line 18 */
4245 #define EXTI_SWIER1_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
4246 #define EXTI_SWIER1_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
4247 #define EXTI_SWIER1_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
4248 #define EXTI_SWIER1_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
4249
4250 /******************* Bit definition for EXTI_PR1 register *******************/
4251 #define EXTI_PR1_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit for line 0 */
4252 #define EXTI_PR1_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit for line 1 */
4253 #define EXTI_PR1_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit for line 2 */
4254 #define EXTI_PR1_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit for line 3 */
4255 #define EXTI_PR1_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit for line 4 */
4256 #define EXTI_PR1_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit for line 5 */
4257 #define EXTI_PR1_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit for line 6 */
4258 #define EXTI_PR1_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit for line 7 */
4259 #define EXTI_PR1_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit for line 8 */
4260 #define EXTI_PR1_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit for line 9 */
4261 #define EXTI_PR1_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit for line 10 */
4262 #define EXTI_PR1_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit for line 11 */
4263 #define EXTI_PR1_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit for line 12 */
4264 #define EXTI_PR1_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit for line 13 */
4265 #define EXTI_PR1_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit for line 14 */
4266 #define EXTI_PR1_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit for line 15 */
4267 #define EXTI_PR1_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit for line 16 */
4268 #define EXTI_PR1_PIF18 ((uint32_t)0x00040000U) /*!< Pending bit for line 18 */
4269 #define EXTI_PR1_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit for line 19 */
4270 #define EXTI_PR1_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit for line 20 */
4271 #define EXTI_PR1_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit for line 21 */
4272 #define EXTI_PR1_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit for line 22 */
4273
4274 /******************* Bit definition for EXTI_IMR2 register ******************/
4275 #define EXTI_IMR2_IM32 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 32 */
4276 #define EXTI_IMR2_IM33 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 33 */
4277 #define EXTI_IMR2_IM34 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 34 */
4278 #define EXTI_IMR2_IM35 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 35 */
4279 #define EXTI_IMR2_IM36 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 36 */
4280 #define EXTI_IMR2_IM37 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 37 */
4281 #define EXTI_IMR2_IM38 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 38 */
4282 #define EXTI_IMR2_IM39 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 39 */
4283
4284 /******************* Bit definition for EXTI_EMR2 register ******************/
4285 #define EXTI_EMR2_EM32 ((uint32_t)0x00000001U) /*!< Event Mask on line 32 */
4286 #define EXTI_EMR2_EM33 ((uint32_t)0x00000002U) /*!< Event Mask on line 33 */
4287 #define EXTI_EMR2_EM34 ((uint32_t)0x00000004U) /*!< Event Mask on line 34 */
4288 #define EXTI_EMR2_EM35 ((uint32_t)0x00000008U) /*!< Event Mask on line 35 */
4289 #define EXTI_EMR2_EM36 ((uint32_t)0x00000010U) /*!< Event Mask on line 36 */
4290 #define EXTI_EMR2_EM37 ((uint32_t)0x00000020U) /*!< Event Mask on line 37 */
4291 #define EXTI_EMR2_EM38 ((uint32_t)0x00000040U) /*!< Event Mask on line 38 */
4292 #define EXTI_EMR2_EM39 ((uint32_t)0x00000080U) /*!< Event Mask on line 39 */
4293
4294 /****************** Bit definition for EXTI_RTSR2 register ******************/
4295 #define EXTI_RTSR2_RT35 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 35 */
4296 #define EXTI_RTSR2_RT36 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 36 */
4297 #define EXTI_RTSR2_RT37 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 37 */
4298 #define EXTI_RTSR2_RT38 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 38 */
4299
4300 /****************** Bit definition for EXTI_FTSR2 register ******************/
4301 #define EXTI_FTSR2_FT35 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 35 */
4302 #define EXTI_FTSR2_FT36 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 36 */
4303 #define EXTI_FTSR2_FT37 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 37 */
4304 #define EXTI_FTSR2_FT38 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 38 */
4305
4306 /****************** Bit definition for EXTI_SWIER2 register *****************/
4307 #define EXTI_SWIER2_SWI35 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 35 */
4308 #define EXTI_SWIER2_SWI36 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 36 */
4309 #define EXTI_SWIER2_SWI37 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 37 */
4310 #define EXTI_SWIER2_SWI38 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 38 */
4311
4312 /******************* Bit definition for EXTI_PR2 register *******************/
4313 #define EXTI_PR2_PIF35 ((uint32_t)0x00000008U) /*!< Pending bit for line 35 */
4314 #define EXTI_PR2_PIF36 ((uint32_t)0x00000010U) /*!< Pending bit for line 36 */
4315 #define EXTI_PR2_PIF37 ((uint32_t)0x00000020U) /*!< Pending bit for line 37 */
4316 #define EXTI_PR2_PIF38 ((uint32_t)0x00000040U) /*!< Pending bit for line 38 */
4317
4318
4319 /******************************************************************************/
4320 /* */
4321 /* FLASH */
4322 /* */
4323 /******************************************************************************/
4324 /******************* Bits definition for FLASH_ACR register *****************/
4325 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007U)
4326 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000U)
4327 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001U)
4328 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002U)
4329 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003U)
4330 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004U)
4331 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100U)
4332 #define FLASH_ACR_ICEN ((uint32_t)0x00000200U)
4333 #define FLASH_ACR_DCEN ((uint32_t)0x00000400U)
4334 #define FLASH_ACR_ICRST ((uint32_t)0x00000800U)
4335 #define FLASH_ACR_DCRST ((uint32_t)0x00001000U)
4336 #define FLASH_ACR_RUN_PD ((uint32_t)0x00002000U) /*!< Flash power down mode during run */
4337 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00004000U) /*!< Flash power down mode during sleep */
4338
4339 /******************* Bits definition for FLASH_SR register ******************/
4340 #define FLASH_SR_EOP ((uint32_t)0x00000001U)
4341 #define FLASH_SR_OPERR ((uint32_t)0x00000002U)
4342 #define FLASH_SR_PROGERR ((uint32_t)0x00000008U)
4343 #define FLASH_SR_WRPERR ((uint32_t)0x00000010U)
4344 #define FLASH_SR_PGAERR ((uint32_t)0x00000020U)
4345 #define FLASH_SR_SIZERR ((uint32_t)0x00000040U)
4346 #define FLASH_SR_PGSERR ((uint32_t)0x00000080U)
4347 #define FLASH_SR_MISERR ((uint32_t)0x00000100U)
4348 #define FLASH_SR_FASTERR ((uint32_t)0x00000200U)
4349 #define FLASH_SR_RDERR ((uint32_t)0x00004000U)
4350 #define FLASH_SR_OPTVERR ((uint32_t)0x00008000U)
4351 #define FLASH_SR_BSY ((uint32_t)0x00010000U)
4352
4353 /******************* Bits definition for FLASH_CR register ******************/
4354 #define FLASH_CR_PG ((uint32_t)0x00000001U)
4355 #define FLASH_CR_PER ((uint32_t)0x00000002U)
4356 #define FLASH_CR_MER1 ((uint32_t)0x00000004U)
4357 #define FLASH_CR_PNB ((uint32_t)0x000007F8U)
4358 #define FLASH_CR_BKER ((uint32_t)0x00000800U)
4359 #define FLASH_CR_MER2 ((uint32_t)0x00008000U)
4360 #define FLASH_CR_STRT ((uint32_t)0x00010000U)
4361 #define FLASH_CR_OPTSTRT ((uint32_t)0x00020000U)
4362 #define FLASH_CR_FSTPG ((uint32_t)0x00040000U)
4363 #define FLASH_CR_EOPIE ((uint32_t)0x01000000U)
4364 #define FLASH_CR_ERRIE ((uint32_t)0x02000000U)
4365 #define FLASH_CR_RDERRIE ((uint32_t)0x04000000U)
4366 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x08000000U)
4367 #define FLASH_CR_OPTLOCK ((uint32_t)0x40000000U)
4368 #define FLASH_CR_LOCK ((uint32_t)0x80000000U)
4369
4370 /******************* Bits definition for FLASH_ECCR register ***************/
4371 #define FLASH_ECCR_ADDR_ECC ((uint32_t)0x0007FFFFU)
4372 #define FLASH_ECCR_BK_ECC ((uint32_t)0x00080000U)
4373 #define FLASH_ECCR_SYSF_ECC ((uint32_t)0x00100000U)
4374 #define FLASH_ECCR_ECCIE ((uint32_t)0x01000000U)
4375 #define FLASH_ECCR_ECCC ((uint32_t)0x40000000U)
4376 #define FLASH_ECCR_ECCD ((uint32_t)0x80000000U)
4377
4378 /******************* Bits definition for FLASH_OPTR register ***************/
4379 #define FLASH_OPTR_RDP ((uint32_t)0x000000FFU)
4380 #define FLASH_OPTR_BOR_LEV ((uint32_t)0x00000700U)
4381 #define FLASH_OPTR_BOR_LEV_0 ((uint32_t)0x00000000U)
4382 #define FLASH_OPTR_BOR_LEV_1 ((uint32_t)0x00000100U)
4383 #define FLASH_OPTR_BOR_LEV_2 ((uint32_t)0x00000200U)
4384 #define FLASH_OPTR_BOR_LEV_3 ((uint32_t)0x00000300U)
4385 #define FLASH_OPTR_BOR_LEV_4 ((uint32_t)0x00000400U)
4386 #define FLASH_OPTR_nRST_STOP ((uint32_t)0x00001000U)
4387 #define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00002000U)
4388 #define FLASH_OPTR_nRST_SHDW ((uint32_t)0x00004000U)
4389 #define FLASH_OPTR_IWDG_SW ((uint32_t)0x00010000U)
4390 #define FLASH_OPTR_IWDG_STOP ((uint32_t)0x00020000U)
4391 #define FLASH_OPTR_IWDG_STDBY ((uint32_t)0x00040000U)
4392 #define FLASH_OPTR_WWDG_SW ((uint32_t)0x00080000U)
4393 #define FLASH_OPTR_BFB2 ((uint32_t)0x00100000U)
4394 #define FLASH_OPTR_DUALBANK ((uint32_t)0x00200000U)
4395 #define FLASH_OPTR_nBOOT1 ((uint32_t)0x00800000U)
4396 #define FLASH_OPTR_SRAM2_PE ((uint32_t)0x01000000U)
4397 #define FLASH_OPTR_SRAM2_RST ((uint32_t)0x02000000U)
4398
4399 /****************** Bits definition for FLASH_PCROP1SR register **********/
4400 #define FLASH_PCROP1SR_PCROP1_STRT ((uint32_t)0x0000FFFFU)
4401
4402 /****************** Bits definition for FLASH_PCROP1ER register ***********/
4403 #define FLASH_PCROP1ER_PCROP1_END ((uint32_t)0x0000FFFFU)
4404 #define FLASH_PCROP1ER_PCROP_RDP ((uint32_t)0x80000000U)
4405
4406 /****************** Bits definition for FLASH_WRP1AR register ***************/
4407 #define FLASH_WRP1AR_WRP1A_STRT ((uint32_t)0x000000FFU)
4408 #define FLASH_WRP1AR_WRP1A_END ((uint32_t)0x00FF0000U)
4409
4410 /****************** Bits definition for FLASH_WRPB1R register ***************/
4411 #define FLASH_WRP1BR_WRP1B_STRT ((uint32_t)0x000000FFU)
4412 #define FLASH_WRP1BR_WRP1B_END ((uint32_t)0x00FF0000U)
4413
4414 /****************** Bits definition for FLASH_PCROP2SR register **********/
4415 #define FLASH_PCROP2SR_PCROP2_STRT ((uint32_t)0x0000FFFFU)
4416
4417 /****************** Bits definition for FLASH_PCROP2ER register ***********/
4418 #define FLASH_PCROP2ER_PCROP2_END ((uint32_t)0x0000FFFFU)
4419
4420 /****************** Bits definition for FLASH_WRP2AR register ***************/
4421 #define FLASH_WRP2AR_WRP2A_STRT ((uint32_t)0x000000FFU)
4422 #define FLASH_WRP2AR_WRP2A_END ((uint32_t)0x00FF0000U)
4423
4424 /****************** Bits definition for FLASH_WRP2BR register ***************/
4425 #define FLASH_WRP2BR_WRP2B_STRT ((uint32_t)0x000000FFU)
4426 #define FLASH_WRP2BR_WRP2B_END ((uint32_t)0x00FF0000U)
4427
4428
4429 /******************************************************************************/
4430 /* */
4431 /* Flexible Memory Controller */
4432 /* */
4433 /******************************************************************************/
4434 /****************** Bit definition for FMC_BCR1 register *******************/
4435 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000U) /*!<Continous clock enable */
4436
4437 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
4438 #define FMC_BCRx_MBKEN ((uint32_t)0x00000001U) /*!<Memory bank enable bit */
4439 #define FMC_BCRx_MUXEN ((uint32_t)0x00000002U) /*!<Address/data multiplexing enable bit */
4440
4441 #define FMC_BCRx_MTYP ((uint32_t)0x0000000CU) /*!<MTYP[1:0] bits (Memory type) */
4442 #define FMC_BCRx_MTYP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
4443 #define FMC_BCRx_MTYP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
4444
4445 #define FMC_BCRx_MWID ((uint32_t)0x00000030U) /*!<MWID[1:0] bits (Memory data bus width) */
4446 #define FMC_BCRx_MWID_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
4447 #define FMC_BCRx_MWID_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
4448
4449 #define FMC_BCRx_FACCEN ((uint32_t)0x00000040U) /*!<Flash access enable */
4450 #define FMC_BCRx_BURSTEN ((uint32_t)0x00000100U) /*!<Burst enable bit */
4451 #define FMC_BCRx_WAITPOL ((uint32_t)0x00000200U) /*!<Wait signal polarity bit */
4452 #define FMC_BCRx_WAITCFG ((uint32_t)0x00000800U) /*!<Wait timing configuration */
4453 #define FMC_BCRx_WREN ((uint32_t)0x00001000U) /*!<Write enable bit */
4454 #define FMC_BCRx_WAITEN ((uint32_t)0x00002000U) /*!<Wait enable bit */
4455 #define FMC_BCRx_EXTMOD ((uint32_t)0x00004000U) /*!<Extended mode enable */
4456 #define FMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000U) /*!<Asynchronous wait */
4457
4458 #define FMC_BCRx_CPSIZE ((uint32_t)0x00070000U) /*!<CRAM page size */
4459 #define FMC_BCRx_CPSIZE_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
4460 #define FMC_BCRx_CPSIZE_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
4461 #define FMC_BCRx_CPSIZE_2 ((uint32_t)0x00040000U) /*!<Bit 1 */
4462
4463 #define FMC_BCRx_CBURSTRW ((uint32_t)0x00080000U) /*!<Write burst enable */
4464
4465 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
4466 #define FMC_BTRx_ADDSET ((uint32_t)0x0000000FU) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4467 #define FMC_BTRx_ADDSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
4468 #define FMC_BTRx_ADDSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
4469 #define FMC_BTRx_ADDSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
4470 #define FMC_BTRx_ADDSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
4471
4472 #define FMC_BTRx_ADDHLD ((uint32_t)0x000000F0U) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4473 #define FMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
4474 #define FMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
4475 #define FMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
4476 #define FMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
4477
4478 #define FMC_BTRx_DATAST ((uint32_t)0x0000FF00U) /*!<DATAST [3:0] bits (Data-phase duration) */
4479 #define FMC_BTRx_DATAST_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
4480 #define FMC_BTRx_DATAST_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
4481 #define FMC_BTRx_DATAST_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
4482 #define FMC_BTRx_DATAST_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
4483 #define FMC_BTRx_DATAST_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
4484 #define FMC_BTRx_DATAST_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
4485 #define FMC_BTRx_DATAST_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
4486 #define FMC_BTRx_DATAST_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
4487
4488 #define FMC_BTRx_BUSTURN ((uint32_t)0x000F0000U) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4489 #define FMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
4490 #define FMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
4491 #define FMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
4492 #define FMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
4493
4494 #define FMC_BTRx_CLKDIV ((uint32_t)0x00F00000U) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4495 #define FMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
4496 #define FMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
4497 #define FMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
4498 #define FMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000U) /*!<Bit 3 */
4499
4500 #define FMC_BTRx_DATLAT ((uint32_t)0x0F000000U) /*!<DATLA[3:0] bits (Data latency) */
4501 #define FMC_BTRx_DATLAT_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
4502 #define FMC_BTRx_DATLAT_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
4503 #define FMC_BTRx_DATLAT_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
4504 #define FMC_BTRx_DATLAT_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
4505
4506 #define FMC_BTRx_ACCMOD ((uint32_t)0x30000000U) /*!<ACCMOD[1:0] bits (Access mode) */
4507 #define FMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
4508 #define FMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
4509
4510 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
4511 #define FMC_BWTRx_ADDSET ((uint32_t)0x0000000FU) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4512 #define FMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
4513 #define FMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
4514 #define FMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
4515 #define FMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
4516
4517 #define FMC_BWTRx_ADDHLD ((uint32_t)0x000000F0U) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4518 #define FMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
4519 #define FMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
4520 #define FMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
4521 #define FMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
4522
4523 #define FMC_BWTRx_DATAST ((uint32_t)0x0000FF00U) /*!<DATAST [3:0] bits (Data-phase duration) */
4524 #define FMC_BWTRx_DATAST_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
4525 #define FMC_BWTRx_DATAST_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
4526 #define FMC_BWTRx_DATAST_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
4527 #define FMC_BWTRx_DATAST_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
4528 #define FMC_BWTRx_DATAST_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
4529 #define FMC_BWTRx_DATAST_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
4530 #define FMC_BWTRx_DATAST_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
4531 #define FMC_BWTRx_DATAST_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
4532
4533 #define FMC_BWTRx_ACCMOD ((uint32_t)0x30000000U) /*!<ACCMOD[1:0] bits (Access mode) */
4534 #define FMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
4535 #define FMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
4536
4537 /****************** Bit definition for FMC_PCR register ********************/
4538 #define FMC_PCR_PWAITEN ((uint32_t)0x00000002U) /*!<Wait feature enable bit */
4539 #define FMC_PCR_PBKEN ((uint32_t)0x00000004U) /*!<NAND Flash memory bank enable bit */
4540 #define FMC_PCR_PTYP ((uint32_t)0x00000008U) /*!<Memory type */
4541
4542 #define FMC_PCR_PWID ((uint32_t)0x00000030U) /*!<PWID[1:0] bits (NAND Flash databus width) */
4543 #define FMC_PCR_PWID_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
4544 #define FMC_PCR_PWID_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
4545
4546 #define FMC_PCR_ECCEN ((uint32_t)0x00000040U) /*!<ECC computation logic enable bit */
4547
4548 #define FMC_PCR_TCLR ((uint32_t)0x00001E00U) /*!<TCLR[3:0] bits (CLE to RE delay) */
4549 #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
4550 #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
4551 #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800U) /*!<Bit 2 */
4552 #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000U) /*!<Bit 3 */
4553
4554 #define FMC_PCR_TAR ((uint32_t)0x0001E000U) /*!<TAR[3:0] bits (ALE to RE delay) */
4555 #define FMC_PCR_TAR_0 ((uint32_t)0x00002000U) /*!<Bit 0 */
4556 #define FMC_PCR_TAR_1 ((uint32_t)0x00004000U) /*!<Bit 1 */
4557 #define FMC_PCR_TAR_2 ((uint32_t)0x00008000U) /*!<Bit 2 */
4558 #define FMC_PCR_TAR_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
4559
4560 #define FMC_PCR_ECCPS ((uint32_t)0x000E0000U) /*!<ECCPS[1:0] bits (ECC page size) */
4561 #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
4562 #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
4563 #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
4564
4565 /******************* Bit definition for FMC_SR register ********************/
4566 #define FMC_SR_IRS ((uint32_t)0x00000001U) /*!<Interrupt Rising Edge status */
4567 #define FMC_SR_ILS ((uint32_t)0x00000002U) /*!<Interrupt Level status */
4568 #define FMC_SR_IFS ((uint32_t)0x00000004U) /*!<Interrupt Falling Edge status */
4569 #define FMC_SR_IREN ((uint32_t)0x00000008U) /*!<Interrupt Rising Edge detection Enable bit */
4570 #define FMC_SR_ILEN ((uint32_t)0x00000010U) /*!<Interrupt Level detection Enable bit */
4571 #define FMC_SR_IFEN ((uint32_t)0x00000020U) /*!<Interrupt Falling Edge detection Enable bit */
4572 #define FMC_SR_FEMPT ((uint32_t)0x00000040U) /*!<FIFO empty */
4573
4574 /****************** Bit definition for FMC_PMEM register ******************/
4575 #define FMC_PMEM_MEMSET ((uint32_t)0x000000FFU) /*!<MEMSET[7:0] bits (Common memory setup time) */
4576 #define FMC_PMEM_MEMSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
4577 #define FMC_PMEM_MEMSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
4578 #define FMC_PMEM_MEMSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
4579 #define FMC_PMEM_MEMSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
4580 #define FMC_PMEM_MEMSET_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
4581 #define FMC_PMEM_MEMSET_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
4582 #define FMC_PMEM_MEMSET_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
4583 #define FMC_PMEM_MEMSET_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
4584
4585 #define FMC_PMEM_MEMWAIT ((uint32_t)0x0000FF00U) /*!<MEMWAIT[7:0] bits (Common memory wait time) */
4586 #define FMC_PMEM_MEMWAIT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
4587 #define FMC_PMEM_MEMWAIT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
4588 #define FMC_PMEM_MEMWAIT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
4589 #define FMC_PMEM_MEMWAIT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
4590 #define FMC_PMEM_MEMWAIT_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
4591 #define FMC_PMEM_MEMWAIT_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
4592 #define FMC_PMEM_MEMWAIT_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
4593 #define FMC_PMEM_MEMWAIT_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
4594
4595 #define FMC_PMEM_MEMHOLD ((uint32_t)0x00FF0000U) /*!<MEMHOLD[7:0] bits (Common memory hold time) */
4596 #define FMC_PMEM_MEMHOLD_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
4597 #define FMC_PMEM_MEMHOLD_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
4598 #define FMC_PMEM_MEMHOLD_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
4599 #define FMC_PMEM_MEMHOLD_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
4600 #define FMC_PMEM_MEMHOLD_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
4601 #define FMC_PMEM_MEMHOLD_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
4602 #define FMC_PMEM_MEMHOLD_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
4603 #define FMC_PMEM_MEMHOLD_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
4604
4605 #define FMC_PMEM_MEMHIZ ((uint32_t)0xFF000000U) /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
4606 #define FMC_PMEM_MEMHIZ_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
4607 #define FMC_PMEM_MEMHIZ_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
4608 #define FMC_PMEM_MEMHIZ_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
4609 #define FMC_PMEM_MEMHIZ_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
4610 #define FMC_PMEM_MEMHIZ_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
4611 #define FMC_PMEM_MEMHIZ_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
4612 #define FMC_PMEM_MEMHIZ_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
4613 #define FMC_PMEM_MEMHIZ_7 ((uint32_t)0x80000000U) /*!<Bit 7 */
4614
4615 /****************** Bit definition for FMC_PATT register *******************/
4616 #define FMC_PATT_ATTSET ((uint32_t)0x000000FFU) /*!<ATTSET[7:0] bits (Attribute memory setup time) */
4617 #define FMC_PATT_ATTSET_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
4618 #define FMC_PATT_ATTSET_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
4619 #define FMC_PATT_ATTSET_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
4620 #define FMC_PATT_ATTSET_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
4621 #define FMC_PATT_ATTSET_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
4622 #define FMC_PATT_ATTSET_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
4623 #define FMC_PATT_ATTSET_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
4624 #define FMC_PATT_ATTSET_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
4625
4626 #define FMC_PATT_ATTWAIT ((uint32_t)0x0000FF00U) /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
4627 #define FMC_PATT_ATTWAIT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
4628 #define FMC_PATT_ATTWAIT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
4629 #define FMC_PATT_ATTWAIT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
4630 #define FMC_PATT_ATTWAIT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
4631 #define FMC_PATT_ATTWAIT_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
4632 #define FMC_PATT_ATTWAIT_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
4633 #define FMC_PATT_ATTWAIT_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
4634 #define FMC_PATT_ATTWAIT_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
4635
4636 #define FMC_PATT_ATTHOLD ((uint32_t)0x00FF0000U) /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
4637 #define FMC_PATT_ATTHOLD_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
4638 #define FMC_PATT_ATTHOLD_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
4639 #define FMC_PATT_ATTHOLD_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
4640 #define FMC_PATT_ATTHOLD_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
4641 #define FMC_PATT_ATTHOLD_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
4642 #define FMC_PATT_ATTHOLD_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
4643 #define FMC_PATT_ATTHOLD_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
4644 #define FMC_PATT_ATTHOLD_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
4645
4646 #define FMC_PATT_ATTHIZ ((uint32_t)0xFF000000U) /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
4647 #define FMC_PATT_ATTHIZ_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
4648 #define FMC_PATT_ATTHIZ_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
4649 #define FMC_PATT_ATTHIZ_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
4650 #define FMC_PATT_ATTHIZ_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
4651 #define FMC_PATT_ATTHIZ_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
4652 #define FMC_PATT_ATTHIZ_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
4653 #define FMC_PATT_ATTHIZ_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
4654 #define FMC_PATT_ATTHIZ_7 ((uint32_t)0x80000000U) /*!<Bit 7 */
4655
4656 /****************** Bit definition for FMC_ECCR register *******************/
4657 #define FMC_ECCR_ECC ((uint32_t)0xFFFFFFFFU) /*!<ECC result */
4658
4659 /******************************************************************************/
4660 /* */
4661 /* General Purpose IOs (GPIO) */
4662 /* */
4663 /******************************************************************************/
4664 /****************** Bits definition for GPIO_MODER register *****************/
4665 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
4666 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
4667 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
4668 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
4669 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
4670 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
4671 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
4672 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
4673 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
4674 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
4675 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
4676 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
4677 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
4678 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
4679 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
4680 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
4681 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
4682 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
4683 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
4684 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
4685 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
4686 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
4687 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
4688 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
4689 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
4690 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
4691 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
4692 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
4693 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
4694 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
4695 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
4696 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
4697 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
4698 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
4699 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
4700 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
4701 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
4702 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
4703 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
4704 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
4705 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
4706 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
4707 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
4708 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
4709 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
4710 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
4711 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
4712 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
4713
4714 /* Legacy defines */
4715 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
4716 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
4717 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
4718 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
4719 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
4720 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
4721 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
4722 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
4723 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
4724 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
4725 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
4726 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
4727 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
4728 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
4729 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
4730 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
4731 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
4732 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
4733 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
4734 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
4735 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
4736 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
4737 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
4738 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
4739 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
4740 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
4741 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
4742 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
4743 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
4744 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
4745 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
4746 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
4747 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
4748 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
4749 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
4750 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
4751 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
4752 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
4753 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
4754 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
4755 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
4756 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
4757 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
4758 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
4759 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
4760 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
4761 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
4762 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
4763
4764 /****************** Bits definition for GPIO_OTYPER register ****************/
4765 #define GPIO_OTYPER_OT0 ((uint32_t)0x00000001U)
4766 #define GPIO_OTYPER_OT1 ((uint32_t)0x00000002U)
4767 #define GPIO_OTYPER_OT2 ((uint32_t)0x00000004U)
4768 #define GPIO_OTYPER_OT3 ((uint32_t)0x00000008U)
4769 #define GPIO_OTYPER_OT4 ((uint32_t)0x00000010U)
4770 #define GPIO_OTYPER_OT5 ((uint32_t)0x00000020U)
4771 #define GPIO_OTYPER_OT6 ((uint32_t)0x00000040U)
4772 #define GPIO_OTYPER_OT7 ((uint32_t)0x00000080U)
4773 #define GPIO_OTYPER_OT8 ((uint32_t)0x00000100U)
4774 #define GPIO_OTYPER_OT9 ((uint32_t)0x00000200U)
4775 #define GPIO_OTYPER_OT10 ((uint32_t)0x00000400U)
4776 #define GPIO_OTYPER_OT11 ((uint32_t)0x00000800U)
4777 #define GPIO_OTYPER_OT12 ((uint32_t)0x00001000U)
4778 #define GPIO_OTYPER_OT13 ((uint32_t)0x00002000U)
4779 #define GPIO_OTYPER_OT14 ((uint32_t)0x00004000U)
4780 #define GPIO_OTYPER_OT15 ((uint32_t)0x00008000U)
4781
4782 /* Legacy defines */
4783 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
4784 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
4785 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
4786 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
4787 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
4788 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
4789 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
4790 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
4791 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
4792 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
4793 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
4794 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
4795 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
4796 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
4797 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
4798 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
4799
4800 /****************** Bits definition for GPIO_OSPEEDR register ***************/
4801 #define GPIO_OSPEEDR_OSPEED0 ((uint32_t)0x00000003U)
4802 #define GPIO_OSPEEDR_OSPEED0_0 ((uint32_t)0x00000001U)
4803 #define GPIO_OSPEEDR_OSPEED0_1 ((uint32_t)0x00000002U)
4804 #define GPIO_OSPEEDR_OSPEED1 ((uint32_t)0x0000000CU)
4805 #define GPIO_OSPEEDR_OSPEED1_0 ((uint32_t)0x00000004U)
4806 #define GPIO_OSPEEDR_OSPEED1_1 ((uint32_t)0x00000008U)
4807 #define GPIO_OSPEEDR_OSPEED2 ((uint32_t)0x00000030U)
4808 #define GPIO_OSPEEDR_OSPEED2_0 ((uint32_t)0x00000010U)
4809 #define GPIO_OSPEEDR_OSPEED2_1 ((uint32_t)0x00000020U)
4810 #define GPIO_OSPEEDR_OSPEED3 ((uint32_t)0x000000C0U)
4811 #define GPIO_OSPEEDR_OSPEED3_0 ((uint32_t)0x00000040U)
4812 #define GPIO_OSPEEDR_OSPEED3_1 ((uint32_t)0x00000080U)
4813 #define GPIO_OSPEEDR_OSPEED4 ((uint32_t)0x00000300U)
4814 #define GPIO_OSPEEDR_OSPEED4_0 ((uint32_t)0x00000100U)
4815 #define GPIO_OSPEEDR_OSPEED4_1 ((uint32_t)0x00000200U)
4816 #define GPIO_OSPEEDR_OSPEED5 ((uint32_t)0x00000C00U)
4817 #define GPIO_OSPEEDR_OSPEED5_0 ((uint32_t)0x00000400U)
4818 #define GPIO_OSPEEDR_OSPEED5_1 ((uint32_t)0x00000800U)
4819 #define GPIO_OSPEEDR_OSPEED6 ((uint32_t)0x00003000U)
4820 #define GPIO_OSPEEDR_OSPEED6_0 ((uint32_t)0x00001000U)
4821 #define GPIO_OSPEEDR_OSPEED6_1 ((uint32_t)0x00002000U)
4822 #define GPIO_OSPEEDR_OSPEED7 ((uint32_t)0x0000C000U)
4823 #define GPIO_OSPEEDR_OSPEED7_0 ((uint32_t)0x00004000U)
4824 #define GPIO_OSPEEDR_OSPEED7_1 ((uint32_t)0x00008000U)
4825 #define GPIO_OSPEEDR_OSPEED8 ((uint32_t)0x00030000U)
4826 #define GPIO_OSPEEDR_OSPEED8_0 ((uint32_t)0x00010000U)
4827 #define GPIO_OSPEEDR_OSPEED8_1 ((uint32_t)0x00020000U)
4828 #define GPIO_OSPEEDR_OSPEED9 ((uint32_t)0x000C0000U)
4829 #define GPIO_OSPEEDR_OSPEED9_0 ((uint32_t)0x00040000U)
4830 #define GPIO_OSPEEDR_OSPEED9_1 ((uint32_t)0x00080000U)
4831 #define GPIO_OSPEEDR_OSPEED10 ((uint32_t)0x00300000U)
4832 #define GPIO_OSPEEDR_OSPEED10_0 ((uint32_t)0x00100000U)
4833 #define GPIO_OSPEEDR_OSPEED10_1 ((uint32_t)0x00200000U)
4834 #define GPIO_OSPEEDR_OSPEED11 ((uint32_t)0x00C00000U)
4835 #define GPIO_OSPEEDR_OSPEED11_0 ((uint32_t)0x00400000U)
4836 #define GPIO_OSPEEDR_OSPEED11_1 ((uint32_t)0x00800000U)
4837 #define GPIO_OSPEEDR_OSPEED12 ((uint32_t)0x03000000U)
4838 #define GPIO_OSPEEDR_OSPEED12_0 ((uint32_t)0x01000000U)
4839 #define GPIO_OSPEEDR_OSPEED12_1 ((uint32_t)0x02000000U)
4840 #define GPIO_OSPEEDR_OSPEED13 ((uint32_t)0x0C000000U)
4841 #define GPIO_OSPEEDR_OSPEED13_0 ((uint32_t)0x04000000U)
4842 #define GPIO_OSPEEDR_OSPEED13_1 ((uint32_t)0x08000000U)
4843 #define GPIO_OSPEEDR_OSPEED14 ((uint32_t)0x30000000U)
4844 #define GPIO_OSPEEDR_OSPEED14_0 ((uint32_t)0x10000000U)
4845 #define GPIO_OSPEEDR_OSPEED14_1 ((uint32_t)0x20000000U)
4846 #define GPIO_OSPEEDR_OSPEED15 ((uint32_t)0xC0000000U)
4847 #define GPIO_OSPEEDR_OSPEED15_0 ((uint32_t)0x40000000U)
4848 #define GPIO_OSPEEDR_OSPEED15_1 ((uint32_t)0x80000000U)
4849
4850 /* Legacy defines */
4851 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
4852 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
4853 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
4854 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
4855 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
4856 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
4857 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
4858 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
4859 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
4860 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
4861 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
4862 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
4863 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
4864 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
4865 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
4866 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
4867 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
4868 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
4869 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
4870 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
4871 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
4872 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
4873 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
4874 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
4875 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
4876 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
4877 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
4878 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
4879 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
4880 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
4881 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
4882 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
4883 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
4884 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
4885 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
4886 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
4887 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
4888 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
4889 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
4890 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
4891 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
4892 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
4893 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
4894 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
4895 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
4896 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
4897 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
4898 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
4899
4900 /****************** Bits definition for GPIO_PUPDR register *****************/
4901 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
4902 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
4903 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
4904 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
4905 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
4906 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
4907 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
4908 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
4909 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
4910 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
4911 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
4912 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
4913 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
4914 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
4915 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
4916 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
4917 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
4918 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
4919 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
4920 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
4921 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
4922 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
4923 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
4924 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
4925 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
4926 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
4927 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
4928 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
4929 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
4930 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
4931 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
4932 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
4933 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
4934 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
4935 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
4936 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
4937 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
4938 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
4939 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
4940 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
4941 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
4942 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
4943 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
4944 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
4945 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
4946 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
4947 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
4948 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
4949
4950 /* Legacy defines */
4951 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
4952 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
4953 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
4954 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
4955 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
4956 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
4957 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
4958 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
4959 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
4960 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
4961 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
4962 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
4963 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
4964 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
4965 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
4966 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
4967 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
4968 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
4969 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
4970 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
4971 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
4972 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
4973 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
4974 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
4975 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
4976 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
4977 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
4978 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
4979 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
4980 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
4981 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
4982 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
4983 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
4984 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
4985 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
4986 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
4987 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
4988 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
4989 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
4990 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
4991 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
4992 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
4993 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
4994 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
4995 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
4996 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
4997 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
4998 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
4999
5000 /****************** Bits definition for GPIO_IDR register *******************/
5001 #define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
5002 #define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
5003 #define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
5004 #define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
5005 #define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
5006 #define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
5007 #define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
5008 #define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
5009 #define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
5010 #define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
5011 #define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
5012 #define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
5013 #define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
5014 #define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
5015 #define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
5016 #define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
5017
5018 /* Legacy defines */
5019 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
5020 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
5021 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
5022 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
5023 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
5024 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
5025 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
5026 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
5027 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
5028 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
5029 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
5030 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
5031 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
5032 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
5033 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
5034 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
5035
5036 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
5037 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
5038 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
5039 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
5040 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
5041 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
5042 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
5043 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
5044 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
5045 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
5046 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
5047 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
5048 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
5049 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
5050 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
5051 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
5052 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
5053
5054 /****************** Bits definition for GPIO_ODR register *******************/
5055 #define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
5056 #define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
5057 #define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
5058 #define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
5059 #define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
5060 #define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
5061 #define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
5062 #define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
5063 #define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
5064 #define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
5065 #define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
5066 #define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
5067 #define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
5068 #define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
5069 #define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
5070 #define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
5071
5072 /* Legacy defines */
5073 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
5074 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
5075 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
5076 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
5077 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
5078 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
5079 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
5080 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
5081 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
5082 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
5083 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
5084 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
5085 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
5086 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
5087 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
5088 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
5089
5090 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
5091 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
5092 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
5093 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
5094 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
5095 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
5096 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
5097 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
5098 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
5099 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
5100 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
5101 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
5102 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
5103 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
5104 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
5105 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
5106 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
5107
5108 /****************** Bits definition for GPIO_BSRR register ******************/
5109 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001U)
5110 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002U)
5111 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004U)
5112 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008U)
5113 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010U)
5114 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020U)
5115 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040U)
5116 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080U)
5117 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100U)
5118 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200U)
5119 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400U)
5120 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800U)
5121 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000U)
5122 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000U)
5123 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000U)
5124 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000U)
5125 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000U)
5126 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000U)
5127 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000U)
5128 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000U)
5129 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000U)
5130 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000U)
5131 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000U)
5132 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000U)
5133 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000U)
5134 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000U)
5135 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000U)
5136 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000U)
5137 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000U)
5138 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000U)
5139 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000U)
5140 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000U)
5141
5142 /* Legacy defines */
5143 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
5144 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
5145 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
5146 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
5147 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
5148 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
5149 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
5150 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
5151 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
5152 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
5153 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
5154 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
5155 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
5156 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
5157 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
5158 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
5159 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
5160 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
5161 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
5162 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
5163 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
5164 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
5165 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
5166 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
5167 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
5168 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
5169 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
5170 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
5171 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
5172 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
5173 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
5174 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
5175
5176 /****************** Bit definition for GPIO_LCKR register *********************/
5177 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
5178 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
5179 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
5180 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
5181 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
5182 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
5183 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
5184 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
5185 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
5186 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
5187 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
5188 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
5189 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
5190 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
5191 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
5192 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
5193 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
5194
5195 /****************** Bit definition for GPIO_AFRL register *********************/
5196 #define GPIO_AFRL_AFSEL0 ((uint32_t)0x0000000FU)
5197 #define GPIO_AFRL_AFSEL0_0 ((uint32_t)0x00000001U)
5198 #define GPIO_AFRL_AFSEL0_1 ((uint32_t)0x00000002U)
5199 #define GPIO_AFRL_AFSEL0_2 ((uint32_t)0x00000004U)
5200 #define GPIO_AFRL_AFSEL0_3 ((uint32_t)0x00000008U)
5201 #define GPIO_AFRL_AFSEL1 ((uint32_t)0x000000F0U)
5202 #define GPIO_AFRL_AFSEL1_0 ((uint32_t)0x00000010U)
5203 #define GPIO_AFRL_AFSEL1_1 ((uint32_t)0x00000020U)
5204 #define GPIO_AFRL_AFSEL1_2 ((uint32_t)0x00000040U)
5205 #define GPIO_AFRL_AFSEL1_3 ((uint32_t)0x00000080U)
5206 #define GPIO_AFRL_AFSEL2 ((uint32_t)0x00000F00U)
5207 #define GPIO_AFRL_AFSEL2_0 ((uint32_t)0x00000100U)
5208 #define GPIO_AFRL_AFSEL2_1 ((uint32_t)0x00000200U)
5209 #define GPIO_AFRL_AFSEL2_2 ((uint32_t)0x00000400U)
5210 #define GPIO_AFRL_AFSEL2_3 ((uint32_t)0x00000800U)
5211 #define GPIO_AFRL_AFSEL3 ((uint32_t)0x0000F000U)
5212 #define GPIO_AFRL_AFSEL3_0 ((uint32_t)0x00001000U)
5213 #define GPIO_AFRL_AFSEL3_1 ((uint32_t)0x00002000U)
5214 #define GPIO_AFRL_AFSEL3_2 ((uint32_t)0x00004000U)
5215 #define GPIO_AFRL_AFSEL3_3 ((uint32_t)0x00008000U)
5216 #define GPIO_AFRL_AFSEL4 ((uint32_t)0x000F0000U)
5217 #define GPIO_AFRL_AFSEL4_0 ((uint32_t)0x00010000U)
5218 #define GPIO_AFRL_AFSEL4_1 ((uint32_t)0x00020000U)
5219 #define GPIO_AFRL_AFSEL4_2 ((uint32_t)0x00040000U)
5220 #define GPIO_AFRL_AFSEL4_3 ((uint32_t)0x00080000U)
5221 #define GPIO_AFRL_AFSEL5 ((uint32_t)0x00F00000U)
5222 #define GPIO_AFRL_AFSEL5_0 ((uint32_t)0x00100000U)
5223 #define GPIO_AFRL_AFSEL5_1 ((uint32_t)0x00200000U)
5224 #define GPIO_AFRL_AFSEL5_2 ((uint32_t)0x00400000U)
5225 #define GPIO_AFRL_AFSEL5_3 ((uint32_t)0x00800000U)
5226 #define GPIO_AFRL_AFSEL6 ((uint32_t)0x0F000000U)
5227 #define GPIO_AFRL_AFSEL6_0 ((uint32_t)0x01000000U)
5228 #define GPIO_AFRL_AFSEL6_1 ((uint32_t)0x02000000U)
5229 #define GPIO_AFRL_AFSEL6_2 ((uint32_t)0x04000000U)
5230 #define GPIO_AFRL_AFSEL6_3 ((uint32_t)0x08000000U)
5231 #define GPIO_AFRL_AFSEL7 ((uint32_t)0xF0000000U)
5232 #define GPIO_AFRL_AFSEL7_0 ((uint32_t)0x10000000U)
5233 #define GPIO_AFRL_AFSEL7_1 ((uint32_t)0x20000000U)
5234 #define GPIO_AFRL_AFSEL7_2 ((uint32_t)0x40000000U)
5235 #define GPIO_AFRL_AFSEL7_3 ((uint32_t)0x80000000U)
5236
5237 /* Legacy defines */
5238 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
5239 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
5240 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
5241 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
5242 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
5243 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
5244 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
5245 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
5246
5247 /****************** Bit definition for GPIO_AFRH register *********************/
5248 #define GPIO_AFRH_AFSEL8 ((uint32_t)0x0000000FU)
5249 #define GPIO_AFRH_AFSEL8_0 ((uint32_t)0x00000001U)
5250 #define GPIO_AFRH_AFSEL8_1 ((uint32_t)0x00000002U)
5251 #define GPIO_AFRH_AFSEL8_2 ((uint32_t)0x00000004U)
5252 #define GPIO_AFRH_AFSEL8_3 ((uint32_t)0x00000008U)
5253 #define GPIO_AFRH_AFSEL9 ((uint32_t)0x000000F0U)
5254 #define GPIO_AFRH_AFSEL9_0 ((uint32_t)0x00000010U)
5255 #define GPIO_AFRH_AFSEL9_1 ((uint32_t)0x00000020U)
5256 #define GPIO_AFRH_AFSEL9_2 ((uint32_t)0x00000040U)
5257 #define GPIO_AFRH_AFSEL9_3 ((uint32_t)0x00000080U)
5258 #define GPIO_AFRH_AFSEL10 ((uint32_t)0x00000F00U)
5259 #define GPIO_AFRH_AFSEL10_0 ((uint32_t)0x00000100U)
5260 #define GPIO_AFRH_AFSEL10_1 ((uint32_t)0x00000200U)
5261 #define GPIO_AFRH_AFSEL10_2 ((uint32_t)0x00000400U)
5262 #define GPIO_AFRH_AFSEL10_3 ((uint32_t)0x00000800U)
5263 #define GPIO_AFRH_AFSEL11 ((uint32_t)0x0000F000U)
5264 #define GPIO_AFRH_AFSEL11_0 ((uint32_t)0x00001000U)
5265 #define GPIO_AFRH_AFSEL11_1 ((uint32_t)0x00002000U)
5266 #define GPIO_AFRH_AFSEL11_2 ((uint32_t)0x00004000U)
5267 #define GPIO_AFRH_AFSEL11_3 ((uint32_t)0x00008000U)
5268 #define GPIO_AFRH_AFSEL12 ((uint32_t)0x000F0000U)
5269 #define GPIO_AFRH_AFSEL12_0 ((uint32_t)0x00010000U)
5270 #define GPIO_AFRH_AFSEL12_1 ((uint32_t)0x00020000U)
5271 #define GPIO_AFRH_AFSEL12_2 ((uint32_t)0x00040000U)
5272 #define GPIO_AFRH_AFSEL12_3 ((uint32_t)0x00080000U)
5273 #define GPIO_AFRH_AFSEL13 ((uint32_t)0x00F00000U)
5274 #define GPIO_AFRH_AFSEL13_0 ((uint32_t)0x00100000U)
5275 #define GPIO_AFRH_AFSEL13_1 ((uint32_t)0x00200000U)
5276 #define GPIO_AFRH_AFSEL13_2 ((uint32_t)0x00400000U)
5277 #define GPIO_AFRH_AFSEL13_3 ((uint32_t)0x00800000U)
5278 #define GPIO_AFRH_AFSEL14 ((uint32_t)0x0F000000U)
5279 #define GPIO_AFRH_AFSEL14_0 ((uint32_t)0x01000000U)
5280 #define GPIO_AFRH_AFSEL14_1 ((uint32_t)0x02000000U)
5281 #define GPIO_AFRH_AFSEL14_2 ((uint32_t)0x04000000U)
5282 #define GPIO_AFRH_AFSEL14_3 ((uint32_t)0x08000000U)
5283 #define GPIO_AFRH_AFSEL15 ((uint32_t)0xF0000000U)
5284 #define GPIO_AFRH_AFSEL15_0 ((uint32_t)0x10000000U)
5285 #define GPIO_AFRH_AFSEL15_1 ((uint32_t)0x20000000U)
5286 #define GPIO_AFRH_AFSEL15_2 ((uint32_t)0x40000000U)
5287 #define GPIO_AFRH_AFSEL15_3 ((uint32_t)0x80000000U)
5288
5289 /* Legacy defines */
5290 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
5291 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
5292 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
5293 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
5294 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
5295 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
5296 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
5297 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
5298
5299 /****************** Bits definition for GPIO_BRR register ******************/
5300 #define GPIO_BRR_BR0 ((uint32_t)0x00000001U)
5301 #define GPIO_BRR_BR1 ((uint32_t)0x00000002U)
5302 #define GPIO_BRR_BR2 ((uint32_t)0x00000004U)
5303 #define GPIO_BRR_BR3 ((uint32_t)0x00000008U)
5304 #define GPIO_BRR_BR4 ((uint32_t)0x00000010U)
5305 #define GPIO_BRR_BR5 ((uint32_t)0x00000020U)
5306 #define GPIO_BRR_BR6 ((uint32_t)0x00000040U)
5307 #define GPIO_BRR_BR7 ((uint32_t)0x00000080U)
5308 #define GPIO_BRR_BR8 ((uint32_t)0x00000100U)
5309 #define GPIO_BRR_BR9 ((uint32_t)0x00000200U)
5310 #define GPIO_BRR_BR10 ((uint32_t)0x00000400U)
5311 #define GPIO_BRR_BR11 ((uint32_t)0x00000800U)
5312 #define GPIO_BRR_BR12 ((uint32_t)0x00001000U)
5313 #define GPIO_BRR_BR13 ((uint32_t)0x00002000U)
5314 #define GPIO_BRR_BR14 ((uint32_t)0x00004000U)
5315 #define GPIO_BRR_BR15 ((uint32_t)0x00008000U)
5316
5317 /* Legacy defines */
5318 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
5319 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
5320 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
5321 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
5322 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
5323 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
5324 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
5325 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
5326 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
5327 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
5328 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
5329 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
5330 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
5331 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
5332 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
5333 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
5334
5335
5336 /****************** Bits definition for GPIO_ASCR register *******************/
5337 #define GPIO_ASCR_ASC0 ((uint32_t)0x00000001U)
5338 #define GPIO_ASCR_ASC1 ((uint32_t)0x00000002U)
5339 #define GPIO_ASCR_ASC2 ((uint32_t)0x00000004U)
5340 #define GPIO_ASCR_ASC3 ((uint32_t)0x00000008U)
5341 #define GPIO_ASCR_ASC4 ((uint32_t)0x00000010U)
5342 #define GPIO_ASCR_ASC5 ((uint32_t)0x00000020U)
5343 #define GPIO_ASCR_ASC6 ((uint32_t)0x00000040U)
5344 #define GPIO_ASCR_ASC7 ((uint32_t)0x00000080U)
5345 #define GPIO_ASCR_ASC8 ((uint32_t)0x00000100U)
5346 #define GPIO_ASCR_ASC9 ((uint32_t)0x00000200U)
5347 #define GPIO_ASCR_ASC10 ((uint32_t)0x00000400U)
5348 #define GPIO_ASCR_ASC11 ((uint32_t)0x00000800U)
5349 #define GPIO_ASCR_ASC12 ((uint32_t)0x00001000U)
5350 #define GPIO_ASCR_ASC13 ((uint32_t)0x00002000U)
5351 #define GPIO_ASCR_ASC14 ((uint32_t)0x00004000U)
5352 #define GPIO_ASCR_ASC15 ((uint32_t)0x00008000U)
5353
5354 /* Legacy defines */
5355 #define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
5356 #define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
5357 #define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
5358 #define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
5359 #define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
5360 #define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
5361 #define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
5362 #define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
5363 #define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
5364 #define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
5365 #define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
5366 #define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
5367 #define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
5368 #define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
5369 #define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
5370 #define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
5371
5372 /******************************************************************************/
5373 /* */
5374 /* Inter-integrated Circuit Interface (I2C) */
5375 /* */
5376 /******************************************************************************/
5377 /******************* Bit definition for I2C_CR1 register *******************/
5378 #define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */
5379 #define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */
5380 #define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */
5381 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */
5382 #define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */
5383 #define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */
5384 #define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */
5385 #define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */
5386 #define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */
5387 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */
5388 #define I2C_CR1_SWRST ((uint32_t)0x00002000U) /*!< Software reset */
5389 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */
5390 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */
5391 #define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */
5392 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */
5393 #define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */
5394 #define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */
5395 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */
5396 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */
5397 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */
5398 #define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */
5399
5400 /****************** Bit definition for I2C_CR2 register ********************/
5401 #define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */
5402 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */
5403 #define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */
5404 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */
5405 #define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */
5406 #define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */
5407 #define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */
5408 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */
5409 #define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */
5410 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */
5411 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */
5412
5413 /******************* Bit definition for I2C_OAR1 register ******************/
5414 #define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */
5415 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */
5416 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */
5417
5418 /******************* Bit definition for I2C_OAR2 register ******************/
5419 #define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */
5420 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */
5421 #define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */
5422 #define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
5423 #define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
5424 #define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
5425 #define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
5426 #define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
5427 #define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
5428 #define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */
5429 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */
5430
5431 /******************* Bit definition for I2C_TIMINGR register *******************/
5432 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */
5433 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */
5434 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */
5435 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */
5436 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */
5437
5438 /******************* Bit definition for I2C_TIMEOUTR register *******************/
5439 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */
5440 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */
5441 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */
5442 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B */
5443 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */
5444
5445 /****************** Bit definition for I2C_ISR register *********************/
5446 #define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */
5447 #define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */
5448 #define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */
5449 #define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode) */
5450 #define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */
5451 #define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */
5452 #define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */
5453 #define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */
5454 #define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */
5455 #define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */
5456 #define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */
5457 #define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */
5458 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */
5459 #define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */
5460 #define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */
5461 #define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */
5462 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */
5463
5464 /****************** Bit definition for I2C_ICR register *********************/
5465 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */
5466 #define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */
5467 #define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */
5468 #define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */
5469 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */
5470 #define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */
5471 #define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */
5472 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */
5473 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */
5474
5475 /****************** Bit definition for I2C_PECR register *********************/
5476 #define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */
5477
5478 /****************** Bit definition for I2C_RXDR register *********************/
5479 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */
5480
5481 /****************** Bit definition for I2C_TXDR register *********************/
5482 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */
5483
5484 /******************************************************************************/
5485 /* */
5486 /* Independent WATCHDOG */
5487 /* */
5488 /******************************************************************************/
5489 /******************* Bit definition for IWDG_KR register ********************/
5490 #define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!<Key value (write only, read 0000h) */
5491
5492 /******************* Bit definition for IWDG_PR register ********************/
5493 #define IWDG_PR_PR ((uint32_t)0x00000007U) /*!<PR[2:0] (Prescaler divider) */
5494 #define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
5495 #define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
5496 #define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
5497
5498 /******************* Bit definition for IWDG_RLR register *******************/
5499 #define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!<Watchdog counter reload value */
5500
5501 /******************* Bit definition for IWDG_SR register ********************/
5502 #define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
5503 #define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
5504 #define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */
5505
5506 /******************* Bit definition for IWDG_KR register ********************/
5507 #define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */
5508
5509 /******************************************************************************/
5510 /* */
5511 /* Firewall */
5512 /* */
5513 /******************************************************************************/
5514
5515 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */
5516 #define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */
5517 #define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */
5518 #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */
5519 #define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */
5520 #define FW_VDSSA_ADD ((uint32_t)0x0001FFC0U) /*!< Volatile Data Segment Start Address */
5521 #define FW_VDSL_LENG ((uint32_t)0x0001FFC0U) /*!< Volatile Data Segment Length */
5522 #define FW_LSSA_ADD ((uint32_t)0x0007FF80U) /*!< Library Segment Start Address*/
5523 #define FW_LSL_LENG ((uint32_t)0x0007FF80U) /*!< Library Segment Length*/
5524
5525 /**************************Bit definition for CR register *********************/
5526 #define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/
5527 #define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/
5528 #define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/
5529
5530 /******************************************************************************/
5531 /* */
5532 /* Power Control */
5533 /* */
5534 /******************************************************************************/
5535
5536 /******************** Bit definition for PWR_CR1 register ********************/
5537
5538 #define PWR_CR1_LPR ((uint32_t)0x00004000U) /*!< Regulator low-power mode */
5539 #define PWR_CR1_VOS ((uint32_t)0x00000600U) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
5540 #define PWR_CR1_VOS_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
5541 #define PWR_CR1_VOS_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
5542 #define PWR_CR1_DBP ((uint32_t)0x00000100U) /*!< Disable Back-up domain Protection */
5543 #define PWR_CR1_LPMS ((uint32_t)0x00000007U) /*!< Low-power mode selection field */
5544 #define PWR_CR1_LPMS_STOP0 ((uint32_t)0x00000000U) /*!< Stop 0 mode */
5545 #define PWR_CR1_LPMS_STOP1 ((uint32_t)0x00000001U) /*!< Stop 1 mode */
5546 #define PWR_CR1_LPMS_STOP2 ((uint32_t)0x00000002U) /*!< Stop 2 mode */
5547 #define PWR_CR1_LPMS_STANDBY ((uint32_t)0x00000003U) /*!< Stand-by mode */
5548 #define PWR_CR1_LPMS_SHUTDOWN ((uint32_t)0x00000004U) /*!< Shut-down mode */
5549
5550
5551 /******************** Bit definition for PWR_CR2 register ********************/
5552 #define PWR_CR2_USV ((uint32_t)0x00000400U) /*!< VDD USB Supply Valid */
5553 #define PWR_CR2_IOSV ((uint32_t)0x00000200U) /*!< VDD IO2 independent I/Os Supply Valid */
5554 /*!< PVME Peripheral Voltage Monitor Enable */
5555 #define PWR_CR2_PVME ((uint32_t)0x000000F0U) /*!< PVM bits field */
5556 #define PWR_CR2_PVME4 ((uint32_t)0x00000080U) /*!< PVM 4 Enable */
5557 #define PWR_CR2_PVME3 ((uint32_t)0x00000040U) /*!< PVM 3 Enable */
5558 #define PWR_CR2_PVME2 ((uint32_t)0x00000020U) /*!< PVM 2 Enable */
5559 #define PWR_CR2_PVME1 ((uint32_t)0x00000010U) /*!< PVM 1 Enable */
5560 /*!< PVD level configuration */
5561 #define PWR_CR2_PLS ((uint32_t)0x0000000EU) /*!< PVD level selection */
5562 #define PWR_CR2_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
5563 #define PWR_CR2_PLS_LEV1 ((uint32_t)0x00000002U) /*!< PVD level 1 */
5564 #define PWR_CR2_PLS_LEV2 ((uint32_t)0x00000004U) /*!< PVD level 2 */
5565 #define PWR_CR2_PLS_LEV3 ((uint32_t)0x00000006U) /*!< PVD level 3 */
5566 #define PWR_CR2_PLS_LEV4 ((uint32_t)0x00000008U) /*!< PVD level 4 */
5567 #define PWR_CR2_PLS_LEV5 ((uint32_t)0x0000000AU) /*!< PVD level 5 */
5568 #define PWR_CR2_PLS_LEV6 ((uint32_t)0x0000000CU) /*!< PVD level 6 */
5569 #define PWR_CR2_PLS_LEV7 ((uint32_t)0x0000000EU) /*!< PVD level 7 */
5570 #define PWR_CR2_PVDE ((uint32_t)0x00000001U) /*!< Power Voltage Detector Enable */
5571
5572 /******************** Bit definition for PWR_CR3 register ********************/
5573 #define PWR_CR3_EIWF ((uint32_t)0x00008000U) /*!< Enable Internal Wake-up line */
5574 #define PWR_CR3_APC ((uint32_t)0x00000400U) /*!< Apply pull-up and pull-down configuration */
5575 #define PWR_CR3_RRS ((uint32_t)0x00000100U) /*!< SRAM2 Retention in Stand-by mode */
5576 #define PWR_CR3_EWUP5 ((uint32_t)0x00000010U) /*!< Enable Wake-Up Pin 5 */
5577 #define PWR_CR3_EWUP4 ((uint32_t)0x00000008U) /*!< Enable Wake-Up Pin 4 */
5578 #define PWR_CR3_EWUP3 ((uint32_t)0x00000004U) /*!< Enable Wake-Up Pin 3 */
5579 #define PWR_CR3_EWUP2 ((uint32_t)0x00000002U) /*!< Enable Wake-Up Pin 2 */
5580 #define PWR_CR3_EWUP1 ((uint32_t)0x00000001U) /*!< Enable Wake-Up Pin 1 */
5581 #define PWR_CR3_EWUP ((uint32_t)0x0000001FU) /*!< Enable Wake-Up Pins */
5582
5583 /******************** Bit definition for PWR_CR4 register ********************/
5584 #define PWR_CR4_VBRS ((uint32_t)0x00000200U) /*!< VBAT Battery charging Resistor Selection */
5585 #define PWR_CR4_VBE ((uint32_t)0x00000100U) /*!< VBAT Battery charging Enable */
5586 #define PWR_CR4_WP5 ((uint32_t)0x00000010U) /*!< Wake-Up Pin 5 polarity */
5587 #define PWR_CR4_WP4 ((uint32_t)0x00000008U) /*!< Wake-Up Pin 4 polarity */
5588 #define PWR_CR4_WP3 ((uint32_t)0x00000004U) /*!< Wake-Up Pin 3 polarity */
5589 #define PWR_CR4_WP2 ((uint32_t)0x00000002U) /*!< Wake-Up Pin 2 polarity */
5590 #define PWR_CR4_WP1 ((uint32_t)0x00000001U) /*!< Wake-Up Pin 1 polarity */
5591
5592 /******************** Bit definition for PWR_SR1 register ********************/
5593 #define PWR_SR1_WUFI ((uint32_t)0x00008000U) /*!< Wake-Up Flag Internal */
5594 #define PWR_SR1_SBF ((uint32_t)0x00000100U) /*!< Stand-By Flag */
5595 #define PWR_SR1_WUF ((uint32_t)0x0000001FU) /*!< Wake-up Flags */
5596 #define PWR_SR1_WUF5 ((uint32_t)0x00000010U) /*!< Wake-up Flag 5 */
5597 #define PWR_SR1_WUF4 ((uint32_t)0x00000008U) /*!< Wake-up Flag 4 */
5598 #define PWR_SR1_WUF3 ((uint32_t)0x00000004U) /*!< Wake-up Flag 3 */
5599 #define PWR_SR1_WUF2 ((uint32_t)0x00000002U) /*!< Wake-up Flag 2 */
5600 #define PWR_SR1_WUF1 ((uint32_t)0x00000001U) /*!< Wake-up Flag 1 */
5601
5602 /******************** Bit definition for PWR_SR2 register ********************/
5603 #define PWR_SR2_PVMO4 ((uint32_t)0x00008000U) /*!< Peripheral Voltage Monitoring Output 4 */
5604 #define PWR_SR2_PVMO3 ((uint32_t)0x00004000U) /*!< Peripheral Voltage Monitoring Output 3 */
5605 #define PWR_SR2_PVMO2 ((uint32_t)0x00002000U) /*!< Peripheral Voltage Monitoring Output 2 */
5606 #define PWR_SR2_PVMO1 ((uint32_t)0x00001000U) /*!< Peripheral Voltage Monitoring Output 1 */
5607 #define PWR_SR2_PVDO ((uint32_t)0x00000800U) /*!< Power Voltage Detector Output */
5608 #define PWR_SR2_VOSF ((uint32_t)0x00000400U) /*!< Voltage Scaling Flag */
5609 #define PWR_SR2_REGLPF ((uint32_t)0x00000200U) /*!< Low-power Regulator Flag */
5610 #define PWR_SR2_REGLPS ((uint32_t)0x00000100U) /*!< Low-power Regulator Started */
5611
5612 /******************** Bit definition for PWR_SCR register ********************/
5613 #define PWR_SCR_CSBF ((uint32_t)0x00000100U) /*!< Clear Stand-By Flag */
5614 #define PWR_SCR_CWUF ((uint32_t)0x0000001FU) /*!< Clear Wake-up Flags */
5615 #define PWR_SCR_CWUF5 ((uint32_t)0x00000010U) /*!< Clear Wake-up Flag 5 */
5616 #define PWR_SCR_CWUF4 ((uint32_t)0x00000008U) /*!< Clear Wake-up Flag 4 */
5617 #define PWR_SCR_CWUF3 ((uint32_t)0x00000004U) /*!< Clear Wake-up Flag 3 */
5618 #define PWR_SCR_CWUF2 ((uint32_t)0x00000002U) /*!< Clear Wake-up Flag 2 */
5619 #define PWR_SCR_CWUF1 ((uint32_t)0x00000001U) /*!< Clear Wake-up Flag 1 */
5620
5621 /******************** Bit definition for PWR_PUCRA register ********************/
5622 #define PWR_PUCRA_PA15 ((uint32_t)0x00008000U) /*!< Port PA15 Pull-Up set */
5623 #define PWR_PUCRA_PA13 ((uint32_t)0x00002000U) /*!< Port PA13 Pull-Up set */
5624 #define PWR_PUCRA_PA12 ((uint32_t)0x00001000U) /*!< Port PA12 Pull-Up set */
5625 #define PWR_PUCRA_PA11 ((uint32_t)0x00000800U) /*!< Port PA11 Pull-Up set */
5626 #define PWR_PUCRA_PA10 ((uint32_t)0x00000400U) /*!< Port PA10 Pull-Up set */
5627 #define PWR_PUCRA_PA9 ((uint32_t)0x00000200U) /*!< Port PA9 Pull-Up set */
5628 #define PWR_PUCRA_PA8 ((uint32_t)0x00000100U) /*!< Port PA8 Pull-Up set */
5629 #define PWR_PUCRA_PA7 ((uint32_t)0x00000080U) /*!< Port PA7 Pull-Up set */
5630 #define PWR_PUCRA_PA6 ((uint32_t)0x00000040U) /*!< Port PA6 Pull-Up set */
5631 #define PWR_PUCRA_PA5 ((uint32_t)0x00000020U) /*!< Port PA5 Pull-Up set */
5632 #define PWR_PUCRA_PA4 ((uint32_t)0x00000010U) /*!< Port PA4 Pull-Up set */
5633 #define PWR_PUCRA_PA3 ((uint32_t)0x00000008U) /*!< Port PA3 Pull-Up set */
5634 #define PWR_PUCRA_PA2 ((uint32_t)0x00000004U) /*!< Port PA2 Pull-Up set */
5635 #define PWR_PUCRA_PA1 ((uint32_t)0x00000002U) /*!< Port PA1 Pull-Up set */
5636 #define PWR_PUCRA_PA0 ((uint32_t)0x00000001U) /*!< Port PA0 Pull-Up set */
5637
5638 /******************** Bit definition for PWR_PDCRA register ********************/
5639 #define PWR_PDCRA_PA14 ((uint32_t)0x00004000U) /*!< Port PA14 Pull-Down set */
5640 #define PWR_PDCRA_PA12 ((uint32_t)0x00001000U) /*!< Port PA12 Pull-Down set */
5641 #define PWR_PDCRA_PA11 ((uint32_t)0x00000800U) /*!< Port PA11 Pull-Down set */
5642 #define PWR_PDCRA_PA10 ((uint32_t)0x00000400U) /*!< Port PA10 Pull-Down set */
5643 #define PWR_PDCRA_PA9 ((uint32_t)0x00000200U) /*!< Port PA9 Pull-Down set */
5644 #define PWR_PDCRA_PA8 ((uint32_t)0x00000100U) /*!< Port PA8 Pull-Down set */
5645 #define PWR_PDCRA_PA7 ((uint32_t)0x00000080U) /*!< Port PA7 Pull-Down set */
5646 #define PWR_PDCRA_PA6 ((uint32_t)0x00000040U) /*!< Port PA6 Pull-Down set */
5647 #define PWR_PDCRA_PA5 ((uint32_t)0x00000020U) /*!< Port PA5 Pull-Down set */
5648 #define PWR_PDCRA_PA4 ((uint32_t)0x00000010U) /*!< Port PA4 Pull-Down set */
5649 #define PWR_PDCRA_PA3 ((uint32_t)0x00000008U) /*!< Port PA3 Pull-Down set */
5650 #define PWR_PDCRA_PA2 ((uint32_t)0x00000004U) /*!< Port PA2 Pull-Down set */
5651 #define PWR_PDCRA_PA1 ((uint32_t)0x00000002U) /*!< Port PA1 Pull-Down set */
5652 #define PWR_PDCRA_PA0 ((uint32_t)0x00000001U) /*!< Port PA0 Pull-Down set */
5653
5654 /******************** Bit definition for PWR_PUCRB register ********************/
5655 #define PWR_PUCRB_PB15 ((uint32_t)0x00008000U) /*!< Port PB15 Pull-Up set */
5656 #define PWR_PUCRB_PB14 ((uint32_t)0x00004000U) /*!< Port PB14 Pull-Up set */
5657 #define PWR_PUCRB_PB13 ((uint32_t)0x00002000U) /*!< Port PB13 Pull-Up set */
5658 #define PWR_PUCRB_PB12 ((uint32_t)0x00001000U) /*!< Port PB12 Pull-Up set */
5659 #define PWR_PUCRB_PB11 ((uint32_t)0x00000800U) /*!< Port PB11 Pull-Up set */
5660 #define PWR_PUCRB_PB10 ((uint32_t)0x00000400U) /*!< Port PB10 Pull-Up set */
5661 #define PWR_PUCRB_PB9 ((uint32_t)0x00000200U) /*!< Port PB9 Pull-Up set */
5662 #define PWR_PUCRB_PB8 ((uint32_t)0x00000100U) /*!< Port PB8 Pull-Up set */
5663 #define PWR_PUCRB_PB7 ((uint32_t)0x00000080U) /*!< Port PB7 Pull-Up set */
5664 #define PWR_PUCRB_PB6 ((uint32_t)0x00000040U) /*!< Port PB6 Pull-Up set */
5665 #define PWR_PUCRB_PB5 ((uint32_t)0x00000020U) /*!< Port PB5 Pull-Up set */
5666 #define PWR_PUCRB_PB4 ((uint32_t)0x00000010U) /*!< Port PB4 Pull-Up set */
5667 #define PWR_PUCRB_PB3 ((uint32_t)0x00000008U) /*!< Port PB3 Pull-Up set */
5668 #define PWR_PUCRB_PB2 ((uint32_t)0x00000004U) /*!< Port PB2 Pull-Up set */
5669 #define PWR_PUCRB_PB1 ((uint32_t)0x00000002U) /*!< Port PB1 Pull-Up set */
5670 #define PWR_PUCRB_PB0 ((uint32_t)0x00000001U) /*!< Port PB0 Pull-Up set */
5671
5672 /******************** Bit definition for PWR_PDCRB register ********************/
5673 #define PWR_PDCRB_PB15 ((uint32_t)0x00008000U) /*!< Port PB15 Pull-Down set */
5674 #define PWR_PDCRB_PB14 ((uint32_t)0x00004000U) /*!< Port PB14 Pull-Down set */
5675 #define PWR_PDCRB_PB13 ((uint32_t)0x00002000U) /*!< Port PB13 Pull-Down set */
5676 #define PWR_PDCRB_PB12 ((uint32_t)0x00001000U) /*!< Port PB12 Pull-Down set */
5677 #define PWR_PDCRB_PB11 ((uint32_t)0x00000800U) /*!< Port PB11 Pull-Down set */
5678 #define PWR_PDCRB_PB10 ((uint32_t)0x00000400U) /*!< Port PB10 Pull-Down set */
5679 #define PWR_PDCRB_PB9 ((uint32_t)0x00000200U) /*!< Port PB9 Pull-Down set */
5680 #define PWR_PDCRB_PB8 ((uint32_t)0x00000100U) /*!< Port PB8 Pull-Down set */
5681 #define PWR_PDCRB_PB7 ((uint32_t)0x00000080U) /*!< Port PB7 Pull-Down set */
5682 #define PWR_PDCRB_PB6 ((uint32_t)0x00000040U) /*!< Port PB6 Pull-Down set */
5683 #define PWR_PDCRB_PB5 ((uint32_t)0x00000020U) /*!< Port PB5 Pull-Down set */
5684 #define PWR_PDCRB_PB3 ((uint32_t)0x00000008U) /*!< Port PB3 Pull-Down set */
5685 #define PWR_PDCRB_PB2 ((uint32_t)0x00000004U) /*!< Port PB2 Pull-Down set */
5686 #define PWR_PDCRB_PB1 ((uint32_t)0x00000002U) /*!< Port PB1 Pull-Down set */
5687 #define PWR_PDCRB_PB0 ((uint32_t)0x00000001U) /*!< Port PB0 Pull-Down set */
5688
5689 /******************** Bit definition for PWR_PUCRC register ********************/
5690 #define PWR_PUCRC_PC15 ((uint32_t)0x00008000U) /*!< Port PC15 Pull-Up set */
5691 #define PWR_PUCRC_PC14 ((uint32_t)0x00004000U) /*!< Port PC14 Pull-Up set */
5692 #define PWR_PUCRC_PC13 ((uint32_t)0x00002000U) /*!< Port PC13 Pull-Up set */
5693 #define PWR_PUCRC_PC12 ((uint32_t)0x00001000U) /*!< Port PC12 Pull-Up set */
5694 #define PWR_PUCRC_PC11 ((uint32_t)0x00000800U) /*!< Port PC11 Pull-Up set */
5695 #define PWR_PUCRC_PC10 ((uint32_t)0x00000400U) /*!< Port PC10 Pull-Up set */
5696 #define PWR_PUCRC_PC9 ((uint32_t)0x00000200U) /*!< Port PC9 Pull-Up set */
5697 #define PWR_PUCRC_PC8 ((uint32_t)0x00000100U) /*!< Port PC8 Pull-Up set */
5698 #define PWR_PUCRC_PC7 ((uint32_t)0x00000080U) /*!< Port PC7 Pull-Up set */
5699 #define PWR_PUCRC_PC6 ((uint32_t)0x00000040U) /*!< Port PC6 Pull-Up set */
5700 #define PWR_PUCRC_PC5 ((uint32_t)0x00000020U) /*!< Port PC5 Pull-Up set */
5701 #define PWR_PUCRC_PC4 ((uint32_t)0x00000010U) /*!< Port PC4 Pull-Up set */
5702 #define PWR_PUCRC_PC3 ((uint32_t)0x00000008U) /*!< Port PC3 Pull-Up set */
5703 #define PWR_PUCRC_PC2 ((uint32_t)0x00000004U) /*!< Port PC2 Pull-Up set */
5704 #define PWR_PUCRC_PC1 ((uint32_t)0x00000002U) /*!< Port PC1 Pull-Up set */
5705 #define PWR_PUCRC_PC0 ((uint32_t)0x00000001U) /*!< Port PC0 Pull-Up set */
5706
5707 /******************** Bit definition for PWR_PDCRC register ********************/
5708 #define PWR_PDCRC_PC15 ((uint32_t)0x00008000U) /*!< Port PC15 Pull-Down set */
5709 #define PWR_PDCRC_PC14 ((uint32_t)0x00004000U) /*!< Port PC14 Pull-Down set */
5710 #define PWR_PDCRC_PC13 ((uint32_t)0x00002000U) /*!< Port PC13 Pull-Down set */
5711 #define PWR_PDCRC_PC12 ((uint32_t)0x00001000U) /*!< Port PC12 Pull-Down set */
5712 #define PWR_PDCRC_PC11 ((uint32_t)0x00000800U) /*!< Port PC11 Pull-Down set */
5713 #define PWR_PDCRC_PC10 ((uint32_t)0x00000400U) /*!< Port PC10 Pull-Down set */
5714 #define PWR_PDCRC_PC9 ((uint32_t)0x00000200U) /*!< Port PC9 Pull-Down set */
5715 #define PWR_PDCRC_PC8 ((uint32_t)0x00000100U) /*!< Port PC8 Pull-Down set */
5716 #define PWR_PDCRC_PC7 ((uint32_t)0x00000080U) /*!< Port PC7 Pull-Down set */
5717 #define PWR_PDCRC_PC6 ((uint32_t)0x00000040U) /*!< Port PC6 Pull-Down set */
5718 #define PWR_PDCRC_PC5 ((uint32_t)0x00000020U) /*!< Port PC5 Pull-Down set */
5719 #define PWR_PDCRC_PC4 ((uint32_t)0x00000010U) /*!< Port PC4 Pull-Down set */
5720 #define PWR_PDCRC_PC3 ((uint32_t)0x00000008U) /*!< Port PC3 Pull-Down set */
5721 #define PWR_PDCRC_PC2 ((uint32_t)0x00000004U) /*!< Port PC2 Pull-Down set */
5722 #define PWR_PDCRC_PC1 ((uint32_t)0x00000002U) /*!< Port PC1 Pull-Down set */
5723 #define PWR_PDCRC_PC0 ((uint32_t)0x00000001U) /*!< Port PC0 Pull-Down set */
5724
5725 /******************** Bit definition for PWR_PUCRD register ********************/
5726 #define PWR_PUCRD_PD15 ((uint32_t)0x00008000U) /*!< Port PD15 Pull-Up set */
5727 #define PWR_PUCRD_PD14 ((uint32_t)0x00004000U) /*!< Port PD14 Pull-Up set */
5728 #define PWR_PUCRD_PD13 ((uint32_t)0x00002000U) /*!< Port PD13 Pull-Up set */
5729 #define PWR_PUCRD_PD12 ((uint32_t)0x00001000U) /*!< Port PD12 Pull-Up set */
5730 #define PWR_PUCRD_PD11 ((uint32_t)0x00000800U) /*!< Port PD11 Pull-Up set */
5731 #define PWR_PUCRD_PD10 ((uint32_t)0x00000400U) /*!< Port PD10 Pull-Up set */
5732 #define PWR_PUCRD_PD9 ((uint32_t)0x00000200U) /*!< Port PD9 Pull-Up set */
5733 #define PWR_PUCRD_PD8 ((uint32_t)0x00000100U) /*!< Port PD8 Pull-Up set */
5734 #define PWR_PUCRD_PD7 ((uint32_t)0x00000080U) /*!< Port PD7 Pull-Up set */
5735 #define PWR_PUCRD_PD6 ((uint32_t)0x00000040U) /*!< Port PD6 Pull-Up set */
5736 #define PWR_PUCRD_PD5 ((uint32_t)0x00000020U) /*!< Port PD5 Pull-Up set */
5737 #define PWR_PUCRD_PD4 ((uint32_t)0x00000010U) /*!< Port PD4 Pull-Up set */
5738 #define PWR_PUCRD_PD3 ((uint32_t)0x00000008U) /*!< Port PD3 Pull-Up set */
5739 #define PWR_PUCRD_PD2 ((uint32_t)0x00000004U) /*!< Port PD2 Pull-Up set */
5740 #define PWR_PUCRD_PD1 ((uint32_t)0x00000002U) /*!< Port PD1 Pull-Up set */
5741 #define PWR_PUCRD_PD0 ((uint32_t)0x00000001U) /*!< Port PD0 Pull-Up set */
5742
5743 /******************** Bit definition for PWR_PDCRD register ********************/
5744 #define PWR_PDCRD_PD15 ((uint32_t)0x00008000U) /*!< Port PD15 Pull-Down set */
5745 #define PWR_PDCRD_PD14 ((uint32_t)0x00004000U) /*!< Port PD14 Pull-Down set */
5746 #define PWR_PDCRD_PD13 ((uint32_t)0x00002000U) /*!< Port PD13 Pull-Down set */
5747 #define PWR_PDCRD_PD12 ((uint32_t)0x00001000U) /*!< Port PD12 Pull-Down set */
5748 #define PWR_PDCRD_PD11 ((uint32_t)0x00000800U) /*!< Port PD11 Pull-Down set */
5749 #define PWR_PDCRD_PD10 ((uint32_t)0x00000400U) /*!< Port PD10 Pull-Down set */
5750 #define PWR_PDCRD_PD9 ((uint32_t)0x00000200U) /*!< Port PD9 Pull-Down set */
5751 #define PWR_PDCRD_PD8 ((uint32_t)0x00000100U) /*!< Port PD8 Pull-Down set */
5752 #define PWR_PDCRD_PD7 ((uint32_t)0x00000080U) /*!< Port PD7 Pull-Down set */
5753 #define PWR_PDCRD_PD6 ((uint32_t)0x00000040U) /*!< Port PD6 Pull-Down set */
5754 #define PWR_PDCRD_PD5 ((uint32_t)0x00000020U) /*!< Port PD5 Pull-Down set */
5755 #define PWR_PDCRD_PD4 ((uint32_t)0x00000010U) /*!< Port PD4 Pull-Down set */
5756 #define PWR_PDCRD_PD3 ((uint32_t)0x00000008U) /*!< Port PD3 Pull-Down set */
5757 #define PWR_PDCRD_PD2 ((uint32_t)0x00000004U) /*!< Port PD2 Pull-Down set */
5758 #define PWR_PDCRD_PD1 ((uint32_t)0x00000002U) /*!< Port PD1 Pull-Down set */
5759 #define PWR_PDCRD_PD0 ((uint32_t)0x00000001U) /*!< Port PD0 Pull-Down set */
5760
5761 /******************** Bit definition for PWR_PUCRE register ********************/
5762 #define PWR_PUCRE_PE15 ((uint32_t)0x00008000U) /*!< Port PE15 Pull-Up set */
5763 #define PWR_PUCRE_PE14 ((uint32_t)0x00004000U) /*!< Port PE14 Pull-Up set */
5764 #define PWR_PUCRE_PE13 ((uint32_t)0x00002000U) /*!< Port PE13 Pull-Up set */
5765 #define PWR_PUCRE_PE12 ((uint32_t)0x00001000U) /*!< Port PE12 Pull-Up set */
5766 #define PWR_PUCRE_PE11 ((uint32_t)0x00000800U) /*!< Port PE11 Pull-Up set */
5767 #define PWR_PUCRE_PE10 ((uint32_t)0x00000400U) /*!< Port PE10 Pull-Up set */
5768 #define PWR_PUCRE_PE9 ((uint32_t)0x00000200U) /*!< Port PE9 Pull-Up set */
5769 #define PWR_PUCRE_PE8 ((uint32_t)0x00000100U) /*!< Port PE8 Pull-Up set */
5770 #define PWR_PUCRE_PE7 ((uint32_t)0x00000080U) /*!< Port PE7 Pull-Up set */
5771 #define PWR_PUCRE_PE6 ((uint32_t)0x00000040U) /*!< Port PE6 Pull-Up set */
5772 #define PWR_PUCRE_PE5 ((uint32_t)0x00000020U) /*!< Port PE5 Pull-Up set */
5773 #define PWR_PUCRE_PE4 ((uint32_t)0x00000010U) /*!< Port PE4 Pull-Up set */
5774 #define PWR_PUCRE_PE3 ((uint32_t)0x00000008U) /*!< Port PE3 Pull-Up set */
5775 #define PWR_PUCRE_PE2 ((uint32_t)0x00000004U) /*!< Port PE2 Pull-Up set */
5776 #define PWR_PUCRE_PE1 ((uint32_t)0x00000002U) /*!< Port PE1 Pull-Up set */
5777 #define PWR_PUCRE_PE0 ((uint32_t)0x00000001U) /*!< Port PE0 Pull-Up set */
5778
5779 /******************** Bit definition for PWR_PDCRE register ********************/
5780 #define PWR_PDCRE_PE15 ((uint32_t)0x00008000U) /*!< Port PE15 Pull-Down set */
5781 #define PWR_PDCRE_PE14 ((uint32_t)0x00004000U) /*!< Port PE14 Pull-Down set */
5782 #define PWR_PDCRE_PE13 ((uint32_t)0x00002000U) /*!< Port PE13 Pull-Down set */
5783 #define PWR_PDCRE_PE12 ((uint32_t)0x00001000U) /*!< Port PE12 Pull-Down set */
5784 #define PWR_PDCRE_PE11 ((uint32_t)0x00000800U) /*!< Port PE11 Pull-Down set */
5785 #define PWR_PDCRE_PE10 ((uint32_t)0x00000400U) /*!< Port PE10 Pull-Down set */
5786 #define PWR_PDCRE_PE9 ((uint32_t)0x00000200U) /*!< Port PE9 Pull-Down set */
5787 #define PWR_PDCRE_PE8 ((uint32_t)0x00000100U) /*!< Port PE8 Pull-Down set */
5788 #define PWR_PDCRE_PE7 ((uint32_t)0x00000080U) /*!< Port PE7 Pull-Down set */
5789 #define PWR_PDCRE_PE6 ((uint32_t)0x00000040U) /*!< Port PE6 Pull-Down set */
5790 #define PWR_PDCRE_PE5 ((uint32_t)0x00000020U) /*!< Port PE5 Pull-Down set */
5791 #define PWR_PDCRE_PE4 ((uint32_t)0x00000010U) /*!< Port PE4 Pull-Down set */
5792 #define PWR_PDCRE_PE3 ((uint32_t)0x00000008U) /*!< Port PE3 Pull-Down set */
5793 #define PWR_PDCRE_PE2 ((uint32_t)0x00000004U) /*!< Port PE2 Pull-Down set */
5794 #define PWR_PDCRE_PE1 ((uint32_t)0x00000002U) /*!< Port PE1 Pull-Down set */
5795 #define PWR_PDCRE_PE0 ((uint32_t)0x00000001U) /*!< Port PE0 Pull-Down set */
5796
5797 /******************** Bit definition for PWR_PUCRF register ********************/
5798 #define PWR_PUCRF_PF15 ((uint32_t)0x00008000U) /*!< Port PF15 Pull-Up set */
5799 #define PWR_PUCRF_PF14 ((uint32_t)0x00004000U) /*!< Port PF14 Pull-Up set */
5800 #define PWR_PUCRF_PF13 ((uint32_t)0x00002000U) /*!< Port PF13 Pull-Up set */
5801 #define PWR_PUCRF_PF12 ((uint32_t)0x00001000U) /*!< Port PF12 Pull-Up set */
5802 #define PWR_PUCRF_PF11 ((uint32_t)0x00000800U) /*!< Port PF11 Pull-Up set */
5803 #define PWR_PUCRF_PF10 ((uint32_t)0x00000400U) /*!< Port PF10 Pull-Up set */
5804 #define PWR_PUCRF_PF9 ((uint32_t)0x00000200U) /*!< Port PF9 Pull-Up set */
5805 #define PWR_PUCRF_PF8 ((uint32_t)0x00000100U) /*!< Port PF8 Pull-Up set */
5806 #define PWR_PUCRF_PF7 ((uint32_t)0x00000080U) /*!< Port PF7 Pull-Up set */
5807 #define PWR_PUCRF_PF6 ((uint32_t)0x00000040U) /*!< Port PF6 Pull-Up set */
5808 #define PWR_PUCRF_PF5 ((uint32_t)0x00000020U) /*!< Port PF5 Pull-Up set */
5809 #define PWR_PUCRF_PF4 ((uint32_t)0x00000010U) /*!< Port PF4 Pull-Up set */
5810 #define PWR_PUCRF_PF3 ((uint32_t)0x00000008U) /*!< Port PF3 Pull-Up set */
5811 #define PWR_PUCRF_PF2 ((uint32_t)0x00000004U) /*!< Port PF2 Pull-Up set */
5812 #define PWR_PUCRF_PF1 ((uint32_t)0x00000002U) /*!< Port PF1 Pull-Up set */
5813 #define PWR_PUCRF_PF0 ((uint32_t)0x00000001U) /*!< Port PF0 Pull-Up set */
5814
5815 /******************** Bit definition for PWR_PDCRF register ********************/
5816 #define PWR_PDCRF_PF15 ((uint32_t)0x00008000U) /*!< Port PF15 Pull-Down set */
5817 #define PWR_PDCRF_PF14 ((uint32_t)0x00004000U) /*!< Port PF14 Pull-Down set */
5818 #define PWR_PDCRF_PF13 ((uint32_t)0x00002000U) /*!< Port PF13 Pull-Down set */
5819 #define PWR_PDCRF_PF12 ((uint32_t)0x00001000U) /*!< Port PF12 Pull-Down set */
5820 #define PWR_PDCRF_PF11 ((uint32_t)0x00000800U) /*!< Port PF11 Pull-Down set */
5821 #define PWR_PDCRF_PF10 ((uint32_t)0x00000400U) /*!< Port PF10 Pull-Down set */
5822 #define PWR_PDCRF_PF9 ((uint32_t)0x00000200U) /*!< Port PF9 Pull-Down set */
5823 #define PWR_PDCRF_PF8 ((uint32_t)0x00000100U) /*!< Port PF8 Pull-Down set */
5824 #define PWR_PDCRF_PF7 ((uint32_t)0x00000080U) /*!< Port PF7 Pull-Down set */
5825 #define PWR_PDCRF_PF6 ((uint32_t)0x00000040U) /*!< Port PF6 Pull-Down set */
5826 #define PWR_PDCRF_PF5 ((uint32_t)0x00000020U) /*!< Port PF5 Pull-Down set */
5827 #define PWR_PDCRF_PF4 ((uint32_t)0x00000010U) /*!< Port PF4 Pull-Down set */
5828 #define PWR_PDCRF_PF3 ((uint32_t)0x00000008U) /*!< Port PF3 Pull-Down set */
5829 #define PWR_PDCRF_PF2 ((uint32_t)0x00000004U) /*!< Port PF2 Pull-Down set */
5830 #define PWR_PDCRF_PF1 ((uint32_t)0x00000002U) /*!< Port PF1 Pull-Down set */
5831 #define PWR_PDCRF_PF0 ((uint32_t)0x00000001U) /*!< Port PF0 Pull-Down set */
5832
5833 /******************** Bit definition for PWR_PUCRG register ********************/
5834 #define PWR_PUCRG_PG15 ((uint32_t)0x00008000U) /*!< Port PG15 Pull-Up set */
5835 #define PWR_PUCRG_PG14 ((uint32_t)0x00004000U) /*!< Port PG14 Pull-Up set */
5836 #define PWR_PUCRG_PG13 ((uint32_t)0x00002000U) /*!< Port PG13 Pull-Up set */
5837 #define PWR_PUCRG_PG12 ((uint32_t)0x00001000U) /*!< Port PG12 Pull-Up set */
5838 #define PWR_PUCRG_PG11 ((uint32_t)0x00000800U) /*!< Port PG11 Pull-Up set */
5839 #define PWR_PUCRG_PG10 ((uint32_t)0x00000400U) /*!< Port PG10 Pull-Up set */
5840 #define PWR_PUCRG_PG9 ((uint32_t)0x00000200U) /*!< Port PG9 Pull-Up set */
5841 #define PWR_PUCRG_PG8 ((uint32_t)0x00000100U) /*!< Port PG8 Pull-Up set */
5842 #define PWR_PUCRG_PG7 ((uint32_t)0x00000080U) /*!< Port PG7 Pull-Up set */
5843 #define PWR_PUCRG_PG6 ((uint32_t)0x00000040U) /*!< Port PG6 Pull-Up set */
5844 #define PWR_PUCRG_PG5 ((uint32_t)0x00000020U) /*!< Port PG5 Pull-Up set */
5845 #define PWR_PUCRG_PG4 ((uint32_t)0x00000010U) /*!< Port PG4 Pull-Up set */
5846 #define PWR_PUCRG_PG3 ((uint32_t)0x00000008U) /*!< Port PG3 Pull-Up set */
5847 #define PWR_PUCRG_PG2 ((uint32_t)0x00000004U) /*!< Port PG2 Pull-Up set */
5848 #define PWR_PUCRG_PG1 ((uint32_t)0x00000002U) /*!< Port PG1 Pull-Up set */
5849 #define PWR_PUCRG_PG0 ((uint32_t)0x00000001U) /*!< Port PG0 Pull-Up set */
5850
5851 /******************** Bit definition for PWR_PDCRG register ********************/
5852 #define PWR_PDCRG_PG15 ((uint32_t)0x00008000U) /*!< Port PG15 Pull-Down set */
5853 #define PWR_PDCRG_PG14 ((uint32_t)0x00004000U) /*!< Port PG14 Pull-Down set */
5854 #define PWR_PDCRG_PG13 ((uint32_t)0x00002000U) /*!< Port PG13 Pull-Down set */
5855 #define PWR_PDCRG_PG12 ((uint32_t)0x00001000U) /*!< Port PG12 Pull-Down set */
5856 #define PWR_PDCRG_PG11 ((uint32_t)0x00000800U) /*!< Port PG11 Pull-Down set */
5857 #define PWR_PDCRG_PG10 ((uint32_t)0x00000400U) /*!< Port PG10 Pull-Down set */
5858 #define PWR_PDCRG_PG9 ((uint32_t)0x00000200U) /*!< Port PG9 Pull-Down set */
5859 #define PWR_PDCRG_PG8 ((uint32_t)0x00000100U) /*!< Port PG8 Pull-Down set */
5860 #define PWR_PDCRG_PG7 ((uint32_t)0x00000080U) /*!< Port PG7 Pull-Down set */
5861 #define PWR_PDCRG_PG6 ((uint32_t)0x00000040U) /*!< Port PG6 Pull-Down set */
5862 #define PWR_PDCRG_PG5 ((uint32_t)0x00000020U) /*!< Port PG5 Pull-Down set */
5863 #define PWR_PDCRG_PG4 ((uint32_t)0x00000010U) /*!< Port PG4 Pull-Down set */
5864 #define PWR_PDCRG_PG3 ((uint32_t)0x00000008U) /*!< Port PG3 Pull-Down set */
5865 #define PWR_PDCRG_PG2 ((uint32_t)0x00000004U) /*!< Port PG2 Pull-Down set */
5866 #define PWR_PDCRG_PG1 ((uint32_t)0x00000002U) /*!< Port PG1 Pull-Down set */
5867 #define PWR_PDCRG_PG0 ((uint32_t)0x00000001U) /*!< Port PG0 Pull-Down set */
5868
5869 /******************** Bit definition for PWR_PUCRH register ********************/
5870 #define PWR_PUCRH_PH1 ((uint32_t)0x00000002U) /*!< Port PH1 Pull-Up set */
5871 #define PWR_PUCRH_PH0 ((uint32_t)0x00000001U) /*!< Port PH0 Pull-Up set */
5872
5873 /******************** Bit definition for PWR_PDCRH register ********************/
5874 #define PWR_PDCRH_PH1 ((uint32_t)0x00000002U) /*!< Port PH1 Pull-Down set */
5875 #define PWR_PDCRH_PH0 ((uint32_t)0x00000001U) /*!< Port PH0 Pull-Down set */
5876
5877
5878 /******************************************************************************/
5879 /* */
5880 /* Reset and Clock Control */
5881 /* */
5882 /******************************************************************************/
5883 /*
5884 * @brief Specific device feature definitions (not present on all devices in the STM32L4 family)
5885 */
5886 #define RCC_PLLSAI2_SUPPORT
5887
5888 /******************** Bit definition for RCC_CR register ********************/
5889 #define RCC_CR_MSION ((uint32_t)0x00000001U) /*!< Internal Multi Speed oscillator (MSI) clock enable */
5890 #define RCC_CR_MSIRDY ((uint32_t)0x00000002U) /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
5891 #define RCC_CR_MSIPLLEN ((uint32_t)0x00000004U) /*!< Internal Multi Speed oscillator (MSI) PLL enable */
5892 #define RCC_CR_MSIRGSEL ((uint32_t)0x00000008U) /*!< Internal Multi Speed oscillator (MSI) range selection */
5893
5894 /*!< MSIRANGE configuration : 12 frequency ranges available */
5895 #define RCC_CR_MSIRANGE ((uint32_t)0x000000F0U) /*!< Internal Multi Speed oscillator (MSI) clock Range */
5896 #define RCC_CR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed oscillator (MSI) clock Range 100 KHz */
5897 #define RCC_CR_MSIRANGE_1 ((uint32_t)0x00000010U) /*!< Internal Multi Speed oscillator (MSI) clock Range 200 KHz */
5898 #define RCC_CR_MSIRANGE_2 ((uint32_t)0x00000020U) /*!< Internal Multi Speed oscillator (MSI) clock Range 400 KHz */
5899 #define RCC_CR_MSIRANGE_3 ((uint32_t)0x00000030U) /*!< Internal Multi Speed oscillator (MSI) clock Range 800 KHz */
5900 #define RCC_CR_MSIRANGE_4 ((uint32_t)0x00000040U) /*!< Internal Multi Speed oscillator (MSI) clock Range 1 MHz */
5901 #define RCC_CR_MSIRANGE_5 ((uint32_t)0x00000050U) /*!< Internal Multi Speed oscillator (MSI) clock Range 2 MHz */
5902 #define RCC_CR_MSIRANGE_6 ((uint32_t)0x00000060U) /*!< Internal Multi Speed oscillator (MSI) clock Range 4 MHz */
5903 #define RCC_CR_MSIRANGE_7 ((uint32_t)0x00000070U) /*!< Internal Multi Speed oscillator (MSI) clock Range 8 KHz */
5904 #define RCC_CR_MSIRANGE_8 ((uint32_t)0x00000080U) /*!< Internal Multi Speed oscillator (MSI) clock Range 16 MHz */
5905 #define RCC_CR_MSIRANGE_9 ((uint32_t)0x00000090U) /*!< Internal Multi Speed oscillator (MSI) clock Range 24 MHz */
5906 #define RCC_CR_MSIRANGE_10 ((uint32_t)0x000000A0U) /*!< Internal Multi Speed oscillator (MSI) clock Range 32 MHz */
5907 #define RCC_CR_MSIRANGE_11 ((uint32_t)0x000000B0U) /*!< Internal Multi Speed oscillator (MSI) clock Range 48 MHz */
5908
5909 #define RCC_CR_HSION ((uint32_t)0x00000100U) /*!< Internal High Speed oscillator (HSI16) clock enable */
5910 #define RCC_CR_HSIKERON ((uint32_t)0x00000200U) /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
5911 #define RCC_CR_HSIRDY ((uint32_t)0x00000400U) /*!< Internal High Speed oscillator (HSI16) clock ready flag */
5912 #define RCC_CR_HSIASFS ((uint32_t)0x00000800U) /*!< HSI16 Automatic Start from Stop */
5913
5914 #define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed oscillator (HSE) clock enable */
5915 #define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed oscillator (HSE) clock ready */
5916 #define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed oscillator (HSE) clock bypass */
5917 #define RCC_CR_CSSON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */
5918
5919 #define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< System PLL clock enable */
5920 #define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< System PLL clock ready */
5921 #define RCC_CR_PLLSAI1ON ((uint32_t)0x04000000U) /*!< SAI1 PLL enable */
5922 #define RCC_CR_PLLSAI1RDY ((uint32_t)0x08000000U) /*!< SAI1 PLL ready */
5923 #define RCC_CR_PLLSAI2ON ((uint32_t)0x10000000U) /*!< SAI2 PLL enable */
5924 #define RCC_CR_PLLSAI2RDY ((uint32_t)0x20000000U) /*!< SAI2 PLL ready */
5925
5926 /******************** Bit definition for RCC_ICSCR register ***************/
5927 /*!< MSICAL configuration */
5928 #define RCC_ICSCR_MSICAL ((uint32_t)0x000000FFU) /*!< MSICAL[7:0] bits */
5929 #define RCC_ICSCR_MSICAL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
5930 #define RCC_ICSCR_MSICAL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
5931 #define RCC_ICSCR_MSICAL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
5932 #define RCC_ICSCR_MSICAL_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
5933 #define RCC_ICSCR_MSICAL_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
5934 #define RCC_ICSCR_MSICAL_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
5935 #define RCC_ICSCR_MSICAL_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
5936 #define RCC_ICSCR_MSICAL_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
5937
5938 /*!< MSITRIM configuration */
5939 #define RCC_ICSCR_MSITRIM ((uint32_t)0x0000FF00U) /*!< MSITRIM[7:0] bits */
5940 #define RCC_ICSCR_MSITRIM_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
5941 #define RCC_ICSCR_MSITRIM_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
5942 #define RCC_ICSCR_MSITRIM_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
5943 #define RCC_ICSCR_MSITRIM_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
5944 #define RCC_ICSCR_MSITRIM_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
5945 #define RCC_ICSCR_MSITRIM_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
5946 #define RCC_ICSCR_MSITRIM_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
5947 #define RCC_ICSCR_MSITRIM_7 ((uint32_t)0x00008000U) /*!<Bit 7 */
5948
5949 /*!< HSICAL configuration */
5950 #define RCC_ICSCR_HSICAL ((uint32_t)0x00FF0000U) /*!< HSICAL[7:0] bits */
5951 #define RCC_ICSCR_HSICAL_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
5952 #define RCC_ICSCR_HSICAL_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
5953 #define RCC_ICSCR_HSICAL_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
5954 #define RCC_ICSCR_HSICAL_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
5955 #define RCC_ICSCR_HSICAL_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
5956 #define RCC_ICSCR_HSICAL_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
5957 #define RCC_ICSCR_HSICAL_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
5958 #define RCC_ICSCR_HSICAL_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
5959
5960 /*!< HSITRIM configuration */
5961 #define RCC_ICSCR_HSITRIM ((uint32_t)0x1F000000U) /*!< HSITRIM[4:0] bits */
5962 #define RCC_ICSCR_HSITRIM_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
5963 #define RCC_ICSCR_HSITRIM_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
5964 #define RCC_ICSCR_HSITRIM_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
5965 #define RCC_ICSCR_HSITRIM_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
5966 #define RCC_ICSCR_HSITRIM_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
5967
5968 /******************** Bit definition for RCC_CFGR register ******************/
5969 /*!< SW configuration */
5970 #define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
5971 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
5972 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
5973
5974 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator selection as system clock */
5975 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI16 oscillator selection as system clock */
5976 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE oscillator selection as system clock */
5977 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selection as system clock */
5978
5979 /*!< SWS configuration */
5980 #define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
5981 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
5982 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
5983
5984 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
5985 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI16 oscillator used as system clock */
5986 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
5987 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
5988
5989 /*!< HPRE configuration */
5990 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
5991 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
5992 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
5993 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
5994 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
5995
5996 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
5997 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
5998 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
5999 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
6000 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
6001 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
6002 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
6003 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
6004 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
6005
6006 /*!< PPRE1 configuration */
6007 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB2 prescaler) */
6008 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
6009 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
6010 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
6011
6012 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
6013 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
6014 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
6015 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
6016 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
6017
6018 /*!< PPRE2 configuration */
6019 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
6020 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!<Bit 0 */
6021 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!<Bit 1 */
6022 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!<Bit 2 */
6023
6024 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
6025 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
6026 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
6027 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
6028 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
6029
6030 #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from stop and CSS backup clock selection */
6031
6032 /*!< MCOSEL configuration */
6033 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000U) /*!< MCOSEL [2:0] bits (Clock output selection) */
6034 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
6035 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
6036 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
6037
6038 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */
6039 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
6040 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
6041 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
6042
6043 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
6044 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
6045 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
6046 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
6047 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
6048
6049 /* Legacy aliases */
6050 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
6051 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
6052 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
6053 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
6054 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
6055 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
6056
6057 /******************** Bit definition for RCC_PLLCFGR register ***************/
6058 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00000003U)
6059
6060 #define RCC_PLLCFGR_PLLSRC_MSI ((uint32_t)0x00000001U) /*!< MSI oscillator source clock selected */
6061 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000002U) /*!< HSI16 oscillator source clock selected */
6062 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00000003U) /*!< HSE oscillator source clock selected */
6063
6064 #define RCC_PLLCFGR_PLLM ((uint32_t)0x00000070U)
6065 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000010U)
6066 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000020U)
6067 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000040U)
6068
6069 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007F00U)
6070 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000100U)
6071 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000200U)
6072 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000400U)
6073 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000800U)
6074 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00001000U)
6075 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00002000U)
6076 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00004000U)
6077
6078 #define RCC_PLLCFGR_PLLPEN ((uint32_t)0x00010000U)
6079 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00020000U)
6080 #define RCC_PLLCFGR_PLLQEN ((uint32_t)0x00100000U)
6081
6082 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x00600000U)
6083 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x00200000U)
6084 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x00400000U)
6085
6086 #define RCC_PLLCFGR_PLLREN ((uint32_t)0x01000000U)
6087 #define RCC_PLLCFGR_PLLR ((uint32_t)0x06000000U)
6088 #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x02000000U)
6089 #define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x04000000U)
6090
6091 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
6092 #define RCC_PLLSAI1CFGR_PLLSAI1N ((uint32_t)0x00007F00U)
6093 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 ((uint32_t)0x00000100U)
6094 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 ((uint32_t)0x00000200U)
6095 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 ((uint32_t)0x00000400U)
6096 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 ((uint32_t)0x00000800U)
6097 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 ((uint32_t)0x00001000U)
6098 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 ((uint32_t)0x00002000U)
6099 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 ((uint32_t)0x00004000U)
6100
6101 #define RCC_PLLSAI1CFGR_PLLSAI1PEN ((uint32_t)0x00010000U)
6102 #define RCC_PLLSAI1CFGR_PLLSAI1P ((uint32_t)0x00020000U)
6103
6104 #define RCC_PLLSAI1CFGR_PLLSAI1QEN ((uint32_t)0x00100000U)
6105 #define RCC_PLLSAI1CFGR_PLLSAI1Q ((uint32_t)0x00600000U)
6106 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 ((uint32_t)0x00200000U)
6107 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 ((uint32_t)0x00400000U)
6108
6109 #define RCC_PLLSAI1CFGR_PLLSAI1REN ((uint32_t)0x01000000U)
6110 #define RCC_PLLSAI1CFGR_PLLSAI1R ((uint32_t)0x06000000U)
6111 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 ((uint32_t)0x02000000U)
6112 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 ((uint32_t)0x04000000U)
6113
6114 /******************** Bit definition for RCC_PLLSAI2CFGR register ************/
6115 #define RCC_PLLSAI2CFGR_PLLSAI2N ((uint32_t)0x00007F00U)
6116 #define RCC_PLLSAI2CFGR_PLLSAI2N_0 ((uint32_t)0x00000100U)
6117 #define RCC_PLLSAI2CFGR_PLLSAI2N_1 ((uint32_t)0x00000200U)
6118 #define RCC_PLLSAI2CFGR_PLLSAI2N_2 ((uint32_t)0x00000400U)
6119 #define RCC_PLLSAI2CFGR_PLLSAI2N_3 ((uint32_t)0x00000800U)
6120 #define RCC_PLLSAI2CFGR_PLLSAI2N_4 ((uint32_t)0x00001000U)
6121 #define RCC_PLLSAI2CFGR_PLLSAI2N_5 ((uint32_t)0x00002000U)
6122 #define RCC_PLLSAI2CFGR_PLLSAI2N_6 ((uint32_t)0x00004000U)
6123
6124 #define RCC_PLLSAI2CFGR_PLLSAI2PEN ((uint32_t)0x00010000U)
6125 #define RCC_PLLSAI2CFGR_PLLSAI2P ((uint32_t)0x00020000U)
6126
6127 #define RCC_PLLSAI2CFGR_PLLSAI2REN ((uint32_t)0x01000000U)
6128 #define RCC_PLLSAI2CFGR_PLLSAI2R ((uint32_t)0x06000000U)
6129 #define RCC_PLLSAI2CFGR_PLLSAI2R_0 ((uint32_t)0x02000000U)
6130 #define RCC_PLLSAI2CFGR_PLLSAI2R_1 ((uint32_t)0x04000000U)
6131
6132 /******************** Bit definition for RCC_CIER register ******************/
6133 #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U)
6134 #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U)
6135 #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000004U)
6136 #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000008U)
6137 #define RCC_CIER_HSERDYIE ((uint32_t)0x00000010U)
6138 #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000020U)
6139 #define RCC_CIER_PLLSAI1RDYIE ((uint32_t)0x00000040U)
6140 #define RCC_CIER_PLLSAI2RDYIE ((uint32_t)0x00000080U)
6141 #define RCC_CIER_LSECSSIE ((uint32_t)0x00000200U)
6142
6143 /******************** Bit definition for RCC_CIFR register ******************/
6144 #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U)
6145 #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U)
6146 #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000004U)
6147 #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000008U)
6148 #define RCC_CIFR_HSERDYF ((uint32_t)0x00000010U)
6149 #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000020U)
6150 #define RCC_CIFR_PLLSAI1RDYF ((uint32_t)0x00000040U)
6151 #define RCC_CIFR_PLLSAI2RDYF ((uint32_t)0x00000080U)
6152 #define RCC_CIFR_CSSF ((uint32_t)0x00000100U)
6153 #define RCC_CIFR_LSECSSF ((uint32_t)0x00000200U)
6154
6155 /******************** Bit definition for RCC_CICR register ******************/
6156 #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U)
6157 #define RCC_CICR_LSERDYC ((uint32_t)0x00000002U)
6158 #define RCC_CICR_MSIRDYC ((uint32_t)0x00000004U)
6159 #define RCC_CICR_HSIRDYC ((uint32_t)0x00000008U)
6160 #define RCC_CICR_HSERDYC ((uint32_t)0x00000010U)
6161 #define RCC_CICR_PLLRDYC ((uint32_t)0x00000020U)
6162 #define RCC_CICR_PLLSAI1RDYC ((uint32_t)0x00000040U)
6163 #define RCC_CICR_PLLSAI2RDYC ((uint32_t)0x00000080U)
6164 #define RCC_CICR_CSSC ((uint32_t)0x00000100U)
6165 #define RCC_CICR_LSECSSC ((uint32_t)0x00000200U)
6166
6167 /******************** Bit definition for RCC_AHB1RSTR register **************/
6168 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00000001U)
6169 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00000002U)
6170 #define RCC_AHB1RSTR_FLASHRST ((uint32_t)0x00000100U)
6171 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000U)
6172 #define RCC_AHB1RSTR_TSCRST ((uint32_t)0x00010000U)
6173
6174 /******************** Bit definition for RCC_AHB2RSTR register **************/
6175 #define RCC_AHB2RSTR_GPIOARST ((uint32_t)0x00000001U)
6176 #define RCC_AHB2RSTR_GPIOBRST ((uint32_t)0x00000002U)
6177 #define RCC_AHB2RSTR_GPIOCRST ((uint32_t)0x00000004U)
6178 #define RCC_AHB2RSTR_GPIODRST ((uint32_t)0x00000008U)
6179 #define RCC_AHB2RSTR_GPIOERST ((uint32_t)0x00000010U)
6180 #define RCC_AHB2RSTR_GPIOFRST ((uint32_t)0x00000020U)
6181 #define RCC_AHB2RSTR_GPIOGRST ((uint32_t)0x00000040U)
6182 #define RCC_AHB2RSTR_GPIOHRST ((uint32_t)0x00000080U)
6183 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00001000U)
6184 #define RCC_AHB2RSTR_ADCRST ((uint32_t)0x00002000U)
6185 #define RCC_AHB2RSTR_AESRST ((uint32_t)0x00010000U)
6186 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00040000U)
6187
6188 /******************** Bit definition for RCC_AHB3RSTR register **************/
6189 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001U)
6190 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000100U)
6191
6192 /******************** Bit definition for RCC_APB1RSTR1 register **************/
6193 #define RCC_APB1RSTR1_TIM2RST ((uint32_t)0x00000001U)
6194 #define RCC_APB1RSTR1_TIM3RST ((uint32_t)0x00000002U)
6195 #define RCC_APB1RSTR1_TIM4RST ((uint32_t)0x00000004U)
6196 #define RCC_APB1RSTR1_TIM5RST ((uint32_t)0x00000008U)
6197 #define RCC_APB1RSTR1_TIM6RST ((uint32_t)0x00000010U)
6198 #define RCC_APB1RSTR1_TIM7RST ((uint32_t)0x00000020U)
6199 #define RCC_APB1RSTR1_LCDRST ((uint32_t)0x00000200U)
6200 #define RCC_APB1RSTR1_SPI2RST ((uint32_t)0x00004000U)
6201 #define RCC_APB1RSTR1_SPI3RST ((uint32_t)0x00008000U)
6202 #define RCC_APB1RSTR1_USART2RST ((uint32_t)0x00020000U)
6203 #define RCC_APB1RSTR1_USART3RST ((uint32_t)0x00040000U)
6204 #define RCC_APB1RSTR1_UART4RST ((uint32_t)0x00080000U)
6205 #define RCC_APB1RSTR1_UART5RST ((uint32_t)0x00100000U)
6206 #define RCC_APB1RSTR1_I2C1RST ((uint32_t)0x00200000U)
6207 #define RCC_APB1RSTR1_I2C2RST ((uint32_t)0x00400000U)
6208 #define RCC_APB1RSTR1_I2C3RST ((uint32_t)0x00800000U)
6209 #define RCC_APB1RSTR1_CAN1RST ((uint32_t)0x02000000U)
6210 #define RCC_APB1RSTR1_PWRRST ((uint32_t)0x10000000U)
6211 #define RCC_APB1RSTR1_DAC1RST ((uint32_t)0x20000000U)
6212 #define RCC_APB1RSTR1_OPAMPRST ((uint32_t)0x40000000U)
6213 #define RCC_APB1RSTR1_LPTIM1RST ((uint32_t)0x80000000U)
6214
6215 /******************** Bit definition for RCC_APB1RSTR2 register **************/
6216 #define RCC_APB1RSTR2_LPUART1RST ((uint32_t)0x00000001U)
6217 #define RCC_APB1RSTR2_SWPMI1RST ((uint32_t)0x00000004U)
6218 #define RCC_APB1RSTR2_LPTIM2RST ((uint32_t)0x00000020U)
6219
6220 /******************** Bit definition for RCC_APB2RSTR register **************/
6221 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U)
6222 #define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000400U)
6223 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800U)
6224 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U)
6225 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000U)
6226 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U)
6227 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000U)
6228 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000U)
6229 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000U)
6230 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00200000U)
6231 #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00400000U)
6232 #define RCC_APB2RSTR_DFSDMRST ((uint32_t)0x01000000U)
6233
6234 /******************** Bit definition for RCC_AHB1ENR register ***************/
6235 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00000001U)
6236 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00000002U)
6237 #define RCC_AHB1ENR_FLASHEN ((uint32_t)0x00000100U)
6238 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000U)
6239 #define RCC_AHB1ENR_TSCEN ((uint32_t)0x00010000U)
6240
6241 /******************** Bit definition for RCC_AHB2ENR register ***************/
6242 #define RCC_AHB2ENR_GPIOAEN ((uint32_t)0x00000001U)
6243 #define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002U)
6244 #define RCC_AHB2ENR_GPIOCEN ((uint32_t)0x00000004U)
6245 #define RCC_AHB2ENR_GPIODEN ((uint32_t)0x00000008U)
6246 #define RCC_AHB2ENR_GPIOEEN ((uint32_t)0x00000010U)
6247 #define RCC_AHB2ENR_GPIOFEN ((uint32_t)0x00000020U)
6248 #define RCC_AHB2ENR_GPIOGEN ((uint32_t)0x00000040U)
6249 #define RCC_AHB2ENR_GPIOHEN ((uint32_t)0x00000080U)
6250 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00001000U)
6251 #define RCC_AHB2ENR_ADCEN ((uint32_t)0x00002000U)
6252 #define RCC_AHB2ENR_AESEN ((uint32_t)0x00010000U)
6253 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00040000U)
6254
6255 /******************** Bit definition for RCC_AHB3ENR register ***************/
6256 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001U)
6257 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000100U)
6258
6259 /******************** Bit definition for RCC_APB1ENR1 register ***************/
6260 #define RCC_APB1ENR1_TIM2EN ((uint32_t)0x00000001U)
6261 #define RCC_APB1ENR1_TIM3EN ((uint32_t)0x00000002U)
6262 #define RCC_APB1ENR1_TIM4EN ((uint32_t)0x00000004U)
6263 #define RCC_APB1ENR1_TIM5EN ((uint32_t)0x00000008U)
6264 #define RCC_APB1ENR1_TIM6EN ((uint32_t)0x00000010U)
6265 #define RCC_APB1ENR1_TIM7EN ((uint32_t)0x00000020U)
6266 #define RCC_APB1ENR1_LCDEN ((uint32_t)0x00000200U)
6267 #define RCC_APB1ENR1_WWDGEN ((uint32_t)0x00000800U)
6268 #define RCC_APB1ENR1_SPI2EN ((uint32_t)0x00004000U)
6269 #define RCC_APB1ENR1_SPI3EN ((uint32_t)0x00008000U)
6270 #define RCC_APB1ENR1_USART2EN ((uint32_t)0x00020000U)
6271 #define RCC_APB1ENR1_USART3EN ((uint32_t)0x00040000U)
6272 #define RCC_APB1ENR1_UART4EN ((uint32_t)0x00080000U)
6273 #define RCC_APB1ENR1_UART5EN ((uint32_t)0x00100000U)
6274 #define RCC_APB1ENR1_I2C1EN ((uint32_t)0x00200000U)
6275 #define RCC_APB1ENR1_I2C2EN ((uint32_t)0x00400000U)
6276 #define RCC_APB1ENR1_I2C3EN ((uint32_t)0x00800000U)
6277 #define RCC_APB1ENR1_CAN1EN ((uint32_t)0x02000000U)
6278 #define RCC_APB1ENR1_PWREN ((uint32_t)0x10000000U)
6279 #define RCC_APB1ENR1_DAC1EN ((uint32_t)0x20000000U)
6280 #define RCC_APB1ENR1_OPAMPEN ((uint32_t)0x40000000U)
6281 #define RCC_APB1ENR1_LPTIM1EN ((uint32_t)0x80000000U)
6282
6283 /******************** Bit definition for RCC_APB1RSTR2 register **************/
6284 #define RCC_APB1ENR2_LPUART1EN ((uint32_t)0x00000001U)
6285 #define RCC_APB1ENR2_SWPMI1EN ((uint32_t)0x00000004U)
6286 #define RCC_APB1ENR2_LPTIM2EN ((uint32_t)0x00000020U)
6287
6288 /******************** Bit definition for RCC_APB2ENR register ***************/
6289 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U)
6290 #define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U)
6291 #define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000400U)
6292 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800U)
6293 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U)
6294 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000U)
6295 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U)
6296 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000U)
6297 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000U)
6298 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000U)
6299 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00200000U)
6300 #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00400000U)
6301 #define RCC_APB2ENR_DFSDMEN ((uint32_t)0x01000000U)
6302
6303 /******************** Bit definition for RCC_AHB1SMENR register ***************/
6304 #define RCC_AHB1SMENR_DMA1SMEN ((uint32_t)0x00000001U)
6305 #define RCC_AHB1SMENR_DMA2SMEN ((uint32_t)0x00000002U)
6306 #define RCC_AHB1SMENR_FLASHSMEN ((uint32_t)0x00000100U)
6307 #define RCC_AHB1SMENR_SRAM1SMEN ((uint32_t)0x00000200U)
6308 #define RCC_AHB1SMENR_CRCSMEN ((uint32_t)0x00001000U)
6309 #define RCC_AHB1SMENR_TSCSMEN ((uint32_t)0x00010000U)
6310
6311 /******************** Bit definition for RCC_AHB2SMENR register *************/
6312 #define RCC_AHB2SMENR_GPIOASMEN ((uint32_t)0x00000001U)
6313 #define RCC_AHB2SMENR_GPIOBSMEN ((uint32_t)0x00000002U)
6314 #define RCC_AHB2SMENR_GPIOCSMEN ((uint32_t)0x00000004U)
6315 #define RCC_AHB2SMENR_GPIODSMEN ((uint32_t)0x00000008U)
6316 #define RCC_AHB2SMENR_GPIOESMEN ((uint32_t)0x00000010U)
6317 #define RCC_AHB2SMENR_GPIOFSMEN ((uint32_t)0x00000020U)
6318 #define RCC_AHB2SMENR_GPIOGSMEN ((uint32_t)0x00000040U)
6319 #define RCC_AHB2SMENR_GPIOHSMEN ((uint32_t)0x00000080U)
6320 #define RCC_AHB2SMENR_SRAM2SMEN ((uint32_t)0x00000200U)
6321 #define RCC_AHB2SMENR_OTGFSSMEN ((uint32_t)0x00001000U)
6322 #define RCC_AHB2SMENR_ADCSMEN ((uint32_t)0x00002000U)
6323 #define RCC_AHB2SMENR_AESSMEN ((uint32_t)0x00010000U)
6324 #define RCC_AHB2SMENR_RNGSMEN ((uint32_t)0x00040000U)
6325
6326 /******************** Bit definition for RCC_AHB3SMENR register *************/
6327 #define RCC_AHB3SMENR_FMCSMEN ((uint32_t)0x00000001U)
6328 #define RCC_AHB3SMENR_QSPISMEN ((uint32_t)0x00000100U)
6329
6330 /******************** Bit definition for RCC_APB1SMENR1 register *************/
6331 #define RCC_APB1SMENR1_TIM2SMEN ((uint32_t)0x00000001U)
6332 #define RCC_APB1SMENR1_TIM3SMEN ((uint32_t)0x00000002U)
6333 #define RCC_APB1SMENR1_TIM4SMEN ((uint32_t)0x00000004U)
6334 #define RCC_APB1SMENR1_TIM5SMEN ((uint32_t)0x00000008U)
6335 #define RCC_APB1SMENR1_TIM6SMEN ((uint32_t)0x00000010U)
6336 #define RCC_APB1SMENR1_TIM7SMEN ((uint32_t)0x00000020U)
6337 #define RCC_APB1SMENR1_LCDSMEN ((uint32_t)0x00000200U)
6338 #define RCC_APB1SMENR1_WWDGSMEN ((uint32_t)0x00000800U)
6339 #define RCC_APB1SMENR1_SPI2SMEN ((uint32_t)0x00004000U)
6340 #define RCC_APB1SMENR1_SPI3SMEN ((uint32_t)0x00008000U)
6341 #define RCC_APB1SMENR1_USART2SMEN ((uint32_t)0x00020000U)
6342 #define RCC_APB1SMENR1_USART3SMEN ((uint32_t)0x00040000U)
6343 #define RCC_APB1SMENR1_UART4SMEN ((uint32_t)0x00080000U)
6344 #define RCC_APB1SMENR1_UART5SMEN ((uint32_t)0x00100000U)
6345 #define RCC_APB1SMENR1_I2C1SMEN ((uint32_t)0x00200000U)
6346 #define RCC_APB1SMENR1_I2C2SMEN ((uint32_t)0x00400000U)
6347 #define RCC_APB1SMENR1_I2C3SMEN ((uint32_t)0x00800000U)
6348 #define RCC_APB1SMENR1_CAN1SMEN ((uint32_t)0x02000000U)
6349 #define RCC_APB1SMENR1_PWRSMEN ((uint32_t)0x10000000U)
6350 #define RCC_APB1SMENR1_DAC1SMEN ((uint32_t)0x20000000U)
6351 #define RCC_APB1SMENR1_OPAMPSMEN ((uint32_t)0x40000000U)
6352 #define RCC_APB1SMENR1_LPTIM1SMEN ((uint32_t)0x80000000U)
6353
6354 /******************** Bit definition for RCC_APB1SMENR2 register *************/
6355 #define RCC_APB1SMENR2_LPUART1SMEN ((uint32_t)0x00000001U)
6356 #define RCC_APB1SMENR2_SWPMI1SMEN ((uint32_t)0x00000004U)
6357 #define RCC_APB1SMENR2_LPTIM2SMEN ((uint32_t)0x00000020U)
6358
6359 /******************** Bit definition for RCC_APB2SMENR register *************/
6360 #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U)
6361 #define RCC_APB2SMENR_SDMMC1SMEN ((uint32_t)0x00000400U)
6362 #define RCC_APB2SMENR_TIM1SMEN ((uint32_t)0x00000800U)
6363 #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U)
6364 #define RCC_APB2SMENR_TIM8SMEN ((uint32_t)0x00002000U)
6365 #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U)
6366 #define RCC_APB2SMENR_TIM15SMEN ((uint32_t)0x00010000U)
6367 #define RCC_APB2SMENR_TIM16SMEN ((uint32_t)0x00020000U)
6368 #define RCC_APB2SMENR_TIM17SMEN ((uint32_t)0x00040000U)
6369 #define RCC_APB2SMENR_SAI1SMEN ((uint32_t)0x00200000U)
6370 #define RCC_APB2SMENR_SAI2SMEN ((uint32_t)0x00400000U)
6371 #define RCC_APB2SMENR_DFSDMSMEN ((uint32_t)0x01000000U)
6372
6373 /******************** Bit definition for RCC_CCIPR register ******************/
6374 #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U)
6375 #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U)
6376 #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U)
6377
6378 #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU)
6379 #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U)
6380 #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U)
6381
6382 #define RCC_CCIPR_USART3SEL ((uint32_t)0x00000030U)
6383 #define RCC_CCIPR_USART3SEL_0 ((uint32_t)0x00000010U)
6384 #define RCC_CCIPR_USART3SEL_1 ((uint32_t)0x00000020U)
6385
6386 #define RCC_CCIPR_UART4SEL ((uint32_t)0x000000C0U)
6387 #define RCC_CCIPR_UART4SEL_0 ((uint32_t)0x00000040U)
6388 #define RCC_CCIPR_UART4SEL_1 ((uint32_t)0x00000080U)
6389
6390 #define RCC_CCIPR_UART5SEL ((uint32_t)0x00000300U)
6391 #define RCC_CCIPR_UART5SEL_0 ((uint32_t)0x00000100U)
6392 #define RCC_CCIPR_UART5SEL_1 ((uint32_t)0x00000200U)
6393
6394 #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x00000C00U)
6395 #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x00000400U)
6396 #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x00000800U)
6397
6398 #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U)
6399 #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U)
6400 #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U)
6401
6402 #define RCC_CCIPR_I2C2SEL ((uint32_t)0x0000C000U)
6403 #define RCC_CCIPR_I2C2SEL_0 ((uint32_t)0x00004000U)
6404 #define RCC_CCIPR_I2C2SEL_1 ((uint32_t)0x00008000U)
6405
6406 #define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000U)
6407 #define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000U)
6408 #define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000U)
6409
6410 #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U)
6411 #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U)
6412 #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U)
6413
6414 #define RCC_CCIPR_LPTIM2SEL ((uint32_t)0x00300000U)
6415 #define RCC_CCIPR_LPTIM2SEL_0 ((uint32_t)0x00100000U)
6416 #define RCC_CCIPR_LPTIM2SEL_1 ((uint32_t)0x00200000U)
6417
6418 #define RCC_CCIPR_SAI1SEL ((uint32_t)0x00C00000U)
6419 #define RCC_CCIPR_SAI1SEL_0 ((uint32_t)0x00400000U)
6420 #define RCC_CCIPR_SAI1SEL_1 ((uint32_t)0x00800000U)
6421
6422 #define RCC_CCIPR_SAI2SEL ((uint32_t)0x03000000U)
6423 #define RCC_CCIPR_SAI2SEL_0 ((uint32_t)0x01000000U)
6424 #define RCC_CCIPR_SAI2SEL_1 ((uint32_t)0x02000000U)
6425
6426 #define RCC_CCIPR_CLK48SEL ((uint32_t)0x0C000000U)
6427 #define RCC_CCIPR_CLK48SEL_0 ((uint32_t)0x04000000U)
6428 #define RCC_CCIPR_CLK48SEL_1 ((uint32_t)0x08000000U)
6429
6430 #define RCC_CCIPR_ADCSEL ((uint32_t)0x30000000U)
6431 #define RCC_CCIPR_ADCSEL_0 ((uint32_t)0x10000000U)
6432 #define RCC_CCIPR_ADCSEL_1 ((uint32_t)0x20000000U)
6433
6434 #define RCC_CCIPR_SWPMI1SEL ((uint32_t)0x40000000U)
6435 #define RCC_CCIPR_DFSDMSEL ((uint32_t)0x80000000U)
6436
6437 /******************** Bit definition for RCC_BDCR register ******************/
6438 #define RCC_BDCR_LSEON ((uint32_t)0x00000001U)
6439 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002U)
6440 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004U)
6441
6442 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018U)
6443 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008U)
6444 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010U)
6445
6446 #define RCC_BDCR_LSECSSON ((uint32_t)0x00000020U)
6447 #define RCC_BDCR_LSECSSD ((uint32_t)0x00000040U)
6448
6449 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300U)
6450 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100U)
6451 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200U)
6452
6453 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000U)
6454 #define RCC_BDCR_BDRST ((uint32_t)0x00010000U)
6455 #define RCC_BDCR_LSCOEN ((uint32_t)0x01000000U)
6456 #define RCC_BDCR_LSCOSEL ((uint32_t)0x02000000U)
6457
6458 /******************** Bit definition for RCC_CSR register *******************/
6459 #define RCC_CSR_LSION ((uint32_t)0x00000001U)
6460 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002U)
6461
6462 #define RCC_CSR_MSISRANGE ((uint32_t)0x00000F00U)
6463 #define RCC_CSR_MSISRANGE_1 ((uint32_t)0x00000400U) /*!< MSI frequency 1MHZ */
6464 #define RCC_CSR_MSISRANGE_2 ((uint32_t)0x00000500U) /*!< MSI frequency 2MHZ */
6465 #define RCC_CSR_MSISRANGE_4 ((uint32_t)0x00000600U) /*!< The default frequency 4MHZ */
6466 #define RCC_CSR_MSISRANGE_8 ((uint32_t)0x00000700U) /*!< MSI frequency 8MHZ */
6467
6468 #define RCC_CSR_RMVF ((uint32_t)0x00800000U)
6469 #define RCC_CSR_FWRSTF ((uint32_t)0x01000000U)
6470 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U)
6471 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000U)
6472 #define RCC_CSR_BORRSTF ((uint32_t)0x08000000U)
6473 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U)
6474 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U)
6475 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U)
6476 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U)
6477
6478
6479
6480 /******************************************************************************/
6481 /* */
6482 /* RNG */
6483 /* */
6484 /******************************************************************************/
6485 /******************** Bits definition for RNG_CR register *******************/
6486 #define RNG_CR_RNGEN ((uint32_t)0x00000004U)
6487 #define RNG_CR_IE ((uint32_t)0x00000008U)
6488
6489 /******************** Bits definition for RNG_SR register *******************/
6490 #define RNG_SR_DRDY ((uint32_t)0x00000001U)
6491 #define RNG_SR_CECS ((uint32_t)0x00000002U)
6492 #define RNG_SR_SECS ((uint32_t)0x00000004U)
6493 #define RNG_SR_CEIS ((uint32_t)0x00000020U)
6494 #define RNG_SR_SEIS ((uint32_t)0x00000040U)
6495
6496 /******************************************************************************/
6497 /* */
6498 /* Real-Time Clock (RTC) */
6499 /* */
6500 /******************************************************************************/
6501 /*
6502 * @brief Specific device feature definitions
6503 */
6504 #define RTC_TAMPER1_SUPPORT
6505 #define RTC_TAMPER3_SUPPORT
6506 #define RTC_WAKEUP_SUPPORT
6507 #define RTC_BACKUP_SUPPORT
6508
6509 /******************** Bits definition for RTC_TR register *******************/
6510 #define RTC_TR_PM ((uint32_t)0x00400000U)
6511 #define RTC_TR_HT ((uint32_t)0x00300000U)
6512 #define RTC_TR_HT_0 ((uint32_t)0x00100000U)
6513 #define RTC_TR_HT_1 ((uint32_t)0x00200000U)
6514 #define RTC_TR_HU ((uint32_t)0x000F0000U)
6515 #define RTC_TR_HU_0 ((uint32_t)0x00010000U)
6516 #define RTC_TR_HU_1 ((uint32_t)0x00020000U)
6517 #define RTC_TR_HU_2 ((uint32_t)0x00040000U)
6518 #define RTC_TR_HU_3 ((uint32_t)0x00080000U)
6519 #define RTC_TR_MNT ((uint32_t)0x00007000U)
6520 #define RTC_TR_MNT_0 ((uint32_t)0x00001000U)
6521 #define RTC_TR_MNT_1 ((uint32_t)0x00002000U)
6522 #define RTC_TR_MNT_2 ((uint32_t)0x00004000U)
6523 #define RTC_TR_MNU ((uint32_t)0x00000F00U)
6524 #define RTC_TR_MNU_0 ((uint32_t)0x00000100U)
6525 #define RTC_TR_MNU_1 ((uint32_t)0x00000200U)
6526 #define RTC_TR_MNU_2 ((uint32_t)0x00000400U)
6527 #define RTC_TR_MNU_3 ((uint32_t)0x00000800U)
6528 #define RTC_TR_ST ((uint32_t)0x00000070U)
6529 #define RTC_TR_ST_0 ((uint32_t)0x00000010U)
6530 #define RTC_TR_ST_1 ((uint32_t)0x00000020U)
6531 #define RTC_TR_ST_2 ((uint32_t)0x00000040U)
6532 #define RTC_TR_SU ((uint32_t)0x0000000FU)
6533 #define RTC_TR_SU_0 ((uint32_t)0x00000001U)
6534 #define RTC_TR_SU_1 ((uint32_t)0x00000002U)
6535 #define RTC_TR_SU_2 ((uint32_t)0x00000004U)
6536 #define RTC_TR_SU_3 ((uint32_t)0x00000008U)
6537
6538 /******************** Bits definition for RTC_DR register *******************/
6539 #define RTC_DR_YT ((uint32_t)0x00F00000U)
6540 #define RTC_DR_YT_0 ((uint32_t)0x00100000U)
6541 #define RTC_DR_YT_1 ((uint32_t)0x00200000U)
6542 #define RTC_DR_YT_2 ((uint32_t)0x00400000U)
6543 #define RTC_DR_YT_3 ((uint32_t)0x00800000U)
6544 #define RTC_DR_YU ((uint32_t)0x000F0000U)
6545 #define RTC_DR_YU_0 ((uint32_t)0x00010000U)
6546 #define RTC_DR_YU_1 ((uint32_t)0x00020000U)
6547 #define RTC_DR_YU_2 ((uint32_t)0x00040000U)
6548 #define RTC_DR_YU_3 ((uint32_t)0x00080000U)
6549 #define RTC_DR_WDU ((uint32_t)0x0000E000U)
6550 #define RTC_DR_WDU_0 ((uint32_t)0x00002000U)
6551 #define RTC_DR_WDU_1 ((uint32_t)0x00004000U)
6552 #define RTC_DR_WDU_2 ((uint32_t)0x00008000U)
6553 #define RTC_DR_MT ((uint32_t)0x00001000U)
6554 #define RTC_DR_MU ((uint32_t)0x00000F00U)
6555 #define RTC_DR_MU_0 ((uint32_t)0x00000100U)
6556 #define RTC_DR_MU_1 ((uint32_t)0x00000200U)
6557 #define RTC_DR_MU_2 ((uint32_t)0x00000400U)
6558 #define RTC_DR_MU_3 ((uint32_t)0x00000800U)
6559 #define RTC_DR_DT ((uint32_t)0x00000030U)
6560 #define RTC_DR_DT_0 ((uint32_t)0x00000010U)
6561 #define RTC_DR_DT_1 ((uint32_t)0x00000020U)
6562 #define RTC_DR_DU ((uint32_t)0x0000000FU)
6563 #define RTC_DR_DU_0 ((uint32_t)0x00000001U)
6564 #define RTC_DR_DU_1 ((uint32_t)0x00000002U)
6565 #define RTC_DR_DU_2 ((uint32_t)0x00000004U)
6566 #define RTC_DR_DU_3 ((uint32_t)0x00000008U)
6567
6568 /******************** Bits definition for RTC_CR register *******************/
6569 #define RTC_CR_ITSE ((uint32_t)0x01000000U)
6570 #define RTC_CR_COE ((uint32_t)0x00800000U)
6571 #define RTC_CR_OSEL ((uint32_t)0x00600000U)
6572 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000U)
6573 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000U)
6574 #define RTC_CR_POL ((uint32_t)0x00100000U)
6575 #define RTC_CR_COSEL ((uint32_t)0x00080000U)
6576 #define RTC_CR_BCK ((uint32_t)0x00040000U)
6577 #define RTC_CR_SUB1H ((uint32_t)0x00020000U)
6578 #define RTC_CR_ADD1H ((uint32_t)0x00010000U)
6579 #define RTC_CR_TSIE ((uint32_t)0x00008000U)
6580 #define RTC_CR_WUTIE ((uint32_t)0x00004000U)
6581 #define RTC_CR_ALRBIE ((uint32_t)0x00002000U)
6582 #define RTC_CR_ALRAIE ((uint32_t)0x00001000U)
6583 #define RTC_CR_TSE ((uint32_t)0x00000800U)
6584 #define RTC_CR_WUTE ((uint32_t)0x00000400U)
6585 #define RTC_CR_ALRBE ((uint32_t)0x00000200U)
6586 #define RTC_CR_ALRAE ((uint32_t)0x00000100U)
6587 #define RTC_CR_FMT ((uint32_t)0x00000040U)
6588 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020U)
6589 #define RTC_CR_REFCKON ((uint32_t)0x00000010U)
6590 #define RTC_CR_TSEDGE ((uint32_t)0x00000008U)
6591 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007U)
6592 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U)
6593 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U)
6594 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U)
6595
6596 /******************** Bits definition for RTC_ISR register ******************/
6597 #define RTC_ISR_ITSF ((uint32_t)0x00020000U)
6598 #define RTC_ISR_RECALPF ((uint32_t)0x00010000U)
6599 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000U)
6600 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000U)
6601 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000U)
6602 #define RTC_ISR_TSOVF ((uint32_t)0x00001000U)
6603 #define RTC_ISR_TSF ((uint32_t)0x00000800U)
6604 #define RTC_ISR_WUTF ((uint32_t)0x00000400U)
6605 #define RTC_ISR_ALRBF ((uint32_t)0x00000200U)
6606 #define RTC_ISR_ALRAF ((uint32_t)0x00000100U)
6607 #define RTC_ISR_INIT ((uint32_t)0x00000080U)
6608 #define RTC_ISR_INITF ((uint32_t)0x00000040U)
6609 #define RTC_ISR_RSF ((uint32_t)0x00000020U)
6610 #define RTC_ISR_INITS ((uint32_t)0x00000010U)
6611 #define RTC_ISR_SHPF ((uint32_t)0x00000008U)
6612 #define RTC_ISR_WUTWF ((uint32_t)0x00000004U)
6613 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002U)
6614 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001U)
6615
6616 /******************** Bits definition for RTC_PRER register *****************/
6617 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U)
6618 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU)
6619
6620 /******************** Bits definition for RTC_WUTR register *****************/
6621 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
6622
6623 /******************** Bits definition for RTC_ALRMAR register ***************/
6624 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U)
6625 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U)
6626 #define RTC_ALRMAR_DT ((uint32_t)0x30000000U)
6627 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U)
6628 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U)
6629 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000U)
6630 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U)
6631 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U)
6632 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U)
6633 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U)
6634 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U)
6635 #define RTC_ALRMAR_PM ((uint32_t)0x00400000U)
6636 #define RTC_ALRMAR_HT ((uint32_t)0x00300000U)
6637 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U)
6638 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U)
6639 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000U)
6640 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U)
6641 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U)
6642 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U)
6643 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U)
6644 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U)
6645 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000U)
6646 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U)
6647 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U)
6648 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U)
6649 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U)
6650 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U)
6651 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U)
6652 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U)
6653 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U)
6654 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U)
6655 #define RTC_ALRMAR_ST ((uint32_t)0x00000070U)
6656 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U)
6657 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U)
6658 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U)
6659 #define RTC_ALRMAR_SU ((uint32_t)0x0000000FU)
6660 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U)
6661 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U)
6662 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U)
6663 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U)
6664
6665 /******************** Bits definition for RTC_ALRMBR register ***************/
6666 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U)
6667 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U)
6668 #define RTC_ALRMBR_DT ((uint32_t)0x30000000U)
6669 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U)
6670 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U)
6671 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000U)
6672 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U)
6673 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U)
6674 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U)
6675 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U)
6676 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U)
6677 #define RTC_ALRMBR_PM ((uint32_t)0x00400000U)
6678 #define RTC_ALRMBR_HT ((uint32_t)0x00300000U)
6679 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U)
6680 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U)
6681 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000U)
6682 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U)
6683 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U)
6684 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U)
6685 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U)
6686 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U)
6687 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000U)
6688 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U)
6689 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U)
6690 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U)
6691 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U)
6692 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U)
6693 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U)
6694 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U)
6695 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U)
6696 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U)
6697 #define RTC_ALRMBR_ST ((uint32_t)0x00000070U)
6698 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U)
6699 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U)
6700 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U)
6701 #define RTC_ALRMBR_SU ((uint32_t)0x0000000FU)
6702 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U)
6703 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U)
6704 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U)
6705 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U)
6706
6707 /******************** Bits definition for RTC_WPR register ******************/
6708 #define RTC_WPR_KEY ((uint32_t)0x000000FFU)
6709
6710 /******************** Bits definition for RTC_SSR register ******************/
6711 #define RTC_SSR_SS ((uint32_t)0x0000FFFFU)
6712
6713 /******************** Bits definition for RTC_SHIFTR register ***************/
6714 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU)
6715 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U)
6716
6717 /******************** Bits definition for RTC_TSTR register *****************/
6718 #define RTC_TSTR_PM ((uint32_t)0x00400000U)
6719 #define RTC_TSTR_HT ((uint32_t)0x00300000U)
6720 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000U)
6721 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000U)
6722 #define RTC_TSTR_HU ((uint32_t)0x000F0000U)
6723 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000U)
6724 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000U)
6725 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000U)
6726 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000U)
6727 #define RTC_TSTR_MNT ((uint32_t)0x00007000U)
6728 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U)
6729 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U)
6730 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U)
6731 #define RTC_TSTR_MNU ((uint32_t)0x00000F00U)
6732 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U)
6733 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U)
6734 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U)
6735 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U)
6736 #define RTC_TSTR_ST ((uint32_t)0x00000070U)
6737 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010U)
6738 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020U)
6739 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040U)
6740 #define RTC_TSTR_SU ((uint32_t)0x0000000FU)
6741 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001U)
6742 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002U)
6743 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004U)
6744 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008U)
6745
6746 /******************** Bits definition for RTC_TSDR register *****************/
6747 #define RTC_TSDR_WDU ((uint32_t)0x0000E000U)
6748 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U)
6749 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U)
6750 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U)
6751 #define RTC_TSDR_MT ((uint32_t)0x00001000U)
6752 #define RTC_TSDR_MU ((uint32_t)0x00000F00U)
6753 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100U)
6754 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200U)
6755 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400U)
6756 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800U)
6757 #define RTC_TSDR_DT ((uint32_t)0x00000030U)
6758 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010U)
6759 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020U)
6760 #define RTC_TSDR_DU ((uint32_t)0x0000000FU)
6761 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001U)
6762 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002U)
6763 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004U)
6764 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008U)
6765
6766 /******************** Bits definition for RTC_TSSSR register ****************/
6767 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
6768
6769 /******************** Bits definition for RTC_CAL register *****************/
6770 #define RTC_CALR_CALP ((uint32_t)0x00008000U)
6771 #define RTC_CALR_CALW8 ((uint32_t)0x00004000U)
6772 #define RTC_CALR_CALW16 ((uint32_t)0x00002000U)
6773 #define RTC_CALR_CALM ((uint32_t)0x000001FFU)
6774 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001U)
6775 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002U)
6776 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004U)
6777 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008U)
6778 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010U)
6779 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020U)
6780 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040U)
6781 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080U)
6782 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100U)
6783
6784 /******************** Bits definition for RTC_TAMPCR register ***************/
6785 #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U)
6786 #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U)
6787 #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U)
6788 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U)
6789 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U)
6790 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U)
6791 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U)
6792 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U)
6793 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U)
6794 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U)
6795 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U)
6796 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U)
6797 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U)
6798 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U)
6799 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U)
6800 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U)
6801 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U)
6802 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U)
6803 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U)
6804 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U)
6805 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U)
6806 #define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U)
6807 #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U)
6808 #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U)
6809 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U)
6810 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U)
6811 #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U)
6812 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U)
6813
6814 /******************** Bits definition for RTC_ALRMASSR register *************/
6815 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
6816 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
6817 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
6818 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
6819 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
6820 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
6821
6822 /******************** Bits definition for RTC_ALRMBSSR register *************/
6823 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
6824 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
6825 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
6826 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
6827 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
6828 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
6829
6830 /******************** Bits definition for RTC_0R register *******************/
6831 #define RTC_OR_OUT_RMP ((uint32_t)0x00000002U)
6832 #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U)
6833
6834
6835 /******************** Bits definition for RTC_BKP0R register ****************/
6836 #define RTC_BKP0R ((uint32_t)0xFFFFFFFFU)
6837
6838 /******************** Bits definition for RTC_BKP1R register ****************/
6839 #define RTC_BKP1R ((uint32_t)0xFFFFFFFFU)
6840
6841 /******************** Bits definition for RTC_BKP2R register ****************/
6842 #define RTC_BKP2R ((uint32_t)0xFFFFFFFFU)
6843
6844 /******************** Bits definition for RTC_BKP3R register ****************/
6845 #define RTC_BKP3R ((uint32_t)0xFFFFFFFFU)
6846
6847 /******************** Bits definition for RTC_BKP4R register ****************/
6848 #define RTC_BKP4R ((uint32_t)0xFFFFFFFFU)
6849
6850 /******************** Bits definition for RTC_BKP5R register ****************/
6851 #define RTC_BKP5R ((uint32_t)0xFFFFFFFFU)
6852
6853 /******************** Bits definition for RTC_BKP6R register ****************/
6854 #define RTC_BKP6R ((uint32_t)0xFFFFFFFFU)
6855
6856 /******************** Bits definition for RTC_BKP7R register ****************/
6857 #define RTC_BKP7R ((uint32_t)0xFFFFFFFFU)
6858
6859 /******************** Bits definition for RTC_BKP8R register ****************/
6860 #define RTC_BKP8R ((uint32_t)0xFFFFFFFFU)
6861
6862 /******************** Bits definition for RTC_BKP9R register ****************/
6863 #define RTC_BKP9R ((uint32_t)0xFFFFFFFFU)
6864
6865 /******************** Bits definition for RTC_BKP10R register ***************/
6866 #define RTC_BKP10R ((uint32_t)0xFFFFFFFFU)
6867
6868 /******************** Bits definition for RTC_BKP11R register ***************/
6869 #define RTC_BKP11R ((uint32_t)0xFFFFFFFFU)
6870
6871 /******************** Bits definition for RTC_BKP12R register ***************/
6872 #define RTC_BKP12R ((uint32_t)0xFFFFFFFFU)
6873
6874 /******************** Bits definition for RTC_BKP13R register ***************/
6875 #define RTC_BKP13R ((uint32_t)0xFFFFFFFFU)
6876
6877 /******************** Bits definition for RTC_BKP14R register ***************/
6878 #define RTC_BKP14R ((uint32_t)0xFFFFFFFFU)
6879
6880 /******************** Bits definition for RTC_BKP15R register ***************/
6881 #define RTC_BKP15R ((uint32_t)0xFFFFFFFFU)
6882
6883 /******************** Bits definition for RTC_BKP16R register ***************/
6884 #define RTC_BKP16R ((uint32_t)0xFFFFFFFFU)
6885
6886 /******************** Bits definition for RTC_BKP17R register ***************/
6887 #define RTC_BKP17R ((uint32_t)0xFFFFFFFFU)
6888
6889 /******************** Bits definition for RTC_BKP18R register ***************/
6890 #define RTC_BKP18R ((uint32_t)0xFFFFFFFFU)
6891
6892 /******************** Bits definition for RTC_BKP19R register ***************/
6893 #define RTC_BKP19R ((uint32_t)0xFFFFFFFFU)
6894
6895 /******************** Bits definition for RTC_BKP20R register ***************/
6896 #define RTC_BKP20R ((uint32_t)0xFFFFFFFFU)
6897
6898 /******************** Bits definition for RTC_BKP21R register ***************/
6899 #define RTC_BKP21R ((uint32_t)0xFFFFFFFFU)
6900
6901 /******************** Bits definition for RTC_BKP22R register ***************/
6902 #define RTC_BKP22R ((uint32_t)0xFFFFFFFFU)
6903
6904 /******************** Bits definition for RTC_BKP23R register ***************/
6905 #define RTC_BKP23R ((uint32_t)0xFFFFFFFFU)
6906
6907 /******************** Bits definition for RTC_BKP24R register ***************/
6908 #define RTC_BKP24R ((uint32_t)0xFFFFFFFFU)
6909
6910 /******************** Bits definition for RTC_BKP25R register ***************/
6911 #define RTC_BKP25R ((uint32_t)0xFFFFFFFFU)
6912
6913 /******************** Bits definition for RTC_BKP26R register ***************/
6914 #define RTC_BKP26R ((uint32_t)0xFFFFFFFFU)
6915
6916 /******************** Bits definition for RTC_BKP27R register ***************/
6917 #define RTC_BKP27R ((uint32_t)0xFFFFFFFFU)
6918
6919 /******************** Bits definition for RTC_BKP28R register ***************/
6920 #define RTC_BKP28R ((uint32_t)0xFFFFFFFFU)
6921
6922 /******************** Bits definition for RTC_BKP29R register ***************/
6923 #define RTC_BKP29R ((uint32_t)0xFFFFFFFFU)
6924
6925 /******************** Bits definition for RTC_BKP30R register ***************/
6926 #define RTC_BKP30R ((uint32_t)0xFFFFFFFFU)
6927
6928 /******************** Bits definition for RTC_BKP31R register ***************/
6929 #define RTC_BKP31R ((uint32_t)0xFFFFFFFFU)
6930
6931 /******************** Number of backup registers ******************************/
6932 #define RTC_BKP_NUMBER ((uint32_t)0x00000020U)
6933
6934 /******************************************************************************/
6935 /* */
6936 /* Serial Audio Interface */
6937 /* */
6938 /******************************************************************************/
6939 /******************** Bit definition for SAI_GCR register *******************/
6940 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003U) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
6941 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
6942 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
6943
6944 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030U) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
6945 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
6946 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
6947
6948 /******************* Bit definition for SAI_xCR1 register *******************/
6949 #define SAI_xCR1_MODE ((uint32_t)0x00000003U) /*!<MODE[1:0] bits (Audio Block Mode) */
6950 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
6951 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
6952
6953 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000CU) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
6954 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
6955 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
6956
6957 #define SAI_xCR1_DS ((uint32_t)0x000000E0U) /*!<DS[1:0] bits (Data Size) */
6958 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
6959 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
6960 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
6961
6962 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100U) /*!<LSB First Configuration */
6963 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200U) /*!<ClocK STRobing edge */
6964
6965 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00U) /*!<SYNCEN[1:0](SYNChronization ENable) */
6966 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
6967 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
6968
6969 #define SAI_xCR1_MONO ((uint32_t)0x00001000U) /*!<Mono mode */
6970 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000U) /*!<Output Drive */
6971 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000U) /*!<Audio Block enable */
6972 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000U) /*!<DMA enable */
6973 #define SAI_xCR1_NODIV ((uint32_t)0x00080000U) /*!<No Divider Configuration */
6974
6975 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000U) /*!<MCKDIV[3:0] (Master ClocK Divider) */
6976 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
6977 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
6978 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
6979 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000U) /*!<Bit 3 */
6980
6981 /******************* Bit definition for SAI_xCR2 register *******************/
6982 #define SAI_xCR2_FTH ((uint32_t)0x00000007U) /*!<FTH[2:0](Fifo THreshold) */
6983 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
6984 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
6985 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
6986
6987 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008U) /*!<Fifo FLUSH */
6988 #define SAI_xCR2_TRIS ((uint32_t)0x00000010U) /*!<TRIState Management on data line */
6989 #define SAI_xCR2_MUTE ((uint32_t)0x00000020U) /*!<Mute mode */
6990 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040U) /*!<Muate value */
6991
6992
6993 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80U) /*!<MUTECNT[5:0] (MUTE counter) */
6994 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
6995 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
6996 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200U) /*!<Bit 2 */
6997 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400U) /*!<Bit 3 */
6998 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800U) /*!<Bit 4 */
6999 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000U) /*!<Bit 5 */
7000
7001 #define SAI_xCR2_CPL ((uint32_t)0x00002000U) /*!<CPL mode */
7002 #define SAI_xCR2_COMP ((uint32_t)0x0000C000U) /*!<COMP[1:0] (Companding mode) */
7003 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
7004 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
7005
7006
7007 /****************** Bit definition for SAI_xFRCR register *******************/
7008 #define SAI_xFRCR_FRL ((uint32_t)0x000000FFU) /*!<FRL[7:0](Frame length) */
7009 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7010 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7011 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
7012 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
7013 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
7014 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
7015 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
7016 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
7017
7018 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00U) /*!<FRL[6:0] (Frame synchronization active level length) */
7019 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7020 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7021 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
7022 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
7023 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
7024 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000U) /*!<Bit 5 */
7025 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000U) /*!<Bit 6 */
7026
7027 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000U) /*!< Frame Synchronization Definition */
7028 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000U) /*!<Frame Synchronization POLarity */
7029 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000U) /*!<Frame Synchronization OFFset */
7030
7031 /****************** Bit definition for SAI_xSLOTR register *******************/
7032 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001FU) /*!<FRL[4:0](First Bit Offset) */
7033 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7034 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7035 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
7036 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
7037 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
7038
7039 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0U) /*!<SLOTSZ[1:0] (Slot size) */
7040 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
7041 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
7042
7043 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00U) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
7044 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7045 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7046 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
7047 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
7048
7049 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000U) /*!<SLOTEN[15:0] (Slot Enable) */
7050
7051 /******************* Bit definition for SAI_xIMR register *******************/
7052 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001U) /*!<Overrun underrun interrupt enable */
7053 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002U) /*!<Mute detection interrupt enable */
7054 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004U) /*!<Wrong Clock Configuration interrupt enable */
7055 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008U) /*!<FIFO request interrupt enable */
7056 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010U) /*!<Codec not ready interrupt enable */
7057 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020U) /*!<Anticipated frame synchronization detection interrupt enable */
7058 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040U) /*!<Late frame synchronization detection interrupt enable */
7059
7060 /******************** Bit definition for SAI_xSR register *******************/
7061 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001U) /*!<Overrun underrun */
7062 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002U) /*!<Mute detection */
7063 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004U) /*!<Wrong Clock Configuration */
7064 #define SAI_xSR_FREQ ((uint32_t)0x00000008U) /*!<FIFO request */
7065 #define SAI_xSR_CNRDY ((uint32_t)0x00000010U) /*!<Codec not ready */
7066 #define SAI_xSR_AFSDET ((uint32_t)0x00000020U) /*!<Anticipated frame synchronization detection */
7067 #define SAI_xSR_LFSDET ((uint32_t)0x00000040U) /*!<Late frame synchronization detection */
7068
7069 #define SAI_xSR_FLVL ((uint32_t)0x00070000U) /*!<FLVL[2:0] (FIFO Level Threshold) */
7070 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
7071 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
7072 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000U) /*!<Bit 2 */
7073
7074 /****************** Bit definition for SAI_xCLRFR register ******************/
7075 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001U) /*!<Clear Overrun underrun */
7076 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002U) /*!<Clear Mute detection */
7077 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004U) /*!<Clear Wrong Clock Configuration */
7078 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008U) /*!<Clear FIFO request */
7079 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010U) /*!<Clear Codec not ready */
7080 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020U) /*!<Clear Anticipated frame synchronization detection */
7081 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040U) /*!<Clear Late frame synchronization detection */
7082
7083 /****************** Bit definition for SAI_xDR register ******************/
7084 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFFU)
7085
7086 /******************************************************************************/
7087 /* */
7088 /* LCD Controller (LCD) */
7089 /* */
7090 /******************************************************************************/
7091
7092 /******************* Bit definition for LCD_CR register *********************/
7093 #define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */
7094 #define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */
7095
7096 #define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */
7097 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */
7098 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */
7099 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */
7100
7101 #define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */
7102 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */
7103 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */
7104
7105 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */
7106 #define LCD_CR_BUFEN ((uint32_t)0x00000100U) /*!< Voltage output buffer enable */
7107
7108 /******************* Bit definition for LCD_FCR register ********************/
7109 #define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */
7110 #define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */
7111 #define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */
7112
7113 #define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Pulse ON Duration) */
7114 #define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
7115 #define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
7116 #define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
7117
7118 #define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */
7119 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
7120 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
7121 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */
7122
7123 #define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */
7124 #define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
7125 #define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
7126 #define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
7127
7128 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */
7129 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
7130 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
7131 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
7132
7133 #define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */
7134 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
7135 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
7136
7137 #define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */
7138 #define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */
7139
7140 /******************* Bit definition for LCD_SR register *********************/
7141 #define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */
7142 #define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */
7143 #define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */
7144 #define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */
7145 #define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */
7146 #define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */
7147
7148 /******************* Bit definition for LCD_CLR register ********************/
7149 #define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */
7150 #define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */
7151
7152 /******************* Bit definition for LCD_RAM register ********************/
7153 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */
7154
7155 /******************************************************************************/
7156 /* */
7157 /* SDMMC Interface */
7158 /* */
7159 /******************************************************************************/
7160 /****************** Bit definition for SDMMC_POWER register ******************/
7161 #define SDMMC_POWER_PWRCTRL ((uint8_t)0x03U) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
7162 #define SDMMC_POWER_PWRCTRL_0 ((uint8_t)0x01U) /*!<Bit 0 */
7163 #define SDMMC_POWER_PWRCTRL_1 ((uint8_t)0x02U) /*!<Bit 1 */
7164
7165 /****************** Bit definition for SDMMC_CLKCR register ******************/
7166 #define SDMMC_CLKCR_CLKDIV ((uint16_t)0x00FFU) /*!<Clock divide factor */
7167 #define SDMMC_CLKCR_CLKEN ((uint16_t)0x0100U) /*!<Clock enable bit */
7168 #define SDMMC_CLKCR_PWRSAV ((uint16_t)0x0200U) /*!<Power saving configuration bit */
7169 #define SDMMC_CLKCR_BYPASS ((uint16_t)0x0400U) /*!<Clock divider bypass enable bit */
7170
7171 #define SDMMC_CLKCR_WIDBUS ((uint16_t)0x1800U) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
7172 #define SDMMC_CLKCR_WIDBUS_0 ((uint16_t)0x0800U) /*!<Bit 0 */
7173 #define SDMMC_CLKCR_WIDBUS_1 ((uint16_t)0x1000U) /*!<Bit 1 */
7174
7175 #define SDMMC_CLKCR_NEGEDGE ((uint16_t)0x2000U) /*!<SDMMC_CK dephasing selection bit */
7176 #define SDMMC_CLKCR_HWFC_EN ((uint16_t)0x4000U) /*!<HW Flow Control enable */
7177
7178 /******************* Bit definition for SDMMC_ARG register *******************/
7179 #define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFFU) /*!<Command argument */
7180
7181 /******************* Bit definition for SDMMC_CMD register *******************/
7182 #define SDMMC_CMD_CMDINDEX ((uint16_t)0x003FU) /*!<Command Index */
7183
7184 #define SDMMC_CMD_WAITRESP ((uint16_t)0x00C0U) /*!<WAITRESP[1:0] bits (Wait for response bits) */
7185 #define SDMMC_CMD_WAITRESP_0 ((uint16_t)0x0040U) /*!< Bit 0 */
7186 #define SDMMC_CMD_WAITRESP_1 ((uint16_t)0x0080U) /*!< Bit 1 */
7187
7188 #define SDMMC_CMD_WAITINT ((uint16_t)0x0100U) /*!<CPSM Waits for Interrupt Request */
7189 #define SDMMC_CMD_WAITPEND ((uint16_t)0x0200U) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
7190 #define SDMMC_CMD_CPSMEN ((uint16_t)0x0400U) /*!<Command path state machine (CPSM) Enable bit */
7191 #define SDMMC_CMD_SDIOSUSPEND ((uint16_t)0x0800U) /*!<SD I/O suspend command */
7192
7193 /***************** Bit definition for SDMMC_RESPCMD register *****************/
7194 #define SDMMC_RESPCMD_RESPCMD ((uint8_t)0x3FU) /*!<Response command index */
7195
7196 /****************** Bit definition for SDMMC_RESP0 register ******************/
7197 #define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
7198
7199 /****************** Bit definition for SDMMC_RESP1 register ******************/
7200 #define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
7201
7202 /****************** Bit definition for SDMMC_RESP2 register ******************/
7203 #define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
7204
7205 /****************** Bit definition for SDMMC_RESP3 register ******************/
7206 #define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
7207
7208 /****************** Bit definition for SDMMC_RESP4 register ******************/
7209 #define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFFU) /*!<Card Status */
7210
7211 /****************** Bit definition for SDMMC_DTIMER register *****************/
7212 #define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFFU) /*!<Data timeout period. */
7213
7214 /****************** Bit definition for SDMMC_DLEN register *******************/
7215 #define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFFU) /*!<Data length value */
7216
7217 /****************** Bit definition for SDMMC_DCTRL register ******************/
7218 #define SDMMC_DCTRL_DTEN ((uint16_t)0x0001U) /*!<Data transfer enabled bit */
7219 #define SDMMC_DCTRL_DTDIR ((uint16_t)0x0002U) /*!<Data transfer direction selection */
7220 #define SDMMC_DCTRL_DTMODE ((uint16_t)0x0004U) /*!<Data transfer mode selection */
7221 #define SDMMC_DCTRL_DMAEN ((uint16_t)0x0008U) /*!<DMA enabled bit */
7222
7223 #define SDMMC_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0U) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
7224 #define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010U) /*!<Bit 0 */
7225 #define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020U) /*!<Bit 1 */
7226 #define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040U) /*!<Bit 2 */
7227 #define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080U) /*!<Bit 3 */
7228
7229 #define SDMMC_DCTRL_RWSTART ((uint16_t)0x0100U) /*!<Read wait start */
7230 #define SDMMC_DCTRL_RWSTOP ((uint16_t)0x0200U) /*!<Read wait stop */
7231 #define SDMMC_DCTRL_RWMOD ((uint16_t)0x0400U) /*!<Read wait mode */
7232 #define SDMMC_DCTRL_SDIOEN ((uint16_t)0x0800U) /*!<SD I/O enable functions */
7233
7234 /****************** Bit definition for SDMMC_DCOUNT register *****************/
7235 #define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFFU) /*!<Data count value */
7236
7237 /****************** Bit definition for SDMMC_STA register ********************/
7238 #define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001U) /*!<Command response received (CRC check failed) */
7239 #define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002U) /*!<Data block sent/received (CRC check failed) */
7240 #define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004U) /*!<Command response timeout */
7241 #define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008U) /*!<Data timeout */
7242 #define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010U) /*!<Transmit FIFO underrun error */
7243 #define SDMMC_STA_RXOVERR ((uint32_t)0x00000020U) /*!<Received FIFO overrun error */
7244 #define SDMMC_STA_CMDREND ((uint32_t)0x00000040U) /*!<Command response received (CRC check passed) */
7245 #define SDMMC_STA_CMDSENT ((uint32_t)0x00000080U) /*!<Command sent (no response required) */
7246 #define SDMMC_STA_DATAEND ((uint32_t)0x00000100U) /*!<Data end (data counter, SDIDCOUNT, is zero) */
7247 #define SDMMC_STA_STBITERR ((uint32_t)0x00000200U) /*!<Start bit not detected on all data signals in wide bus mode */
7248 #define SDMMC_STA_DBCKEND ((uint32_t)0x00000400U) /*!<Data block sent/received (CRC check passed) */
7249 #define SDMMC_STA_CMDACT ((uint32_t)0x00000800U) /*!<Command transfer in progress */
7250 #define SDMMC_STA_TXACT ((uint32_t)0x00001000U) /*!<Data transmit in progress */
7251 #define SDMMC_STA_RXACT ((uint32_t)0x00002000U) /*!<Data receive in progress */
7252 #define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000U) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
7253 #define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000U) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
7254 #define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000U) /*!<Transmit FIFO full */
7255 #define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000U) /*!<Receive FIFO full */
7256 #define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000U) /*!<Transmit FIFO empty */
7257 #define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000U) /*!<Receive FIFO empty */
7258 #define SDMMC_STA_TXDAVL ((uint32_t)0x00100000U) /*!<Data available in transmit FIFO */
7259 #define SDMMC_STA_RXDAVL ((uint32_t)0x00200000U) /*!<Data available in receive FIFO */
7260 #define SDMMC_STA_SDIOIT ((uint32_t)0x00400000U) /*!<SDIO interrupt received */
7261
7262 /******************* Bit definition for SDMMC_ICR register *******************/
7263 #define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001U) /*!<CCRCFAIL flag clear bit */
7264 #define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002U) /*!<DCRCFAIL flag clear bit */
7265 #define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004U) /*!<CTIMEOUT flag clear bit */
7266 #define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008U) /*!<DTIMEOUT flag clear bit */
7267 #define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010U) /*!<TXUNDERR flag clear bit */
7268 #define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020U) /*!<RXOVERR flag clear bit */
7269 #define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040U) /*!<CMDREND flag clear bit */
7270 #define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080U) /*!<CMDSENT flag clear bit */
7271 #define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100U) /*!<DATAEND flag clear bit */
7272 #define SDMMC_ICR_STBITERRC ((uint32_t)0x00000200U) /*!<STBITERR flag clear bit */
7273 #define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400U) /*!<DBCKEND flag clear bit */
7274 #define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000U) /*!<SDIOIT flag clear bit */
7275
7276 /****************** Bit definition for SDMMC_MASK register *******************/
7277 #define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001U) /*!<Command CRC Fail Interrupt Enable */
7278 #define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002U) /*!<Data CRC Fail Interrupt Enable */
7279 #define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004U) /*!<Command TimeOut Interrupt Enable */
7280 #define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008U) /*!<Data TimeOut Interrupt Enable */
7281 #define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010U) /*!<Tx FIFO UnderRun Error Interrupt Enable */
7282 #define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020U) /*!<Rx FIFO OverRun Error Interrupt Enable */
7283 #define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040U) /*!<Command Response Received Interrupt Enable */
7284 #define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080U) /*!<Command Sent Interrupt Enable */
7285 #define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100U) /*!<Data End Interrupt Enable */
7286 #define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400U) /*!<Data Block End Interrupt Enable */
7287 #define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800U) /*!<CCommand Acting Interrupt Enable */
7288 #define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000U) /*!<Data Transmit Acting Interrupt Enable */
7289 #define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000U) /*!<Data receive acting interrupt enabled */
7290 #define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000U) /*!<Tx FIFO Half Empty interrupt Enable */
7291 #define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000U) /*!<Rx FIFO Half Full interrupt Enable */
7292 #define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000U) /*!<Tx FIFO Full interrupt Enable */
7293 #define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000U) /*!<Rx FIFO Full interrupt Enable */
7294 #define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000U) /*!<Tx FIFO Empty interrupt Enable */
7295 #define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000U) /*!<Rx FIFO Empty interrupt Enable */
7296 #define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000U) /*!<Data available in Tx FIFO interrupt Enable */
7297 #define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000U) /*!<Data available in Rx FIFO interrupt Enable */
7298 #define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000U) /*!<SDIO Mode Interrupt Received interrupt Enable */
7299
7300 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
7301 #define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFFU) /*!<Remaining number of words to be written to or read from the FIFO */
7302
7303 /****************** Bit definition for SDMMC_FIFO register *******************/
7304 #define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFFU) /*!<Receive and transmit FIFO data */
7305
7306 /******************************************************************************/
7307 /* */
7308 /* Serial Peripheral Interface (SPI) */
7309 /* */
7310 /******************************************************************************/
7311 /******************* Bit definition for SPI_CR1 register ********************/
7312 #define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!<Clock Phase */
7313 #define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!<Clock Polarity */
7314 #define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!<Master Selection */
7315
7316 #define SPI_CR1_BR ((uint32_t)0x00000038U) /*!<BR[2:0] bits (Baud Rate Control) */
7317 #define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
7318 #define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
7319 #define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
7320
7321 #define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!<SPI Enable */
7322 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!<Frame Format */
7323 #define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!<Internal slave select */
7324 #define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!<Software slave management */
7325 #define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!<Receive only */
7326 #define SPI_CR1_CRCL ((uint32_t)0x00000800U) /*!< CRC Length */
7327 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!<Transmit CRC next */
7328 #define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!<Hardware CRC calculation enable */
7329 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!<Output enable in bidirectional mode */
7330 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!<Bidirectional data mode enable */
7331
7332 /******************* Bit definition for SPI_CR2 register ********************/
7333 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
7334 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
7335 #define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
7336 #define SPI_CR2_NSSP ((uint32_t)0x00000008U) /*!< NSS pulse management Enable */
7337 #define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */
7338 #define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
7339 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
7340 #define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
7341 #define SPI_CR2_DS ((uint32_t)0x00000F00U) /*!< DS[3:0] Data Size */
7342 #define SPI_CR2_DS_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
7343 #define SPI_CR2_DS_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
7344 #define SPI_CR2_DS_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
7345 #define SPI_CR2_DS_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
7346 #define SPI_CR2_FRXTH ((uint32_t)0x00001000U) /*!< FIFO reception Threshold */
7347 #define SPI_CR2_LDMARX ((uint32_t)0x00002000U) /*!< Last DMA transfer for reception */
7348 #define SPI_CR2_LDMATX ((uint32_t)0x00004000U) /*!< Last DMA transfer for transmission */
7349
7350 /******************** Bit definition for SPI_SR register ********************/
7351 #define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
7352 #define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
7353 #define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
7354 #define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
7355 #define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
7356 #define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
7357 #define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
7358 #define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
7359 #define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */
7360 #define SPI_SR_FRLVL ((uint32_t)0x00000600U) /*!< FIFO Reception Level */
7361 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
7362 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
7363 #define SPI_SR_FTLVL ((uint32_t)0x00001800U) /*!< FIFO Transmission Level */
7364 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
7365 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
7366
7367 /******************** Bit definition for SPI_DR register ********************/
7368 #define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!<Data Register */
7369
7370 /******************* Bit definition for SPI_CRCPR register ******************/
7371 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!<CRC polynomial register */
7372
7373 /****************** Bit definition for SPI_RXCRCR register ******************/
7374 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!<Rx CRC Register */
7375
7376 /****************** Bit definition for SPI_TXCRCR register ******************/
7377 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!<Tx CRC Register */
7378
7379 /******************************************************************************/
7380 /* */
7381 /* QUADSPI */
7382 /* */
7383 /******************************************************************************/
7384 /***************** Bit definition for QUADSPI_CR register *******************/
7385 #define QUADSPI_CR_EN ((uint32_t)0x00000001U) /*!< Enable */
7386 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002U) /*!< Abort request */
7387 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004U) /*!< DMA Enable */
7388 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008U) /*!< Timeout Counter Enable */
7389 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010U) /*!< Sample Shift */
7390 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00U) /*!< FTHRES[3:0] FIFO Level */
7391 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000U) /*!< Transfer Error Interrupt Enable */
7392 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000U) /*!< Transfer Complete Interrupt Enable */
7393 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000U) /*!< FIFO Threshold Interrupt Enable */
7394 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000U) /*!< Status Match Interrupt Enable */
7395 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000U) /*!< TimeOut Interrupt Enable */
7396 #define QUADSPI_CR_APMS ((uint32_t)0x00400000U) /*!< Automatic Polling Mode Stop */
7397 #define QUADSPI_CR_PMM ((uint32_t)0x00800000U) /*!< Polling Match Mode */
7398 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000U) /*!< PRESCALER[7:0] Clock prescaler */
7399
7400 /***************** Bit definition for QUADSPI_DCR register ******************/
7401 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001U) /*!< Mode 0 / Mode 3 */
7402 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700U) /*!< CSHT[2:0]: ChipSelect High Time */
7403 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
7404 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
7405 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
7406 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000U) /*!< FSIZE[4:0]: Flash Size */
7407
7408 /****************** Bit definition for QUADSPI_SR register *******************/
7409 #define QUADSPI_SR_TEF ((uint32_t)0x00000001U) /*!< Transfer Error Flag */
7410 #define QUADSPI_SR_TCF ((uint32_t)0x00000002U) /*!< Transfer Complete Flag */
7411 #define QUADSPI_SR_FTF ((uint32_t)0x00000004U) /*!< FIFO Threshlod Flag */
7412 #define QUADSPI_SR_SMF ((uint32_t)0x00000008U) /*!< Status Match Flag */
7413 #define QUADSPI_SR_TOF ((uint32_t)0x00000010U) /*!< Timeout Flag */
7414 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020U) /*!< Busy */
7415 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00U) /*!< FIFO Threshlod Flag */
7416
7417 /****************** Bit definition for QUADSPI_FCR register ******************/
7418 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001U) /*!< Clear Transfer Error Flag */
7419 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002U) /*!< Clear Transfer Complete Flag */
7420 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008U) /*!< Clear Status Match Flag */
7421 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010U) /*!< Clear Timeout Flag */
7422
7423 /****************** Bit definition for QUADSPI_DLR register ******************/
7424 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFFU) /*!< DL[31:0]: Data Length */
7425
7426 /****************** Bit definition for QUADSPI_CCR register ******************/
7427 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FFU) /*!< INSTRUCTION[7:0]: Instruction */
7428 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300U) /*!< IMODE[1:0]: Instruction Mode */
7429 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
7430 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
7431 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00U) /*!< ADMODE[1:0]: Address Mode */
7432 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
7433 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
7434 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000U) /*!< ADSIZE[1:0]: Address Size */
7435 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
7436 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
7437 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000U) /*!< ABMODE[1:0]: Alternate Bytes Mode */
7438 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000U) /*!< Bit 0 */
7439 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000U) /*!< Bit 1 */
7440 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000U) /*!< ABSIZE[1:0]: Instruction Mode */
7441 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
7442 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
7443 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000U) /*!< DCYC[4:0]: Dummy Cycles */
7444 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000U) /*!< DMODE[1:0]: Data Mode */
7445 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
7446 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
7447 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000U) /*!< FMODE[1:0]: Functional Mode */
7448 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
7449 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
7450 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000U) /*!< SIOO: Send Instruction Only Once Mode */
7451 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000U) /*!< DDRM: Double Data Rate Mode */
7452
7453 /****************** Bit definition for QUADSPI_AR register *******************/
7454 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFFU) /*!< ADDRESS[31:0]: Address */
7455
7456 /****************** Bit definition for QUADSPI_ABR register ******************/
7457 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFFU) /*!< ALTERNATE[31:0]: Alternate Bytes */
7458
7459 /****************** Bit definition for QUADSPI_DR register *******************/
7460 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFFU) /*!< DATA[31:0]: Data */
7461
7462 /****************** Bit definition for QUADSPI_PSMKR register ****************/
7463 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFFU) /*!< MASK[31:0]: Status Mask */
7464
7465 /****************** Bit definition for QUADSPI_PSMAR register ****************/
7466 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFFU) /*!< MATCH[31:0]: Status Match */
7467
7468 /****************** Bit definition for QUADSPI_PIR register *****************/
7469 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFFU) /*!< INTERVAL[15:0]: Polling Interval */
7470
7471 /****************** Bit definition for QUADSPI_LPTR register *****************/
7472 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< TIMEOUT[15:0]: Timeout period */
7473
7474 /******************************************************************************/
7475 /* */
7476 /* SYSCFG */
7477 /* */
7478 /******************************************************************************/
7479 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
7480 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007U) /*!< SYSCFG_Memory Remap Config */
7481 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001U)
7482 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002U)
7483 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004U)
7484
7485 #define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100U) /*!< Flash Bank mode selection */
7486
7487
7488 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
7489 #define SYSCFG_CFGR1_FWDIS ((uint32_t)0x00000001U) /*!< FIREWALL access enable*/
7490 #define SYSCFG_CFGR1_BOOSTEN ((uint32_t)0x00000100U) /*!< I/O analog switch voltage booster enable */
7491 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000U) /*!< I2C PB6 Fast mode plus */
7492 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000U) /*!< I2C PB7 Fast mode plus */
7493 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000U) /*!< I2C PB8 Fast mode plus */
7494 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000U) /*!< I2C PB9 Fast mode plus */
7495 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000U) /*!< I2C1 Fast mode plus */
7496 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000U) /*!< I2C2 Fast mode plus */
7497 #define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x00400000U) /*!< I2C3 Fast mode plus */
7498 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000U) /*!< Invalid operation Interrupt enable */
7499 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000U) /*!< Divide-by-zero Interrupt enable */
7500 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000U) /*!< Underflow Interrupt enable */
7501 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000U) /*!< Overflow Interrupt enable */
7502 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000U) /*!< Input denormal Interrupt enable */
7503 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
7504
7505 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
7506 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x00000007U) /*!<EXTI 0 configuration */
7507 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00000070U) /*!<EXTI 1 configuration */
7508 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000700U) /*!<EXTI 2 configuration */
7509 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x00007000U) /*!<EXTI 3 configuration */
7510 /**
7511 * @brief EXTI0 configuration
7512 */
7513 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!<PA[0] pin */
7514 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!<PB[0] pin */
7515 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!<PC[0] pin */
7516 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003U) /*!<PD[0] pin */
7517 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004U) /*!<PE[0] pin */
7518 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005U) /*!<PF[0] pin */
7519 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006U) /*!<PG[0] pin */
7520 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007U) /*!<PH[0] pin */
7521
7522
7523 /**
7524 * @brief EXTI1 configuration
7525 */
7526 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!<PA[1] pin */
7527 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!<PB[1] pin */
7528 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!<PC[1] pin */
7529 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030U) /*!<PD[1] pin */
7530 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040U) /*!<PE[1] pin */
7531 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050U) /*!<PF[1] pin */
7532 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060U) /*!<PG[1] pin */
7533 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070U) /*!<PH[1] pin */
7534
7535 /**
7536 * @brief EXTI2 configuration
7537 */
7538 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!<PA[2] pin */
7539 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!<PB[2] pin */
7540 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!<PC[2] pin */
7541 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!<PD[2] pin */
7542 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400U) /*!<PE[2] pin */
7543 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500U) /*!<PF[2] pin */
7544 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600U) /*!<PG[2] pin */
7545
7546
7547 /**
7548 * @brief EXTI3 configuration
7549 */
7550 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!<PA[3] pin */
7551 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!<PB[3] pin */
7552 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!<PC[3] pin */
7553 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000U) /*!<PD[3] pin */
7554 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000U) /*!<PE[3] pin */
7555 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000U) /*!<PF[3] pin */
7556 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000U) /*!<PG[3] pin */
7557
7558
7559 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
7560 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x00000007U) /*!<EXTI 4 configuration */
7561 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00000070U) /*!<EXTI 5 configuration */
7562 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000700U) /*!<EXTI 6 configuration */
7563 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x00007000U) /*!<EXTI 7 configuration */
7564 /**
7565 * @brief EXTI4 configuration
7566 */
7567 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!<PA[4] pin */
7568 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!<PB[4] pin */
7569 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!<PC[4] pin */
7570 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003U) /*!<PD[4] pin */
7571 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004U) /*!<PE[4] pin */
7572 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005U) /*!<PF[4] pin */
7573 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006U) /*!<PG[4] pin */
7574
7575 /**
7576 * @brief EXTI5 configuration
7577 */
7578 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!<PA[5] pin */
7579 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!<PB[5] pin */
7580 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!<PC[5] pin */
7581 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030U) /*!<PD[5] pin */
7582 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040U) /*!<PE[5] pin */
7583 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050U) /*!<PF[5] pin */
7584 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060U) /*!<PG[5] pin */
7585
7586 /**
7587 * @brief EXTI6 configuration
7588 */
7589 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!<PA[6] pin */
7590 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!<PB[6] pin */
7591 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!<PC[6] pin */
7592 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300U) /*!<PD[6] pin */
7593 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400U) /*!<PE[6] pin */
7594 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500U) /*!<PF[6] pin */
7595 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600U) /*!<PG[6] pin */
7596
7597 /**
7598 * @brief EXTI7 configuration
7599 */
7600 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!<PA[7] pin */
7601 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!<PB[7] pin */
7602 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!<PC[7] pin */
7603 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000U) /*!<PD[7] pin */
7604 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000U) /*!<PE[7] pin */
7605 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000U) /*!<PF[7] pin */
7606 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000U) /*!<PG[7] pin */
7607
7608
7609 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
7610 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x00000007U) /*!<EXTI 8 configuration */
7611 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00000070U) /*!<EXTI 9 configuration */
7612 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000700U) /*!<EXTI 10 configuration */
7613 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x00007000U) /*!<EXTI 11 configuration */
7614
7615 /**
7616 * @brief EXTI8 configuration
7617 */
7618 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!<PA[8] pin */
7619 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!<PB[8] pin */
7620 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!<PC[8] pin */
7621 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003U) /*!<PD[8] pin */
7622 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004U) /*!<PE[8] pin */
7623 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005U) /*!<PF[8] pin */
7624 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006U) /*!<PG[8] pin */
7625
7626 /**
7627 * @brief EXTI9 configuration
7628 */
7629 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!<PA[9] pin */
7630 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!<PB[9] pin */
7631 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!<PC[9] pin */
7632 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030U) /*!<PD[9] pin */
7633 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040U) /*!<PE[9] pin */
7634 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050U) /*!<PF[9] pin */
7635 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060U) /*!<PG[9] pin */
7636
7637 /**
7638 * @brief EXTI10 configuration
7639 */
7640 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!<PA[10] pin */
7641 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!<PB[10] pin */
7642 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!<PC[10] pin */
7643 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300U) /*!<PD[10] pin */
7644 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400U) /*!<PE[10] pin */
7645 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500U) /*!<PF[10] pin */
7646 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600U) /*!<PG[10] pin */
7647
7648 /**
7649 * @brief EXTI11 configuration
7650 */
7651 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!<PA[11] pin */
7652 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!<PB[11] pin */
7653 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!<PC[11] pin */
7654 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000U) /*!<PD[11] pin */
7655 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000U) /*!<PE[11] pin */
7656 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000U) /*!<PF[11] pin */
7657 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000U) /*!<PG[11] pin */
7658
7659 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7660 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x00000007U) /*!<EXTI 12 configuration */
7661 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00000070U) /*!<EXTI 13 configuration */
7662 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000700U) /*!<EXTI 14 configuration */
7663 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x00007000U) /*!<EXTI 15 configuration */
7664 /**
7665 * @brief EXTI12 configuration
7666 */
7667 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!<PA[12] pin */
7668 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!<PB[12] pin */
7669 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!<PC[12] pin */
7670 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003U) /*!<PD[12] pin */
7671 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004U) /*!<PE[12] pin */
7672 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005U) /*!<PF[12] pin */
7673 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006U) /*!<PG[12] pin */
7674
7675 /**
7676 * @brief EXTI13 configuration
7677 */
7678 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!<PA[13] pin */
7679 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!<PB[13] pin */
7680 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!<PC[13] pin */
7681 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030U) /*!<PD[13] pin */
7682 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040U) /*!<PE[13] pin */
7683 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050U) /*!<PF[13] pin */
7684 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060U) /*!<PG[13] pin */
7685
7686 /**
7687 * @brief EXTI14 configuration
7688 */
7689 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!<PA[14] pin */
7690 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!<PB[14] pin */
7691 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!<PC[14] pin */
7692 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300U) /*!<PD[14] pin */
7693 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400U) /*!<PE[14] pin */
7694 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500U) /*!<PF[14] pin */
7695 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600U) /*!<PG[14] pin */
7696
7697 /**
7698 * @brief EXTI15 configuration
7699 */
7700 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!<PA[15] pin */
7701 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!<PB[15] pin */
7702 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!<PC[15] pin */
7703 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000U) /*!<PD[15] pin */
7704 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000U) /*!<PE[15] pin */
7705 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000U) /*!<PF[15] pin */
7706 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000U) /*!<PG[15] pin */
7707
7708 /****************** Bit definition for SYSCFG_SCSR register ****************/
7709 #define SYSCFG_SCSR_SRAM2ER ((uint32_t)0x00000001U) /*!< SRAM2 Erase Request */
7710 #define SYSCFG_SCSR_SRAM2BSY ((uint32_t)0x00000002U) /*!< SRAM2 Erase Ongoing */
7711
7712 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
7713 #define SYSCFG_CFGR2_CLL ((uint32_t)0x00000001U) /*!< Core Lockup Lock */
7714 #define SYSCFG_CFGR2_SPL ((uint32_t)0x00000002U) /*!< SRAM Parity Lock*/
7715 #define SYSCFG_CFGR2_PVDL ((uint32_t)0x00000004U) /*!< PVD Lock */
7716 #define SYSCFG_CFGR2_ECCL ((uint32_t)0x00000008U) /*!< ECC Lock*/
7717 #define SYSCFG_CFGR2_SPF ((uint32_t)0x00000100U) /*!< SRAM Parity Flag */
7718
7719 /****************** Bit definition for SYSCFG_SWPR register ****************/
7720 #define SYSCFG_SWPR_PAGE0 ((uint32_t)0x00000001U) /*!< SRAM2 Write protection page 0 */
7721 #define SYSCFG_SWPR_PAGE1 ((uint32_t)0x00000002U) /*!< SRAM2 Write protection page 1 */
7722 #define SYSCFG_SWPR_PAGE2 ((uint32_t)0x00000004U) /*!< SRAM2 Write protection page 2 */
7723 #define SYSCFG_SWPR_PAGE3 ((uint32_t)0x00000008U) /*!< SRAM2 Write protection page 3 */
7724 #define SYSCFG_SWPR_PAGE4 ((uint32_t)0x00000010U) /*!< SRAM2 Write protection page 4 */
7725 #define SYSCFG_SWPR_PAGE5 ((uint32_t)0x00000020U) /*!< SRAM2 Write protection page 5 */
7726 #define SYSCFG_SWPR_PAGE6 ((uint32_t)0x00000040U) /*!< SRAM2 Write protection page 6 */
7727 #define SYSCFG_SWPR_PAGE7 ((uint32_t)0x00000080U) /*!< SRAM2 Write protection page 7 */
7728 #define SYSCFG_SWPR_PAGE8 ((uint32_t)0x00000100U) /*!< SRAM2 Write protection page 8 */
7729 #define SYSCFG_SWPR_PAGE9 ((uint32_t)0x00000200U) /*!< SRAM2 Write protection page 9 */
7730 #define SYSCFG_SWPR_PAGE10 ((uint32_t)0x00000400U) /*!< SRAM2 Write protection page 10*/
7731 #define SYSCFG_SWPR_PAGE11 ((uint32_t)0x00000800U) /*!< SRAM2 Write protection page 11*/
7732 #define SYSCFG_SWPR_PAGE12 ((uint32_t)0x00001000U) /*!< SRAM2 Write protection page 12*/
7733 #define SYSCFG_SWPR_PAGE13 ((uint32_t)0x00002000U) /*!< SRAM2 Write protection page 13*/
7734 #define SYSCFG_SWPR_PAGE14 ((uint32_t)0x00004000U) /*!< SRAM2 Write protection page 14*/
7735 #define SYSCFG_SWPR_PAGE15 ((uint32_t)0x00008000U) /*!< SRAM2 Write protection page 15*/
7736 #define SYSCFG_SWPR_PAGE16 ((uint32_t)0x00010000U) /*!< SRAM2 Write protection page 16*/
7737 #define SYSCFG_SWPR_PAGE17 ((uint32_t)0x00020000U) /*!< SRAM2 Write protection page 17*/
7738 #define SYSCFG_SWPR_PAGE18 ((uint32_t)0x00040000U) /*!< SRAM2 Write protection page 18*/
7739 #define SYSCFG_SWPR_PAGE19 ((uint32_t)0x00080000U) /*!< SRAM2 Write protection page 19*/
7740 #define SYSCFG_SWPR_PAGE20 ((uint32_t)0x00100000U) /*!< SRAM2 Write protection page 20*/
7741 #define SYSCFG_SWPR_PAGE21 ((uint32_t)0x00200000U) /*!< SRAM2 Write protection page 21*/
7742 #define SYSCFG_SWPR_PAGE22 ((uint32_t)0x00400000U) /*!< SRAM2 Write protection page 22*/
7743 #define SYSCFG_SWPR_PAGE23 ((uint32_t)0x00800000U) /*!< SRAM2 Write protection page 23*/
7744 #define SYSCFG_SWPR_PAGE24 ((uint32_t)0x01000000U) /*!< SRAM2 Write protection page 24*/
7745 #define SYSCFG_SWPR_PAGE25 ((uint32_t)0x02000000U) /*!< SRAM2 Write protection page 25*/
7746 #define SYSCFG_SWPR_PAGE26 ((uint32_t)0x04000000U) /*!< SRAM2 Write protection page 26*/
7747 #define SYSCFG_SWPR_PAGE27 ((uint32_t)0x08000000U) /*!< SRAM2 Write protection page 27*/
7748 #define SYSCFG_SWPR_PAGE28 ((uint32_t)0x10000000U) /*!< SRAM2 Write protection page 28*/
7749 #define SYSCFG_SWPR_PAGE29 ((uint32_t)0x20000000U) /*!< SRAM2 Write protection page 29*/
7750 #define SYSCFG_SWPR_PAGE30 ((uint32_t)0x40000000U) /*!< SRAM2 Write protection page 30*/
7751 #define SYSCFG_SWPR_PAGE31 ((uint32_t)0x80000000U) /*!< SRAM2 Write protection page 31*/
7752
7753 /****************** Bit definition for SYSCFG_SKR register ****************/
7754 #define SYSCFG_SKR_KEY ((uint32_t)0x000000FFU) /*!< SRAM2 write protection key for software erase */
7755
7756
7757
7758
7759 /******************************************************************************/
7760 /* */
7761 /* TIM */
7762 /* */
7763 /******************************************************************************/
7764 /******************* Bit definition for TIM_CR1 register ********************/
7765 #define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
7766 #define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
7767 #define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
7768 #define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
7769 #define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
7770
7771 #define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
7772 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
7773 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
7774
7775 #define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
7776
7777 #define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
7778 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7779 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7780
7781 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800U) /*!<Update interrupt flag remap */
7782
7783 /******************* Bit definition for TIM_CR2 register ********************/
7784 #define TIM_CR2_CCPC ((uint32_t)0x00000001U) /*!<Capture/Compare Preloaded Control */
7785 #define TIM_CR2_CCUS ((uint32_t)0x00000004U) /*!<Capture/Compare Control Update Selection */
7786 #define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
7787
7788 #define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
7789 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7790 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7791 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7792
7793 #define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
7794 #define TIM_CR2_OIS1 ((uint32_t)0x00000100U) /*!<Output Idle state 1 (OC1 output) */
7795 #define TIM_CR2_OIS1N ((uint32_t)0x00000200U) /*!<Output Idle state 1 (OC1N output) */
7796 #define TIM_CR2_OIS2 ((uint32_t)0x00000400U) /*!<Output Idle state 2 (OC2 output) */
7797 #define TIM_CR2_OIS2N ((uint32_t)0x00000800U) /*!<Output Idle state 2 (OC2N output) */
7798 #define TIM_CR2_OIS3 ((uint32_t)0x00001000U) /*!<Output Idle state 3 (OC3 output) */
7799 #define TIM_CR2_OIS3N ((uint32_t)0x00002000U) /*!<Output Idle state 3 (OC3N output) */
7800 #define TIM_CR2_OIS4 ((uint32_t)0x00004000U) /*!<Output Idle state 4 (OC4 output) */
7801 #define TIM_CR2_OIS5 ((uint32_t)0x00010000U) /*!<Output Idle state 5 (OC5 output) */
7802 #define TIM_CR2_OIS6 ((uint32_t)0x00040000U) /*!<Output Idle state 6 (OC6 output) */
7803
7804 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000U) /*!<MMS[2:0] bits (Master Mode Selection) */
7805 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
7806 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
7807 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000U) /*!<Bit 2 */
7808 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000U) /*!<Bit 2 */
7809
7810 /******************* Bit definition for TIM_SMCR register *******************/
7811 #define TIM_SMCR_SMS ((uint32_t)0x00010007U) /*!<SMS[2:0] bits (Slave mode selection) */
7812 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7813 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7814 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
7815 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
7816
7817 #define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
7818
7819 #define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
7820 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7821 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7822 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7823
7824 #define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
7825
7826 #define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
7827 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7828 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7829 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
7830 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
7831
7832 #define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
7833 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7834 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7835
7836 #define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
7837 #define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
7838
7839 /******************* Bit definition for TIM_DIER register *******************/
7840 #define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
7841 #define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
7842 #define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
7843 #define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
7844 #define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
7845 #define TIM_DIER_COMIE ((uint32_t)0x00000020U) /*!<COM interrupt enable */
7846 #define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
7847 #define TIM_DIER_BIE ((uint32_t)0x00000080U) /*!<Break interrupt enable */
7848 #define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
7849 #define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
7850 #define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
7851 #define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
7852 #define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
7853 #define TIM_DIER_COMDE ((uint32_t)0x00002000U) /*!<COM DMA request enable */
7854 #define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
7855
7856 /******************** Bit definition for TIM_SR register ********************/
7857 #define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
7858 #define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
7859 #define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
7860 #define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
7861 #define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
7862 #define TIM_SR_COMIF ((uint32_t)0x00000020U) /*!<COM interrupt Flag */
7863 #define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
7864 #define TIM_SR_BIF ((uint32_t)0x00000080U) /*!<Break interrupt Flag */
7865 #define TIM_SR_B2IF ((uint32_t)0x00000100U) /*!<Break 2 interrupt Flag */
7866 #define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
7867 #define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
7868 #define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
7869 #define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
7870 #define TIM_SR_SBIF ((uint32_t)0x00002000U) /*!<System Break interrupt Flag */
7871 #define TIM_SR_CC5IF ((uint32_t)0x00010000U) /*!<Capture/Compare 5 interrupt Flag */
7872 #define TIM_SR_CC6IF ((uint32_t)0x00020000U) /*!<Capture/Compare 6 interrupt Flag */
7873
7874
7875 /******************* Bit definition for TIM_EGR register ********************/
7876 #define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
7877 #define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
7878 #define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
7879 #define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
7880 #define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
7881 #define TIM_EGR_COMG ((uint32_t)0x00000020U) /*!<Capture/Compare Control Update Generation */
7882 #define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
7883 #define TIM_EGR_BG ((uint32_t)0x00000080U) /*!<Break Generation */
7884 #define TIM_EGR_B2G ((uint32_t)0x00000100U) /*!<Break 2 Generation */
7885
7886
7887 /****************** Bit definition for TIM_CCMR1 register *******************/
7888 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7889 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7890 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7891
7892 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
7893 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
7894
7895 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7896 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7897 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7898 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7899 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
7900
7901 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1 Clear Enable */
7902
7903 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7904 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7905 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7906
7907 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
7908 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
7909
7910 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7911 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7912 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7913 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
7914 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
7915
7916 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
7917
7918 /*----------------------------------------------------------------------------*/
7919 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7920 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
7921 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
7922
7923 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7924 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7925 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7926 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7927 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
7928
7929 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7930 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
7931 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
7932
7933 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7934 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7935 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7936 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
7937 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
7938
7939 /****************** Bit definition for TIM_CCMR2 register *******************/
7940 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7941 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
7942 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
7943
7944 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
7945 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
7946
7947 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7948 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7949 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7950 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7951 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
7952
7953 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
7954
7955 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7956 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
7957 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
7958
7959 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
7960 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
7961
7962 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7963 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7964 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7965 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
7966 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
7967
7968 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
7969
7970 /*----------------------------------------------------------------------------*/
7971 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7972 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
7973 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
7974
7975 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7976 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7977 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7978 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7979 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
7980
7981 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7982 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
7983 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
7984
7985 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7986 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
7987 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
7988 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
7989 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
7990
7991 /****************** Bit definition for TIM_CCMR3 register *******************/
7992 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004U) /*!<Output Compare 5 Fast enable */
7993 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008U) /*!<Output Compare 5 Preload enable */
7994
7995 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070U) /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
7996 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
7997 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
7998 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
7999 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
8000
8001 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080U) /*!<Output Compare 5 Clear Enable */
8002
8003 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400U) /*!<Output Compare 6 Fast enable */
8004 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800U) /*!<Output Compare 6 Preload enable */
8005
8006 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000U) /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
8007 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
8008 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
8009 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
8010 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
8011
8012 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000U) /*!<Output Compare 6 Clear Enable */
8013
8014 /******************* Bit definition for TIM_CCER register *******************/
8015 #define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
8016 #define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
8017 #define TIM_CCER_CC1NE ((uint32_t)0x00000004U) /*!<Capture/Compare 1 Complementary output enable */
8018 #define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
8019 #define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
8020 #define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
8021 #define TIM_CCER_CC2NE ((uint32_t)0x00000040U) /*!<Capture/Compare 2 Complementary output enable */
8022 #define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
8023 #define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
8024 #define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
8025 #define TIM_CCER_CC3NE ((uint32_t)0x00000400U) /*!<Capture/Compare 3 Complementary output enable */
8026 #define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
8027 #define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
8028 #define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
8029 #define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
8030 #define TIM_CCER_CC5E ((uint32_t)0x00010000U) /*!<Capture/Compare 5 output enable */
8031 #define TIM_CCER_CC5P ((uint32_t)0x00020000U) /*!<Capture/Compare 5 output Polarity */
8032 #define TIM_CCER_CC6E ((uint32_t)0x00100000U) /*!<Capture/Compare 6 output enable */
8033 #define TIM_CCER_CC6P ((uint32_t)0x00200000U) /*!<Capture/Compare 6 output Polarity */
8034
8035 /******************* Bit definition for TIM_CNT register ********************/
8036 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFFU) /*!<Counter Value */
8037 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000U) /*!<Update interrupt flag copy (if UIFREMAP=1) */
8038
8039 /******************* Bit definition for TIM_PSC register ********************/
8040 #define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
8041
8042 /******************* Bit definition for TIM_ARR register ********************/
8043 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFFU) /*!<Actual auto-reload Value */
8044
8045 /******************* Bit definition for TIM_RCR register ********************/
8046 #define TIM_RCR_REP ((uint32_t)0x0000FFFFU) /*!<Repetition Counter Value */
8047
8048 /******************* Bit definition for TIM_CCR1 register *******************/
8049 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
8050
8051 /******************* Bit definition for TIM_CCR2 register *******************/
8052 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
8053
8054 /******************* Bit definition for TIM_CCR3 register *******************/
8055 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
8056
8057 /******************* Bit definition for TIM_CCR4 register *******************/
8058 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
8059
8060 /******************* Bit definition for TIM_CCR5 register *******************/
8061 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFFU) /*!<Capture/Compare 5 Value */
8062 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000U) /*!<Group Channel 5 and Channel 1 */
8063 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000U) /*!<Group Channel 5 and Channel 2 */
8064 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000U) /*!<Group Channel 5 and Channel 3 */
8065
8066 /******************* Bit definition for TIM_CCR6 register *******************/
8067 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 6 Value */
8068
8069 /******************* Bit definition for TIM_BDTR register *******************/
8070 #define TIM_BDTR_DTG ((uint32_t)0x000000FFU) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
8071 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8072 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8073 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
8074 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
8075 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
8076 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
8077 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
8078 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080U) /*!<Bit 7 */
8079
8080 #define TIM_BDTR_LOCK ((uint32_t)0x00000300U) /*!<LOCK[1:0] bits (Lock Configuration) */
8081 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
8082 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
8083
8084 #define TIM_BDTR_OSSI ((uint32_t)0x00000400U) /*!<Off-State Selection for Idle mode */
8085 #define TIM_BDTR_OSSR ((uint32_t)0x00000800U) /*!<Off-State Selection for Run mode */
8086 #define TIM_BDTR_BKE ((uint32_t)0x00001000U) /*!<Break enable for Break 1 */
8087 #define TIM_BDTR_BKP ((uint32_t)0x00002000U) /*!<Break Polarity for Break 1 */
8088 #define TIM_BDTR_AOE ((uint32_t)0x00004000U) /*!<Automatic Output enable */
8089 #define TIM_BDTR_MOE ((uint32_t)0x00008000U) /*!<Main Output enable */
8090
8091 #define TIM_BDTR_BKF ((uint32_t)0x000F0000U) /*!<Break Filter for Break 1 */
8092 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000U) /*!<Break Filter for Break 2 */
8093
8094 #define TIM_BDTR_BK2E ((uint32_t)0x01000000U) /*!<Break enable for Break 2 */
8095 #define TIM_BDTR_BK2P ((uint32_t)0x02000000U) /*!<Break Polarity for Break 2 */
8096
8097 /******************* Bit definition for TIM_DCR register ********************/
8098 #define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
8099 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8100 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8101 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
8102 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
8103 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
8104
8105 #define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
8106 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
8107 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
8108 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
8109 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
8110 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
8111
8112 /******************* Bit definition for TIM_DMAR register *******************/
8113 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
8114
8115 /******************* Bit definition for TIM1_OR1 register *******************/
8116 #define TIM1_OR1_ETR_ADC1_RMP ((uint32_t)0x00000003U) /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
8117 #define TIM1_OR1_ETR_ADC1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8118 #define TIM1_OR1_ETR_ADC1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8119
8120 #define TIM1_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000CU) /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
8121 #define TIM1_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
8122 #define TIM1_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
8123
8124 #define TIM1_OR1_TI1_RMP ((uint32_t)0x00000010U) /*!<TIM1 Input Capture 1 remap */
8125
8126 /******************* Bit definition for TIM1_OR2 register *******************/
8127 #define TIM1_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
8128 #define TIM1_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
8129 #define TIM1_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
8130 #define TIM1_OR2_BKDFBK0E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[0] enable */
8131 #define TIM1_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
8132 #define TIM1_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
8133 #define TIM1_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
8134
8135 #define TIM1_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
8136 #define TIM1_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
8137 #define TIM1_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
8138 #define TIM1_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
8139
8140 /******************* Bit definition for TIM1_OR3 register *******************/
8141 #define TIM1_OR3_BK2INE ((uint32_t)0x00000001U) /*!<BRK2 BKIN2 input enable */
8142 #define TIM1_OR3_BK2CMP1E ((uint32_t)0x00000002U) /*!<BRK2 COMP1 enable */
8143 #define TIM1_OR3_BK2CMP2E ((uint32_t)0x00000004U) /*!<BRK2 COMP2 enable */
8144 #define TIM1_OR3_BK2DFBK1E ((uint32_t)0x00000100U) /*!<BRK2 DFSDM_BREAK[1] enable */
8145 #define TIM1_OR3_BK2INP ((uint32_t)0x00000200U) /*!<BRK2 BKIN2 input polarity */
8146 #define TIM1_OR3_BK2CMP1P ((uint32_t)0x00000400U) /*!<BRK2 COMP1 input polarity */
8147 #define TIM1_OR3_BK2CMP2P ((uint32_t)0x00000800U) /*!<BRK2 COMP2 input polarity */
8148
8149 /******************* Bit definition for TIM8_OR1 register *******************/
8150 #define TIM8_OR1_ETR_ADC2_RMP ((uint32_t)0x00000003U) /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
8151 #define TIM8_OR1_ETR_ADC2_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8152 #define TIM8_OR1_ETR_ADC2_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8153
8154 #define TIM8_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000CU) /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
8155 #define TIM8_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
8156 #define TIM8_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
8157
8158 #define TIM8_OR1_TI1_RMP ((uint32_t)0x00000010U) /*!<TIM8 Input Capture 1 remap */
8159
8160 /******************* Bit definition for TIM8_OR2 register *******************/
8161 #define TIM8_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
8162 #define TIM8_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
8163 #define TIM8_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
8164 #define TIM8_OR2_BKDFBK2E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[2] enable */
8165 #define TIM8_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
8166 #define TIM8_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
8167 #define TIM8_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
8168
8169 #define TIM8_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
8170 #define TIM8_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
8171 #define TIM8_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
8172 #define TIM8_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
8173
8174 /******************* Bit definition for TIM8_OR3 register *******************/
8175 #define TIM8_OR3_BK2INE ((uint32_t)0x00000001U) /*!<BRK2 BKIN2 input enable */
8176 #define TIM8_OR3_BK2CMP1E ((uint32_t)0x00000002U) /*!<BRK2 COMP1 enable */
8177 #define TIM8_OR3_BK2CMP2E ((uint32_t)0x00000004U) /*!<BRK2 COMP2 enable */
8178 #define TIM8_OR3_BK2DFBK3E ((uint32_t)0x00000100U) /*!<BRK2 DFSDM_BREAK[3] enable */
8179 #define TIM8_OR3_BK2INP ((uint32_t)0x00000200U) /*!<BRK2 BKIN2 input polarity */
8180 #define TIM8_OR3_BK2CMP1P ((uint32_t)0x00000400U) /*!<BRK2 COMP1 input polarity */
8181 #define TIM8_OR3_BK2CMP2P ((uint32_t)0x00000800U) /*!<BRK2 COMP2 input polarity */
8182
8183 /******************* Bit definition for TIM2_OR1 register *******************/
8184 #define TIM2_OR1_ITR1_RMP ((uint32_t)0x00000001U) /*!<TIM2 Internal trigger 1 remap */
8185 #define TIM2_OR1_ETR1_RMP ((uint32_t)0x00000002U) /*!<TIM2 External trigger 1 remap */
8186
8187 #define TIM2_OR1_TI4_RMP ((uint32_t)0x0000000CU) /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
8188 #define TIM2_OR1_TI4_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
8189 #define TIM2_OR1_TI4_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
8190
8191 /******************* Bit definition for TIM2_OR2 register *******************/
8192 #define TIM2_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
8193 #define TIM2_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
8194 #define TIM2_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
8195 #define TIM2_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
8196
8197 /******************* Bit definition for TIM3_OR1 register *******************/
8198 #define TIM3_OR1_TI1_RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
8199 #define TIM3_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8200 #define TIM3_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8201
8202 /******************* Bit definition for TIM3_OR2 register *******************/
8203 #define TIM3_OR2_ETRSEL ((uint32_t)0x0001C000U) /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
8204 #define TIM3_OR2_ETRSEL_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
8205 #define TIM3_OR2_ETRSEL_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
8206 #define TIM3_OR2_ETRSEL_2 ((uint32_t)0x00010000U) /*!<Bit 2 */
8207
8208 /******************* Bit definition for TIM15_OR1 register ******************/
8209 #define TIM15_OR1_TI1_RMP ((uint32_t)0x00000001U) /*!<TIM15 Input Capture 1 remap */
8210
8211 #define TIM15_OR1_ENCODER_MODE ((uint32_t)0x00000006U) /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
8212 #define TIM15_OR1_ENCODER_MODE_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
8213 #define TIM15_OR1_ENCODER_MODE_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
8214
8215 /******************* Bit definition for TIM15_OR2 register ******************/
8216 #define TIM15_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
8217 #define TIM15_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
8218 #define TIM15_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
8219 #define TIM15_OR2_BKDFBK0E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[0] enable */
8220 #define TIM15_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
8221 #define TIM15_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
8222 #define TIM15_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
8223
8224 /******************* Bit definition for TIM16_OR1 register ******************/
8225 #define TIM16_OR1_TI1_RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
8226 #define TIM16_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8227 #define TIM16_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8228
8229 /******************* Bit definition for TIM16_OR2 register ******************/
8230 #define TIM16_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
8231 #define TIM16_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
8232 #define TIM16_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
8233 #define TIM16_OR2_BKDFBK1E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[1] enable */
8234 #define TIM16_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
8235 #define TIM16_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
8236 #define TIM16_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
8237
8238 /******************* Bit definition for TIM17_OR1 register ******************/
8239 #define TIM17_OR1_TI1_RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
8240 #define TIM17_OR1_TI1_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8241 #define TIM17_OR1_TI1_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8242
8243 /******************* Bit definition for TIM17_OR2 register ******************/
8244 #define TIM17_OR2_BKINE ((uint32_t)0x00000001U) /*!<BRK BKIN input enable */
8245 #define TIM17_OR2_BKCMP1E ((uint32_t)0x00000002U) /*!<BRK COMP1 enable */
8246 #define TIM17_OR2_BKCMP2E ((uint32_t)0x00000004U) /*!<BRK COMP2 enable */
8247 #define TIM17_OR2_BKDFBK2E ((uint32_t)0x00000100U) /*!<BRK DFSDM_BREAK[2] enable */
8248 #define TIM17_OR2_BKINP ((uint32_t)0x00000200U) /*!<BRK BKIN input polarity */
8249 #define TIM17_OR2_BKCMP1P ((uint32_t)0x00000400U) /*!<BRK COMP1 input polarity */
8250 #define TIM17_OR2_BKCMP2P ((uint32_t)0x00000800U) /*!<BRK COMP2 input polarity */
8251
8252 /******************************************************************************/
8253 /* */
8254 /* Low Power Timer (LPTTIM) */
8255 /* */
8256 /******************************************************************************/
8257 /****************** Bit definition for LPTIM_ISR register *******************/
8258 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */
8259 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */
8260 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */
8261 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */
8262 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */
8263 #define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */
8264 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */
8265
8266 /****************** Bit definition for LPTIM_ICR register *******************/
8267 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */
8268 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */
8269 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */
8270 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */
8271 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */
8272 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */
8273 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */
8274
8275 /****************** Bit definition for LPTIM_IER register ********************/
8276 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */
8277 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */
8278 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */
8279 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */
8280 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */
8281 #define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */
8282 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */
8283
8284 /****************** Bit definition for LPTIM_CFGR register *******************/
8285 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */
8286
8287 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */
8288 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
8289 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
8290
8291 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
8292 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
8293 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
8294
8295 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
8296 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
8297 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
8298
8299 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */
8300 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
8301 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
8302 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
8303
8304 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
8305 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
8306 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
8307 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
8308
8309 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
8310 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
8311 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
8312
8313 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */
8314 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */
8315 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */
8316 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */
8317 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */
8318 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */
8319
8320 /****************** Bit definition for LPTIM_CR register ********************/
8321 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */
8322 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */
8323 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */
8324
8325 /****************** Bit definition for LPTIM_CMP register *******************/
8326 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */
8327
8328 /****************** Bit definition for LPTIM_ARR register *******************/
8329 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */
8330
8331 /****************** Bit definition for LPTIM_CNT register *******************/
8332 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */
8333
8334 /****************** Bit definition for LPTIM_OR register *******************/
8335 #define LPTIM_OR_OR ((uint32_t)0x00000003U) /*!< LPTIMER[1:0] bits (Remap selection) */
8336 #define LPTIM_OR_OR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
8337 #define LPTIM_OR_OR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
8338
8339 /******************************************************************************/
8340 /* */
8341 /* Analog Comparators (COMP) */
8342 /* */
8343 /******************************************************************************/
8344 /********************** Bit definition for COMPx_CSR register ***************/
8345 #define COMP_CSR_EN ((uint32_t)0x00000001U) /*!< COMPx enable */
8346
8347 #define COMP_CSR_PWRMODE ((uint32_t)0x0000000CU) /*!< COMPx power mode */
8348 #define COMP_CSR_PWRMODE_0 ((uint32_t)0x00000004U) /*!< COMPx power mode bit 0 */
8349 #define COMP_CSR_PWRMODE_1 ((uint32_t)0x00000008U) /*!< COMPx power mode bit 1 */
8350
8351 #define COMP_CSR_INMSEL ((uint32_t)0x00000070U) /*!< COMPx inverting input (minus) selection */
8352 #define COMP_CSR_INMSEL_0 ((uint32_t)0x00000010U) /*!< COMPx inverting input (minus) selection bit 0 */
8353 #define COMP_CSR_INMSEL_1 ((uint32_t)0x00000020U) /*!< COMPx inverting input (minus) selection bit 1 */
8354 #define COMP_CSR_INMSEL_2 ((uint32_t)0x00000040U) /*!< COMPx inverting input (minus) selection bit 2 */
8355
8356 #define COMP_CSR_INPSEL ((uint32_t)0x00000080U) /*!< COMPx non inverting input (plus) selection */
8357 #define COMP_CSR_INPSEL_0 ((uint32_t)0x00000080U) /*!< COMPx non inverting input (plus) selection bit 0*/
8358 #define COMP_CSR_WINMODE ((uint32_t)0x00000200U) /*!< COMPx window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
8359 #define COMP_CSR_POLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */
8360
8361 #define COMP_CSR_HYST ((uint32_t)0x00030000U) /*!< COMPx hysteresis */
8362 #define COMP_CSR_HYST_0 ((uint32_t)0x00010000U) /*!< COMPx hysteresis bit 0 */
8363 #define COMP_CSR_HYST_1 ((uint32_t)0x00020000U) /*!< COMPx hysteresis bit 1 */
8364
8365 #define COMP_CSR_BLANKING ((uint32_t)0x001C0000U) /*!< COMPx blanking source */
8366 #define COMP_CSR_BLANKING_0 ((uint32_t)0x00040000U) /*!< COMPx blanking source bit 0 */
8367 #define COMP_CSR_BLANKING_1 ((uint32_t)0x00080000U) /*!< COMPx blanking source bit 1 */
8368 #define COMP_CSR_BLANKING_2 ((uint32_t)0x00100000U) /*!< COMPx blanking source bit 2 */
8369
8370 #define COMP_CSR_BRGEN ((uint32_t)0x00400000U) /*!< COMPx voltage scaler enable */
8371 #define COMP_CSR_SCALEN ((uint32_t)0x00800000U) /*!< COMPx scaler bridge enable */
8372 #define COMP_CSR_VALUE ((uint32_t)0x40000000U) /*!< COMPx value */
8373 #define COMP_CSR_LOCK ((uint32_t)0x80000000U) /*!< COMPx lock */
8374
8375 /******************************************************************************/
8376 /* */
8377 /* Operational Amplifier (OPAMP) */
8378 /* */
8379 /******************************************************************************/
8380 /********************* Bit definition for OPAMPx_CSR register ***************/
8381 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001U) /*!< OPAMP enable */
8382 #define OPAMP_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier Low Power Mode */
8383
8384 #define OPAMP_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier PGA mode */
8385 #define OPAMP_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
8386 #define OPAMP_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
8387
8388 #define OPAMP_CSR_PGGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier Programmable amplifier gain value */
8389 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
8390 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
8391
8392 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
8393 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
8394 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
8395
8396 #define OPAMP_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
8397 #define OPAMP_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
8398 #define OPAMP_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
8399 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
8400 #define OPAMP_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
8401
8402 /********************* Bit definition for OPAMP1_CSR register ***************/
8403 #define OPAMP1_CSR_OPAEN ((uint32_t)0x00000001U) /*!< Operational amplifier1 Enable */
8404 #define OPAMP1_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier1 Low Power Mode */
8405
8406 #define OPAMP1_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier1 PGA mode */
8407 #define OPAMP1_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
8408 #define OPAMP1_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
8409
8410 #define OPAMP1_CSR_PGAGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier1 Programmable amplifier gain value */
8411 #define OPAMP1_CSR_PGAGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
8412 #define OPAMP1_CSR_PGAGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
8413
8414 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
8415 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
8416 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
8417
8418 #define OPAMP1_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
8419 #define OPAMP1_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
8420 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
8421 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
8422 #define OPAMP1_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier1 calibration output */
8423 #define OPAMP1_CSR_OPARANGE ((uint32_t)0x80000000U) /*!< Operational amplifiers power supply range for stability */
8424
8425 /********************* Bit definition for OPAMP2_CSR register ***************/
8426 #define OPAMP2_CSR_OPAEN ((uint32_t)0x00000001U) /*!< Operational amplifier2 Enable */
8427 #define OPAMP2_CSR_OPALPM ((uint32_t)0x00000002U) /*!< Operational amplifier2 Low Power Mode */
8428
8429 #define OPAMP2_CSR_OPAMODE ((uint32_t)0x0000000CU) /*!< Operational amplifier2 PGA mode */
8430 #define OPAMP2_CSR_OPAMODE_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
8431 #define OPAMP2_CSR_OPAMODE_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
8432
8433 #define OPAMP2_CSR_PGAGAIN ((uint32_t)0x00000030U) /*!< Operational amplifier2 Programmable amplifier gain value */
8434 #define OPAMP2_CSR_PGAGAIN_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
8435 #define OPAMP2_CSR_PGAGAIN_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
8436
8437 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000300U) /*!< Inverting input selection */
8438 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
8439 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
8440
8441 #define OPAMP2_CSR_VPSEL ((uint32_t)0x00000400U) /*!< Non inverted input selection */
8442 #define OPAMP2_CSR_CALON ((uint32_t)0x00001000U) /*!< Calibration mode enable */
8443 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00002000U) /*!< Calibration selection */
8444 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00004000U) /*!< User trimming enable */
8445 #define OPAMP2_CSR_CALOUT ((uint32_t)0x00008000U) /*!< Operational amplifier2 calibration output */
8446
8447 /******************* Bit definition for OPAMP_OTR register ******************/
8448 #define OPAMP_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8449 #define OPAMP_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8450
8451 /******************* Bit definition for OPAMP1_OTR register ******************/
8452 #define OPAMP1_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8453 #define OPAMP1_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8454
8455 /******************* Bit definition for OPAMP2_OTR register ******************/
8456 #define OPAMP2_OTR_TRIMOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8457 #define OPAMP2_OTR_TRIMOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8458
8459 /******************* Bit definition for OPAMP_LPOTR register ****************/
8460 #define OPAMP_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8461 #define OPAMP_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8462
8463 /******************* Bit definition for OPAMP1_LPOTR register ****************/
8464 #define OPAMP1_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8465 #define OPAMP1_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8466
8467 /******************* Bit definition for OPAMP2_LPOTR register ****************/
8468 #define OPAMP2_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001FU) /*!< Trim for NMOS differential pairs */
8469 #define OPAMP2_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00U) /*!< Trim for PMOS differential pairs */
8470
8471 /******************************************************************************/
8472 /* */
8473 /* Touch Sensing Controller (TSC) */
8474 /* */
8475 /******************************************************************************/
8476 /******************* Bit definition for TSC_CR register *********************/
8477 #define TSC_CR_TSCE ((uint32_t)0x00000001U) /*!<Touch sensing controller enable */
8478 #define TSC_CR_START ((uint32_t)0x00000002U) /*!<Start acquisition */
8479 #define TSC_CR_AM ((uint32_t)0x00000004U) /*!<Acquisition mode */
8480 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /*!<Synchronization pin polarity */
8481 #define TSC_CR_IODEF ((uint32_t)0x00000010U) /*!<IO default mode */
8482
8483 #define TSC_CR_MCV ((uint32_t)0x000000E0U) /*!<MCV[2:0] bits (Max Count Value) */
8484 #define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
8485 #define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
8486 #define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
8487
8488 #define TSC_CR_PGPSC ((uint32_t)0x00007000U) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
8489 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
8490 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
8491 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
8492
8493 #define TSC_CR_SSPSC ((uint32_t)0x00008000U) /*!<Spread Spectrum Prescaler */
8494 #define TSC_CR_SSE ((uint32_t)0x00010000U) /*!<Spread Spectrum Enable */
8495
8496 #define TSC_CR_SSD ((uint32_t)0x00FE0000U) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
8497 #define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
8498 #define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
8499 #define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
8500 #define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
8501 #define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
8502 #define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
8503 #define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
8504
8505 #define TSC_CR_CTPL ((uint32_t)0x0F000000U) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
8506 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
8507 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
8508 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
8509 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
8510
8511 #define TSC_CR_CTPH ((uint32_t)0xF0000000U) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
8512 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
8513 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
8514 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
8515 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /*!<Bit 3 */
8516
8517 /******************* Bit definition for TSC_IER register ********************/
8518 #define TSC_IER_EOAIE ((uint32_t)0x00000001U) /*!<End of acquisition interrupt enable */
8519 #define TSC_IER_MCEIE ((uint32_t)0x00000002U) /*!<Max count error interrupt enable */
8520
8521 /******************* Bit definition for TSC_ICR register ********************/
8522 #define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /*!<End of acquisition interrupt clear */
8523 #define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /*!<Max count error interrupt clear */
8524
8525 /******************* Bit definition for TSC_ISR register ********************/
8526 #define TSC_ISR_EOAF ((uint32_t)0x00000001U) /*!<End of acquisition flag */
8527 #define TSC_ISR_MCEF ((uint32_t)0x00000002U) /*!<Max count error flag */
8528
8529 /******************* Bit definition for TSC_IOHCR register ******************/
8530 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
8531 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
8532 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
8533 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
8534 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
8535 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
8536 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
8537 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
8538 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
8539 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
8540 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
8541 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
8542 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
8543 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
8544 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
8545 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
8546 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
8547 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
8548 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
8549 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
8550 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
8551 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
8552 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
8553 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
8554 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
8555 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
8556 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
8557 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
8558 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
8559 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
8560 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
8561 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
8562
8563 /******************* Bit definition for TSC_IOASCR register *****************/
8564 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 analog switch enable */
8565 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 analog switch enable */
8566 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 analog switch enable */
8567 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 analog switch enable */
8568 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 analog switch enable */
8569 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 analog switch enable */
8570 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 analog switch enable */
8571 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 analog switch enable */
8572 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 analog switch enable */
8573 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 analog switch enable */
8574 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 analog switch enable */
8575 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 analog switch enable */
8576 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 analog switch enable */
8577 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 analog switch enable */
8578 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 analog switch enable */
8579 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 analog switch enable */
8580 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 analog switch enable */
8581 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 analog switch enable */
8582 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 analog switch enable */
8583 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 analog switch enable */
8584 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 analog switch enable */
8585 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 analog switch enable */
8586 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 analog switch enable */
8587 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 analog switch enable */
8588 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 analog switch enable */
8589 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 analog switch enable */
8590 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 analog switch enable */
8591 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 analog switch enable */
8592 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 analog switch enable */
8593 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 analog switch enable */
8594 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 analog switch enable */
8595 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 analog switch enable */
8596
8597 /******************* Bit definition for TSC_IOSCR register ******************/
8598 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 sampling mode */
8599 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 sampling mode */
8600 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 sampling mode */
8601 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 sampling mode */
8602 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 sampling mode */
8603 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 sampling mode */
8604 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 sampling mode */
8605 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 sampling mode */
8606 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 sampling mode */
8607 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 sampling mode */
8608 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 sampling mode */
8609 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 sampling mode */
8610 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 sampling mode */
8611 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 sampling mode */
8612 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 sampling mode */
8613 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 sampling mode */
8614 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 sampling mode */
8615 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 sampling mode */
8616 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 sampling mode */
8617 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 sampling mode */
8618 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 sampling mode */
8619 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 sampling mode */
8620 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 sampling mode */
8621 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 sampling mode */
8622 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 sampling mode */
8623 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 sampling mode */
8624 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 sampling mode */
8625 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 sampling mode */
8626 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 sampling mode */
8627 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 sampling mode */
8628 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 sampling mode */
8629 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 sampling mode */
8630
8631 /******************* Bit definition for TSC_IOCCR register ******************/
8632 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 channel mode */
8633 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 channel mode */
8634 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 channel mode */
8635 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 channel mode */
8636 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 channel mode */
8637 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 channel mode */
8638 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 channel mode */
8639 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 channel mode */
8640 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 channel mode */
8641 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 channel mode */
8642 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 channel mode */
8643 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 channel mode */
8644 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 channel mode */
8645 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 channel mode */
8646 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 channel mode */
8647 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 channel mode */
8648 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 channel mode */
8649 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 channel mode */
8650 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 channel mode */
8651 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 channel mode */
8652 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 channel mode */
8653 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 channel mode */
8654 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 channel mode */
8655 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 channel mode */
8656 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 channel mode */
8657 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 channel mode */
8658 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 channel mode */
8659 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 channel mode */
8660 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 channel mode */
8661 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 channel mode */
8662 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 channel mode */
8663 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 channel mode */
8664
8665 /******************* Bit definition for TSC_IOGCSR register *****************/
8666 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /*!<Analog IO GROUP1 enable */
8667 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /*!<Analog IO GROUP2 enable */
8668 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /*!<Analog IO GROUP3 enable */
8669 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /*!<Analog IO GROUP4 enable */
8670 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /*!<Analog IO GROUP5 enable */
8671 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /*!<Analog IO GROUP6 enable */
8672 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /*!<Analog IO GROUP7 enable */
8673 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080U) /*!<Analog IO GROUP8 enable */
8674 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /*!<Analog IO GROUP1 status */
8675 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /*!<Analog IO GROUP2 status */
8676 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /*!<Analog IO GROUP3 status */
8677 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /*!<Analog IO GROUP4 status */
8678 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /*!<Analog IO GROUP5 status */
8679 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /*!<Analog IO GROUP6 status */
8680 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /*!<Analog IO GROUP7 status */
8681 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000U) /*!<Analog IO GROUP8 status */
8682
8683 /******************* Bit definition for TSC_IOGXCR register *****************/
8684 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /*!<CNT[13:0] bits (Counter value) */
8685
8686 /******************************************************************************/
8687 /* */
8688 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
8689 /* */
8690 /******************************************************************************/
8691 /****************** Bit definition for USART_CR1 register *******************/
8692 #define USART_CR1_UE ((uint32_t)0x00000001U) /*!< USART Enable */
8693 #define USART_CR1_UESM ((uint32_t)0x00000002U) /*!< USART Enable in STOP Mode */
8694 #define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
8695 #define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
8696 #define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
8697 #define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
8698 #define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
8699 #define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< TXE Interrupt Enable */
8700 #define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
8701 #define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
8702 #define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
8703 #define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Receiver Wakeup method */
8704 #define USART_CR1_M ((uint32_t)0x10001000U) /*!< Word length */
8705 #define USART_CR1_M0 ((uint32_t)0x00001000U) /*!< Word length - Bit 0 */
8706 #define USART_CR1_MME ((uint32_t)0x00002000U) /*!< Mute Mode Enable */
8707 #define USART_CR1_CMIE ((uint32_t)0x00004000U) /*!< Character match interrupt enable */
8708 #define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit or 16-bit mode */
8709 #define USART_CR1_DEDT ((uint32_t)0x001F0000U) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
8710 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
8711 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
8712 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
8713 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
8714 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
8715 #define USART_CR1_DEAT ((uint32_t)0x03E00000U) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
8716 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
8717 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
8718 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
8719 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /*!< Bit 3 */
8720 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /*!< Bit 4 */
8721 #define USART_CR1_RTOIE ((uint32_t)0x04000000U) /*!< Receive Time Out interrupt enable */
8722 #define USART_CR1_EOBIE ((uint32_t)0x08000000U) /*!< End of Block interrupt enable */
8723 #define USART_CR1_M1 ((uint32_t)0x10000000U) /*!< Word length - Bit 1 */
8724
8725 /****************** Bit definition for USART_CR2 register *******************/
8726 #define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /*!< 7-bit or 4-bit Address Detection */
8727 #define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
8728 #define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
8729 #define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
8730 #define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
8731 #define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
8732 #define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
8733 #define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
8734 #define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
8735 #define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
8736 #define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
8737 #define USART_CR2_SWAP ((uint32_t)0x00008000U) /*!< SWAP TX/RX pins */
8738 #define USART_CR2_RXINV ((uint32_t)0x00010000U) /*!< RX pin active level inversion */
8739 #define USART_CR2_TXINV ((uint32_t)0x00020000U) /*!< TX pin active level inversion */
8740 #define USART_CR2_DATAINV ((uint32_t)0x00040000U) /*!< Binary data inversion */
8741 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /*!< Most Significant Bit First */
8742 #define USART_CR2_ABREN ((uint32_t)0x00100000U) /*!< Auto Baud-Rate Enable*/
8743 #define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
8744 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
8745 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
8746 #define USART_CR2_RTOEN ((uint32_t)0x00800000U) /*!< Receiver Time-Out enable */
8747 #define USART_CR2_ADD ((uint32_t)0xFF000000U) /*!< Address of the USART node */
8748
8749 /****************** Bit definition for USART_CR3 register *******************/
8750 #define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
8751 #define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
8752 #define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
8753 #define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
8754 #define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< SmartCard NACK enable */
8755 #define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< SmartCard mode enable */
8756 #define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
8757 #define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
8758 #define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
8759 #define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
8760 #define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
8761 #define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
8762 #define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /*!< Overrun Disable */
8763 #define USART_CR3_DDRE ((uint32_t)0x00002000U) /*!< DMA Disable on Reception Error */
8764 #define USART_CR3_DEM ((uint32_t)0x00004000U) /*!< Driver Enable Mode */
8765 #define USART_CR3_DEP ((uint32_t)0x00008000U) /*!< Driver Enable Polarity Selection */
8766 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
8767 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
8768 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
8769 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /*!< Bit 2 */
8770 #define USART_CR3_WUS ((uint32_t)0x00300000U) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
8771 #define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
8772 #define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
8773 #define USART_CR3_WUFIE ((uint32_t)0x00400000U) /*!< Wake Up Interrupt Enable */
8774
8775 /****************** Bit definition for USART_BRR register *******************/
8776 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000FU) /*!< Fraction of USARTDIV */
8777 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0U) /*!< Mantissa of USARTDIV */
8778
8779 /****************** Bit definition for USART_GTPR register ******************/
8780 #define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
8781 #define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< GT[7:0] bits (Guard time value) */
8782
8783
8784 /******************* Bit definition for USART_RTOR register *****************/
8785 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /*!< Receiver Time Out Value */
8786 #define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /*!< Block Length */
8787
8788 /******************* Bit definition for USART_RQR register ******************/
8789 #define USART_RQR_ABRRQ ((uint16_t)0x0001U) /*!< Auto-Baud Rate Request */
8790 #define USART_RQR_SBKRQ ((uint16_t)0x0002U) /*!< Send Break Request */
8791 #define USART_RQR_MMRQ ((uint16_t)0x0004U) /*!< Mute Mode Request */
8792 #define USART_RQR_RXFRQ ((uint16_t)0x0008U) /*!< Receive Data flush Request */
8793 #define USART_RQR_TXFRQ ((uint16_t)0x0010U) /*!< Transmit data flush Request */
8794
8795 /******************* Bit definition for USART_ISR register ******************/
8796 #define USART_ISR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
8797 #define USART_ISR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
8798 #define USART_ISR_NE ((uint32_t)0x00000004U) /*!< Noise detected Flag */
8799 #define USART_ISR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
8800 #define USART_ISR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
8801 #define USART_ISR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
8802 #define USART_ISR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
8803 #define USART_ISR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
8804 #define USART_ISR_LBDF ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
8805 #define USART_ISR_CTSIF ((uint32_t)0x00000200U) /*!< CTS interrupt flag */
8806 #define USART_ISR_CTS ((uint32_t)0x00000400U) /*!< CTS flag */
8807 #define USART_ISR_RTOF ((uint32_t)0x00000800U) /*!< Receiver Time Out */
8808 #define USART_ISR_EOBF ((uint32_t)0x00001000U) /*!< End Of Block Flag */
8809 #define USART_ISR_ABRE ((uint32_t)0x00004000U) /*!< Auto-Baud Rate Error */
8810 #define USART_ISR_ABRF ((uint32_t)0x00008000U) /*!< Auto-Baud Rate Flag */
8811 #define USART_ISR_BUSY ((uint32_t)0x00010000U) /*!< Busy Flag */
8812 #define USART_ISR_CMF ((uint32_t)0x00020000U) /*!< Character Match Flag */
8813 #define USART_ISR_SBKF ((uint32_t)0x00040000U) /*!< Send Break Flag */
8814 #define USART_ISR_RWU ((uint32_t)0x00080000U) /*!< Receive Wake Up from mute mode Flag */
8815 #define USART_ISR_WUF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Flag */
8816 #define USART_ISR_TEACK ((uint32_t)0x00200000U) /*!< Transmit Enable Acknowledge Flag */
8817 #define USART_ISR_REACK ((uint32_t)0x00400000U) /*!< Receive Enable Acknowledge Flag */
8818
8819 /******************* Bit definition for USART_ICR register ******************/
8820 #define USART_ICR_PECF ((uint32_t)0x00000001U) /*!< Parity Error Clear Flag */
8821 #define USART_ICR_FECF ((uint32_t)0x00000002U) /*!< Framing Error Clear Flag */
8822 #define USART_ICR_NCF ((uint32_t)0x00000004U) /*!< Noise detected Clear Flag */
8823 #define USART_ICR_ORECF ((uint32_t)0x00000008U) /*!< OverRun Error Clear Flag */
8824 #define USART_ICR_IDLECF ((uint32_t)0x00000010U) /*!< IDLE line detected Clear Flag */
8825 #define USART_ICR_TCCF ((uint32_t)0x00000040U) /*!< Transmission Complete Clear Flag */
8826 #define USART_ICR_LBDCF ((uint32_t)0x00000100U) /*!< LIN Break Detection Clear Flag */
8827 #define USART_ICR_CTSCF ((uint32_t)0x00000200U) /*!< CTS Interrupt Clear Flag */
8828 #define USART_ICR_RTOCF ((uint32_t)0x00000800U) /*!< Receiver Time Out Clear Flag */
8829 #define USART_ICR_EOBCF ((uint32_t)0x00001000U) /*!< End Of Block Clear Flag */
8830 #define USART_ICR_CMCF ((uint32_t)0x00020000U) /*!< Character Match Clear Flag */
8831 #define USART_ICR_WUCF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Clear Flag */
8832
8833 /******************* Bit definition for USART_RDR register ******************/
8834 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
8835
8836 /******************* Bit definition for USART_TDR register ******************/
8837 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
8838
8839 /******************************************************************************/
8840 /* */
8841 /* Single Wire Protocol Master Interface (SWPMI) */
8842 /* */
8843 /******************************************************************************/
8844
8845 /******************* Bit definition for SWPMI_CR register ********************/
8846 #define SWPMI_CR_RXDMA ((uint32_t)0x00000001U) /*!<Reception DMA enable */
8847 #define SWPMI_CR_TXDMA ((uint32_t)0x00000002U) /*!<Transmission DMA enable */
8848 #define SWPMI_CR_RXMODE ((uint32_t)0x00000004U) /*!<Reception buffering mode */
8849 #define SWPMI_CR_TXMODE ((uint32_t)0x00000008U) /*!<Transmission buffering mode */
8850 #define SWPMI_CR_LPBK ((uint32_t)0x00000010U) /*!<Loopback mode enable */
8851 #define SWPMI_CR_SWPACT ((uint32_t)0x00000020U) /*!<Single wire protocol master interface activate */
8852 #define SWPMI_CR_DEACT ((uint32_t)0x00000400U) /*!<Single wire protocol master interface deactivate */
8853
8854 /******************* Bit definition for SWPMI_BRR register ********************/
8855 #define SWPMI_BRR_BR ((uint32_t)0x0000003FU) /*!<BR[5:0] bits (Bitrate prescaler) */
8856
8857 /******************* Bit definition for SWPMI_ISR register ********************/
8858 #define SWPMI_ISR_RXBFF ((uint32_t)0x00000001U) /*!<Receive buffer full flag */
8859 #define SWPMI_ISR_TXBEF ((uint32_t)0x00000002U) /*!<Transmit buffer empty flag */
8860 #define SWPMI_ISR_RXBERF ((uint32_t)0x00000004U) /*!<Receive CRC error flag */
8861 #define SWPMI_ISR_RXOVRF ((uint32_t)0x00000008U) /*!<Receive overrun error flag */
8862 #define SWPMI_ISR_TXUNRF ((uint32_t)0x00000010U) /*!<Transmit underrun error flag */
8863 #define SWPMI_ISR_RXNE ((uint32_t)0x00000020U) /*!<Receive data register not empty */
8864 #define SWPMI_ISR_TXE ((uint32_t)0x00000040U) /*!<Transmit data register empty */
8865 #define SWPMI_ISR_TCF ((uint32_t)0x00000080U) /*!<Transfer complete flag */
8866 #define SWPMI_ISR_SRF ((uint32_t)0x00000100U) /*!<Slave resume flag */
8867 #define SWPMI_ISR_SUSP ((uint32_t)0x00000200U) /*!<SUSPEND flag */
8868 #define SWPMI_ISR_DEACTF ((uint32_t)0x00000400U) /*!<DEACTIVATED flag */
8869
8870 /******************* Bit definition for SWPMI_ICR register ********************/
8871 #define SWPMI_ICR_CRXBFF ((uint32_t)0x00000001U) /*!<Clear receive buffer full flag */
8872 #define SWPMI_ICR_CTXBEF ((uint32_t)0x00000002U) /*!<Clear transmit buffer empty flag */
8873 #define SWPMI_ICR_CRXBERF ((uint32_t)0x00000004U) /*!<Clear receive CRC error flag */
8874 #define SWPMI_ICR_CRXOVRF ((uint32_t)0x00000008U) /*!<Clear receive overrun error flag */
8875 #define SWPMI_ICR_CTXUNRF ((uint32_t)0x00000010U) /*!<Clear transmit underrun error flag */
8876 #define SWPMI_ICR_CTCF ((uint32_t)0x00000080U) /*!<Clear transfer complete flag */
8877 #define SWPMI_ICR_CSRF ((uint32_t)0x00000100U) /*!<Clear slave resume flag */
8878
8879 /******************* Bit definition for SWPMI_IER register ********************/
8880 #define SWPMI_IER_SRIE ((uint32_t)0x00000100U) /*!<Slave resume interrupt enable */
8881 #define SWPMI_IER_TCIE ((uint32_t)0x00000080U) /*!<Transmit complete interrupt enable */
8882 #define SWPMI_IER_TIE ((uint32_t)0x00000040U) /*!<Transmit interrupt enable */
8883 #define SWPMI_IER_RIE ((uint32_t)0x00000020U) /*!<Receive interrupt enable */
8884 #define SWPMI_IER_TXUNRIE ((uint32_t)0x00000010U) /*!<Transmit underrun error interrupt enable */
8885 #define SWPMI_IER_RXOVRIE ((uint32_t)0x00000008U) /*!<Receive overrun error interrupt enable */
8886 #define SWPMI_IER_RXBERIE ((uint32_t)0x00000004U) /*!<Receive CRC error interrupt enable */
8887 #define SWPMI_IER_TXBEIE ((uint32_t)0x00000002U) /*!<Transmit buffer empty interrupt enable */
8888 #define SWPMI_IER_RXBFIE ((uint32_t)0x00000001U) /*!<Receive buffer full interrupt enable */
8889
8890 /******************* Bit definition for SWPMI_RFL register ********************/
8891 #define SWPMI_RFL_RFL ((uint32_t)0x0000001FU) /*!<RFL[4:0] bits (Receive Frame length) */
8892 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
8893
8894 /******************* Bit definition for SWPMI_TDR register ********************/
8895 #define SWPMI_TDR_TD ((uint32_t)0xFFFFFFFFU) /*!<Transmit Data Register */
8896
8897 /******************* Bit definition for SWPMI_RDR register ********************/
8898 #define SWPMI_RDR_RD ((uint32_t)0xFFFFFFFFU) /*!<Receive Data Register */
8899
8900 /******************* Bit definition for SWPMI_OR register ********************/
8901 #define SWPMI_OR_TBYP ((uint32_t)0x00000001U) /*!<SWP Transceiver Bypass */
8902 #define SWPMI_OR_CLASS ((uint32_t)0x00000002U) /*!<SWP Voltage Class selection */
8903
8904 /******************************************************************************/
8905 /* */
8906 /* VREFBUF */
8907 /* */
8908 /******************************************************************************/
8909 /******************* Bit definition for VREFBUF_CSR register ****************/
8910 #define VREFBUF_CSR_ENVR ((uint32_t)0x00000001U) /*!<Voltage reference buffer enable */
8911 #define VREFBUF_CSR_HIZ ((uint32_t)0x00000002U) /*!<High impedance mode */
8912 #define VREFBUF_CSR_VRS ((uint32_t)0x00000004U) /*!<Voltage reference scale */
8913 #define VREFBUF_CSR_VRR ((uint32_t)0x00000008U) /*!<Voltage reference buffer ready */
8914
8915 /******************* Bit definition for VREFBUF_CCR register ******************/
8916 #define VREFBUF_CCR_TRIM ((uint32_t)0x0000003FU) /*!<TRIM[5:0] bits (Trimming code) */
8917
8918 /******************************************************************************/
8919 /* */
8920 /* Window WATCHDOG */
8921 /* */
8922 /******************************************************************************/
8923 /******************* Bit definition for WWDG_CR register ********************/
8924 #define WWDG_CR_T ((uint32_t)0x0000007FU) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
8925 #define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8926 #define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8927 #define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
8928 #define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
8929 #define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
8930 #define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
8931 #define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
8932
8933 #define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!<Activation bit */
8934
8935 /******************* Bit definition for WWDG_CFR register *******************/
8936 #define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!<W[6:0] bits (7-bit window value) */
8937 #define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
8938 #define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
8939 #define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
8940 #define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
8941 #define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
8942 #define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
8943 #define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
8944
8945 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!<WDGTB[1:0] bits (Timer Base) */
8946 #define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
8947 #define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
8948
8949 #define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!<Early Wakeup Interrupt */
8950
8951 /******************* Bit definition for WWDG_SR register ********************/
8952 #define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!<Early Wakeup Interrupt Flag */
8953
8954
8955 /******************************************************************************/
8956 /* */
8957 /* Debug MCU */
8958 /* */
8959 /******************************************************************************/
8960 /******************** Bit definition for DBGMCU_IDCODE register *************/
8961 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU)
8962 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U)
8963
8964 /******************** Bit definition for DBGMCU_CR register *****************/
8965 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U)
8966 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U)
8967 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U)
8968 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020U)
8969
8970 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0U)
8971 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040U)/*!<Bit 0 */
8972 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080U)/*!<Bit 1 */
8973
8974 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
8975 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP ((uint32_t)0x00000001U)
8976 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP ((uint32_t)0x00000002U)
8977 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP ((uint32_t)0x00000004U)
8978 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP ((uint32_t)0x00000008U)
8979 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP ((uint32_t)0x00000010U)
8980 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP ((uint32_t)0x00000020U)
8981 #define DBGMCU_APB1FZR1_DBG_RTC_STOP ((uint32_t)0x00000400U)
8982 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP ((uint32_t)0x00000800U)
8983 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP ((uint32_t)0x00001000U)
8984 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP ((uint32_t)0x00200000U)
8985 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP ((uint32_t)0x00400000U)
8986 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP ((uint32_t)0x00800000U)
8987 #define DBGMCU_APB1FZR1_DBG_CAN_STOP ((uint32_t)0x02000000U)
8988 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP ((uint32_t)0x80000000U)
8989
8990 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
8991 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP ((uint32_t)0x00000020U)
8992
8993 /******************** Bit definition for DBGMCU_APB2FZ register ************/
8994 #define DBGMCU_APB2FZ_DBG_TIM1_STOP ((uint32_t)0x00000800U)
8995 #define DBGMCU_APB2FZ_DBG_TIM8_STOP ((uint32_t)0x00002000U)
8996 #define DBGMCU_APB2FZ_DBG_TIM15_STOP ((uint32_t)0x00010000U)
8997 #define DBGMCU_APB2FZ_DBG_TIM16_STOP ((uint32_t)0x00020000U)
8998 #define DBGMCU_APB2FZ_DBG_TIM17_STOP ((uint32_t)0x00040000U)
8999
9000 /******************************************************************************/
9001 /* */
9002 /* USB_OTG */
9003 /* */
9004 /******************************************************************************/
9005 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
9006 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001U) /*!< Session request success */
9007 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002U) /*!< Session request */
9008 #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004U) /*!< VBUS valid override enable */
9009 #define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008U) /*!< VBUS valid override value */
9010 #define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010U) /*!< A-peripheral session valid override enable */
9011 #define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020U) /*!< A-peripheral session valid override value */
9012 #define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040U) /*!< B-peripheral session valid override enable */
9013 #define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080U) /*!< B-peripheral session valid override value */
9014 #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000U) /*!< B-session valid*/
9015
9016 /******************** Bit definition for USB_OTG_HCFG register ********************/
9017
9018 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003U) /*!< FS/LS PHY clock select */
9019 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
9020 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
9021 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004U) /*!< FS- and LS-only support */
9022
9023 /******************** Bit definition for USB_OTG_DCFG register ********************/
9024
9025 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003U) /*!< Device speed */
9026 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
9027 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
9028 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004U) /*!< Nonzero-length status OUT handshake */
9029 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0U) /*!< Device address */
9030 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
9031 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
9032 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
9033 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
9034 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100U) /*!<Bit 4 */
9035 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200U) /*!<Bit 5 */
9036 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400U) /*!<Bit 6 */
9037 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800U) /*!< Periodic (micro)frame interval */
9038 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800U) /*!<Bit 0 */
9039 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000U) /*!<Bit 1 */
9040 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000U) /*!< Periodic scheduling interval */
9041 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
9042 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
9043
9044 /******************** Bit definition for USB_OTG_PCGCR register ********************/
9045 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001U) /*!< Stop PHY clock */
9046 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002U) /*!< Gate HCLK */
9047 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010U) /*!< PHY suspended */
9048
9049 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
9050 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004U) /*!< Session end detected */
9051 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100U) /*!< Session request success status change */
9052 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200U) /*!< Host negotiation success status change */
9053 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000U) /*!< Host negotiation detected */
9054 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000U) /*!< A-device timeout change */
9055 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000U) /*!< Debounce done */
9056
9057 /******************** Bit definition for USB_OTG_DCTL register ********************/
9058 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001U) /*!< Remote wakeup signaling */
9059 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002U) /*!< Soft disconnect */
9060 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004U) /*!< Global IN NAK status */
9061 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008U) /*!< Global OUT NAK status */
9062
9063 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070U) /*!< Test control */
9064 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
9065 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
9066 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
9067 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080U) /*!< Set global IN NAK */
9068 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100U) /*!< Clear global IN NAK */
9069 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200U) /*!< Set global OUT NAK */
9070 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400U) /*!< Clear global OUT NAK */
9071 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800U) /*!< Power-on programming done */
9072
9073 /******************** Bit definition for USB_OTG_HFIR register ********************/
9074 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFFU) /*!< Frame interval */
9075
9076 /******************** Bit definition for USB_OTG_HFNUM register ********************/
9077 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFFU) /*!< Frame number */
9078 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000U) /*!< Frame time remaining */
9079
9080 /******************** Bit definition for USB_OTG_DSTS register ********************/
9081 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001U) /*!< Suspend status */
9082
9083 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006U) /*!< Enumerated speed */
9084 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
9085 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
9086 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008U) /*!< Erratic error */
9087 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00U) /*!< Frame number of the received SOF */
9088
9089 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
9090 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001U) /*!< Global interrupt mask */
9091 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001EU) /*!< Burst length/type */
9092 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
9093 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
9094 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008U) /*!<Bit 2 */
9095 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010U) /*!<Bit 3 */
9096 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020U) /*!< DMA enable */
9097 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080U) /*!< TxFIFO empty level */
9098 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100U) /*!< Periodic TxFIFO empty level */
9099
9100 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
9101
9102 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007U) /*!< FS timeout calibration */
9103 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
9104 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
9105 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
9106 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040U) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
9107 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100U) /*!< SRP-capable */
9108 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200U) /*!< HNP-capable */
9109 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00U) /*!< USB turnaround time */
9110 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
9111 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
9112 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000U) /*!<Bit 2 */
9113 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000U) /*!<Bit 3 */
9114 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000U) /*!< PHY Low-power clock select */
9115 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000U) /*!< ULPI FS/LS select */
9116 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000U) /*!< ULPI Auto-resume */
9117 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000U) /*!< ULPI Clock SuspendM */
9118 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000U) /*!< ULPI External VBUS Drive */
9119 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000U) /*!< ULPI external VBUS indicator */
9120 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000U) /*!< TermSel DLine pulsing selection */
9121 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000U) /*!< Indicator complement */
9122 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000U) /*!< Indicator pass through */
9123 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000U) /*!< ULPI interface protect disable */
9124 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000U) /*!< Forced host mode */
9125 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000U) /*!< Forced peripheral mode */
9126 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000U) /*!< Corrupt Tx packet */
9127
9128 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
9129 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001U) /*!< Core soft reset */
9130 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002U) /*!< HCLK soft reset */
9131 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004U) /*!< Host frame counter reset */
9132 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010U) /*!< RxFIFO flush */
9133 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020U) /*!< TxFIFO flush */
9134 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0U) /*!< TxFIFO number */
9135 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
9136 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
9137 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100U) /*!<Bit 2 */
9138 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200U) /*!<Bit 3 */
9139 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400U) /*!<Bit 4 */
9140 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000U) /*!< DMA request signal */
9141 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000U) /*!< AHB master idle */
9142
9143 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
9144 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed interrupt mask */
9145 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt mask */
9146 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008U) /*!< Timeout condition mask (nonisochronous endpoints) */
9147 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010U) /*!< IN token received when TxFIFO empty mask */
9148 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020U) /*!< IN token received with EP mismatch mask */
9149 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040U) /*!< IN endpoint NAK effective mask */
9150 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100U) /*!< FIFO underrun mask */
9151 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200U) /*!< BNA interrupt mask */
9152
9153 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
9154 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFFU) /*!< Periodic transmit data FIFO space available */
9155 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000U) /*!< Periodic transmit request queue space available */
9156 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
9157 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
9158 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
9159 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
9160 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
9161 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
9162 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
9163 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
9164
9165 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000U) /*!< Top of the periodic transmit request queue */
9166 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
9167 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
9168 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
9169 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
9170 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
9171 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
9172 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
9173 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000U) /*!<Bit 7 */
9174
9175 /******************** Bit definition for USB_OTG_HAINT register ********************/
9176 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFFU) /*!< Channel interrupts */
9177
9178 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
9179 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed interrupt mask */
9180 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt mask */
9181 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008U) /*!< SETUP phase done mask */
9182 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010U) /*!< OUT token received when endpoint disabled mask */
9183 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040U) /*!< Back-to-back SETUP packets received mask */
9184 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100U) /*!< OUT packet error mask */
9185 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200U) /*!< BNA interrupt mask */
9186
9187 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
9188 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001U) /*!< Current mode of operation */
9189 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002U) /*!< Mode mismatch interrupt */
9190 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004U) /*!< OTG interrupt */
9191 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008U) /*!< Start of frame */
9192 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010U) /*!< RxFIFO nonempty */
9193 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020U) /*!< Nonperiodic TxFIFO empty */
9194 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040U) /*!< Global IN nonperiodic NAK effective */
9195 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080U) /*!< Global OUT NAK effective */
9196 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400U) /*!< Early suspend */
9197 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800U) /*!< USB suspend */
9198 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000U) /*!< USB reset */
9199 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000U) /*!< Enumeration done */
9200 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000U) /*!< Isochronous OUT packet dropped interrupt */
9201 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000U) /*!< End of periodic frame interrupt */
9202 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000U) /*!< IN endpoint interrupt */
9203 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000U) /*!< OUT endpoint interrupt */
9204 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000U) /*!< Incomplete isochronous IN transfer */
9205 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000U) /*!< Incomplete periodic transfer */
9206 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000U) /*!< Data fetch suspended */
9207 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000U) /*!< Host port interrupt */
9208 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000U) /*!< Host channels interrupt */
9209 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000U) /*!< Periodic TxFIFO empty */
9210 #define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000U) /*!< LPM interrupt */
9211 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000U) /*!< Connector ID status change */
9212 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000U) /*!< Disconnect detected interrupt */
9213 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000U) /*!< Session request/new session detected interrupt */
9214 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000U) /*!< Resume/remote wakeup detected interrupt */
9215
9216 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
9217
9218 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002U) /*!< Mode mismatch interrupt mask */
9219 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004U) /*!< OTG interrupt mask */
9220 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008U) /*!< Start of frame mask */
9221 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010U) /*!< Receive FIFO nonempty mask */
9222 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020U) /*!< Nonperiodic TxFIFO empty mask */
9223 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040U) /*!< Global nonperiodic IN NAK effective mask */
9224 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080U) /*!< Global OUT NAK effective mask */
9225 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400U) /*!< Early suspend mask */
9226 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800U) /*!< USB suspend mask */
9227 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000U) /*!< USB reset mask */
9228 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000U) /*!< Enumeration done mask */
9229 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000U) /*!< Isochronous OUT packet dropped interrupt mask */
9230 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000U) /*!< End of periodic frame interrupt mask */
9231 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000U) /*!< Endpoint mismatch interrupt mask */
9232 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000U) /*!< IN endpoints interrupt mask */
9233 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000U) /*!< OUT endpoints interrupt mask */
9234 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000U) /*!< Incomplete isochronous IN transfer mask */
9235 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000U) /*!< Incomplete periodic transfer mask */
9236 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000U) /*!< Data fetch suspended mask */
9237 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000U) /*!< Host port interrupt mask */
9238 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000U) /*!< Host channels interrupt mask */
9239 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000U) /*!< Periodic TxFIFO empty mask */
9240 #define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000U) /*!< LPM interrupt Mask */
9241 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000U) /*!< Connector ID status change mask */
9242 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000U) /*!< Disconnect detected interrupt mask */
9243 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000U) /*!< Session request/new session detected interrupt mask */
9244 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000U) /*!< Resume/remote wakeup detected interrupt mask */
9245
9246 /******************** Bit definition for USB_OTG_DAINT register ********************/
9247 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFFU) /*!< IN endpoint interrupt bits */
9248 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000U) /*!< OUT endpoint interrupt bits */
9249
9250 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
9251 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFFU) /*!< Channel interrupt mask */
9252
9253 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
9254 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000FU) /*!< IN EP interrupt mask bits */
9255 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0U) /*!< OUT EP interrupt mask bits */
9256 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000U) /*!< OUT EP interrupt mask bits */
9257 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000U) /*!< OUT EP interrupt mask bits */
9258
9259 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
9260 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFFU) /*!< IN EP interrupt mask bits */
9261 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000U) /*!< OUT EP interrupt mask bits */
9262
9263 /******************** Bit definition for OTG register ********************/
9264
9265 #define USB_OTG_CHNUM ((uint32_t)0x0000000FU) /*!< Channel number */
9266 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
9267 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
9268 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
9269 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
9270 #define USB_OTG_BCNT ((uint32_t)0x00007FF0U) /*!< Byte count */
9271 #define USB_OTG_DPID ((uint32_t)0x00018000U) /*!< Data PID */
9272 #define USB_OTG_DPID_0 ((uint32_t)0x00008000U) /*!<Bit 0 */
9273 #define USB_OTG_DPID_1 ((uint32_t)0x00010000U) /*!<Bit 1 */
9274 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000U) /*!< Packet status */
9275 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
9276 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
9277 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
9278 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
9279 #define USB_OTG_EPNUM ((uint32_t)0x0000000FU) /*!< Endpoint number */
9280 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
9281 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
9282 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
9283 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
9284 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000U) /*!< Frame number */
9285 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000U) /*!<Bit 0 */
9286 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000U) /*!<Bit 1 */
9287 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000U) /*!<Bit 2 */
9288 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
9289
9290 /******************** Bit definition for OTG register ********************/
9291
9292 #define USB_OTG_CHNUM ((uint32_t)0x0000000FU) /*!< Channel number */
9293 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
9294 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
9295 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
9296 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
9297 #define USB_OTG_BCNT ((uint32_t)0x00007FF0U) /*!< Byte count */
9298 #define USB_OTG_DPID ((uint32_t)0x00018000U) /*!< Data PID */
9299 #define USB_OTG_DPID_0 ((uint32_t)0x00008000U) /*!<Bit 0 */
9300 #define USB_OTG_DPID_1 ((uint32_t)0x00010000U) /*!<Bit 1 */
9301 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000U) /*!< Packet status */
9302 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
9303 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
9304 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
9305 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
9306 #define USB_OTG_EPNUM ((uint32_t)0x0000000FU) /*!< Endpoint number */
9307 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
9308 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
9309 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
9310 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
9311 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000U) /*!< Frame number */
9312 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000U) /*!<Bit 0 */
9313 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000U) /*!<Bit 1 */
9314 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000U) /*!<Bit 2 */
9315 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000U) /*!<Bit 3 */
9316
9317 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
9318 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFFU) /*!< RxFIFO depth */
9319
9320 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
9321 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFFU) /*!< Device VBUS discharge time */
9322
9323 /******************** Bit definition for OTG register ********************/
9324 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFFU) /*!< Nonperiodic transmit RAM start address */
9325 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000U) /*!< Nonperiodic TxFIFO depth */
9326 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFFU) /*!< Endpoint 0 transmit RAM start address */
9327 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000U) /*!< Endpoint 0 TxFIFO depth */
9328
9329 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
9330 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFFU) /*!< Device VBUS pulsing time */
9331
9332 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
9333 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFFU) /*!< Nonperiodic TxFIFO space available */
9334
9335 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000U) /*!< Nonperiodic transmit request queue space available */
9336 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000U) /*!<Bit 0 */
9337 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000U) /*!<Bit 1 */
9338 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000U) /*!<Bit 2 */
9339 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000U) /*!<Bit 3 */
9340 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000U) /*!<Bit 4 */
9341 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000U) /*!<Bit 5 */
9342 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000U) /*!<Bit 6 */
9343 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000U) /*!<Bit 7 */
9344
9345 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000U) /*!< Top of the nonperiodic transmit request queue */
9346 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
9347 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
9348 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
9349 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
9350 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000U) /*!<Bit 4 */
9351 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000U) /*!<Bit 5 */
9352 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000U) /*!<Bit 6 */
9353
9354 /******************** Bit definition for USB_OTG_DTHRCTL register ***************/
9355 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001U) /*!< Nonisochronous IN endpoints threshold enable */
9356 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002U) /*!< ISO IN endpoint threshold enable */
9357
9358 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FCU) /*!< Transmit threshold length */
9359 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
9360 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
9361 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010U) /*!<Bit 2 */
9362 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020U) /*!<Bit 3 */
9363 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040U) /*!<Bit 4 */
9364 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080U) /*!<Bit 5 */
9365 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100U) /*!<Bit 6 */
9366 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200U) /*!<Bit 7 */
9367 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400U) /*!<Bit 8 */
9368 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000U) /*!< Receive threshold enable */
9369
9370 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000U) /*!< Receive threshold length */
9371 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
9372 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
9373 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
9374 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
9375 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
9376 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
9377 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
9378 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000U) /*!<Bit 7 */
9379 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000U) /*!<Bit 8 */
9380 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000U) /*!< Arbiter parking enable */
9381
9382 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
9383 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFFU) /*!< IN EP Tx FIFO empty interrupt mask bits */
9384
9385 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
9386 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002U) /*!< IN endpoint 1interrupt bit */
9387 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000U) /*!< OUT endpoint 1 interrupt bit */
9388
9389 /******************** Bit definition for USB_OTG_GCCFG register ********************/
9390 #define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001U) /*!< Data contact detection (DCD) status */
9391 #define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002U) /*!< Primary detection (PD) status */
9392 #define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004U) /*!< Secondary detection (SD) status */
9393 #define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008U) /*!< DM pull-up detection status */
9394 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000U) /*!< Power down */
9395 #define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000U) /*!< Battery charging detector (BCD) enable */
9396 #define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000U) /*!< Data contact detection (DCD) mode enable*/
9397 #define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000U) /*!< Primary detection (PD) mode enable*/
9398 #define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000U) /*!< Secondary detection (SD) mode enable */
9399 #define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000U) /*!< Secondary detection (SD) mode enable */
9400
9401 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
9402 #define USB_OTG_GPWRDN_DISABLEVBUS ((uint32_t)0x00000040U) /*!< Power down */
9403
9404 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
9405 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002U) /*!< IN Endpoint 1 interrupt mask bit */
9406 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000U) /*!< OUT Endpoint 1 interrupt mask bit */
9407
9408 /******************** Bit definition for USB_OTG_CID register ********************/
9409 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFFU) /*!< Product ID field */
9410
9411
9412 /******************** Bit definition for USB_OTG_GHWCFG3 register ********************/
9413 #define USB_OTG_GHWCFG3_LPMMode ((uint32_t)0x00004000U) /* LPM mode specified for Mode of Operation */
9414
9415 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
9416 #define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000U) /* Enable best effort service latency */
9417 #define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000U) /* LPM retry count status */
9418 #define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000U) /* Send LPM transaction */
9419 #define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000U) /* LPM retry count */
9420 #define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000U) /* LPMCHIDX: */
9421 #define USB_OTG_GLPMCFG_L1ResumeOK ((uint32_t)0x00010000U) /* Sleep State Resume OK */
9422 #define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000U) /* Port sleep status */
9423 #define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000U) /* LPM response */
9424 #define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000U) /* L1 deep sleep enable */
9425 #define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00U) /* BESL threshold */
9426 #define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080U) /* L1 shallow sleep enable */
9427 #define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040U) /* bRemoteWake value received with last ACKed LPM Token */
9428 #define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003CU) /* BESL value received with last ACKed LPM Token */
9429 #define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002U) /* LPM Token acknowledge enable*/
9430 #define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001U) /* LPM support enable */
9431
9432
9433 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
9434 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed interrupt mask */
9435 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt mask */
9436 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008U) /*!< Timeout condition mask (nonisochronous endpoints) */
9437 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010U) /*!< IN token received when TxFIFO empty mask */
9438 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020U) /*!< IN token received with EP mismatch mask */
9439 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040U) /*!< IN endpoint NAK effective mask */
9440 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100U) /*!< FIFO underrun mask */
9441 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200U) /*!< BNA interrupt mask */
9442 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000U) /*!< NAK interrupt mask */
9443
9444 /******************** Bit definition for USB_OTG_HPRT register ********************/
9445 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001U) /*!< Port connect status */
9446 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002U) /*!< Port connect detected */
9447 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004U) /*!< Port enable */
9448 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008U) /*!< Port enable/disable change */
9449 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010U) /*!< Port overcurrent active */
9450 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020U) /*!< Port overcurrent change */
9451 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040U) /*!< Port resume */
9452 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080U) /*!< Port suspend */
9453 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100U) /*!< Port reset */
9454
9455 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00U) /*!< Port line status */
9456 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
9457 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
9458 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000U) /*!< Port power */
9459
9460 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000U) /*!< Port test control */
9461 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000U) /*!<Bit 0 */
9462 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000U) /*!<Bit 1 */
9463 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000U) /*!<Bit 2 */
9464 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000U) /*!<Bit 3 */
9465
9466 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000U) /*!< Port speed */
9467 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
9468 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
9469
9470 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
9471 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed interrupt mask */
9472 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt mask */
9473 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008U) /*!< Timeout condition mask */
9474 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010U) /*!< IN token received when TxFIFO empty mask */
9475 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020U) /*!< IN token received with EP mismatch mask */
9476 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040U) /*!< IN endpoint NAK effective mask */
9477 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100U) /*!< OUT packet error mask */
9478 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200U) /*!< BNA interrupt mask */
9479 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000U) /*!< Bubble error interrupt mask */
9480 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000U) /*!< NAK interrupt mask */
9481 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000U) /*!< NYET interrupt mask */
9482
9483 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
9484 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFFU) /*!< Host periodic TxFIFO start address */
9485 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000U) /*!< Host periodic TxFIFO depth */
9486
9487 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
9488 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FFU) /*!< Maximum packet size */
9489 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000U) /*!< USB active endpoint */
9490 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000U) /*!< Even/odd frame */
9491 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000U) /*!< NAK status */
9492
9493 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000U) /*!< Endpoint type */
9494 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000U) /*!<Bit 0 */
9495 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000U) /*!<Bit 1 */
9496 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000U) /*!< STALL handshake */
9497
9498 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000U) /*!< TxFIFO number */
9499 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
9500 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
9501 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000U) /*!<Bit 2 */
9502 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000U) /*!<Bit 3 */
9503 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000U) /*!< Clear NAK */
9504 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000U) /*!< Set NAK */
9505 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000U) /*!< Set DATA0 PID */
9506 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000U) /*!< Set odd frame */
9507 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000U) /*!< Endpoint disable */
9508 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000U) /*!< Endpoint enable */
9509
9510 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
9511 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FFU) /*!< Maximum packet size */
9512
9513 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800U) /*!< Endpoint number */
9514 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800U) /*!<Bit 0 */
9515 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000U) /*!<Bit 1 */
9516 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000U) /*!<Bit 2 */
9517 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000U) /*!<Bit 3 */
9518 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000U) /*!< Endpoint direction */
9519 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000U) /*!< Low-speed device */
9520
9521 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000U) /*!< Endpoint type */
9522 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000U) /*!<Bit 0 */
9523 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000U) /*!<Bit 1 */
9524
9525 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000U) /*!< Multi Count (MC) / Error Count (EC) */
9526 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000U) /*!<Bit 0 */
9527 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000U) /*!<Bit 1 */
9528
9529 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000U) /*!< Device address */
9530 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
9531 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
9532 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000U) /*!<Bit 2 */
9533 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000U) /*!<Bit 3 */
9534 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000U) /*!<Bit 4 */
9535 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000U) /*!<Bit 5 */
9536 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000U) /*!<Bit 6 */
9537 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000U) /*!< Odd frame */
9538 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000U) /*!< Channel disable */
9539 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000U) /*!< Channel enable */
9540
9541 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
9542
9543 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007FU) /*!< Port address */
9544 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
9545 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
9546 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
9547 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
9548 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
9549 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020U) /*!<Bit 5 */
9550 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040U) /*!<Bit 6 */
9551
9552 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80U) /*!< Hub address */
9553 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080U) /*!<Bit 0 */
9554 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100U) /*!<Bit 1 */
9555 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200U) /*!<Bit 2 */
9556 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400U) /*!<Bit 3 */
9557 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800U) /*!<Bit 4 */
9558 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000U) /*!<Bit 5 */
9559 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000U) /*!<Bit 6 */
9560
9561 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000U) /*!< XACTPOS */
9562 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000U) /*!<Bit 0 */
9563 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000U) /*!<Bit 1 */
9564 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000U) /*!< Do complete split */
9565 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000U) /*!< Split enable */
9566
9567 /******************** Bit definition for USB_OTG_HCINT register ********************/
9568 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001U) /*!< Transfer completed */
9569 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002U) /*!< Channel halted */
9570 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004U) /*!< AHB error */
9571 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008U) /*!< STALL response received interrupt */
9572 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010U) /*!< NAK response received interrupt */
9573 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020U) /*!< ACK response received/transmitted interrupt */
9574 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040U) /*!< Response received interrupt */
9575 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080U) /*!< Transaction error */
9576 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100U) /*!< Babble error */
9577 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200U) /*!< Frame overrun */
9578 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400U) /*!< Data toggle error */
9579
9580 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
9581 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001U) /*!< Transfer completed interrupt */
9582 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt */
9583 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008U) /*!< Timeout condition */
9584 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010U) /*!< IN token received when TxFIFO is empty */
9585 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040U) /*!< IN endpoint NAK effective */
9586 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080U) /*!< Transmit FIFO empty */
9587 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100U) /*!< Transmit Fifo Underrun */
9588 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200U) /*!< Buffer not available interrupt */
9589 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800U) /*!< Packet dropped status */
9590 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000U) /*!< Babble error interrupt */
9591 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000U) /*!< NAK interrupt */
9592
9593 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
9594 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001U) /*!< Transfer completed mask */
9595 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002U) /*!< Channel halted mask */
9596 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004U) /*!< AHB error */
9597 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008U) /*!< STALL response received interrupt mask */
9598 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010U) /*!< NAK response received interrupt mask */
9599 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020U) /*!< ACK response received/transmitted interrupt mask */
9600 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040U) /*!< response received interrupt mask */
9601 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080U) /*!< Transaction error mask */
9602 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100U) /*!< Babble error mask */
9603 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200U) /*!< Frame overrun mask */
9604 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400U) /*!< Data toggle error mask */
9605
9606 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
9607
9608 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFFU) /*!< Transfer size */
9609 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000U) /*!< Packet count */
9610 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000U) /*!< Packet count */
9611 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
9612 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFFU) /*!< Transfer size */
9613 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000U) /*!< Packet count */
9614 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000U) /*!< Do PING */
9615 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000U) /*!< Data PID */
9616 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000U) /*!<Bit 0 */
9617 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000U) /*!<Bit 1 */
9618
9619 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
9620 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFFU) /*!< DMA address */
9621
9622 /******************** Bit definition for USB_OTG_HCDMA register ********************/
9623 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFFU) /*!< DMA address */
9624
9625 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
9626 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFFU) /*!< IN endpoint TxFIFO space avail */
9627
9628 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
9629 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFFU) /*!< IN endpoint FIFOx transmit RAM start address */
9630 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000U) /*!< IN endpoint TxFIFO depth */
9631
9632 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
9633
9634 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FFU) /*!< Maximum packet size */ /*!<Bit 1 */
9635 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000U) /*!< USB active endpoint */
9636 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000U) /*!< NAK status */
9637 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000U) /*!< Set DATA0 PID */
9638 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000U) /*!< Set odd frame */
9639 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000U) /*!< Endpoint type */
9640 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000U) /*!<Bit 0 */
9641 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000U) /*!<Bit 1 */
9642 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000U) /*!< Snoop mode */
9643 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000U) /*!< STALL handshake */
9644 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000U) /*!< Clear NAK */
9645 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000U) /*!< Set NAK */
9646 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000U) /*!< Endpoint disable */
9647 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000U) /*!< Endpoint enable */
9648
9649 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
9650 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001U) /*!< Transfer completed interrupt */
9651 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002U) /*!< Endpoint disabled interrupt */
9652 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008U) /*!< SETUP phase done */
9653 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010U) /*!< OUT token received when endpoint disabled */
9654 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040U) /*!< Back-to-back SETUP packets received */
9655 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000U) /*!< NYET interrupt */
9656
9657 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
9658
9659 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFFU) /*!< Transfer size */
9660 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000U) /*!< Packet count */
9661
9662 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000U) /*!< SETUP packet count */
9663 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000U) /*!<Bit 0 */
9664 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000U) /*!<Bit 1 */
9665
9666 /******************** Bit definition for PCGCCTL register ********************/
9667 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001U) /*!< SETUP packet count */
9668 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002U) /*!<Bit 0 */
9669 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010U) /*!<Bit 1 */
9670
9671
9672 /**
9673 * @}
9674 */
9675
9676 /**
9677 * @}
9678 */
9679
9680 /** @addtogroup Exported_macros
9681 * @{
9682 */
9683
9684 /******************************* ADC Instances ********************************/
9685 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
9686 ((INSTANCE) == ADC2) || \
9687 ((INSTANCE) == ADC3))
9688
9689 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9690
9691 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
9692
9693 /******************************* AES Instances ********************************/
9694 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
9695
9696 /******************************** CAN Instances ******************************/
9697 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
9698
9699 /******************************** COMP Instances ******************************/
9700 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
9701 ((INSTANCE) == COMP2))
9702
9703 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
9704
9705 /******************** COMP Instances with window mode capability **************/
9706 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
9707
9708 /******************************* CRC Instances ********************************/
9709 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
9710
9711 /******************************* DAC Instances ********************************/
9712 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
9713
9714 /****************************** DFSDM Instances *******************************/
9715 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Filter0) || \
9716 ((INSTANCE) == DFSDM_Filter1) || \
9717 ((INSTANCE) == DFSDM_Filter2) || \
9718 ((INSTANCE) == DFSDM_Filter3))
9719
9720 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Channel0) || \
9721 ((INSTANCE) == DFSDM_Channel1) || \
9722 ((INSTANCE) == DFSDM_Channel2) || \
9723 ((INSTANCE) == DFSDM_Channel3) || \
9724 ((INSTANCE) == DFSDM_Channel4) || \
9725 ((INSTANCE) == DFSDM_Channel5) || \
9726 ((INSTANCE) == DFSDM_Channel6) || \
9727 ((INSTANCE) == DFSDM_Channel7))
9728
9729 /******************************** DMA Instances *******************************/
9730 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
9731 ((INSTANCE) == DMA1_Channel2) || \
9732 ((INSTANCE) == DMA1_Channel3) || \
9733 ((INSTANCE) == DMA1_Channel4) || \
9734 ((INSTANCE) == DMA1_Channel5) || \
9735 ((INSTANCE) == DMA1_Channel6) || \
9736 ((INSTANCE) == DMA1_Channel7) || \
9737 ((INSTANCE) == DMA2_Channel1) || \
9738 ((INSTANCE) == DMA2_Channel2) || \
9739 ((INSTANCE) == DMA2_Channel3) || \
9740 ((INSTANCE) == DMA2_Channel4) || \
9741 ((INSTANCE) == DMA2_Channel5) || \
9742 ((INSTANCE) == DMA2_Channel6) || \
9743 ((INSTANCE) == DMA2_Channel7))
9744
9745 /******************************* GPIO Instances *******************************/
9746 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
9747 ((INSTANCE) == GPIOB) || \
9748 ((INSTANCE) == GPIOC) || \
9749 ((INSTANCE) == GPIOD) || \
9750 ((INSTANCE) == GPIOE) || \
9751 ((INSTANCE) == GPIOF) || \
9752 ((INSTANCE) == GPIOG) || \
9753 ((INSTANCE) == GPIOH))
9754
9755 /******************************* GPIO AF Instances ****************************/
9756 /* On L4, all GPIO Bank support AF */
9757 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9758
9759 /**************************** GPIO Lock Instances *****************************/
9760 /* On L4, all GPIO Bank support the Lock mechanism */
9761 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9762
9763 /******************************** I2C Instances *******************************/
9764 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
9765 ((INSTANCE) == I2C2) || \
9766 ((INSTANCE) == I2C3))
9767
9768 /******************************* LCD Instances ********************************/
9769 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
9770
9771 /******************************* HCD Instances *******************************/
9772 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
9773
9774 /****************************** OPAMP Instances *******************************/
9775 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
9776 ((INSTANCE) == OPAMP2))
9777
9778 #define IS_OPAMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP12_COMMON)
9779
9780 /******************************* PCD Instances *******************************/
9781 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
9782
9783 /******************************* QSPI Instances *******************************/
9784 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
9785
9786 /******************************* RNG Instances ********************************/
9787 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
9788
9789 /****************************** RTC Instances *********************************/
9790 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
9791
9792 /******************************** SAI Instances *******************************/
9793 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
9794 ((INSTANCE) == SAI1_Block_B) || \
9795 ((INSTANCE) == SAI2_Block_A) || \
9796 ((INSTANCE) == SAI2_Block_B))
9797
9798 /****************************** SDMMC Instances *******************************/
9799 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
9800
9801 /****************************** SMBUS Instances *******************************/
9802 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
9803 ((INSTANCE) == I2C2) || \
9804 ((INSTANCE) == I2C3))
9805
9806 /******************************** SPI Instances *******************************/
9807 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
9808 ((INSTANCE) == SPI2) || \
9809 ((INSTANCE) == SPI3))
9810
9811 /******************************** SWPMI Instances *****************************/
9812 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
9813
9814 /****************** LPTIM Instances : All supported instances *****************/
9815 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
9816 ((INSTANCE) == LPTIM2))
9817
9818 /****************** TIM Instances : All supported instances *******************/
9819 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9820 ((INSTANCE) == TIM2) || \
9821 ((INSTANCE) == TIM3) || \
9822 ((INSTANCE) == TIM4) || \
9823 ((INSTANCE) == TIM5) || \
9824 ((INSTANCE) == TIM6) || \
9825 ((INSTANCE) == TIM7) || \
9826 ((INSTANCE) == TIM8) || \
9827 ((INSTANCE) == TIM15) || \
9828 ((INSTANCE) == TIM16) || \
9829 ((INSTANCE) == TIM17))
9830
9831 /****************** TIM Instances : supporting 32 bits counter ****************/
9832 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
9833 ((INSTANCE) == TIM5))
9834
9835 /****************** TIM Instances : supporting the break function *************/
9836 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9837 ((INSTANCE) == TIM8) || \
9838 ((INSTANCE) == TIM15) || \
9839 ((INSTANCE) == TIM16) || \
9840 ((INSTANCE) == TIM17))
9841
9842 /************** TIM Instances : supporting Break source selection *************/
9843 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9844 ((INSTANCE) == TIM8) || \
9845 ((INSTANCE) == TIM15) || \
9846 ((INSTANCE) == TIM16) || \
9847 ((INSTANCE) == TIM17))
9848
9849 /****************** TIM Instances : supporting 2 break inputs *****************/
9850 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9851 ((INSTANCE) == TIM8))
9852
9853 /************* TIM Instances : at least 1 capture/compare channel *************/
9854 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9855 ((INSTANCE) == TIM2) || \
9856 ((INSTANCE) == TIM3) || \
9857 ((INSTANCE) == TIM4) || \
9858 ((INSTANCE) == TIM5) || \
9859 ((INSTANCE) == TIM8) || \
9860 ((INSTANCE) == TIM15) || \
9861 ((INSTANCE) == TIM16) || \
9862 ((INSTANCE) == TIM17))
9863
9864 /************ TIM Instances : at least 2 capture/compare channels *************/
9865 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9866 ((INSTANCE) == TIM2) || \
9867 ((INSTANCE) == TIM3) || \
9868 ((INSTANCE) == TIM4) || \
9869 ((INSTANCE) == TIM5) || \
9870 ((INSTANCE) == TIM8) || \
9871 ((INSTANCE) == TIM15))
9872
9873 /************ TIM Instances : at least 3 capture/compare channels *************/
9874 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9875 ((INSTANCE) == TIM2) || \
9876 ((INSTANCE) == TIM3) || \
9877 ((INSTANCE) == TIM4) || \
9878 ((INSTANCE) == TIM5) || \
9879 ((INSTANCE) == TIM8))
9880
9881 /************ TIM Instances : at least 4 capture/compare channels *************/
9882 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9883 ((INSTANCE) == TIM2) || \
9884 ((INSTANCE) == TIM3) || \
9885 ((INSTANCE) == TIM4) || \
9886 ((INSTANCE) == TIM5) || \
9887 ((INSTANCE) == TIM8))
9888
9889 /****************** TIM Instances : at least 5 capture/compare channels *******/
9890 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9891 ((INSTANCE) == TIM8))
9892
9893 /****************** TIM Instances : at least 6 capture/compare channels *******/
9894 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9895 ((INSTANCE) == TIM8))
9896
9897 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
9898 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9899 ((INSTANCE) == TIM8) || \
9900 ((INSTANCE) == TIM15) || \
9901 ((INSTANCE) == TIM16) || \
9902 ((INSTANCE) == TIM17))
9903
9904 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
9905 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9906 ((INSTANCE) == TIM2) || \
9907 ((INSTANCE) == TIM3) || \
9908 ((INSTANCE) == TIM4) || \
9909 ((INSTANCE) == TIM5) || \
9910 ((INSTANCE) == TIM6) || \
9911 ((INSTANCE) == TIM7) || \
9912 ((INSTANCE) == TIM8) || \
9913 ((INSTANCE) == TIM15) || \
9914 ((INSTANCE) == TIM16) || \
9915 ((INSTANCE) == TIM17))
9916
9917 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
9918 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9919 ((INSTANCE) == TIM2) || \
9920 ((INSTANCE) == TIM3) || \
9921 ((INSTANCE) == TIM4) || \
9922 ((INSTANCE) == TIM5) || \
9923 ((INSTANCE) == TIM8) || \
9924 ((INSTANCE) == TIM15) || \
9925 ((INSTANCE) == TIM16) || \
9926 ((INSTANCE) == TIM17))
9927
9928 /******************** TIM Instances : DMA burst feature ***********************/
9929 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9930 ((INSTANCE) == TIM2) || \
9931 ((INSTANCE) == TIM3) || \
9932 ((INSTANCE) == TIM4) || \
9933 ((INSTANCE) == TIM5) || \
9934 ((INSTANCE) == TIM8) || \
9935 ((INSTANCE) == TIM15) || \
9936 ((INSTANCE) == TIM16) || \
9937 ((INSTANCE) == TIM17))
9938
9939 /******************* TIM Instances : output(s) available **********************/
9940 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
9941 ((((INSTANCE) == TIM1) && \
9942 (((CHANNEL) == TIM_CHANNEL_1) || \
9943 ((CHANNEL) == TIM_CHANNEL_2) || \
9944 ((CHANNEL) == TIM_CHANNEL_3) || \
9945 ((CHANNEL) == TIM_CHANNEL_4) || \
9946 ((CHANNEL) == TIM_CHANNEL_5) || \
9947 ((CHANNEL) == TIM_CHANNEL_6))) \
9948 || \
9949 (((INSTANCE) == TIM2) && \
9950 (((CHANNEL) == TIM_CHANNEL_1) || \
9951 ((CHANNEL) == TIM_CHANNEL_2) || \
9952 ((CHANNEL) == TIM_CHANNEL_3) || \
9953 ((CHANNEL) == TIM_CHANNEL_4))) \
9954 || \
9955 (((INSTANCE) == TIM3) && \
9956 (((CHANNEL) == TIM_CHANNEL_1) || \
9957 ((CHANNEL) == TIM_CHANNEL_2) || \
9958 ((CHANNEL) == TIM_CHANNEL_3) || \
9959 ((CHANNEL) == TIM_CHANNEL_4))) \
9960 || \
9961 (((INSTANCE) == TIM4) && \
9962 (((CHANNEL) == TIM_CHANNEL_1) || \
9963 ((CHANNEL) == TIM_CHANNEL_2) || \
9964 ((CHANNEL) == TIM_CHANNEL_3) || \
9965 ((CHANNEL) == TIM_CHANNEL_4))) \
9966 || \
9967 (((INSTANCE) == TIM5) && \
9968 (((CHANNEL) == TIM_CHANNEL_1) || \
9969 ((CHANNEL) == TIM_CHANNEL_2) || \
9970 ((CHANNEL) == TIM_CHANNEL_3) || \
9971 ((CHANNEL) == TIM_CHANNEL_4))) \
9972 || \
9973 (((INSTANCE) == TIM8) && \
9974 (((CHANNEL) == TIM_CHANNEL_1) || \
9975 ((CHANNEL) == TIM_CHANNEL_2) || \
9976 ((CHANNEL) == TIM_CHANNEL_3) || \
9977 ((CHANNEL) == TIM_CHANNEL_4) || \
9978 ((CHANNEL) == TIM_CHANNEL_5) || \
9979 ((CHANNEL) == TIM_CHANNEL_6))) \
9980 || \
9981 (((INSTANCE) == TIM15) && \
9982 (((CHANNEL) == TIM_CHANNEL_1) || \
9983 ((CHANNEL) == TIM_CHANNEL_2))) \
9984 || \
9985 (((INSTANCE) == TIM16) && \
9986 (((CHANNEL) == TIM_CHANNEL_1))) \
9987 || \
9988 (((INSTANCE) == TIM17) && \
9989 (((CHANNEL) == TIM_CHANNEL_1))))
9990
9991 /****************** TIM Instances : supporting complementary output(s) ********/
9992 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
9993 ((((INSTANCE) == TIM1) && \
9994 (((CHANNEL) == TIM_CHANNEL_1) || \
9995 ((CHANNEL) == TIM_CHANNEL_2) || \
9996 ((CHANNEL) == TIM_CHANNEL_3))) \
9997 || \
9998 (((INSTANCE) == TIM8) && \
9999 (((CHANNEL) == TIM_CHANNEL_1) || \
10000 ((CHANNEL) == TIM_CHANNEL_2) || \
10001 ((CHANNEL) == TIM_CHANNEL_3))) \
10002 || \
10003 (((INSTANCE) == TIM15) && \
10004 ((CHANNEL) == TIM_CHANNEL_1)) \
10005 || \
10006 (((INSTANCE) == TIM16) && \
10007 ((CHANNEL) == TIM_CHANNEL_1)) \
10008 || \
10009 (((INSTANCE) == TIM17) && \
10010 ((CHANNEL) == TIM_CHANNEL_1)))
10011
10012 /****************** TIM Instances : supporting clock division *****************/
10013 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10014 ((INSTANCE) == TIM2) || \
10015 ((INSTANCE) == TIM3) || \
10016 ((INSTANCE) == TIM4) || \
10017 ((INSTANCE) == TIM5) || \
10018 ((INSTANCE) == TIM8) || \
10019 ((INSTANCE) == TIM15) || \
10020 ((INSTANCE) == TIM16) || \
10021 ((INSTANCE) == TIM17))
10022
10023 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
10024 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10025 ((INSTANCE) == TIM2) || \
10026 ((INSTANCE) == TIM3) || \
10027 ((INSTANCE) == TIM4) || \
10028 ((INSTANCE) == TIM5) || \
10029 ((INSTANCE) == TIM8) || \
10030 ((INSTANCE) == TIM15))
10031
10032 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
10033 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10034 ((INSTANCE) == TIM2) || \
10035 ((INSTANCE) == TIM3) || \
10036 ((INSTANCE) == TIM4) || \
10037 ((INSTANCE) == TIM5) || \
10038 ((INSTANCE) == TIM8))
10039
10040 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
10041 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10042 ((INSTANCE) == TIM2) || \
10043 ((INSTANCE) == TIM3) || \
10044 ((INSTANCE) == TIM4) || \
10045 ((INSTANCE) == TIM5) || \
10046 ((INSTANCE) == TIM8) || \
10047 ((INSTANCE) == TIM15))
10048
10049 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
10050 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10051 ((INSTANCE) == TIM2) || \
10052 ((INSTANCE) == TIM3) || \
10053 ((INSTANCE) == TIM4) || \
10054 ((INSTANCE) == TIM5) || \
10055 ((INSTANCE) == TIM8) || \
10056 ((INSTANCE) == TIM15))
10057
10058 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
10059 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10060 ((INSTANCE) == TIM8))
10061
10062 /****************** TIM Instances : supporting commutation event generation ***/
10063 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10064 ((INSTANCE) == TIM8) || \
10065 ((INSTANCE) == TIM15) || \
10066 ((INSTANCE) == TIM16) || \
10067 ((INSTANCE) == TIM17))
10068
10069 /****************** TIM Instances : supporting counting mode selection ********/
10070 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10071 ((INSTANCE) == TIM2) || \
10072 ((INSTANCE) == TIM3) || \
10073 ((INSTANCE) == TIM4) || \
10074 ((INSTANCE) == TIM5) || \
10075 ((INSTANCE) == TIM8))
10076
10077 /****************** TIM Instances : supporting encoder interface **************/
10078 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10079 ((INSTANCE) == TIM2) || \
10080 ((INSTANCE) == TIM3) || \
10081 ((INSTANCE) == TIM4) || \
10082 ((INSTANCE) == TIM5) || \
10083 ((INSTANCE) == TIM8))
10084
10085 /****************** TIM Instances : supporting Hall sensor interface **********/
10086 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10087 ((INSTANCE) == TIM2) || \
10088 ((INSTANCE) == TIM3) || \
10089 ((INSTANCE) == TIM4) || \
10090 ((INSTANCE) == TIM5))
10091
10092 /**************** TIM Instances : external trigger input available ************/
10093 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10094 ((INSTANCE) == TIM2) || \
10095 ((INSTANCE) == TIM3) || \
10096 ((INSTANCE) == TIM4) || \
10097 ((INSTANCE) == TIM5) || \
10098 ((INSTANCE) == TIM8))
10099
10100 /************* TIM Instances : supporting ETR source selection ***************/
10101 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10102 ((INSTANCE) == TIM2) || \
10103 ((INSTANCE) == TIM3) || \
10104 ((INSTANCE) == TIM8))
10105
10106 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
10107 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10108 ((INSTANCE) == TIM2) || \
10109 ((INSTANCE) == TIM3) || \
10110 ((INSTANCE) == TIM4) || \
10111 ((INSTANCE) == TIM5) || \
10112 ((INSTANCE) == TIM6) || \
10113 ((INSTANCE) == TIM7) || \
10114 ((INSTANCE) == TIM8) || \
10115 ((INSTANCE) == TIM15))
10116
10117 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
10118 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10119 ((INSTANCE) == TIM2) || \
10120 ((INSTANCE) == TIM3) || \
10121 ((INSTANCE) == TIM4) || \
10122 ((INSTANCE) == TIM5) || \
10123 ((INSTANCE) == TIM8) || \
10124 ((INSTANCE) == TIM15))
10125
10126 /****************** TIM Instances : supporting OCxREF clear *******************/
10127 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10128 ((INSTANCE) == TIM2) || \
10129 ((INSTANCE) == TIM3) || \
10130 ((INSTANCE) == TIM4) || \
10131 ((INSTANCE) == TIM5) || \
10132 ((INSTANCE) == TIM8))
10133
10134 /****************** TIM Instances : remapping capability **********************/
10135 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10136 ((INSTANCE) == TIM2) || \
10137 ((INSTANCE) == TIM3) || \
10138 ((INSTANCE) == TIM8) || \
10139 ((INSTANCE) == TIM15) || \
10140 ((INSTANCE) == TIM16) || \
10141 ((INSTANCE) == TIM17))
10142
10143 /****************** TIM Instances : supporting repetition counter *************/
10144 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10145 ((INSTANCE) == TIM8) || \
10146 ((INSTANCE) == TIM15) || \
10147 ((INSTANCE) == TIM16) || \
10148 ((INSTANCE) == TIM17))
10149
10150 /****************** TIM Instances : supporting synchronization ****************/
10151 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
10152
10153 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
10154 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10155 ((INSTANCE) == TIM8))
10156
10157 /******************* TIM Instances : Timer input XOR function *****************/
10158 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10159 ((INSTANCE) == TIM2) || \
10160 ((INSTANCE) == TIM3) || \
10161 ((INSTANCE) == TIM4) || \
10162 ((INSTANCE) == TIM5) || \
10163 ((INSTANCE) == TIM8) || \
10164 ((INSTANCE) == TIM15))
10165
10166 /****************************** TSC Instances *********************************/
10167 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
10168
10169 /******************** USART Instances : Synchronous mode **********************/
10170 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10171 ((INSTANCE) == USART2) || \
10172 ((INSTANCE) == USART3))
10173
10174 /******************** UART Instances : Asynchronous mode **********************/
10175 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10176 ((INSTANCE) == USART2) || \
10177 ((INSTANCE) == USART3) || \
10178 ((INSTANCE) == UART4) || \
10179 ((INSTANCE) == UART5))
10180
10181 /****************** UART Instances : Auto Baud Rate detection ****************/
10182 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10183 ((INSTANCE) == USART2) || \
10184 ((INSTANCE) == USART3) || \
10185 ((INSTANCE) == UART4) || \
10186 ((INSTANCE) == UART5))
10187
10188 /****************** UART Instances : Driver Enable *****************/
10189 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10190 ((INSTANCE) == USART2) || \
10191 ((INSTANCE) == USART3) || \
10192 ((INSTANCE) == UART4) || \
10193 ((INSTANCE) == UART5) || \
10194 ((INSTANCE) == LPUART1))
10195
10196 /******************** UART Instances : Half-Duplex mode **********************/
10197 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10198 ((INSTANCE) == USART2) || \
10199 ((INSTANCE) == USART3) || \
10200 ((INSTANCE) == UART4) || \
10201 ((INSTANCE) == UART5) || \
10202 ((INSTANCE) == LPUART1))
10203
10204 /****************** UART Instances : Hardware Flow control ********************/
10205 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10206 ((INSTANCE) == USART2) || \
10207 ((INSTANCE) == USART3) || \
10208 ((INSTANCE) == UART4) || \
10209 ((INSTANCE) == UART5) || \
10210 ((INSTANCE) == LPUART1))
10211
10212 /******************** UART Instances : LIN mode **********************/
10213 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10214 ((INSTANCE) == USART2) || \
10215 ((INSTANCE) == USART3) || \
10216 ((INSTANCE) == UART4) || \
10217 ((INSTANCE) == UART5))
10218
10219 /******************** UART Instances : Wake-up from Stop mode **********************/
10220 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10221 ((INSTANCE) == USART2) || \
10222 ((INSTANCE) == USART3) || \
10223 ((INSTANCE) == UART4) || \
10224 ((INSTANCE) == UART5) || \
10225 ((INSTANCE) == LPUART1))
10226
10227 /*********************** UART Instances : IRDA mode ***************************/
10228 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10229 ((INSTANCE) == USART2) || \
10230 ((INSTANCE) == USART3) || \
10231 ((INSTANCE) == UART4) || \
10232 ((INSTANCE) == UART5))
10233
10234 /********************* USART Instances : Smard card mode ***********************/
10235 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10236 ((INSTANCE) == USART2) || \
10237 ((INSTANCE) == USART3))
10238
10239 /******************** LPUART Instance *****************************************/
10240 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
10241
10242 /****************************** IWDG Instances ********************************/
10243 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
10244
10245 /****************************** WWDG Instances ********************************/
10246 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
10247
10248 /**
10249 * @}
10250 */
10251
10252
10253 /******************************************************************************/
10254 /* For a painless codes migration between the STM32L4xx device product */
10255 /* lines, the aliases defined below are put in place to overcome the */
10256 /* differences in the interrupt handlers and IRQn definitions. */
10257 /* No need to update developed interrupt code when moving across */
10258 /* product lines within the same STM32L4 Family */
10259 /******************************************************************************/
10260
10261 /* Aliases for __IRQn */
10262 #define TIM8_IRQn TIM8_UP_IRQn
10263
10264 /* Aliases for __IRQHandler */
10265 #define TIM8_IRQHandler TIM8_UP_IRQHandler
10266
10267
10268 #ifdef __cplusplus
10269 }
10270 #endif /* __cplusplus */
10271
10272 #endif /* __STM32L486xx_H */
10273
10274 /**
10275 * @}
10276 */
10277
10278 /**
10279 * @}
10280 */
10281
10282 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/