Mercurial > pub > halpp

comparison l476rg-hal-test/src/startup_stm32l486xx.s @ 0:32a3b1785697

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
parents
children
comparison
equal deleted inserted replaced
-1:000000000000 0:32a3b1785697
1 /**
2 ******************************************************************************
3 * @file startup_stm32l486xx.s
4 * @author MCD Application Team
5 * @version V1.0.3
6 * @date 29-January-2016
7 * @brief STM32L486xx devices vector table for GCC toolchain.
8 * This module performs:
9 * - Set the initial SP
10 * - Set the initial PC == Reset_Handler,
11 * - Set the vector table entries with the exceptions ISR address,
12 * - Configure the clock system
13 * - Branches to main in the C library (which eventually
14 * calls main()).
15 * After Reset the Cortex-M4 processor is in Thread mode,
16 * priority is Privileged, and the Stack is set to Main.
17 ******************************************************************************
18 * @attention
19 *
20 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
21 *
22 * Redistribution and use in source and binary forms, with or without modification,
23 * are permitted provided that the following conditions are met:
24 * 1. Redistributions of source code must retain the above copyright notice,
25 * this list of conditions and the following disclaimer.
26 * 2. Redistributions in binary form must reproduce the above copyright notice,
27 * this list of conditions and the following disclaimer in the documentation
28 * and/or other materials provided with the distribution.
29 * 3. Neither the name of STMicroelectronics nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
40 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
41 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
42 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *
44 ******************************************************************************
45 */
46
47 .syntax unified
48 .cpu cortex-m4
49 .fpu softvfp
50 .thumb
51
52 .global g_pfnVectors
53 .global Default_Handler
54
55 /* start address for the initialization values of the .data section.
56 defined in linker script */
57 .word _sidata
58 /* start address for the .data section. defined in linker script */
59 .word _sdata
60 /* end address for the .data section. defined in linker script */
61 .word _edata
62 /* start address for the .bss section. defined in linker script */
63 .word _sbss
64 /* end address for the .bss section. defined in linker script */
65 .word _ebss
66
67 .equ BootRAM, 0xF1E0F85F
68 /**
69 * @brief This is the code that gets called when the processor first
70 * starts execution following a reset event. Only the absolutely
71 * necessary set is performed, after which the application
72 * supplied main() routine is called.
73 * @param None
74 * @retval : None
75 */
76
77 .section .text.Reset_Handler
78 .weak Reset_Handler
79 .type Reset_Handler, %function
80 Reset_Handler:
81 ldr sp, =_estack /* Atollic update: set stack pointer */
82
83 /* Copy the data segment initializers from flash to SRAM */
84 movs r1, #0
85 b LoopCopyDataInit
86
87 CopyDataInit:
88 ldr r3, =_sidata
89 ldr r3, [r3, r1]
90 str r3, [r0, r1]
91 adds r1, r1, #4
92
93 LoopCopyDataInit:
94 ldr r0, =_sdata
95 ldr r3, =_edata
96 adds r2, r0, r1
97 cmp r2, r3
98 bcc CopyDataInit
99 ldr r2, =_sbss
100 b LoopFillZerobss
101 /* Zero fill the bss segment. */
102 FillZerobss:
103 movs r3, #0
104 str r3, [r2], #4
105
106 LoopFillZerobss:
107 ldr r3, = _ebss
108 cmp r2, r3
109 bcc FillZerobss
110
111 /* Call the clock system intitialization function.*/
112 bl SystemInit
113 /* Call static constructors */
114 bl __libc_init_array
115 /* Call the application's entry point.*/
116 bl main
117
118 LoopForever:
119 b LoopForever
120
121 .size Reset_Handler, .-Reset_Handler
122
123 /**
124 * @brief This is the code that gets called when the processor receives an
125 * unexpected interrupt. This simply enters an infinite loop, preserving
126 * the system state for examination by a debugger.
127 *
128 * @param None
129 * @retval : None
130 */
131 .section .text.Default_Handler,"ax",%progbits
132 Default_Handler:
133 Infinite_Loop:
134 b Infinite_Loop
135 .size Default_Handler, .-Default_Handler
136 /******************************************************************************
137 *
138 * The minimal vector table for a Cortex-M4. Note that the proper constructs
139 * must be placed on this to ensure that it ends up at physical address
140 * 0x0000.0000.
141 *
142 ******************************************************************************/
143 .section .isr_vector,"a",%progbits
144 .type g_pfnVectors, %object
145 .size g_pfnVectors, .-g_pfnVectors
146
147
148 g_pfnVectors:
149 .word _estack
150 .word Reset_Handler
151 .word NMI_Handler
152 .word HardFault_Handler
153 .word MemManage_Handler
154 .word BusFault_Handler
155 .word UsageFault_Handler
156 .word 0
157 .word 0
158 .word 0
159 .word 0
160 .word SVC_Handler
161 .word DebugMon_Handler
162 .word 0
163 .word PendSV_Handler
164 .word SysTick_Handler
165 .word WWDG_IRQHandler
166 .word PVD_PVM_IRQHandler
167 .word TAMP_STAMP_IRQHandler
168 .word RTC_WKUP_IRQHandler
169 .word FLASH_IRQHandler
170 .word RCC_IRQHandler
171 .word EXTI0_IRQHandler
172 .word EXTI1_IRQHandler
173 .word EXTI2_IRQHandler
174 .word EXTI3_IRQHandler
175 .word EXTI4_IRQHandler
176 .word DMA1_Channel1_IRQHandler
177 .word DMA1_Channel2_IRQHandler
178 .word DMA1_Channel3_IRQHandler
179 .word DMA1_Channel4_IRQHandler
180 .word DMA1_Channel5_IRQHandler
181 .word DMA1_Channel6_IRQHandler
182 .word DMA1_Channel7_IRQHandler
183 .word ADC1_2_IRQHandler
184 .word CAN1_TX_IRQHandler
185 .word CAN1_RX0_IRQHandler
186 .word CAN1_RX1_IRQHandler
187 .word CAN1_SCE_IRQHandler
188 .word EXTI9_5_IRQHandler
189 .word TIM1_BRK_TIM15_IRQHandler
190 .word TIM1_UP_TIM16_IRQHandler
191 .word TIM1_TRG_COM_TIM17_IRQHandler
192 .word TIM1_CC_IRQHandler
193 .word TIM2_IRQHandler
194 .word TIM3_IRQHandler
195 .word TIM4_IRQHandler
196 .word I2C1_EV_IRQHandler
197 .word I2C1_ER_IRQHandler
198 .word I2C2_EV_IRQHandler
199 .word I2C2_ER_IRQHandler
200 .word SPI1_IRQHandler
201 .word SPI2_IRQHandler
202 .word USART1_IRQHandler
203 .word USART2_IRQHandler
204 .word USART3_IRQHandler
205 .word EXTI15_10_IRQHandler
206 .word RTC_Alarm_IRQHandler
207 .word DFSDM3_IRQHandler
208 .word TIM8_BRK_IRQHandler
209 .word TIM8_UP_IRQHandler
210 .word TIM8_TRG_COM_IRQHandler
211 .word TIM8_CC_IRQHandler
212 .word ADC3_IRQHandler
213 .word FMC_IRQHandler
214 .word SDMMC1_IRQHandler
215 .word TIM5_IRQHandler
216 .word SPI3_IRQHandler
217 .word UART4_IRQHandler
218 .word UART5_IRQHandler
219 .word TIM6_DAC_IRQHandler
220 .word TIM7_IRQHandler
221 .word DMA2_Channel1_IRQHandler
222 .word DMA2_Channel2_IRQHandler
223 .word DMA2_Channel3_IRQHandler
224 .word DMA2_Channel4_IRQHandler
225 .word DMA2_Channel5_IRQHandler
226 .word DFSDM0_IRQHandler
227 .word DFSDM1_IRQHandler
228 .word DFSDM2_IRQHandler
229 .word COMP_IRQHandler
230 .word LPTIM1_IRQHandler
231 .word LPTIM2_IRQHandler
232 .word OTG_FS_IRQHandler
233 .word DMA2_Channel6_IRQHandler
234 .word DMA2_Channel7_IRQHandler
235 .word LPUART1_IRQHandler
236 .word QUADSPI_IRQHandler
237 .word I2C3_EV_IRQHandler
238 .word I2C3_ER_IRQHandler
239 .word SAI1_IRQHandler
240 .word SAI2_IRQHandler
241 .word SWPMI1_IRQHandler
242 .word TSC_IRQHandler
243 .word LCD_IRQHandler
244 .word AES_IRQHandler
245 .word RNG_IRQHandler
246 .word FPU_IRQHandler
247
248
249 /*******************************************************************************
250 *
251 * Provide weak aliases for each Exception handler to the Default_Handler.
252 * As they are weak aliases, any function with the same name will override
253 * this definition.
254 *
255 *******************************************************************************/
256
257 .weak NMI_Handler
258 .thumb_set NMI_Handler,Default_Handler
259
260 .weak HardFault_Handler
261 .thumb_set HardFault_Handler,Default_Handler
262
263 .weak MemManage_Handler
264 .thumb_set MemManage_Handler,Default_Handler
265
266 .weak BusFault_Handler
267 .thumb_set BusFault_Handler,Default_Handler
268
269 .weak UsageFault_Handler
270 .thumb_set UsageFault_Handler,Default_Handler
271
272 .weak SVC_Handler
273 .thumb_set SVC_Handler,Default_Handler
274
275 .weak DebugMon_Handler
276 .thumb_set DebugMon_Handler,Default_Handler
277
278 .weak PendSV_Handler
279 .thumb_set PendSV_Handler,Default_Handler
280
281 .weak SysTick_Handler
282 .thumb_set SysTick_Handler,Default_Handler
283
284 .weak WWDG_IRQHandler
285 .thumb_set WWDG_IRQHandler,Default_Handler
286
287 .weak PVD_PVM_IRQHandler
288 .thumb_set PVD_PVM_IRQHandler,Default_Handler
289
290 .weak TAMP_STAMP_IRQHandler
291 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
292
293 .weak RTC_WKUP_IRQHandler
294 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
295
296 .weak FLASH_IRQHandler
297 .thumb_set FLASH_IRQHandler,Default_Handler
298
299 .weak RCC_IRQHandler
300 .thumb_set RCC_IRQHandler,Default_Handler
301
302 .weak EXTI0_IRQHandler
303 .thumb_set EXTI0_IRQHandler,Default_Handler
304
305 .weak EXTI1_IRQHandler
306 .thumb_set EXTI1_IRQHandler,Default_Handler
307
308 .weak EXTI2_IRQHandler
309 .thumb_set EXTI2_IRQHandler,Default_Handler
310
311 .weak EXTI3_IRQHandler
312 .thumb_set EXTI3_IRQHandler,Default_Handler
313
314 .weak EXTI4_IRQHandler
315 .thumb_set EXTI4_IRQHandler,Default_Handler
316
317 .weak DMA1_Channel1_IRQHandler
318 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
319
320 .weak DMA1_Channel2_IRQHandler
321 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
322
323 .weak DMA1_Channel3_IRQHandler
324 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
325
326 .weak DMA1_Channel4_IRQHandler
327 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
328
329 .weak DMA1_Channel5_IRQHandler
330 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
331
332 .weak DMA1_Channel6_IRQHandler
333 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
334
335 .weak DMA1_Channel7_IRQHandler
336 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
337
338 .weak ADC1_2_IRQHandler
339 .thumb_set ADC1_2_IRQHandler,Default_Handler
340
341 .weak CAN1_TX_IRQHandler
342 .thumb_set CAN1_TX_IRQHandler,Default_Handler
343
344 .weak CAN1_RX0_IRQHandler
345 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
346
347 .weak CAN1_RX1_IRQHandler
348 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
349
350 .weak CAN1_SCE_IRQHandler
351 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
352
353 .weak EXTI9_5_IRQHandler
354 .thumb_set EXTI9_5_IRQHandler,Default_Handler
355
356 .weak TIM1_BRK_TIM15_IRQHandler
357 .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
358
359 .weak TIM1_UP_TIM16_IRQHandler
360 .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
361
362 .weak TIM1_TRG_COM_TIM17_IRQHandler
363 .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
364
365 .weak TIM1_CC_IRQHandler
366 .thumb_set TIM1_CC_IRQHandler,Default_Handler
367
368 .weak TIM2_IRQHandler
369 .thumb_set TIM2_IRQHandler,Default_Handler
370
371 .weak TIM3_IRQHandler
372 .thumb_set TIM3_IRQHandler,Default_Handler
373
374 .weak TIM4_IRQHandler
375 .thumb_set TIM4_IRQHandler,Default_Handler
376
377 .weak I2C1_EV_IRQHandler
378 .thumb_set I2C1_EV_IRQHandler,Default_Handler
379
380 .weak I2C1_ER_IRQHandler
381 .thumb_set I2C1_ER_IRQHandler,Default_Handler
382
383 .weak I2C2_EV_IRQHandler
384 .thumb_set I2C2_EV_IRQHandler,Default_Handler
385
386 .weak I2C2_ER_IRQHandler
387 .thumb_set I2C2_ER_IRQHandler,Default_Handler
388
389 .weak SPI1_IRQHandler
390 .thumb_set SPI1_IRQHandler,Default_Handler
391
392 .weak SPI2_IRQHandler
393 .thumb_set SPI2_IRQHandler,Default_Handler
394
395 .weak USART1_IRQHandler
396 .thumb_set USART1_IRQHandler,Default_Handler
397
398 .weak USART2_IRQHandler
399 .thumb_set USART2_IRQHandler,Default_Handler
400
401 .weak USART3_IRQHandler
402 .thumb_set USART3_IRQHandler,Default_Handler
403
404 .weak EXTI15_10_IRQHandler
405 .thumb_set EXTI15_10_IRQHandler,Default_Handler
406
407 .weak RTC_Alarm_IRQHandler
408 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
409
410 .weak DFSDM3_IRQHandler
411 .thumb_set DFSDM3_IRQHandler,Default_Handler
412
413 .weak TIM8_BRK_IRQHandler
414 .thumb_set TIM8_BRK_IRQHandler,Default_Handler
415
416 .weak TIM8_UP_IRQHandler
417 .thumb_set TIM8_UP_IRQHandler,Default_Handler
418
419 .weak TIM8_TRG_COM_IRQHandler
420 .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
421
422 .weak TIM8_CC_IRQHandler
423 .thumb_set TIM8_CC_IRQHandler,Default_Handler
424
425 .weak ADC3_IRQHandler
426 .thumb_set ADC3_IRQHandler,Default_Handler
427
428 .weak FMC_IRQHandler
429 .thumb_set FMC_IRQHandler,Default_Handler
430
431 .weak SDMMC1_IRQHandler
432 .thumb_set SDMMC1_IRQHandler,Default_Handler
433
434 .weak TIM5_IRQHandler
435 .thumb_set TIM5_IRQHandler,Default_Handler
436
437 .weak SPI3_IRQHandler
438 .thumb_set SPI3_IRQHandler,Default_Handler
439
440 .weak UART4_IRQHandler
441 .thumb_set UART4_IRQHandler,Default_Handler
442
443 .weak UART5_IRQHandler
444 .thumb_set UART5_IRQHandler,Default_Handler
445
446 .weak TIM6_DAC_IRQHandler
447 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
448
449 .weak TIM7_IRQHandler
450 .thumb_set TIM7_IRQHandler,Default_Handler
451
452 .weak DMA2_Channel1_IRQHandler
453 .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
454
455 .weak DMA2_Channel2_IRQHandler
456 .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
457
458 .weak DMA2_Channel3_IRQHandler
459 .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
460
461 .weak DMA2_Channel4_IRQHandler
462 .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
463
464 .weak DMA2_Channel5_IRQHandler
465 .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
466
467 .weak DFSDM0_IRQHandler
468 .thumb_set DFSDM0_IRQHandler,Default_Handler
469
470 .weak DFSDM1_IRQHandler
471 .thumb_set DFSDM1_IRQHandler,Default_Handler
472
473 .weak DFSDM2_IRQHandler
474 .thumb_set DFSDM2_IRQHandler,Default_Handler
475
476 .weak COMP_IRQHandler
477 .thumb_set COMP_IRQHandler,Default_Handler
478
479 .weak LPTIM1_IRQHandler
480 .thumb_set LPTIM1_IRQHandler,Default_Handler
481
482 .weak LPTIM2_IRQHandler
483 .thumb_set LPTIM2_IRQHandler,Default_Handler
484
485 .weak OTG_FS_IRQHandler
486 .thumb_set OTG_FS_IRQHandler,Default_Handler
487
488 .weak DMA2_Channel6_IRQHandler
489 .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
490
491 .weak DMA2_Channel7_IRQHandler
492 .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
493
494 .weak LPUART1_IRQHandler
495 .thumb_set LPUART1_IRQHandler,Default_Handler
496
497 .weak QUADSPI_IRQHandler
498 .thumb_set QUADSPI_IRQHandler,Default_Handler
499
500 .weak I2C3_EV_IRQHandler
501 .thumb_set I2C3_EV_IRQHandler,Default_Handler
502
503 .weak I2C3_ER_IRQHandler
504 .thumb_set I2C3_ER_IRQHandler,Default_Handler
505
506 .weak SAI1_IRQHandler
507 .thumb_set SAI1_IRQHandler,Default_Handler
508
509 .weak SAI2_IRQHandler
510 .thumb_set SAI2_IRQHandler,Default_Handler
511
512 .weak SWPMI1_IRQHandler
513 .thumb_set SWPMI1_IRQHandler,Default_Handler
514
515 .weak TSC_IRQHandler
516 .thumb_set TSC_IRQHandler,Default_Handler
517
518 .weak LCD_IRQHandler
519 .thumb_set LCD_IRQHandler,Default_Handler
520
521 .weak AES_IRQHandler
522 .thumb_set AES_IRQHandler,Default_Handler
523
524 .weak RNG_IRQHandler
525 .thumb_set RNG_IRQHandler,Default_Handler
526
527 .weak FPU_IRQHandler
528 .thumb_set FPU_IRQHandler,Default_Handler
529 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/