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comparison l476rg/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h @ 0:32a3b1785697

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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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-1:000000000000 0:32a3b1785697
1 /**
2 ******************************************************************************
3 * @file stm32l476xx.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 28-October-2016
7 * @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral’s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 /** @addtogroup CMSIS_Device
45 * @{
46 */
47
48 /** @addtogroup stm32l476xx
49 * @{
50 */
51
52 #ifndef __STM32L476xx_H
53 #define __STM32L476xx_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif /* __cplusplus */
58
59 /** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63 /**
64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
65 */
66 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
67 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
68 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
70 #define __FPU_PRESENT 1 /*!< FPU present */
71
72 /**
73 * @}
74 */
75
76 /** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80 /**
81 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
88 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
96 /****** STM32 specific Interrupt Numbers **********************************************************************/
97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
98 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
102 RCC_IRQn = 5, /*!< RCC global Interrupt */
103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
108 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
109 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
110 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
111 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
112 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
113 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
114 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
115 ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */
116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
121 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
122 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
123 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
139 DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */
140 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
141 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
142 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
144 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
145 FMC_IRQn = 48, /*!< FMC global Interrupt */
146 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
153 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
154 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
155 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
156 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
157 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
158 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
159 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
160 DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */
161 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
162 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
163 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
165 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
166 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
167 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
168 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
171 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
172 SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
173 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
174 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
175 LCD_IRQn = 78, /*!< LCD global interrupt */
176 RNG_IRQn = 80, /*!< RNG global interrupt */
177 FPU_IRQn = 81 /*!< FPU global interrupt */
178 } IRQn_Type;
179
180 /**
181 * @}
182 */
183
184 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
185 #include "system_stm32l4xx.h"
186 #include <stdint.h>
187
188 /** @addtogroup Peripheral_registers_structures
189 * @{
190 */
191
192 /**
193 * @brief Analog to Digital Converter
194 */
195
196 typedef struct
197 {
198 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
199 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
200 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
201 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
202 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
203 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
204 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
205 uint32_t RESERVED1; /*!< Reserved, 0x1C */
206 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
207 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
208 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
209 uint32_t RESERVED2; /*!< Reserved, 0x2C */
210 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
211 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
212 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
213 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
214 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
215 uint32_t RESERVED3; /*!< Reserved, 0x44 */
216 uint32_t RESERVED4; /*!< Reserved, 0x48 */
217 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
218 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
219 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
220 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
221 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
222 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
223 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
224 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
225 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
226 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
227 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
228 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
229 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
230 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
231 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
232 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
233 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
234 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
235
236 } ADC_TypeDef;
237
238 typedef struct
239 {
240 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
241 uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
242 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
243 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
244 } ADC_Common_TypeDef;
245
246
247 /**
248 * @brief Controller Area Network TxMailBox
249 */
250
251 typedef struct
252 {
253 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
254 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
255 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
256 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
257 } CAN_TxMailBox_TypeDef;
258
259 /**
260 * @brief Controller Area Network FIFOMailBox
261 */
262
263 typedef struct
264 {
265 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
266 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
267 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
268 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
269 } CAN_FIFOMailBox_TypeDef;
270
271 /**
272 * @brief Controller Area Network FilterRegister
273 */
274
275 typedef struct
276 {
277 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
278 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
279 } CAN_FilterRegister_TypeDef;
280
281 /**
282 * @brief Controller Area Network
283 */
284
285 typedef struct
286 {
287 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
288 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
289 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
290 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
291 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
292 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
293 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
294 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
295 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
296 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
297 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
298 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
299 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
300 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
301 uint32_t RESERVED2; /*!< Reserved, 0x208 */
302 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
303 uint32_t RESERVED3; /*!< Reserved, 0x210 */
304 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
305 uint32_t RESERVED4; /*!< Reserved, 0x218 */
306 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
307 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
308 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
309 } CAN_TypeDef;
310
311
312 /**
313 * @brief Comparator
314 */
315
316 typedef struct
317 {
318 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
319 } COMP_TypeDef;
320
321 typedef struct
322 {
323 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
324 } COMP_Common_TypeDef;
325
326 /**
327 * @brief CRC calculation unit
328 */
329
330 typedef struct
331 {
332 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
333 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
334 uint8_t RESERVED0; /*!< Reserved, 0x05 */
335 uint16_t RESERVED1; /*!< Reserved, 0x06 */
336 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
337 uint32_t RESERVED2; /*!< Reserved, 0x0C */
338 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
339 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
340 } CRC_TypeDef;
341
342 /**
343 * @brief Digital to Analog Converter
344 */
345
346 typedef struct
347 {
348 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
349 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
350 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
351 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
352 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
353 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
354 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
355 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
356 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
357 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
358 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
359 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
360 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
361 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
362 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
363 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
364 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
365 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
366 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
367 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
368 } DAC_TypeDef;
369
370 /**
371 * @brief DFSDM module registers
372 */
373 typedef struct
374 {
375 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
376 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
377 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
378 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
379 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
380 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
381 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
382 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
383 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
384 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
385 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
386 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
387 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
388 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
389 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
390 } DFSDM_Filter_TypeDef;
391
392 /**
393 * @brief DFSDM channel configuration registers
394 */
395 typedef struct
396 {
397 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
398 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
399 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
400 short circuit detector register, Address offset: 0x08 */
401 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
402 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
403 } DFSDM_Channel_TypeDef;
404
405 /**
406 * @brief Debug MCU
407 */
408
409 typedef struct
410 {
411 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
412 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
413 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
414 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
415 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
416 } DBGMCU_TypeDef;
417
418
419 /**
420 * @brief DMA Controller
421 */
422
423 typedef struct
424 {
425 __IO uint32_t CCR; /*!< DMA channel x configuration register */
426 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
427 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
428 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
429 } DMA_Channel_TypeDef;
430
431 typedef struct
432 {
433 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
434 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
435 } DMA_TypeDef;
436
437 typedef struct
438 {
439 __IO uint32_t CSELR; /*!< DMA channel selection register */
440 } DMA_Request_TypeDef;
441
442 /* Legacy define */
443 #define DMA_request_TypeDef DMA_Request_TypeDef
444
445
446 /**
447 * @brief External Interrupt/Event Controller
448 */
449
450 typedef struct
451 {
452 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
453 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
454 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
455 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
456 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
457 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
458 uint32_t RESERVED1; /*!< Reserved, 0x18 */
459 uint32_t RESERVED2; /*!< Reserved, 0x1C */
460 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
461 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
462 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
463 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
464 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
465 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
466 } EXTI_TypeDef;
467
468
469 /**
470 * @brief Firewall
471 */
472
473 typedef struct
474 {
475 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
476 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
477 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
478 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
479 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
480 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
481 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
482 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
483 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
484 } FIREWALL_TypeDef;
485
486
487 /**
488 * @brief FLASH Registers
489 */
490
491 typedef struct
492 {
493 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
494 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
495 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
496 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
497 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
498 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
499 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
500 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
501 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
502 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
503 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
504 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
505 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
506 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
507 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
508 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
509 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
510 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
511 } FLASH_TypeDef;
512
513
514 /**
515 * @brief Flexible Memory Controller
516 */
517
518 typedef struct
519 {
520 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
521 } FMC_Bank1_TypeDef;
522
523 /**
524 * @brief Flexible Memory Controller Bank1E
525 */
526
527 typedef struct
528 {
529 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
530 } FMC_Bank1E_TypeDef;
531
532 /**
533 * @brief Flexible Memory Controller Bank3
534 */
535
536 typedef struct
537 {
538 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
539 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
540 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
541 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
542 uint32_t RESERVED0; /*!< Reserved, 0x90 */
543 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
544 } FMC_Bank3_TypeDef;
545
546 /**
547 * @brief General Purpose I/O
548 */
549
550 typedef struct
551 {
552 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
553 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
554 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
555 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
556 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
557 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
558 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
559 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
560 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
561 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
562 __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */
563
564 } GPIO_TypeDef;
565
566
567 /**
568 * @brief Inter-integrated Circuit Interface
569 */
570
571 typedef struct
572 {
573 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
574 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
575 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
576 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
577 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
578 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
579 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
580 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
581 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
582 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
583 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
584 } I2C_TypeDef;
585
586 /**
587 * @brief Independent WATCHDOG
588 */
589
590 typedef struct
591 {
592 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
593 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
594 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
595 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
596 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
597 } IWDG_TypeDef;
598
599 /**
600 * @brief LCD
601 */
602
603 typedef struct
604 {
605 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
606 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
607 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
608 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
609 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
610 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
611 } LCD_TypeDef;
612
613 /**
614 * @brief LPTIMER
615 */
616 typedef struct
617 {
618 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
619 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
620 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
621 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
622 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
623 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
624 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
625 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
626 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
627 } LPTIM_TypeDef;
628
629 /**
630 * @brief Operational Amplifier (OPAMP)
631 */
632
633 typedef struct
634 {
635 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
636 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
637 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
638 } OPAMP_TypeDef;
639
640 typedef struct
641 {
642 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
643 } OPAMP_Common_TypeDef;
644
645 /**
646 * @brief Power Control
647 */
648
649 typedef struct
650 {
651 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
652 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
653 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
654 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
655 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
656 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
657 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
658 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
659 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
660 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
661 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
662 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
663 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
664 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
665 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
666 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
667 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
668 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
669 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
670 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
671 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
672 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
673 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
674 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
675 } PWR_TypeDef;
676
677
678 /**
679 * @brief QUAD Serial Peripheral Interface
680 */
681
682 typedef struct
683 {
684 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
685 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
686 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
687 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
688 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
689 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
690 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
691 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
692 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
693 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
694 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
695 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
696 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
697 } QUADSPI_TypeDef;
698
699
700 /**
701 * @brief Reset and Clock Control
702 */
703
704 typedef struct
705 {
706 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
707 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
708 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
709 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
710 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
711 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
712 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
713 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
714 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
715 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
716 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
717 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
718 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
719 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
720 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
721 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
722 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
723 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
724 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
725 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
726 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
727 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
728 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
729 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
730 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
731 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
732 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
733 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
734 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
735 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
736 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
737 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
738 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
739 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
740 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
741 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
742 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
743 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
744 } RCC_TypeDef;
745
746 /**
747 * @brief Real-Time Clock
748 */
749
750 typedef struct
751 {
752 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
753 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
754 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
755 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
756 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
757 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
758 uint32_t reserved; /*!< Reserved */
759 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
760 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
761 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
762 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
763 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
764 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
765 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
766 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
767 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
768 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
769 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
770 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
771 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
772 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
773 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
774 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
775 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
776 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
777 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
778 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
779 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
780 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
781 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
782 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
783 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
784 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
785 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
786 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
787 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
788 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
789 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
790 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
791 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
792 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
793 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
794 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
795 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
796 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
797 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
798 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
799 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
800 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
801 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
802 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
803 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
804 } RTC_TypeDef;
805
806
807 /**
808 * @brief Serial Audio Interface
809 */
810
811 typedef struct
812 {
813 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
814 } SAI_TypeDef;
815
816 typedef struct
817 {
818 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
819 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
820 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
821 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
822 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
823 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
824 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
825 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
826 } SAI_Block_TypeDef;
827
828
829 /**
830 * @brief Secure digital input/output Interface
831 */
832
833 typedef struct
834 {
835 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
836 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
837 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
838 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
839 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
840 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
841 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
842 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
843 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
844 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
845 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
846 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
847 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
848 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
849 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
850 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
851 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
852 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
853 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
854 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
855 } SDMMC_TypeDef;
856
857
858 /**
859 * @brief Serial Peripheral Interface
860 */
861
862 typedef struct
863 {
864 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
865 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
866 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
867 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
868 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
869 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
870 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
871 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
872 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
873 } SPI_TypeDef;
874
875
876 /**
877 * @brief Single Wire Protocol Master Interface SPWMI
878 */
879
880 typedef struct
881 {
882 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
883 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
884 uint32_t RESERVED1; /*!< Reserved, 0x08 */
885 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
886 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
887 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
888 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
889 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
890 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
891 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
892 } SWPMI_TypeDef;
893
894
895 /**
896 * @brief System configuration controller
897 */
898
899 typedef struct
900 {
901 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
902 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
903 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
904 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
905 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
906 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
907 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
908 } SYSCFG_TypeDef;
909
910
911 /**
912 * @brief TIM
913 */
914
915 typedef struct
916 {
917 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
918 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
919 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
920 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
921 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
922 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
923 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
924 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
925 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
926 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
927 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
928 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
929 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
930 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
931 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
932 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
933 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
934 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
935 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
936 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
937 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
938 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
939 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
940 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
941 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
942 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
943 } TIM_TypeDef;
944
945
946 /**
947 * @brief Touch Sensing Controller (TSC)
948 */
949
950 typedef struct
951 {
952 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
953 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
954 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
955 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
956 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
957 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
958 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
959 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
960 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
961 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
962 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
963 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
964 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
965 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
966 } TSC_TypeDef;
967
968 /**
969 * @brief Universal Synchronous Asynchronous Receiver Transmitter
970 */
971
972 typedef struct
973 {
974 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
975 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
976 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
977 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
978 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
979 uint16_t RESERVED2; /*!< Reserved, 0x12 */
980 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
981 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
982 uint16_t RESERVED3; /*!< Reserved, 0x1A */
983 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
984 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
985 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
986 uint16_t RESERVED4; /*!< Reserved, 0x26 */
987 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
988 uint16_t RESERVED5; /*!< Reserved, 0x2A */
989 } USART_TypeDef;
990
991 /**
992 * @brief VREFBUF
993 */
994
995 typedef struct
996 {
997 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
998 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
999 } VREFBUF_TypeDef;
1000
1001 /**
1002 * @brief Window WATCHDOG
1003 */
1004
1005 typedef struct
1006 {
1007 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1008 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1009 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1010 } WWDG_TypeDef;
1011
1012 /**
1013 * @brief RNG
1014 */
1015
1016 typedef struct
1017 {
1018 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1019 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1020 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1021 } RNG_TypeDef;
1022
1023 /**
1024 * @brief USB_OTG_Core_register
1025 */
1026 typedef struct
1027 {
1028 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
1029 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
1030 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
1031 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
1032 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
1033 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
1034 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
1035 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
1036 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
1037 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
1038 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
1039 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
1040 uint32_t Reserved30[2]; /* Reserved 030h*/
1041 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
1042 __IO uint32_t CID; /* User ID Register 03Ch*/
1043 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1044 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1045 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1046 __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
1047 uint32_t Reserved6; /* Reserved 050h*/
1048 __IO uint32_t GLPMCFG; /* LPM Register 054h*/
1049 __IO uint32_t GPWRDN; /* Power Down Register 058h*/
1050 __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
1051 __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
1052 uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
1053 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
1054 __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
1055 } USB_OTG_GlobalTypeDef;
1056
1057 /**
1058 * @brief USB_OTG_device_Registers
1059 */
1060 typedef struct
1061 {
1062 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
1063 __IO uint32_t DCTL; /* dev Control Register 804h*/
1064 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
1065 uint32_t Reserved0C; /* Reserved 80Ch*/
1066 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
1067 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
1068 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
1069 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
1070 uint32_t Reserved20; /* Reserved 820h*/
1071 uint32_t Reserved9; /* Reserved 824h*/
1072 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
1073 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
1074 __IO uint32_t DTHRCTL; /* dev thr 830h*/
1075 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
1076 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
1077 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
1078 uint32_t Reserved40; /* dedicated EP mask 840h*/
1079 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
1080 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
1081 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
1082 } USB_OTG_DeviceTypeDef;
1083
1084 /**
1085 * @brief USB_OTG_IN_Endpoint-Specific_Register
1086 */
1087 typedef struct
1088 {
1089 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
1090 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
1091 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
1092 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
1093 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
1094 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
1095 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
1096 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1097 } USB_OTG_INEndpointTypeDef;
1098
1099 /**
1100 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1101 */
1102 typedef struct
1103 {
1104 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1105 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1106 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1107 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1108 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1109 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1110 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1111 } USB_OTG_OUTEndpointTypeDef;
1112
1113 /**
1114 * @brief USB_OTG_Host_Mode_Register_Structures
1115 */
1116 typedef struct
1117 {
1118 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1119 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1120 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1121 uint32_t Reserved40C; /* Reserved 40Ch*/
1122 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1123 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1124 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1125 } USB_OTG_HostTypeDef;
1126
1127 /**
1128 * @brief USB_OTG_Host_Channel_Specific_Registers
1129 */
1130 typedef struct
1131 {
1132 __IO uint32_t HCCHAR;
1133 __IO uint32_t HCSPLT;
1134 __IO uint32_t HCINT;
1135 __IO uint32_t HCINTMSK;
1136 __IO uint32_t HCTSIZ;
1137 __IO uint32_t HCDMA;
1138 uint32_t Reserved[2];
1139 } USB_OTG_HostChannelTypeDef;
1140
1141 /**
1142 * @}
1143 */
1144
1145 /** @addtogroup Peripheral_memory_map
1146 * @{
1147 */
1148 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
1149 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */
1150 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
1151 #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
1152 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
1153 #define QSPI_BASE ((uint32_t)0x90000000U) /*!< QSPI memories accessible over AHB base address */
1154 #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
1155 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
1156 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
1157 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
1158 #define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
1159
1160 /* Legacy defines */
1161 #define SRAM_BASE SRAM1_BASE
1162 #define SRAM_BB_BASE SRAM1_BB_BASE
1163
1164 #define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
1165 #define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
1166
1167 /*!< Peripheral memory map */
1168 #define APB1PERIPH_BASE PERIPH_BASE
1169 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1170 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1171 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
1172
1173 #define FMC_BANK1 FMC_BASE
1174 #define FMC_BANK1_1 FMC_BANK1
1175 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
1176 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
1177 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
1178 #define FMC_BANK3 (FMC_BASE + 0x20000000U)
1179
1180 /*!< APB1 peripherals */
1181 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1182 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1183 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1184 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1185 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1186 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1187 #define LCD_BASE (APB1PERIPH_BASE + 0x2400U)
1188 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1189 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1190 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1191 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1192 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1193 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1194 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1195 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1196 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1197 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1198 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1199 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1200 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1201 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1202 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1203 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
1204 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
1205 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
1206 #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
1207 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
1208 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
1209 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
1210 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
1211
1212
1213 /*!< APB2 peripherals */
1214 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
1215 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
1216 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
1217 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
1218 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
1219 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
1220 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
1221 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
1222 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1223 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
1224 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
1225 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
1226 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
1227 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
1228 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
1229 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1230 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1231 #define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
1232 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
1233 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
1234 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
1235 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
1236 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
1237 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
1238 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
1239 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
1240 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
1241 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
1242 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
1243 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
1244 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
1245 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
1246 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
1247
1248 /*!< AHB1 peripherals */
1249 #define DMA1_BASE (AHB1PERIPH_BASE)
1250 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
1251 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
1252 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
1253 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1254 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
1255
1256
1257 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
1258 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
1259 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
1260 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
1261 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
1262 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
1263 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
1264 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
1265
1266
1267 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
1268 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
1269 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
1270 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
1271 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
1272 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
1273 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
1274 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
1275
1276
1277 /*!< AHB2 peripherals */
1278 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
1279 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
1280 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
1281 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
1282 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
1283 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
1284 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
1285 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
1286
1287 #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
1288
1289 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
1290 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U)
1291 #define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U)
1292 #define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
1293
1294
1295 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
1296
1297
1298 /*!< FMC Banks registers base address */
1299 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1300 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1301 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1302
1303 /* Debug MCU registers base address */
1304 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
1305
1306 /*!< USB registers base address */
1307 #define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
1308
1309 #define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
1310 #define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
1311 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
1312 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
1313 #define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
1314 #define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
1315 #define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
1316 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
1317 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
1318 #define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
1319 #define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
1320 #define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
1321
1322
1323 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
1324 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
1325 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
1326 /**
1327 * @}
1328 */
1329
1330 /** @addtogroup Peripheral_declaration
1331 * @{
1332 */
1333 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1334 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1335 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1336 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1337 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1338 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1339 #define LCD ((LCD_TypeDef *) LCD_BASE)
1340 #define RTC ((RTC_TypeDef *) RTC_BASE)
1341 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1342 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1343 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1344 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1345 #define USART2 ((USART_TypeDef *) USART2_BASE)
1346 #define USART3 ((USART_TypeDef *) USART3_BASE)
1347 #define UART4 ((USART_TypeDef *) UART4_BASE)
1348 #define UART5 ((USART_TypeDef *) UART5_BASE)
1349 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1350 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1351 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1352 #define CAN ((CAN_TypeDef *) CAN1_BASE)
1353 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1354 #define PWR ((PWR_TypeDef *) PWR_BASE)
1355 #define DAC ((DAC_TypeDef *) DAC1_BASE)
1356 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1357 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1358 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1359 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1360 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1361 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1362 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1363 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
1364 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1365
1366 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1367 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1368 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1369 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1370 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1371 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1372 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1373 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1374 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1375 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1376 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1377 #define USART1 ((USART_TypeDef *) USART1_BASE)
1378 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1379 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1380 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1381 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1382 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1383 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1384 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1385 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1386 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1387 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1388 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1389 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1390 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1391 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1392 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1393 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1394 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1395 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1396 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1397 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1398 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1399 /* Aliases to keep compatibility after DFSDM renaming */
1400 #define DFSDM_Channel0 DFSDM1_Channel0
1401 #define DFSDM_Channel1 DFSDM1_Channel1
1402 #define DFSDM_Channel2 DFSDM1_Channel2
1403 #define DFSDM_Channel3 DFSDM1_Channel3
1404 #define DFSDM_Channel4 DFSDM1_Channel4
1405 #define DFSDM_Channel5 DFSDM1_Channel5
1406 #define DFSDM_Channel6 DFSDM1_Channel6
1407 #define DFSDM_Channel7 DFSDM1_Channel7
1408 #define DFSDM_Filter0 DFSDM1_Filter0
1409 #define DFSDM_Filter1 DFSDM1_Filter1
1410 #define DFSDM_Filter2 DFSDM1_Filter2
1411 #define DFSDM_Filter3 DFSDM1_Filter3
1412 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1413 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1414 #define RCC ((RCC_TypeDef *) RCC_BASE)
1415 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1416 #define CRC ((CRC_TypeDef *) CRC_BASE)
1417 #define TSC ((TSC_TypeDef *) TSC_BASE)
1418
1419 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1420 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1421 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1422 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1423 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1424 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1425 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1426 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1427 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1428 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1429 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1430 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1431 #define RNG ((RNG_TypeDef *) RNG_BASE)
1432
1433
1434 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1435 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1436 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1437 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1438 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1439 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1440 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1441 #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
1442
1443
1444 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1445 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1446 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1447 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1448 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1449 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1450 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1451 #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
1452
1453
1454 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1455 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1456 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1457
1458 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1459
1460 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1461
1462 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1463 /**
1464 * @}
1465 */
1466
1467 /** @addtogroup Exported_constants
1468 * @{
1469 */
1470
1471 /** @addtogroup Peripheral_Registers_Bits_Definition
1472 * @{
1473 */
1474
1475 /******************************************************************************/
1476 /* Peripheral Registers_Bits_Definition */
1477 /******************************************************************************/
1478
1479 /******************************************************************************/
1480 /* */
1481 /* Analog to Digital Converter */
1482 /* */
1483 /******************************************************************************/
1484
1485 /*
1486 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1487 */
1488 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1489
1490 /******************** Bit definition for ADC_ISR register *******************/
1491 #define ADC_ISR_ADRDY_Pos (0U)
1492 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1493 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1494 #define ADC_ISR_EOSMP_Pos (1U)
1495 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1496 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1497 #define ADC_ISR_EOC_Pos (2U)
1498 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1499 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1500 #define ADC_ISR_EOS_Pos (3U)
1501 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1502 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1503 #define ADC_ISR_OVR_Pos (4U)
1504 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1505 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1506 #define ADC_ISR_JEOC_Pos (5U)
1507 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1508 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1509 #define ADC_ISR_JEOS_Pos (6U)
1510 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1511 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1512 #define ADC_ISR_AWD1_Pos (7U)
1513 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1514 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1515 #define ADC_ISR_AWD2_Pos (8U)
1516 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1517 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1518 #define ADC_ISR_AWD3_Pos (9U)
1519 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1520 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1521 #define ADC_ISR_JQOVF_Pos (10U)
1522 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1523 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1524
1525 /******************** Bit definition for ADC_IER register *******************/
1526 #define ADC_IER_ADRDYIE_Pos (0U)
1527 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1528 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1529 #define ADC_IER_EOSMPIE_Pos (1U)
1530 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1531 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1532 #define ADC_IER_EOCIE_Pos (2U)
1533 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1534 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1535 #define ADC_IER_EOSIE_Pos (3U)
1536 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1537 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1538 #define ADC_IER_OVRIE_Pos (4U)
1539 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1540 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1541 #define ADC_IER_JEOCIE_Pos (5U)
1542 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1543 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1544 #define ADC_IER_JEOSIE_Pos (6U)
1545 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1546 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1547 #define ADC_IER_AWD1IE_Pos (7U)
1548 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1549 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1550 #define ADC_IER_AWD2IE_Pos (8U)
1551 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1552 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1553 #define ADC_IER_AWD3IE_Pos (9U)
1554 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1555 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1556 #define ADC_IER_JQOVFIE_Pos (10U)
1557 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1558 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1559
1560 /* Legacy defines */
1561 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1562 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1563 #define ADC_IER_EOC (ADC_IER_EOCIE)
1564 #define ADC_IER_EOS (ADC_IER_EOSIE)
1565 #define ADC_IER_OVR (ADC_IER_OVRIE)
1566 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
1567 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
1568 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1569 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1570 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1571 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1572
1573 /******************** Bit definition for ADC_CR register ********************/
1574 #define ADC_CR_ADEN_Pos (0U)
1575 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1576 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1577 #define ADC_CR_ADDIS_Pos (1U)
1578 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1579 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1580 #define ADC_CR_ADSTART_Pos (2U)
1581 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1582 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1583 #define ADC_CR_JADSTART_Pos (3U)
1584 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1585 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1586 #define ADC_CR_ADSTP_Pos (4U)
1587 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1588 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1589 #define ADC_CR_JADSTP_Pos (5U)
1590 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1591 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1592 #define ADC_CR_ADVREGEN_Pos (28U)
1593 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1594 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1595 #define ADC_CR_DEEPPWD_Pos (29U)
1596 #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1597 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1598 #define ADC_CR_ADCALDIF_Pos (30U)
1599 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1600 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1601 #define ADC_CR_ADCAL_Pos (31U)
1602 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1603 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1604
1605 /******************** Bit definition for ADC_CFGR register ******************/
1606 #define ADC_CFGR_DMAEN_Pos (0U)
1607 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1608 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
1609 #define ADC_CFGR_DMACFG_Pos (1U)
1610 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1611 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
1612
1613 #define ADC_CFGR_RES_Pos (3U)
1614 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1615 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1616 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1617 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1618
1619 #define ADC_CFGR_ALIGN_Pos (5U)
1620 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1621 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1622
1623 #define ADC_CFGR_EXTSEL_Pos (6U)
1624 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
1625 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1626 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1627 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1628 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1629 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1630
1631 #define ADC_CFGR_EXTEN_Pos (10U)
1632 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1633 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1634 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1635 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1636
1637 #define ADC_CFGR_OVRMOD_Pos (12U)
1638 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1639 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1640 #define ADC_CFGR_CONT_Pos (13U)
1641 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1642 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1643 #define ADC_CFGR_AUTDLY_Pos (14U)
1644 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1645 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1646
1647 #define ADC_CFGR_DISCEN_Pos (16U)
1648 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1649 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1650
1651 #define ADC_CFGR_DISCNUM_Pos (17U)
1652 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1653 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
1654 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1655 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1656 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1657
1658 #define ADC_CFGR_JDISCEN_Pos (20U)
1659 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1660 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
1661 #define ADC_CFGR_JQM_Pos (21U)
1662 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1663 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1664 #define ADC_CFGR_AWD1SGL_Pos (22U)
1665 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1666 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1667 #define ADC_CFGR_AWD1EN_Pos (23U)
1668 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1669 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1670 #define ADC_CFGR_JAWD1EN_Pos (24U)
1671 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1672 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1673 #define ADC_CFGR_JAUTO_Pos (25U)
1674 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1675 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1676
1677 #define ADC_CFGR_AWD1CH_Pos (26U)
1678 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1679 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1680 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1681 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1682 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1683 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1684 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1685
1686 #define ADC_CFGR_JQDIS_Pos (31U)
1687 #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
1688 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1689
1690 /******************** Bit definition for ADC_CFGR2 register *****************/
1691 #define ADC_CFGR2_ROVSE_Pos (0U)
1692 #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1693 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1694 #define ADC_CFGR2_JOVSE_Pos (1U)
1695 #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1696 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1697
1698 #define ADC_CFGR2_OVSR_Pos (2U)
1699 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1700 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1701 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1702 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1703 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1704
1705 #define ADC_CFGR2_OVSS_Pos (5U)
1706 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1707 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1708 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1709 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1710 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1711 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1712
1713 #define ADC_CFGR2_TROVS_Pos (9U)
1714 #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
1715 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1716 #define ADC_CFGR2_ROVSM_Pos (10U)
1717 #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
1718 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1719
1720 /******************** Bit definition for ADC_SMPR1 register *****************/
1721 #define ADC_SMPR1_SMP0_Pos (0U)
1722 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1723 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1724 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1725 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1726 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1727
1728 #define ADC_SMPR1_SMP1_Pos (3U)
1729 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1730 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1731 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1732 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1733 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1734
1735 #define ADC_SMPR1_SMP2_Pos (6U)
1736 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1737 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1738 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1739 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1740 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1741
1742 #define ADC_SMPR1_SMP3_Pos (9U)
1743 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1744 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1745 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1746 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1747 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1748
1749 #define ADC_SMPR1_SMP4_Pos (12U)
1750 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1751 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1752 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1753 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1754 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1755
1756 #define ADC_SMPR1_SMP5_Pos (15U)
1757 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1758 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1759 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1760 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1761 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1762
1763 #define ADC_SMPR1_SMP6_Pos (18U)
1764 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1765 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1766 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1767 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1768 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1769
1770 #define ADC_SMPR1_SMP7_Pos (21U)
1771 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1772 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1773 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1774 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1775 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1776
1777 #define ADC_SMPR1_SMP8_Pos (24U)
1778 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1779 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1780 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1781 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1782 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1783
1784 #define ADC_SMPR1_SMP9_Pos (27U)
1785 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1786 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
1787 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
1788 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
1789 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
1790
1791 /******************** Bit definition for ADC_SMPR2 register *****************/
1792 #define ADC_SMPR2_SMP10_Pos (0U)
1793 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
1794 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
1795 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
1796 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
1797 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
1798
1799 #define ADC_SMPR2_SMP11_Pos (3U)
1800 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
1801 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
1802 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
1803 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
1804 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
1805
1806 #define ADC_SMPR2_SMP12_Pos (6U)
1807 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
1808 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
1809 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
1810 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
1811 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
1812
1813 #define ADC_SMPR2_SMP13_Pos (9U)
1814 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
1815 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
1816 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
1817 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
1818 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
1819
1820 #define ADC_SMPR2_SMP14_Pos (12U)
1821 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
1822 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
1823 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
1824 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
1825 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
1826
1827 #define ADC_SMPR2_SMP15_Pos (15U)
1828 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
1829 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
1830 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
1831 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
1832 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
1833
1834 #define ADC_SMPR2_SMP16_Pos (18U)
1835 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
1836 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
1837 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
1838 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
1839 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
1840
1841 #define ADC_SMPR2_SMP17_Pos (21U)
1842 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
1843 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
1844 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
1845 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
1846 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
1847
1848 #define ADC_SMPR2_SMP18_Pos (24U)
1849 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
1850 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
1851 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
1852 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
1853 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
1854
1855 /******************** Bit definition for ADC_TR1 register *******************/
1856 #define ADC_TR1_LT1_Pos (0U)
1857 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1858 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1859 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1860 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1861 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1862 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1863 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1864 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1865 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1866 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1867 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1868 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1869 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1870 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1871
1872 #define ADC_TR1_HT1_Pos (16U)
1873 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1874 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1875 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1876 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1877 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1878 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1879 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1880 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1881 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1882 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1883 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1884 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1885 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1886 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1887
1888 /******************** Bit definition for ADC_TR2 register *******************/
1889 #define ADC_TR2_LT2_Pos (0U)
1890 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
1891 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1892 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
1893 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
1894 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
1895 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
1896 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
1897 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
1898 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
1899 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
1900
1901 #define ADC_TR2_HT2_Pos (16U)
1902 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
1903 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1904 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
1905 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
1906 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
1907 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
1908 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
1909 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
1910 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
1911 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
1912
1913 /******************** Bit definition for ADC_TR3 register *******************/
1914 #define ADC_TR3_LT3_Pos (0U)
1915 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
1916 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1917 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
1918 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
1919 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
1920 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
1921 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
1922 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
1923 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
1924 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
1925
1926 #define ADC_TR3_HT3_Pos (16U)
1927 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
1928 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1929 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
1930 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
1931 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
1932 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
1933 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
1934 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
1935 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
1936 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
1937
1938 /******************** Bit definition for ADC_SQR1 register ******************/
1939 #define ADC_SQR1_L_Pos (0U)
1940 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
1941 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
1942 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
1943 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
1944 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
1945 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
1946
1947 #define ADC_SQR1_SQ1_Pos (6U)
1948 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
1949 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
1950 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
1951 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
1952 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
1953 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
1954 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
1955
1956 #define ADC_SQR1_SQ2_Pos (12U)
1957 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
1958 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
1959 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
1960 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
1961 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
1962 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
1963 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
1964
1965 #define ADC_SQR1_SQ3_Pos (18U)
1966 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
1967 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
1968 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
1969 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
1970 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
1971 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
1972 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
1973
1974 #define ADC_SQR1_SQ4_Pos (24U)
1975 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
1976 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
1977 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
1978 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
1979 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
1980 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
1981 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
1982
1983 /******************** Bit definition for ADC_SQR2 register ******************/
1984 #define ADC_SQR2_SQ5_Pos (0U)
1985 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
1986 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
1987 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
1988 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
1989 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
1990 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
1991 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
1992
1993 #define ADC_SQR2_SQ6_Pos (6U)
1994 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
1995 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
1996 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
1997 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
1998 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
1999 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
2000 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
2001
2002 #define ADC_SQR2_SQ7_Pos (12U)
2003 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
2004 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
2005 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
2006 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
2007 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
2008 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
2009 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
2010
2011 #define ADC_SQR2_SQ8_Pos (18U)
2012 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
2013 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
2014 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
2015 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
2016 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
2017 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
2018 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
2019
2020 #define ADC_SQR2_SQ9_Pos (24U)
2021 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
2022 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
2023 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
2024 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
2025 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
2026 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
2027 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
2028
2029 /******************** Bit definition for ADC_SQR3 register ******************/
2030 #define ADC_SQR3_SQ10_Pos (0U)
2031 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
2032 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
2033 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
2034 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
2035 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
2036 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
2037 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
2038
2039 #define ADC_SQR3_SQ11_Pos (6U)
2040 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
2041 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
2042 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
2043 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
2044 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
2045 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
2046 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
2047
2048 #define ADC_SQR3_SQ12_Pos (12U)
2049 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
2050 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
2051 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
2052 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
2053 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
2054 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
2055 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
2056
2057 #define ADC_SQR3_SQ13_Pos (18U)
2058 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
2059 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
2060 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
2061 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
2062 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
2063 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
2064 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
2065
2066 #define ADC_SQR3_SQ14_Pos (24U)
2067 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
2068 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
2069 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
2070 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
2071 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
2072 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
2073 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
2074
2075 /******************** Bit definition for ADC_SQR4 register ******************/
2076 #define ADC_SQR4_SQ15_Pos (0U)
2077 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
2078 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
2079 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
2080 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
2081 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
2082 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
2083 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
2084
2085 #define ADC_SQR4_SQ16_Pos (6U)
2086 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
2087 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
2088 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
2089 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
2090 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
2091 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
2092 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
2093
2094 /******************** Bit definition for ADC_DR register ********************/
2095 #define ADC_DR_RDATA_Pos (0U)
2096 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
2097 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
2098 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
2099 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
2100 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
2101 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
2102 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
2103 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
2104 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
2105 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
2106 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
2107 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
2108 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
2109 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
2110 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
2111 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
2112 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
2113 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
2114
2115 /******************** Bit definition for ADC_JSQR register ******************/
2116 #define ADC_JSQR_JL_Pos (0U)
2117 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
2118 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
2119 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
2120 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
2121
2122 #define ADC_JSQR_JEXTSEL_Pos (2U)
2123 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
2124 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
2125 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
2126 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
2127 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
2128 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
2129
2130 #define ADC_JSQR_JEXTEN_Pos (6U)
2131 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
2132 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
2133 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
2134 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
2135
2136 #define ADC_JSQR_JSQ1_Pos (8U)
2137 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
2138 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
2139 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
2140 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
2141 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
2142 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
2143 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
2144
2145 #define ADC_JSQR_JSQ2_Pos (14U)
2146 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
2147 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
2148 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
2149 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
2150 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
2151 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
2152 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
2153
2154 #define ADC_JSQR_JSQ3_Pos (20U)
2155 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
2156 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
2157 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
2158 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
2159 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
2160 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
2161 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
2162
2163 #define ADC_JSQR_JSQ4_Pos (26U)
2164 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
2165 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
2166 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
2167 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
2168 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
2169 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
2170 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
2171
2172
2173 /******************** Bit definition for ADC_OFR1 register ******************/
2174 #define ADC_OFR1_OFFSET1_Pos (0U)
2175 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
2176 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
2177 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
2178 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
2179 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
2180 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
2181 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
2182 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
2183 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
2184 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
2185 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
2186 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
2187 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
2188 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
2189
2190 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
2191 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
2192 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
2193 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
2194 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
2195 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
2196 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
2197 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
2198
2199 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
2200 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
2201 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
2202
2203 /******************** Bit definition for ADC_OFR2 register ******************/
2204 #define ADC_OFR2_OFFSET2_Pos (0U)
2205 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
2206 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
2207 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
2208 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
2209 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
2210 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
2211 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
2212 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
2213 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
2214 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
2215 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
2216 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
2217 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
2218 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
2219
2220 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
2221 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
2222 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
2223 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
2224 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
2225 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
2226 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
2227 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
2228
2229 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
2230 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
2231 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
2232
2233 /******************** Bit definition for ADC_OFR3 register ******************/
2234 #define ADC_OFR3_OFFSET3_Pos (0U)
2235 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
2236 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
2237 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
2238 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
2239 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
2240 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
2241 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
2242 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
2243 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
2244 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
2245 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
2246 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
2247 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
2248 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
2249
2250 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
2251 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
2252 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
2253 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
2254 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
2255 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
2256 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
2257 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
2258
2259 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
2260 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
2261 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
2262
2263 /******************** Bit definition for ADC_OFR4 register ******************/
2264 #define ADC_OFR4_OFFSET4_Pos (0U)
2265 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
2266 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
2267 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
2268 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
2269 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
2270 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
2271 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
2272 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
2273 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
2274 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
2275 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
2276 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
2277 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
2278 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
2279
2280 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
2281 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
2282 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
2283 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
2284 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
2285 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
2286 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
2287 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
2288
2289 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
2290 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
2291 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
2292
2293 /******************** Bit definition for ADC_JDR1 register ******************/
2294 #define ADC_JDR1_JDATA_Pos (0U)
2295 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
2296 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
2297 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
2298 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
2299 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
2300 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
2301 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
2302 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
2303 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
2304 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
2305 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
2306 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
2307 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
2308 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
2309 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
2310 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
2311 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
2312 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
2313
2314 /******************** Bit definition for ADC_JDR2 register ******************/
2315 #define ADC_JDR2_JDATA_Pos (0U)
2316 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
2317 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
2318 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
2319 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
2320 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
2321 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
2322 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
2323 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
2324 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
2325 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
2326 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
2327 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
2328 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
2329 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
2330 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
2331 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
2332 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
2333 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
2334
2335 /******************** Bit definition for ADC_JDR3 register ******************/
2336 #define ADC_JDR3_JDATA_Pos (0U)
2337 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
2338 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
2339 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
2340 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
2341 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
2342 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
2343 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
2344 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
2345 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
2346 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
2347 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
2348 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
2349 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
2350 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
2351 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
2352 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
2353 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
2354 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
2355
2356 /******************** Bit definition for ADC_JDR4 register ******************/
2357 #define ADC_JDR4_JDATA_Pos (0U)
2358 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
2359 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
2360 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
2361 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
2362 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
2363 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
2364 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
2365 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
2366 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
2367 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
2368 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
2369 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
2370 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
2371 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
2372 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
2373 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
2374 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
2375 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
2376
2377 /******************** Bit definition for ADC_AWD2CR register ****************/
2378 #define ADC_AWD2CR_AWD2CH_Pos (0U)
2379 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
2380 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
2381 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
2382 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
2383 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
2384 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
2385 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
2386 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
2387 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
2388 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
2389 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
2390 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
2391 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
2392 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
2393 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
2394 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
2395 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
2396 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
2397 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
2398 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
2399 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
2400
2401 /******************** Bit definition for ADC_AWD3CR register ****************/
2402 #define ADC_AWD3CR_AWD3CH_Pos (0U)
2403 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
2404 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
2405 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
2406 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
2407 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
2408 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
2409 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
2410 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
2411 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
2412 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
2413 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
2414 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
2415 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
2416 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
2417 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
2418 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
2419 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
2420 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
2421 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
2422 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
2423 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
2424
2425 /******************** Bit definition for ADC_DIFSEL register ****************/
2426 #define ADC_DIFSEL_DIFSEL_Pos (0U)
2427 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
2428 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
2429 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
2430 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
2431 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
2432 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
2433 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
2434 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
2435 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
2436 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
2437 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
2438 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
2439 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
2440 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
2441 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
2442 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
2443 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
2444 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
2445 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
2446 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
2447 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
2448
2449 /******************** Bit definition for ADC_CALFACT register ***************/
2450 #define ADC_CALFACT_CALFACT_S_Pos (0U)
2451 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
2452 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2453 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
2454 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
2455 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
2456 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
2457 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
2458 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
2459 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
2460
2461 #define ADC_CALFACT_CALFACT_D_Pos (16U)
2462 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
2463 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
2464 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
2465 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
2466 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
2467 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
2468 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2469 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2470 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
2471
2472 /************************* ADC Common registers *****************************/
2473 /******************** Bit definition for ADC_CSR register *******************/
2474 #define ADC_CSR_ADRDY_MST_Pos (0U)
2475 #define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
2476 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
2477 #define ADC_CSR_EOSMP_MST_Pos (1U)
2478 #define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
2479 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
2480 #define ADC_CSR_EOC_MST_Pos (2U)
2481 #define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
2482 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
2483 #define ADC_CSR_EOS_MST_Pos (3U)
2484 #define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
2485 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
2486 #define ADC_CSR_OVR_MST_Pos (4U)
2487 #define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
2488 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
2489 #define ADC_CSR_JEOC_MST_Pos (5U)
2490 #define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
2491 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
2492 #define ADC_CSR_JEOS_MST_Pos (6U)
2493 #define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
2494 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
2495 #define ADC_CSR_AWD1_MST_Pos (7U)
2496 #define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
2497 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
2498 #define ADC_CSR_AWD2_MST_Pos (8U)
2499 #define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
2500 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
2501 #define ADC_CSR_AWD3_MST_Pos (9U)
2502 #define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
2503 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
2504 #define ADC_CSR_JQOVF_MST_Pos (10U)
2505 #define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
2506 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
2507
2508 #define ADC_CSR_ADRDY_SLV_Pos (16U)
2509 #define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
2510 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
2511 #define ADC_CSR_EOSMP_SLV_Pos (17U)
2512 #define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
2513 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
2514 #define ADC_CSR_EOC_SLV_Pos (18U)
2515 #define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
2516 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
2517 #define ADC_CSR_EOS_SLV_Pos (19U)
2518 #define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
2519 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
2520 #define ADC_CSR_OVR_SLV_Pos (20U)
2521 #define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
2522 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
2523 #define ADC_CSR_JEOC_SLV_Pos (21U)
2524 #define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
2525 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
2526 #define ADC_CSR_JEOS_SLV_Pos (22U)
2527 #define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
2528 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
2529 #define ADC_CSR_AWD1_SLV_Pos (23U)
2530 #define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
2531 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
2532 #define ADC_CSR_AWD2_SLV_Pos (24U)
2533 #define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
2534 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
2535 #define ADC_CSR_AWD3_SLV_Pos (25U)
2536 #define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
2537 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
2538 #define ADC_CSR_JQOVF_SLV_Pos (26U)
2539 #define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
2540 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
2541
2542 /******************** Bit definition for ADC_CCR register *******************/
2543 #define ADC_CCR_DUAL_Pos (0U)
2544 #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
2545 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
2546 #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
2547 #define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
2548 #define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
2549 #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
2550 #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
2551
2552 #define ADC_CCR_DELAY_Pos (8U)
2553 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2554 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
2555 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2556 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2557 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2558 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2559
2560 #define ADC_CCR_DMACFG_Pos (13U)
2561 #define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
2562 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
2563
2564 #define ADC_CCR_MDMA_Pos (14U)
2565 #define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
2566 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
2567 #define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
2568 #define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
2569
2570 #define ADC_CCR_CKMODE_Pos (16U)
2571 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2572 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2573 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2574 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2575
2576 #define ADC_CCR_PRESC_Pos (18U)
2577 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
2578 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
2579 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
2580 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
2581 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
2582 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
2583
2584 #define ADC_CCR_VREFEN_Pos (22U)
2585 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2586 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2587 #define ADC_CCR_TSEN_Pos (23U)
2588 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
2589 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
2590 #define ADC_CCR_VBATEN_Pos (24U)
2591 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
2592 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
2593
2594 /******************** Bit definition for ADC_CDR register *******************/
2595 #define ADC_CDR_RDATA_MST_Pos (0U)
2596 #define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
2597 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
2598 #define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
2599 #define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
2600 #define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
2601 #define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
2602 #define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
2603 #define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
2604 #define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
2605 #define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
2606 #define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
2607 #define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
2608 #define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
2609 #define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
2610 #define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
2611 #define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
2612 #define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
2613 #define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
2614
2615 #define ADC_CDR_RDATA_SLV_Pos (16U)
2616 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
2617 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
2618 #define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
2619 #define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
2620 #define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
2621 #define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
2622 #define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
2623 #define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
2624 #define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
2625 #define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
2626 #define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
2627 #define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
2628 #define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
2629 #define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
2630 #define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
2631 #define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
2632 #define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
2633 #define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
2634
2635 /******************************************************************************/
2636 /* */
2637 /* Controller Area Network */
2638 /* */
2639 /******************************************************************************/
2640 /*!<CAN control and status registers */
2641 /******************* Bit definition for CAN_MCR register ********************/
2642 #define CAN_MCR_INRQ_Pos (0U)
2643 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2644 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2645 #define CAN_MCR_SLEEP_Pos (1U)
2646 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2647 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2648 #define CAN_MCR_TXFP_Pos (2U)
2649 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2650 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2651 #define CAN_MCR_RFLM_Pos (3U)
2652 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2653 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2654 #define CAN_MCR_NART_Pos (4U)
2655 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2656 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2657 #define CAN_MCR_AWUM_Pos (5U)
2658 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2659 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2660 #define CAN_MCR_ABOM_Pos (6U)
2661 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2662 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2663 #define CAN_MCR_TTCM_Pos (7U)
2664 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2665 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2666 #define CAN_MCR_RESET_Pos (15U)
2667 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2668 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2669
2670 /******************* Bit definition for CAN_MSR register ********************/
2671 #define CAN_MSR_INAK_Pos (0U)
2672 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2673 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2674 #define CAN_MSR_SLAK_Pos (1U)
2675 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2676 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2677 #define CAN_MSR_ERRI_Pos (2U)
2678 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2679 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2680 #define CAN_MSR_WKUI_Pos (3U)
2681 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2682 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2683 #define CAN_MSR_SLAKI_Pos (4U)
2684 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2685 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2686 #define CAN_MSR_TXM_Pos (8U)
2687 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2688 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2689 #define CAN_MSR_RXM_Pos (9U)
2690 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2691 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2692 #define CAN_MSR_SAMP_Pos (10U)
2693 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2694 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2695 #define CAN_MSR_RX_Pos (11U)
2696 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2697 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2698
2699 /******************* Bit definition for CAN_TSR register ********************/
2700 #define CAN_TSR_RQCP0_Pos (0U)
2701 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2702 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2703 #define CAN_TSR_TXOK0_Pos (1U)
2704 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2705 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2706 #define CAN_TSR_ALST0_Pos (2U)
2707 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2708 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2709 #define CAN_TSR_TERR0_Pos (3U)
2710 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2711 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2712 #define CAN_TSR_ABRQ0_Pos (7U)
2713 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2714 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2715 #define CAN_TSR_RQCP1_Pos (8U)
2716 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2717 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2718 #define CAN_TSR_TXOK1_Pos (9U)
2719 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2720 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2721 #define CAN_TSR_ALST1_Pos (10U)
2722 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2723 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2724 #define CAN_TSR_TERR1_Pos (11U)
2725 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2726 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2727 #define CAN_TSR_ABRQ1_Pos (15U)
2728 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2729 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2730 #define CAN_TSR_RQCP2_Pos (16U)
2731 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2732 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2733 #define CAN_TSR_TXOK2_Pos (17U)
2734 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2735 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2736 #define CAN_TSR_ALST2_Pos (18U)
2737 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2738 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2739 #define CAN_TSR_TERR2_Pos (19U)
2740 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2741 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2742 #define CAN_TSR_ABRQ2_Pos (23U)
2743 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2744 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2745 #define CAN_TSR_CODE_Pos (24U)
2746 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2747 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2748
2749 #define CAN_TSR_TME_Pos (26U)
2750 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2751 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2752 #define CAN_TSR_TME0_Pos (26U)
2753 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2754 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2755 #define CAN_TSR_TME1_Pos (27U)
2756 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2757 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2758 #define CAN_TSR_TME2_Pos (28U)
2759 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2760 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2761
2762 #define CAN_TSR_LOW_Pos (29U)
2763 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2764 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2765 #define CAN_TSR_LOW0_Pos (29U)
2766 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2767 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2768 #define CAN_TSR_LOW1_Pos (30U)
2769 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2770 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2771 #define CAN_TSR_LOW2_Pos (31U)
2772 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2773 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2774
2775 /******************* Bit definition for CAN_RF0R register *******************/
2776 #define CAN_RF0R_FMP0_Pos (0U)
2777 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2778 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2779 #define CAN_RF0R_FULL0_Pos (3U)
2780 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2781 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2782 #define CAN_RF0R_FOVR0_Pos (4U)
2783 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2784 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2785 #define CAN_RF0R_RFOM0_Pos (5U)
2786 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2787 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2788
2789 /******************* Bit definition for CAN_RF1R register *******************/
2790 #define CAN_RF1R_FMP1_Pos (0U)
2791 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2792 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2793 #define CAN_RF1R_FULL1_Pos (3U)
2794 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2795 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2796 #define CAN_RF1R_FOVR1_Pos (4U)
2797 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2798 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2799 #define CAN_RF1R_RFOM1_Pos (5U)
2800 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2801 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2802
2803 /******************** Bit definition for CAN_IER register *******************/
2804 #define CAN_IER_TMEIE_Pos (0U)
2805 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2806 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2807 #define CAN_IER_FMPIE0_Pos (1U)
2808 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2809 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2810 #define CAN_IER_FFIE0_Pos (2U)
2811 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2812 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2813 #define CAN_IER_FOVIE0_Pos (3U)
2814 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2815 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2816 #define CAN_IER_FMPIE1_Pos (4U)
2817 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2818 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2819 #define CAN_IER_FFIE1_Pos (5U)
2820 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2821 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2822 #define CAN_IER_FOVIE1_Pos (6U)
2823 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2824 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2825 #define CAN_IER_EWGIE_Pos (8U)
2826 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2827 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2828 #define CAN_IER_EPVIE_Pos (9U)
2829 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2830 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2831 #define CAN_IER_BOFIE_Pos (10U)
2832 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2833 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2834 #define CAN_IER_LECIE_Pos (11U)
2835 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2836 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2837 #define CAN_IER_ERRIE_Pos (15U)
2838 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2839 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2840 #define CAN_IER_WKUIE_Pos (16U)
2841 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2842 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2843 #define CAN_IER_SLKIE_Pos (17U)
2844 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2845 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2846
2847 /******************** Bit definition for CAN_ESR register *******************/
2848 #define CAN_ESR_EWGF_Pos (0U)
2849 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2850 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2851 #define CAN_ESR_EPVF_Pos (1U)
2852 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2853 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2854 #define CAN_ESR_BOFF_Pos (2U)
2855 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2856 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2857
2858 #define CAN_ESR_LEC_Pos (4U)
2859 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2860 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2861 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2862 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2863 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2864
2865 #define CAN_ESR_TEC_Pos (16U)
2866 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2867 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2868 #define CAN_ESR_REC_Pos (24U)
2869 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2870 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2871
2872 /******************* Bit definition for CAN_BTR register ********************/
2873 #define CAN_BTR_BRP_Pos (0U)
2874 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2875 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2876 #define CAN_BTR_TS1_Pos (16U)
2877 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2878 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2879 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2880 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2881 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2882 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2883 #define CAN_BTR_TS2_Pos (20U)
2884 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2885 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2886 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2887 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2888 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2889 #define CAN_BTR_SJW_Pos (24U)
2890 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2891 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2892 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2893 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2894 #define CAN_BTR_LBKM_Pos (30U)
2895 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2896 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2897 #define CAN_BTR_SILM_Pos (31U)
2898 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2899 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2900
2901 /*!<Mailbox registers */
2902 /****************** Bit definition for CAN_TI0R register ********************/
2903 #define CAN_TI0R_TXRQ_Pos (0U)
2904 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2905 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2906 #define CAN_TI0R_RTR_Pos (1U)
2907 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2908 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2909 #define CAN_TI0R_IDE_Pos (2U)
2910 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2911 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2912 #define CAN_TI0R_EXID_Pos (3U)
2913 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2914 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2915 #define CAN_TI0R_STID_Pos (21U)
2916 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2917 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2918
2919 /****************** Bit definition for CAN_TDT0R register *******************/
2920 #define CAN_TDT0R_DLC_Pos (0U)
2921 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2922 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2923 #define CAN_TDT0R_TGT_Pos (8U)
2924 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2925 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2926 #define CAN_TDT0R_TIME_Pos (16U)
2927 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2928 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2929
2930 /****************** Bit definition for CAN_TDL0R register *******************/
2931 #define CAN_TDL0R_DATA0_Pos (0U)
2932 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2933 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2934 #define CAN_TDL0R_DATA1_Pos (8U)
2935 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2936 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2937 #define CAN_TDL0R_DATA2_Pos (16U)
2938 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2939 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2940 #define CAN_TDL0R_DATA3_Pos (24U)
2941 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2942 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2943
2944 /****************** Bit definition for CAN_TDH0R register *******************/
2945 #define CAN_TDH0R_DATA4_Pos (0U)
2946 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2947 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2948 #define CAN_TDH0R_DATA5_Pos (8U)
2949 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2950 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2951 #define CAN_TDH0R_DATA6_Pos (16U)
2952 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2953 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2954 #define CAN_TDH0R_DATA7_Pos (24U)
2955 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2956 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2957
2958 /******************* Bit definition for CAN_TI1R register *******************/
2959 #define CAN_TI1R_TXRQ_Pos (0U)
2960 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2961 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2962 #define CAN_TI1R_RTR_Pos (1U)
2963 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2964 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2965 #define CAN_TI1R_IDE_Pos (2U)
2966 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2967 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2968 #define CAN_TI1R_EXID_Pos (3U)
2969 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2970 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2971 #define CAN_TI1R_STID_Pos (21U)
2972 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2973 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2974
2975 /******************* Bit definition for CAN_TDT1R register ******************/
2976 #define CAN_TDT1R_DLC_Pos (0U)
2977 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2978 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2979 #define CAN_TDT1R_TGT_Pos (8U)
2980 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2981 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2982 #define CAN_TDT1R_TIME_Pos (16U)
2983 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2984 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2985
2986 /******************* Bit definition for CAN_TDL1R register ******************/
2987 #define CAN_TDL1R_DATA0_Pos (0U)
2988 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2989 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2990 #define CAN_TDL1R_DATA1_Pos (8U)
2991 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2992 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2993 #define CAN_TDL1R_DATA2_Pos (16U)
2994 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2995 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2996 #define CAN_TDL1R_DATA3_Pos (24U)
2997 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2998 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2999
3000 /******************* Bit definition for CAN_TDH1R register ******************/
3001 #define CAN_TDH1R_DATA4_Pos (0U)
3002 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
3003 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
3004 #define CAN_TDH1R_DATA5_Pos (8U)
3005 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3006 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
3007 #define CAN_TDH1R_DATA6_Pos (16U)
3008 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3009 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
3010 #define CAN_TDH1R_DATA7_Pos (24U)
3011 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
3012 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
3013
3014 /******************* Bit definition for CAN_TI2R register *******************/
3015 #define CAN_TI2R_TXRQ_Pos (0U)
3016 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
3017 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
3018 #define CAN_TI2R_RTR_Pos (1U)
3019 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
3020 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
3021 #define CAN_TI2R_IDE_Pos (2U)
3022 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
3023 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
3024 #define CAN_TI2R_EXID_Pos (3U)
3025 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
3026 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
3027 #define CAN_TI2R_STID_Pos (21U)
3028 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
3029 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3030
3031 /******************* Bit definition for CAN_TDT2R register ******************/
3032 #define CAN_TDT2R_DLC_Pos (0U)
3033 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
3034 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
3035 #define CAN_TDT2R_TGT_Pos (8U)
3036 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
3037 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
3038 #define CAN_TDT2R_TIME_Pos (16U)
3039 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
3040 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
3041
3042 /******************* Bit definition for CAN_TDL2R register ******************/
3043 #define CAN_TDL2R_DATA0_Pos (0U)
3044 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
3045 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
3046 #define CAN_TDL2R_DATA1_Pos (8U)
3047 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
3048 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
3049 #define CAN_TDL2R_DATA2_Pos (16U)
3050 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
3051 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
3052 #define CAN_TDL2R_DATA3_Pos (24U)
3053 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
3054 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
3055
3056 /******************* Bit definition for CAN_TDH2R register ******************/
3057 #define CAN_TDH2R_DATA4_Pos (0U)
3058 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
3059 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
3060 #define CAN_TDH2R_DATA5_Pos (8U)
3061 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
3062 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
3063 #define CAN_TDH2R_DATA6_Pos (16U)
3064 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
3065 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
3066 #define CAN_TDH2R_DATA7_Pos (24U)
3067 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
3068 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
3069
3070 /******************* Bit definition for CAN_RI0R register *******************/
3071 #define CAN_RI0R_RTR_Pos (1U)
3072 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
3073 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
3074 #define CAN_RI0R_IDE_Pos (2U)
3075 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
3076 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
3077 #define CAN_RI0R_EXID_Pos (3U)
3078 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
3079 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
3080 #define CAN_RI0R_STID_Pos (21U)
3081 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
3082 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3083
3084 /******************* Bit definition for CAN_RDT0R register ******************/
3085 #define CAN_RDT0R_DLC_Pos (0U)
3086 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
3087 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
3088 #define CAN_RDT0R_FMI_Pos (8U)
3089 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
3090 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
3091 #define CAN_RDT0R_TIME_Pos (16U)
3092 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
3093 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
3094
3095 /******************* Bit definition for CAN_RDL0R register ******************/
3096 #define CAN_RDL0R_DATA0_Pos (0U)
3097 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
3098 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
3099 #define CAN_RDL0R_DATA1_Pos (8U)
3100 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
3101 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
3102 #define CAN_RDL0R_DATA2_Pos (16U)
3103 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
3104 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
3105 #define CAN_RDL0R_DATA3_Pos (24U)
3106 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
3107 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
3108
3109 /******************* Bit definition for CAN_RDH0R register ******************/
3110 #define CAN_RDH0R_DATA4_Pos (0U)
3111 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
3112 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
3113 #define CAN_RDH0R_DATA5_Pos (8U)
3114 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
3115 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
3116 #define CAN_RDH0R_DATA6_Pos (16U)
3117 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
3118 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
3119 #define CAN_RDH0R_DATA7_Pos (24U)
3120 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
3121 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
3122
3123 /******************* Bit definition for CAN_RI1R register *******************/
3124 #define CAN_RI1R_RTR_Pos (1U)
3125 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
3126 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
3127 #define CAN_RI1R_IDE_Pos (2U)
3128 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
3129 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
3130 #define CAN_RI1R_EXID_Pos (3U)
3131 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
3132 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
3133 #define CAN_RI1R_STID_Pos (21U)
3134 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
3135 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3136
3137 /******************* Bit definition for CAN_RDT1R register ******************/
3138 #define CAN_RDT1R_DLC_Pos (0U)
3139 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
3140 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
3141 #define CAN_RDT1R_FMI_Pos (8U)
3142 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
3143 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
3144 #define CAN_RDT1R_TIME_Pos (16U)
3145 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
3146 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
3147
3148 /******************* Bit definition for CAN_RDL1R register ******************/
3149 #define CAN_RDL1R_DATA0_Pos (0U)
3150 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
3151 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
3152 #define CAN_RDL1R_DATA1_Pos (8U)
3153 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
3154 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
3155 #define CAN_RDL1R_DATA2_Pos (16U)
3156 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
3157 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
3158 #define CAN_RDL1R_DATA3_Pos (24U)
3159 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
3160 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
3161
3162 /******************* Bit definition for CAN_RDH1R register ******************/
3163 #define CAN_RDH1R_DATA4_Pos (0U)
3164 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
3165 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
3166 #define CAN_RDH1R_DATA5_Pos (8U)
3167 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3168 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
3169 #define CAN_RDH1R_DATA6_Pos (16U)
3170 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3171 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
3172 #define CAN_RDH1R_DATA7_Pos (24U)
3173 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
3174 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
3175
3176 /*!<CAN filter registers */
3177 /******************* Bit definition for CAN_FMR register ********************/
3178 #define CAN_FMR_FINIT_Pos (0U)
3179 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
3180 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
3181
3182 /******************* Bit definition for CAN_FM1R register *******************/
3183 #define CAN_FM1R_FBM_Pos (0U)
3184 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
3185 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
3186 #define CAN_FM1R_FBM0_Pos (0U)
3187 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
3188 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
3189 #define CAN_FM1R_FBM1_Pos (1U)
3190 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
3191 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
3192 #define CAN_FM1R_FBM2_Pos (2U)
3193 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
3194 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
3195 #define CAN_FM1R_FBM3_Pos (3U)
3196 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
3197 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
3198 #define CAN_FM1R_FBM4_Pos (4U)
3199 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
3200 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
3201 #define CAN_FM1R_FBM5_Pos (5U)
3202 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
3203 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
3204 #define CAN_FM1R_FBM6_Pos (6U)
3205 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
3206 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
3207 #define CAN_FM1R_FBM7_Pos (7U)
3208 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
3209 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
3210 #define CAN_FM1R_FBM8_Pos (8U)
3211 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
3212 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
3213 #define CAN_FM1R_FBM9_Pos (9U)
3214 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
3215 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
3216 #define CAN_FM1R_FBM10_Pos (10U)
3217 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
3218 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
3219 #define CAN_FM1R_FBM11_Pos (11U)
3220 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
3221 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
3222 #define CAN_FM1R_FBM12_Pos (12U)
3223 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
3224 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
3225 #define CAN_FM1R_FBM13_Pos (13U)
3226 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
3227 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
3228
3229 /******************* Bit definition for CAN_FS1R register *******************/
3230 #define CAN_FS1R_FSC_Pos (0U)
3231 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
3232 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
3233 #define CAN_FS1R_FSC0_Pos (0U)
3234 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
3235 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
3236 #define CAN_FS1R_FSC1_Pos (1U)
3237 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
3238 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
3239 #define CAN_FS1R_FSC2_Pos (2U)
3240 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
3241 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
3242 #define CAN_FS1R_FSC3_Pos (3U)
3243 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
3244 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
3245 #define CAN_FS1R_FSC4_Pos (4U)
3246 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
3247 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
3248 #define CAN_FS1R_FSC5_Pos (5U)
3249 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
3250 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
3251 #define CAN_FS1R_FSC6_Pos (6U)
3252 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
3253 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
3254 #define CAN_FS1R_FSC7_Pos (7U)
3255 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
3256 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
3257 #define CAN_FS1R_FSC8_Pos (8U)
3258 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
3259 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
3260 #define CAN_FS1R_FSC9_Pos (9U)
3261 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
3262 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
3263 #define CAN_FS1R_FSC10_Pos (10U)
3264 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
3265 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
3266 #define CAN_FS1R_FSC11_Pos (11U)
3267 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
3268 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
3269 #define CAN_FS1R_FSC12_Pos (12U)
3270 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
3271 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
3272 #define CAN_FS1R_FSC13_Pos (13U)
3273 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
3274 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
3275
3276 /****************** Bit definition for CAN_FFA1R register *******************/
3277 #define CAN_FFA1R_FFA_Pos (0U)
3278 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
3279 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
3280 #define CAN_FFA1R_FFA0_Pos (0U)
3281 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
3282 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
3283 #define CAN_FFA1R_FFA1_Pos (1U)
3284 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
3285 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
3286 #define CAN_FFA1R_FFA2_Pos (2U)
3287 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
3288 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
3289 #define CAN_FFA1R_FFA3_Pos (3U)
3290 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
3291 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
3292 #define CAN_FFA1R_FFA4_Pos (4U)
3293 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
3294 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
3295 #define CAN_FFA1R_FFA5_Pos (5U)
3296 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
3297 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
3298 #define CAN_FFA1R_FFA6_Pos (6U)
3299 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
3300 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
3301 #define CAN_FFA1R_FFA7_Pos (7U)
3302 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
3303 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
3304 #define CAN_FFA1R_FFA8_Pos (8U)
3305 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
3306 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
3307 #define CAN_FFA1R_FFA9_Pos (9U)
3308 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
3309 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
3310 #define CAN_FFA1R_FFA10_Pos (10U)
3311 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
3312 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
3313 #define CAN_FFA1R_FFA11_Pos (11U)
3314 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
3315 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
3316 #define CAN_FFA1R_FFA12_Pos (12U)
3317 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
3318 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
3319 #define CAN_FFA1R_FFA13_Pos (13U)
3320 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
3321 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
3322
3323 /******************* Bit definition for CAN_FA1R register *******************/
3324 #define CAN_FA1R_FACT_Pos (0U)
3325 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
3326 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
3327 #define CAN_FA1R_FACT0_Pos (0U)
3328 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
3329 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
3330 #define CAN_FA1R_FACT1_Pos (1U)
3331 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
3332 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
3333 #define CAN_FA1R_FACT2_Pos (2U)
3334 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
3335 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
3336 #define CAN_FA1R_FACT3_Pos (3U)
3337 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
3338 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
3339 #define CAN_FA1R_FACT4_Pos (4U)
3340 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
3341 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
3342 #define CAN_FA1R_FACT5_Pos (5U)
3343 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
3344 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
3345 #define CAN_FA1R_FACT6_Pos (6U)
3346 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
3347 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
3348 #define CAN_FA1R_FACT7_Pos (7U)
3349 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
3350 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
3351 #define CAN_FA1R_FACT8_Pos (8U)
3352 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
3353 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
3354 #define CAN_FA1R_FACT9_Pos (9U)
3355 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
3356 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
3357 #define CAN_FA1R_FACT10_Pos (10U)
3358 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
3359 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
3360 #define CAN_FA1R_FACT11_Pos (11U)
3361 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
3362 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
3363 #define CAN_FA1R_FACT12_Pos (12U)
3364 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
3365 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
3366 #define CAN_FA1R_FACT13_Pos (13U)
3367 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
3368 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
3369
3370 /******************* Bit definition for CAN_F0R1 register *******************/
3371 #define CAN_F0R1_FB0_Pos (0U)
3372 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
3373 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
3374 #define CAN_F0R1_FB1_Pos (1U)
3375 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
3376 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
3377 #define CAN_F0R1_FB2_Pos (2U)
3378 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
3379 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
3380 #define CAN_F0R1_FB3_Pos (3U)
3381 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
3382 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
3383 #define CAN_F0R1_FB4_Pos (4U)
3384 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
3385 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
3386 #define CAN_F0R1_FB5_Pos (5U)
3387 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
3388 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
3389 #define CAN_F0R1_FB6_Pos (6U)
3390 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
3391 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
3392 #define CAN_F0R1_FB7_Pos (7U)
3393 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
3394 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
3395 #define CAN_F0R1_FB8_Pos (8U)
3396 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
3397 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
3398 #define CAN_F0R1_FB9_Pos (9U)
3399 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
3400 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
3401 #define CAN_F0R1_FB10_Pos (10U)
3402 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
3403 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
3404 #define CAN_F0R1_FB11_Pos (11U)
3405 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
3406 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
3407 #define CAN_F0R1_FB12_Pos (12U)
3408 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
3409 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
3410 #define CAN_F0R1_FB13_Pos (13U)
3411 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
3412 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
3413 #define CAN_F0R1_FB14_Pos (14U)
3414 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
3415 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
3416 #define CAN_F0R1_FB15_Pos (15U)
3417 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3418 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3419 #define CAN_F0R1_FB16_Pos (16U)
3420 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3421 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3422 #define CAN_F0R1_FB17_Pos (17U)
3423 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3424 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3425 #define CAN_F0R1_FB18_Pos (18U)
3426 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3427 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3428 #define CAN_F0R1_FB19_Pos (19U)
3429 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3430 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3431 #define CAN_F0R1_FB20_Pos (20U)
3432 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3433 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3434 #define CAN_F0R1_FB21_Pos (21U)
3435 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3436 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3437 #define CAN_F0R1_FB22_Pos (22U)
3438 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3439 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3440 #define CAN_F0R1_FB23_Pos (23U)
3441 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3442 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3443 #define CAN_F0R1_FB24_Pos (24U)
3444 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3445 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3446 #define CAN_F0R1_FB25_Pos (25U)
3447 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3448 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3449 #define CAN_F0R1_FB26_Pos (26U)
3450 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3451 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3452 #define CAN_F0R1_FB27_Pos (27U)
3453 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3454 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3455 #define CAN_F0R1_FB28_Pos (28U)
3456 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3457 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3458 #define CAN_F0R1_FB29_Pos (29U)
3459 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3460 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3461 #define CAN_F0R1_FB30_Pos (30U)
3462 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3463 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3464 #define CAN_F0R1_FB31_Pos (31U)
3465 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3466 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3467
3468 /******************* Bit definition for CAN_F1R1 register *******************/
3469 #define CAN_F1R1_FB0_Pos (0U)
3470 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3471 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3472 #define CAN_F1R1_FB1_Pos (1U)
3473 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3474 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3475 #define CAN_F1R1_FB2_Pos (2U)
3476 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3477 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3478 #define CAN_F1R1_FB3_Pos (3U)
3479 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3480 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3481 #define CAN_F1R1_FB4_Pos (4U)
3482 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3483 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3484 #define CAN_F1R1_FB5_Pos (5U)
3485 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3486 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3487 #define CAN_F1R1_FB6_Pos (6U)
3488 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3489 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3490 #define CAN_F1R1_FB7_Pos (7U)
3491 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3492 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3493 #define CAN_F1R1_FB8_Pos (8U)
3494 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3495 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3496 #define CAN_F1R1_FB9_Pos (9U)
3497 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3498 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3499 #define CAN_F1R1_FB10_Pos (10U)
3500 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3501 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3502 #define CAN_F1R1_FB11_Pos (11U)
3503 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3504 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3505 #define CAN_F1R1_FB12_Pos (12U)
3506 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3507 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3508 #define CAN_F1R1_FB13_Pos (13U)
3509 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3510 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3511 #define CAN_F1R1_FB14_Pos (14U)
3512 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3513 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3514 #define CAN_F1R1_FB15_Pos (15U)
3515 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3516 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3517 #define CAN_F1R1_FB16_Pos (16U)
3518 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3519 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3520 #define CAN_F1R1_FB17_Pos (17U)
3521 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3522 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3523 #define CAN_F1R1_FB18_Pos (18U)
3524 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3525 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3526 #define CAN_F1R1_FB19_Pos (19U)
3527 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3528 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3529 #define CAN_F1R1_FB20_Pos (20U)
3530 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3531 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3532 #define CAN_F1R1_FB21_Pos (21U)
3533 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3534 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3535 #define CAN_F1R1_FB22_Pos (22U)
3536 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3537 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3538 #define CAN_F1R1_FB23_Pos (23U)
3539 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3540 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3541 #define CAN_F1R1_FB24_Pos (24U)
3542 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3543 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3544 #define CAN_F1R1_FB25_Pos (25U)
3545 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3546 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3547 #define CAN_F1R1_FB26_Pos (26U)
3548 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3549 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3550 #define CAN_F1R1_FB27_Pos (27U)
3551 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3552 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3553 #define CAN_F1R1_FB28_Pos (28U)
3554 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3555 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3556 #define CAN_F1R1_FB29_Pos (29U)
3557 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3558 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3559 #define CAN_F1R1_FB30_Pos (30U)
3560 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3561 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3562 #define CAN_F1R1_FB31_Pos (31U)
3563 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3564 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3565
3566 /******************* Bit definition for CAN_F2R1 register *******************/
3567 #define CAN_F2R1_FB0_Pos (0U)
3568 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3569 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3570 #define CAN_F2R1_FB1_Pos (1U)
3571 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3572 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3573 #define CAN_F2R1_FB2_Pos (2U)
3574 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3575 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3576 #define CAN_F2R1_FB3_Pos (3U)
3577 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3578 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3579 #define CAN_F2R1_FB4_Pos (4U)
3580 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3581 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3582 #define CAN_F2R1_FB5_Pos (5U)
3583 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3584 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3585 #define CAN_F2R1_FB6_Pos (6U)
3586 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3587 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3588 #define CAN_F2R1_FB7_Pos (7U)
3589 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3590 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3591 #define CAN_F2R1_FB8_Pos (8U)
3592 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3593 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3594 #define CAN_F2R1_FB9_Pos (9U)
3595 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3596 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3597 #define CAN_F2R1_FB10_Pos (10U)
3598 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3599 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3600 #define CAN_F2R1_FB11_Pos (11U)
3601 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3602 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3603 #define CAN_F2R1_FB12_Pos (12U)
3604 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3605 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3606 #define CAN_F2R1_FB13_Pos (13U)
3607 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3608 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3609 #define CAN_F2R1_FB14_Pos (14U)
3610 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3611 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3612 #define CAN_F2R1_FB15_Pos (15U)
3613 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3614 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3615 #define CAN_F2R1_FB16_Pos (16U)
3616 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3617 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3618 #define CAN_F2R1_FB17_Pos (17U)
3619 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3620 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3621 #define CAN_F2R1_FB18_Pos (18U)
3622 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3623 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3624 #define CAN_F2R1_FB19_Pos (19U)
3625 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3626 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3627 #define CAN_F2R1_FB20_Pos (20U)
3628 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3629 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3630 #define CAN_F2R1_FB21_Pos (21U)
3631 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3632 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3633 #define CAN_F2R1_FB22_Pos (22U)
3634 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3635 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3636 #define CAN_F2R1_FB23_Pos (23U)
3637 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3638 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3639 #define CAN_F2R1_FB24_Pos (24U)
3640 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3641 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3642 #define CAN_F2R1_FB25_Pos (25U)
3643 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3644 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3645 #define CAN_F2R1_FB26_Pos (26U)
3646 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3647 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3648 #define CAN_F2R1_FB27_Pos (27U)
3649 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3650 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3651 #define CAN_F2R1_FB28_Pos (28U)
3652 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3653 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3654 #define CAN_F2R1_FB29_Pos (29U)
3655 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3656 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3657 #define CAN_F2R1_FB30_Pos (30U)
3658 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3659 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3660 #define CAN_F2R1_FB31_Pos (31U)
3661 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3662 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3663
3664 /******************* Bit definition for CAN_F3R1 register *******************/
3665 #define CAN_F3R1_FB0_Pos (0U)
3666 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3667 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3668 #define CAN_F3R1_FB1_Pos (1U)
3669 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3670 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3671 #define CAN_F3R1_FB2_Pos (2U)
3672 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3673 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3674 #define CAN_F3R1_FB3_Pos (3U)
3675 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3676 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3677 #define CAN_F3R1_FB4_Pos (4U)
3678 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3679 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3680 #define CAN_F3R1_FB5_Pos (5U)
3681 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3682 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3683 #define CAN_F3R1_FB6_Pos (6U)
3684 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3685 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3686 #define CAN_F3R1_FB7_Pos (7U)
3687 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3688 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3689 #define CAN_F3R1_FB8_Pos (8U)
3690 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3691 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3692 #define CAN_F3R1_FB9_Pos (9U)
3693 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3694 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3695 #define CAN_F3R1_FB10_Pos (10U)
3696 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3697 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3698 #define CAN_F3R1_FB11_Pos (11U)
3699 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3700 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3701 #define CAN_F3R1_FB12_Pos (12U)
3702 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3703 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3704 #define CAN_F3R1_FB13_Pos (13U)
3705 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3706 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3707 #define CAN_F3R1_FB14_Pos (14U)
3708 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3709 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3710 #define CAN_F3R1_FB15_Pos (15U)
3711 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3712 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3713 #define CAN_F3R1_FB16_Pos (16U)
3714 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3715 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3716 #define CAN_F3R1_FB17_Pos (17U)
3717 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3718 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3719 #define CAN_F3R1_FB18_Pos (18U)
3720 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3721 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3722 #define CAN_F3R1_FB19_Pos (19U)
3723 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3724 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3725 #define CAN_F3R1_FB20_Pos (20U)
3726 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3727 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3728 #define CAN_F3R1_FB21_Pos (21U)
3729 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3730 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3731 #define CAN_F3R1_FB22_Pos (22U)
3732 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3733 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3734 #define CAN_F3R1_FB23_Pos (23U)
3735 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3736 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3737 #define CAN_F3R1_FB24_Pos (24U)
3738 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3739 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3740 #define CAN_F3R1_FB25_Pos (25U)
3741 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3742 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3743 #define CAN_F3R1_FB26_Pos (26U)
3744 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3745 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3746 #define CAN_F3R1_FB27_Pos (27U)
3747 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3748 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3749 #define CAN_F3R1_FB28_Pos (28U)
3750 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3751 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3752 #define CAN_F3R1_FB29_Pos (29U)
3753 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3754 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3755 #define CAN_F3R1_FB30_Pos (30U)
3756 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3757 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3758 #define CAN_F3R1_FB31_Pos (31U)
3759 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3760 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3761
3762 /******************* Bit definition for CAN_F4R1 register *******************/
3763 #define CAN_F4R1_FB0_Pos (0U)
3764 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3765 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3766 #define CAN_F4R1_FB1_Pos (1U)
3767 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3768 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3769 #define CAN_F4R1_FB2_Pos (2U)
3770 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3771 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3772 #define CAN_F4R1_FB3_Pos (3U)
3773 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3774 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3775 #define CAN_F4R1_FB4_Pos (4U)
3776 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3777 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3778 #define CAN_F4R1_FB5_Pos (5U)
3779 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3780 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3781 #define CAN_F4R1_FB6_Pos (6U)
3782 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3783 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3784 #define CAN_F4R1_FB7_Pos (7U)
3785 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3786 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3787 #define CAN_F4R1_FB8_Pos (8U)
3788 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3789 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3790 #define CAN_F4R1_FB9_Pos (9U)
3791 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3792 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3793 #define CAN_F4R1_FB10_Pos (10U)
3794 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3795 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3796 #define CAN_F4R1_FB11_Pos (11U)
3797 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3798 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3799 #define CAN_F4R1_FB12_Pos (12U)
3800 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3801 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3802 #define CAN_F4R1_FB13_Pos (13U)
3803 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3804 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3805 #define CAN_F4R1_FB14_Pos (14U)
3806 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3807 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3808 #define CAN_F4R1_FB15_Pos (15U)
3809 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3810 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3811 #define CAN_F4R1_FB16_Pos (16U)
3812 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3813 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3814 #define CAN_F4R1_FB17_Pos (17U)
3815 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3816 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3817 #define CAN_F4R1_FB18_Pos (18U)
3818 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3819 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3820 #define CAN_F4R1_FB19_Pos (19U)
3821 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3822 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3823 #define CAN_F4R1_FB20_Pos (20U)
3824 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3825 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3826 #define CAN_F4R1_FB21_Pos (21U)
3827 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3828 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3829 #define CAN_F4R1_FB22_Pos (22U)
3830 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3831 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3832 #define CAN_F4R1_FB23_Pos (23U)
3833 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3834 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3835 #define CAN_F4R1_FB24_Pos (24U)
3836 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3837 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3838 #define CAN_F4R1_FB25_Pos (25U)
3839 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3840 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3841 #define CAN_F4R1_FB26_Pos (26U)
3842 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3843 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3844 #define CAN_F4R1_FB27_Pos (27U)
3845 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3846 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3847 #define CAN_F4R1_FB28_Pos (28U)
3848 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3849 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3850 #define CAN_F4R1_FB29_Pos (29U)
3851 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3852 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3853 #define CAN_F4R1_FB30_Pos (30U)
3854 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3855 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3856 #define CAN_F4R1_FB31_Pos (31U)
3857 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3858 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3859
3860 /******************* Bit definition for CAN_F5R1 register *******************/
3861 #define CAN_F5R1_FB0_Pos (0U)
3862 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3863 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3864 #define CAN_F5R1_FB1_Pos (1U)
3865 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3866 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3867 #define CAN_F5R1_FB2_Pos (2U)
3868 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3869 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3870 #define CAN_F5R1_FB3_Pos (3U)
3871 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3872 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3873 #define CAN_F5R1_FB4_Pos (4U)
3874 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3875 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3876 #define CAN_F5R1_FB5_Pos (5U)
3877 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3878 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3879 #define CAN_F5R1_FB6_Pos (6U)
3880 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3881 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3882 #define CAN_F5R1_FB7_Pos (7U)
3883 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3884 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3885 #define CAN_F5R1_FB8_Pos (8U)
3886 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3887 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3888 #define CAN_F5R1_FB9_Pos (9U)
3889 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3890 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3891 #define CAN_F5R1_FB10_Pos (10U)
3892 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3893 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3894 #define CAN_F5R1_FB11_Pos (11U)
3895 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3896 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3897 #define CAN_F5R1_FB12_Pos (12U)
3898 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3899 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3900 #define CAN_F5R1_FB13_Pos (13U)
3901 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3902 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3903 #define CAN_F5R1_FB14_Pos (14U)
3904 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3905 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3906 #define CAN_F5R1_FB15_Pos (15U)
3907 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3908 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3909 #define CAN_F5R1_FB16_Pos (16U)
3910 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3911 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3912 #define CAN_F5R1_FB17_Pos (17U)
3913 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3914 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3915 #define CAN_F5R1_FB18_Pos (18U)
3916 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3917 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3918 #define CAN_F5R1_FB19_Pos (19U)
3919 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3920 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3921 #define CAN_F5R1_FB20_Pos (20U)
3922 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3923 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3924 #define CAN_F5R1_FB21_Pos (21U)
3925 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3926 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3927 #define CAN_F5R1_FB22_Pos (22U)
3928 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3929 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3930 #define CAN_F5R1_FB23_Pos (23U)
3931 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3932 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3933 #define CAN_F5R1_FB24_Pos (24U)
3934 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3935 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3936 #define CAN_F5R1_FB25_Pos (25U)
3937 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3938 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3939 #define CAN_F5R1_FB26_Pos (26U)
3940 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3941 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3942 #define CAN_F5R1_FB27_Pos (27U)
3943 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3944 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3945 #define CAN_F5R1_FB28_Pos (28U)
3946 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3947 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3948 #define CAN_F5R1_FB29_Pos (29U)
3949 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3950 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3951 #define CAN_F5R1_FB30_Pos (30U)
3952 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3953 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3954 #define CAN_F5R1_FB31_Pos (31U)
3955 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3956 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3957
3958 /******************* Bit definition for CAN_F6R1 register *******************/
3959 #define CAN_F6R1_FB0_Pos (0U)
3960 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3961 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3962 #define CAN_F6R1_FB1_Pos (1U)
3963 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3964 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3965 #define CAN_F6R1_FB2_Pos (2U)
3966 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3967 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3968 #define CAN_F6R1_FB3_Pos (3U)
3969 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3970 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3971 #define CAN_F6R1_FB4_Pos (4U)
3972 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3973 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3974 #define CAN_F6R1_FB5_Pos (5U)
3975 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3976 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3977 #define CAN_F6R1_FB6_Pos (6U)
3978 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3979 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3980 #define CAN_F6R1_FB7_Pos (7U)
3981 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3982 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3983 #define CAN_F6R1_FB8_Pos (8U)
3984 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3985 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3986 #define CAN_F6R1_FB9_Pos (9U)
3987 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3988 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3989 #define CAN_F6R1_FB10_Pos (10U)
3990 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3991 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3992 #define CAN_F6R1_FB11_Pos (11U)
3993 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3994 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3995 #define CAN_F6R1_FB12_Pos (12U)
3996 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3997 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3998 #define CAN_F6R1_FB13_Pos (13U)
3999 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
4000 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
4001 #define CAN_F6R1_FB14_Pos (14U)
4002 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
4003 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
4004 #define CAN_F6R1_FB15_Pos (15U)
4005 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
4006 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
4007 #define CAN_F6R1_FB16_Pos (16U)
4008 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
4009 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
4010 #define CAN_F6R1_FB17_Pos (17U)
4011 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
4012 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
4013 #define CAN_F6R1_FB18_Pos (18U)
4014 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
4015 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
4016 #define CAN_F6R1_FB19_Pos (19U)
4017 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
4018 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
4019 #define CAN_F6R1_FB20_Pos (20U)
4020 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
4021 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
4022 #define CAN_F6R1_FB21_Pos (21U)
4023 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
4024 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
4025 #define CAN_F6R1_FB22_Pos (22U)
4026 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
4027 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
4028 #define CAN_F6R1_FB23_Pos (23U)
4029 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
4030 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
4031 #define CAN_F6R1_FB24_Pos (24U)
4032 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
4033 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
4034 #define CAN_F6R1_FB25_Pos (25U)
4035 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
4036 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
4037 #define CAN_F6R1_FB26_Pos (26U)
4038 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
4039 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
4040 #define CAN_F6R1_FB27_Pos (27U)
4041 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
4042 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
4043 #define CAN_F6R1_FB28_Pos (28U)
4044 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
4045 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
4046 #define CAN_F6R1_FB29_Pos (29U)
4047 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
4048 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
4049 #define CAN_F6R1_FB30_Pos (30U)
4050 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
4051 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
4052 #define CAN_F6R1_FB31_Pos (31U)
4053 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
4054 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
4055
4056 /******************* Bit definition for CAN_F7R1 register *******************/
4057 #define CAN_F7R1_FB0_Pos (0U)
4058 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
4059 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
4060 #define CAN_F7R1_FB1_Pos (1U)
4061 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
4062 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
4063 #define CAN_F7R1_FB2_Pos (2U)
4064 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
4065 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
4066 #define CAN_F7R1_FB3_Pos (3U)
4067 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
4068 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
4069 #define CAN_F7R1_FB4_Pos (4U)
4070 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
4071 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
4072 #define CAN_F7R1_FB5_Pos (5U)
4073 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
4074 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
4075 #define CAN_F7R1_FB6_Pos (6U)
4076 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
4077 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
4078 #define CAN_F7R1_FB7_Pos (7U)
4079 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
4080 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
4081 #define CAN_F7R1_FB8_Pos (8U)
4082 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
4083 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
4084 #define CAN_F7R1_FB9_Pos (9U)
4085 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
4086 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
4087 #define CAN_F7R1_FB10_Pos (10U)
4088 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
4089 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
4090 #define CAN_F7R1_FB11_Pos (11U)
4091 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
4092 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
4093 #define CAN_F7R1_FB12_Pos (12U)
4094 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
4095 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
4096 #define CAN_F7R1_FB13_Pos (13U)
4097 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
4098 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
4099 #define CAN_F7R1_FB14_Pos (14U)
4100 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
4101 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
4102 #define CAN_F7R1_FB15_Pos (15U)
4103 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
4104 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
4105 #define CAN_F7R1_FB16_Pos (16U)
4106 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
4107 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
4108 #define CAN_F7R1_FB17_Pos (17U)
4109 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
4110 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
4111 #define CAN_F7R1_FB18_Pos (18U)
4112 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
4113 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
4114 #define CAN_F7R1_FB19_Pos (19U)
4115 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
4116 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
4117 #define CAN_F7R1_FB20_Pos (20U)
4118 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
4119 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
4120 #define CAN_F7R1_FB21_Pos (21U)
4121 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
4122 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
4123 #define CAN_F7R1_FB22_Pos (22U)
4124 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
4125 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
4126 #define CAN_F7R1_FB23_Pos (23U)
4127 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
4128 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
4129 #define CAN_F7R1_FB24_Pos (24U)
4130 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
4131 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
4132 #define CAN_F7R1_FB25_Pos (25U)
4133 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
4134 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
4135 #define CAN_F7R1_FB26_Pos (26U)
4136 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
4137 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
4138 #define CAN_F7R1_FB27_Pos (27U)
4139 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
4140 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
4141 #define CAN_F7R1_FB28_Pos (28U)
4142 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
4143 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
4144 #define CAN_F7R1_FB29_Pos (29U)
4145 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
4146 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
4147 #define CAN_F7R1_FB30_Pos (30U)
4148 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
4149 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
4150 #define CAN_F7R1_FB31_Pos (31U)
4151 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
4152 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
4153
4154 /******************* Bit definition for CAN_F8R1 register *******************/
4155 #define CAN_F8R1_FB0_Pos (0U)
4156 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
4157 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
4158 #define CAN_F8R1_FB1_Pos (1U)
4159 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
4160 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
4161 #define CAN_F8R1_FB2_Pos (2U)
4162 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
4163 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
4164 #define CAN_F8R1_FB3_Pos (3U)
4165 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
4166 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
4167 #define CAN_F8R1_FB4_Pos (4U)
4168 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
4169 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
4170 #define CAN_F8R1_FB5_Pos (5U)
4171 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
4172 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
4173 #define CAN_F8R1_FB6_Pos (6U)
4174 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
4175 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
4176 #define CAN_F8R1_FB7_Pos (7U)
4177 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
4178 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
4179 #define CAN_F8R1_FB8_Pos (8U)
4180 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
4181 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
4182 #define CAN_F8R1_FB9_Pos (9U)
4183 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
4184 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
4185 #define CAN_F8R1_FB10_Pos (10U)
4186 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
4187 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
4188 #define CAN_F8R1_FB11_Pos (11U)
4189 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
4190 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
4191 #define CAN_F8R1_FB12_Pos (12U)
4192 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
4193 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
4194 #define CAN_F8R1_FB13_Pos (13U)
4195 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
4196 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
4197 #define CAN_F8R1_FB14_Pos (14U)
4198 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
4199 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
4200 #define CAN_F8R1_FB15_Pos (15U)
4201 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
4202 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
4203 #define CAN_F8R1_FB16_Pos (16U)
4204 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
4205 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
4206 #define CAN_F8R1_FB17_Pos (17U)
4207 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
4208 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
4209 #define CAN_F8R1_FB18_Pos (18U)
4210 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
4211 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
4212 #define CAN_F8R1_FB19_Pos (19U)
4213 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
4214 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
4215 #define CAN_F8R1_FB20_Pos (20U)
4216 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
4217 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
4218 #define CAN_F8R1_FB21_Pos (21U)
4219 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
4220 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
4221 #define CAN_F8R1_FB22_Pos (22U)
4222 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
4223 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
4224 #define CAN_F8R1_FB23_Pos (23U)
4225 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
4226 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
4227 #define CAN_F8R1_FB24_Pos (24U)
4228 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
4229 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
4230 #define CAN_F8R1_FB25_Pos (25U)
4231 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
4232 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
4233 #define CAN_F8R1_FB26_Pos (26U)
4234 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
4235 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
4236 #define CAN_F8R1_FB27_Pos (27U)
4237 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
4238 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
4239 #define CAN_F8R1_FB28_Pos (28U)
4240 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
4241 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
4242 #define CAN_F8R1_FB29_Pos (29U)
4243 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
4244 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
4245 #define CAN_F8R1_FB30_Pos (30U)
4246 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
4247 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
4248 #define CAN_F8R1_FB31_Pos (31U)
4249 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
4250 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
4251
4252 /******************* Bit definition for CAN_F9R1 register *******************/
4253 #define CAN_F9R1_FB0_Pos (0U)
4254 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
4255 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
4256 #define CAN_F9R1_FB1_Pos (1U)
4257 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
4258 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
4259 #define CAN_F9R1_FB2_Pos (2U)
4260 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
4261 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
4262 #define CAN_F9R1_FB3_Pos (3U)
4263 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
4264 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
4265 #define CAN_F9R1_FB4_Pos (4U)
4266 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
4267 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
4268 #define CAN_F9R1_FB5_Pos (5U)
4269 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
4270 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
4271 #define CAN_F9R1_FB6_Pos (6U)
4272 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
4273 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
4274 #define CAN_F9R1_FB7_Pos (7U)
4275 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
4276 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
4277 #define CAN_F9R1_FB8_Pos (8U)
4278 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
4279 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
4280 #define CAN_F9R1_FB9_Pos (9U)
4281 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
4282 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
4283 #define CAN_F9R1_FB10_Pos (10U)
4284 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
4285 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
4286 #define CAN_F9R1_FB11_Pos (11U)
4287 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
4288 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
4289 #define CAN_F9R1_FB12_Pos (12U)
4290 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
4291 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
4292 #define CAN_F9R1_FB13_Pos (13U)
4293 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
4294 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
4295 #define CAN_F9R1_FB14_Pos (14U)
4296 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
4297 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
4298 #define CAN_F9R1_FB15_Pos (15U)
4299 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
4300 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
4301 #define CAN_F9R1_FB16_Pos (16U)
4302 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
4303 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
4304 #define CAN_F9R1_FB17_Pos (17U)
4305 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
4306 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
4307 #define CAN_F9R1_FB18_Pos (18U)
4308 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
4309 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
4310 #define CAN_F9R1_FB19_Pos (19U)
4311 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
4312 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
4313 #define CAN_F9R1_FB20_Pos (20U)
4314 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
4315 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
4316 #define CAN_F9R1_FB21_Pos (21U)
4317 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
4318 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
4319 #define CAN_F9R1_FB22_Pos (22U)
4320 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
4321 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
4322 #define CAN_F9R1_FB23_Pos (23U)
4323 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
4324 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
4325 #define CAN_F9R1_FB24_Pos (24U)
4326 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
4327 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
4328 #define CAN_F9R1_FB25_Pos (25U)
4329 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
4330 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
4331 #define CAN_F9R1_FB26_Pos (26U)
4332 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
4333 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
4334 #define CAN_F9R1_FB27_Pos (27U)
4335 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
4336 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
4337 #define CAN_F9R1_FB28_Pos (28U)
4338 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
4339 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
4340 #define CAN_F9R1_FB29_Pos (29U)
4341 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
4342 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
4343 #define CAN_F9R1_FB30_Pos (30U)
4344 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
4345 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
4346 #define CAN_F9R1_FB31_Pos (31U)
4347 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
4348 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
4349
4350 /******************* Bit definition for CAN_F10R1 register ******************/
4351 #define CAN_F10R1_FB0_Pos (0U)
4352 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
4353 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
4354 #define CAN_F10R1_FB1_Pos (1U)
4355 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
4356 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
4357 #define CAN_F10R1_FB2_Pos (2U)
4358 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
4359 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
4360 #define CAN_F10R1_FB3_Pos (3U)
4361 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
4362 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
4363 #define CAN_F10R1_FB4_Pos (4U)
4364 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
4365 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
4366 #define CAN_F10R1_FB5_Pos (5U)
4367 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
4368 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
4369 #define CAN_F10R1_FB6_Pos (6U)
4370 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
4371 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
4372 #define CAN_F10R1_FB7_Pos (7U)
4373 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
4374 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
4375 #define CAN_F10R1_FB8_Pos (8U)
4376 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
4377 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
4378 #define CAN_F10R1_FB9_Pos (9U)
4379 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
4380 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
4381 #define CAN_F10R1_FB10_Pos (10U)
4382 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
4383 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
4384 #define CAN_F10R1_FB11_Pos (11U)
4385 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
4386 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
4387 #define CAN_F10R1_FB12_Pos (12U)
4388 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
4389 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
4390 #define CAN_F10R1_FB13_Pos (13U)
4391 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
4392 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
4393 #define CAN_F10R1_FB14_Pos (14U)
4394 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
4395 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
4396 #define CAN_F10R1_FB15_Pos (15U)
4397 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
4398 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
4399 #define CAN_F10R1_FB16_Pos (16U)
4400 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
4401 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
4402 #define CAN_F10R1_FB17_Pos (17U)
4403 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
4404 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
4405 #define CAN_F10R1_FB18_Pos (18U)
4406 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
4407 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
4408 #define CAN_F10R1_FB19_Pos (19U)
4409 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
4410 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
4411 #define CAN_F10R1_FB20_Pos (20U)
4412 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
4413 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
4414 #define CAN_F10R1_FB21_Pos (21U)
4415 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
4416 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
4417 #define CAN_F10R1_FB22_Pos (22U)
4418 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
4419 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
4420 #define CAN_F10R1_FB23_Pos (23U)
4421 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
4422 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
4423 #define CAN_F10R1_FB24_Pos (24U)
4424 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
4425 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
4426 #define CAN_F10R1_FB25_Pos (25U)
4427 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
4428 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
4429 #define CAN_F10R1_FB26_Pos (26U)
4430 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
4431 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
4432 #define CAN_F10R1_FB27_Pos (27U)
4433 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
4434 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
4435 #define CAN_F10R1_FB28_Pos (28U)
4436 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
4437 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
4438 #define CAN_F10R1_FB29_Pos (29U)
4439 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
4440 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
4441 #define CAN_F10R1_FB30_Pos (30U)
4442 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4443 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4444 #define CAN_F10R1_FB31_Pos (31U)
4445 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4446 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4447
4448 /******************* Bit definition for CAN_F11R1 register ******************/
4449 #define CAN_F11R1_FB0_Pos (0U)
4450 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4451 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4452 #define CAN_F11R1_FB1_Pos (1U)
4453 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4454 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4455 #define CAN_F11R1_FB2_Pos (2U)
4456 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4457 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4458 #define CAN_F11R1_FB3_Pos (3U)
4459 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4460 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4461 #define CAN_F11R1_FB4_Pos (4U)
4462 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4463 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4464 #define CAN_F11R1_FB5_Pos (5U)
4465 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4466 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4467 #define CAN_F11R1_FB6_Pos (6U)
4468 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4469 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4470 #define CAN_F11R1_FB7_Pos (7U)
4471 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4472 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4473 #define CAN_F11R1_FB8_Pos (8U)
4474 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4475 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4476 #define CAN_F11R1_FB9_Pos (9U)
4477 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4478 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4479 #define CAN_F11R1_FB10_Pos (10U)
4480 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4481 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4482 #define CAN_F11R1_FB11_Pos (11U)
4483 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4484 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4485 #define CAN_F11R1_FB12_Pos (12U)
4486 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4487 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4488 #define CAN_F11R1_FB13_Pos (13U)
4489 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4490 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4491 #define CAN_F11R1_FB14_Pos (14U)
4492 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4493 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4494 #define CAN_F11R1_FB15_Pos (15U)
4495 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4496 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4497 #define CAN_F11R1_FB16_Pos (16U)
4498 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4499 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4500 #define CAN_F11R1_FB17_Pos (17U)
4501 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4502 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4503 #define CAN_F11R1_FB18_Pos (18U)
4504 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4505 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4506 #define CAN_F11R1_FB19_Pos (19U)
4507 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4508 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4509 #define CAN_F11R1_FB20_Pos (20U)
4510 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4511 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4512 #define CAN_F11R1_FB21_Pos (21U)
4513 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4514 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4515 #define CAN_F11R1_FB22_Pos (22U)
4516 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4517 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4518 #define CAN_F11R1_FB23_Pos (23U)
4519 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4520 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4521 #define CAN_F11R1_FB24_Pos (24U)
4522 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4523 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4524 #define CAN_F11R1_FB25_Pos (25U)
4525 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4526 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4527 #define CAN_F11R1_FB26_Pos (26U)
4528 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4529 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4530 #define CAN_F11R1_FB27_Pos (27U)
4531 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4532 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4533 #define CAN_F11R1_FB28_Pos (28U)
4534 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4535 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4536 #define CAN_F11R1_FB29_Pos (29U)
4537 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4538 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4539 #define CAN_F11R1_FB30_Pos (30U)
4540 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4541 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4542 #define CAN_F11R1_FB31_Pos (31U)
4543 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4544 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4545
4546 /******************* Bit definition for CAN_F12R1 register ******************/
4547 #define CAN_F12R1_FB0_Pos (0U)
4548 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4549 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4550 #define CAN_F12R1_FB1_Pos (1U)
4551 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4552 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4553 #define CAN_F12R1_FB2_Pos (2U)
4554 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4555 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4556 #define CAN_F12R1_FB3_Pos (3U)
4557 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4558 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4559 #define CAN_F12R1_FB4_Pos (4U)
4560 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4561 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4562 #define CAN_F12R1_FB5_Pos (5U)
4563 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4564 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4565 #define CAN_F12R1_FB6_Pos (6U)
4566 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4567 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4568 #define CAN_F12R1_FB7_Pos (7U)
4569 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4570 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4571 #define CAN_F12R1_FB8_Pos (8U)
4572 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4573 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4574 #define CAN_F12R1_FB9_Pos (9U)
4575 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4576 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4577 #define CAN_F12R1_FB10_Pos (10U)
4578 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4579 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4580 #define CAN_F12R1_FB11_Pos (11U)
4581 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4582 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4583 #define CAN_F12R1_FB12_Pos (12U)
4584 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4585 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4586 #define CAN_F12R1_FB13_Pos (13U)
4587 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4588 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4589 #define CAN_F12R1_FB14_Pos (14U)
4590 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4591 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4592 #define CAN_F12R1_FB15_Pos (15U)
4593 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4594 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4595 #define CAN_F12R1_FB16_Pos (16U)
4596 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4597 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4598 #define CAN_F12R1_FB17_Pos (17U)
4599 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4600 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4601 #define CAN_F12R1_FB18_Pos (18U)
4602 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4603 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4604 #define CAN_F12R1_FB19_Pos (19U)
4605 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4606 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4607 #define CAN_F12R1_FB20_Pos (20U)
4608 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4609 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4610 #define CAN_F12R1_FB21_Pos (21U)
4611 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4612 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4613 #define CAN_F12R1_FB22_Pos (22U)
4614 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4615 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4616 #define CAN_F12R1_FB23_Pos (23U)
4617 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4618 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4619 #define CAN_F12R1_FB24_Pos (24U)
4620 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4621 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4622 #define CAN_F12R1_FB25_Pos (25U)
4623 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4624 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4625 #define CAN_F12R1_FB26_Pos (26U)
4626 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4627 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4628 #define CAN_F12R1_FB27_Pos (27U)
4629 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4630 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4631 #define CAN_F12R1_FB28_Pos (28U)
4632 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4633 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4634 #define CAN_F12R1_FB29_Pos (29U)
4635 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4636 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4637 #define CAN_F12R1_FB30_Pos (30U)
4638 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4639 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4640 #define CAN_F12R1_FB31_Pos (31U)
4641 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4642 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4643
4644 /******************* Bit definition for CAN_F13R1 register ******************/
4645 #define CAN_F13R1_FB0_Pos (0U)
4646 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4647 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4648 #define CAN_F13R1_FB1_Pos (1U)
4649 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4650 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4651 #define CAN_F13R1_FB2_Pos (2U)
4652 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4653 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4654 #define CAN_F13R1_FB3_Pos (3U)
4655 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4656 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4657 #define CAN_F13R1_FB4_Pos (4U)
4658 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4659 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4660 #define CAN_F13R1_FB5_Pos (5U)
4661 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4662 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4663 #define CAN_F13R1_FB6_Pos (6U)
4664 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4665 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4666 #define CAN_F13R1_FB7_Pos (7U)
4667 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4668 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4669 #define CAN_F13R1_FB8_Pos (8U)
4670 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4671 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4672 #define CAN_F13R1_FB9_Pos (9U)
4673 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4674 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4675 #define CAN_F13R1_FB10_Pos (10U)
4676 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4677 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4678 #define CAN_F13R1_FB11_Pos (11U)
4679 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4680 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4681 #define CAN_F13R1_FB12_Pos (12U)
4682 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4683 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4684 #define CAN_F13R1_FB13_Pos (13U)
4685 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4686 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4687 #define CAN_F13R1_FB14_Pos (14U)
4688 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4689 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4690 #define CAN_F13R1_FB15_Pos (15U)
4691 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4692 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4693 #define CAN_F13R1_FB16_Pos (16U)
4694 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4695 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4696 #define CAN_F13R1_FB17_Pos (17U)
4697 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4698 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4699 #define CAN_F13R1_FB18_Pos (18U)
4700 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4701 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4702 #define CAN_F13R1_FB19_Pos (19U)
4703 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4704 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4705 #define CAN_F13R1_FB20_Pos (20U)
4706 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4707 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4708 #define CAN_F13R1_FB21_Pos (21U)
4709 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4710 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4711 #define CAN_F13R1_FB22_Pos (22U)
4712 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4713 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4714 #define CAN_F13R1_FB23_Pos (23U)
4715 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4716 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4717 #define CAN_F13R1_FB24_Pos (24U)
4718 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4719 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4720 #define CAN_F13R1_FB25_Pos (25U)
4721 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4722 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4723 #define CAN_F13R1_FB26_Pos (26U)
4724 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4725 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4726 #define CAN_F13R1_FB27_Pos (27U)
4727 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4728 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4729 #define CAN_F13R1_FB28_Pos (28U)
4730 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4731 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4732 #define CAN_F13R1_FB29_Pos (29U)
4733 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4734 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4735 #define CAN_F13R1_FB30_Pos (30U)
4736 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4737 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4738 #define CAN_F13R1_FB31_Pos (31U)
4739 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4740 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4741
4742 /******************* Bit definition for CAN_F0R2 register *******************/
4743 #define CAN_F0R2_FB0_Pos (0U)
4744 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4745 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4746 #define CAN_F0R2_FB1_Pos (1U)
4747 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4748 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4749 #define CAN_F0R2_FB2_Pos (2U)
4750 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4751 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4752 #define CAN_F0R2_FB3_Pos (3U)
4753 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4754 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4755 #define CAN_F0R2_FB4_Pos (4U)
4756 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4757 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4758 #define CAN_F0R2_FB5_Pos (5U)
4759 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4760 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4761 #define CAN_F0R2_FB6_Pos (6U)
4762 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4763 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4764 #define CAN_F0R2_FB7_Pos (7U)
4765 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4766 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4767 #define CAN_F0R2_FB8_Pos (8U)
4768 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4769 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4770 #define CAN_F0R2_FB9_Pos (9U)
4771 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4772 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4773 #define CAN_F0R2_FB10_Pos (10U)
4774 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4775 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4776 #define CAN_F0R2_FB11_Pos (11U)
4777 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4778 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4779 #define CAN_F0R2_FB12_Pos (12U)
4780 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4781 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4782 #define CAN_F0R2_FB13_Pos (13U)
4783 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4784 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4785 #define CAN_F0R2_FB14_Pos (14U)
4786 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4787 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4788 #define CAN_F0R2_FB15_Pos (15U)
4789 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4790 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4791 #define CAN_F0R2_FB16_Pos (16U)
4792 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4793 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4794 #define CAN_F0R2_FB17_Pos (17U)
4795 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4796 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4797 #define CAN_F0R2_FB18_Pos (18U)
4798 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4799 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4800 #define CAN_F0R2_FB19_Pos (19U)
4801 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4802 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4803 #define CAN_F0R2_FB20_Pos (20U)
4804 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4805 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4806 #define CAN_F0R2_FB21_Pos (21U)
4807 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4808 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4809 #define CAN_F0R2_FB22_Pos (22U)
4810 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4811 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4812 #define CAN_F0R2_FB23_Pos (23U)
4813 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4814 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4815 #define CAN_F0R2_FB24_Pos (24U)
4816 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4817 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4818 #define CAN_F0R2_FB25_Pos (25U)
4819 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4820 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4821 #define CAN_F0R2_FB26_Pos (26U)
4822 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4823 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4824 #define CAN_F0R2_FB27_Pos (27U)
4825 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4826 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4827 #define CAN_F0R2_FB28_Pos (28U)
4828 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4829 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4830 #define CAN_F0R2_FB29_Pos (29U)
4831 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4832 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4833 #define CAN_F0R2_FB30_Pos (30U)
4834 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4835 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4836 #define CAN_F0R2_FB31_Pos (31U)
4837 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4838 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4839
4840 /******************* Bit definition for CAN_F1R2 register *******************/
4841 #define CAN_F1R2_FB0_Pos (0U)
4842 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4843 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4844 #define CAN_F1R2_FB1_Pos (1U)
4845 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4846 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4847 #define CAN_F1R2_FB2_Pos (2U)
4848 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4849 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4850 #define CAN_F1R2_FB3_Pos (3U)
4851 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4852 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4853 #define CAN_F1R2_FB4_Pos (4U)
4854 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4855 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4856 #define CAN_F1R2_FB5_Pos (5U)
4857 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4858 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4859 #define CAN_F1R2_FB6_Pos (6U)
4860 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4861 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4862 #define CAN_F1R2_FB7_Pos (7U)
4863 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4864 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4865 #define CAN_F1R2_FB8_Pos (8U)
4866 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4867 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4868 #define CAN_F1R2_FB9_Pos (9U)
4869 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4870 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4871 #define CAN_F1R2_FB10_Pos (10U)
4872 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4873 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4874 #define CAN_F1R2_FB11_Pos (11U)
4875 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4876 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4877 #define CAN_F1R2_FB12_Pos (12U)
4878 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4879 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4880 #define CAN_F1R2_FB13_Pos (13U)
4881 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4882 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4883 #define CAN_F1R2_FB14_Pos (14U)
4884 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4885 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4886 #define CAN_F1R2_FB15_Pos (15U)
4887 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4888 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4889 #define CAN_F1R2_FB16_Pos (16U)
4890 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4891 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4892 #define CAN_F1R2_FB17_Pos (17U)
4893 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4894 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4895 #define CAN_F1R2_FB18_Pos (18U)
4896 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4897 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4898 #define CAN_F1R2_FB19_Pos (19U)
4899 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4900 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4901 #define CAN_F1R2_FB20_Pos (20U)
4902 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4903 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4904 #define CAN_F1R2_FB21_Pos (21U)
4905 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4906 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4907 #define CAN_F1R2_FB22_Pos (22U)
4908 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4909 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4910 #define CAN_F1R2_FB23_Pos (23U)
4911 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4912 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4913 #define CAN_F1R2_FB24_Pos (24U)
4914 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4915 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4916 #define CAN_F1R2_FB25_Pos (25U)
4917 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4918 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4919 #define CAN_F1R2_FB26_Pos (26U)
4920 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4921 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4922 #define CAN_F1R2_FB27_Pos (27U)
4923 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4924 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4925 #define CAN_F1R2_FB28_Pos (28U)
4926 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4927 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4928 #define CAN_F1R2_FB29_Pos (29U)
4929 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4930 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4931 #define CAN_F1R2_FB30_Pos (30U)
4932 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4933 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4934 #define CAN_F1R2_FB31_Pos (31U)
4935 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4936 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4937
4938 /******************* Bit definition for CAN_F2R2 register *******************/
4939 #define CAN_F2R2_FB0_Pos (0U)
4940 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4941 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4942 #define CAN_F2R2_FB1_Pos (1U)
4943 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4944 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4945 #define CAN_F2R2_FB2_Pos (2U)
4946 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4947 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4948 #define CAN_F2R2_FB3_Pos (3U)
4949 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4950 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4951 #define CAN_F2R2_FB4_Pos (4U)
4952 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4953 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4954 #define CAN_F2R2_FB5_Pos (5U)
4955 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4956 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4957 #define CAN_F2R2_FB6_Pos (6U)
4958 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4959 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4960 #define CAN_F2R2_FB7_Pos (7U)
4961 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4962 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4963 #define CAN_F2R2_FB8_Pos (8U)
4964 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4965 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4966 #define CAN_F2R2_FB9_Pos (9U)
4967 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4968 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4969 #define CAN_F2R2_FB10_Pos (10U)
4970 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4971 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4972 #define CAN_F2R2_FB11_Pos (11U)
4973 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4974 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4975 #define CAN_F2R2_FB12_Pos (12U)
4976 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4977 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4978 #define CAN_F2R2_FB13_Pos (13U)
4979 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4980 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4981 #define CAN_F2R2_FB14_Pos (14U)
4982 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4983 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4984 #define CAN_F2R2_FB15_Pos (15U)
4985 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4986 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4987 #define CAN_F2R2_FB16_Pos (16U)
4988 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4989 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4990 #define CAN_F2R2_FB17_Pos (17U)
4991 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4992 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4993 #define CAN_F2R2_FB18_Pos (18U)
4994 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4995 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4996 #define CAN_F2R2_FB19_Pos (19U)
4997 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4998 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4999 #define CAN_F2R2_FB20_Pos (20U)
5000 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
5001 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
5002 #define CAN_F2R2_FB21_Pos (21U)
5003 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
5004 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
5005 #define CAN_F2R2_FB22_Pos (22U)
5006 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
5007 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
5008 #define CAN_F2R2_FB23_Pos (23U)
5009 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
5010 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
5011 #define CAN_F2R2_FB24_Pos (24U)
5012 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
5013 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
5014 #define CAN_F2R2_FB25_Pos (25U)
5015 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
5016 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
5017 #define CAN_F2R2_FB26_Pos (26U)
5018 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
5019 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
5020 #define CAN_F2R2_FB27_Pos (27U)
5021 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
5022 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
5023 #define CAN_F2R2_FB28_Pos (28U)
5024 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
5025 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
5026 #define CAN_F2R2_FB29_Pos (29U)
5027 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
5028 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
5029 #define CAN_F2R2_FB30_Pos (30U)
5030 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
5031 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
5032 #define CAN_F2R2_FB31_Pos (31U)
5033 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
5034 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
5035
5036 /******************* Bit definition for CAN_F3R2 register *******************/
5037 #define CAN_F3R2_FB0_Pos (0U)
5038 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
5039 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
5040 #define CAN_F3R2_FB1_Pos (1U)
5041 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
5042 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
5043 #define CAN_F3R2_FB2_Pos (2U)
5044 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
5045 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
5046 #define CAN_F3R2_FB3_Pos (3U)
5047 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
5048 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
5049 #define CAN_F3R2_FB4_Pos (4U)
5050 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
5051 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
5052 #define CAN_F3R2_FB5_Pos (5U)
5053 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
5054 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
5055 #define CAN_F3R2_FB6_Pos (6U)
5056 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
5057 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
5058 #define CAN_F3R2_FB7_Pos (7U)
5059 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
5060 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
5061 #define CAN_F3R2_FB8_Pos (8U)
5062 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
5063 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
5064 #define CAN_F3R2_FB9_Pos (9U)
5065 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
5066 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
5067 #define CAN_F3R2_FB10_Pos (10U)
5068 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
5069 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
5070 #define CAN_F3R2_FB11_Pos (11U)
5071 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
5072 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
5073 #define CAN_F3R2_FB12_Pos (12U)
5074 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
5075 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
5076 #define CAN_F3R2_FB13_Pos (13U)
5077 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
5078 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
5079 #define CAN_F3R2_FB14_Pos (14U)
5080 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
5081 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
5082 #define CAN_F3R2_FB15_Pos (15U)
5083 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
5084 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
5085 #define CAN_F3R2_FB16_Pos (16U)
5086 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
5087 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
5088 #define CAN_F3R2_FB17_Pos (17U)
5089 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
5090 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
5091 #define CAN_F3R2_FB18_Pos (18U)
5092 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
5093 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
5094 #define CAN_F3R2_FB19_Pos (19U)
5095 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
5096 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
5097 #define CAN_F3R2_FB20_Pos (20U)
5098 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
5099 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
5100 #define CAN_F3R2_FB21_Pos (21U)
5101 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
5102 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
5103 #define CAN_F3R2_FB22_Pos (22U)
5104 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
5105 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
5106 #define CAN_F3R2_FB23_Pos (23U)
5107 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
5108 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
5109 #define CAN_F3R2_FB24_Pos (24U)
5110 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
5111 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
5112 #define CAN_F3R2_FB25_Pos (25U)
5113 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
5114 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
5115 #define CAN_F3R2_FB26_Pos (26U)
5116 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
5117 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
5118 #define CAN_F3R2_FB27_Pos (27U)
5119 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
5120 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
5121 #define CAN_F3R2_FB28_Pos (28U)
5122 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
5123 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
5124 #define CAN_F3R2_FB29_Pos (29U)
5125 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
5126 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
5127 #define CAN_F3R2_FB30_Pos (30U)
5128 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
5129 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
5130 #define CAN_F3R2_FB31_Pos (31U)
5131 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
5132 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
5133
5134 /******************* Bit definition for CAN_F4R2 register *******************/
5135 #define CAN_F4R2_FB0_Pos (0U)
5136 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
5137 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
5138 #define CAN_F4R2_FB1_Pos (1U)
5139 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
5140 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
5141 #define CAN_F4R2_FB2_Pos (2U)
5142 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
5143 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
5144 #define CAN_F4R2_FB3_Pos (3U)
5145 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
5146 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
5147 #define CAN_F4R2_FB4_Pos (4U)
5148 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
5149 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
5150 #define CAN_F4R2_FB5_Pos (5U)
5151 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
5152 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
5153 #define CAN_F4R2_FB6_Pos (6U)
5154 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
5155 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
5156 #define CAN_F4R2_FB7_Pos (7U)
5157 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
5158 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
5159 #define CAN_F4R2_FB8_Pos (8U)
5160 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
5161 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
5162 #define CAN_F4R2_FB9_Pos (9U)
5163 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
5164 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
5165 #define CAN_F4R2_FB10_Pos (10U)
5166 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
5167 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
5168 #define CAN_F4R2_FB11_Pos (11U)
5169 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
5170 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
5171 #define CAN_F4R2_FB12_Pos (12U)
5172 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
5173 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
5174 #define CAN_F4R2_FB13_Pos (13U)
5175 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
5176 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
5177 #define CAN_F4R2_FB14_Pos (14U)
5178 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
5179 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
5180 #define CAN_F4R2_FB15_Pos (15U)
5181 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
5182 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
5183 #define CAN_F4R2_FB16_Pos (16U)
5184 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
5185 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
5186 #define CAN_F4R2_FB17_Pos (17U)
5187 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
5188 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
5189 #define CAN_F4R2_FB18_Pos (18U)
5190 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
5191 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
5192 #define CAN_F4R2_FB19_Pos (19U)
5193 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
5194 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
5195 #define CAN_F4R2_FB20_Pos (20U)
5196 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
5197 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
5198 #define CAN_F4R2_FB21_Pos (21U)
5199 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
5200 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
5201 #define CAN_F4R2_FB22_Pos (22U)
5202 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
5203 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
5204 #define CAN_F4R2_FB23_Pos (23U)
5205 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
5206 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
5207 #define CAN_F4R2_FB24_Pos (24U)
5208 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
5209 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
5210 #define CAN_F4R2_FB25_Pos (25U)
5211 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
5212 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
5213 #define CAN_F4R2_FB26_Pos (26U)
5214 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
5215 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
5216 #define CAN_F4R2_FB27_Pos (27U)
5217 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
5218 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
5219 #define CAN_F4R2_FB28_Pos (28U)
5220 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
5221 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
5222 #define CAN_F4R2_FB29_Pos (29U)
5223 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
5224 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
5225 #define CAN_F4R2_FB30_Pos (30U)
5226 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
5227 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
5228 #define CAN_F4R2_FB31_Pos (31U)
5229 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
5230 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
5231
5232 /******************* Bit definition for CAN_F5R2 register *******************/
5233 #define CAN_F5R2_FB0_Pos (0U)
5234 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
5235 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
5236 #define CAN_F5R2_FB1_Pos (1U)
5237 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
5238 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
5239 #define CAN_F5R2_FB2_Pos (2U)
5240 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
5241 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
5242 #define CAN_F5R2_FB3_Pos (3U)
5243 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
5244 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
5245 #define CAN_F5R2_FB4_Pos (4U)
5246 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
5247 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
5248 #define CAN_F5R2_FB5_Pos (5U)
5249 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
5250 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
5251 #define CAN_F5R2_FB6_Pos (6U)
5252 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
5253 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
5254 #define CAN_F5R2_FB7_Pos (7U)
5255 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
5256 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
5257 #define CAN_F5R2_FB8_Pos (8U)
5258 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
5259 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
5260 #define CAN_F5R2_FB9_Pos (9U)
5261 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
5262 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
5263 #define CAN_F5R2_FB10_Pos (10U)
5264 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
5265 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
5266 #define CAN_F5R2_FB11_Pos (11U)
5267 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
5268 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
5269 #define CAN_F5R2_FB12_Pos (12U)
5270 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
5271 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
5272 #define CAN_F5R2_FB13_Pos (13U)
5273 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
5274 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
5275 #define CAN_F5R2_FB14_Pos (14U)
5276 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
5277 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
5278 #define CAN_F5R2_FB15_Pos (15U)
5279 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
5280 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
5281 #define CAN_F5R2_FB16_Pos (16U)
5282 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
5283 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
5284 #define CAN_F5R2_FB17_Pos (17U)
5285 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
5286 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
5287 #define CAN_F5R2_FB18_Pos (18U)
5288 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
5289 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
5290 #define CAN_F5R2_FB19_Pos (19U)
5291 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
5292 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
5293 #define CAN_F5R2_FB20_Pos (20U)
5294 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
5295 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
5296 #define CAN_F5R2_FB21_Pos (21U)
5297 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
5298 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
5299 #define CAN_F5R2_FB22_Pos (22U)
5300 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
5301 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
5302 #define CAN_F5R2_FB23_Pos (23U)
5303 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
5304 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
5305 #define CAN_F5R2_FB24_Pos (24U)
5306 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
5307 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
5308 #define CAN_F5R2_FB25_Pos (25U)
5309 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
5310 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
5311 #define CAN_F5R2_FB26_Pos (26U)
5312 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
5313 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
5314 #define CAN_F5R2_FB27_Pos (27U)
5315 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
5316 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
5317 #define CAN_F5R2_FB28_Pos (28U)
5318 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
5319 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
5320 #define CAN_F5R2_FB29_Pos (29U)
5321 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
5322 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
5323 #define CAN_F5R2_FB30_Pos (30U)
5324 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
5325 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
5326 #define CAN_F5R2_FB31_Pos (31U)
5327 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
5328 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
5329
5330 /******************* Bit definition for CAN_F6R2 register *******************/
5331 #define CAN_F6R2_FB0_Pos (0U)
5332 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
5333 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
5334 #define CAN_F6R2_FB1_Pos (1U)
5335 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
5336 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
5337 #define CAN_F6R2_FB2_Pos (2U)
5338 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
5339 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
5340 #define CAN_F6R2_FB3_Pos (3U)
5341 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
5342 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
5343 #define CAN_F6R2_FB4_Pos (4U)
5344 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
5345 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
5346 #define CAN_F6R2_FB5_Pos (5U)
5347 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
5348 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
5349 #define CAN_F6R2_FB6_Pos (6U)
5350 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
5351 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
5352 #define CAN_F6R2_FB7_Pos (7U)
5353 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
5354 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
5355 #define CAN_F6R2_FB8_Pos (8U)
5356 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
5357 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
5358 #define CAN_F6R2_FB9_Pos (9U)
5359 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
5360 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
5361 #define CAN_F6R2_FB10_Pos (10U)
5362 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
5363 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
5364 #define CAN_F6R2_FB11_Pos (11U)
5365 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
5366 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
5367 #define CAN_F6R2_FB12_Pos (12U)
5368 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
5369 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
5370 #define CAN_F6R2_FB13_Pos (13U)
5371 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
5372 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
5373 #define CAN_F6R2_FB14_Pos (14U)
5374 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
5375 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
5376 #define CAN_F6R2_FB15_Pos (15U)
5377 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
5378 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
5379 #define CAN_F6R2_FB16_Pos (16U)
5380 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
5381 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
5382 #define CAN_F6R2_FB17_Pos (17U)
5383 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
5384 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
5385 #define CAN_F6R2_FB18_Pos (18U)
5386 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
5387 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
5388 #define CAN_F6R2_FB19_Pos (19U)
5389 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
5390 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
5391 #define CAN_F6R2_FB20_Pos (20U)
5392 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
5393 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
5394 #define CAN_F6R2_FB21_Pos (21U)
5395 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
5396 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
5397 #define CAN_F6R2_FB22_Pos (22U)
5398 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
5399 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
5400 #define CAN_F6R2_FB23_Pos (23U)
5401 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
5402 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
5403 #define CAN_F6R2_FB24_Pos (24U)
5404 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
5405 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
5406 #define CAN_F6R2_FB25_Pos (25U)
5407 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
5408 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
5409 #define CAN_F6R2_FB26_Pos (26U)
5410 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
5411 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
5412 #define CAN_F6R2_FB27_Pos (27U)
5413 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
5414 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
5415 #define CAN_F6R2_FB28_Pos (28U)
5416 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
5417 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
5418 #define CAN_F6R2_FB29_Pos (29U)
5419 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
5420 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
5421 #define CAN_F6R2_FB30_Pos (30U)
5422 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
5423 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
5424 #define CAN_F6R2_FB31_Pos (31U)
5425 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
5426 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
5427
5428 /******************* Bit definition for CAN_F7R2 register *******************/
5429 #define CAN_F7R2_FB0_Pos (0U)
5430 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
5431 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
5432 #define CAN_F7R2_FB1_Pos (1U)
5433 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
5434 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
5435 #define CAN_F7R2_FB2_Pos (2U)
5436 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
5437 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
5438 #define CAN_F7R2_FB3_Pos (3U)
5439 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
5440 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
5441 #define CAN_F7R2_FB4_Pos (4U)
5442 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5443 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5444 #define CAN_F7R2_FB5_Pos (5U)
5445 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5446 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5447 #define CAN_F7R2_FB6_Pos (6U)
5448 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5449 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5450 #define CAN_F7R2_FB7_Pos (7U)
5451 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5452 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5453 #define CAN_F7R2_FB8_Pos (8U)
5454 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5455 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5456 #define CAN_F7R2_FB9_Pos (9U)
5457 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5458 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5459 #define CAN_F7R2_FB10_Pos (10U)
5460 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5461 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5462 #define CAN_F7R2_FB11_Pos (11U)
5463 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5464 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5465 #define CAN_F7R2_FB12_Pos (12U)
5466 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5467 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5468 #define CAN_F7R2_FB13_Pos (13U)
5469 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5470 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5471 #define CAN_F7R2_FB14_Pos (14U)
5472 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5473 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5474 #define CAN_F7R2_FB15_Pos (15U)
5475 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5476 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5477 #define CAN_F7R2_FB16_Pos (16U)
5478 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5479 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5480 #define CAN_F7R2_FB17_Pos (17U)
5481 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5482 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5483 #define CAN_F7R2_FB18_Pos (18U)
5484 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5485 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5486 #define CAN_F7R2_FB19_Pos (19U)
5487 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5488 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5489 #define CAN_F7R2_FB20_Pos (20U)
5490 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5491 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5492 #define CAN_F7R2_FB21_Pos (21U)
5493 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5494 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5495 #define CAN_F7R2_FB22_Pos (22U)
5496 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5497 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5498 #define CAN_F7R2_FB23_Pos (23U)
5499 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5500 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5501 #define CAN_F7R2_FB24_Pos (24U)
5502 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5503 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5504 #define CAN_F7R2_FB25_Pos (25U)
5505 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5506 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5507 #define CAN_F7R2_FB26_Pos (26U)
5508 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5509 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5510 #define CAN_F7R2_FB27_Pos (27U)
5511 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5512 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5513 #define CAN_F7R2_FB28_Pos (28U)
5514 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5515 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5516 #define CAN_F7R2_FB29_Pos (29U)
5517 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5518 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5519 #define CAN_F7R2_FB30_Pos (30U)
5520 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5521 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5522 #define CAN_F7R2_FB31_Pos (31U)
5523 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5524 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5525
5526 /******************* Bit definition for CAN_F8R2 register *******************/
5527 #define CAN_F8R2_FB0_Pos (0U)
5528 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5529 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5530 #define CAN_F8R2_FB1_Pos (1U)
5531 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5532 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5533 #define CAN_F8R2_FB2_Pos (2U)
5534 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5535 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5536 #define CAN_F8R2_FB3_Pos (3U)
5537 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5538 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5539 #define CAN_F8R2_FB4_Pos (4U)
5540 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5541 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5542 #define CAN_F8R2_FB5_Pos (5U)
5543 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5544 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5545 #define CAN_F8R2_FB6_Pos (6U)
5546 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5547 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5548 #define CAN_F8R2_FB7_Pos (7U)
5549 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5550 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5551 #define CAN_F8R2_FB8_Pos (8U)
5552 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5553 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5554 #define CAN_F8R2_FB9_Pos (9U)
5555 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5556 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5557 #define CAN_F8R2_FB10_Pos (10U)
5558 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5559 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5560 #define CAN_F8R2_FB11_Pos (11U)
5561 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5562 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5563 #define CAN_F8R2_FB12_Pos (12U)
5564 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5565 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5566 #define CAN_F8R2_FB13_Pos (13U)
5567 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5568 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5569 #define CAN_F8R2_FB14_Pos (14U)
5570 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5571 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5572 #define CAN_F8R2_FB15_Pos (15U)
5573 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5574 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5575 #define CAN_F8R2_FB16_Pos (16U)
5576 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5577 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5578 #define CAN_F8R2_FB17_Pos (17U)
5579 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5580 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5581 #define CAN_F8R2_FB18_Pos (18U)
5582 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5583 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5584 #define CAN_F8R2_FB19_Pos (19U)
5585 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5586 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5587 #define CAN_F8R2_FB20_Pos (20U)
5588 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5589 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5590 #define CAN_F8R2_FB21_Pos (21U)
5591 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5592 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5593 #define CAN_F8R2_FB22_Pos (22U)
5594 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5595 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5596 #define CAN_F8R2_FB23_Pos (23U)
5597 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5598 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5599 #define CAN_F8R2_FB24_Pos (24U)
5600 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5601 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5602 #define CAN_F8R2_FB25_Pos (25U)
5603 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5604 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5605 #define CAN_F8R2_FB26_Pos (26U)
5606 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5607 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5608 #define CAN_F8R2_FB27_Pos (27U)
5609 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5610 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5611 #define CAN_F8R2_FB28_Pos (28U)
5612 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5613 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5614 #define CAN_F8R2_FB29_Pos (29U)
5615 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5616 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5617 #define CAN_F8R2_FB30_Pos (30U)
5618 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5619 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5620 #define CAN_F8R2_FB31_Pos (31U)
5621 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5622 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5623
5624 /******************* Bit definition for CAN_F9R2 register *******************/
5625 #define CAN_F9R2_FB0_Pos (0U)
5626 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5627 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5628 #define CAN_F9R2_FB1_Pos (1U)
5629 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5630 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5631 #define CAN_F9R2_FB2_Pos (2U)
5632 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5633 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5634 #define CAN_F9R2_FB3_Pos (3U)
5635 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5636 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5637 #define CAN_F9R2_FB4_Pos (4U)
5638 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5639 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5640 #define CAN_F9R2_FB5_Pos (5U)
5641 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5642 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5643 #define CAN_F9R2_FB6_Pos (6U)
5644 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5645 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5646 #define CAN_F9R2_FB7_Pos (7U)
5647 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5648 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5649 #define CAN_F9R2_FB8_Pos (8U)
5650 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5651 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5652 #define CAN_F9R2_FB9_Pos (9U)
5653 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5654 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5655 #define CAN_F9R2_FB10_Pos (10U)
5656 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5657 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5658 #define CAN_F9R2_FB11_Pos (11U)
5659 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5660 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5661 #define CAN_F9R2_FB12_Pos (12U)
5662 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5663 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5664 #define CAN_F9R2_FB13_Pos (13U)
5665 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5666 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5667 #define CAN_F9R2_FB14_Pos (14U)
5668 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5669 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5670 #define CAN_F9R2_FB15_Pos (15U)
5671 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5672 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5673 #define CAN_F9R2_FB16_Pos (16U)
5674 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5675 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5676 #define CAN_F9R2_FB17_Pos (17U)
5677 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5678 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5679 #define CAN_F9R2_FB18_Pos (18U)
5680 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5681 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5682 #define CAN_F9R2_FB19_Pos (19U)
5683 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5684 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5685 #define CAN_F9R2_FB20_Pos (20U)
5686 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5687 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5688 #define CAN_F9R2_FB21_Pos (21U)
5689 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5690 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5691 #define CAN_F9R2_FB22_Pos (22U)
5692 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5693 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5694 #define CAN_F9R2_FB23_Pos (23U)
5695 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5696 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5697 #define CAN_F9R2_FB24_Pos (24U)
5698 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5699 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5700 #define CAN_F9R2_FB25_Pos (25U)
5701 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5702 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5703 #define CAN_F9R2_FB26_Pos (26U)
5704 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5705 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5706 #define CAN_F9R2_FB27_Pos (27U)
5707 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5708 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5709 #define CAN_F9R2_FB28_Pos (28U)
5710 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5711 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5712 #define CAN_F9R2_FB29_Pos (29U)
5713 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5714 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5715 #define CAN_F9R2_FB30_Pos (30U)
5716 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5717 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5718 #define CAN_F9R2_FB31_Pos (31U)
5719 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5720 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5721
5722 /******************* Bit definition for CAN_F10R2 register ******************/
5723 #define CAN_F10R2_FB0_Pos (0U)
5724 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5725 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5726 #define CAN_F10R2_FB1_Pos (1U)
5727 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5728 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5729 #define CAN_F10R2_FB2_Pos (2U)
5730 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5731 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5732 #define CAN_F10R2_FB3_Pos (3U)
5733 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5734 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5735 #define CAN_F10R2_FB4_Pos (4U)
5736 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5737 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5738 #define CAN_F10R2_FB5_Pos (5U)
5739 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5740 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5741 #define CAN_F10R2_FB6_Pos (6U)
5742 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5743 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5744 #define CAN_F10R2_FB7_Pos (7U)
5745 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5746 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5747 #define CAN_F10R2_FB8_Pos (8U)
5748 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5749 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5750 #define CAN_F10R2_FB9_Pos (9U)
5751 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5752 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5753 #define CAN_F10R2_FB10_Pos (10U)
5754 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5755 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5756 #define CAN_F10R2_FB11_Pos (11U)
5757 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5758 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5759 #define CAN_F10R2_FB12_Pos (12U)
5760 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5761 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5762 #define CAN_F10R2_FB13_Pos (13U)
5763 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5764 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5765 #define CAN_F10R2_FB14_Pos (14U)
5766 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5767 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5768 #define CAN_F10R2_FB15_Pos (15U)
5769 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5770 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5771 #define CAN_F10R2_FB16_Pos (16U)
5772 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5773 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5774 #define CAN_F10R2_FB17_Pos (17U)
5775 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5776 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5777 #define CAN_F10R2_FB18_Pos (18U)
5778 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5779 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5780 #define CAN_F10R2_FB19_Pos (19U)
5781 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5782 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5783 #define CAN_F10R2_FB20_Pos (20U)
5784 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5785 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5786 #define CAN_F10R2_FB21_Pos (21U)
5787 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5788 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5789 #define CAN_F10R2_FB22_Pos (22U)
5790 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5791 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5792 #define CAN_F10R2_FB23_Pos (23U)
5793 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5794 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5795 #define CAN_F10R2_FB24_Pos (24U)
5796 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5797 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5798 #define CAN_F10R2_FB25_Pos (25U)
5799 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5800 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5801 #define CAN_F10R2_FB26_Pos (26U)
5802 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5803 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5804 #define CAN_F10R2_FB27_Pos (27U)
5805 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5806 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5807 #define CAN_F10R2_FB28_Pos (28U)
5808 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5809 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5810 #define CAN_F10R2_FB29_Pos (29U)
5811 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5812 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5813 #define CAN_F10R2_FB30_Pos (30U)
5814 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5815 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5816 #define CAN_F10R2_FB31_Pos (31U)
5817 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5818 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5819
5820 /******************* Bit definition for CAN_F11R2 register ******************/
5821 #define CAN_F11R2_FB0_Pos (0U)
5822 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5823 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5824 #define CAN_F11R2_FB1_Pos (1U)
5825 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5826 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5827 #define CAN_F11R2_FB2_Pos (2U)
5828 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5829 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5830 #define CAN_F11R2_FB3_Pos (3U)
5831 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5832 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5833 #define CAN_F11R2_FB4_Pos (4U)
5834 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5835 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5836 #define CAN_F11R2_FB5_Pos (5U)
5837 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5838 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5839 #define CAN_F11R2_FB6_Pos (6U)
5840 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5841 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5842 #define CAN_F11R2_FB7_Pos (7U)
5843 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5844 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5845 #define CAN_F11R2_FB8_Pos (8U)
5846 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5847 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5848 #define CAN_F11R2_FB9_Pos (9U)
5849 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5850 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5851 #define CAN_F11R2_FB10_Pos (10U)
5852 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5853 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5854 #define CAN_F11R2_FB11_Pos (11U)
5855 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5856 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5857 #define CAN_F11R2_FB12_Pos (12U)
5858 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5859 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5860 #define CAN_F11R2_FB13_Pos (13U)
5861 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5862 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5863 #define CAN_F11R2_FB14_Pos (14U)
5864 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5865 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5866 #define CAN_F11R2_FB15_Pos (15U)
5867 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5868 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5869 #define CAN_F11R2_FB16_Pos (16U)
5870 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5871 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5872 #define CAN_F11R2_FB17_Pos (17U)
5873 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5874 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5875 #define CAN_F11R2_FB18_Pos (18U)
5876 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5877 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5878 #define CAN_F11R2_FB19_Pos (19U)
5879 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5880 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5881 #define CAN_F11R2_FB20_Pos (20U)
5882 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5883 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5884 #define CAN_F11R2_FB21_Pos (21U)
5885 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5886 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5887 #define CAN_F11R2_FB22_Pos (22U)
5888 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5889 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5890 #define CAN_F11R2_FB23_Pos (23U)
5891 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5892 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5893 #define CAN_F11R2_FB24_Pos (24U)
5894 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5895 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5896 #define CAN_F11R2_FB25_Pos (25U)
5897 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5898 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5899 #define CAN_F11R2_FB26_Pos (26U)
5900 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5901 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5902 #define CAN_F11R2_FB27_Pos (27U)
5903 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5904 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5905 #define CAN_F11R2_FB28_Pos (28U)
5906 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5907 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5908 #define CAN_F11R2_FB29_Pos (29U)
5909 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5910 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5911 #define CAN_F11R2_FB30_Pos (30U)
5912 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5913 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5914 #define CAN_F11R2_FB31_Pos (31U)
5915 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5916 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5917
5918 /******************* Bit definition for CAN_F12R2 register ******************/
5919 #define CAN_F12R2_FB0_Pos (0U)
5920 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5921 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5922 #define CAN_F12R2_FB1_Pos (1U)
5923 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5924 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5925 #define CAN_F12R2_FB2_Pos (2U)
5926 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5927 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5928 #define CAN_F12R2_FB3_Pos (3U)
5929 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5930 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5931 #define CAN_F12R2_FB4_Pos (4U)
5932 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5933 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5934 #define CAN_F12R2_FB5_Pos (5U)
5935 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5936 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5937 #define CAN_F12R2_FB6_Pos (6U)
5938 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5939 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5940 #define CAN_F12R2_FB7_Pos (7U)
5941 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5942 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5943 #define CAN_F12R2_FB8_Pos (8U)
5944 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5945 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5946 #define CAN_F12R2_FB9_Pos (9U)
5947 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5948 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5949 #define CAN_F12R2_FB10_Pos (10U)
5950 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5951 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5952 #define CAN_F12R2_FB11_Pos (11U)
5953 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5954 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5955 #define CAN_F12R2_FB12_Pos (12U)
5956 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5957 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5958 #define CAN_F12R2_FB13_Pos (13U)
5959 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5960 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5961 #define CAN_F12R2_FB14_Pos (14U)
5962 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5963 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5964 #define CAN_F12R2_FB15_Pos (15U)
5965 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5966 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5967 #define CAN_F12R2_FB16_Pos (16U)
5968 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5969 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5970 #define CAN_F12R2_FB17_Pos (17U)
5971 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5972 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5973 #define CAN_F12R2_FB18_Pos (18U)
5974 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5975 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5976 #define CAN_F12R2_FB19_Pos (19U)
5977 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5978 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5979 #define CAN_F12R2_FB20_Pos (20U)
5980 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5981 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5982 #define CAN_F12R2_FB21_Pos (21U)
5983 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5984 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5985 #define CAN_F12R2_FB22_Pos (22U)
5986 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5987 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5988 #define CAN_F12R2_FB23_Pos (23U)
5989 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5990 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5991 #define CAN_F12R2_FB24_Pos (24U)
5992 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5993 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5994 #define CAN_F12R2_FB25_Pos (25U)
5995 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5996 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5997 #define CAN_F12R2_FB26_Pos (26U)
5998 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5999 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
6000 #define CAN_F12R2_FB27_Pos (27U)
6001 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
6002 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
6003 #define CAN_F12R2_FB28_Pos (28U)
6004 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
6005 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
6006 #define CAN_F12R2_FB29_Pos (29U)
6007 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
6008 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
6009 #define CAN_F12R2_FB30_Pos (30U)
6010 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
6011 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
6012 #define CAN_F12R2_FB31_Pos (31U)
6013 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
6014 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
6015
6016 /******************* Bit definition for CAN_F13R2 register ******************/
6017 #define CAN_F13R2_FB0_Pos (0U)
6018 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
6019 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
6020 #define CAN_F13R2_FB1_Pos (1U)
6021 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
6022 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
6023 #define CAN_F13R2_FB2_Pos (2U)
6024 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
6025 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
6026 #define CAN_F13R2_FB3_Pos (3U)
6027 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
6028 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
6029 #define CAN_F13R2_FB4_Pos (4U)
6030 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
6031 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
6032 #define CAN_F13R2_FB5_Pos (5U)
6033 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
6034 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
6035 #define CAN_F13R2_FB6_Pos (6U)
6036 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
6037 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
6038 #define CAN_F13R2_FB7_Pos (7U)
6039 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
6040 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
6041 #define CAN_F13R2_FB8_Pos (8U)
6042 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
6043 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
6044 #define CAN_F13R2_FB9_Pos (9U)
6045 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
6046 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
6047 #define CAN_F13R2_FB10_Pos (10U)
6048 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
6049 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
6050 #define CAN_F13R2_FB11_Pos (11U)
6051 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
6052 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
6053 #define CAN_F13R2_FB12_Pos (12U)
6054 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
6055 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
6056 #define CAN_F13R2_FB13_Pos (13U)
6057 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
6058 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
6059 #define CAN_F13R2_FB14_Pos (14U)
6060 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
6061 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
6062 #define CAN_F13R2_FB15_Pos (15U)
6063 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
6064 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
6065 #define CAN_F13R2_FB16_Pos (16U)
6066 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
6067 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
6068 #define CAN_F13R2_FB17_Pos (17U)
6069 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
6070 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
6071 #define CAN_F13R2_FB18_Pos (18U)
6072 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
6073 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
6074 #define CAN_F13R2_FB19_Pos (19U)
6075 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
6076 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
6077 #define CAN_F13R2_FB20_Pos (20U)
6078 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
6079 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
6080 #define CAN_F13R2_FB21_Pos (21U)
6081 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
6082 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
6083 #define CAN_F13R2_FB22_Pos (22U)
6084 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
6085 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
6086 #define CAN_F13R2_FB23_Pos (23U)
6087 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
6088 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
6089 #define CAN_F13R2_FB24_Pos (24U)
6090 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
6091 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
6092 #define CAN_F13R2_FB25_Pos (25U)
6093 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
6094 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
6095 #define CAN_F13R2_FB26_Pos (26U)
6096 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
6097 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
6098 #define CAN_F13R2_FB27_Pos (27U)
6099 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
6100 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
6101 #define CAN_F13R2_FB28_Pos (28U)
6102 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
6103 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
6104 #define CAN_F13R2_FB29_Pos (29U)
6105 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
6106 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
6107 #define CAN_F13R2_FB30_Pos (30U)
6108 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
6109 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
6110 #define CAN_F13R2_FB31_Pos (31U)
6111 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
6112 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
6113
6114 /******************************************************************************/
6115 /* */
6116 /* CRC calculation unit */
6117 /* */
6118 /******************************************************************************/
6119 /******************* Bit definition for CRC_DR register *********************/
6120 #define CRC_DR_DR_Pos (0U)
6121 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
6122 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
6123
6124 /******************* Bit definition for CRC_IDR register ********************/
6125 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
6126
6127 /******************** Bit definition for CRC_CR register ********************/
6128 #define CRC_CR_RESET_Pos (0U)
6129 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
6130 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
6131 #define CRC_CR_POLYSIZE_Pos (3U)
6132 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
6133 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
6134 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
6135 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
6136 #define CRC_CR_REV_IN_Pos (5U)
6137 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
6138 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
6139 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
6140 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
6141 #define CRC_CR_REV_OUT_Pos (7U)
6142 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
6143 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
6144
6145 /******************* Bit definition for CRC_INIT register *******************/
6146 #define CRC_INIT_INIT_Pos (0U)
6147 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
6148 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
6149
6150 /******************* Bit definition for CRC_POL register ********************/
6151 #define CRC_POL_POL_Pos (0U)
6152 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
6153 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
6154
6155 /******************************************************************************/
6156 /* */
6157 /* Digital to Analog Converter */
6158 /* */
6159 /******************************************************************************/
6160 /*
6161 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
6162 */
6163 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
6164
6165 /******************** Bit definition for DAC_CR register ********************/
6166 #define DAC_CR_EN1_Pos (0U)
6167 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
6168 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
6169 #define DAC_CR_TEN1_Pos (2U)
6170 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
6171 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
6172
6173 #define DAC_CR_TSEL1_Pos (3U)
6174 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
6175 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
6176 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
6177 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
6178 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
6179
6180 #define DAC_CR_WAVE1_Pos (6U)
6181 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
6182 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
6183 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
6184 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
6185
6186 #define DAC_CR_MAMP1_Pos (8U)
6187 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
6188 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6189 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
6190 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
6191 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
6192 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
6193
6194 #define DAC_CR_DMAEN1_Pos (12U)
6195 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
6196 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
6197 #define DAC_CR_DMAUDRIE1_Pos (13U)
6198 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
6199 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
6200 #define DAC_CR_CEN1_Pos (14U)
6201 #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
6202 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
6203
6204 #define DAC_CR_EN2_Pos (16U)
6205 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
6206 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
6207 #define DAC_CR_TEN2_Pos (18U)
6208 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
6209 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
6210
6211 #define DAC_CR_TSEL2_Pos (19U)
6212 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
6213 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
6214 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
6215 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
6216 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
6217
6218 #define DAC_CR_WAVE2_Pos (22U)
6219 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
6220 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6221 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
6222 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
6223
6224 #define DAC_CR_MAMP2_Pos (24U)
6225 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
6226 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6227 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
6228 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
6229 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
6230 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
6231
6232 #define DAC_CR_DMAEN2_Pos (28U)
6233 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
6234 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
6235 #define DAC_CR_DMAUDRIE2_Pos (29U)
6236 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
6237 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
6238 #define DAC_CR_CEN2_Pos (30U)
6239 #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
6240 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
6241
6242 /***************** Bit definition for DAC_SWTRIGR register ******************/
6243 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6244 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
6245 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
6246 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6247 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
6248 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
6249
6250 /***************** Bit definition for DAC_DHR12R1 register ******************/
6251 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
6252 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
6253 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6254
6255 /***************** Bit definition for DAC_DHR12L1 register ******************/
6256 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
6257 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6258 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6259
6260 /****************** Bit definition for DAC_DHR8R1 register ******************/
6261 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
6262 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
6263 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6264
6265 /***************** Bit definition for DAC_DHR12R2 register ******************/
6266 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
6267 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
6268 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6269
6270 /***************** Bit definition for DAC_DHR12L2 register ******************/
6271 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
6272 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
6273 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6274
6275 /****************** Bit definition for DAC_DHR8R2 register ******************/
6276 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
6277 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
6278 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6279
6280 /***************** Bit definition for DAC_DHR12RD register ******************/
6281 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
6282 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
6283 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6284 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
6285 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
6286 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6287
6288 /***************** Bit definition for DAC_DHR12LD register ******************/
6289 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
6290 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6291 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6292 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
6293 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
6294 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6295
6296 /****************** Bit definition for DAC_DHR8RD register ******************/
6297 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
6298 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
6299 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6300 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
6301 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
6302 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6303
6304 /******************* Bit definition for DAC_DOR1 register *******************/
6305 #define DAC_DOR1_DACC1DOR_Pos (0U)
6306 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
6307 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
6308
6309 /******************* Bit definition for DAC_DOR2 register *******************/
6310 #define DAC_DOR2_DACC2DOR_Pos (0U)
6311 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
6312 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
6313
6314 /******************** Bit definition for DAC_SR register ********************/
6315 #define DAC_SR_DMAUDR1_Pos (13U)
6316 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
6317 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
6318 #define DAC_SR_CAL_FLAG1_Pos (14U)
6319 #define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
6320 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
6321 #define DAC_SR_BWST1_Pos (15U)
6322 #define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
6323 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
6324
6325 #define DAC_SR_DMAUDR2_Pos (29U)
6326 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
6327 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
6328 #define DAC_SR_CAL_FLAG2_Pos (30U)
6329 #define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
6330 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
6331 #define DAC_SR_BWST2_Pos (31U)
6332 #define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
6333 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
6334
6335 /******************* Bit definition for DAC_CCR register ********************/
6336 #define DAC_CCR_OTRIM1_Pos (0U)
6337 #define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
6338 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
6339 #define DAC_CCR_OTRIM2_Pos (16U)
6340 #define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
6341 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
6342
6343 /******************* Bit definition for DAC_MCR register *******************/
6344 #define DAC_MCR_MODE1_Pos (0U)
6345 #define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
6346 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
6347 #define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
6348 #define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
6349 #define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
6350
6351 #define DAC_MCR_MODE2_Pos (16U)
6352 #define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
6353 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
6354 #define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
6355 #define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
6356 #define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
6357
6358 /****************** Bit definition for DAC_SHSR1 register ******************/
6359 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
6360 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
6361 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
6362
6363 /****************** Bit definition for DAC_SHSR2 register ******************/
6364 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
6365 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
6366 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
6367
6368 /****************** Bit definition for DAC_SHHR register ******************/
6369 #define DAC_SHHR_THOLD1_Pos (0U)
6370 #define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
6371 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
6372 #define DAC_SHHR_THOLD2_Pos (16U)
6373 #define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
6374 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
6375
6376 /****************** Bit definition for DAC_SHRR register ******************/
6377 #define DAC_SHRR_TREFRESH1_Pos (0U)
6378 #define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
6379 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
6380 #define DAC_SHRR_TREFRESH2_Pos (16U)
6381 #define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
6382 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
6383
6384 /******************************************************************************/
6385 /* */
6386 /* Digital Filter for Sigma Delta Modulators */
6387 /* */
6388 /******************************************************************************/
6389
6390 /**************** DFSDM channel configuration registers ********************/
6391
6392 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6393 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6394 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6395 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6396 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6397 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6398 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6399 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6400 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6401 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6402 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6403 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6404 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6405 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6406 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6407 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6408 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6409 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6410 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6411 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6412 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6413 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6414 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6415 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
6416 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6417 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6418 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6419 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6420 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6421 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6422 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6423 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6424 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6425 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6426 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6427 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6428 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6429 #define DFSDM_CHCFGR1_SITP_Pos (0U)
6430 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6431 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6432 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6433 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6434
6435 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6436 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6437 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6438 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6439 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6440 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6441 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6442
6443 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
6444 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6445 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6446 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6447 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6448 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6449 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6450 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6451 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6452 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6453 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6454 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6455 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6456 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6457 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6458
6459 /**************** Bit definition for DFSDM_CHWDATR register *******************/
6460 #define DFSDM_CHWDATR_WDATA_Pos (0U)
6461 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6462 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6463
6464 /**************** Bit definition for DFSDM_CHDATINR register *****************/
6465 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
6466 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6467 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6468 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
6469 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6470 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6471
6472 /************************ DFSDM module registers ****************************/
6473
6474 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
6475 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6476 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6477 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6478 #define DFSDM_FLTCR1_FAST_Pos (29U)
6479 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6480 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6481 #define DFSDM_FLTCR1_RCH_Pos (24U)
6482 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6483 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6484 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6485 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6486 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6487 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
6488 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6489 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6490 #define DFSDM_FLTCR1_RCONT_Pos (18U)
6491 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6492 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6493 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6494 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6495 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6496 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6497 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6498 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6499 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6500 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6501 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6502 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
6503 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
6504 #define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6505 #define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6506 #define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6507 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6508 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6509 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6510 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
6511 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6512 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6513 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
6514 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6515 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6516 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6517 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6518 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6519 #define DFSDM_FLTCR1_DFEN_Pos (0U)
6520 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6521 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6522
6523 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
6524 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
6525 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6526 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6527 #define DFSDM_FLTCR2_EXCH_Pos (8U)
6528 #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6529 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6530 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
6531 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6532 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6533 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
6534 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6535 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6536 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
6537 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6538 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6539 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6540 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6541 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6542 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6543 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6544 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6545 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
6546 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6547 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6548 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6549 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6550 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6551
6552 /***************** Bit definition for DFSDM_FLTISR register *******************/
6553 #define DFSDM_FLTISR_SCDF_Pos (24U)
6554 #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6555 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6556 #define DFSDM_FLTISR_CKABF_Pos (16U)
6557 #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6558 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6559 #define DFSDM_FLTISR_RCIP_Pos (14U)
6560 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6561 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6562 #define DFSDM_FLTISR_JCIP_Pos (13U)
6563 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6564 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6565 #define DFSDM_FLTISR_AWDF_Pos (4U)
6566 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6567 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6568 #define DFSDM_FLTISR_ROVRF_Pos (3U)
6569 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6570 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6571 #define DFSDM_FLTISR_JOVRF_Pos (2U)
6572 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6573 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6574 #define DFSDM_FLTISR_REOCF_Pos (1U)
6575 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6576 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6577 #define DFSDM_FLTISR_JEOCF_Pos (0U)
6578 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6579 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6580
6581 /***************** Bit definition for DFSDM_FLTICR register *******************/
6582 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
6583 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
6584 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6585 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6586 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6587 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6588 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6589 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6590 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6591 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6592 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6593 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6594
6595 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
6596 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6597 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6598 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6599
6600 /***************** Bit definition for DFSDM_FLTFCR register *******************/
6601 #define DFSDM_FLTFCR_FORD_Pos (29U)
6602 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6603 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6604 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6605 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6606 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6607 #define DFSDM_FLTFCR_FOSR_Pos (16U)
6608 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6609 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6610 #define DFSDM_FLTFCR_IOSR_Pos (0U)
6611 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6612 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6613
6614 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
6615 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6616 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6617 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6618 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6619 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6620 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6621
6622 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
6623 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6624 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6625 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6626 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6627 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6628 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6629 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6630 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6631 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6632
6633 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
6634 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6635 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6636 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6637 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6638 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6639 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6640
6641 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
6642 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6643 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6644 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
6645 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6646 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6647 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6648
6649 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
6650 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6651 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6652 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6653 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6654 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6655 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6656
6657 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
6658 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6659 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6660 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6661 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6662 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6663 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6664
6665 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
6666 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6667 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6668 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6669 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6670 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6671 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6672
6673 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
6674 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6675 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6676 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6677 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6678 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6679 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6680
6681 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
6682 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6683 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6684 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6685
6686 /******************************************************************************/
6687 /* */
6688 /* DMA Controller (DMA) */
6689 /* */
6690 /******************************************************************************/
6691
6692 /******************* Bit definition for DMA_ISR register ********************/
6693 #define DMA_ISR_GIF1_Pos (0U)
6694 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
6695 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6696 #define DMA_ISR_TCIF1_Pos (1U)
6697 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
6698 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6699 #define DMA_ISR_HTIF1_Pos (2U)
6700 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
6701 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6702 #define DMA_ISR_TEIF1_Pos (3U)
6703 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
6704 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6705 #define DMA_ISR_GIF2_Pos (4U)
6706 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
6707 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6708 #define DMA_ISR_TCIF2_Pos (5U)
6709 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
6710 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6711 #define DMA_ISR_HTIF2_Pos (6U)
6712 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
6713 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6714 #define DMA_ISR_TEIF2_Pos (7U)
6715 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
6716 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6717 #define DMA_ISR_GIF3_Pos (8U)
6718 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
6719 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6720 #define DMA_ISR_TCIF3_Pos (9U)
6721 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
6722 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6723 #define DMA_ISR_HTIF3_Pos (10U)
6724 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
6725 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6726 #define DMA_ISR_TEIF3_Pos (11U)
6727 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
6728 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6729 #define DMA_ISR_GIF4_Pos (12U)
6730 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
6731 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6732 #define DMA_ISR_TCIF4_Pos (13U)
6733 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
6734 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6735 #define DMA_ISR_HTIF4_Pos (14U)
6736 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
6737 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6738 #define DMA_ISR_TEIF4_Pos (15U)
6739 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
6740 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6741 #define DMA_ISR_GIF5_Pos (16U)
6742 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
6743 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6744 #define DMA_ISR_TCIF5_Pos (17U)
6745 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
6746 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6747 #define DMA_ISR_HTIF5_Pos (18U)
6748 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
6749 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6750 #define DMA_ISR_TEIF5_Pos (19U)
6751 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
6752 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6753 #define DMA_ISR_GIF6_Pos (20U)
6754 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
6755 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6756 #define DMA_ISR_TCIF6_Pos (21U)
6757 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
6758 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6759 #define DMA_ISR_HTIF6_Pos (22U)
6760 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
6761 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6762 #define DMA_ISR_TEIF6_Pos (23U)
6763 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
6764 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6765 #define DMA_ISR_GIF7_Pos (24U)
6766 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
6767 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6768 #define DMA_ISR_TCIF7_Pos (25U)
6769 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
6770 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6771 #define DMA_ISR_HTIF7_Pos (26U)
6772 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
6773 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6774 #define DMA_ISR_TEIF7_Pos (27U)
6775 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
6776 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6777
6778 /******************* Bit definition for DMA_IFCR register *******************/
6779 #define DMA_IFCR_CGIF1_Pos (0U)
6780 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
6781 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
6782 #define DMA_IFCR_CTCIF1_Pos (1U)
6783 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
6784 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6785 #define DMA_IFCR_CHTIF1_Pos (2U)
6786 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
6787 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6788 #define DMA_IFCR_CTEIF1_Pos (3U)
6789 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
6790 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6791 #define DMA_IFCR_CGIF2_Pos (4U)
6792 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
6793 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6794 #define DMA_IFCR_CTCIF2_Pos (5U)
6795 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
6796 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6797 #define DMA_IFCR_CHTIF2_Pos (6U)
6798 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
6799 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6800 #define DMA_IFCR_CTEIF2_Pos (7U)
6801 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
6802 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6803 #define DMA_IFCR_CGIF3_Pos (8U)
6804 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
6805 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6806 #define DMA_IFCR_CTCIF3_Pos (9U)
6807 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
6808 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6809 #define DMA_IFCR_CHTIF3_Pos (10U)
6810 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
6811 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6812 #define DMA_IFCR_CTEIF3_Pos (11U)
6813 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
6814 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6815 #define DMA_IFCR_CGIF4_Pos (12U)
6816 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
6817 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6818 #define DMA_IFCR_CTCIF4_Pos (13U)
6819 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
6820 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6821 #define DMA_IFCR_CHTIF4_Pos (14U)
6822 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
6823 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6824 #define DMA_IFCR_CTEIF4_Pos (15U)
6825 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
6826 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6827 #define DMA_IFCR_CGIF5_Pos (16U)
6828 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
6829 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6830 #define DMA_IFCR_CTCIF5_Pos (17U)
6831 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
6832 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6833 #define DMA_IFCR_CHTIF5_Pos (18U)
6834 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
6835 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6836 #define DMA_IFCR_CTEIF5_Pos (19U)
6837 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
6838 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6839 #define DMA_IFCR_CGIF6_Pos (20U)
6840 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
6841 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6842 #define DMA_IFCR_CTCIF6_Pos (21U)
6843 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
6844 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6845 #define DMA_IFCR_CHTIF6_Pos (22U)
6846 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
6847 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6848 #define DMA_IFCR_CTEIF6_Pos (23U)
6849 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
6850 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6851 #define DMA_IFCR_CGIF7_Pos (24U)
6852 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
6853 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6854 #define DMA_IFCR_CTCIF7_Pos (25U)
6855 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
6856 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6857 #define DMA_IFCR_CHTIF7_Pos (26U)
6858 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
6859 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6860 #define DMA_IFCR_CTEIF7_Pos (27U)
6861 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
6862 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6863
6864 /******************* Bit definition for DMA_CCR register ********************/
6865 #define DMA_CCR_EN_Pos (0U)
6866 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
6867 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
6868 #define DMA_CCR_TCIE_Pos (1U)
6869 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6870 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6871 #define DMA_CCR_HTIE_Pos (2U)
6872 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6873 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6874 #define DMA_CCR_TEIE_Pos (3U)
6875 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6876 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6877 #define DMA_CCR_DIR_Pos (4U)
6878 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
6879 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
6880 #define DMA_CCR_CIRC_Pos (5U)
6881 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6882 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
6883 #define DMA_CCR_PINC_Pos (6U)
6884 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
6885 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6886 #define DMA_CCR_MINC_Pos (7U)
6887 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
6888 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
6889
6890 #define DMA_CCR_PSIZE_Pos (8U)
6891 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6892 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6893 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6894 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6895
6896 #define DMA_CCR_MSIZE_Pos (10U)
6897 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6898 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6899 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6900 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6901
6902 #define DMA_CCR_PL_Pos (12U)
6903 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
6904 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6905 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
6906 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
6907
6908 #define DMA_CCR_MEM2MEM_Pos (14U)
6909 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6910 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6911
6912 /****************** Bit definition for DMA_CNDTR register *******************/
6913 #define DMA_CNDTR_NDT_Pos (0U)
6914 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6915 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6916
6917 /****************** Bit definition for DMA_CPAR register ********************/
6918 #define DMA_CPAR_PA_Pos (0U)
6919 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6920 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
6921
6922 /****************** Bit definition for DMA_CMAR register ********************/
6923 #define DMA_CMAR_MA_Pos (0U)
6924 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
6925 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
6926
6927
6928 /******************* Bit definition for DMA_CSELR register *******************/
6929 #define DMA_CSELR_C1S_Pos (0U)
6930 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
6931 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
6932 #define DMA_CSELR_C2S_Pos (4U)
6933 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
6934 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
6935 #define DMA_CSELR_C3S_Pos (8U)
6936 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
6937 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
6938 #define DMA_CSELR_C4S_Pos (12U)
6939 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
6940 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
6941 #define DMA_CSELR_C5S_Pos (16U)
6942 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
6943 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
6944 #define DMA_CSELR_C6S_Pos (20U)
6945 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
6946 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
6947 #define DMA_CSELR_C7S_Pos (24U)
6948 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
6949 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
6950
6951 /******************************************************************************/
6952 /* */
6953 /* External Interrupt/Event Controller */
6954 /* */
6955 /******************************************************************************/
6956 /******************* Bit definition for EXTI_IMR1 register ******************/
6957 #define EXTI_IMR1_IM0_Pos (0U)
6958 #define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
6959 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
6960 #define EXTI_IMR1_IM1_Pos (1U)
6961 #define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
6962 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
6963 #define EXTI_IMR1_IM2_Pos (2U)
6964 #define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
6965 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
6966 #define EXTI_IMR1_IM3_Pos (3U)
6967 #define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
6968 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
6969 #define EXTI_IMR1_IM4_Pos (4U)
6970 #define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
6971 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
6972 #define EXTI_IMR1_IM5_Pos (5U)
6973 #define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
6974 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
6975 #define EXTI_IMR1_IM6_Pos (6U)
6976 #define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
6977 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
6978 #define EXTI_IMR1_IM7_Pos (7U)
6979 #define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
6980 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
6981 #define EXTI_IMR1_IM8_Pos (8U)
6982 #define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
6983 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
6984 #define EXTI_IMR1_IM9_Pos (9U)
6985 #define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
6986 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
6987 #define EXTI_IMR1_IM10_Pos (10U)
6988 #define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
6989 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
6990 #define EXTI_IMR1_IM11_Pos (11U)
6991 #define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
6992 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
6993 #define EXTI_IMR1_IM12_Pos (12U)
6994 #define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
6995 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
6996 #define EXTI_IMR1_IM13_Pos (13U)
6997 #define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
6998 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
6999 #define EXTI_IMR1_IM14_Pos (14U)
7000 #define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
7001 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
7002 #define EXTI_IMR1_IM15_Pos (15U)
7003 #define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
7004 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
7005 #define EXTI_IMR1_IM16_Pos (16U)
7006 #define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
7007 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
7008 #define EXTI_IMR1_IM17_Pos (17U)
7009 #define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
7010 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
7011 #define EXTI_IMR1_IM18_Pos (18U)
7012 #define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
7013 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
7014 #define EXTI_IMR1_IM19_Pos (19U)
7015 #define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
7016 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
7017 #define EXTI_IMR1_IM20_Pos (20U)
7018 #define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
7019 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
7020 #define EXTI_IMR1_IM21_Pos (21U)
7021 #define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
7022 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
7023 #define EXTI_IMR1_IM22_Pos (22U)
7024 #define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
7025 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
7026 #define EXTI_IMR1_IM23_Pos (23U)
7027 #define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
7028 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
7029 #define EXTI_IMR1_IM24_Pos (24U)
7030 #define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
7031 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
7032 #define EXTI_IMR1_IM25_Pos (25U)
7033 #define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
7034 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
7035 #define EXTI_IMR1_IM26_Pos (26U)
7036 #define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
7037 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
7038 #define EXTI_IMR1_IM27_Pos (27U)
7039 #define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
7040 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
7041 #define EXTI_IMR1_IM28_Pos (28U)
7042 #define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
7043 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
7044 #define EXTI_IMR1_IM29_Pos (29U)
7045 #define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
7046 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
7047 #define EXTI_IMR1_IM30_Pos (30U)
7048 #define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
7049 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
7050 #define EXTI_IMR1_IM31_Pos (31U)
7051 #define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
7052 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
7053 #define EXTI_IMR1_IM_Pos (0U)
7054 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
7055 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
7056
7057 /******************* Bit definition for EXTI_EMR1 register ******************/
7058 #define EXTI_EMR1_EM0_Pos (0U)
7059 #define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
7060 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
7061 #define EXTI_EMR1_EM1_Pos (1U)
7062 #define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
7063 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
7064 #define EXTI_EMR1_EM2_Pos (2U)
7065 #define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
7066 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
7067 #define EXTI_EMR1_EM3_Pos (3U)
7068 #define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
7069 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
7070 #define EXTI_EMR1_EM4_Pos (4U)
7071 #define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
7072 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
7073 #define EXTI_EMR1_EM5_Pos (5U)
7074 #define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
7075 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
7076 #define EXTI_EMR1_EM6_Pos (6U)
7077 #define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
7078 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
7079 #define EXTI_EMR1_EM7_Pos (7U)
7080 #define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
7081 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
7082 #define EXTI_EMR1_EM8_Pos (8U)
7083 #define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
7084 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
7085 #define EXTI_EMR1_EM9_Pos (9U)
7086 #define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
7087 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
7088 #define EXTI_EMR1_EM10_Pos (10U)
7089 #define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
7090 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
7091 #define EXTI_EMR1_EM11_Pos (11U)
7092 #define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
7093 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
7094 #define EXTI_EMR1_EM12_Pos (12U)
7095 #define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
7096 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
7097 #define EXTI_EMR1_EM13_Pos (13U)
7098 #define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
7099 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
7100 #define EXTI_EMR1_EM14_Pos (14U)
7101 #define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
7102 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
7103 #define EXTI_EMR1_EM15_Pos (15U)
7104 #define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
7105 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
7106 #define EXTI_EMR1_EM16_Pos (16U)
7107 #define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
7108 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
7109 #define EXTI_EMR1_EM17_Pos (17U)
7110 #define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
7111 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
7112 #define EXTI_EMR1_EM18_Pos (18U)
7113 #define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
7114 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
7115 #define EXTI_EMR1_EM19_Pos (19U)
7116 #define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
7117 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
7118 #define EXTI_EMR1_EM20_Pos (20U)
7119 #define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
7120 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
7121 #define EXTI_EMR1_EM21_Pos (21U)
7122 #define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
7123 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
7124 #define EXTI_EMR1_EM22_Pos (22U)
7125 #define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
7126 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
7127 #define EXTI_EMR1_EM23_Pos (23U)
7128 #define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
7129 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
7130 #define EXTI_EMR1_EM24_Pos (24U)
7131 #define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
7132 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
7133 #define EXTI_EMR1_EM25_Pos (25U)
7134 #define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
7135 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
7136 #define EXTI_EMR1_EM26_Pos (26U)
7137 #define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
7138 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
7139 #define EXTI_EMR1_EM27_Pos (27U)
7140 #define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
7141 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
7142 #define EXTI_EMR1_EM28_Pos (28U)
7143 #define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
7144 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
7145 #define EXTI_EMR1_EM29_Pos (29U)
7146 #define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
7147 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
7148 #define EXTI_EMR1_EM30_Pos (30U)
7149 #define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
7150 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
7151 #define EXTI_EMR1_EM31_Pos (31U)
7152 #define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
7153 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
7154
7155 /****************** Bit definition for EXTI_RTSR1 register ******************/
7156 #define EXTI_RTSR1_RT0_Pos (0U)
7157 #define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
7158 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
7159 #define EXTI_RTSR1_RT1_Pos (1U)
7160 #define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
7161 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
7162 #define EXTI_RTSR1_RT2_Pos (2U)
7163 #define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
7164 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
7165 #define EXTI_RTSR1_RT3_Pos (3U)
7166 #define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
7167 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
7168 #define EXTI_RTSR1_RT4_Pos (4U)
7169 #define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
7170 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
7171 #define EXTI_RTSR1_RT5_Pos (5U)
7172 #define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
7173 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
7174 #define EXTI_RTSR1_RT6_Pos (6U)
7175 #define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
7176 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
7177 #define EXTI_RTSR1_RT7_Pos (7U)
7178 #define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
7179 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
7180 #define EXTI_RTSR1_RT8_Pos (8U)
7181 #define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
7182 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
7183 #define EXTI_RTSR1_RT9_Pos (9U)
7184 #define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
7185 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
7186 #define EXTI_RTSR1_RT10_Pos (10U)
7187 #define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
7188 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
7189 #define EXTI_RTSR1_RT11_Pos (11U)
7190 #define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
7191 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
7192 #define EXTI_RTSR1_RT12_Pos (12U)
7193 #define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
7194 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
7195 #define EXTI_RTSR1_RT13_Pos (13U)
7196 #define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
7197 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
7198 #define EXTI_RTSR1_RT14_Pos (14U)
7199 #define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
7200 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
7201 #define EXTI_RTSR1_RT15_Pos (15U)
7202 #define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
7203 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
7204 #define EXTI_RTSR1_RT16_Pos (16U)
7205 #define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
7206 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
7207 #define EXTI_RTSR1_RT18_Pos (18U)
7208 #define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
7209 #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
7210 #define EXTI_RTSR1_RT19_Pos (19U)
7211 #define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
7212 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
7213 #define EXTI_RTSR1_RT20_Pos (20U)
7214 #define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
7215 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
7216 #define EXTI_RTSR1_RT21_Pos (21U)
7217 #define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
7218 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
7219 #define EXTI_RTSR1_RT22_Pos (22U)
7220 #define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
7221 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
7222
7223 /****************** Bit definition for EXTI_FTSR1 register ******************/
7224 #define EXTI_FTSR1_FT0_Pos (0U)
7225 #define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
7226 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
7227 #define EXTI_FTSR1_FT1_Pos (1U)
7228 #define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
7229 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
7230 #define EXTI_FTSR1_FT2_Pos (2U)
7231 #define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
7232 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
7233 #define EXTI_FTSR1_FT3_Pos (3U)
7234 #define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
7235 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
7236 #define EXTI_FTSR1_FT4_Pos (4U)
7237 #define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
7238 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
7239 #define EXTI_FTSR1_FT5_Pos (5U)
7240 #define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
7241 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
7242 #define EXTI_FTSR1_FT6_Pos (6U)
7243 #define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
7244 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
7245 #define EXTI_FTSR1_FT7_Pos (7U)
7246 #define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
7247 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
7248 #define EXTI_FTSR1_FT8_Pos (8U)
7249 #define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
7250 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
7251 #define EXTI_FTSR1_FT9_Pos (9U)
7252 #define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
7253 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
7254 #define EXTI_FTSR1_FT10_Pos (10U)
7255 #define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
7256 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
7257 #define EXTI_FTSR1_FT11_Pos (11U)
7258 #define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
7259 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
7260 #define EXTI_FTSR1_FT12_Pos (12U)
7261 #define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
7262 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
7263 #define EXTI_FTSR1_FT13_Pos (13U)
7264 #define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
7265 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
7266 #define EXTI_FTSR1_FT14_Pos (14U)
7267 #define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
7268 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
7269 #define EXTI_FTSR1_FT15_Pos (15U)
7270 #define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
7271 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
7272 #define EXTI_FTSR1_FT16_Pos (16U)
7273 #define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
7274 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
7275 #define EXTI_FTSR1_FT18_Pos (18U)
7276 #define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
7277 #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
7278 #define EXTI_FTSR1_FT19_Pos (19U)
7279 #define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
7280 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
7281 #define EXTI_FTSR1_FT20_Pos (20U)
7282 #define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
7283 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
7284 #define EXTI_FTSR1_FT21_Pos (21U)
7285 #define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
7286 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
7287 #define EXTI_FTSR1_FT22_Pos (22U)
7288 #define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
7289 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
7290
7291 /****************** Bit definition for EXTI_SWIER1 register *****************/
7292 #define EXTI_SWIER1_SWI0_Pos (0U)
7293 #define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
7294 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
7295 #define EXTI_SWIER1_SWI1_Pos (1U)
7296 #define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
7297 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
7298 #define EXTI_SWIER1_SWI2_Pos (2U)
7299 #define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
7300 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
7301 #define EXTI_SWIER1_SWI3_Pos (3U)
7302 #define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
7303 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
7304 #define EXTI_SWIER1_SWI4_Pos (4U)
7305 #define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
7306 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
7307 #define EXTI_SWIER1_SWI5_Pos (5U)
7308 #define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
7309 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
7310 #define EXTI_SWIER1_SWI6_Pos (6U)
7311 #define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
7312 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
7313 #define EXTI_SWIER1_SWI7_Pos (7U)
7314 #define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
7315 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
7316 #define EXTI_SWIER1_SWI8_Pos (8U)
7317 #define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
7318 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
7319 #define EXTI_SWIER1_SWI9_Pos (9U)
7320 #define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
7321 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
7322 #define EXTI_SWIER1_SWI10_Pos (10U)
7323 #define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
7324 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
7325 #define EXTI_SWIER1_SWI11_Pos (11U)
7326 #define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
7327 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
7328 #define EXTI_SWIER1_SWI12_Pos (12U)
7329 #define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
7330 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
7331 #define EXTI_SWIER1_SWI13_Pos (13U)
7332 #define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
7333 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
7334 #define EXTI_SWIER1_SWI14_Pos (14U)
7335 #define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
7336 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
7337 #define EXTI_SWIER1_SWI15_Pos (15U)
7338 #define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
7339 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
7340 #define EXTI_SWIER1_SWI16_Pos (16U)
7341 #define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
7342 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
7343 #define EXTI_SWIER1_SWI18_Pos (18U)
7344 #define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
7345 #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
7346 #define EXTI_SWIER1_SWI19_Pos (19U)
7347 #define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
7348 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
7349 #define EXTI_SWIER1_SWI20_Pos (20U)
7350 #define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
7351 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
7352 #define EXTI_SWIER1_SWI21_Pos (21U)
7353 #define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
7354 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
7355 #define EXTI_SWIER1_SWI22_Pos (22U)
7356 #define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
7357 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
7358
7359 /******************* Bit definition for EXTI_PR1 register *******************/
7360 #define EXTI_PR1_PIF0_Pos (0U)
7361 #define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
7362 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
7363 #define EXTI_PR1_PIF1_Pos (1U)
7364 #define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
7365 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
7366 #define EXTI_PR1_PIF2_Pos (2U)
7367 #define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
7368 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
7369 #define EXTI_PR1_PIF3_Pos (3U)
7370 #define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
7371 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
7372 #define EXTI_PR1_PIF4_Pos (4U)
7373 #define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
7374 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
7375 #define EXTI_PR1_PIF5_Pos (5U)
7376 #define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
7377 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
7378 #define EXTI_PR1_PIF6_Pos (6U)
7379 #define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
7380 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
7381 #define EXTI_PR1_PIF7_Pos (7U)
7382 #define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
7383 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
7384 #define EXTI_PR1_PIF8_Pos (8U)
7385 #define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
7386 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
7387 #define EXTI_PR1_PIF9_Pos (9U)
7388 #define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
7389 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
7390 #define EXTI_PR1_PIF10_Pos (10U)
7391 #define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
7392 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
7393 #define EXTI_PR1_PIF11_Pos (11U)
7394 #define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
7395 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
7396 #define EXTI_PR1_PIF12_Pos (12U)
7397 #define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
7398 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
7399 #define EXTI_PR1_PIF13_Pos (13U)
7400 #define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
7401 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
7402 #define EXTI_PR1_PIF14_Pos (14U)
7403 #define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
7404 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
7405 #define EXTI_PR1_PIF15_Pos (15U)
7406 #define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
7407 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
7408 #define EXTI_PR1_PIF16_Pos (16U)
7409 #define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
7410 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
7411 #define EXTI_PR1_PIF18_Pos (18U)
7412 #define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
7413 #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
7414 #define EXTI_PR1_PIF19_Pos (19U)
7415 #define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
7416 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
7417 #define EXTI_PR1_PIF20_Pos (20U)
7418 #define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
7419 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
7420 #define EXTI_PR1_PIF21_Pos (21U)
7421 #define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
7422 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
7423 #define EXTI_PR1_PIF22_Pos (22U)
7424 #define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
7425 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
7426
7427 /******************* Bit definition for EXTI_IMR2 register ******************/
7428 #define EXTI_IMR2_IM32_Pos (0U)
7429 #define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
7430 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
7431 #define EXTI_IMR2_IM33_Pos (1U)
7432 #define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
7433 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
7434 #define EXTI_IMR2_IM34_Pos (2U)
7435 #define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
7436 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
7437 #define EXTI_IMR2_IM35_Pos (3U)
7438 #define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
7439 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
7440 #define EXTI_IMR2_IM36_Pos (4U)
7441 #define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
7442 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
7443 #define EXTI_IMR2_IM37_Pos (5U)
7444 #define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
7445 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
7446 #define EXTI_IMR2_IM38_Pos (6U)
7447 #define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
7448 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
7449 #define EXTI_IMR2_IM39_Pos (7U)
7450 #define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
7451 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
7452 #define EXTI_IMR2_IM_Pos (0U)
7453 #define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
7454 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
7455
7456 /******************* Bit definition for EXTI_EMR2 register ******************/
7457 #define EXTI_EMR2_EM32_Pos (0U)
7458 #define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
7459 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
7460 #define EXTI_EMR2_EM33_Pos (1U)
7461 #define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
7462 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
7463 #define EXTI_EMR2_EM34_Pos (2U)
7464 #define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
7465 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
7466 #define EXTI_EMR2_EM35_Pos (3U)
7467 #define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
7468 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
7469 #define EXTI_EMR2_EM36_Pos (4U)
7470 #define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
7471 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
7472 #define EXTI_EMR2_EM37_Pos (5U)
7473 #define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
7474 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
7475 #define EXTI_EMR2_EM38_Pos (6U)
7476 #define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
7477 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
7478 #define EXTI_EMR2_EM39_Pos (7U)
7479 #define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
7480 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
7481
7482 /****************** Bit definition for EXTI_RTSR2 register ******************/
7483 #define EXTI_RTSR2_RT35_Pos (3U)
7484 #define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
7485 #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
7486 #define EXTI_RTSR2_RT36_Pos (4U)
7487 #define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
7488 #define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
7489 #define EXTI_RTSR2_RT37_Pos (5U)
7490 #define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
7491 #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
7492 #define EXTI_RTSR2_RT38_Pos (6U)
7493 #define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
7494 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
7495
7496 /****************** Bit definition for EXTI_FTSR2 register ******************/
7497 #define EXTI_FTSR2_FT35_Pos (3U)
7498 #define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
7499 #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
7500 #define EXTI_FTSR2_FT36_Pos (4U)
7501 #define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
7502 #define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
7503 #define EXTI_FTSR2_FT37_Pos (5U)
7504 #define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
7505 #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
7506 #define EXTI_FTSR2_FT38_Pos (6U)
7507 #define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
7508 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
7509
7510 /****************** Bit definition for EXTI_SWIER2 register *****************/
7511 #define EXTI_SWIER2_SWI35_Pos (3U)
7512 #define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
7513 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
7514 #define EXTI_SWIER2_SWI36_Pos (4U)
7515 #define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
7516 #define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
7517 #define EXTI_SWIER2_SWI37_Pos (5U)
7518 #define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
7519 #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
7520 #define EXTI_SWIER2_SWI38_Pos (6U)
7521 #define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
7522 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
7523
7524 /******************* Bit definition for EXTI_PR2 register *******************/
7525 #define EXTI_PR2_PIF35_Pos (3U)
7526 #define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
7527 #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
7528 #define EXTI_PR2_PIF36_Pos (4U)
7529 #define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
7530 #define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
7531 #define EXTI_PR2_PIF37_Pos (5U)
7532 #define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
7533 #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
7534 #define EXTI_PR2_PIF38_Pos (6U)
7535 #define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
7536 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
7537
7538
7539 /******************************************************************************/
7540 /* */
7541 /* FLASH */
7542 /* */
7543 /******************************************************************************/
7544 /******************* Bits definition for FLASH_ACR register *****************/
7545 #define FLASH_ACR_LATENCY_Pos (0U)
7546 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
7547 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7548 #define FLASH_ACR_LATENCY_0WS (0x00000000U)
7549 #define FLASH_ACR_LATENCY_1WS (0x00000001U)
7550 #define FLASH_ACR_LATENCY_2WS (0x00000002U)
7551 #define FLASH_ACR_LATENCY_3WS (0x00000003U)
7552 #define FLASH_ACR_LATENCY_4WS (0x00000004U)
7553 #define FLASH_ACR_PRFTEN_Pos (8U)
7554 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
7555 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7556 #define FLASH_ACR_ICEN_Pos (9U)
7557 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
7558 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
7559 #define FLASH_ACR_DCEN_Pos (10U)
7560 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
7561 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
7562 #define FLASH_ACR_ICRST_Pos (11U)
7563 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
7564 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
7565 #define FLASH_ACR_DCRST_Pos (12U)
7566 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
7567 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
7568 #define FLASH_ACR_RUN_PD_Pos (13U)
7569 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
7570 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
7571 #define FLASH_ACR_SLEEP_PD_Pos (14U)
7572 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
7573 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
7574
7575 /******************* Bits definition for FLASH_SR register ******************/
7576 #define FLASH_SR_EOP_Pos (0U)
7577 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
7578 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
7579 #define FLASH_SR_OPERR_Pos (1U)
7580 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
7581 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7582 #define FLASH_SR_PROGERR_Pos (3U)
7583 #define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
7584 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
7585 #define FLASH_SR_WRPERR_Pos (4U)
7586 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
7587 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7588 #define FLASH_SR_PGAERR_Pos (5U)
7589 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
7590 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7591 #define FLASH_SR_SIZERR_Pos (6U)
7592 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
7593 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
7594 #define FLASH_SR_PGSERR_Pos (7U)
7595 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
7596 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
7597 #define FLASH_SR_MISERR_Pos (8U)
7598 #define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
7599 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
7600 #define FLASH_SR_FASTERR_Pos (9U)
7601 #define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
7602 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
7603 #define FLASH_SR_RDERR_Pos (14U)
7604 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
7605 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
7606 #define FLASH_SR_OPTVERR_Pos (15U)
7607 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
7608 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
7609 #define FLASH_SR_BSY_Pos (16U)
7610 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
7611 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
7612
7613 /******************* Bits definition for FLASH_CR register ******************/
7614 #define FLASH_CR_PG_Pos (0U)
7615 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
7616 #define FLASH_CR_PG FLASH_CR_PG_Msk
7617 #define FLASH_CR_PER_Pos (1U)
7618 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
7619 #define FLASH_CR_PER FLASH_CR_PER_Msk
7620 #define FLASH_CR_MER1_Pos (2U)
7621 #define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
7622 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
7623 #define FLASH_CR_PNB_Pos (3U)
7624 #define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
7625 #define FLASH_CR_PNB FLASH_CR_PNB_Msk
7626 #define FLASH_CR_BKER_Pos (11U)
7627 #define FLASH_CR_BKER_Msk (0x1U << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
7628 #define FLASH_CR_BKER FLASH_CR_BKER_Msk
7629 #define FLASH_CR_MER2_Pos (15U)
7630 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
7631 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
7632 #define FLASH_CR_STRT_Pos (16U)
7633 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
7634 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
7635 #define FLASH_CR_OPTSTRT_Pos (17U)
7636 #define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
7637 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
7638 #define FLASH_CR_FSTPG_Pos (18U)
7639 #define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
7640 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
7641 #define FLASH_CR_EOPIE_Pos (24U)
7642 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
7643 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7644 #define FLASH_CR_ERRIE_Pos (25U)
7645 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
7646 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
7647 #define FLASH_CR_RDERRIE_Pos (26U)
7648 #define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
7649 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
7650 #define FLASH_CR_OBL_LAUNCH_Pos (27U)
7651 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
7652 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
7653 #define FLASH_CR_OPTLOCK_Pos (30U)
7654 #define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
7655 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
7656 #define FLASH_CR_LOCK_Pos (31U)
7657 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
7658 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7659
7660 /******************* Bits definition for FLASH_ECCR register ***************/
7661 #define FLASH_ECCR_ADDR_ECC_Pos (0U)
7662 #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
7663 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
7664 #define FLASH_ECCR_BK_ECC_Pos (19U)
7665 #define FLASH_ECCR_BK_ECC_Msk (0x1U << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00080000 */
7666 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
7667 #define FLASH_ECCR_SYSF_ECC_Pos (20U)
7668 #define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
7669 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
7670 #define FLASH_ECCR_ECCIE_Pos (24U)
7671 #define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
7672 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
7673 #define FLASH_ECCR_ECCC_Pos (30U)
7674 #define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
7675 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
7676 #define FLASH_ECCR_ECCD_Pos (31U)
7677 #define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
7678 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
7679
7680 /******************* Bits definition for FLASH_OPTR register ***************/
7681 #define FLASH_OPTR_RDP_Pos (0U)
7682 #define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
7683 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
7684 #define FLASH_OPTR_BOR_LEV_Pos (8U)
7685 #define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
7686 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
7687 #define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
7688 #define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
7689 #define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
7690 #define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
7691 #define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
7692 #define FLASH_OPTR_nRST_STOP_Pos (12U)
7693 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
7694 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
7695 #define FLASH_OPTR_nRST_STDBY_Pos (13U)
7696 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
7697 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
7698 #define FLASH_OPTR_nRST_SHDW_Pos (14U)
7699 #define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
7700 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
7701 #define FLASH_OPTR_IWDG_SW_Pos (16U)
7702 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
7703 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
7704 #define FLASH_OPTR_IWDG_STOP_Pos (17U)
7705 #define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
7706 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
7707 #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
7708 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
7709 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
7710 #define FLASH_OPTR_WWDG_SW_Pos (19U)
7711 #define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
7712 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
7713 #define FLASH_OPTR_BFB2_Pos (20U)
7714 #define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
7715 #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
7716 #define FLASH_OPTR_DUALBANK_Pos (21U)
7717 #define FLASH_OPTR_DUALBANK_Msk (0x1U << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */
7718 #define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk
7719 #define FLASH_OPTR_nBOOT1_Pos (23U)
7720 #define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
7721 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
7722 #define FLASH_OPTR_SRAM2_PE_Pos (24U)
7723 #define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
7724 #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
7725 #define FLASH_OPTR_SRAM2_RST_Pos (25U)
7726 #define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
7727 #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
7728
7729 /****************** Bits definition for FLASH_PCROP1SR register **********/
7730 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
7731 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
7732 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
7733
7734 /****************** Bits definition for FLASH_PCROP1ER register ***********/
7735 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
7736 #define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
7737 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
7738 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
7739 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
7740 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
7741
7742 /****************** Bits definition for FLASH_WRP1AR register ***************/
7743 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
7744 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
7745 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
7746 #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7747 #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7748 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
7749
7750 /****************** Bits definition for FLASH_WRPB1R register ***************/
7751 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
7752 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
7753 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
7754 #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7755 #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7756 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
7757
7758 /****************** Bits definition for FLASH_PCROP2SR register **********/
7759 #define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
7760 #define FLASH_PCROP2SR_PCROP2_STRT_Msk (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
7761 #define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
7762
7763 /****************** Bits definition for FLASH_PCROP2ER register ***********/
7764 #define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
7765 #define FLASH_PCROP2ER_PCROP2_END_Msk (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
7766 #define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
7767
7768 /****************** Bits definition for FLASH_WRP2AR register ***************/
7769 #define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
7770 #define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
7771 #define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
7772 #define FLASH_WRP2AR_WRP2A_END_Pos (16U)
7773 #define FLASH_WRP2AR_WRP2A_END_Msk (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
7774 #define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
7775
7776 /****************** Bits definition for FLASH_WRP2BR register ***************/
7777 #define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
7778 #define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
7779 #define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
7780 #define FLASH_WRP2BR_WRP2B_END_Pos (16U)
7781 #define FLASH_WRP2BR_WRP2B_END_Msk (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
7782 #define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
7783
7784
7785 /******************************************************************************/
7786 /* */
7787 /* Flexible Memory Controller */
7788 /* */
7789 /******************************************************************************/
7790 /****************** Bit definition for FMC_BCR1 register *******************/
7791 #define FMC_BCR1_CCLKEN_Pos (20U)
7792 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
7793 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
7794
7795 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
7796 #define FMC_BCRx_MBKEN_Pos (0U)
7797 #define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
7798 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
7799 #define FMC_BCRx_MUXEN_Pos (1U)
7800 #define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
7801 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7802
7803 #define FMC_BCRx_MTYP_Pos (2U)
7804 #define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
7805 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7806 #define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
7807 #define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
7808
7809 #define FMC_BCRx_MWID_Pos (4U)
7810 #define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
7811 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7812 #define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
7813 #define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
7814
7815 #define FMC_BCRx_FACCEN_Pos (6U)
7816 #define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
7817 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
7818 #define FMC_BCRx_BURSTEN_Pos (8U)
7819 #define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
7820 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
7821 #define FMC_BCRx_WAITPOL_Pos (9U)
7822 #define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
7823 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
7824 #define FMC_BCRx_WAITCFG_Pos (11U)
7825 #define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
7826 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
7827 #define FMC_BCRx_WREN_Pos (12U)
7828 #define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
7829 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
7830 #define FMC_BCRx_WAITEN_Pos (13U)
7831 #define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
7832 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
7833 #define FMC_BCRx_EXTMOD_Pos (14U)
7834 #define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
7835 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
7836 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
7837 #define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
7838 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
7839
7840 #define FMC_BCRx_CPSIZE_Pos (16U)
7841 #define FMC_BCRx_CPSIZE_Msk (0x7U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
7842 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
7843 #define FMC_BCRx_CPSIZE_0 (0x1U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
7844 #define FMC_BCRx_CPSIZE_1 (0x2U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
7845 #define FMC_BCRx_CPSIZE_2 (0x4U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
7846
7847 #define FMC_BCRx_CBURSTRW_Pos (19U)
7848 #define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
7849 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
7850
7851 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
7852 #define FMC_BTRx_ADDSET_Pos (0U)
7853 #define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
7854 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7855 #define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
7856 #define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
7857 #define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
7858 #define FMC_BTRx_ADDSET_3 (0x8U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
7859
7860 #define FMC_BTRx_ADDHLD_Pos (4U)
7861 #define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
7862 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7863 #define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
7864 #define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
7865 #define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
7866 #define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
7867
7868 #define FMC_BTRx_DATAST_Pos (8U)
7869 #define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
7870 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7871 #define FMC_BTRx_DATAST_0 (0x01U << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
7872 #define FMC_BTRx_DATAST_1 (0x02U << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
7873 #define FMC_BTRx_DATAST_2 (0x04U << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
7874 #define FMC_BTRx_DATAST_3 (0x08U << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
7875 #define FMC_BTRx_DATAST_4 (0x10U << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
7876 #define FMC_BTRx_DATAST_5 (0x20U << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
7877 #define FMC_BTRx_DATAST_6 (0x40U << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
7878 #define FMC_BTRx_DATAST_7 (0x80U << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
7879
7880 #define FMC_BTRx_BUSTURN_Pos (16U)
7881 #define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
7882 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7883 #define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
7884 #define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
7885 #define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
7886 #define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
7887
7888 #define FMC_BTRx_CLKDIV_Pos (20U)
7889 #define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
7890 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7891 #define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
7892 #define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
7893 #define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
7894 #define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
7895
7896 #define FMC_BTRx_DATLAT_Pos (24U)
7897 #define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
7898 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
7899 #define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
7900 #define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
7901 #define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
7902 #define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
7903
7904 #define FMC_BTRx_ACCMOD_Pos (28U)
7905 #define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
7906 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7907 #define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
7908 #define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
7909
7910 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
7911 #define FMC_BWTRx_ADDSET_Pos (0U)
7912 #define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
7913 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7914 #define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
7915 #define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
7916 #define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
7917 #define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
7918
7919 #define FMC_BWTRx_ADDHLD_Pos (4U)
7920 #define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
7921 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7922 #define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
7923 #define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
7924 #define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
7925 #define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
7926
7927 #define FMC_BWTRx_DATAST_Pos (8U)
7928 #define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
7929 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7930 #define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
7931 #define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
7932 #define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
7933 #define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
7934 #define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
7935 #define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
7936 #define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
7937 #define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
7938
7939 #define FMC_BWTRx_BUSTURN_Pos (16U)
7940 #define FMC_BWTRx_BUSTURN_Msk (0xFU << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
7941 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7942 #define FMC_BWTRx_BUSTURN_0 (0x1U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
7943 #define FMC_BWTRx_BUSTURN_1 (0x2U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
7944 #define FMC_BWTRx_BUSTURN_2 (0x4U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
7945 #define FMC_BWTRx_BUSTURN_3 (0x8U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
7946
7947 #define FMC_BWTRx_ACCMOD_Pos (28U)
7948 #define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
7949 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7950 #define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
7951 #define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
7952
7953 /****************** Bit definition for FMC_PCR register ********************/
7954 #define FMC_PCR_PWAITEN_Pos (1U)
7955 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
7956 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
7957 #define FMC_PCR_PBKEN_Pos (2U)
7958 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
7959 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
7960 #define FMC_PCR_PTYP_Pos (3U)
7961 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
7962 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
7963
7964 #define FMC_PCR_PWID_Pos (4U)
7965 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
7966 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7967 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
7968 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
7969
7970 #define FMC_PCR_ECCEN_Pos (6U)
7971 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
7972 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
7973
7974 #define FMC_PCR_TCLR_Pos (9U)
7975 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
7976 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7977 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
7978 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
7979 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
7980 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
7981
7982 #define FMC_PCR_TAR_Pos (13U)
7983 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
7984 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7985 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
7986 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
7987 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
7988 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
7989
7990 #define FMC_PCR_ECCPS_Pos (17U)
7991 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
7992 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
7993 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
7994 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
7995 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
7996
7997 /******************* Bit definition for FMC_SR register ********************/
7998 #define FMC_SR_IRS_Pos (0U)
7999 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
8000 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
8001 #define FMC_SR_ILS_Pos (1U)
8002 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
8003 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
8004 #define FMC_SR_IFS_Pos (2U)
8005 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
8006 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
8007 #define FMC_SR_IREN_Pos (3U)
8008 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
8009 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
8010 #define FMC_SR_ILEN_Pos (4U)
8011 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
8012 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
8013 #define FMC_SR_IFEN_Pos (5U)
8014 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
8015 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
8016 #define FMC_SR_FEMPT_Pos (6U)
8017 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
8018 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
8019
8020 /****************** Bit definition for FMC_PMEM register ******************/
8021 #define FMC_PMEM_MEMSET_Pos (0U)
8022 #define FMC_PMEM_MEMSET_Msk (0xFFU << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
8023 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
8024 #define FMC_PMEM_MEMSET_0 (0x01U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
8025 #define FMC_PMEM_MEMSET_1 (0x02U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
8026 #define FMC_PMEM_MEMSET_2 (0x04U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
8027 #define FMC_PMEM_MEMSET_3 (0x08U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
8028 #define FMC_PMEM_MEMSET_4 (0x10U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
8029 #define FMC_PMEM_MEMSET_5 (0x20U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
8030 #define FMC_PMEM_MEMSET_6 (0x40U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
8031 #define FMC_PMEM_MEMSET_7 (0x80U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
8032
8033 #define FMC_PMEM_MEMWAIT_Pos (8U)
8034 #define FMC_PMEM_MEMWAIT_Msk (0xFFU << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
8035 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
8036 #define FMC_PMEM_MEMWAIT_0 (0x01U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
8037 #define FMC_PMEM_MEMWAIT_1 (0x02U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
8038 #define FMC_PMEM_MEMWAIT_2 (0x04U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
8039 #define FMC_PMEM_MEMWAIT_3 (0x08U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
8040 #define FMC_PMEM_MEMWAIT_4 (0x10U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
8041 #define FMC_PMEM_MEMWAIT_5 (0x20U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
8042 #define FMC_PMEM_MEMWAIT_6 (0x40U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
8043 #define FMC_PMEM_MEMWAIT_7 (0x80U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
8044
8045 #define FMC_PMEM_MEMHOLD_Pos (16U)
8046 #define FMC_PMEM_MEMHOLD_Msk (0xFFU << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
8047 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
8048 #define FMC_PMEM_MEMHOLD_0 (0x01U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
8049 #define FMC_PMEM_MEMHOLD_1 (0x02U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
8050 #define FMC_PMEM_MEMHOLD_2 (0x04U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
8051 #define FMC_PMEM_MEMHOLD_3 (0x08U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
8052 #define FMC_PMEM_MEMHOLD_4 (0x10U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
8053 #define FMC_PMEM_MEMHOLD_5 (0x20U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
8054 #define FMC_PMEM_MEMHOLD_6 (0x40U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
8055 #define FMC_PMEM_MEMHOLD_7 (0x80U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
8056
8057 #define FMC_PMEM_MEMHIZ_Pos (24U)
8058 #define FMC_PMEM_MEMHIZ_Msk (0xFFU << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
8059 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
8060 #define FMC_PMEM_MEMHIZ_0 (0x01U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
8061 #define FMC_PMEM_MEMHIZ_1 (0x02U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
8062 #define FMC_PMEM_MEMHIZ_2 (0x04U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
8063 #define FMC_PMEM_MEMHIZ_3 (0x08U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
8064 #define FMC_PMEM_MEMHIZ_4 (0x10U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
8065 #define FMC_PMEM_MEMHIZ_5 (0x20U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
8066 #define FMC_PMEM_MEMHIZ_6 (0x40U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
8067 #define FMC_PMEM_MEMHIZ_7 (0x80U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
8068
8069 /****************** Bit definition for FMC_PATT register *******************/
8070 #define FMC_PATT_ATTSET_Pos (0U)
8071 #define FMC_PATT_ATTSET_Msk (0xFFU << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
8072 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
8073 #define FMC_PATT_ATTSET_0 (0x01U << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
8074 #define FMC_PATT_ATTSET_1 (0x02U << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
8075 #define FMC_PATT_ATTSET_2 (0x04U << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
8076 #define FMC_PATT_ATTSET_3 (0x08U << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
8077 #define FMC_PATT_ATTSET_4 (0x10U << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
8078 #define FMC_PATT_ATTSET_5 (0x20U << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
8079 #define FMC_PATT_ATTSET_6 (0x40U << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
8080 #define FMC_PATT_ATTSET_7 (0x80U << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
8081
8082 #define FMC_PATT_ATTWAIT_Pos (8U)
8083 #define FMC_PATT_ATTWAIT_Msk (0xFFU << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
8084 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
8085 #define FMC_PATT_ATTWAIT_0 (0x01U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
8086 #define FMC_PATT_ATTWAIT_1 (0x02U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
8087 #define FMC_PATT_ATTWAIT_2 (0x04U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
8088 #define FMC_PATT_ATTWAIT_3 (0x08U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
8089 #define FMC_PATT_ATTWAIT_4 (0x10U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
8090 #define FMC_PATT_ATTWAIT_5 (0x20U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
8091 #define FMC_PATT_ATTWAIT_6 (0x40U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
8092 #define FMC_PATT_ATTWAIT_7 (0x80U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
8093
8094 #define FMC_PATT_ATTHOLD_Pos (16U)
8095 #define FMC_PATT_ATTHOLD_Msk (0xFFU << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
8096 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
8097 #define FMC_PATT_ATTHOLD_0 (0x01U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
8098 #define FMC_PATT_ATTHOLD_1 (0x02U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
8099 #define FMC_PATT_ATTHOLD_2 (0x04U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
8100 #define FMC_PATT_ATTHOLD_3 (0x08U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
8101 #define FMC_PATT_ATTHOLD_4 (0x10U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
8102 #define FMC_PATT_ATTHOLD_5 (0x20U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
8103 #define FMC_PATT_ATTHOLD_6 (0x40U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
8104 #define FMC_PATT_ATTHOLD_7 (0x80U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
8105
8106 #define FMC_PATT_ATTHIZ_Pos (24U)
8107 #define FMC_PATT_ATTHIZ_Msk (0xFFU << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
8108 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
8109 #define FMC_PATT_ATTHIZ_0 (0x01U << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
8110 #define FMC_PATT_ATTHIZ_1 (0x02U << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
8111 #define FMC_PATT_ATTHIZ_2 (0x04U << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
8112 #define FMC_PATT_ATTHIZ_3 (0x08U << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
8113 #define FMC_PATT_ATTHIZ_4 (0x10U << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
8114 #define FMC_PATT_ATTHIZ_5 (0x20U << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
8115 #define FMC_PATT_ATTHIZ_6 (0x40U << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
8116 #define FMC_PATT_ATTHIZ_7 (0x80U << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
8117
8118 /****************** Bit definition for FMC_ECCR register *******************/
8119 #define FMC_ECCR_ECC_Pos (0U)
8120 #define FMC_ECCR_ECC_Msk (0xFFFFFFFFU << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
8121 #define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
8122
8123 /******************************************************************************/
8124 /* */
8125 /* General Purpose IOs (GPIO) */
8126 /* */
8127 /******************************************************************************/
8128 /****************** Bits definition for GPIO_MODER register *****************/
8129 #define GPIO_MODER_MODE0_Pos (0U)
8130 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
8131 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
8132 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
8133 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
8134 #define GPIO_MODER_MODE1_Pos (2U)
8135 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
8136 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
8137 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
8138 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
8139 #define GPIO_MODER_MODE2_Pos (4U)
8140 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
8141 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
8142 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
8143 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
8144 #define GPIO_MODER_MODE3_Pos (6U)
8145 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
8146 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
8147 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
8148 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
8149 #define GPIO_MODER_MODE4_Pos (8U)
8150 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
8151 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
8152 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
8153 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
8154 #define GPIO_MODER_MODE5_Pos (10U)
8155 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
8156 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
8157 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
8158 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
8159 #define GPIO_MODER_MODE6_Pos (12U)
8160 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
8161 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
8162 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
8163 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
8164 #define GPIO_MODER_MODE7_Pos (14U)
8165 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
8166 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
8167 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
8168 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
8169 #define GPIO_MODER_MODE8_Pos (16U)
8170 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
8171 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
8172 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
8173 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
8174 #define GPIO_MODER_MODE9_Pos (18U)
8175 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
8176 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
8177 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
8178 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
8179 #define GPIO_MODER_MODE10_Pos (20U)
8180 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
8181 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
8182 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
8183 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
8184 #define GPIO_MODER_MODE11_Pos (22U)
8185 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
8186 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
8187 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
8188 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
8189 #define GPIO_MODER_MODE12_Pos (24U)
8190 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
8191 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
8192 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
8193 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
8194 #define GPIO_MODER_MODE13_Pos (26U)
8195 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
8196 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
8197 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
8198 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
8199 #define GPIO_MODER_MODE14_Pos (28U)
8200 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
8201 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8202 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
8203 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
8204 #define GPIO_MODER_MODE15_Pos (30U)
8205 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
8206 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8207 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
8208 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
8209
8210 /* Legacy defines */
8211 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
8212 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
8213 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
8214 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
8215 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
8216 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
8217 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
8218 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
8219 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
8220 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
8221 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
8222 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
8223 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
8224 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
8225 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
8226 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
8227 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
8228 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
8229 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
8230 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
8231 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
8232 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
8233 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
8234 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
8235 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
8236 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
8237 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
8238 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
8239 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
8240 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
8241 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
8242 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
8243 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
8244 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
8245 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
8246 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
8247 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
8248 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
8249 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
8250 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
8251 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
8252 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
8253 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
8254 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
8255 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
8256 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
8257 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
8258 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
8259
8260 /****************** Bits definition for GPIO_OTYPER register ****************/
8261 #define GPIO_OTYPER_OT0_Pos (0U)
8262 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
8263 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8264 #define GPIO_OTYPER_OT1_Pos (1U)
8265 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
8266 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8267 #define GPIO_OTYPER_OT2_Pos (2U)
8268 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
8269 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8270 #define GPIO_OTYPER_OT3_Pos (3U)
8271 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
8272 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8273 #define GPIO_OTYPER_OT4_Pos (4U)
8274 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
8275 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8276 #define GPIO_OTYPER_OT5_Pos (5U)
8277 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
8278 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8279 #define GPIO_OTYPER_OT6_Pos (6U)
8280 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
8281 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8282 #define GPIO_OTYPER_OT7_Pos (7U)
8283 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
8284 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8285 #define GPIO_OTYPER_OT8_Pos (8U)
8286 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
8287 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8288 #define GPIO_OTYPER_OT9_Pos (9U)
8289 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
8290 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8291 #define GPIO_OTYPER_OT10_Pos (10U)
8292 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
8293 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8294 #define GPIO_OTYPER_OT11_Pos (11U)
8295 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
8296 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8297 #define GPIO_OTYPER_OT12_Pos (12U)
8298 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
8299 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8300 #define GPIO_OTYPER_OT13_Pos (13U)
8301 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
8302 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8303 #define GPIO_OTYPER_OT14_Pos (14U)
8304 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
8305 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8306 #define GPIO_OTYPER_OT15_Pos (15U)
8307 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
8308 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8309
8310 /* Legacy defines */
8311 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8312 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8313 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8314 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8315 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8316 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8317 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8318 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8319 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8320 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8321 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8322 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8323 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8324 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8325 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8326 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8327
8328 /****************** Bits definition for GPIO_OSPEEDR register ***************/
8329 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8330 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
8331 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8332 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
8333 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
8334 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8335 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
8336 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8337 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
8338 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
8339 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8340 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
8341 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8342 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
8343 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
8344 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8345 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
8346 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8347 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
8348 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
8349 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8350 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
8351 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8352 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
8353 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
8354 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8355 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
8356 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8357 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
8358 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
8359 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8360 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
8361 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8362 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
8363 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
8364 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8365 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
8366 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8367 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
8368 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
8369 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8370 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
8371 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8372 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
8373 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
8374 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8375 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
8376 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8377 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
8378 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
8379 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8380 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
8381 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8382 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
8383 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
8384 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8385 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
8386 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8387 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
8388 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
8389 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8390 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
8391 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8392 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
8393 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
8394 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8395 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
8396 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8397 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
8398 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
8399 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8400 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
8401 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8402 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
8403 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
8404 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8405 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
8406 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8407 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
8408 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
8409
8410 /* Legacy defines */
8411 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8412 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8413 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8414 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8415 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8416 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8417 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8418 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8419 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8420 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8421 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8422 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8423 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8424 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8425 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8426 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8427 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8428 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8429 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8430 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8431 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8432 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8433 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8434 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8435 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8436 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8437 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8438 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8439 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8440 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8441 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8442 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8443 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8444 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8445 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8446 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8447 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8448 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8449 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8450 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8451 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8452 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8453 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8454 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8455 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8456 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8457 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8458 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8459
8460 /****************** Bits definition for GPIO_PUPDR register *****************/
8461 #define GPIO_PUPDR_PUPD0_Pos (0U)
8462 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
8463 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8464 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
8465 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
8466 #define GPIO_PUPDR_PUPD1_Pos (2U)
8467 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
8468 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8469 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
8470 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
8471 #define GPIO_PUPDR_PUPD2_Pos (4U)
8472 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
8473 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8474 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
8475 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
8476 #define GPIO_PUPDR_PUPD3_Pos (6U)
8477 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
8478 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8479 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
8480 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
8481 #define GPIO_PUPDR_PUPD4_Pos (8U)
8482 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
8483 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8484 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
8485 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
8486 #define GPIO_PUPDR_PUPD5_Pos (10U)
8487 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
8488 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8489 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
8490 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
8491 #define GPIO_PUPDR_PUPD6_Pos (12U)
8492 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
8493 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8494 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
8495 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
8496 #define GPIO_PUPDR_PUPD7_Pos (14U)
8497 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
8498 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8499 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
8500 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
8501 #define GPIO_PUPDR_PUPD8_Pos (16U)
8502 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
8503 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8504 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
8505 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
8506 #define GPIO_PUPDR_PUPD9_Pos (18U)
8507 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
8508 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8509 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
8510 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
8511 #define GPIO_PUPDR_PUPD10_Pos (20U)
8512 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
8513 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8514 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
8515 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
8516 #define GPIO_PUPDR_PUPD11_Pos (22U)
8517 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
8518 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8519 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
8520 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
8521 #define GPIO_PUPDR_PUPD12_Pos (24U)
8522 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
8523 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8524 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
8525 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
8526 #define GPIO_PUPDR_PUPD13_Pos (26U)
8527 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
8528 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8529 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
8530 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
8531 #define GPIO_PUPDR_PUPD14_Pos (28U)
8532 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
8533 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8534 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
8535 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
8536 #define GPIO_PUPDR_PUPD15_Pos (30U)
8537 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
8538 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8539 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
8540 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
8541
8542 /* Legacy defines */
8543 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8544 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8545 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8546 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8547 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8548 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8549 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8550 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8551 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8552 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8553 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8554 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8555 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8556 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8557 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8558 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8559 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8560 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8561 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8562 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8563 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8564 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8565 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8566 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8567 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8568 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8569 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8570 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8571 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8572 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8573 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8574 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8575 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8576 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8577 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8578 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8579 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8580 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8581 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8582 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8583 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8584 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8585 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8586 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8587 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8588 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8589 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8590 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8591
8592 /****************** Bits definition for GPIO_IDR register *******************/
8593 #define GPIO_IDR_ID0_Pos (0U)
8594 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
8595 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8596 #define GPIO_IDR_ID1_Pos (1U)
8597 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
8598 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8599 #define GPIO_IDR_ID2_Pos (2U)
8600 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
8601 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8602 #define GPIO_IDR_ID3_Pos (3U)
8603 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
8604 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8605 #define GPIO_IDR_ID4_Pos (4U)
8606 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
8607 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8608 #define GPIO_IDR_ID5_Pos (5U)
8609 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
8610 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8611 #define GPIO_IDR_ID6_Pos (6U)
8612 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
8613 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8614 #define GPIO_IDR_ID7_Pos (7U)
8615 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
8616 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8617 #define GPIO_IDR_ID8_Pos (8U)
8618 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
8619 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8620 #define GPIO_IDR_ID9_Pos (9U)
8621 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
8622 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8623 #define GPIO_IDR_ID10_Pos (10U)
8624 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
8625 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8626 #define GPIO_IDR_ID11_Pos (11U)
8627 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
8628 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8629 #define GPIO_IDR_ID12_Pos (12U)
8630 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
8631 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8632 #define GPIO_IDR_ID13_Pos (13U)
8633 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
8634 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8635 #define GPIO_IDR_ID14_Pos (14U)
8636 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
8637 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8638 #define GPIO_IDR_ID15_Pos (15U)
8639 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
8640 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8641
8642 /* Legacy defines */
8643 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8644 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8645 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8646 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8647 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8648 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8649 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8650 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8651 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8652 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8653 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8654 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8655 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8656 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8657 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8658 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8659
8660 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
8661 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
8662 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
8663 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
8664 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
8665 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
8666 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
8667 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
8668 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
8669 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
8670 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
8671 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
8672 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
8673 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
8674 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
8675 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
8676 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
8677
8678 /****************** Bits definition for GPIO_ODR register *******************/
8679 #define GPIO_ODR_OD0_Pos (0U)
8680 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
8681 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8682 #define GPIO_ODR_OD1_Pos (1U)
8683 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
8684 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8685 #define GPIO_ODR_OD2_Pos (2U)
8686 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
8687 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8688 #define GPIO_ODR_OD3_Pos (3U)
8689 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
8690 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8691 #define GPIO_ODR_OD4_Pos (4U)
8692 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
8693 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8694 #define GPIO_ODR_OD5_Pos (5U)
8695 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
8696 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8697 #define GPIO_ODR_OD6_Pos (6U)
8698 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
8699 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8700 #define GPIO_ODR_OD7_Pos (7U)
8701 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
8702 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8703 #define GPIO_ODR_OD8_Pos (8U)
8704 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
8705 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8706 #define GPIO_ODR_OD9_Pos (9U)
8707 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
8708 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8709 #define GPIO_ODR_OD10_Pos (10U)
8710 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
8711 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8712 #define GPIO_ODR_OD11_Pos (11U)
8713 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
8714 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8715 #define GPIO_ODR_OD12_Pos (12U)
8716 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
8717 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8718 #define GPIO_ODR_OD13_Pos (13U)
8719 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
8720 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8721 #define GPIO_ODR_OD14_Pos (14U)
8722 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
8723 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8724 #define GPIO_ODR_OD15_Pos (15U)
8725 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
8726 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8727
8728 /* Legacy defines */
8729 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8730 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8731 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8732 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8733 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8734 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8735 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8736 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8737 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8738 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8739 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8740 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8741 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8742 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8743 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8744 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8745
8746 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
8747 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
8748 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
8749 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
8750 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
8751 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
8752 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
8753 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
8754 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
8755 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
8756 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
8757 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
8758 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
8759 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
8760 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
8761 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
8762 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
8763
8764 /****************** Bits definition for GPIO_BSRR register ******************/
8765 #define GPIO_BSRR_BS0_Pos (0U)
8766 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
8767 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8768 #define GPIO_BSRR_BS1_Pos (1U)
8769 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
8770 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8771 #define GPIO_BSRR_BS2_Pos (2U)
8772 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
8773 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8774 #define GPIO_BSRR_BS3_Pos (3U)
8775 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
8776 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8777 #define GPIO_BSRR_BS4_Pos (4U)
8778 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
8779 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8780 #define GPIO_BSRR_BS5_Pos (5U)
8781 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
8782 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8783 #define GPIO_BSRR_BS6_Pos (6U)
8784 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
8785 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8786 #define GPIO_BSRR_BS7_Pos (7U)
8787 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
8788 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8789 #define GPIO_BSRR_BS8_Pos (8U)
8790 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
8791 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8792 #define GPIO_BSRR_BS9_Pos (9U)
8793 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
8794 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8795 #define GPIO_BSRR_BS10_Pos (10U)
8796 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
8797 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8798 #define GPIO_BSRR_BS11_Pos (11U)
8799 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
8800 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8801 #define GPIO_BSRR_BS12_Pos (12U)
8802 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
8803 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8804 #define GPIO_BSRR_BS13_Pos (13U)
8805 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
8806 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8807 #define GPIO_BSRR_BS14_Pos (14U)
8808 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
8809 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8810 #define GPIO_BSRR_BS15_Pos (15U)
8811 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
8812 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8813 #define GPIO_BSRR_BR0_Pos (16U)
8814 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
8815 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8816 #define GPIO_BSRR_BR1_Pos (17U)
8817 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
8818 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8819 #define GPIO_BSRR_BR2_Pos (18U)
8820 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
8821 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8822 #define GPIO_BSRR_BR3_Pos (19U)
8823 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
8824 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8825 #define GPIO_BSRR_BR4_Pos (20U)
8826 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
8827 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8828 #define GPIO_BSRR_BR5_Pos (21U)
8829 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
8830 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8831 #define GPIO_BSRR_BR6_Pos (22U)
8832 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
8833 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8834 #define GPIO_BSRR_BR7_Pos (23U)
8835 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
8836 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8837 #define GPIO_BSRR_BR8_Pos (24U)
8838 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
8839 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8840 #define GPIO_BSRR_BR9_Pos (25U)
8841 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
8842 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8843 #define GPIO_BSRR_BR10_Pos (26U)
8844 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
8845 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8846 #define GPIO_BSRR_BR11_Pos (27U)
8847 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
8848 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8849 #define GPIO_BSRR_BR12_Pos (28U)
8850 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
8851 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8852 #define GPIO_BSRR_BR13_Pos (29U)
8853 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
8854 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8855 #define GPIO_BSRR_BR14_Pos (30U)
8856 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
8857 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8858 #define GPIO_BSRR_BR15_Pos (31U)
8859 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
8860 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8861
8862 /* Legacy defines */
8863 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8864 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8865 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8866 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8867 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8868 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8869 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8870 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8871 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8872 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8873 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8874 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8875 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8876 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8877 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8878 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8879 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8880 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8881 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8882 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8883 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8884 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8885 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8886 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8887 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8888 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8889 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8890 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8891 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8892 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8893 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8894 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8895
8896 /****************** Bit definition for GPIO_LCKR register *********************/
8897 #define GPIO_LCKR_LCK0_Pos (0U)
8898 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
8899 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8900 #define GPIO_LCKR_LCK1_Pos (1U)
8901 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
8902 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8903 #define GPIO_LCKR_LCK2_Pos (2U)
8904 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
8905 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8906 #define GPIO_LCKR_LCK3_Pos (3U)
8907 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
8908 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8909 #define GPIO_LCKR_LCK4_Pos (4U)
8910 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
8911 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8912 #define GPIO_LCKR_LCK5_Pos (5U)
8913 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
8914 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8915 #define GPIO_LCKR_LCK6_Pos (6U)
8916 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
8917 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8918 #define GPIO_LCKR_LCK7_Pos (7U)
8919 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
8920 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8921 #define GPIO_LCKR_LCK8_Pos (8U)
8922 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
8923 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8924 #define GPIO_LCKR_LCK9_Pos (9U)
8925 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
8926 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8927 #define GPIO_LCKR_LCK10_Pos (10U)
8928 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
8929 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8930 #define GPIO_LCKR_LCK11_Pos (11U)
8931 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
8932 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8933 #define GPIO_LCKR_LCK12_Pos (12U)
8934 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
8935 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8936 #define GPIO_LCKR_LCK13_Pos (13U)
8937 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
8938 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8939 #define GPIO_LCKR_LCK14_Pos (14U)
8940 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
8941 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8942 #define GPIO_LCKR_LCK15_Pos (15U)
8943 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
8944 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8945 #define GPIO_LCKR_LCKK_Pos (16U)
8946 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
8947 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8948
8949 /****************** Bit definition for GPIO_AFRL register *********************/
8950 #define GPIO_AFRL_AFSEL0_Pos (0U)
8951 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
8952 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8953 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
8954 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
8955 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
8956 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
8957 #define GPIO_AFRL_AFSEL1_Pos (4U)
8958 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
8959 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8960 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
8961 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
8962 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
8963 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
8964 #define GPIO_AFRL_AFSEL2_Pos (8U)
8965 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
8966 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8967 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
8968 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
8969 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
8970 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
8971 #define GPIO_AFRL_AFSEL3_Pos (12U)
8972 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
8973 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8974 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
8975 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
8976 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
8977 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
8978 #define GPIO_AFRL_AFSEL4_Pos (16U)
8979 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
8980 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8981 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
8982 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
8983 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
8984 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
8985 #define GPIO_AFRL_AFSEL5_Pos (20U)
8986 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
8987 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8988 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
8989 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
8990 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
8991 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
8992 #define GPIO_AFRL_AFSEL6_Pos (24U)
8993 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
8994 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8995 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
8996 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
8997 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
8998 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
8999 #define GPIO_AFRL_AFSEL7_Pos (28U)
9000 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
9001 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
9002 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
9003 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
9004 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
9005 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
9006
9007 /* Legacy defines */
9008 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
9009 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
9010 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
9011 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
9012 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
9013 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
9014 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
9015 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9016
9017 /****************** Bit definition for GPIO_AFRH register *********************/
9018 #define GPIO_AFRH_AFSEL8_Pos (0U)
9019 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
9020 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9021 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
9022 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
9023 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
9024 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
9025 #define GPIO_AFRH_AFSEL9_Pos (4U)
9026 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
9027 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9028 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
9029 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
9030 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
9031 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
9032 #define GPIO_AFRH_AFSEL10_Pos (8U)
9033 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
9034 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9035 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
9036 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
9037 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
9038 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
9039 #define GPIO_AFRH_AFSEL11_Pos (12U)
9040 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
9041 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9042 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
9043 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
9044 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
9045 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
9046 #define GPIO_AFRH_AFSEL12_Pos (16U)
9047 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
9048 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9049 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
9050 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
9051 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
9052 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
9053 #define GPIO_AFRH_AFSEL13_Pos (20U)
9054 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
9055 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9056 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
9057 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
9058 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
9059 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
9060 #define GPIO_AFRH_AFSEL14_Pos (24U)
9061 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
9062 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9063 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
9064 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
9065 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
9066 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
9067 #define GPIO_AFRH_AFSEL15_Pos (28U)
9068 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
9069 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9070 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
9071 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
9072 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
9073 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
9074
9075 /* Legacy defines */
9076 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9077 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9078 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9079 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9080 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9081 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9082 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9083 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9084
9085 /****************** Bits definition for GPIO_BRR register ******************/
9086 #define GPIO_BRR_BR0_Pos (0U)
9087 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
9088 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
9089 #define GPIO_BRR_BR1_Pos (1U)
9090 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
9091 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
9092 #define GPIO_BRR_BR2_Pos (2U)
9093 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
9094 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
9095 #define GPIO_BRR_BR3_Pos (3U)
9096 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
9097 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
9098 #define GPIO_BRR_BR4_Pos (4U)
9099 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
9100 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
9101 #define GPIO_BRR_BR5_Pos (5U)
9102 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
9103 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
9104 #define GPIO_BRR_BR6_Pos (6U)
9105 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
9106 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
9107 #define GPIO_BRR_BR7_Pos (7U)
9108 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
9109 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
9110 #define GPIO_BRR_BR8_Pos (8U)
9111 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
9112 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
9113 #define GPIO_BRR_BR9_Pos (9U)
9114 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
9115 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
9116 #define GPIO_BRR_BR10_Pos (10U)
9117 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
9118 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
9119 #define GPIO_BRR_BR11_Pos (11U)
9120 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
9121 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
9122 #define GPIO_BRR_BR12_Pos (12U)
9123 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
9124 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
9125 #define GPIO_BRR_BR13_Pos (13U)
9126 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
9127 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
9128 #define GPIO_BRR_BR14_Pos (14U)
9129 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
9130 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
9131 #define GPIO_BRR_BR15_Pos (15U)
9132 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
9133 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
9134
9135 /* Legacy defines */
9136 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
9137 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
9138 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
9139 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
9140 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
9141 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
9142 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
9143 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
9144 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
9145 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
9146 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
9147 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
9148 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
9149 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
9150 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
9151 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
9152
9153
9154 /****************** Bits definition for GPIO_ASCR register *******************/
9155 #define GPIO_ASCR_ASC0_Pos (0U)
9156 #define GPIO_ASCR_ASC0_Msk (0x1U << GPIO_ASCR_ASC0_Pos) /*!< 0x00000001 */
9157 #define GPIO_ASCR_ASC0 GPIO_ASCR_ASC0_Msk
9158 #define GPIO_ASCR_ASC1_Pos (1U)
9159 #define GPIO_ASCR_ASC1_Msk (0x1U << GPIO_ASCR_ASC1_Pos) /*!< 0x00000002 */
9160 #define GPIO_ASCR_ASC1 GPIO_ASCR_ASC1_Msk
9161 #define GPIO_ASCR_ASC2_Pos (2U)
9162 #define GPIO_ASCR_ASC2_Msk (0x1U << GPIO_ASCR_ASC2_Pos) /*!< 0x00000004 */
9163 #define GPIO_ASCR_ASC2 GPIO_ASCR_ASC2_Msk
9164 #define GPIO_ASCR_ASC3_Pos (3U)
9165 #define GPIO_ASCR_ASC3_Msk (0x1U << GPIO_ASCR_ASC3_Pos) /*!< 0x00000008 */
9166 #define GPIO_ASCR_ASC3 GPIO_ASCR_ASC3_Msk
9167 #define GPIO_ASCR_ASC4_Pos (4U)
9168 #define GPIO_ASCR_ASC4_Msk (0x1U << GPIO_ASCR_ASC4_Pos) /*!< 0x00000010 */
9169 #define GPIO_ASCR_ASC4 GPIO_ASCR_ASC4_Msk
9170 #define GPIO_ASCR_ASC5_Pos (5U)
9171 #define GPIO_ASCR_ASC5_Msk (0x1U << GPIO_ASCR_ASC5_Pos) /*!< 0x00000020 */
9172 #define GPIO_ASCR_ASC5 GPIO_ASCR_ASC5_Msk
9173 #define GPIO_ASCR_ASC6_Pos (6U)
9174 #define GPIO_ASCR_ASC6_Msk (0x1U << GPIO_ASCR_ASC6_Pos) /*!< 0x00000040 */
9175 #define GPIO_ASCR_ASC6 GPIO_ASCR_ASC6_Msk
9176 #define GPIO_ASCR_ASC7_Pos (7U)
9177 #define GPIO_ASCR_ASC7_Msk (0x1U << GPIO_ASCR_ASC7_Pos) /*!< 0x00000080 */
9178 #define GPIO_ASCR_ASC7 GPIO_ASCR_ASC7_Msk
9179 #define GPIO_ASCR_ASC8_Pos (8U)
9180 #define GPIO_ASCR_ASC8_Msk (0x1U << GPIO_ASCR_ASC8_Pos) /*!< 0x00000100 */
9181 #define GPIO_ASCR_ASC8 GPIO_ASCR_ASC8_Msk
9182 #define GPIO_ASCR_ASC9_Pos (9U)
9183 #define GPIO_ASCR_ASC9_Msk (0x1U << GPIO_ASCR_ASC9_Pos) /*!< 0x00000200 */
9184 #define GPIO_ASCR_ASC9 GPIO_ASCR_ASC9_Msk
9185 #define GPIO_ASCR_ASC10_Pos (10U)
9186 #define GPIO_ASCR_ASC10_Msk (0x1U << GPIO_ASCR_ASC10_Pos) /*!< 0x00000400 */
9187 #define GPIO_ASCR_ASC10 GPIO_ASCR_ASC10_Msk
9188 #define GPIO_ASCR_ASC11_Pos (11U)
9189 #define GPIO_ASCR_ASC11_Msk (0x1U << GPIO_ASCR_ASC11_Pos) /*!< 0x00000800 */
9190 #define GPIO_ASCR_ASC11 GPIO_ASCR_ASC11_Msk
9191 #define GPIO_ASCR_ASC12_Pos (12U)
9192 #define GPIO_ASCR_ASC12_Msk (0x1U << GPIO_ASCR_ASC12_Pos) /*!< 0x00001000 */
9193 #define GPIO_ASCR_ASC12 GPIO_ASCR_ASC12_Msk
9194 #define GPIO_ASCR_ASC13_Pos (13U)
9195 #define GPIO_ASCR_ASC13_Msk (0x1U << GPIO_ASCR_ASC13_Pos) /*!< 0x00002000 */
9196 #define GPIO_ASCR_ASC13 GPIO_ASCR_ASC13_Msk
9197 #define GPIO_ASCR_ASC14_Pos (14U)
9198 #define GPIO_ASCR_ASC14_Msk (0x1U << GPIO_ASCR_ASC14_Pos) /*!< 0x00004000 */
9199 #define GPIO_ASCR_ASC14 GPIO_ASCR_ASC14_Msk
9200 #define GPIO_ASCR_ASC15_Pos (15U)
9201 #define GPIO_ASCR_ASC15_Msk (0x1U << GPIO_ASCR_ASC15_Pos) /*!< 0x00008000 */
9202 #define GPIO_ASCR_ASC15 GPIO_ASCR_ASC15_Msk
9203
9204 /* Legacy defines */
9205 #define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
9206 #define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
9207 #define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
9208 #define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
9209 #define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
9210 #define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
9211 #define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
9212 #define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
9213 #define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
9214 #define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
9215 #define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
9216 #define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
9217 #define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
9218 #define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
9219 #define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
9220 #define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
9221
9222 /******************************************************************************/
9223 /* */
9224 /* Inter-integrated Circuit Interface (I2C) */
9225 /* */
9226 /******************************************************************************/
9227 /******************* Bit definition for I2C_CR1 register *******************/
9228 #define I2C_CR1_PE_Pos (0U)
9229 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
9230 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
9231 #define I2C_CR1_TXIE_Pos (1U)
9232 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
9233 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
9234 #define I2C_CR1_RXIE_Pos (2U)
9235 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
9236 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
9237 #define I2C_CR1_ADDRIE_Pos (3U)
9238 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
9239 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
9240 #define I2C_CR1_NACKIE_Pos (4U)
9241 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
9242 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
9243 #define I2C_CR1_STOPIE_Pos (5U)
9244 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
9245 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
9246 #define I2C_CR1_TCIE_Pos (6U)
9247 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
9248 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
9249 #define I2C_CR1_ERRIE_Pos (7U)
9250 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
9251 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
9252 #define I2C_CR1_DNF_Pos (8U)
9253 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
9254 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
9255 #define I2C_CR1_ANFOFF_Pos (12U)
9256 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
9257 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
9258 #define I2C_CR1_SWRST_Pos (13U)
9259 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
9260 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
9261 #define I2C_CR1_TXDMAEN_Pos (14U)
9262 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
9263 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
9264 #define I2C_CR1_RXDMAEN_Pos (15U)
9265 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
9266 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
9267 #define I2C_CR1_SBC_Pos (16U)
9268 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
9269 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
9270 #define I2C_CR1_NOSTRETCH_Pos (17U)
9271 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
9272 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
9273 #define I2C_CR1_WUPEN_Pos (18U)
9274 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
9275 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
9276 #define I2C_CR1_GCEN_Pos (19U)
9277 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
9278 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
9279 #define I2C_CR1_SMBHEN_Pos (20U)
9280 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
9281 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
9282 #define I2C_CR1_SMBDEN_Pos (21U)
9283 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
9284 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
9285 #define I2C_CR1_ALERTEN_Pos (22U)
9286 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
9287 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
9288 #define I2C_CR1_PECEN_Pos (23U)
9289 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
9290 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
9291
9292 /****************** Bit definition for I2C_CR2 register ********************/
9293 #define I2C_CR2_SADD_Pos (0U)
9294 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
9295 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
9296 #define I2C_CR2_RD_WRN_Pos (10U)
9297 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
9298 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
9299 #define I2C_CR2_ADD10_Pos (11U)
9300 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
9301 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
9302 #define I2C_CR2_HEAD10R_Pos (12U)
9303 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
9304 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
9305 #define I2C_CR2_START_Pos (13U)
9306 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
9307 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
9308 #define I2C_CR2_STOP_Pos (14U)
9309 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
9310 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
9311 #define I2C_CR2_NACK_Pos (15U)
9312 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
9313 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
9314 #define I2C_CR2_NBYTES_Pos (16U)
9315 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
9316 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
9317 #define I2C_CR2_RELOAD_Pos (24U)
9318 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
9319 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
9320 #define I2C_CR2_AUTOEND_Pos (25U)
9321 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
9322 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
9323 #define I2C_CR2_PECBYTE_Pos (26U)
9324 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
9325 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
9326
9327 /******************* Bit definition for I2C_OAR1 register ******************/
9328 #define I2C_OAR1_OA1_Pos (0U)
9329 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
9330 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
9331 #define I2C_OAR1_OA1MODE_Pos (10U)
9332 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
9333 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
9334 #define I2C_OAR1_OA1EN_Pos (15U)
9335 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
9336 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
9337
9338 /******************* Bit definition for I2C_OAR2 register ******************/
9339 #define I2C_OAR2_OA2_Pos (1U)
9340 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
9341 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
9342 #define I2C_OAR2_OA2MSK_Pos (8U)
9343 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
9344 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
9345 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
9346 #define I2C_OAR2_OA2MASK01_Pos (8U)
9347 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
9348 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
9349 #define I2C_OAR2_OA2MASK02_Pos (9U)
9350 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
9351 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
9352 #define I2C_OAR2_OA2MASK03_Pos (8U)
9353 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
9354 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
9355 #define I2C_OAR2_OA2MASK04_Pos (10U)
9356 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
9357 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
9358 #define I2C_OAR2_OA2MASK05_Pos (8U)
9359 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
9360 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
9361 #define I2C_OAR2_OA2MASK06_Pos (9U)
9362 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
9363 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
9364 #define I2C_OAR2_OA2MASK07_Pos (8U)
9365 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
9366 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
9367 #define I2C_OAR2_OA2EN_Pos (15U)
9368 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
9369 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
9370
9371 /******************* Bit definition for I2C_TIMINGR register *******************/
9372 #define I2C_TIMINGR_SCLL_Pos (0U)
9373 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
9374 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
9375 #define I2C_TIMINGR_SCLH_Pos (8U)
9376 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
9377 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
9378 #define I2C_TIMINGR_SDADEL_Pos (16U)
9379 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
9380 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
9381 #define I2C_TIMINGR_SCLDEL_Pos (20U)
9382 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
9383 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
9384 #define I2C_TIMINGR_PRESC_Pos (28U)
9385 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
9386 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
9387
9388 /******************* Bit definition for I2C_TIMEOUTR register *******************/
9389 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9390 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
9391 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
9392 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
9393 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
9394 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
9395 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9396 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
9397 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
9398 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9399 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
9400 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
9401 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
9402 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
9403 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
9404
9405 /****************** Bit definition for I2C_ISR register *********************/
9406 #define I2C_ISR_TXE_Pos (0U)
9407 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
9408 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
9409 #define I2C_ISR_TXIS_Pos (1U)
9410 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
9411 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
9412 #define I2C_ISR_RXNE_Pos (2U)
9413 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
9414 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
9415 #define I2C_ISR_ADDR_Pos (3U)
9416 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
9417 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
9418 #define I2C_ISR_NACKF_Pos (4U)
9419 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
9420 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
9421 #define I2C_ISR_STOPF_Pos (5U)
9422 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
9423 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
9424 #define I2C_ISR_TC_Pos (6U)
9425 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
9426 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
9427 #define I2C_ISR_TCR_Pos (7U)
9428 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
9429 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
9430 #define I2C_ISR_BERR_Pos (8U)
9431 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
9432 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
9433 #define I2C_ISR_ARLO_Pos (9U)
9434 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
9435 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
9436 #define I2C_ISR_OVR_Pos (10U)
9437 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
9438 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
9439 #define I2C_ISR_PECERR_Pos (11U)
9440 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
9441 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
9442 #define I2C_ISR_TIMEOUT_Pos (12U)
9443 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
9444 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
9445 #define I2C_ISR_ALERT_Pos (13U)
9446 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
9447 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
9448 #define I2C_ISR_BUSY_Pos (15U)
9449 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
9450 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
9451 #define I2C_ISR_DIR_Pos (16U)
9452 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
9453 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
9454 #define I2C_ISR_ADDCODE_Pos (17U)
9455 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
9456 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
9457
9458 /****************** Bit definition for I2C_ICR register *********************/
9459 #define I2C_ICR_ADDRCF_Pos (3U)
9460 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
9461 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
9462 #define I2C_ICR_NACKCF_Pos (4U)
9463 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
9464 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
9465 #define I2C_ICR_STOPCF_Pos (5U)
9466 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
9467 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
9468 #define I2C_ICR_BERRCF_Pos (8U)
9469 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
9470 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
9471 #define I2C_ICR_ARLOCF_Pos (9U)
9472 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
9473 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
9474 #define I2C_ICR_OVRCF_Pos (10U)
9475 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
9476 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
9477 #define I2C_ICR_PECCF_Pos (11U)
9478 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
9479 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
9480 #define I2C_ICR_TIMOUTCF_Pos (12U)
9481 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
9482 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
9483 #define I2C_ICR_ALERTCF_Pos (13U)
9484 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
9485 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
9486
9487 /****************** Bit definition for I2C_PECR register *********************/
9488 #define I2C_PECR_PEC_Pos (0U)
9489 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
9490 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
9491
9492 /****************** Bit definition for I2C_RXDR register *********************/
9493 #define I2C_RXDR_RXDATA_Pos (0U)
9494 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
9495 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
9496
9497 /****************** Bit definition for I2C_TXDR register *********************/
9498 #define I2C_TXDR_TXDATA_Pos (0U)
9499 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
9500 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
9501
9502 /******************************************************************************/
9503 /* */
9504 /* Independent WATCHDOG */
9505 /* */
9506 /******************************************************************************/
9507 /******************* Bit definition for IWDG_KR register ********************/
9508 #define IWDG_KR_KEY_Pos (0U)
9509 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
9510 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
9511
9512 /******************* Bit definition for IWDG_PR register ********************/
9513 #define IWDG_PR_PR_Pos (0U)
9514 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
9515 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
9516 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
9517 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
9518 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
9519
9520 /******************* Bit definition for IWDG_RLR register *******************/
9521 #define IWDG_RLR_RL_Pos (0U)
9522 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
9523 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
9524
9525 /******************* Bit definition for IWDG_SR register ********************/
9526 #define IWDG_SR_PVU_Pos (0U)
9527 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
9528 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
9529 #define IWDG_SR_RVU_Pos (1U)
9530 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
9531 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
9532 #define IWDG_SR_WVU_Pos (2U)
9533 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
9534 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
9535
9536 /******************* Bit definition for IWDG_KR register ********************/
9537 #define IWDG_WINR_WIN_Pos (0U)
9538 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
9539 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
9540
9541 /******************************************************************************/
9542 /* */
9543 /* Firewall */
9544 /* */
9545 /******************************************************************************/
9546
9547 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
9548 #define FW_CSSA_ADD_Pos (8U)
9549 #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
9550 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
9551 #define FW_CSL_LENG_Pos (8U)
9552 #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
9553 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
9554 #define FW_NVDSSA_ADD_Pos (8U)
9555 #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
9556 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
9557 #define FW_NVDSL_LENG_Pos (8U)
9558 #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
9559 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
9560 #define FW_VDSSA_ADD_Pos (6U)
9561 #define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
9562 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
9563 #define FW_VDSL_LENG_Pos (6U)
9564 #define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
9565 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
9566
9567 /**************************Bit definition for CR register *********************/
9568 #define FW_CR_FPA_Pos (0U)
9569 #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
9570 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
9571 #define FW_CR_VDS_Pos (1U)
9572 #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
9573 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
9574 #define FW_CR_VDE_Pos (2U)
9575 #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
9576 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
9577
9578 /******************************************************************************/
9579 /* */
9580 /* Power Control */
9581 /* */
9582 /******************************************************************************/
9583
9584 /******************** Bit definition for PWR_CR1 register ********************/
9585
9586 #define PWR_CR1_LPR_Pos (14U)
9587 #define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
9588 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
9589 #define PWR_CR1_VOS_Pos (9U)
9590 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
9591 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
9592 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
9593 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
9594 #define PWR_CR1_DBP_Pos (8U)
9595 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
9596 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
9597 #define PWR_CR1_LPMS_Pos (0U)
9598 #define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
9599 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
9600 #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
9601 #define PWR_CR1_LPMS_STOP1_Pos (0U)
9602 #define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
9603 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
9604 #define PWR_CR1_LPMS_STOP2_Pos (1U)
9605 #define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
9606 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
9607 #define PWR_CR1_LPMS_STANDBY_Pos (0U)
9608 #define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
9609 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
9610 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
9611 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
9612 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
9613
9614
9615 /******************** Bit definition for PWR_CR2 register ********************/
9616 #define PWR_CR2_USV_Pos (10U)
9617 #define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
9618 #define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
9619 #define PWR_CR2_IOSV_Pos (9U)
9620 #define PWR_CR2_IOSV_Msk (0x1U << PWR_CR2_IOSV_Pos) /*!< 0x00000200 */
9621 #define PWR_CR2_IOSV PWR_CR2_IOSV_Msk /*!< VDD IO2 independent I/Os Supply Valid */
9622 /*!< PVME Peripheral Voltage Monitor Enable */
9623 #define PWR_CR2_PVME_Pos (4U)
9624 #define PWR_CR2_PVME_Msk (0xFU << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
9625 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
9626 #define PWR_CR2_PVME4_Pos (7U)
9627 #define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
9628 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
9629 #define PWR_CR2_PVME3_Pos (6U)
9630 #define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
9631 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
9632 #define PWR_CR2_PVME2_Pos (5U)
9633 #define PWR_CR2_PVME2_Msk (0x1U << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
9634 #define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
9635 #define PWR_CR2_PVME1_Pos (4U)
9636 #define PWR_CR2_PVME1_Msk (0x1U << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
9637 #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
9638 /*!< PVD level configuration */
9639 #define PWR_CR2_PLS_Pos (1U)
9640 #define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
9641 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
9642 #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
9643 #define PWR_CR2_PLS_LEV1_Pos (1U)
9644 #define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
9645 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
9646 #define PWR_CR2_PLS_LEV2_Pos (2U)
9647 #define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
9648 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
9649 #define PWR_CR2_PLS_LEV3_Pos (1U)
9650 #define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
9651 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
9652 #define PWR_CR2_PLS_LEV4_Pos (3U)
9653 #define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
9654 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
9655 #define PWR_CR2_PLS_LEV5_Pos (1U)
9656 #define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
9657 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
9658 #define PWR_CR2_PLS_LEV6_Pos (2U)
9659 #define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
9660 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
9661 #define PWR_CR2_PLS_LEV7_Pos (1U)
9662 #define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
9663 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
9664 #define PWR_CR2_PVDE_Pos (0U)
9665 #define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
9666 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
9667
9668 /******************** Bit definition for PWR_CR3 register ********************/
9669 #define PWR_CR3_EIWF_Pos (15U)
9670 #define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
9671 #define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
9672 #define PWR_CR3_APC_Pos (10U)
9673 #define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
9674 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
9675 #define PWR_CR3_RRS_Pos (8U)
9676 #define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
9677 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
9678 #define PWR_CR3_EWUP5_Pos (4U)
9679 #define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
9680 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
9681 #define PWR_CR3_EWUP4_Pos (3U)
9682 #define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
9683 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
9684 #define PWR_CR3_EWUP3_Pos (2U)
9685 #define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
9686 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
9687 #define PWR_CR3_EWUP2_Pos (1U)
9688 #define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
9689 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
9690 #define PWR_CR3_EWUP1_Pos (0U)
9691 #define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
9692 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
9693 #define PWR_CR3_EWUP_Pos (0U)
9694 #define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
9695 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
9696
9697 /******************** Bit definition for PWR_CR4 register ********************/
9698 #define PWR_CR4_VBRS_Pos (9U)
9699 #define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
9700 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
9701 #define PWR_CR4_VBE_Pos (8U)
9702 #define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
9703 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
9704 #define PWR_CR4_WP5_Pos (4U)
9705 #define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
9706 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
9707 #define PWR_CR4_WP4_Pos (3U)
9708 #define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
9709 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
9710 #define PWR_CR4_WP3_Pos (2U)
9711 #define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
9712 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
9713 #define PWR_CR4_WP2_Pos (1U)
9714 #define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
9715 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
9716 #define PWR_CR4_WP1_Pos (0U)
9717 #define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
9718 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
9719
9720 /******************** Bit definition for PWR_SR1 register ********************/
9721 #define PWR_SR1_WUFI_Pos (15U)
9722 #define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
9723 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
9724 #define PWR_SR1_SBF_Pos (8U)
9725 #define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
9726 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
9727 #define PWR_SR1_WUF_Pos (0U)
9728 #define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
9729 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
9730 #define PWR_SR1_WUF5_Pos (4U)
9731 #define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
9732 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
9733 #define PWR_SR1_WUF4_Pos (3U)
9734 #define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
9735 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
9736 #define PWR_SR1_WUF3_Pos (2U)
9737 #define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
9738 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
9739 #define PWR_SR1_WUF2_Pos (1U)
9740 #define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
9741 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
9742 #define PWR_SR1_WUF1_Pos (0U)
9743 #define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
9744 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
9745
9746 /******************** Bit definition for PWR_SR2 register ********************/
9747 #define PWR_SR2_PVMO4_Pos (15U)
9748 #define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
9749 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
9750 #define PWR_SR2_PVMO3_Pos (14U)
9751 #define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
9752 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
9753 #define PWR_SR2_PVMO2_Pos (13U)
9754 #define PWR_SR2_PVMO2_Msk (0x1U << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
9755 #define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
9756 #define PWR_SR2_PVMO1_Pos (12U)
9757 #define PWR_SR2_PVMO1_Msk (0x1U << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
9758 #define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
9759 #define PWR_SR2_PVDO_Pos (11U)
9760 #define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
9761 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
9762 #define PWR_SR2_VOSF_Pos (10U)
9763 #define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
9764 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
9765 #define PWR_SR2_REGLPF_Pos (9U)
9766 #define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
9767 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
9768 #define PWR_SR2_REGLPS_Pos (8U)
9769 #define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
9770 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
9771
9772 /******************** Bit definition for PWR_SCR register ********************/
9773 #define PWR_SCR_CSBF_Pos (8U)
9774 #define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
9775 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
9776 #define PWR_SCR_CWUF_Pos (0U)
9777 #define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
9778 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
9779 #define PWR_SCR_CWUF5_Pos (4U)
9780 #define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
9781 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
9782 #define PWR_SCR_CWUF4_Pos (3U)
9783 #define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
9784 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
9785 #define PWR_SCR_CWUF3_Pos (2U)
9786 #define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
9787 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
9788 #define PWR_SCR_CWUF2_Pos (1U)
9789 #define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
9790 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
9791 #define PWR_SCR_CWUF1_Pos (0U)
9792 #define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
9793 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
9794
9795 /******************** Bit definition for PWR_PUCRA register ********************/
9796 #define PWR_PUCRA_PA15_Pos (15U)
9797 #define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
9798 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
9799 #define PWR_PUCRA_PA13_Pos (13U)
9800 #define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
9801 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
9802 #define PWR_PUCRA_PA12_Pos (12U)
9803 #define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
9804 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
9805 #define PWR_PUCRA_PA11_Pos (11U)
9806 #define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
9807 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
9808 #define PWR_PUCRA_PA10_Pos (10U)
9809 #define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
9810 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
9811 #define PWR_PUCRA_PA9_Pos (9U)
9812 #define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
9813 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
9814 #define PWR_PUCRA_PA8_Pos (8U)
9815 #define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
9816 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
9817 #define PWR_PUCRA_PA7_Pos (7U)
9818 #define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
9819 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
9820 #define PWR_PUCRA_PA6_Pos (6U)
9821 #define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
9822 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
9823 #define PWR_PUCRA_PA5_Pos (5U)
9824 #define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
9825 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
9826 #define PWR_PUCRA_PA4_Pos (4U)
9827 #define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
9828 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
9829 #define PWR_PUCRA_PA3_Pos (3U)
9830 #define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
9831 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
9832 #define PWR_PUCRA_PA2_Pos (2U)
9833 #define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
9834 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
9835 #define PWR_PUCRA_PA1_Pos (1U)
9836 #define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
9837 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
9838 #define PWR_PUCRA_PA0_Pos (0U)
9839 #define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
9840 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
9841
9842 /******************** Bit definition for PWR_PDCRA register ********************/
9843 #define PWR_PDCRA_PA14_Pos (14U)
9844 #define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
9845 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
9846 #define PWR_PDCRA_PA12_Pos (12U)
9847 #define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
9848 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
9849 #define PWR_PDCRA_PA11_Pos (11U)
9850 #define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
9851 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
9852 #define PWR_PDCRA_PA10_Pos (10U)
9853 #define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
9854 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
9855 #define PWR_PDCRA_PA9_Pos (9U)
9856 #define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
9857 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
9858 #define PWR_PDCRA_PA8_Pos (8U)
9859 #define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
9860 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
9861 #define PWR_PDCRA_PA7_Pos (7U)
9862 #define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
9863 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
9864 #define PWR_PDCRA_PA6_Pos (6U)
9865 #define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
9866 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
9867 #define PWR_PDCRA_PA5_Pos (5U)
9868 #define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
9869 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
9870 #define PWR_PDCRA_PA4_Pos (4U)
9871 #define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
9872 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
9873 #define PWR_PDCRA_PA3_Pos (3U)
9874 #define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
9875 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
9876 #define PWR_PDCRA_PA2_Pos (2U)
9877 #define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
9878 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
9879 #define PWR_PDCRA_PA1_Pos (1U)
9880 #define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
9881 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
9882 #define PWR_PDCRA_PA0_Pos (0U)
9883 #define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
9884 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
9885
9886 /******************** Bit definition for PWR_PUCRB register ********************/
9887 #define PWR_PUCRB_PB15_Pos (15U)
9888 #define PWR_PUCRB_PB15_Msk (0x1U << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
9889 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
9890 #define PWR_PUCRB_PB14_Pos (14U)
9891 #define PWR_PUCRB_PB14_Msk (0x1U << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
9892 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
9893 #define PWR_PUCRB_PB13_Pos (13U)
9894 #define PWR_PUCRB_PB13_Msk (0x1U << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
9895 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
9896 #define PWR_PUCRB_PB12_Pos (12U)
9897 #define PWR_PUCRB_PB12_Msk (0x1U << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
9898 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
9899 #define PWR_PUCRB_PB11_Pos (11U)
9900 #define PWR_PUCRB_PB11_Msk (0x1U << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
9901 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
9902 #define PWR_PUCRB_PB10_Pos (10U)
9903 #define PWR_PUCRB_PB10_Msk (0x1U << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
9904 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
9905 #define PWR_PUCRB_PB9_Pos (9U)
9906 #define PWR_PUCRB_PB9_Msk (0x1U << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
9907 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
9908 #define PWR_PUCRB_PB8_Pos (8U)
9909 #define PWR_PUCRB_PB8_Msk (0x1U << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
9910 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
9911 #define PWR_PUCRB_PB7_Pos (7U)
9912 #define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
9913 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
9914 #define PWR_PUCRB_PB6_Pos (6U)
9915 #define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
9916 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
9917 #define PWR_PUCRB_PB5_Pos (5U)
9918 #define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
9919 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
9920 #define PWR_PUCRB_PB4_Pos (4U)
9921 #define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
9922 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
9923 #define PWR_PUCRB_PB3_Pos (3U)
9924 #define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
9925 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
9926 #define PWR_PUCRB_PB2_Pos (2U)
9927 #define PWR_PUCRB_PB2_Msk (0x1U << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
9928 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
9929 #define PWR_PUCRB_PB1_Pos (1U)
9930 #define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
9931 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
9932 #define PWR_PUCRB_PB0_Pos (0U)
9933 #define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
9934 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
9935
9936 /******************** Bit definition for PWR_PDCRB register ********************/
9937 #define PWR_PDCRB_PB15_Pos (15U)
9938 #define PWR_PDCRB_PB15_Msk (0x1U << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
9939 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
9940 #define PWR_PDCRB_PB14_Pos (14U)
9941 #define PWR_PDCRB_PB14_Msk (0x1U << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
9942 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
9943 #define PWR_PDCRB_PB13_Pos (13U)
9944 #define PWR_PDCRB_PB13_Msk (0x1U << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
9945 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
9946 #define PWR_PDCRB_PB12_Pos (12U)
9947 #define PWR_PDCRB_PB12_Msk (0x1U << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
9948 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
9949 #define PWR_PDCRB_PB11_Pos (11U)
9950 #define PWR_PDCRB_PB11_Msk (0x1U << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
9951 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
9952 #define PWR_PDCRB_PB10_Pos (10U)
9953 #define PWR_PDCRB_PB10_Msk (0x1U << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
9954 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
9955 #define PWR_PDCRB_PB9_Pos (9U)
9956 #define PWR_PDCRB_PB9_Msk (0x1U << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
9957 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
9958 #define PWR_PDCRB_PB8_Pos (8U)
9959 #define PWR_PDCRB_PB8_Msk (0x1U << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
9960 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
9961 #define PWR_PDCRB_PB7_Pos (7U)
9962 #define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
9963 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
9964 #define PWR_PDCRB_PB6_Pos (6U)
9965 #define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
9966 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
9967 #define PWR_PDCRB_PB5_Pos (5U)
9968 #define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
9969 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
9970 #define PWR_PDCRB_PB3_Pos (3U)
9971 #define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
9972 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
9973 #define PWR_PDCRB_PB2_Pos (2U)
9974 #define PWR_PDCRB_PB2_Msk (0x1U << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
9975 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
9976 #define PWR_PDCRB_PB1_Pos (1U)
9977 #define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
9978 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
9979 #define PWR_PDCRB_PB0_Pos (0U)
9980 #define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
9981 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
9982
9983 /******************** Bit definition for PWR_PUCRC register ********************/
9984 #define PWR_PUCRC_PC15_Pos (15U)
9985 #define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
9986 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
9987 #define PWR_PUCRC_PC14_Pos (14U)
9988 #define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
9989 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
9990 #define PWR_PUCRC_PC13_Pos (13U)
9991 #define PWR_PUCRC_PC13_Msk (0x1U << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
9992 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
9993 #define PWR_PUCRC_PC12_Pos (12U)
9994 #define PWR_PUCRC_PC12_Msk (0x1U << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
9995 #define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
9996 #define PWR_PUCRC_PC11_Pos (11U)
9997 #define PWR_PUCRC_PC11_Msk (0x1U << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
9998 #define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
9999 #define PWR_PUCRC_PC10_Pos (10U)
10000 #define PWR_PUCRC_PC10_Msk (0x1U << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
10001 #define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
10002 #define PWR_PUCRC_PC9_Pos (9U)
10003 #define PWR_PUCRC_PC9_Msk (0x1U << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
10004 #define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
10005 #define PWR_PUCRC_PC8_Pos (8U)
10006 #define PWR_PUCRC_PC8_Msk (0x1U << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
10007 #define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
10008 #define PWR_PUCRC_PC7_Pos (7U)
10009 #define PWR_PUCRC_PC7_Msk (0x1U << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
10010 #define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
10011 #define PWR_PUCRC_PC6_Pos (6U)
10012 #define PWR_PUCRC_PC6_Msk (0x1U << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
10013 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
10014 #define PWR_PUCRC_PC5_Pos (5U)
10015 #define PWR_PUCRC_PC5_Msk (0x1U << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
10016 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
10017 #define PWR_PUCRC_PC4_Pos (4U)
10018 #define PWR_PUCRC_PC4_Msk (0x1U << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
10019 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
10020 #define PWR_PUCRC_PC3_Pos (3U)
10021 #define PWR_PUCRC_PC3_Msk (0x1U << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
10022 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
10023 #define PWR_PUCRC_PC2_Pos (2U)
10024 #define PWR_PUCRC_PC2_Msk (0x1U << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
10025 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
10026 #define PWR_PUCRC_PC1_Pos (1U)
10027 #define PWR_PUCRC_PC1_Msk (0x1U << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
10028 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
10029 #define PWR_PUCRC_PC0_Pos (0U)
10030 #define PWR_PUCRC_PC0_Msk (0x1U << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
10031 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
10032
10033 /******************** Bit definition for PWR_PDCRC register ********************/
10034 #define PWR_PDCRC_PC15_Pos (15U)
10035 #define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
10036 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
10037 #define PWR_PDCRC_PC14_Pos (14U)
10038 #define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
10039 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
10040 #define PWR_PDCRC_PC13_Pos (13U)
10041 #define PWR_PDCRC_PC13_Msk (0x1U << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
10042 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
10043 #define PWR_PDCRC_PC12_Pos (12U)
10044 #define PWR_PDCRC_PC12_Msk (0x1U << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
10045 #define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
10046 #define PWR_PDCRC_PC11_Pos (11U)
10047 #define PWR_PDCRC_PC11_Msk (0x1U << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
10048 #define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
10049 #define PWR_PDCRC_PC10_Pos (10U)
10050 #define PWR_PDCRC_PC10_Msk (0x1U << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
10051 #define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
10052 #define PWR_PDCRC_PC9_Pos (9U)
10053 #define PWR_PDCRC_PC9_Msk (0x1U << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
10054 #define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
10055 #define PWR_PDCRC_PC8_Pos (8U)
10056 #define PWR_PDCRC_PC8_Msk (0x1U << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
10057 #define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
10058 #define PWR_PDCRC_PC7_Pos (7U)
10059 #define PWR_PDCRC_PC7_Msk (0x1U << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
10060 #define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
10061 #define PWR_PDCRC_PC6_Pos (6U)
10062 #define PWR_PDCRC_PC6_Msk (0x1U << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
10063 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
10064 #define PWR_PDCRC_PC5_Pos (5U)
10065 #define PWR_PDCRC_PC5_Msk (0x1U << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
10066 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
10067 #define PWR_PDCRC_PC4_Pos (4U)
10068 #define PWR_PDCRC_PC4_Msk (0x1U << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
10069 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
10070 #define PWR_PDCRC_PC3_Pos (3U)
10071 #define PWR_PDCRC_PC3_Msk (0x1U << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
10072 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
10073 #define PWR_PDCRC_PC2_Pos (2U)
10074 #define PWR_PDCRC_PC2_Msk (0x1U << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
10075 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
10076 #define PWR_PDCRC_PC1_Pos (1U)
10077 #define PWR_PDCRC_PC1_Msk (0x1U << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
10078 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
10079 #define PWR_PDCRC_PC0_Pos (0U)
10080 #define PWR_PDCRC_PC0_Msk (0x1U << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
10081 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
10082
10083 /******************** Bit definition for PWR_PUCRD register ********************/
10084 #define PWR_PUCRD_PD15_Pos (15U)
10085 #define PWR_PUCRD_PD15_Msk (0x1U << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
10086 #define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
10087 #define PWR_PUCRD_PD14_Pos (14U)
10088 #define PWR_PUCRD_PD14_Msk (0x1U << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
10089 #define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
10090 #define PWR_PUCRD_PD13_Pos (13U)
10091 #define PWR_PUCRD_PD13_Msk (0x1U << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
10092 #define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
10093 #define PWR_PUCRD_PD12_Pos (12U)
10094 #define PWR_PUCRD_PD12_Msk (0x1U << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
10095 #define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
10096 #define PWR_PUCRD_PD11_Pos (11U)
10097 #define PWR_PUCRD_PD11_Msk (0x1U << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
10098 #define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
10099 #define PWR_PUCRD_PD10_Pos (10U)
10100 #define PWR_PUCRD_PD10_Msk (0x1U << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
10101 #define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
10102 #define PWR_PUCRD_PD9_Pos (9U)
10103 #define PWR_PUCRD_PD9_Msk (0x1U << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
10104 #define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
10105 #define PWR_PUCRD_PD8_Pos (8U)
10106 #define PWR_PUCRD_PD8_Msk (0x1U << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
10107 #define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
10108 #define PWR_PUCRD_PD7_Pos (7U)
10109 #define PWR_PUCRD_PD7_Msk (0x1U << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
10110 #define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
10111 #define PWR_PUCRD_PD6_Pos (6U)
10112 #define PWR_PUCRD_PD6_Msk (0x1U << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
10113 #define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
10114 #define PWR_PUCRD_PD5_Pos (5U)
10115 #define PWR_PUCRD_PD5_Msk (0x1U << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
10116 #define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
10117 #define PWR_PUCRD_PD4_Pos (4U)
10118 #define PWR_PUCRD_PD4_Msk (0x1U << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
10119 #define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
10120 #define PWR_PUCRD_PD3_Pos (3U)
10121 #define PWR_PUCRD_PD3_Msk (0x1U << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
10122 #define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
10123 #define PWR_PUCRD_PD2_Pos (2U)
10124 #define PWR_PUCRD_PD2_Msk (0x1U << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
10125 #define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
10126 #define PWR_PUCRD_PD1_Pos (1U)
10127 #define PWR_PUCRD_PD1_Msk (0x1U << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
10128 #define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
10129 #define PWR_PUCRD_PD0_Pos (0U)
10130 #define PWR_PUCRD_PD0_Msk (0x1U << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
10131 #define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
10132
10133 /******************** Bit definition for PWR_PDCRD register ********************/
10134 #define PWR_PDCRD_PD15_Pos (15U)
10135 #define PWR_PDCRD_PD15_Msk (0x1U << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
10136 #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
10137 #define PWR_PDCRD_PD14_Pos (14U)
10138 #define PWR_PDCRD_PD14_Msk (0x1U << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
10139 #define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
10140 #define PWR_PDCRD_PD13_Pos (13U)
10141 #define PWR_PDCRD_PD13_Msk (0x1U << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
10142 #define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
10143 #define PWR_PDCRD_PD12_Pos (12U)
10144 #define PWR_PDCRD_PD12_Msk (0x1U << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
10145 #define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
10146 #define PWR_PDCRD_PD11_Pos (11U)
10147 #define PWR_PDCRD_PD11_Msk (0x1U << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
10148 #define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
10149 #define PWR_PDCRD_PD10_Pos (10U)
10150 #define PWR_PDCRD_PD10_Msk (0x1U << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
10151 #define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
10152 #define PWR_PDCRD_PD9_Pos (9U)
10153 #define PWR_PDCRD_PD9_Msk (0x1U << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
10154 #define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
10155 #define PWR_PDCRD_PD8_Pos (8U)
10156 #define PWR_PDCRD_PD8_Msk (0x1U << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
10157 #define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
10158 #define PWR_PDCRD_PD7_Pos (7U)
10159 #define PWR_PDCRD_PD7_Msk (0x1U << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
10160 #define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
10161 #define PWR_PDCRD_PD6_Pos (6U)
10162 #define PWR_PDCRD_PD6_Msk (0x1U << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
10163 #define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
10164 #define PWR_PDCRD_PD5_Pos (5U)
10165 #define PWR_PDCRD_PD5_Msk (0x1U << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
10166 #define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
10167 #define PWR_PDCRD_PD4_Pos (4U)
10168 #define PWR_PDCRD_PD4_Msk (0x1U << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
10169 #define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
10170 #define PWR_PDCRD_PD3_Pos (3U)
10171 #define PWR_PDCRD_PD3_Msk (0x1U << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
10172 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
10173 #define PWR_PDCRD_PD2_Pos (2U)
10174 #define PWR_PDCRD_PD2_Msk (0x1U << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
10175 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
10176 #define PWR_PDCRD_PD1_Pos (1U)
10177 #define PWR_PDCRD_PD1_Msk (0x1U << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
10178 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
10179 #define PWR_PDCRD_PD0_Pos (0U)
10180 #define PWR_PDCRD_PD0_Msk (0x1U << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
10181 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
10182
10183 /******************** Bit definition for PWR_PUCRE register ********************/
10184 #define PWR_PUCRE_PE15_Pos (15U)
10185 #define PWR_PUCRE_PE15_Msk (0x1U << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
10186 #define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
10187 #define PWR_PUCRE_PE14_Pos (14U)
10188 #define PWR_PUCRE_PE14_Msk (0x1U << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
10189 #define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
10190 #define PWR_PUCRE_PE13_Pos (13U)
10191 #define PWR_PUCRE_PE13_Msk (0x1U << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
10192 #define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
10193 #define PWR_PUCRE_PE12_Pos (12U)
10194 #define PWR_PUCRE_PE12_Msk (0x1U << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
10195 #define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
10196 #define PWR_PUCRE_PE11_Pos (11U)
10197 #define PWR_PUCRE_PE11_Msk (0x1U << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
10198 #define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
10199 #define PWR_PUCRE_PE10_Pos (10U)
10200 #define PWR_PUCRE_PE10_Msk (0x1U << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
10201 #define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
10202 #define PWR_PUCRE_PE9_Pos (9U)
10203 #define PWR_PUCRE_PE9_Msk (0x1U << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
10204 #define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
10205 #define PWR_PUCRE_PE8_Pos (8U)
10206 #define PWR_PUCRE_PE8_Msk (0x1U << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
10207 #define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
10208 #define PWR_PUCRE_PE7_Pos (7U)
10209 #define PWR_PUCRE_PE7_Msk (0x1U << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
10210 #define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
10211 #define PWR_PUCRE_PE6_Pos (6U)
10212 #define PWR_PUCRE_PE6_Msk (0x1U << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
10213 #define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
10214 #define PWR_PUCRE_PE5_Pos (5U)
10215 #define PWR_PUCRE_PE5_Msk (0x1U << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
10216 #define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
10217 #define PWR_PUCRE_PE4_Pos (4U)
10218 #define PWR_PUCRE_PE4_Msk (0x1U << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
10219 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
10220 #define PWR_PUCRE_PE3_Pos (3U)
10221 #define PWR_PUCRE_PE3_Msk (0x1U << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
10222 #define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
10223 #define PWR_PUCRE_PE2_Pos (2U)
10224 #define PWR_PUCRE_PE2_Msk (0x1U << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
10225 #define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
10226 #define PWR_PUCRE_PE1_Pos (1U)
10227 #define PWR_PUCRE_PE1_Msk (0x1U << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
10228 #define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
10229 #define PWR_PUCRE_PE0_Pos (0U)
10230 #define PWR_PUCRE_PE0_Msk (0x1U << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
10231 #define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
10232
10233 /******************** Bit definition for PWR_PDCRE register ********************/
10234 #define PWR_PDCRE_PE15_Pos (15U)
10235 #define PWR_PDCRE_PE15_Msk (0x1U << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
10236 #define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
10237 #define PWR_PDCRE_PE14_Pos (14U)
10238 #define PWR_PDCRE_PE14_Msk (0x1U << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
10239 #define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
10240 #define PWR_PDCRE_PE13_Pos (13U)
10241 #define PWR_PDCRE_PE13_Msk (0x1U << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
10242 #define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
10243 #define PWR_PDCRE_PE12_Pos (12U)
10244 #define PWR_PDCRE_PE12_Msk (0x1U << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
10245 #define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
10246 #define PWR_PDCRE_PE11_Pos (11U)
10247 #define PWR_PDCRE_PE11_Msk (0x1U << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
10248 #define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
10249 #define PWR_PDCRE_PE10_Pos (10U)
10250 #define PWR_PDCRE_PE10_Msk (0x1U << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
10251 #define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
10252 #define PWR_PDCRE_PE9_Pos (9U)
10253 #define PWR_PDCRE_PE9_Msk (0x1U << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
10254 #define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
10255 #define PWR_PDCRE_PE8_Pos (8U)
10256 #define PWR_PDCRE_PE8_Msk (0x1U << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
10257 #define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
10258 #define PWR_PDCRE_PE7_Pos (7U)
10259 #define PWR_PDCRE_PE7_Msk (0x1U << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
10260 #define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
10261 #define PWR_PDCRE_PE6_Pos (6U)
10262 #define PWR_PDCRE_PE6_Msk (0x1U << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
10263 #define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
10264 #define PWR_PDCRE_PE5_Pos (5U)
10265 #define PWR_PDCRE_PE5_Msk (0x1U << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
10266 #define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
10267 #define PWR_PDCRE_PE4_Pos (4U)
10268 #define PWR_PDCRE_PE4_Msk (0x1U << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
10269 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
10270 #define PWR_PDCRE_PE3_Pos (3U)
10271 #define PWR_PDCRE_PE3_Msk (0x1U << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
10272 #define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
10273 #define PWR_PDCRE_PE2_Pos (2U)
10274 #define PWR_PDCRE_PE2_Msk (0x1U << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
10275 #define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
10276 #define PWR_PDCRE_PE1_Pos (1U)
10277 #define PWR_PDCRE_PE1_Msk (0x1U << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
10278 #define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
10279 #define PWR_PDCRE_PE0_Pos (0U)
10280 #define PWR_PDCRE_PE0_Msk (0x1U << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
10281 #define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
10282
10283 /******************** Bit definition for PWR_PUCRF register ********************/
10284 #define PWR_PUCRF_PF15_Pos (15U)
10285 #define PWR_PUCRF_PF15_Msk (0x1U << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
10286 #define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
10287 #define PWR_PUCRF_PF14_Pos (14U)
10288 #define PWR_PUCRF_PF14_Msk (0x1U << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
10289 #define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
10290 #define PWR_PUCRF_PF13_Pos (13U)
10291 #define PWR_PUCRF_PF13_Msk (0x1U << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
10292 #define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
10293 #define PWR_PUCRF_PF12_Pos (12U)
10294 #define PWR_PUCRF_PF12_Msk (0x1U << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
10295 #define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
10296 #define PWR_PUCRF_PF11_Pos (11U)
10297 #define PWR_PUCRF_PF11_Msk (0x1U << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
10298 #define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
10299 #define PWR_PUCRF_PF10_Pos (10U)
10300 #define PWR_PUCRF_PF10_Msk (0x1U << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
10301 #define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
10302 #define PWR_PUCRF_PF9_Pos (9U)
10303 #define PWR_PUCRF_PF9_Msk (0x1U << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
10304 #define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
10305 #define PWR_PUCRF_PF8_Pos (8U)
10306 #define PWR_PUCRF_PF8_Msk (0x1U << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
10307 #define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
10308 #define PWR_PUCRF_PF7_Pos (7U)
10309 #define PWR_PUCRF_PF7_Msk (0x1U << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
10310 #define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
10311 #define PWR_PUCRF_PF6_Pos (6U)
10312 #define PWR_PUCRF_PF6_Msk (0x1U << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
10313 #define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
10314 #define PWR_PUCRF_PF5_Pos (5U)
10315 #define PWR_PUCRF_PF5_Msk (0x1U << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
10316 #define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
10317 #define PWR_PUCRF_PF4_Pos (4U)
10318 #define PWR_PUCRF_PF4_Msk (0x1U << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
10319 #define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
10320 #define PWR_PUCRF_PF3_Pos (3U)
10321 #define PWR_PUCRF_PF3_Msk (0x1U << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
10322 #define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
10323 #define PWR_PUCRF_PF2_Pos (2U)
10324 #define PWR_PUCRF_PF2_Msk (0x1U << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
10325 #define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
10326 #define PWR_PUCRF_PF1_Pos (1U)
10327 #define PWR_PUCRF_PF1_Msk (0x1U << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
10328 #define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
10329 #define PWR_PUCRF_PF0_Pos (0U)
10330 #define PWR_PUCRF_PF0_Msk (0x1U << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
10331 #define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
10332
10333 /******************** Bit definition for PWR_PDCRF register ********************/
10334 #define PWR_PDCRF_PF15_Pos (15U)
10335 #define PWR_PDCRF_PF15_Msk (0x1U << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
10336 #define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
10337 #define PWR_PDCRF_PF14_Pos (14U)
10338 #define PWR_PDCRF_PF14_Msk (0x1U << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
10339 #define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
10340 #define PWR_PDCRF_PF13_Pos (13U)
10341 #define PWR_PDCRF_PF13_Msk (0x1U << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
10342 #define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
10343 #define PWR_PDCRF_PF12_Pos (12U)
10344 #define PWR_PDCRF_PF12_Msk (0x1U << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
10345 #define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
10346 #define PWR_PDCRF_PF11_Pos (11U)
10347 #define PWR_PDCRF_PF11_Msk (0x1U << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
10348 #define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
10349 #define PWR_PDCRF_PF10_Pos (10U)
10350 #define PWR_PDCRF_PF10_Msk (0x1U << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
10351 #define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
10352 #define PWR_PDCRF_PF9_Pos (9U)
10353 #define PWR_PDCRF_PF9_Msk (0x1U << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
10354 #define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
10355 #define PWR_PDCRF_PF8_Pos (8U)
10356 #define PWR_PDCRF_PF8_Msk (0x1U << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
10357 #define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
10358 #define PWR_PDCRF_PF7_Pos (7U)
10359 #define PWR_PDCRF_PF7_Msk (0x1U << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
10360 #define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
10361 #define PWR_PDCRF_PF6_Pos (6U)
10362 #define PWR_PDCRF_PF6_Msk (0x1U << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
10363 #define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
10364 #define PWR_PDCRF_PF5_Pos (5U)
10365 #define PWR_PDCRF_PF5_Msk (0x1U << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
10366 #define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
10367 #define PWR_PDCRF_PF4_Pos (4U)
10368 #define PWR_PDCRF_PF4_Msk (0x1U << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
10369 #define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
10370 #define PWR_PDCRF_PF3_Pos (3U)
10371 #define PWR_PDCRF_PF3_Msk (0x1U << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
10372 #define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
10373 #define PWR_PDCRF_PF2_Pos (2U)
10374 #define PWR_PDCRF_PF2_Msk (0x1U << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
10375 #define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
10376 #define PWR_PDCRF_PF1_Pos (1U)
10377 #define PWR_PDCRF_PF1_Msk (0x1U << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
10378 #define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
10379 #define PWR_PDCRF_PF0_Pos (0U)
10380 #define PWR_PDCRF_PF0_Msk (0x1U << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
10381 #define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
10382
10383 /******************** Bit definition for PWR_PUCRG register ********************/
10384 #define PWR_PUCRG_PG15_Pos (15U)
10385 #define PWR_PUCRG_PG15_Msk (0x1U << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
10386 #define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
10387 #define PWR_PUCRG_PG14_Pos (14U)
10388 #define PWR_PUCRG_PG14_Msk (0x1U << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
10389 #define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
10390 #define PWR_PUCRG_PG13_Pos (13U)
10391 #define PWR_PUCRG_PG13_Msk (0x1U << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
10392 #define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
10393 #define PWR_PUCRG_PG12_Pos (12U)
10394 #define PWR_PUCRG_PG12_Msk (0x1U << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
10395 #define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
10396 #define PWR_PUCRG_PG11_Pos (11U)
10397 #define PWR_PUCRG_PG11_Msk (0x1U << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
10398 #define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
10399 #define PWR_PUCRG_PG10_Pos (10U)
10400 #define PWR_PUCRG_PG10_Msk (0x1U << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
10401 #define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
10402 #define PWR_PUCRG_PG9_Pos (9U)
10403 #define PWR_PUCRG_PG9_Msk (0x1U << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
10404 #define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
10405 #define PWR_PUCRG_PG8_Pos (8U)
10406 #define PWR_PUCRG_PG8_Msk (0x1U << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
10407 #define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
10408 #define PWR_PUCRG_PG7_Pos (7U)
10409 #define PWR_PUCRG_PG7_Msk (0x1U << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
10410 #define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
10411 #define PWR_PUCRG_PG6_Pos (6U)
10412 #define PWR_PUCRG_PG6_Msk (0x1U << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
10413 #define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
10414 #define PWR_PUCRG_PG5_Pos (5U)
10415 #define PWR_PUCRG_PG5_Msk (0x1U << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
10416 #define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
10417 #define PWR_PUCRG_PG4_Pos (4U)
10418 #define PWR_PUCRG_PG4_Msk (0x1U << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
10419 #define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
10420 #define PWR_PUCRG_PG3_Pos (3U)
10421 #define PWR_PUCRG_PG3_Msk (0x1U << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
10422 #define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
10423 #define PWR_PUCRG_PG2_Pos (2U)
10424 #define PWR_PUCRG_PG2_Msk (0x1U << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
10425 #define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
10426 #define PWR_PUCRG_PG1_Pos (1U)
10427 #define PWR_PUCRG_PG1_Msk (0x1U << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
10428 #define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
10429 #define PWR_PUCRG_PG0_Pos (0U)
10430 #define PWR_PUCRG_PG0_Msk (0x1U << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
10431 #define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
10432
10433 /******************** Bit definition for PWR_PDCRG register ********************/
10434 #define PWR_PDCRG_PG15_Pos (15U)
10435 #define PWR_PDCRG_PG15_Msk (0x1U << PWR_PDCRG_PG15_Pos) /*!< 0x00008000 */
10436 #define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk /*!< Port PG15 Pull-Down set */
10437 #define PWR_PDCRG_PG14_Pos (14U)
10438 #define PWR_PDCRG_PG14_Msk (0x1U << PWR_PDCRG_PG14_Pos) /*!< 0x00004000 */
10439 #define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk /*!< Port PG14 Pull-Down set */
10440 #define PWR_PDCRG_PG13_Pos (13U)
10441 #define PWR_PDCRG_PG13_Msk (0x1U << PWR_PDCRG_PG13_Pos) /*!< 0x00002000 */
10442 #define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk /*!< Port PG13 Pull-Down set */
10443 #define PWR_PDCRG_PG12_Pos (12U)
10444 #define PWR_PDCRG_PG12_Msk (0x1U << PWR_PDCRG_PG12_Pos) /*!< 0x00001000 */
10445 #define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk /*!< Port PG12 Pull-Down set */
10446 #define PWR_PDCRG_PG11_Pos (11U)
10447 #define PWR_PDCRG_PG11_Msk (0x1U << PWR_PDCRG_PG11_Pos) /*!< 0x00000800 */
10448 #define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk /*!< Port PG11 Pull-Down set */
10449 #define PWR_PDCRG_PG10_Pos (10U)
10450 #define PWR_PDCRG_PG10_Msk (0x1U << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
10451 #define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
10452 #define PWR_PDCRG_PG9_Pos (9U)
10453 #define PWR_PDCRG_PG9_Msk (0x1U << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
10454 #define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
10455 #define PWR_PDCRG_PG8_Pos (8U)
10456 #define PWR_PDCRG_PG8_Msk (0x1U << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
10457 #define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
10458 #define PWR_PDCRG_PG7_Pos (7U)
10459 #define PWR_PDCRG_PG7_Msk (0x1U << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
10460 #define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
10461 #define PWR_PDCRG_PG6_Pos (6U)
10462 #define PWR_PDCRG_PG6_Msk (0x1U << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
10463 #define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
10464 #define PWR_PDCRG_PG5_Pos (5U)
10465 #define PWR_PDCRG_PG5_Msk (0x1U << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
10466 #define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
10467 #define PWR_PDCRG_PG4_Pos (4U)
10468 #define PWR_PDCRG_PG4_Msk (0x1U << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
10469 #define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
10470 #define PWR_PDCRG_PG3_Pos (3U)
10471 #define PWR_PDCRG_PG3_Msk (0x1U << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
10472 #define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
10473 #define PWR_PDCRG_PG2_Pos (2U)
10474 #define PWR_PDCRG_PG2_Msk (0x1U << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
10475 #define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
10476 #define PWR_PDCRG_PG1_Pos (1U)
10477 #define PWR_PDCRG_PG1_Msk (0x1U << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
10478 #define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
10479 #define PWR_PDCRG_PG0_Pos (0U)
10480 #define PWR_PDCRG_PG0_Msk (0x1U << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
10481 #define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
10482
10483 /******************** Bit definition for PWR_PUCRH register ********************/
10484 #define PWR_PUCRH_PH1_Pos (1U)
10485 #define PWR_PUCRH_PH1_Msk (0x1U << PWR_PUCRH_PH1_Pos) /*!< 0x00000002 */
10486 #define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk /*!< Port PH1 Pull-Up set */
10487 #define PWR_PUCRH_PH0_Pos (0U)
10488 #define PWR_PUCRH_PH0_Msk (0x1U << PWR_PUCRH_PH0_Pos) /*!< 0x00000001 */
10489 #define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk /*!< Port PH0 Pull-Up set */
10490
10491 /******************** Bit definition for PWR_PDCRH register ********************/
10492 #define PWR_PDCRH_PH1_Pos (1U)
10493 #define PWR_PDCRH_PH1_Msk (0x1U << PWR_PDCRH_PH1_Pos) /*!< 0x00000002 */
10494 #define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk /*!< Port PH1 Pull-Down set */
10495 #define PWR_PDCRH_PH0_Pos (0U)
10496 #define PWR_PDCRH_PH0_Msk (0x1U << PWR_PDCRH_PH0_Pos) /*!< 0x00000001 */
10497 #define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk /*!< Port PH0 Pull-Down set */
10498
10499
10500 /******************************************************************************/
10501 /* */
10502 /* Reset and Clock Control */
10503 /* */
10504 /******************************************************************************/
10505 /*
10506 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
10507 */
10508 #define RCC_PLLSAI2_SUPPORT
10509
10510 /******************** Bit definition for RCC_CR register ********************/
10511 #define RCC_CR_MSION_Pos (0U)
10512 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
10513 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
10514 #define RCC_CR_MSIRDY_Pos (1U)
10515 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
10516 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
10517 #define RCC_CR_MSIPLLEN_Pos (2U)
10518 #define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
10519 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
10520 #define RCC_CR_MSIRGSEL_Pos (3U)
10521 #define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
10522 #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
10523
10524 /*!< MSIRANGE configuration : 12 frequency ranges available */
10525 #define RCC_CR_MSIRANGE_Pos (4U)
10526 #define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
10527 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
10528 #define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
10529 #define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
10530 #define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
10531 #define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
10532 #define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
10533 #define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
10534 #define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
10535 #define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
10536 #define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
10537 #define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
10538 #define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
10539 #define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
10540
10541 #define RCC_CR_HSION_Pos (8U)
10542 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
10543 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
10544 #define RCC_CR_HSIKERON_Pos (9U)
10545 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
10546 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
10547 #define RCC_CR_HSIRDY_Pos (10U)
10548 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
10549 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
10550 #define RCC_CR_HSIASFS_Pos (11U)
10551 #define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
10552 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
10553
10554 #define RCC_CR_HSEON_Pos (16U)
10555 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
10556 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
10557 #define RCC_CR_HSERDY_Pos (17U)
10558 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
10559 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
10560 #define RCC_CR_HSEBYP_Pos (18U)
10561 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
10562 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
10563 #define RCC_CR_CSSON_Pos (19U)
10564 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
10565 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
10566
10567 #define RCC_CR_PLLON_Pos (24U)
10568 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
10569 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
10570 #define RCC_CR_PLLRDY_Pos (25U)
10571 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
10572 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
10573 #define RCC_CR_PLLSAI1ON_Pos (26U)
10574 #define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
10575 #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
10576 #define RCC_CR_PLLSAI1RDY_Pos (27U)
10577 #define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
10578 #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
10579 #define RCC_CR_PLLSAI2ON_Pos (28U)
10580 #define RCC_CR_PLLSAI2ON_Msk (0x1U << RCC_CR_PLLSAI2ON_Pos) /*!< 0x10000000 */
10581 #define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk /*!< SAI2 PLL enable */
10582 #define RCC_CR_PLLSAI2RDY_Pos (29U)
10583 #define RCC_CR_PLLSAI2RDY_Msk (0x1U << RCC_CR_PLLSAI2RDY_Pos) /*!< 0x20000000 */
10584 #define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk /*!< SAI2 PLL ready */
10585
10586 /******************** Bit definition for RCC_ICSCR register ***************/
10587 /*!< MSICAL configuration */
10588 #define RCC_ICSCR_MSICAL_Pos (0U)
10589 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
10590 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
10591 #define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
10592 #define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
10593 #define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
10594 #define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
10595 #define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
10596 #define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
10597 #define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
10598 #define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
10599
10600 /*!< MSITRIM configuration */
10601 #define RCC_ICSCR_MSITRIM_Pos (8U)
10602 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
10603 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
10604 #define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
10605 #define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
10606 #define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
10607 #define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
10608 #define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
10609 #define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
10610 #define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
10611 #define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
10612
10613 /*!< HSICAL configuration */
10614 #define RCC_ICSCR_HSICAL_Pos (16U)
10615 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
10616 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
10617 #define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
10618 #define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
10619 #define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
10620 #define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
10621 #define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
10622 #define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
10623 #define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
10624 #define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
10625
10626 /*!< HSITRIM configuration */
10627 #define RCC_ICSCR_HSITRIM_Pos (24U)
10628 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
10629 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
10630 #define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
10631 #define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
10632 #define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
10633 #define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
10634 #define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
10635
10636 /******************** Bit definition for RCC_CFGR register ******************/
10637 /*!< SW configuration */
10638 #define RCC_CFGR_SW_Pos (0U)
10639 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
10640 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
10641 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
10642 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
10643
10644 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
10645 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
10646 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
10647 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
10648
10649 /*!< SWS configuration */
10650 #define RCC_CFGR_SWS_Pos (2U)
10651 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
10652 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
10653 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
10654 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
10655
10656 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
10657 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
10658 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
10659 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
10660
10661 /*!< HPRE configuration */
10662 #define RCC_CFGR_HPRE_Pos (4U)
10663 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
10664 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
10665 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
10666 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
10667 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
10668 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
10669
10670 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
10671 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
10672 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
10673 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
10674 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
10675 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
10676 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
10677 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
10678 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
10679
10680 /*!< PPRE1 configuration */
10681 #define RCC_CFGR_PPRE1_Pos (8U)
10682 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
10683 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
10684 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
10685 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
10686 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
10687
10688 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
10689 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
10690 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
10691 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
10692 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
10693
10694 /*!< PPRE2 configuration */
10695 #define RCC_CFGR_PPRE2_Pos (11U)
10696 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
10697 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
10698 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
10699 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
10700 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
10701
10702 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
10703 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
10704 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
10705 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
10706 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
10707
10708 #define RCC_CFGR_STOPWUCK_Pos (15U)
10709 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
10710 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
10711
10712 /*!< MCOSEL configuration */
10713 #define RCC_CFGR_MCOSEL_Pos (24U)
10714 #define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
10715 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
10716 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
10717 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
10718 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
10719
10720 #define RCC_CFGR_MCOPRE_Pos (28U)
10721 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
10722 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
10723 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
10724 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
10725 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
10726
10727 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
10728 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
10729 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
10730 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
10731 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
10732
10733 /* Legacy aliases */
10734 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
10735 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
10736 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
10737 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
10738 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
10739 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
10740
10741 /******************** Bit definition for RCC_PLLCFGR register ***************/
10742 #define RCC_PLLCFGR_PLLSRC_Pos (0U)
10743 #define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
10744 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10745
10746 #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
10747 #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
10748 #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
10749 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
10750 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
10751 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
10752 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
10753 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
10754 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
10755
10756 #define RCC_PLLCFGR_PLLM_Pos (4U)
10757 #define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
10758 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10759 #define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
10760 #define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
10761 #define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
10762
10763 #define RCC_PLLCFGR_PLLN_Pos (8U)
10764 #define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
10765 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10766 #define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
10767 #define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
10768 #define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
10769 #define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
10770 #define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
10771 #define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
10772 #define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
10773
10774 #define RCC_PLLCFGR_PLLPEN_Pos (16U)
10775 #define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
10776 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
10777 #define RCC_PLLCFGR_PLLP_Pos (17U)
10778 #define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
10779 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10780 #define RCC_PLLCFGR_PLLQEN_Pos (20U)
10781 #define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
10782 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
10783
10784 #define RCC_PLLCFGR_PLLQ_Pos (21U)
10785 #define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
10786 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10787 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
10788 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
10789
10790 #define RCC_PLLCFGR_PLLREN_Pos (24U)
10791 #define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
10792 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
10793 #define RCC_PLLCFGR_PLLR_Pos (25U)
10794 #define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
10795 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
10796 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
10797 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
10798
10799 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
10800 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
10801 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
10802 #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
10803 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
10804 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
10805 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
10806 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
10807 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
10808 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
10809 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
10810
10811 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
10812 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
10813 #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
10814 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
10815 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
10816 #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
10817
10818 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
10819 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
10820 #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
10821 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
10822 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
10823 #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
10824 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
10825 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
10826
10827 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
10828 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
10829 #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
10830 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
10831 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
10832 #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
10833 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
10834 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
10835
10836 /******************** Bit definition for RCC_PLLSAI2CFGR register ************/
10837 #define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
10838 #define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
10839 #define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
10840 #define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
10841 #define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
10842 #define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
10843 #define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
10844 #define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
10845 #define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
10846 #define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
10847
10848 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
10849 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
10850 #define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
10851 #define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
10852 #define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
10853 #define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
10854
10855 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
10856 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
10857 #define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
10858 #define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
10859 #define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
10860 #define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
10861 #define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
10862 #define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
10863
10864 /******************** Bit definition for RCC_CIER register ******************/
10865 #define RCC_CIER_LSIRDYIE_Pos (0U)
10866 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
10867 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
10868 #define RCC_CIER_LSERDYIE_Pos (1U)
10869 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
10870 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
10871 #define RCC_CIER_MSIRDYIE_Pos (2U)
10872 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
10873 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
10874 #define RCC_CIER_HSIRDYIE_Pos (3U)
10875 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
10876 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
10877 #define RCC_CIER_HSERDYIE_Pos (4U)
10878 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
10879 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
10880 #define RCC_CIER_PLLRDYIE_Pos (5U)
10881 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
10882 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
10883 #define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
10884 #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
10885 #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
10886 #define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
10887 #define RCC_CIER_PLLSAI2RDYIE_Msk (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
10888 #define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
10889 #define RCC_CIER_LSECSSIE_Pos (9U)
10890 #define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
10891 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
10892
10893 /******************** Bit definition for RCC_CIFR register ******************/
10894 #define RCC_CIFR_LSIRDYF_Pos (0U)
10895 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
10896 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
10897 #define RCC_CIFR_LSERDYF_Pos (1U)
10898 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
10899 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
10900 #define RCC_CIFR_MSIRDYF_Pos (2U)
10901 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
10902 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
10903 #define RCC_CIFR_HSIRDYF_Pos (3U)
10904 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
10905 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
10906 #define RCC_CIFR_HSERDYF_Pos (4U)
10907 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
10908 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
10909 #define RCC_CIFR_PLLRDYF_Pos (5U)
10910 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
10911 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
10912 #define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
10913 #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
10914 #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
10915 #define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
10916 #define RCC_CIFR_PLLSAI2RDYF_Msk (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
10917 #define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
10918 #define RCC_CIFR_CSSF_Pos (8U)
10919 #define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
10920 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
10921 #define RCC_CIFR_LSECSSF_Pos (9U)
10922 #define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
10923 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
10924
10925 /******************** Bit definition for RCC_CICR register ******************/
10926 #define RCC_CICR_LSIRDYC_Pos (0U)
10927 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
10928 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
10929 #define RCC_CICR_LSERDYC_Pos (1U)
10930 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
10931 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
10932 #define RCC_CICR_MSIRDYC_Pos (2U)
10933 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
10934 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
10935 #define RCC_CICR_HSIRDYC_Pos (3U)
10936 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
10937 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
10938 #define RCC_CICR_HSERDYC_Pos (4U)
10939 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
10940 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
10941 #define RCC_CICR_PLLRDYC_Pos (5U)
10942 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
10943 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
10944 #define RCC_CICR_PLLSAI1RDYC_Pos (6U)
10945 #define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
10946 #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
10947 #define RCC_CICR_PLLSAI2RDYC_Pos (7U)
10948 #define RCC_CICR_PLLSAI2RDYC_Msk (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
10949 #define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
10950 #define RCC_CICR_CSSC_Pos (8U)
10951 #define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
10952 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
10953 #define RCC_CICR_LSECSSC_Pos (9U)
10954 #define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
10955 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
10956
10957 /******************** Bit definition for RCC_AHB1RSTR register **************/
10958 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
10959 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
10960 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10961 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
10962 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
10963 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10964 #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
10965 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
10966 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
10967 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
10968 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
10969 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10970 #define RCC_AHB1RSTR_TSCRST_Pos (16U)
10971 #define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
10972 #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
10973
10974 /******************** Bit definition for RCC_AHB2RSTR register **************/
10975 #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
10976 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
10977 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
10978 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
10979 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
10980 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
10981 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
10982 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
10983 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
10984 #define RCC_AHB2RSTR_GPIODRST_Pos (3U)
10985 #define RCC_AHB2RSTR_GPIODRST_Msk (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
10986 #define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
10987 #define RCC_AHB2RSTR_GPIOERST_Pos (4U)
10988 #define RCC_AHB2RSTR_GPIOERST_Msk (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
10989 #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
10990 #define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
10991 #define RCC_AHB2RSTR_GPIOFRST_Msk (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
10992 #define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
10993 #define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
10994 #define RCC_AHB2RSTR_GPIOGRST_Msk (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
10995 #define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
10996 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
10997 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
10998 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
10999 #define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
11000 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
11001 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
11002 #define RCC_AHB2RSTR_ADCRST_Pos (13U)
11003 #define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
11004 #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
11005 #define RCC_AHB2RSTR_RNGRST_Pos (18U)
11006 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
11007 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
11008
11009 /******************** Bit definition for RCC_AHB3RSTR register **************/
11010 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
11011 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
11012 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
11013 #define RCC_AHB3RSTR_QSPIRST_Pos (8U)
11014 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
11015 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
11016
11017 /******************** Bit definition for RCC_APB1RSTR1 register **************/
11018 #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
11019 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
11020 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
11021 #define RCC_APB1RSTR1_TIM3RST_Pos (1U)
11022 #define RCC_APB1RSTR1_TIM3RST_Msk (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
11023 #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
11024 #define RCC_APB1RSTR1_TIM4RST_Pos (2U)
11025 #define RCC_APB1RSTR1_TIM4RST_Msk (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
11026 #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
11027 #define RCC_APB1RSTR1_TIM5RST_Pos (3U)
11028 #define RCC_APB1RSTR1_TIM5RST_Msk (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
11029 #define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
11030 #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
11031 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
11032 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
11033 #define RCC_APB1RSTR1_TIM7RST_Pos (5U)
11034 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
11035 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
11036 #define RCC_APB1RSTR1_LCDRST_Pos (9U)
11037 #define RCC_APB1RSTR1_LCDRST_Msk (0x1U << RCC_APB1RSTR1_LCDRST_Pos) /*!< 0x00000200 */
11038 #define RCC_APB1RSTR1_LCDRST RCC_APB1RSTR1_LCDRST_Msk
11039 #define RCC_APB1RSTR1_SPI2RST_Pos (14U)
11040 #define RCC_APB1RSTR1_SPI2RST_Msk (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
11041 #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
11042 #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
11043 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
11044 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
11045 #define RCC_APB1RSTR1_USART2RST_Pos (17U)
11046 #define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
11047 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
11048 #define RCC_APB1RSTR1_USART3RST_Pos (18U)
11049 #define RCC_APB1RSTR1_USART3RST_Msk (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
11050 #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
11051 #define RCC_APB1RSTR1_UART4RST_Pos (19U)
11052 #define RCC_APB1RSTR1_UART4RST_Msk (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
11053 #define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
11054 #define RCC_APB1RSTR1_UART5RST_Pos (20U)
11055 #define RCC_APB1RSTR1_UART5RST_Msk (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
11056 #define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
11057 #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
11058 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
11059 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
11060 #define RCC_APB1RSTR1_I2C2RST_Pos (22U)
11061 #define RCC_APB1RSTR1_I2C2RST_Msk (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
11062 #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
11063 #define RCC_APB1RSTR1_I2C3RST_Pos (23U)
11064 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
11065 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
11066 #define RCC_APB1RSTR1_CAN1RST_Pos (25U)
11067 #define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
11068 #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
11069 #define RCC_APB1RSTR1_PWRRST_Pos (28U)
11070 #define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
11071 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
11072 #define RCC_APB1RSTR1_DAC1RST_Pos (29U)
11073 #define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
11074 #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
11075 #define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
11076 #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
11077 #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
11078 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
11079 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
11080 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
11081
11082 /******************** Bit definition for RCC_APB1RSTR2 register **************/
11083 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
11084 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
11085 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
11086 #define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
11087 #define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
11088 #define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
11089 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
11090 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
11091 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
11092
11093 /******************** Bit definition for RCC_APB2RSTR register **************/
11094 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
11095 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
11096 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
11097 #define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
11098 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
11099 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
11100 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
11101 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
11102 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
11103 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
11104 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
11105 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
11106 #define RCC_APB2RSTR_TIM8RST_Pos (13U)
11107 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
11108 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
11109 #define RCC_APB2RSTR_USART1RST_Pos (14U)
11110 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
11111 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
11112 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
11113 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
11114 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
11115 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
11116 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
11117 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
11118 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
11119 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
11120 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
11121 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
11122 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
11123 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
11124 #define RCC_APB2RSTR_SAI2RST_Pos (22U)
11125 #define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
11126 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
11127 #define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
11128 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
11129 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
11130
11131 /******************** Bit definition for RCC_AHB1ENR register ***************/
11132 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
11133 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
11134 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
11135 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
11136 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
11137 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
11138 #define RCC_AHB1ENR_FLASHEN_Pos (8U)
11139 #define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
11140 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
11141 #define RCC_AHB1ENR_CRCEN_Pos (12U)
11142 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
11143 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
11144 #define RCC_AHB1ENR_TSCEN_Pos (16U)
11145 #define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
11146 #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
11147
11148 /******************** Bit definition for RCC_AHB2ENR register ***************/
11149 #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
11150 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
11151 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
11152 #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
11153 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
11154 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
11155 #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
11156 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
11157 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
11158 #define RCC_AHB2ENR_GPIODEN_Pos (3U)
11159 #define RCC_AHB2ENR_GPIODEN_Msk (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
11160 #define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
11161 #define RCC_AHB2ENR_GPIOEEN_Pos (4U)
11162 #define RCC_AHB2ENR_GPIOEEN_Msk (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
11163 #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
11164 #define RCC_AHB2ENR_GPIOFEN_Pos (5U)
11165 #define RCC_AHB2ENR_GPIOFEN_Msk (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
11166 #define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
11167 #define RCC_AHB2ENR_GPIOGEN_Pos (6U)
11168 #define RCC_AHB2ENR_GPIOGEN_Msk (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
11169 #define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
11170 #define RCC_AHB2ENR_GPIOHEN_Pos (7U)
11171 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
11172 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
11173 #define RCC_AHB2ENR_OTGFSEN_Pos (12U)
11174 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
11175 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11176 #define RCC_AHB2ENR_ADCEN_Pos (13U)
11177 #define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
11178 #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
11179 #define RCC_AHB2ENR_RNGEN_Pos (18U)
11180 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
11181 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11182
11183 /******************** Bit definition for RCC_AHB3ENR register ***************/
11184 #define RCC_AHB3ENR_FMCEN_Pos (0U)
11185 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
11186 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11187 #define RCC_AHB3ENR_QSPIEN_Pos (8U)
11188 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
11189 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
11190
11191 /******************** Bit definition for RCC_APB1ENR1 register ***************/
11192 #define RCC_APB1ENR1_TIM2EN_Pos (0U)
11193 #define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
11194 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
11195 #define RCC_APB1ENR1_TIM3EN_Pos (1U)
11196 #define RCC_APB1ENR1_TIM3EN_Msk (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
11197 #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
11198 #define RCC_APB1ENR1_TIM4EN_Pos (2U)
11199 #define RCC_APB1ENR1_TIM4EN_Msk (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
11200 #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
11201 #define RCC_APB1ENR1_TIM5EN_Pos (3U)
11202 #define RCC_APB1ENR1_TIM5EN_Msk (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
11203 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
11204 #define RCC_APB1ENR1_TIM6EN_Pos (4U)
11205 #define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
11206 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
11207 #define RCC_APB1ENR1_TIM7EN_Pos (5U)
11208 #define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
11209 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
11210 #define RCC_APB1ENR1_LCDEN_Pos (9U)
11211 #define RCC_APB1ENR1_LCDEN_Msk (0x1U << RCC_APB1ENR1_LCDEN_Pos) /*!< 0x00000200 */
11212 #define RCC_APB1ENR1_LCDEN RCC_APB1ENR1_LCDEN_Msk
11213 #define RCC_APB1ENR1_WWDGEN_Pos (11U)
11214 #define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
11215 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
11216 #define RCC_APB1ENR1_SPI2EN_Pos (14U)
11217 #define RCC_APB1ENR1_SPI2EN_Msk (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
11218 #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
11219 #define RCC_APB1ENR1_SPI3EN_Pos (15U)
11220 #define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
11221 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
11222 #define RCC_APB1ENR1_USART2EN_Pos (17U)
11223 #define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
11224 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
11225 #define RCC_APB1ENR1_USART3EN_Pos (18U)
11226 #define RCC_APB1ENR1_USART3EN_Msk (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
11227 #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
11228 #define RCC_APB1ENR1_UART4EN_Pos (19U)
11229 #define RCC_APB1ENR1_UART4EN_Msk (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
11230 #define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
11231 #define RCC_APB1ENR1_UART5EN_Pos (20U)
11232 #define RCC_APB1ENR1_UART5EN_Msk (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
11233 #define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
11234 #define RCC_APB1ENR1_I2C1EN_Pos (21U)
11235 #define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
11236 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
11237 #define RCC_APB1ENR1_I2C2EN_Pos (22U)
11238 #define RCC_APB1ENR1_I2C2EN_Msk (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
11239 #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
11240 #define RCC_APB1ENR1_I2C3EN_Pos (23U)
11241 #define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
11242 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
11243 #define RCC_APB1ENR1_CAN1EN_Pos (25U)
11244 #define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
11245 #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
11246 #define RCC_APB1ENR1_PWREN_Pos (28U)
11247 #define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
11248 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
11249 #define RCC_APB1ENR1_DAC1EN_Pos (29U)
11250 #define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
11251 #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
11252 #define RCC_APB1ENR1_OPAMPEN_Pos (30U)
11253 #define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
11254 #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
11255 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
11256 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
11257 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
11258
11259 /******************** Bit definition for RCC_APB1RSTR2 register **************/
11260 #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
11261 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
11262 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
11263 #define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
11264 #define RCC_APB1ENR2_SWPMI1EN_Msk (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
11265 #define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
11266 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
11267 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
11268 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
11269
11270 /******************** Bit definition for RCC_APB2ENR register ***************/
11271 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
11272 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
11273 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11274 #define RCC_APB2ENR_FWEN_Pos (7U)
11275 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
11276 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
11277 #define RCC_APB2ENR_SDMMC1EN_Pos (10U)
11278 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
11279 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
11280 #define RCC_APB2ENR_TIM1EN_Pos (11U)
11281 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
11282 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11283 #define RCC_APB2ENR_SPI1EN_Pos (12U)
11284 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
11285 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11286 #define RCC_APB2ENR_TIM8EN_Pos (13U)
11287 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
11288 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11289 #define RCC_APB2ENR_USART1EN_Pos (14U)
11290 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
11291 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11292 #define RCC_APB2ENR_TIM15EN_Pos (16U)
11293 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
11294 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
11295 #define RCC_APB2ENR_TIM16EN_Pos (17U)
11296 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
11297 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
11298 #define RCC_APB2ENR_TIM17EN_Pos (18U)
11299 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
11300 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
11301 #define RCC_APB2ENR_SAI1EN_Pos (21U)
11302 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
11303 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11304 #define RCC_APB2ENR_SAI2EN_Pos (22U)
11305 #define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */
11306 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
11307 #define RCC_APB2ENR_DFSDM1EN_Pos (24U)
11308 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
11309 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
11310
11311 /******************** Bit definition for RCC_AHB1SMENR register ***************/
11312 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
11313 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
11314 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
11315 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
11316 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
11317 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
11318 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
11319 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
11320 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
11321 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
11322 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
11323 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
11324 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
11325 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
11326 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
11327 #define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
11328 #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
11329 #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
11330
11331 /******************** Bit definition for RCC_AHB2SMENR register *************/
11332 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
11333 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
11334 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
11335 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
11336 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
11337 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
11338 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
11339 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
11340 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
11341 #define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
11342 #define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
11343 #define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
11344 #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
11345 #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
11346 #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
11347 #define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
11348 #define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
11349 #define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
11350 #define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
11351 #define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
11352 #define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
11353 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
11354 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
11355 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
11356 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
11357 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
11358 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
11359 #define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
11360 #define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
11361 #define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
11362 #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
11363 #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
11364 #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
11365 #define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
11366 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
11367 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
11368
11369 /******************** Bit definition for RCC_AHB3SMENR register *************/
11370 #define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
11371 #define RCC_AHB3SMENR_FMCSMEN_Msk (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
11372 #define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
11373 #define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
11374 #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
11375 #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
11376
11377 /******************** Bit definition for RCC_APB1SMENR1 register *************/
11378 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
11379 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
11380 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
11381 #define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
11382 #define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
11383 #define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
11384 #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
11385 #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
11386 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
11387 #define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
11388 #define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
11389 #define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
11390 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
11391 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
11392 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
11393 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
11394 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
11395 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
11396 #define RCC_APB1SMENR1_LCDSMEN_Pos (9U)
11397 #define RCC_APB1SMENR1_LCDSMEN_Msk (0x1U << RCC_APB1SMENR1_LCDSMEN_Pos) /*!< 0x00000200 */
11398 #define RCC_APB1SMENR1_LCDSMEN RCC_APB1SMENR1_LCDSMEN_Msk
11399 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
11400 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
11401 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
11402 #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
11403 #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
11404 #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
11405 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
11406 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
11407 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
11408 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
11409 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
11410 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
11411 #define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
11412 #define RCC_APB1SMENR1_USART3SMEN_Msk (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
11413 #define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
11414 #define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
11415 #define RCC_APB1SMENR1_UART4SMEN_Msk (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
11416 #define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
11417 #define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
11418 #define RCC_APB1SMENR1_UART5SMEN_Msk (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
11419 #define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
11420 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
11421 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
11422 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
11423 #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
11424 #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
11425 #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
11426 #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
11427 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
11428 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
11429 #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
11430 #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
11431 #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
11432 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
11433 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
11434 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
11435 #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
11436 #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
11437 #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
11438 #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
11439 #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
11440 #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
11441 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
11442 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
11443 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
11444
11445 /******************** Bit definition for RCC_APB1SMENR2 register *************/
11446 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
11447 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
11448 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
11449 #define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
11450 #define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
11451 #define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
11452 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
11453 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
11454 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
11455
11456 /******************** Bit definition for RCC_APB2SMENR register *************/
11457 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
11458 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
11459 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
11460 #define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
11461 #define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
11462 #define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
11463 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
11464 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
11465 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
11466 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
11467 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
11468 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
11469 #define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
11470 #define RCC_APB2SMENR_TIM8SMEN_Msk (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
11471 #define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
11472 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
11473 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
11474 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
11475 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
11476 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
11477 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
11478 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
11479 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
11480 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
11481 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
11482 #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
11483 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
11484 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
11485 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
11486 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
11487 #define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
11488 #define RCC_APB2SMENR_SAI2SMEN_Msk (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
11489 #define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
11490 #define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
11491 #define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
11492 #define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
11493
11494 /******************** Bit definition for RCC_CCIPR register ******************/
11495 #define RCC_CCIPR_USART1SEL_Pos (0U)
11496 #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
11497 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
11498 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
11499 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
11500
11501 #define RCC_CCIPR_USART2SEL_Pos (2U)
11502 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
11503 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
11504 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
11505 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
11506
11507 #define RCC_CCIPR_USART3SEL_Pos (4U)
11508 #define RCC_CCIPR_USART3SEL_Msk (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
11509 #define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
11510 #define RCC_CCIPR_USART3SEL_0 (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
11511 #define RCC_CCIPR_USART3SEL_1 (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
11512
11513 #define RCC_CCIPR_UART4SEL_Pos (6U)
11514 #define RCC_CCIPR_UART4SEL_Msk (0x3U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
11515 #define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
11516 #define RCC_CCIPR_UART4SEL_0 (0x1U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
11517 #define RCC_CCIPR_UART4SEL_1 (0x2U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
11518
11519 #define RCC_CCIPR_UART5SEL_Pos (8U)
11520 #define RCC_CCIPR_UART5SEL_Msk (0x3U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
11521 #define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
11522 #define RCC_CCIPR_UART5SEL_0 (0x1U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
11523 #define RCC_CCIPR_UART5SEL_1 (0x2U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
11524
11525 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
11526 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
11527 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
11528 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
11529 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
11530
11531 #define RCC_CCIPR_I2C1SEL_Pos (12U)
11532 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
11533 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
11534 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
11535 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
11536
11537 #define RCC_CCIPR_I2C2SEL_Pos (14U)
11538 #define RCC_CCIPR_I2C2SEL_Msk (0x3U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
11539 #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
11540 #define RCC_CCIPR_I2C2SEL_0 (0x1U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
11541 #define RCC_CCIPR_I2C2SEL_1 (0x2U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
11542
11543 #define RCC_CCIPR_I2C3SEL_Pos (16U)
11544 #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
11545 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
11546 #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
11547 #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
11548
11549 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
11550 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
11551 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
11552 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
11553 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
11554
11555 #define RCC_CCIPR_LPTIM2SEL_Pos (20U)
11556 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
11557 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
11558 #define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
11559 #define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
11560
11561 #define RCC_CCIPR_SAI1SEL_Pos (22U)
11562 #define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
11563 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
11564 #define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
11565 #define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
11566
11567 #define RCC_CCIPR_SAI2SEL_Pos (24U)
11568 #define RCC_CCIPR_SAI2SEL_Msk (0x3U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x03000000 */
11569 #define RCC_CCIPR_SAI2SEL RCC_CCIPR_SAI2SEL_Msk
11570 #define RCC_CCIPR_SAI2SEL_0 (0x1U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x01000000 */
11571 #define RCC_CCIPR_SAI2SEL_1 (0x2U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x02000000 */
11572
11573 #define RCC_CCIPR_CLK48SEL_Pos (26U)
11574 #define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
11575 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
11576 #define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
11577 #define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
11578
11579 #define RCC_CCIPR_ADCSEL_Pos (28U)
11580 #define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
11581 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
11582 #define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
11583 #define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
11584
11585 #define RCC_CCIPR_SWPMI1SEL_Pos (30U)
11586 #define RCC_CCIPR_SWPMI1SEL_Msk (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
11587 #define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
11588
11589 #define RCC_CCIPR_DFSDM1SEL_Pos (31U)
11590 #define RCC_CCIPR_DFSDM1SEL_Msk (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
11591 #define RCC_CCIPR_DFSDM1SEL RCC_CCIPR_DFSDM1SEL_Msk
11592
11593 /******************** Bit definition for RCC_BDCR register ******************/
11594 #define RCC_BDCR_LSEON_Pos (0U)
11595 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
11596 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11597 #define RCC_BDCR_LSERDY_Pos (1U)
11598 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
11599 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11600 #define RCC_BDCR_LSEBYP_Pos (2U)
11601 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
11602 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11603
11604 #define RCC_BDCR_LSEDRV_Pos (3U)
11605 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
11606 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
11607 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
11608 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
11609
11610 #define RCC_BDCR_LSECSSON_Pos (5U)
11611 #define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
11612 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
11613 #define RCC_BDCR_LSECSSD_Pos (6U)
11614 #define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
11615 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
11616
11617 #define RCC_BDCR_RTCSEL_Pos (8U)
11618 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
11619 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11620 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
11621 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
11622
11623 #define RCC_BDCR_RTCEN_Pos (15U)
11624 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
11625 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11626 #define RCC_BDCR_BDRST_Pos (16U)
11627 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
11628 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11629 #define RCC_BDCR_LSCOEN_Pos (24U)
11630 #define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
11631 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
11632 #define RCC_BDCR_LSCOSEL_Pos (25U)
11633 #define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
11634 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
11635
11636 /******************** Bit definition for RCC_CSR register *******************/
11637 #define RCC_CSR_LSION_Pos (0U)
11638 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
11639 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
11640 #define RCC_CSR_LSIRDY_Pos (1U)
11641 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
11642 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11643
11644 #define RCC_CSR_MSISRANGE_Pos (8U)
11645 #define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
11646 #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
11647 #define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
11648 #define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
11649 #define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
11650 #define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
11651
11652 #define RCC_CSR_RMVF_Pos (23U)
11653 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
11654 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11655 #define RCC_CSR_FWRSTF_Pos (24U)
11656 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
11657 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
11658 #define RCC_CSR_OBLRSTF_Pos (25U)
11659 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
11660 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
11661 #define RCC_CSR_PINRSTF_Pos (26U)
11662 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
11663 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11664 #define RCC_CSR_BORRSTF_Pos (27U)
11665 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
11666 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11667 #define RCC_CSR_SFTRSTF_Pos (28U)
11668 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
11669 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11670 #define RCC_CSR_IWDGRSTF_Pos (29U)
11671 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
11672 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11673 #define RCC_CSR_WWDGRSTF_Pos (30U)
11674 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
11675 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11676 #define RCC_CSR_LPWRRSTF_Pos (31U)
11677 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
11678 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11679
11680 /******************************************************************************/
11681 /* */
11682 /* RNG */
11683 /* */
11684 /******************************************************************************/
11685 /******************** Bits definition for RNG_CR register *******************/
11686 #define RNG_CR_RNGEN_Pos (2U)
11687 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
11688 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11689 #define RNG_CR_IE_Pos (3U)
11690 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
11691 #define RNG_CR_IE RNG_CR_IE_Msk
11692
11693 /******************** Bits definition for RNG_SR register *******************/
11694 #define RNG_SR_DRDY_Pos (0U)
11695 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
11696 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
11697 #define RNG_SR_CECS_Pos (1U)
11698 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
11699 #define RNG_SR_CECS RNG_SR_CECS_Msk
11700 #define RNG_SR_SECS_Pos (2U)
11701 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
11702 #define RNG_SR_SECS RNG_SR_SECS_Msk
11703 #define RNG_SR_CEIS_Pos (5U)
11704 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
11705 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
11706 #define RNG_SR_SEIS_Pos (6U)
11707 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
11708 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
11709
11710 /******************************************************************************/
11711 /* */
11712 /* Real-Time Clock (RTC) */
11713 /* */
11714 /******************************************************************************/
11715 /*
11716 * @brief Specific device feature definitions
11717 */
11718 #define RTC_TAMPER1_SUPPORT
11719 #define RTC_TAMPER2_SUPPORT
11720 #define RTC_TAMPER3_SUPPORT
11721 #define RTC_WAKEUP_SUPPORT
11722 #define RTC_BACKUP_SUPPORT
11723
11724 /******************** Bits definition for RTC_TR register *******************/
11725 #define RTC_TR_PM_Pos (22U)
11726 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
11727 #define RTC_TR_PM RTC_TR_PM_Msk
11728 #define RTC_TR_HT_Pos (20U)
11729 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
11730 #define RTC_TR_HT RTC_TR_HT_Msk
11731 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
11732 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
11733 #define RTC_TR_HU_Pos (16U)
11734 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
11735 #define RTC_TR_HU RTC_TR_HU_Msk
11736 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
11737 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
11738 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
11739 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
11740 #define RTC_TR_MNT_Pos (12U)
11741 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
11742 #define RTC_TR_MNT RTC_TR_MNT_Msk
11743 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
11744 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
11745 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
11746 #define RTC_TR_MNU_Pos (8U)
11747 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
11748 #define RTC_TR_MNU RTC_TR_MNU_Msk
11749 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
11750 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
11751 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
11752 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
11753 #define RTC_TR_ST_Pos (4U)
11754 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
11755 #define RTC_TR_ST RTC_TR_ST_Msk
11756 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
11757 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
11758 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
11759 #define RTC_TR_SU_Pos (0U)
11760 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
11761 #define RTC_TR_SU RTC_TR_SU_Msk
11762 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
11763 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
11764 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
11765 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
11766
11767 /******************** Bits definition for RTC_DR register *******************/
11768 #define RTC_DR_YT_Pos (20U)
11769 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
11770 #define RTC_DR_YT RTC_DR_YT_Msk
11771 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
11772 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
11773 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
11774 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
11775 #define RTC_DR_YU_Pos (16U)
11776 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
11777 #define RTC_DR_YU RTC_DR_YU_Msk
11778 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
11779 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
11780 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
11781 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
11782 #define RTC_DR_WDU_Pos (13U)
11783 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
11784 #define RTC_DR_WDU RTC_DR_WDU_Msk
11785 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
11786 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
11787 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
11788 #define RTC_DR_MT_Pos (12U)
11789 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
11790 #define RTC_DR_MT RTC_DR_MT_Msk
11791 #define RTC_DR_MU_Pos (8U)
11792 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
11793 #define RTC_DR_MU RTC_DR_MU_Msk
11794 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
11795 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
11796 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
11797 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
11798 #define RTC_DR_DT_Pos (4U)
11799 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
11800 #define RTC_DR_DT RTC_DR_DT_Msk
11801 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
11802 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
11803 #define RTC_DR_DU_Pos (0U)
11804 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
11805 #define RTC_DR_DU RTC_DR_DU_Msk
11806 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
11807 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
11808 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
11809 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
11810
11811 /******************** Bits definition for RTC_CR register *******************/
11812 #define RTC_CR_ITSE_Pos (24U)
11813 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
11814 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
11815 #define RTC_CR_COE_Pos (23U)
11816 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
11817 #define RTC_CR_COE RTC_CR_COE_Msk
11818 #define RTC_CR_OSEL_Pos (21U)
11819 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
11820 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
11821 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
11822 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
11823 #define RTC_CR_POL_Pos (20U)
11824 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
11825 #define RTC_CR_POL RTC_CR_POL_Msk
11826 #define RTC_CR_COSEL_Pos (19U)
11827 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
11828 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
11829 #define RTC_CR_BCK_Pos (18U)
11830 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
11831 #define RTC_CR_BCK RTC_CR_BCK_Msk
11832 #define RTC_CR_SUB1H_Pos (17U)
11833 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
11834 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11835 #define RTC_CR_ADD1H_Pos (16U)
11836 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
11837 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11838 #define RTC_CR_TSIE_Pos (15U)
11839 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
11840 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
11841 #define RTC_CR_WUTIE_Pos (14U)
11842 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
11843 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11844 #define RTC_CR_ALRBIE_Pos (13U)
11845 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
11846 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11847 #define RTC_CR_ALRAIE_Pos (12U)
11848 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
11849 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11850 #define RTC_CR_TSE_Pos (11U)
11851 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
11852 #define RTC_CR_TSE RTC_CR_TSE_Msk
11853 #define RTC_CR_WUTE_Pos (10U)
11854 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
11855 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
11856 #define RTC_CR_ALRBE_Pos (9U)
11857 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
11858 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11859 #define RTC_CR_ALRAE_Pos (8U)
11860 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
11861 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11862 #define RTC_CR_FMT_Pos (6U)
11863 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
11864 #define RTC_CR_FMT RTC_CR_FMT_Msk
11865 #define RTC_CR_BYPSHAD_Pos (5U)
11866 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
11867 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11868 #define RTC_CR_REFCKON_Pos (4U)
11869 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
11870 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11871 #define RTC_CR_TSEDGE_Pos (3U)
11872 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
11873 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11874 #define RTC_CR_WUCKSEL_Pos (0U)
11875 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
11876 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11877 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
11878 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
11879 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
11880
11881 /******************** Bits definition for RTC_ISR register ******************/
11882 #define RTC_ISR_ITSF_Pos (17U)
11883 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
11884 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
11885 #define RTC_ISR_RECALPF_Pos (16U)
11886 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
11887 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11888 #define RTC_ISR_TAMP3F_Pos (15U)
11889 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
11890 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
11891 #define RTC_ISR_TAMP2F_Pos (14U)
11892 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
11893 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11894 #define RTC_ISR_TAMP1F_Pos (13U)
11895 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
11896 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11897 #define RTC_ISR_TSOVF_Pos (12U)
11898 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
11899 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11900 #define RTC_ISR_TSF_Pos (11U)
11901 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
11902 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
11903 #define RTC_ISR_WUTF_Pos (10U)
11904 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
11905 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11906 #define RTC_ISR_ALRBF_Pos (9U)
11907 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
11908 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11909 #define RTC_ISR_ALRAF_Pos (8U)
11910 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
11911 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11912 #define RTC_ISR_INIT_Pos (7U)
11913 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
11914 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
11915 #define RTC_ISR_INITF_Pos (6U)
11916 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
11917 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
11918 #define RTC_ISR_RSF_Pos (5U)
11919 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
11920 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
11921 #define RTC_ISR_INITS_Pos (4U)
11922 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
11923 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
11924 #define RTC_ISR_SHPF_Pos (3U)
11925 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
11926 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11927 #define RTC_ISR_WUTWF_Pos (2U)
11928 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
11929 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11930 #define RTC_ISR_ALRBWF_Pos (1U)
11931 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
11932 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11933 #define RTC_ISR_ALRAWF_Pos (0U)
11934 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
11935 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11936
11937 /******************** Bits definition for RTC_PRER register *****************/
11938 #define RTC_PRER_PREDIV_A_Pos (16U)
11939 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
11940 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11941 #define RTC_PRER_PREDIV_S_Pos (0U)
11942 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
11943 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11944
11945 /******************** Bits definition for RTC_WUTR register *****************/
11946 #define RTC_WUTR_WUT_Pos (0U)
11947 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
11948 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11949
11950 /******************** Bits definition for RTC_ALRMAR register ***************/
11951 #define RTC_ALRMAR_MSK4_Pos (31U)
11952 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
11953 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11954 #define RTC_ALRMAR_WDSEL_Pos (30U)
11955 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
11956 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11957 #define RTC_ALRMAR_DT_Pos (28U)
11958 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
11959 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11960 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
11961 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
11962 #define RTC_ALRMAR_DU_Pos (24U)
11963 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
11964 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11965 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
11966 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
11967 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
11968 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
11969 #define RTC_ALRMAR_MSK3_Pos (23U)
11970 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
11971 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11972 #define RTC_ALRMAR_PM_Pos (22U)
11973 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
11974 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11975 #define RTC_ALRMAR_HT_Pos (20U)
11976 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
11977 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11978 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
11979 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
11980 #define RTC_ALRMAR_HU_Pos (16U)
11981 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
11982 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11983 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
11984 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
11985 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
11986 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
11987 #define RTC_ALRMAR_MSK2_Pos (15U)
11988 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
11989 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11990 #define RTC_ALRMAR_MNT_Pos (12U)
11991 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
11992 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11993 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
11994 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
11995 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
11996 #define RTC_ALRMAR_MNU_Pos (8U)
11997 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
11998 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11999 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
12000 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
12001 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
12002 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
12003 #define RTC_ALRMAR_MSK1_Pos (7U)
12004 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
12005 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
12006 #define RTC_ALRMAR_ST_Pos (4U)
12007 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
12008 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
12009 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
12010 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
12011 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
12012 #define RTC_ALRMAR_SU_Pos (0U)
12013 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
12014 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
12015 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
12016 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
12017 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
12018 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
12019
12020 /******************** Bits definition for RTC_ALRMBR register ***************/
12021 #define RTC_ALRMBR_MSK4_Pos (31U)
12022 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
12023 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
12024 #define RTC_ALRMBR_WDSEL_Pos (30U)
12025 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
12026 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
12027 #define RTC_ALRMBR_DT_Pos (28U)
12028 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
12029 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
12030 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
12031 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
12032 #define RTC_ALRMBR_DU_Pos (24U)
12033 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
12034 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
12035 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
12036 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
12037 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
12038 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
12039 #define RTC_ALRMBR_MSK3_Pos (23U)
12040 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
12041 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
12042 #define RTC_ALRMBR_PM_Pos (22U)
12043 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
12044 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
12045 #define RTC_ALRMBR_HT_Pos (20U)
12046 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
12047 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
12048 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
12049 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
12050 #define RTC_ALRMBR_HU_Pos (16U)
12051 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
12052 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
12053 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
12054 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
12055 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
12056 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
12057 #define RTC_ALRMBR_MSK2_Pos (15U)
12058 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
12059 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
12060 #define RTC_ALRMBR_MNT_Pos (12U)
12061 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
12062 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
12063 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
12064 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
12065 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
12066 #define RTC_ALRMBR_MNU_Pos (8U)
12067 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
12068 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
12069 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
12070 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
12071 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
12072 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
12073 #define RTC_ALRMBR_MSK1_Pos (7U)
12074 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
12075 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
12076 #define RTC_ALRMBR_ST_Pos (4U)
12077 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
12078 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
12079 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
12080 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
12081 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
12082 #define RTC_ALRMBR_SU_Pos (0U)
12083 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
12084 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
12085 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
12086 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
12087 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
12088 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
12089
12090 /******************** Bits definition for RTC_WPR register ******************/
12091 #define RTC_WPR_KEY_Pos (0U)
12092 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
12093 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
12094
12095 /******************** Bits definition for RTC_SSR register ******************/
12096 #define RTC_SSR_SS_Pos (0U)
12097 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
12098 #define RTC_SSR_SS RTC_SSR_SS_Msk
12099
12100 /******************** Bits definition for RTC_SHIFTR register ***************/
12101 #define RTC_SHIFTR_SUBFS_Pos (0U)
12102 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
12103 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12104 #define RTC_SHIFTR_ADD1S_Pos (31U)
12105 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
12106 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12107
12108 /******************** Bits definition for RTC_TSTR register *****************/
12109 #define RTC_TSTR_PM_Pos (22U)
12110 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
12111 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
12112 #define RTC_TSTR_HT_Pos (20U)
12113 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
12114 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
12115 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
12116 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
12117 #define RTC_TSTR_HU_Pos (16U)
12118 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
12119 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
12120 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
12121 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
12122 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
12123 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
12124 #define RTC_TSTR_MNT_Pos (12U)
12125 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
12126 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12127 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
12128 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
12129 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
12130 #define RTC_TSTR_MNU_Pos (8U)
12131 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
12132 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12133 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
12134 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
12135 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
12136 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
12137 #define RTC_TSTR_ST_Pos (4U)
12138 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
12139 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
12140 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
12141 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
12142 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
12143 #define RTC_TSTR_SU_Pos (0U)
12144 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
12145 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
12146 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
12147 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
12148 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
12149 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
12150
12151 /******************** Bits definition for RTC_TSDR register *****************/
12152 #define RTC_TSDR_WDU_Pos (13U)
12153 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
12154 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12155 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
12156 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
12157 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
12158 #define RTC_TSDR_MT_Pos (12U)
12159 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
12160 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
12161 #define RTC_TSDR_MU_Pos (8U)
12162 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
12163 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
12164 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
12165 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
12166 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
12167 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
12168 #define RTC_TSDR_DT_Pos (4U)
12169 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
12170 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
12171 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
12172 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
12173 #define RTC_TSDR_DU_Pos (0U)
12174 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
12175 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
12176 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
12177 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
12178 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
12179 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
12180
12181 /******************** Bits definition for RTC_TSSSR register ****************/
12182 #define RTC_TSSSR_SS_Pos (0U)
12183 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
12184 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12185
12186 /******************** Bits definition for RTC_CAL register *****************/
12187 #define RTC_CALR_CALP_Pos (15U)
12188 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
12189 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
12190 #define RTC_CALR_CALW8_Pos (14U)
12191 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
12192 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12193 #define RTC_CALR_CALW16_Pos (13U)
12194 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
12195 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12196 #define RTC_CALR_CALM_Pos (0U)
12197 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
12198 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
12199 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
12200 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
12201 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
12202 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
12203 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
12204 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
12205 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
12206 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
12207 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
12208
12209 /******************** Bits definition for RTC_TAMPCR register ***************/
12210 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
12211 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
12212 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
12213 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
12214 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
12215 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
12216 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
12217 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
12218 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
12219 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
12220 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
12221 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
12222 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
12223 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
12224 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
12225 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
12226 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
12227 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
12228 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
12229 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
12230 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
12231 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
12232 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
12233 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
12234 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
12235 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
12236 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
12237 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
12238 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
12239 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
12240 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
12241 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
12242 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
12243 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
12244 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
12245 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
12246 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
12247 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
12248 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
12249 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
12250 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
12251 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
12252 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
12253 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
12254 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
12255 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
12256 #define RTC_TAMPCR_TAMPTS_Pos (7U)
12257 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
12258 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
12259 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
12260 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
12261 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
12262 #define RTC_TAMPCR_TAMP3E_Pos (5U)
12263 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
12264 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
12265 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
12266 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
12267 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
12268 #define RTC_TAMPCR_TAMP2E_Pos (3U)
12269 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
12270 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
12271 #define RTC_TAMPCR_TAMPIE_Pos (2U)
12272 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
12273 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
12274 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
12275 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
12276 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
12277 #define RTC_TAMPCR_TAMP1E_Pos (0U)
12278 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
12279 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
12280
12281 /******************** Bits definition for RTC_ALRMASSR register *************/
12282 #define RTC_ALRMASSR_MASKSS_Pos (24U)
12283 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
12284 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12285 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
12286 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
12287 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
12288 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
12289 #define RTC_ALRMASSR_SS_Pos (0U)
12290 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
12291 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12292
12293 /******************** Bits definition for RTC_ALRMBSSR register *************/
12294 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
12295 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
12296 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12297 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
12298 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
12299 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
12300 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
12301 #define RTC_ALRMBSSR_SS_Pos (0U)
12302 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
12303 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12304
12305 /******************** Bits definition for RTC_0R register *******************/
12306 #define RTC_OR_OUT_RMP_Pos (1U)
12307 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
12308 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
12309 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
12310 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
12311 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
12312
12313
12314 /******************** Bits definition for RTC_BKP0R register ****************/
12315 #define RTC_BKP0R_Pos (0U)
12316 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
12317 #define RTC_BKP0R RTC_BKP0R_Msk
12318
12319 /******************** Bits definition for RTC_BKP1R register ****************/
12320 #define RTC_BKP1R_Pos (0U)
12321 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
12322 #define RTC_BKP1R RTC_BKP1R_Msk
12323
12324 /******************** Bits definition for RTC_BKP2R register ****************/
12325 #define RTC_BKP2R_Pos (0U)
12326 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
12327 #define RTC_BKP2R RTC_BKP2R_Msk
12328
12329 /******************** Bits definition for RTC_BKP3R register ****************/
12330 #define RTC_BKP3R_Pos (0U)
12331 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
12332 #define RTC_BKP3R RTC_BKP3R_Msk
12333
12334 /******************** Bits definition for RTC_BKP4R register ****************/
12335 #define RTC_BKP4R_Pos (0U)
12336 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
12337 #define RTC_BKP4R RTC_BKP4R_Msk
12338
12339 /******************** Bits definition for RTC_BKP5R register ****************/
12340 #define RTC_BKP5R_Pos (0U)
12341 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
12342 #define RTC_BKP5R RTC_BKP5R_Msk
12343
12344 /******************** Bits definition for RTC_BKP6R register ****************/
12345 #define RTC_BKP6R_Pos (0U)
12346 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
12347 #define RTC_BKP6R RTC_BKP6R_Msk
12348
12349 /******************** Bits definition for RTC_BKP7R register ****************/
12350 #define RTC_BKP7R_Pos (0U)
12351 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
12352 #define RTC_BKP7R RTC_BKP7R_Msk
12353
12354 /******************** Bits definition for RTC_BKP8R register ****************/
12355 #define RTC_BKP8R_Pos (0U)
12356 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
12357 #define RTC_BKP8R RTC_BKP8R_Msk
12358
12359 /******************** Bits definition for RTC_BKP9R register ****************/
12360 #define RTC_BKP9R_Pos (0U)
12361 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
12362 #define RTC_BKP9R RTC_BKP9R_Msk
12363
12364 /******************** Bits definition for RTC_BKP10R register ***************/
12365 #define RTC_BKP10R_Pos (0U)
12366 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
12367 #define RTC_BKP10R RTC_BKP10R_Msk
12368
12369 /******************** Bits definition for RTC_BKP11R register ***************/
12370 #define RTC_BKP11R_Pos (0U)
12371 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
12372 #define RTC_BKP11R RTC_BKP11R_Msk
12373
12374 /******************** Bits definition for RTC_BKP12R register ***************/
12375 #define RTC_BKP12R_Pos (0U)
12376 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
12377 #define RTC_BKP12R RTC_BKP12R_Msk
12378
12379 /******************** Bits definition for RTC_BKP13R register ***************/
12380 #define RTC_BKP13R_Pos (0U)
12381 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
12382 #define RTC_BKP13R RTC_BKP13R_Msk
12383
12384 /******************** Bits definition for RTC_BKP14R register ***************/
12385 #define RTC_BKP14R_Pos (0U)
12386 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
12387 #define RTC_BKP14R RTC_BKP14R_Msk
12388
12389 /******************** Bits definition for RTC_BKP15R register ***************/
12390 #define RTC_BKP15R_Pos (0U)
12391 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
12392 #define RTC_BKP15R RTC_BKP15R_Msk
12393
12394 /******************** Bits definition for RTC_BKP16R register ***************/
12395 #define RTC_BKP16R_Pos (0U)
12396 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
12397 #define RTC_BKP16R RTC_BKP16R_Msk
12398
12399 /******************** Bits definition for RTC_BKP17R register ***************/
12400 #define RTC_BKP17R_Pos (0U)
12401 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
12402 #define RTC_BKP17R RTC_BKP17R_Msk
12403
12404 /******************** Bits definition for RTC_BKP18R register ***************/
12405 #define RTC_BKP18R_Pos (0U)
12406 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
12407 #define RTC_BKP18R RTC_BKP18R_Msk
12408
12409 /******************** Bits definition for RTC_BKP19R register ***************/
12410 #define RTC_BKP19R_Pos (0U)
12411 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
12412 #define RTC_BKP19R RTC_BKP19R_Msk
12413
12414 /******************** Bits definition for RTC_BKP20R register ***************/
12415 #define RTC_BKP20R_Pos (0U)
12416 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
12417 #define RTC_BKP20R RTC_BKP20R_Msk
12418
12419 /******************** Bits definition for RTC_BKP21R register ***************/
12420 #define RTC_BKP21R_Pos (0U)
12421 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
12422 #define RTC_BKP21R RTC_BKP21R_Msk
12423
12424 /******************** Bits definition for RTC_BKP22R register ***************/
12425 #define RTC_BKP22R_Pos (0U)
12426 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
12427 #define RTC_BKP22R RTC_BKP22R_Msk
12428
12429 /******************** Bits definition for RTC_BKP23R register ***************/
12430 #define RTC_BKP23R_Pos (0U)
12431 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
12432 #define RTC_BKP23R RTC_BKP23R_Msk
12433
12434 /******************** Bits definition for RTC_BKP24R register ***************/
12435 #define RTC_BKP24R_Pos (0U)
12436 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
12437 #define RTC_BKP24R RTC_BKP24R_Msk
12438
12439 /******************** Bits definition for RTC_BKP25R register ***************/
12440 #define RTC_BKP25R_Pos (0U)
12441 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
12442 #define RTC_BKP25R RTC_BKP25R_Msk
12443
12444 /******************** Bits definition for RTC_BKP26R register ***************/
12445 #define RTC_BKP26R_Pos (0U)
12446 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
12447 #define RTC_BKP26R RTC_BKP26R_Msk
12448
12449 /******************** Bits definition for RTC_BKP27R register ***************/
12450 #define RTC_BKP27R_Pos (0U)
12451 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
12452 #define RTC_BKP27R RTC_BKP27R_Msk
12453
12454 /******************** Bits definition for RTC_BKP28R register ***************/
12455 #define RTC_BKP28R_Pos (0U)
12456 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
12457 #define RTC_BKP28R RTC_BKP28R_Msk
12458
12459 /******************** Bits definition for RTC_BKP29R register ***************/
12460 #define RTC_BKP29R_Pos (0U)
12461 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
12462 #define RTC_BKP29R RTC_BKP29R_Msk
12463
12464 /******************** Bits definition for RTC_BKP30R register ***************/
12465 #define RTC_BKP30R_Pos (0U)
12466 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
12467 #define RTC_BKP30R RTC_BKP30R_Msk
12468
12469 /******************** Bits definition for RTC_BKP31R register ***************/
12470 #define RTC_BKP31R_Pos (0U)
12471 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
12472 #define RTC_BKP31R RTC_BKP31R_Msk
12473
12474 /******************** Number of backup registers ******************************/
12475 #define RTC_BKP_NUMBER 32U
12476
12477 /******************************************************************************/
12478 /* */
12479 /* Serial Audio Interface */
12480 /* */
12481 /******************************************************************************/
12482 /******************** Bit definition for SAI_GCR register *******************/
12483 #define SAI_GCR_SYNCIN_Pos (0U)
12484 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
12485 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
12486 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
12487 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
12488
12489 #define SAI_GCR_SYNCOUT_Pos (4U)
12490 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
12491 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
12492 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
12493 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
12494
12495 /******************* Bit definition for SAI_xCR1 register *******************/
12496 #define SAI_xCR1_MODE_Pos (0U)
12497 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
12498 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
12499 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
12500 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
12501
12502 #define SAI_xCR1_PRTCFG_Pos (2U)
12503 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
12504 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
12505 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
12506 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
12507
12508 #define SAI_xCR1_DS_Pos (5U)
12509 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
12510 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
12511 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
12512 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
12513 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
12514
12515 #define SAI_xCR1_LSBFIRST_Pos (8U)
12516 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
12517 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
12518 #define SAI_xCR1_CKSTR_Pos (9U)
12519 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
12520 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
12521
12522 #define SAI_xCR1_SYNCEN_Pos (10U)
12523 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
12524 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
12525 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
12526 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
12527
12528 #define SAI_xCR1_MONO_Pos (12U)
12529 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
12530 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
12531 #define SAI_xCR1_OUTDRIV_Pos (13U)
12532 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
12533 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
12534 #define SAI_xCR1_SAIEN_Pos (16U)
12535 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
12536 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
12537 #define SAI_xCR1_DMAEN_Pos (17U)
12538 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
12539 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
12540 #define SAI_xCR1_NODIV_Pos (19U)
12541 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
12542 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
12543
12544 #define SAI_xCR1_MCKDIV_Pos (20U)
12545 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
12546 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
12547 #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
12548 #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
12549 #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
12550 #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
12551
12552 /******************* Bit definition for SAI_xCR2 register *******************/
12553 #define SAI_xCR2_FTH_Pos (0U)
12554 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
12555 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
12556 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
12557 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
12558 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
12559
12560 #define SAI_xCR2_FFLUSH_Pos (3U)
12561 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
12562 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
12563 #define SAI_xCR2_TRIS_Pos (4U)
12564 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
12565 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
12566 #define SAI_xCR2_MUTE_Pos (5U)
12567 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
12568 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
12569 #define SAI_xCR2_MUTEVAL_Pos (6U)
12570 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
12571 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
12572
12573
12574 #define SAI_xCR2_MUTECNT_Pos (7U)
12575 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
12576 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
12577 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
12578 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
12579 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
12580 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
12581 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
12582 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
12583
12584 #define SAI_xCR2_CPL_Pos (13U)
12585 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
12586 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
12587 #define SAI_xCR2_COMP_Pos (14U)
12588 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
12589 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
12590 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
12591 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
12592
12593
12594 /****************** Bit definition for SAI_xFRCR register *******************/
12595 #define SAI_xFRCR_FRL_Pos (0U)
12596 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
12597 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
12598 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
12599 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
12600 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
12601 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
12602 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
12603 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
12604 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
12605 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
12606
12607 #define SAI_xFRCR_FSALL_Pos (8U)
12608 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
12609 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
12610 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
12611 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
12612 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
12613 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
12614 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
12615 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
12616 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
12617
12618 #define SAI_xFRCR_FSDEF_Pos (16U)
12619 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
12620 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
12621 #define SAI_xFRCR_FSPOL_Pos (17U)
12622 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
12623 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
12624 #define SAI_xFRCR_FSOFF_Pos (18U)
12625 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
12626 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
12627
12628 /****************** Bit definition for SAI_xSLOTR register *******************/
12629 #define SAI_xSLOTR_FBOFF_Pos (0U)
12630 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
12631 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
12632 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
12633 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
12634 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
12635 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
12636 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
12637
12638 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
12639 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
12640 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
12641 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
12642 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
12643
12644 #define SAI_xSLOTR_NBSLOT_Pos (8U)
12645 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
12646 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
12647 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
12648 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
12649 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
12650 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
12651
12652 #define SAI_xSLOTR_SLOTEN_Pos (16U)
12653 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
12654 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
12655
12656 /******************* Bit definition for SAI_xIMR register *******************/
12657 #define SAI_xIMR_OVRUDRIE_Pos (0U)
12658 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
12659 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
12660 #define SAI_xIMR_MUTEDETIE_Pos (1U)
12661 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
12662 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
12663 #define SAI_xIMR_WCKCFGIE_Pos (2U)
12664 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
12665 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
12666 #define SAI_xIMR_FREQIE_Pos (3U)
12667 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
12668 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
12669 #define SAI_xIMR_CNRDYIE_Pos (4U)
12670 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
12671 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
12672 #define SAI_xIMR_AFSDETIE_Pos (5U)
12673 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
12674 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
12675 #define SAI_xIMR_LFSDETIE_Pos (6U)
12676 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
12677 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
12678
12679 /******************** Bit definition for SAI_xSR register *******************/
12680 #define SAI_xSR_OVRUDR_Pos (0U)
12681 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
12682 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
12683 #define SAI_xSR_MUTEDET_Pos (1U)
12684 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
12685 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
12686 #define SAI_xSR_WCKCFG_Pos (2U)
12687 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
12688 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
12689 #define SAI_xSR_FREQ_Pos (3U)
12690 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
12691 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
12692 #define SAI_xSR_CNRDY_Pos (4U)
12693 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
12694 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
12695 #define SAI_xSR_AFSDET_Pos (5U)
12696 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
12697 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
12698 #define SAI_xSR_LFSDET_Pos (6U)
12699 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
12700 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
12701
12702 #define SAI_xSR_FLVL_Pos (16U)
12703 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
12704 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
12705 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
12706 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
12707 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
12708
12709 /****************** Bit definition for SAI_xCLRFR register ******************/
12710 #define SAI_xCLRFR_COVRUDR_Pos (0U)
12711 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
12712 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
12713 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
12714 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
12715 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
12716 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
12717 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
12718 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
12719 #define SAI_xCLRFR_CFREQ_Pos (3U)
12720 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
12721 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
12722 #define SAI_xCLRFR_CCNRDY_Pos (4U)
12723 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
12724 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
12725 #define SAI_xCLRFR_CAFSDET_Pos (5U)
12726 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
12727 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
12728 #define SAI_xCLRFR_CLFSDET_Pos (6U)
12729 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
12730 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
12731
12732 /****************** Bit definition for SAI_xDR register ******************/
12733 #define SAI_xDR_DATA_Pos (0U)
12734 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
12735 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
12736
12737 /******************************************************************************/
12738 /* */
12739 /* LCD Controller (LCD) */
12740 /* */
12741 /******************************************************************************/
12742
12743 /******************* Bit definition for LCD_CR register *********************/
12744 #define LCD_CR_LCDEN_Pos (0U)
12745 #define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
12746 #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
12747 #define LCD_CR_VSEL_Pos (1U)
12748 #define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
12749 #define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
12750
12751 #define LCD_CR_DUTY_Pos (2U)
12752 #define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
12753 #define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
12754 #define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
12755 #define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
12756 #define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
12757
12758 #define LCD_CR_BIAS_Pos (5U)
12759 #define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
12760 #define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
12761 #define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
12762 #define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
12763
12764 #define LCD_CR_MUX_SEG_Pos (7U)
12765 #define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
12766 #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
12767 #define LCD_CR_BUFEN_Pos (8U)
12768 #define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
12769 #define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable */
12770
12771 /******************* Bit definition for LCD_FCR register ********************/
12772 #define LCD_FCR_HD_Pos (0U)
12773 #define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */
12774 #define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
12775 #define LCD_FCR_SOFIE_Pos (1U)
12776 #define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
12777 #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
12778 #define LCD_FCR_UDDIE_Pos (3U)
12779 #define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
12780 #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
12781
12782 #define LCD_FCR_PON_Pos (4U)
12783 #define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */
12784 #define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
12785 #define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */
12786 #define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */
12787 #define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */
12788
12789 #define LCD_FCR_DEAD_Pos (7U)
12790 #define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
12791 #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
12792 #define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
12793 #define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
12794 #define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
12795
12796 #define LCD_FCR_CC_Pos (10U)
12797 #define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
12798 #define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
12799 #define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */
12800 #define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */
12801 #define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */
12802
12803 #define LCD_FCR_BLINKF_Pos (13U)
12804 #define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
12805 #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
12806 #define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
12807 #define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
12808 #define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
12809
12810 #define LCD_FCR_BLINK_Pos (16U)
12811 #define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
12812 #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
12813 #define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
12814 #define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
12815
12816 #define LCD_FCR_DIV_Pos (18U)
12817 #define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
12818 #define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
12819 #define LCD_FCR_PS_Pos (22U)
12820 #define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
12821 #define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
12822
12823 /******************* Bit definition for LCD_SR register *********************/
12824 #define LCD_SR_ENS_Pos (0U)
12825 #define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */
12826 #define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
12827 #define LCD_SR_SOF_Pos (1U)
12828 #define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */
12829 #define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
12830 #define LCD_SR_UDR_Pos (2U)
12831 #define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */
12832 #define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
12833 #define LCD_SR_UDD_Pos (3U)
12834 #define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */
12835 #define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
12836 #define LCD_SR_RDY_Pos (4U)
12837 #define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */
12838 #define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
12839 #define LCD_SR_FCRSR_Pos (5U)
12840 #define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
12841 #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
12842
12843 /******************* Bit definition for LCD_CLR register ********************/
12844 #define LCD_CLR_SOFC_Pos (1U)
12845 #define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
12846 #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
12847 #define LCD_CLR_UDDC_Pos (3U)
12848 #define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
12849 #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
12850
12851 /******************* Bit definition for LCD_RAM register ********************/
12852 #define LCD_RAM_SEGMENT_DATA_Pos (0U)
12853 #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
12854 #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
12855
12856 /******************************************************************************/
12857 /* */
12858 /* SDMMC Interface */
12859 /* */
12860 /******************************************************************************/
12861 /****************** Bit definition for SDMMC_POWER register ******************/
12862 #define SDMMC_POWER_PWRCTRL_Pos (0U)
12863 #define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
12864 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
12865 #define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
12866 #define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
12867
12868 /****************** Bit definition for SDMMC_CLKCR register ******************/
12869 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
12870 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
12871 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
12872 #define SDMMC_CLKCR_CLKEN_Pos (8U)
12873 #define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
12874 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
12875 #define SDMMC_CLKCR_PWRSAV_Pos (9U)
12876 #define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
12877 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
12878 #define SDMMC_CLKCR_BYPASS_Pos (10U)
12879 #define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
12880 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
12881 #define SDMMC_CLKCR_WIDBUS_Pos (11U)
12882 #define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
12883 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
12884 #define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */
12885 #define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */
12886 #define SDMMC_CLKCR_NEGEDGE_Pos (13U)
12887 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
12888 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
12889 #define SDMMC_CLKCR_HWFC_EN_Pos (14U)
12890 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
12891 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
12892
12893 /******************* Bit definition for SDMMC_ARG register *******************/
12894 #define SDMMC_ARG_CMDARG_Pos (0U)
12895 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
12896 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
12897
12898 /******************* Bit definition for SDMMC_CMD register *******************/
12899 #define SDMMC_CMD_CMDINDEX_Pos (0U)
12900 #define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
12901 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
12902 #define SDMMC_CMD_WAITRESP_Pos (6U)
12903 #define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
12904 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
12905 #define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000040 */
12906 #define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000080 */
12907 #define SDMMC_CMD_WAITINT_Pos (8U)
12908 #define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
12909 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
12910 #define SDMMC_CMD_WAITPEND_Pos (9U)
12911 #define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
12912 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
12913 #define SDMMC_CMD_CPSMEN_Pos (10U)
12914 #define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
12915 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
12916 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
12917 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
12918 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
12919
12920 /***************** Bit definition for SDMMC_RESPCMD register *****************/
12921 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
12922 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
12923 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
12924
12925 /****************** Bit definition for SDMMC_RESP1 register ******************/
12926 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
12927 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
12928 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
12929
12930 /****************** Bit definition for SDMMC_RESP2 register ******************/
12931 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
12932 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
12933 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
12934
12935 /****************** Bit definition for SDMMC_RESP3 register ******************/
12936 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
12937 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
12938 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
12939
12940 /****************** Bit definition for SDMMC_RESP4 register ******************/
12941 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
12942 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
12943 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
12944
12945 /****************** Bit definition for SDMMC_DTIMER register *****************/
12946 #define SDMMC_DTIMER_DATATIME_Pos (0U)
12947 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
12948 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
12949
12950 /****************** Bit definition for SDMMC_DLEN register *******************/
12951 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
12952 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
12953 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
12954
12955 /****************** Bit definition for SDMMC_DCTRL register ******************/
12956 #define SDMMC_DCTRL_DTEN_Pos (0U)
12957 #define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
12958 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
12959 #define SDMMC_DCTRL_DTDIR_Pos (1U)
12960 #define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
12961 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
12962 #define SDMMC_DCTRL_DTMODE_Pos (2U)
12963 #define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
12964 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
12965 #define SDMMC_DCTRL_DMAEN_Pos (3U)
12966 #define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
12967 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
12968 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
12969 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
12970 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
12971 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
12972 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
12973 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
12974 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
12975 #define SDMMC_DCTRL_RWSTART_Pos (8U)
12976 #define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
12977 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
12978 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
12979 #define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
12980 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
12981 #define SDMMC_DCTRL_RWMOD_Pos (10U)
12982 #define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
12983 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
12984 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
12985 #define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
12986 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
12987
12988 /****************** Bit definition for SDMMC_DCOUNT register *****************/
12989 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
12990 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
12991 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
12992
12993 /****************** Bit definition for SDMMC_STA register ********************/
12994 #define SDMMC_STA_CCRCFAIL_Pos (0U)
12995 #define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
12996 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
12997 #define SDMMC_STA_DCRCFAIL_Pos (1U)
12998 #define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
12999 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
13000 #define SDMMC_STA_CTIMEOUT_Pos (2U)
13001 #define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
13002 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
13003 #define SDMMC_STA_DTIMEOUT_Pos (3U)
13004 #define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
13005 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
13006 #define SDMMC_STA_TXUNDERR_Pos (4U)
13007 #define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
13008 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
13009 #define SDMMC_STA_RXOVERR_Pos (5U)
13010 #define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
13011 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
13012 #define SDMMC_STA_CMDREND_Pos (6U)
13013 #define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
13014 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
13015 #define SDMMC_STA_CMDSENT_Pos (7U)
13016 #define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
13017 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
13018 #define SDMMC_STA_DATAEND_Pos (8U)
13019 #define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
13020 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
13021 #define SDMMC_STA_STBITERR_Pos (9U)
13022 #define SDMMC_STA_STBITERR_Msk (0x1U << SDMMC_STA_STBITERR_Pos) /*!< 0x00000200 */
13023 #define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
13024 #define SDMMC_STA_DBCKEND_Pos (10U)
13025 #define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
13026 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
13027 #define SDMMC_STA_CMDACT_Pos (11U)
13028 #define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
13029 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
13030 #define SDMMC_STA_TXACT_Pos (12U)
13031 #define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
13032 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
13033 #define SDMMC_STA_RXACT_Pos (13U)
13034 #define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
13035 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
13036 #define SDMMC_STA_TXFIFOHE_Pos (14U)
13037 #define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
13038 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
13039 #define SDMMC_STA_RXFIFOHF_Pos (15U)
13040 #define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
13041 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
13042 #define SDMMC_STA_TXFIFOF_Pos (16U)
13043 #define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
13044 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
13045 #define SDMMC_STA_RXFIFOF_Pos (17U)
13046 #define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
13047 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
13048 #define SDMMC_STA_TXFIFOE_Pos (18U)
13049 #define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
13050 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
13051 #define SDMMC_STA_RXFIFOE_Pos (19U)
13052 #define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
13053 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
13054 #define SDMMC_STA_TXDAVL_Pos (20U)
13055 #define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
13056 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
13057 #define SDMMC_STA_RXDAVL_Pos (21U)
13058 #define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
13059 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
13060 #define SDMMC_STA_SDIOIT_Pos (22U)
13061 #define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
13062 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
13063
13064 /******************* Bit definition for SDMMC_ICR register *******************/
13065 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
13066 #define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
13067 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
13068 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
13069 #define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13070 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
13071 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
13072 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
13073 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
13074 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
13075 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
13076 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
13077 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
13078 #define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
13079 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
13080 #define SDMMC_ICR_RXOVERRC_Pos (5U)
13081 #define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
13082 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
13083 #define SDMMC_ICR_CMDRENDC_Pos (6U)
13084 #define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
13085 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
13086 #define SDMMC_ICR_CMDSENTC_Pos (7U)
13087 #define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
13088 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
13089 #define SDMMC_ICR_DATAENDC_Pos (8U)
13090 #define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
13091 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
13092 #define SDMMC_ICR_STBITERRC_Pos (9U)
13093 #define SDMMC_ICR_STBITERRC_Msk (0x1U << SDMMC_ICR_STBITERRC_Pos) /*!< 0x00000200 */
13094 #define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
13095 #define SDMMC_ICR_DBCKENDC_Pos (10U)
13096 #define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
13097 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
13098 #define SDMMC_ICR_SDIOITC_Pos (22U)
13099 #define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
13100 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
13101
13102 /****************** Bit definition for SDMMC_MASK register *******************/
13103 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
13104 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
13105 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
13106 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
13107 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
13108 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
13109 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
13110 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
13111 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
13112 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
13113 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
13114 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
13115 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
13116 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
13117 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
13118 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
13119 #define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
13120 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
13121 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
13122 #define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
13123 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
13124 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
13125 #define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
13126 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
13127 #define SDMMC_MASK_DATAENDIE_Pos (8U)
13128 #define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
13129 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
13130 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
13131 #define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
13132 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
13133 #define SDMMC_MASK_CMDACTIE_Pos (11U)
13134 #define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
13135 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
13136 #define SDMMC_MASK_TXACTIE_Pos (12U)
13137 #define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
13138 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
13139 #define SDMMC_MASK_RXACTIE_Pos (13U)
13140 #define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
13141 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
13142 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
13143 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
13144 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
13145 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
13146 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
13147 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
13148 #define SDMMC_MASK_TXFIFOFIE_Pos (16U)
13149 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
13150 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
13151 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
13152 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
13153 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
13154 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
13155 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
13156 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
13157 #define SDMMC_MASK_RXFIFOEIE_Pos (19U)
13158 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
13159 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
13160 #define SDMMC_MASK_TXDAVLIE_Pos (20U)
13161 #define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
13162 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
13163 #define SDMMC_MASK_RXDAVLIE_Pos (21U)
13164 #define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
13165 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
13166 #define SDMMC_MASK_SDIOITIE_Pos (22U)
13167 #define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
13168 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
13169
13170 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
13171 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
13172 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
13173 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
13174
13175 /****************** Bit definition for SDMMC_FIFO register *******************/
13176 #define SDMMC_FIFO_FIFODATA_Pos (0U)
13177 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
13178 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
13179
13180 /******************************************************************************/
13181 /* */
13182 /* Serial Peripheral Interface (SPI) */
13183 /* */
13184 /******************************************************************************/
13185 /******************* Bit definition for SPI_CR1 register ********************/
13186 #define SPI_CR1_CPHA_Pos (0U)
13187 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
13188 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
13189 #define SPI_CR1_CPOL_Pos (1U)
13190 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
13191 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
13192 #define SPI_CR1_MSTR_Pos (2U)
13193 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
13194 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
13195
13196 #define SPI_CR1_BR_Pos (3U)
13197 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
13198 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
13199 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
13200 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
13201 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
13202
13203 #define SPI_CR1_SPE_Pos (6U)
13204 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
13205 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
13206 #define SPI_CR1_LSBFIRST_Pos (7U)
13207 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
13208 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
13209 #define SPI_CR1_SSI_Pos (8U)
13210 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
13211 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
13212 #define SPI_CR1_SSM_Pos (9U)
13213 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
13214 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
13215 #define SPI_CR1_RXONLY_Pos (10U)
13216 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
13217 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
13218 #define SPI_CR1_CRCL_Pos (11U)
13219 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
13220 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
13221 #define SPI_CR1_CRCNEXT_Pos (12U)
13222 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
13223 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
13224 #define SPI_CR1_CRCEN_Pos (13U)
13225 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
13226 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
13227 #define SPI_CR1_BIDIOE_Pos (14U)
13228 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
13229 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
13230 #define SPI_CR1_BIDIMODE_Pos (15U)
13231 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
13232 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
13233
13234 /******************* Bit definition for SPI_CR2 register ********************/
13235 #define SPI_CR2_RXDMAEN_Pos (0U)
13236 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
13237 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
13238 #define SPI_CR2_TXDMAEN_Pos (1U)
13239 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
13240 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
13241 #define SPI_CR2_SSOE_Pos (2U)
13242 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
13243 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
13244 #define SPI_CR2_NSSP_Pos (3U)
13245 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
13246 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
13247 #define SPI_CR2_FRF_Pos (4U)
13248 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
13249 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
13250 #define SPI_CR2_ERRIE_Pos (5U)
13251 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
13252 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
13253 #define SPI_CR2_RXNEIE_Pos (6U)
13254 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
13255 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
13256 #define SPI_CR2_TXEIE_Pos (7U)
13257 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
13258 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
13259 #define SPI_CR2_DS_Pos (8U)
13260 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
13261 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
13262 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
13263 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
13264 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
13265 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
13266 #define SPI_CR2_FRXTH_Pos (12U)
13267 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
13268 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
13269 #define SPI_CR2_LDMARX_Pos (13U)
13270 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
13271 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
13272 #define SPI_CR2_LDMATX_Pos (14U)
13273 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
13274 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
13275
13276 /******************** Bit definition for SPI_SR register ********************/
13277 #define SPI_SR_RXNE_Pos (0U)
13278 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
13279 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
13280 #define SPI_SR_TXE_Pos (1U)
13281 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
13282 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
13283 #define SPI_SR_CHSIDE_Pos (2U)
13284 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
13285 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
13286 #define SPI_SR_UDR_Pos (3U)
13287 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
13288 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
13289 #define SPI_SR_CRCERR_Pos (4U)
13290 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
13291 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
13292 #define SPI_SR_MODF_Pos (5U)
13293 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
13294 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
13295 #define SPI_SR_OVR_Pos (6U)
13296 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
13297 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
13298 #define SPI_SR_BSY_Pos (7U)
13299 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
13300 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
13301 #define SPI_SR_FRE_Pos (8U)
13302 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
13303 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
13304 #define SPI_SR_FRLVL_Pos (9U)
13305 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
13306 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
13307 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
13308 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
13309 #define SPI_SR_FTLVL_Pos (11U)
13310 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
13311 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
13312 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
13313 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
13314
13315 /******************** Bit definition for SPI_DR register ********************/
13316 #define SPI_DR_DR_Pos (0U)
13317 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
13318 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
13319
13320 /******************* Bit definition for SPI_CRCPR register ******************/
13321 #define SPI_CRCPR_CRCPOLY_Pos (0U)
13322 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
13323 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
13324
13325 /****************** Bit definition for SPI_RXCRCR register ******************/
13326 #define SPI_RXCRCR_RXCRC_Pos (0U)
13327 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
13328 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
13329
13330 /****************** Bit definition for SPI_TXCRCR register ******************/
13331 #define SPI_TXCRCR_TXCRC_Pos (0U)
13332 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
13333 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
13334
13335 /******************************************************************************/
13336 /* */
13337 /* QUADSPI */
13338 /* */
13339 /******************************************************************************/
13340 /***************** Bit definition for QUADSPI_CR register *******************/
13341 #define QUADSPI_CR_EN_Pos (0U)
13342 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
13343 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
13344 #define QUADSPI_CR_ABORT_Pos (1U)
13345 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
13346 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
13347 #define QUADSPI_CR_DMAEN_Pos (2U)
13348 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
13349 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
13350 #define QUADSPI_CR_TCEN_Pos (3U)
13351 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
13352 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
13353 #define QUADSPI_CR_SSHIFT_Pos (4U)
13354 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
13355 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
13356 #define QUADSPI_CR_FTHRES_Pos (8U)
13357 #define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
13358 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
13359 #define QUADSPI_CR_TEIE_Pos (16U)
13360 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
13361 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
13362 #define QUADSPI_CR_TCIE_Pos (17U)
13363 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
13364 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
13365 #define QUADSPI_CR_FTIE_Pos (18U)
13366 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
13367 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
13368 #define QUADSPI_CR_SMIE_Pos (19U)
13369 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
13370 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
13371 #define QUADSPI_CR_TOIE_Pos (20U)
13372 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
13373 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
13374 #define QUADSPI_CR_APMS_Pos (22U)
13375 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
13376 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
13377 #define QUADSPI_CR_PMM_Pos (23U)
13378 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
13379 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
13380 #define QUADSPI_CR_PRESCALER_Pos (24U)
13381 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
13382 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
13383
13384 /***************** Bit definition for QUADSPI_DCR register ******************/
13385 #define QUADSPI_DCR_CKMODE_Pos (0U)
13386 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
13387 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
13388 #define QUADSPI_DCR_CSHT_Pos (8U)
13389 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
13390 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
13391 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
13392 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
13393 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
13394 #define QUADSPI_DCR_FSIZE_Pos (16U)
13395 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
13396 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
13397
13398 /****************** Bit definition for QUADSPI_SR register *******************/
13399 #define QUADSPI_SR_TEF_Pos (0U)
13400 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
13401 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
13402 #define QUADSPI_SR_TCF_Pos (1U)
13403 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
13404 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
13405 #define QUADSPI_SR_FTF_Pos (2U)
13406 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
13407 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
13408 #define QUADSPI_SR_SMF_Pos (3U)
13409 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
13410 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
13411 #define QUADSPI_SR_TOF_Pos (4U)
13412 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
13413 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
13414 #define QUADSPI_SR_BUSY_Pos (5U)
13415 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
13416 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
13417 #define QUADSPI_SR_FLEVEL_Pos (8U)
13418 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
13419 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
13420
13421 /****************** Bit definition for QUADSPI_FCR register ******************/
13422 #define QUADSPI_FCR_CTEF_Pos (0U)
13423 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
13424 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
13425 #define QUADSPI_FCR_CTCF_Pos (1U)
13426 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
13427 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
13428 #define QUADSPI_FCR_CSMF_Pos (3U)
13429 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
13430 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
13431 #define QUADSPI_FCR_CTOF_Pos (4U)
13432 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
13433 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
13434
13435 /****************** Bit definition for QUADSPI_DLR register ******************/
13436 #define QUADSPI_DLR_DL_Pos (0U)
13437 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
13438 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
13439
13440 /****************** Bit definition for QUADSPI_CCR register ******************/
13441 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
13442 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
13443 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
13444 #define QUADSPI_CCR_IMODE_Pos (8U)
13445 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
13446 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
13447 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
13448 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
13449 #define QUADSPI_CCR_ADMODE_Pos (10U)
13450 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
13451 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
13452 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
13453 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
13454 #define QUADSPI_CCR_ADSIZE_Pos (12U)
13455 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
13456 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
13457 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
13458 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
13459 #define QUADSPI_CCR_ABMODE_Pos (14U)
13460 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
13461 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
13462 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
13463 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
13464 #define QUADSPI_CCR_ABSIZE_Pos (16U)
13465 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
13466 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
13467 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
13468 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
13469 #define QUADSPI_CCR_DCYC_Pos (18U)
13470 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
13471 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
13472 #define QUADSPI_CCR_DMODE_Pos (24U)
13473 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
13474 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
13475 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
13476 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
13477 #define QUADSPI_CCR_FMODE_Pos (26U)
13478 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
13479 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
13480 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
13481 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
13482 #define QUADSPI_CCR_SIOO_Pos (28U)
13483 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
13484 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
13485 #define QUADSPI_CCR_DDRM_Pos (31U)
13486 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
13487 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
13488
13489 /****************** Bit definition for QUADSPI_AR register *******************/
13490 #define QUADSPI_AR_ADDRESS_Pos (0U)
13491 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
13492 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
13493
13494 /****************** Bit definition for QUADSPI_ABR register ******************/
13495 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
13496 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
13497 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
13498
13499 /****************** Bit definition for QUADSPI_DR register *******************/
13500 #define QUADSPI_DR_DATA_Pos (0U)
13501 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
13502 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
13503
13504 /****************** Bit definition for QUADSPI_PSMKR register ****************/
13505 #define QUADSPI_PSMKR_MASK_Pos (0U)
13506 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
13507 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
13508
13509 /****************** Bit definition for QUADSPI_PSMAR register ****************/
13510 #define QUADSPI_PSMAR_MATCH_Pos (0U)
13511 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
13512 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
13513
13514 /****************** Bit definition for QUADSPI_PIR register *****************/
13515 #define QUADSPI_PIR_INTERVAL_Pos (0U)
13516 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
13517 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
13518
13519 /****************** Bit definition for QUADSPI_LPTR register *****************/
13520 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
13521 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
13522 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
13523
13524 /******************************************************************************/
13525 /* */
13526 /* SYSCFG */
13527 /* */
13528 /******************************************************************************/
13529 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
13530 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
13531 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
13532 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
13533 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
13534 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
13535 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
13536
13537 #define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
13538 #define SYSCFG_MEMRMP_FB_MODE_Msk (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
13539 #define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< Flash Bank mode selection */
13540
13541 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
13542 #define SYSCFG_CFGR1_FWDIS_Pos (0U)
13543 #define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
13544 #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
13545 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
13546 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
13547 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
13548 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
13549 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
13550 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
13551 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
13552 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
13553 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
13554 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
13555 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
13556 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
13557 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
13558 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
13559 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
13560 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
13561 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
13562 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
13563 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
13564 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
13565 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
13566 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
13567 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
13568 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
13569 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
13570 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
13571 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
13572 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
13573 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
13574 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
13575
13576 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13577 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13578 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
13579 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
13580 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13581 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
13582 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
13583 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13584 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
13585 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
13586 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13587 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
13588 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
13589
13590 /**
13591 * @brief EXTI0 configuration
13592 */
13593 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
13594 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
13595 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
13596 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
13597 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
13598 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
13599 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
13600 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
13601
13602 /**
13603 * @brief EXTI1 configuration
13604 */
13605 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
13606 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
13607 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
13608 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
13609 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
13610 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
13611 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
13612 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
13613
13614 /**
13615 * @brief EXTI2 configuration
13616 */
13617 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
13618 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
13619 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
13620 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
13621 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
13622 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
13623 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
13624
13625 /**
13626 * @brief EXTI3 configuration
13627 */
13628 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
13629 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
13630 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
13631 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
13632 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
13633 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
13634 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
13635
13636 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13637 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13638 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
13639 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
13640 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13641 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
13642 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
13643 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13644 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
13645 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
13646 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13647 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
13648 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
13649 /**
13650 * @brief EXTI4 configuration
13651 */
13652 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
13653 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
13654 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
13655 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
13656 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
13657 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
13658 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
13659
13660 /**
13661 * @brief EXTI5 configuration
13662 */
13663 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
13664 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
13665 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
13666 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
13667 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
13668 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
13669 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
13670
13671 /**
13672 * @brief EXTI6 configuration
13673 */
13674 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
13675 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
13676 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
13677 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
13678 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
13679 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
13680 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
13681
13682 /**
13683 * @brief EXTI7 configuration
13684 */
13685 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
13686 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
13687 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
13688 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
13689 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
13690 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
13691 #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
13692
13693 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13694 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13695 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
13696 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
13697 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13698 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
13699 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
13700 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13701 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
13702 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
13703 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13704 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
13705 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
13706
13707 /**
13708 * @brief EXTI8 configuration
13709 */
13710 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
13711 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
13712 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
13713 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
13714 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
13715 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
13716 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
13717
13718 /**
13719 * @brief EXTI9 configuration
13720 */
13721 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
13722 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
13723 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
13724 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
13725 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
13726 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
13727 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
13728
13729 /**
13730 * @brief EXTI10 configuration
13731 */
13732 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
13733 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
13734 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
13735 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
13736 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
13737 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
13738 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
13739
13740 /**
13741 * @brief EXTI11 configuration
13742 */
13743 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
13744 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
13745 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
13746 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
13747 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
13748 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
13749 #define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
13750
13751 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13752 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13753 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
13754 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
13755 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13756 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
13757 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
13758 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13759 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
13760 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
13761 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13762 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
13763 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
13764
13765 /**
13766 * @brief EXTI12 configuration
13767 */
13768 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
13769 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
13770 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
13771 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
13772 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
13773 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
13774 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
13775
13776 /**
13777 * @brief EXTI13 configuration
13778 */
13779 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
13780 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
13781 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
13782 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
13783 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
13784 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
13785 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
13786
13787 /**
13788 * @brief EXTI14 configuration
13789 */
13790 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
13791 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
13792 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
13793 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
13794 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
13795 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
13796 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
13797
13798 /**
13799 * @brief EXTI15 configuration
13800 */
13801 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
13802 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
13803 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
13804 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
13805 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
13806 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
13807 #define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
13808
13809 /****************** Bit definition for SYSCFG_SCSR register ****************/
13810 #define SYSCFG_SCSR_SRAM2ER_Pos (0U)
13811 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
13812 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
13813 #define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
13814 #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
13815 #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
13816
13817 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
13818 #define SYSCFG_CFGR2_CLL_Pos (0U)
13819 #define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
13820 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
13821 #define SYSCFG_CFGR2_SPL_Pos (1U)
13822 #define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
13823 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
13824 #define SYSCFG_CFGR2_PVDL_Pos (2U)
13825 #define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
13826 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
13827 #define SYSCFG_CFGR2_ECCL_Pos (3U)
13828 #define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
13829 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
13830 #define SYSCFG_CFGR2_SPF_Pos (8U)
13831 #define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
13832 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
13833
13834 /****************** Bit definition for SYSCFG_SWPR register ****************/
13835 #define SYSCFG_SWPR_PAGE0_Pos (0U)
13836 #define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
13837 #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
13838 #define SYSCFG_SWPR_PAGE1_Pos (1U)
13839 #define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
13840 #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
13841 #define SYSCFG_SWPR_PAGE2_Pos (2U)
13842 #define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
13843 #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
13844 #define SYSCFG_SWPR_PAGE3_Pos (3U)
13845 #define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
13846 #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
13847 #define SYSCFG_SWPR_PAGE4_Pos (4U)
13848 #define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
13849 #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
13850 #define SYSCFG_SWPR_PAGE5_Pos (5U)
13851 #define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
13852 #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
13853 #define SYSCFG_SWPR_PAGE6_Pos (6U)
13854 #define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
13855 #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
13856 #define SYSCFG_SWPR_PAGE7_Pos (7U)
13857 #define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
13858 #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
13859 #define SYSCFG_SWPR_PAGE8_Pos (8U)
13860 #define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
13861 #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
13862 #define SYSCFG_SWPR_PAGE9_Pos (9U)
13863 #define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
13864 #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
13865 #define SYSCFG_SWPR_PAGE10_Pos (10U)
13866 #define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
13867 #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
13868 #define SYSCFG_SWPR_PAGE11_Pos (11U)
13869 #define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
13870 #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
13871 #define SYSCFG_SWPR_PAGE12_Pos (12U)
13872 #define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
13873 #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
13874 #define SYSCFG_SWPR_PAGE13_Pos (13U)
13875 #define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
13876 #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
13877 #define SYSCFG_SWPR_PAGE14_Pos (14U)
13878 #define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
13879 #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
13880 #define SYSCFG_SWPR_PAGE15_Pos (15U)
13881 #define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
13882 #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
13883 #define SYSCFG_SWPR_PAGE16_Pos (16U)
13884 #define SYSCFG_SWPR_PAGE16_Msk (0x1U << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
13885 #define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16*/
13886 #define SYSCFG_SWPR_PAGE17_Pos (17U)
13887 #define SYSCFG_SWPR_PAGE17_Msk (0x1U << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
13888 #define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17*/
13889 #define SYSCFG_SWPR_PAGE18_Pos (18U)
13890 #define SYSCFG_SWPR_PAGE18_Msk (0x1U << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
13891 #define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18*/
13892 #define SYSCFG_SWPR_PAGE19_Pos (19U)
13893 #define SYSCFG_SWPR_PAGE19_Msk (0x1U << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
13894 #define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19*/
13895 #define SYSCFG_SWPR_PAGE20_Pos (20U)
13896 #define SYSCFG_SWPR_PAGE20_Msk (0x1U << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
13897 #define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20*/
13898 #define SYSCFG_SWPR_PAGE21_Pos (21U)
13899 #define SYSCFG_SWPR_PAGE21_Msk (0x1U << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
13900 #define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21*/
13901 #define SYSCFG_SWPR_PAGE22_Pos (22U)
13902 #define SYSCFG_SWPR_PAGE22_Msk (0x1U << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
13903 #define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22*/
13904 #define SYSCFG_SWPR_PAGE23_Pos (23U)
13905 #define SYSCFG_SWPR_PAGE23_Msk (0x1U << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
13906 #define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23*/
13907 #define SYSCFG_SWPR_PAGE24_Pos (24U)
13908 #define SYSCFG_SWPR_PAGE24_Msk (0x1U << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
13909 #define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24*/
13910 #define SYSCFG_SWPR_PAGE25_Pos (25U)
13911 #define SYSCFG_SWPR_PAGE25_Msk (0x1U << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
13912 #define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25*/
13913 #define SYSCFG_SWPR_PAGE26_Pos (26U)
13914 #define SYSCFG_SWPR_PAGE26_Msk (0x1U << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
13915 #define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26*/
13916 #define SYSCFG_SWPR_PAGE27_Pos (27U)
13917 #define SYSCFG_SWPR_PAGE27_Msk (0x1U << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
13918 #define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27*/
13919 #define SYSCFG_SWPR_PAGE28_Pos (28U)
13920 #define SYSCFG_SWPR_PAGE28_Msk (0x1U << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
13921 #define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28*/
13922 #define SYSCFG_SWPR_PAGE29_Pos (29U)
13923 #define SYSCFG_SWPR_PAGE29_Msk (0x1U << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
13924 #define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29*/
13925 #define SYSCFG_SWPR_PAGE30_Pos (30U)
13926 #define SYSCFG_SWPR_PAGE30_Msk (0x1U << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
13927 #define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30*/
13928 #define SYSCFG_SWPR_PAGE31_Pos (31U)
13929 #define SYSCFG_SWPR_PAGE31_Msk (0x1U << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
13930 #define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31*/
13931
13932 /****************** Bit definition for SYSCFG_SKR register ****************/
13933 #define SYSCFG_SKR_KEY_Pos (0U)
13934 #define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
13935 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
13936
13937
13938
13939
13940 /******************************************************************************/
13941 /* */
13942 /* TIM */
13943 /* */
13944 /******************************************************************************/
13945 /******************* Bit definition for TIM_CR1 register ********************/
13946 #define TIM_CR1_CEN_Pos (0U)
13947 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
13948 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
13949 #define TIM_CR1_UDIS_Pos (1U)
13950 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
13951 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
13952 #define TIM_CR1_URS_Pos (2U)
13953 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
13954 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
13955 #define TIM_CR1_OPM_Pos (3U)
13956 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
13957 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
13958 #define TIM_CR1_DIR_Pos (4U)
13959 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
13960 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
13961
13962 #define TIM_CR1_CMS_Pos (5U)
13963 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
13964 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
13965 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
13966 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
13967
13968 #define TIM_CR1_ARPE_Pos (7U)
13969 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
13970 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
13971
13972 #define TIM_CR1_CKD_Pos (8U)
13973 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
13974 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
13975 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
13976 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
13977
13978 #define TIM_CR1_UIFREMAP_Pos (11U)
13979 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
13980 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
13981
13982 /******************* Bit definition for TIM_CR2 register ********************/
13983 #define TIM_CR2_CCPC_Pos (0U)
13984 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
13985 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
13986 #define TIM_CR2_CCUS_Pos (2U)
13987 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
13988 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
13989 #define TIM_CR2_CCDS_Pos (3U)
13990 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
13991 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
13992
13993 #define TIM_CR2_MMS_Pos (4U)
13994 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
13995 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
13996 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
13997 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
13998 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
13999
14000 #define TIM_CR2_TI1S_Pos (7U)
14001 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
14002 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
14003 #define TIM_CR2_OIS1_Pos (8U)
14004 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
14005 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
14006 #define TIM_CR2_OIS1N_Pos (9U)
14007 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
14008 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
14009 #define TIM_CR2_OIS2_Pos (10U)
14010 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
14011 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
14012 #define TIM_CR2_OIS2N_Pos (11U)
14013 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
14014 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
14015 #define TIM_CR2_OIS3_Pos (12U)
14016 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
14017 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
14018 #define TIM_CR2_OIS3N_Pos (13U)
14019 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
14020 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
14021 #define TIM_CR2_OIS4_Pos (14U)
14022 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
14023 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
14024 #define TIM_CR2_OIS5_Pos (16U)
14025 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
14026 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
14027 #define TIM_CR2_OIS6_Pos (18U)
14028 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
14029 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
14030
14031 #define TIM_CR2_MMS2_Pos (20U)
14032 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
14033 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
14034 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
14035 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
14036 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
14037 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
14038
14039 /******************* Bit definition for TIM_SMCR register *******************/
14040 #define TIM_SMCR_SMS_Pos (0U)
14041 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
14042 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
14043 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
14044 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
14045 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
14046 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
14047
14048 #define TIM_SMCR_OCCS_Pos (3U)
14049 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
14050 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
14051
14052 #define TIM_SMCR_TS_Pos (4U)
14053 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
14054 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
14055 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
14056 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
14057 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
14058
14059 #define TIM_SMCR_MSM_Pos (7U)
14060 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
14061 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
14062
14063 #define TIM_SMCR_ETF_Pos (8U)
14064 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
14065 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
14066 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
14067 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
14068 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
14069 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
14070
14071 #define TIM_SMCR_ETPS_Pos (12U)
14072 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
14073 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
14074 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
14075 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
14076
14077 #define TIM_SMCR_ECE_Pos (14U)
14078 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
14079 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
14080 #define TIM_SMCR_ETP_Pos (15U)
14081 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
14082 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
14083
14084 /******************* Bit definition for TIM_DIER register *******************/
14085 #define TIM_DIER_UIE_Pos (0U)
14086 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
14087 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
14088 #define TIM_DIER_CC1IE_Pos (1U)
14089 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
14090 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
14091 #define TIM_DIER_CC2IE_Pos (2U)
14092 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
14093 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
14094 #define TIM_DIER_CC3IE_Pos (3U)
14095 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
14096 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
14097 #define TIM_DIER_CC4IE_Pos (4U)
14098 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
14099 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
14100 #define TIM_DIER_COMIE_Pos (5U)
14101 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
14102 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
14103 #define TIM_DIER_TIE_Pos (6U)
14104 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
14105 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
14106 #define TIM_DIER_BIE_Pos (7U)
14107 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
14108 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
14109 #define TIM_DIER_UDE_Pos (8U)
14110 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
14111 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
14112 #define TIM_DIER_CC1DE_Pos (9U)
14113 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
14114 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
14115 #define TIM_DIER_CC2DE_Pos (10U)
14116 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
14117 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
14118 #define TIM_DIER_CC3DE_Pos (11U)
14119 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
14120 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
14121 #define TIM_DIER_CC4DE_Pos (12U)
14122 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
14123 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
14124 #define TIM_DIER_COMDE_Pos (13U)
14125 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
14126 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
14127 #define TIM_DIER_TDE_Pos (14U)
14128 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
14129 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
14130
14131 /******************** Bit definition for TIM_SR register ********************/
14132 #define TIM_SR_UIF_Pos (0U)
14133 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
14134 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
14135 #define TIM_SR_CC1IF_Pos (1U)
14136 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
14137 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
14138 #define TIM_SR_CC2IF_Pos (2U)
14139 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
14140 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
14141 #define TIM_SR_CC3IF_Pos (3U)
14142 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
14143 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
14144 #define TIM_SR_CC4IF_Pos (4U)
14145 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
14146 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
14147 #define TIM_SR_COMIF_Pos (5U)
14148 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
14149 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
14150 #define TIM_SR_TIF_Pos (6U)
14151 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
14152 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
14153 #define TIM_SR_BIF_Pos (7U)
14154 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
14155 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
14156 #define TIM_SR_B2IF_Pos (8U)
14157 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
14158 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
14159 #define TIM_SR_CC1OF_Pos (9U)
14160 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
14161 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
14162 #define TIM_SR_CC2OF_Pos (10U)
14163 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
14164 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
14165 #define TIM_SR_CC3OF_Pos (11U)
14166 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
14167 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
14168 #define TIM_SR_CC4OF_Pos (12U)
14169 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
14170 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
14171 #define TIM_SR_SBIF_Pos (13U)
14172 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
14173 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
14174 #define TIM_SR_CC5IF_Pos (16U)
14175 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
14176 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
14177 #define TIM_SR_CC6IF_Pos (17U)
14178 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
14179 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
14180
14181
14182 /******************* Bit definition for TIM_EGR register ********************/
14183 #define TIM_EGR_UG_Pos (0U)
14184 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
14185 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
14186 #define TIM_EGR_CC1G_Pos (1U)
14187 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
14188 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
14189 #define TIM_EGR_CC2G_Pos (2U)
14190 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
14191 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
14192 #define TIM_EGR_CC3G_Pos (3U)
14193 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
14194 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
14195 #define TIM_EGR_CC4G_Pos (4U)
14196 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
14197 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
14198 #define TIM_EGR_COMG_Pos (5U)
14199 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
14200 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
14201 #define TIM_EGR_TG_Pos (6U)
14202 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
14203 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
14204 #define TIM_EGR_BG_Pos (7U)
14205 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
14206 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
14207 #define TIM_EGR_B2G_Pos (8U)
14208 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
14209 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
14210
14211
14212 /****************** Bit definition for TIM_CCMR1 register *******************/
14213 #define TIM_CCMR1_CC1S_Pos (0U)
14214 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
14215 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
14216 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
14217 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
14218
14219 #define TIM_CCMR1_OC1FE_Pos (2U)
14220 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
14221 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
14222 #define TIM_CCMR1_OC1PE_Pos (3U)
14223 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
14224 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
14225
14226 #define TIM_CCMR1_OC1M_Pos (4U)
14227 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
14228 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
14229 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
14230 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
14231 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
14232 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
14233
14234 #define TIM_CCMR1_OC1CE_Pos (7U)
14235 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
14236 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
14237
14238 #define TIM_CCMR1_CC2S_Pos (8U)
14239 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
14240 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
14241 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
14242 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
14243
14244 #define TIM_CCMR1_OC2FE_Pos (10U)
14245 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
14246 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
14247 #define TIM_CCMR1_OC2PE_Pos (11U)
14248 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
14249 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
14250
14251 #define TIM_CCMR1_OC2M_Pos (12U)
14252 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
14253 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
14254 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
14255 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
14256 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
14257 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
14258
14259 #define TIM_CCMR1_OC2CE_Pos (15U)
14260 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
14261 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
14262
14263 /*----------------------------------------------------------------------------*/
14264 #define TIM_CCMR1_IC1PSC_Pos (2U)
14265 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
14266 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
14267 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
14268 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
14269
14270 #define TIM_CCMR1_IC1F_Pos (4U)
14271 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
14272 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
14273 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
14274 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
14275 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
14276 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
14277
14278 #define TIM_CCMR1_IC2PSC_Pos (10U)
14279 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
14280 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
14281 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
14282 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
14283
14284 #define TIM_CCMR1_IC2F_Pos (12U)
14285 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
14286 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
14287 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
14288 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
14289 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
14290 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
14291
14292 /****************** Bit definition for TIM_CCMR2 register *******************/
14293 #define TIM_CCMR2_CC3S_Pos (0U)
14294 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
14295 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
14296 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
14297 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
14298
14299 #define TIM_CCMR2_OC3FE_Pos (2U)
14300 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
14301 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
14302 #define TIM_CCMR2_OC3PE_Pos (3U)
14303 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
14304 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
14305
14306 #define TIM_CCMR2_OC3M_Pos (4U)
14307 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
14308 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
14309 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
14310 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
14311 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
14312 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
14313
14314 #define TIM_CCMR2_OC3CE_Pos (7U)
14315 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
14316 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
14317
14318 #define TIM_CCMR2_CC4S_Pos (8U)
14319 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
14320 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
14321 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
14322 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
14323
14324 #define TIM_CCMR2_OC4FE_Pos (10U)
14325 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
14326 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
14327 #define TIM_CCMR2_OC4PE_Pos (11U)
14328 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
14329 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
14330
14331 #define TIM_CCMR2_OC4M_Pos (12U)
14332 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
14333 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
14334 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
14335 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
14336 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
14337 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
14338
14339 #define TIM_CCMR2_OC4CE_Pos (15U)
14340 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
14341 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
14342
14343 /*----------------------------------------------------------------------------*/
14344 #define TIM_CCMR2_IC3PSC_Pos (2U)
14345 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
14346 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
14347 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
14348 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
14349
14350 #define TIM_CCMR2_IC3F_Pos (4U)
14351 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
14352 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
14353 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
14354 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
14355 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
14356 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
14357
14358 #define TIM_CCMR2_IC4PSC_Pos (10U)
14359 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
14360 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
14361 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
14362 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
14363
14364 #define TIM_CCMR2_IC4F_Pos (12U)
14365 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
14366 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
14367 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
14368 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
14369 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
14370 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
14371
14372 /****************** Bit definition for TIM_CCMR3 register *******************/
14373 #define TIM_CCMR3_OC5FE_Pos (2U)
14374 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
14375 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
14376 #define TIM_CCMR3_OC5PE_Pos (3U)
14377 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
14378 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
14379
14380 #define TIM_CCMR3_OC5M_Pos (4U)
14381 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
14382 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
14383 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
14384 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
14385 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
14386 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
14387
14388 #define TIM_CCMR3_OC5CE_Pos (7U)
14389 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
14390 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
14391
14392 #define TIM_CCMR3_OC6FE_Pos (10U)
14393 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
14394 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
14395 #define TIM_CCMR3_OC6PE_Pos (11U)
14396 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
14397 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
14398
14399 #define TIM_CCMR3_OC6M_Pos (12U)
14400 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
14401 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
14402 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
14403 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
14404 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
14405 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
14406
14407 #define TIM_CCMR3_OC6CE_Pos (15U)
14408 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
14409 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
14410
14411 /******************* Bit definition for TIM_CCER register *******************/
14412 #define TIM_CCER_CC1E_Pos (0U)
14413 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
14414 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
14415 #define TIM_CCER_CC1P_Pos (1U)
14416 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
14417 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
14418 #define TIM_CCER_CC1NE_Pos (2U)
14419 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
14420 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
14421 #define TIM_CCER_CC1NP_Pos (3U)
14422 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
14423 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
14424 #define TIM_CCER_CC2E_Pos (4U)
14425 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
14426 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
14427 #define TIM_CCER_CC2P_Pos (5U)
14428 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
14429 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
14430 #define TIM_CCER_CC2NE_Pos (6U)
14431 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
14432 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
14433 #define TIM_CCER_CC2NP_Pos (7U)
14434 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
14435 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
14436 #define TIM_CCER_CC3E_Pos (8U)
14437 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
14438 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
14439 #define TIM_CCER_CC3P_Pos (9U)
14440 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
14441 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
14442 #define TIM_CCER_CC3NE_Pos (10U)
14443 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
14444 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
14445 #define TIM_CCER_CC3NP_Pos (11U)
14446 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
14447 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
14448 #define TIM_CCER_CC4E_Pos (12U)
14449 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
14450 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
14451 #define TIM_CCER_CC4P_Pos (13U)
14452 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
14453 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
14454 #define TIM_CCER_CC4NP_Pos (15U)
14455 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
14456 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
14457 #define TIM_CCER_CC5E_Pos (16U)
14458 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
14459 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
14460 #define TIM_CCER_CC5P_Pos (17U)
14461 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
14462 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
14463 #define TIM_CCER_CC6E_Pos (20U)
14464 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
14465 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
14466 #define TIM_CCER_CC6P_Pos (21U)
14467 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
14468 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
14469
14470 /******************* Bit definition for TIM_CNT register ********************/
14471 #define TIM_CNT_CNT_Pos (0U)
14472 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
14473 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
14474 #define TIM_CNT_UIFCPY_Pos (31U)
14475 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
14476 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
14477
14478 /******************* Bit definition for TIM_PSC register ********************/
14479 #define TIM_PSC_PSC_Pos (0U)
14480 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
14481 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
14482
14483 /******************* Bit definition for TIM_ARR register ********************/
14484 #define TIM_ARR_ARR_Pos (0U)
14485 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
14486 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
14487
14488 /******************* Bit definition for TIM_RCR register ********************/
14489 #define TIM_RCR_REP_Pos (0U)
14490 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
14491 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
14492
14493 /******************* Bit definition for TIM_CCR1 register *******************/
14494 #define TIM_CCR1_CCR1_Pos (0U)
14495 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
14496 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
14497
14498 /******************* Bit definition for TIM_CCR2 register *******************/
14499 #define TIM_CCR2_CCR2_Pos (0U)
14500 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
14501 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
14502
14503 /******************* Bit definition for TIM_CCR3 register *******************/
14504 #define TIM_CCR3_CCR3_Pos (0U)
14505 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
14506 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
14507
14508 /******************* Bit definition for TIM_CCR4 register *******************/
14509 #define TIM_CCR4_CCR4_Pos (0U)
14510 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
14511 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
14512
14513 /******************* Bit definition for TIM_CCR5 register *******************/
14514 #define TIM_CCR5_CCR5_Pos (0U)
14515 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14516 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
14517 #define TIM_CCR5_GC5C1_Pos (29U)
14518 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
14519 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
14520 #define TIM_CCR5_GC5C2_Pos (30U)
14521 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
14522 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
14523 #define TIM_CCR5_GC5C3_Pos (31U)
14524 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
14525 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
14526
14527 /******************* Bit definition for TIM_CCR6 register *******************/
14528 #define TIM_CCR6_CCR6_Pos (0U)
14529 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
14530 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
14531
14532 /******************* Bit definition for TIM_BDTR register *******************/
14533 #define TIM_BDTR_DTG_Pos (0U)
14534 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
14535 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
14536 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
14537 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
14538 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
14539 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
14540 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
14541 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
14542 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
14543 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
14544
14545 #define TIM_BDTR_LOCK_Pos (8U)
14546 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
14547 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
14548 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
14549 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
14550
14551 #define TIM_BDTR_OSSI_Pos (10U)
14552 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
14553 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
14554 #define TIM_BDTR_OSSR_Pos (11U)
14555 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
14556 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
14557 #define TIM_BDTR_BKE_Pos (12U)
14558 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
14559 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
14560 #define TIM_BDTR_BKP_Pos (13U)
14561 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
14562 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
14563 #define TIM_BDTR_AOE_Pos (14U)
14564 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
14565 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
14566 #define TIM_BDTR_MOE_Pos (15U)
14567 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
14568 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
14569
14570 #define TIM_BDTR_BKF_Pos (16U)
14571 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
14572 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
14573 #define TIM_BDTR_BK2F_Pos (20U)
14574 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
14575 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
14576
14577 #define TIM_BDTR_BK2E_Pos (24U)
14578 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
14579 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
14580 #define TIM_BDTR_BK2P_Pos (25U)
14581 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
14582 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
14583
14584 /******************* Bit definition for TIM_DCR register ********************/
14585 #define TIM_DCR_DBA_Pos (0U)
14586 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
14587 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
14588 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
14589 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
14590 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
14591 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
14592 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
14593
14594 #define TIM_DCR_DBL_Pos (8U)
14595 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
14596 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
14597 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
14598 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
14599 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
14600 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
14601 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
14602
14603 /******************* Bit definition for TIM_DMAR register *******************/
14604 #define TIM_DMAR_DMAB_Pos (0U)
14605 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
14606 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
14607
14608 /******************* Bit definition for TIM1_OR1 register *******************/
14609 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
14610 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
14611 #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
14612 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
14613 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
14614
14615 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U)
14616 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
14617 #define TIM1_OR1_ETR_ADC3_RMP TIM1_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
14618 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
14619 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
14620
14621 #define TIM1_OR1_TI1_RMP_Pos (4U)
14622 #define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
14623 #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
14624
14625 /******************* Bit definition for TIM1_OR2 register *******************/
14626 #define TIM1_OR2_BKINE_Pos (0U)
14627 #define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
14628 #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14629 #define TIM1_OR2_BKCMP1E_Pos (1U)
14630 #define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14631 #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14632 #define TIM1_OR2_BKCMP2E_Pos (2U)
14633 #define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14634 #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14635 #define TIM1_OR2_BKDF1BK0E_Pos (8U)
14636 #define TIM1_OR2_BKDF1BK0E_Msk (0x1U << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
14637 #define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
14638 #define TIM1_OR2_BKINP_Pos (9U)
14639 #define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
14640 #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14641 #define TIM1_OR2_BKCMP1P_Pos (10U)
14642 #define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14643 #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14644 #define TIM1_OR2_BKCMP2P_Pos (11U)
14645 #define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14646 #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14647
14648 #define TIM1_OR2_ETRSEL_Pos (14U)
14649 #define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
14650 #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
14651 #define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
14652 #define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
14653 #define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14654
14655 /******************* Bit definition for TIM1_OR3 register *******************/
14656 #define TIM1_OR3_BK2INE_Pos (0U)
14657 #define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
14658 #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
14659 #define TIM1_OR3_BK2CMP1E_Pos (1U)
14660 #define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
14661 #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
14662 #define TIM1_OR3_BK2CMP2E_Pos (2U)
14663 #define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
14664 #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
14665 #define TIM1_OR3_BK2DF1BK1E_Pos (8U)
14666 #define TIM1_OR3_BK2DF1BK1E_Msk (0x1U << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */
14667 #define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */
14668 #define TIM1_OR3_BK2INP_Pos (9U)
14669 #define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
14670 #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
14671 #define TIM1_OR3_BK2CMP1P_Pos (10U)
14672 #define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
14673 #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
14674 #define TIM1_OR3_BK2CMP2P_Pos (11U)
14675 #define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
14676 #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
14677
14678 /******************* Bit definition for TIM8_OR1 register *******************/
14679 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U)
14680 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */
14681 #define TIM8_OR1_ETR_ADC2_RMP TIM8_OR1_ETR_ADC2_RMP_Msk /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
14682 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */
14683 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
14684
14685 #define TIM8_OR1_ETR_ADC3_RMP_Pos (2U)
14686 #define TIM8_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
14687 #define TIM8_OR1_ETR_ADC3_RMP TIM8_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
14688 #define TIM8_OR1_ETR_ADC3_RMP_0 (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
14689 #define TIM8_OR1_ETR_ADC3_RMP_1 (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
14690
14691 #define TIM8_OR1_TI1_RMP_Pos (4U)
14692 #define TIM8_OR1_TI1_RMP_Msk (0x1U << TIM8_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
14693 #define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk /*!<TIM8 Input Capture 1 remap */
14694
14695 /******************* Bit definition for TIM8_OR2 register *******************/
14696 #define TIM8_OR2_BKINE_Pos (0U)
14697 #define TIM8_OR2_BKINE_Msk (0x1U << TIM8_OR2_BKINE_Pos) /*!< 0x00000001 */
14698 #define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14699 #define TIM8_OR2_BKCMP1E_Pos (1U)
14700 #define TIM8_OR2_BKCMP1E_Msk (0x1U << TIM8_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14701 #define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14702 #define TIM8_OR2_BKCMP2E_Pos (2U)
14703 #define TIM8_OR2_BKCMP2E_Msk (0x1U << TIM8_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14704 #define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14705 #define TIM8_OR2_BKDF1BK2E_Pos (8U)
14706 #define TIM8_OR2_BKDF1BK2E_Msk (0x1U << TIM8_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
14707 #define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
14708 #define TIM8_OR2_BKINP_Pos (9U)
14709 #define TIM8_OR2_BKINP_Msk (0x1U << TIM8_OR2_BKINP_Pos) /*!< 0x00000200 */
14710 #define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14711 #define TIM8_OR2_BKCMP1P_Pos (10U)
14712 #define TIM8_OR2_BKCMP1P_Msk (0x1U << TIM8_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14713 #define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14714 #define TIM8_OR2_BKCMP2P_Pos (11U)
14715 #define TIM8_OR2_BKCMP2P_Msk (0x1U << TIM8_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14716 #define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14717
14718 #define TIM8_OR2_ETRSEL_Pos (14U)
14719 #define TIM8_OR2_ETRSEL_Msk (0x7U << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
14720 #define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
14721 #define TIM8_OR2_ETRSEL_0 (0x1U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */
14722 #define TIM8_OR2_ETRSEL_1 (0x2U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */
14723 #define TIM8_OR2_ETRSEL_2 (0x4U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14724
14725 /******************* Bit definition for TIM8_OR3 register *******************/
14726 #define TIM8_OR3_BK2INE_Pos (0U)
14727 #define TIM8_OR3_BK2INE_Msk (0x1U << TIM8_OR3_BK2INE_Pos) /*!< 0x00000001 */
14728 #define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
14729 #define TIM8_OR3_BK2CMP1E_Pos (1U)
14730 #define TIM8_OR3_BK2CMP1E_Msk (0x1U << TIM8_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
14731 #define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
14732 #define TIM8_OR3_BK2CMP2E_Pos (2U)
14733 #define TIM8_OR3_BK2CMP2E_Msk (0x1U << TIM8_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
14734 #define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
14735 #define TIM8_OR3_BK2DF1BK3E_Pos (8U)
14736 #define TIM8_OR3_BK2DF1BK3E_Msk (0x1U << TIM8_OR3_BK2DF1BK3E_Pos) /*!< 0x00000100 */
14737 #define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk /*!<BRK2 DFSDM1_BREAK[3] enable */
14738 #define TIM8_OR3_BK2INP_Pos (9U)
14739 #define TIM8_OR3_BK2INP_Msk (0x1U << TIM8_OR3_BK2INP_Pos) /*!< 0x00000200 */
14740 #define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
14741 #define TIM8_OR3_BK2CMP1P_Pos (10U)
14742 #define TIM8_OR3_BK2CMP1P_Msk (0x1U << TIM8_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
14743 #define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
14744 #define TIM8_OR3_BK2CMP2P_Pos (11U)
14745 #define TIM8_OR3_BK2CMP2P_Msk (0x1U << TIM8_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
14746 #define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
14747
14748 /******************* Bit definition for TIM2_OR1 register *******************/
14749 #define TIM2_OR1_ITR1_RMP_Pos (0U)
14750 #define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
14751 #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
14752 #define TIM2_OR1_ETR1_RMP_Pos (1U)
14753 #define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
14754 #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
14755
14756 #define TIM2_OR1_TI4_RMP_Pos (2U)
14757 #define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
14758 #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
14759 #define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
14760 #define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
14761
14762 /******************* Bit definition for TIM2_OR2 register *******************/
14763 #define TIM2_OR2_ETRSEL_Pos (14U)
14764 #define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
14765 #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
14766 #define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
14767 #define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
14768 #define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14769
14770 /******************* Bit definition for TIM3_OR1 register *******************/
14771 #define TIM3_OR1_TI1_RMP_Pos (0U)
14772 #define TIM3_OR1_TI1_RMP_Msk (0x3U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14773 #define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
14774 #define TIM3_OR1_TI1_RMP_0 (0x1U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14775 #define TIM3_OR1_TI1_RMP_1 (0x2U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
14776
14777 /******************* Bit definition for TIM3_OR2 register *******************/
14778 #define TIM3_OR2_ETRSEL_Pos (14U)
14779 #define TIM3_OR2_ETRSEL_Msk (0x7U << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
14780 #define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
14781 #define TIM3_OR2_ETRSEL_0 (0x1U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */
14782 #define TIM3_OR2_ETRSEL_1 (0x2U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */
14783 #define TIM3_OR2_ETRSEL_2 (0x4U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14784
14785 /******************* Bit definition for TIM15_OR1 register ******************/
14786 #define TIM15_OR1_TI1_RMP_Pos (0U)
14787 #define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14788 #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
14789
14790 #define TIM15_OR1_ENCODER_MODE_Pos (1U)
14791 #define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
14792 #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
14793 #define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
14794 #define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
14795
14796 /******************* Bit definition for TIM15_OR2 register ******************/
14797 #define TIM15_OR2_BKINE_Pos (0U)
14798 #define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
14799 #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14800 #define TIM15_OR2_BKCMP1E_Pos (1U)
14801 #define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14802 #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14803 #define TIM15_OR2_BKCMP2E_Pos (2U)
14804 #define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14805 #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14806 #define TIM15_OR2_BKDF1BK0E_Pos (8U)
14807 #define TIM15_OR2_BKDF1BK0E_Msk (0x1U << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
14808 #define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
14809 #define TIM15_OR2_BKINP_Pos (9U)
14810 #define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
14811 #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14812 #define TIM15_OR2_BKCMP1P_Pos (10U)
14813 #define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14814 #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14815 #define TIM15_OR2_BKCMP2P_Pos (11U)
14816 #define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14817 #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14818
14819 /******************* Bit definition for TIM16_OR1 register ******************/
14820 #define TIM16_OR1_TI1_RMP_Pos (0U)
14821 #define TIM16_OR1_TI1_RMP_Msk (0x3U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14822 #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
14823 #define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14824 #define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
14825
14826 /******************* Bit definition for TIM16_OR2 register ******************/
14827 #define TIM16_OR2_BKINE_Pos (0U)
14828 #define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
14829 #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14830 #define TIM16_OR2_BKCMP1E_Pos (1U)
14831 #define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14832 #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14833 #define TIM16_OR2_BKCMP2E_Pos (2U)
14834 #define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14835 #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14836 #define TIM16_OR2_BKDF1BK1E_Pos (8U)
14837 #define TIM16_OR2_BKDF1BK1E_Msk (0x1U << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */
14838 #define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */
14839 #define TIM16_OR2_BKINP_Pos (9U)
14840 #define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
14841 #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14842 #define TIM16_OR2_BKCMP1P_Pos (10U)
14843 #define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14844 #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14845 #define TIM16_OR2_BKCMP2P_Pos (11U)
14846 #define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14847 #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14848
14849 /******************* Bit definition for TIM17_OR1 register ******************/
14850 #define TIM17_OR1_TI1_RMP_Pos (0U)
14851 #define TIM17_OR1_TI1_RMP_Msk (0x3U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14852 #define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
14853 #define TIM17_OR1_TI1_RMP_0 (0x1U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14854 #define TIM17_OR1_TI1_RMP_1 (0x2U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
14855
14856 /******************* Bit definition for TIM17_OR2 register ******************/
14857 #define TIM17_OR2_BKINE_Pos (0U)
14858 #define TIM17_OR2_BKINE_Msk (0x1U << TIM17_OR2_BKINE_Pos) /*!< 0x00000001 */
14859 #define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk /*!<BRK BKIN input enable */
14860 #define TIM17_OR2_BKCMP1E_Pos (1U)
14861 #define TIM17_OR2_BKCMP1E_Msk (0x1U << TIM17_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
14862 #define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
14863 #define TIM17_OR2_BKCMP2E_Pos (2U)
14864 #define TIM17_OR2_BKCMP2E_Msk (0x1U << TIM17_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
14865 #define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
14866 #define TIM17_OR2_BKDF1BK2E_Pos (8U)
14867 #define TIM17_OR2_BKDF1BK2E_Msk (0x1U << TIM17_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
14868 #define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
14869 #define TIM17_OR2_BKINP_Pos (9U)
14870 #define TIM17_OR2_BKINP_Msk (0x1U << TIM17_OR2_BKINP_Pos) /*!< 0x00000200 */
14871 #define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
14872 #define TIM17_OR2_BKCMP1P_Pos (10U)
14873 #define TIM17_OR2_BKCMP1P_Msk (0x1U << TIM17_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
14874 #define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
14875 #define TIM17_OR2_BKCMP2P_Pos (11U)
14876 #define TIM17_OR2_BKCMP2P_Msk (0x1U << TIM17_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
14877 #define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
14878
14879 /******************************************************************************/
14880 /* */
14881 /* Low Power Timer (LPTTIM) */
14882 /* */
14883 /******************************************************************************/
14884 /****************** Bit definition for LPTIM_ISR register *******************/
14885 #define LPTIM_ISR_CMPM_Pos (0U)
14886 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
14887 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
14888 #define LPTIM_ISR_ARRM_Pos (1U)
14889 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
14890 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
14891 #define LPTIM_ISR_EXTTRIG_Pos (2U)
14892 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
14893 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
14894 #define LPTIM_ISR_CMPOK_Pos (3U)
14895 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
14896 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
14897 #define LPTIM_ISR_ARROK_Pos (4U)
14898 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
14899 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
14900 #define LPTIM_ISR_UP_Pos (5U)
14901 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
14902 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
14903 #define LPTIM_ISR_DOWN_Pos (6U)
14904 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
14905 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
14906
14907 /****************** Bit definition for LPTIM_ICR register *******************/
14908 #define LPTIM_ICR_CMPMCF_Pos (0U)
14909 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
14910 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
14911 #define LPTIM_ICR_ARRMCF_Pos (1U)
14912 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
14913 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
14914 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
14915 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
14916 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
14917 #define LPTIM_ICR_CMPOKCF_Pos (3U)
14918 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
14919 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
14920 #define LPTIM_ICR_ARROKCF_Pos (4U)
14921 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
14922 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
14923 #define LPTIM_ICR_UPCF_Pos (5U)
14924 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
14925 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
14926 #define LPTIM_ICR_DOWNCF_Pos (6U)
14927 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
14928 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
14929
14930 /****************** Bit definition for LPTIM_IER register ********************/
14931 #define LPTIM_IER_CMPMIE_Pos (0U)
14932 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
14933 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
14934 #define LPTIM_IER_ARRMIE_Pos (1U)
14935 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
14936 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
14937 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
14938 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
14939 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
14940 #define LPTIM_IER_CMPOKIE_Pos (3U)
14941 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
14942 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
14943 #define LPTIM_IER_ARROKIE_Pos (4U)
14944 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
14945 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
14946 #define LPTIM_IER_UPIE_Pos (5U)
14947 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
14948 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
14949 #define LPTIM_IER_DOWNIE_Pos (6U)
14950 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
14951 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
14952
14953 /****************** Bit definition for LPTIM_CFGR register *******************/
14954 #define LPTIM_CFGR_CKSEL_Pos (0U)
14955 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
14956 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
14957
14958 #define LPTIM_CFGR_CKPOL_Pos (1U)
14959 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
14960 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
14961 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
14962 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
14963
14964 #define LPTIM_CFGR_CKFLT_Pos (3U)
14965 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
14966 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
14967 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
14968 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
14969
14970 #define LPTIM_CFGR_TRGFLT_Pos (6U)
14971 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
14972 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
14973 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
14974 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
14975
14976 #define LPTIM_CFGR_PRESC_Pos (9U)
14977 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
14978 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
14979 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
14980 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
14981 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
14982
14983 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
14984 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
14985 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
14986 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
14987 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
14988 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
14989
14990 #define LPTIM_CFGR_TRIGEN_Pos (17U)
14991 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
14992 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
14993 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
14994 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
14995
14996 #define LPTIM_CFGR_TIMOUT_Pos (19U)
14997 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
14998 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
14999 #define LPTIM_CFGR_WAVE_Pos (20U)
15000 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
15001 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
15002 #define LPTIM_CFGR_WAVPOL_Pos (21U)
15003 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
15004 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
15005 #define LPTIM_CFGR_PRELOAD_Pos (22U)
15006 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
15007 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
15008 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
15009 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
15010 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
15011 #define LPTIM_CFGR_ENC_Pos (24U)
15012 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
15013 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
15014
15015 /****************** Bit definition for LPTIM_CR register ********************/
15016 #define LPTIM_CR_ENABLE_Pos (0U)
15017 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
15018 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
15019 #define LPTIM_CR_SNGSTRT_Pos (1U)
15020 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
15021 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
15022 #define LPTIM_CR_CNTSTRT_Pos (2U)
15023 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
15024 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
15025
15026 /****************** Bit definition for LPTIM_CMP register *******************/
15027 #define LPTIM_CMP_CMP_Pos (0U)
15028 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
15029 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
15030
15031 /****************** Bit definition for LPTIM_ARR register *******************/
15032 #define LPTIM_ARR_ARR_Pos (0U)
15033 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
15034 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
15035
15036 /****************** Bit definition for LPTIM_CNT register *******************/
15037 #define LPTIM_CNT_CNT_Pos (0U)
15038 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
15039 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
15040
15041 /****************** Bit definition for LPTIM_OR register ********************/
15042 #define LPTIM_OR_OR_Pos (0U)
15043 #define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
15044 #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
15045 #define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
15046 #define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
15047
15048 /******************************************************************************/
15049 /* */
15050 /* Analog Comparators (COMP) */
15051 /* */
15052 /******************************************************************************/
15053 /********************** Bit definition for COMP_CSR register ****************/
15054 #define COMP_CSR_EN_Pos (0U)
15055 #define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
15056 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
15057
15058 #define COMP_CSR_PWRMODE_Pos (2U)
15059 #define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
15060 #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
15061 #define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
15062 #define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
15063
15064 #define COMP_CSR_INMSEL_Pos (4U)
15065 #define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
15066 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
15067 #define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
15068 #define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
15069 #define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
15070
15071 #define COMP_CSR_INPSEL_Pos (7U)
15072 #define COMP_CSR_INPSEL_Msk (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
15073 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
15074 #define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
15075
15076 #define COMP_CSR_WINMODE_Pos (9U)
15077 #define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
15078 #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
15079
15080 #define COMP_CSR_POLARITY_Pos (15U)
15081 #define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
15082 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
15083
15084 #define COMP_CSR_HYST_Pos (16U)
15085 #define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
15086 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
15087 #define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
15088 #define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
15089
15090 #define COMP_CSR_BLANKING_Pos (18U)
15091 #define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
15092 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
15093 #define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
15094 #define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
15095 #define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
15096
15097 #define COMP_CSR_BRGEN_Pos (22U)
15098 #define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
15099 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
15100 #define COMP_CSR_SCALEN_Pos (23U)
15101 #define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
15102 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
15103
15104 #define COMP_CSR_VALUE_Pos (30U)
15105 #define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
15106 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
15107
15108 #define COMP_CSR_LOCK_Pos (31U)
15109 #define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
15110 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
15111
15112 /******************************************************************************/
15113 /* */
15114 /* Operational Amplifier (OPAMP) */
15115 /* */
15116 /******************************************************************************/
15117 /********************* Bit definition for OPAMPx_CSR register ***************/
15118 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
15119 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
15120 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
15121 #define OPAMP_CSR_OPALPM_Pos (1U)
15122 #define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
15123 #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
15124
15125 #define OPAMP_CSR_OPAMODE_Pos (2U)
15126 #define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
15127 #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
15128 #define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
15129 #define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
15130
15131 #define OPAMP_CSR_PGGAIN_Pos (4U)
15132 #define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
15133 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
15134 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
15135 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
15136
15137 #define OPAMP_CSR_VMSEL_Pos (8U)
15138 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
15139 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
15140 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
15141 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
15142
15143 #define OPAMP_CSR_VPSEL_Pos (10U)
15144 #define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
15145 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
15146 #define OPAMP_CSR_CALON_Pos (12U)
15147 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
15148 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
15149 #define OPAMP_CSR_CALSEL_Pos (13U)
15150 #define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
15151 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
15152 #define OPAMP_CSR_USERTRIM_Pos (14U)
15153 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
15154 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
15155 #define OPAMP_CSR_CALOUT_Pos (15U)
15156 #define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
15157 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
15158
15159 /********************* Bit definition for OPAMP1_CSR register ***************/
15160 #define OPAMP1_CSR_OPAEN_Pos (0U)
15161 #define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
15162 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
15163 #define OPAMP1_CSR_OPALPM_Pos (1U)
15164 #define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
15165 #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
15166
15167 #define OPAMP1_CSR_OPAMODE_Pos (2U)
15168 #define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
15169 #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
15170 #define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
15171 #define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
15172
15173 #define OPAMP1_CSR_PGAGAIN_Pos (4U)
15174 #define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
15175 #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
15176 #define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
15177 #define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
15178
15179 #define OPAMP1_CSR_VMSEL_Pos (8U)
15180 #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
15181 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
15182 #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
15183 #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
15184
15185 #define OPAMP1_CSR_VPSEL_Pos (10U)
15186 #define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
15187 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
15188 #define OPAMP1_CSR_CALON_Pos (12U)
15189 #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
15190 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
15191 #define OPAMP1_CSR_CALSEL_Pos (13U)
15192 #define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
15193 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
15194 #define OPAMP1_CSR_USERTRIM_Pos (14U)
15195 #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
15196 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
15197 #define OPAMP1_CSR_CALOUT_Pos (15U)
15198 #define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
15199 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
15200
15201 #define OPAMP1_CSR_OPARANGE_Pos (31U)
15202 #define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
15203 #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
15204
15205 /********************* Bit definition for OPAMP2_CSR register ***************/
15206 #define OPAMP2_CSR_OPAEN_Pos (0U)
15207 #define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
15208 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
15209 #define OPAMP2_CSR_OPALPM_Pos (1U)
15210 #define OPAMP2_CSR_OPALPM_Msk (0x1U << OPAMP2_CSR_OPALPM_Pos) /*!< 0x00000002 */
15211 #define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk /*!< Operational amplifier2 Low Power Mode */
15212
15213 #define OPAMP2_CSR_OPAMODE_Pos (2U)
15214 #define OPAMP2_CSR_OPAMODE_Msk (0x3U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x0000000C */
15215 #define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk /*!< Operational amplifier2 PGA mode */
15216 #define OPAMP2_CSR_OPAMODE_0 (0x1U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000004 */
15217 #define OPAMP2_CSR_OPAMODE_1 (0x2U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000008 */
15218
15219 #define OPAMP2_CSR_PGAGAIN_Pos (4U)
15220 #define OPAMP2_CSR_PGAGAIN_Msk (0x3U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
15221 #define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
15222 #define OPAMP2_CSR_PGAGAIN_0 (0x1U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
15223 #define OPAMP2_CSR_PGAGAIN_1 (0x2U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
15224
15225 #define OPAMP2_CSR_VMSEL_Pos (8U)
15226 #define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000300 */
15227 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
15228 #define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000100 */
15229 #define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000200 */
15230
15231 #define OPAMP2_CSR_VPSEL_Pos (10U)
15232 #define OPAMP2_CSR_VPSEL_Msk (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000400 */
15233 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
15234 #define OPAMP2_CSR_CALON_Pos (12U)
15235 #define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00001000 */
15236 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
15237 #define OPAMP2_CSR_CALSEL_Pos (13U)
15238 #define OPAMP2_CSR_CALSEL_Msk (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
15239 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
15240 #define OPAMP2_CSR_USERTRIM_Pos (14U)
15241 #define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00004000 */
15242 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
15243 #define OPAMP2_CSR_CALOUT_Pos (15U)
15244 #define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x00008000 */
15245 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
15246
15247 /******************* Bit definition for OPAMP_OTR register ******************/
15248 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
15249 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
15250 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15251 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
15252 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
15253 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15254
15255 /******************* Bit definition for OPAMP1_OTR register ******************/
15256 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
15257 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
15258 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15259 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
15260 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
15261 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15262
15263 /******************* Bit definition for OPAMP2_OTR register ******************/
15264 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
15265 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
15266 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15267 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
15268 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
15269 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15270
15271 /******************* Bit definition for OPAMP_LPOTR register ****************/
15272 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
15273 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
15274 #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15275 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
15276 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
15277 #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15278
15279 /******************* Bit definition for OPAMP1_LPOTR register ****************/
15280 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
15281 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
15282 #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15283 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
15284 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
15285 #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15286
15287 /******************* Bit definition for OPAMP2_LPOTR register ****************/
15288 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
15289 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
15290 #define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
15291 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
15292 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
15293 #define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
15294
15295 /******************************************************************************/
15296 /* */
15297 /* Touch Sensing Controller (TSC) */
15298 /* */
15299 /******************************************************************************/
15300 /******************* Bit definition for TSC_CR register *********************/
15301 #define TSC_CR_TSCE_Pos (0U)
15302 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
15303 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
15304 #define TSC_CR_START_Pos (1U)
15305 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
15306 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
15307 #define TSC_CR_AM_Pos (2U)
15308 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
15309 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
15310 #define TSC_CR_SYNCPOL_Pos (3U)
15311 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
15312 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
15313 #define TSC_CR_IODEF_Pos (4U)
15314 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
15315 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
15316
15317 #define TSC_CR_MCV_Pos (5U)
15318 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
15319 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
15320 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
15321 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
15322 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
15323
15324 #define TSC_CR_PGPSC_Pos (12U)
15325 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
15326 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
15327 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
15328 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
15329 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
15330
15331 #define TSC_CR_SSPSC_Pos (15U)
15332 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
15333 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
15334 #define TSC_CR_SSE_Pos (16U)
15335 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
15336 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
15337
15338 #define TSC_CR_SSD_Pos (17U)
15339 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
15340 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
15341 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
15342 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
15343 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
15344 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
15345 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
15346 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
15347 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
15348
15349 #define TSC_CR_CTPL_Pos (24U)
15350 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
15351 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
15352 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
15353 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
15354 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
15355 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
15356
15357 #define TSC_CR_CTPH_Pos (28U)
15358 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
15359 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
15360 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
15361 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
15362 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
15363 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
15364
15365 /******************* Bit definition for TSC_IER register ********************/
15366 #define TSC_IER_EOAIE_Pos (0U)
15367 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
15368 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
15369 #define TSC_IER_MCEIE_Pos (1U)
15370 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
15371 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
15372
15373 /******************* Bit definition for TSC_ICR register ********************/
15374 #define TSC_ICR_EOAIC_Pos (0U)
15375 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
15376 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
15377 #define TSC_ICR_MCEIC_Pos (1U)
15378 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
15379 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
15380
15381 /******************* Bit definition for TSC_ISR register ********************/
15382 #define TSC_ISR_EOAF_Pos (0U)
15383 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
15384 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
15385 #define TSC_ISR_MCEF_Pos (1U)
15386 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
15387 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
15388
15389 /******************* Bit definition for TSC_IOHCR register ******************/
15390 #define TSC_IOHCR_G1_IO1_Pos (0U)
15391 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
15392 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
15393 #define TSC_IOHCR_G1_IO2_Pos (1U)
15394 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
15395 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
15396 #define TSC_IOHCR_G1_IO3_Pos (2U)
15397 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
15398 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
15399 #define TSC_IOHCR_G1_IO4_Pos (3U)
15400 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
15401 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
15402 #define TSC_IOHCR_G2_IO1_Pos (4U)
15403 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
15404 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
15405 #define TSC_IOHCR_G2_IO2_Pos (5U)
15406 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
15407 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
15408 #define TSC_IOHCR_G2_IO3_Pos (6U)
15409 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
15410 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
15411 #define TSC_IOHCR_G2_IO4_Pos (7U)
15412 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
15413 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
15414 #define TSC_IOHCR_G3_IO1_Pos (8U)
15415 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
15416 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
15417 #define TSC_IOHCR_G3_IO2_Pos (9U)
15418 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
15419 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
15420 #define TSC_IOHCR_G3_IO3_Pos (10U)
15421 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
15422 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
15423 #define TSC_IOHCR_G3_IO4_Pos (11U)
15424 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
15425 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
15426 #define TSC_IOHCR_G4_IO1_Pos (12U)
15427 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
15428 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
15429 #define TSC_IOHCR_G4_IO2_Pos (13U)
15430 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
15431 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
15432 #define TSC_IOHCR_G4_IO3_Pos (14U)
15433 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
15434 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
15435 #define TSC_IOHCR_G4_IO4_Pos (15U)
15436 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
15437 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
15438 #define TSC_IOHCR_G5_IO1_Pos (16U)
15439 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
15440 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
15441 #define TSC_IOHCR_G5_IO2_Pos (17U)
15442 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
15443 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
15444 #define TSC_IOHCR_G5_IO3_Pos (18U)
15445 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
15446 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
15447 #define TSC_IOHCR_G5_IO4_Pos (19U)
15448 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
15449 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
15450 #define TSC_IOHCR_G6_IO1_Pos (20U)
15451 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
15452 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
15453 #define TSC_IOHCR_G6_IO2_Pos (21U)
15454 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
15455 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
15456 #define TSC_IOHCR_G6_IO3_Pos (22U)
15457 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
15458 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
15459 #define TSC_IOHCR_G6_IO4_Pos (23U)
15460 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
15461 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
15462 #define TSC_IOHCR_G7_IO1_Pos (24U)
15463 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
15464 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
15465 #define TSC_IOHCR_G7_IO2_Pos (25U)
15466 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
15467 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
15468 #define TSC_IOHCR_G7_IO3_Pos (26U)
15469 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
15470 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
15471 #define TSC_IOHCR_G7_IO4_Pos (27U)
15472 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
15473 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
15474 #define TSC_IOHCR_G8_IO1_Pos (28U)
15475 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
15476 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
15477 #define TSC_IOHCR_G8_IO2_Pos (29U)
15478 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
15479 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
15480 #define TSC_IOHCR_G8_IO3_Pos (30U)
15481 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
15482 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
15483 #define TSC_IOHCR_G8_IO4_Pos (31U)
15484 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
15485 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
15486
15487 /******************* Bit definition for TSC_IOASCR register *****************/
15488 #define TSC_IOASCR_G1_IO1_Pos (0U)
15489 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
15490 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
15491 #define TSC_IOASCR_G1_IO2_Pos (1U)
15492 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
15493 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
15494 #define TSC_IOASCR_G1_IO3_Pos (2U)
15495 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
15496 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
15497 #define TSC_IOASCR_G1_IO4_Pos (3U)
15498 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
15499 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
15500 #define TSC_IOASCR_G2_IO1_Pos (4U)
15501 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
15502 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
15503 #define TSC_IOASCR_G2_IO2_Pos (5U)
15504 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
15505 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
15506 #define TSC_IOASCR_G2_IO3_Pos (6U)
15507 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
15508 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
15509 #define TSC_IOASCR_G2_IO4_Pos (7U)
15510 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
15511 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
15512 #define TSC_IOASCR_G3_IO1_Pos (8U)
15513 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
15514 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
15515 #define TSC_IOASCR_G3_IO2_Pos (9U)
15516 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
15517 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
15518 #define TSC_IOASCR_G3_IO3_Pos (10U)
15519 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
15520 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
15521 #define TSC_IOASCR_G3_IO4_Pos (11U)
15522 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
15523 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
15524 #define TSC_IOASCR_G4_IO1_Pos (12U)
15525 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
15526 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
15527 #define TSC_IOASCR_G4_IO2_Pos (13U)
15528 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
15529 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
15530 #define TSC_IOASCR_G4_IO3_Pos (14U)
15531 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
15532 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
15533 #define TSC_IOASCR_G4_IO4_Pos (15U)
15534 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
15535 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
15536 #define TSC_IOASCR_G5_IO1_Pos (16U)
15537 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
15538 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
15539 #define TSC_IOASCR_G5_IO2_Pos (17U)
15540 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
15541 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
15542 #define TSC_IOASCR_G5_IO3_Pos (18U)
15543 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
15544 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
15545 #define TSC_IOASCR_G5_IO4_Pos (19U)
15546 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
15547 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
15548 #define TSC_IOASCR_G6_IO1_Pos (20U)
15549 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
15550 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
15551 #define TSC_IOASCR_G6_IO2_Pos (21U)
15552 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
15553 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
15554 #define TSC_IOASCR_G6_IO3_Pos (22U)
15555 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
15556 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
15557 #define TSC_IOASCR_G6_IO4_Pos (23U)
15558 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
15559 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
15560 #define TSC_IOASCR_G7_IO1_Pos (24U)
15561 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
15562 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
15563 #define TSC_IOASCR_G7_IO2_Pos (25U)
15564 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
15565 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
15566 #define TSC_IOASCR_G7_IO3_Pos (26U)
15567 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
15568 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
15569 #define TSC_IOASCR_G7_IO4_Pos (27U)
15570 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
15571 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
15572 #define TSC_IOASCR_G8_IO1_Pos (28U)
15573 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
15574 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
15575 #define TSC_IOASCR_G8_IO2_Pos (29U)
15576 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
15577 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
15578 #define TSC_IOASCR_G8_IO3_Pos (30U)
15579 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
15580 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
15581 #define TSC_IOASCR_G8_IO4_Pos (31U)
15582 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
15583 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
15584
15585 /******************* Bit definition for TSC_IOSCR register ******************/
15586 #define TSC_IOSCR_G1_IO1_Pos (0U)
15587 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
15588 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
15589 #define TSC_IOSCR_G1_IO2_Pos (1U)
15590 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
15591 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
15592 #define TSC_IOSCR_G1_IO3_Pos (2U)
15593 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
15594 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
15595 #define TSC_IOSCR_G1_IO4_Pos (3U)
15596 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
15597 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
15598 #define TSC_IOSCR_G2_IO1_Pos (4U)
15599 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
15600 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
15601 #define TSC_IOSCR_G2_IO2_Pos (5U)
15602 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
15603 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
15604 #define TSC_IOSCR_G2_IO3_Pos (6U)
15605 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
15606 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
15607 #define TSC_IOSCR_G2_IO4_Pos (7U)
15608 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
15609 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
15610 #define TSC_IOSCR_G3_IO1_Pos (8U)
15611 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
15612 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
15613 #define TSC_IOSCR_G3_IO2_Pos (9U)
15614 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
15615 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
15616 #define TSC_IOSCR_G3_IO3_Pos (10U)
15617 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
15618 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
15619 #define TSC_IOSCR_G3_IO4_Pos (11U)
15620 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
15621 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
15622 #define TSC_IOSCR_G4_IO1_Pos (12U)
15623 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
15624 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
15625 #define TSC_IOSCR_G4_IO2_Pos (13U)
15626 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
15627 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
15628 #define TSC_IOSCR_G4_IO3_Pos (14U)
15629 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
15630 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
15631 #define TSC_IOSCR_G4_IO4_Pos (15U)
15632 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
15633 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
15634 #define TSC_IOSCR_G5_IO1_Pos (16U)
15635 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
15636 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
15637 #define TSC_IOSCR_G5_IO2_Pos (17U)
15638 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
15639 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
15640 #define TSC_IOSCR_G5_IO3_Pos (18U)
15641 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
15642 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
15643 #define TSC_IOSCR_G5_IO4_Pos (19U)
15644 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
15645 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
15646 #define TSC_IOSCR_G6_IO1_Pos (20U)
15647 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
15648 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
15649 #define TSC_IOSCR_G6_IO2_Pos (21U)
15650 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
15651 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
15652 #define TSC_IOSCR_G6_IO3_Pos (22U)
15653 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
15654 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
15655 #define TSC_IOSCR_G6_IO4_Pos (23U)
15656 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
15657 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
15658 #define TSC_IOSCR_G7_IO1_Pos (24U)
15659 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
15660 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
15661 #define TSC_IOSCR_G7_IO2_Pos (25U)
15662 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
15663 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
15664 #define TSC_IOSCR_G7_IO3_Pos (26U)
15665 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
15666 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
15667 #define TSC_IOSCR_G7_IO4_Pos (27U)
15668 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
15669 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
15670 #define TSC_IOSCR_G8_IO1_Pos (28U)
15671 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
15672 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
15673 #define TSC_IOSCR_G8_IO2_Pos (29U)
15674 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
15675 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
15676 #define TSC_IOSCR_G8_IO3_Pos (30U)
15677 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
15678 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
15679 #define TSC_IOSCR_G8_IO4_Pos (31U)
15680 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
15681 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
15682
15683 /******************* Bit definition for TSC_IOCCR register ******************/
15684 #define TSC_IOCCR_G1_IO1_Pos (0U)
15685 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
15686 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
15687 #define TSC_IOCCR_G1_IO2_Pos (1U)
15688 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
15689 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
15690 #define TSC_IOCCR_G1_IO3_Pos (2U)
15691 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
15692 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
15693 #define TSC_IOCCR_G1_IO4_Pos (3U)
15694 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
15695 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
15696 #define TSC_IOCCR_G2_IO1_Pos (4U)
15697 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
15698 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
15699 #define TSC_IOCCR_G2_IO2_Pos (5U)
15700 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
15701 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
15702 #define TSC_IOCCR_G2_IO3_Pos (6U)
15703 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
15704 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
15705 #define TSC_IOCCR_G2_IO4_Pos (7U)
15706 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
15707 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
15708 #define TSC_IOCCR_G3_IO1_Pos (8U)
15709 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
15710 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
15711 #define TSC_IOCCR_G3_IO2_Pos (9U)
15712 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
15713 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
15714 #define TSC_IOCCR_G3_IO3_Pos (10U)
15715 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
15716 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
15717 #define TSC_IOCCR_G3_IO4_Pos (11U)
15718 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
15719 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
15720 #define TSC_IOCCR_G4_IO1_Pos (12U)
15721 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
15722 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
15723 #define TSC_IOCCR_G4_IO2_Pos (13U)
15724 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
15725 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
15726 #define TSC_IOCCR_G4_IO3_Pos (14U)
15727 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
15728 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
15729 #define TSC_IOCCR_G4_IO4_Pos (15U)
15730 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
15731 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
15732 #define TSC_IOCCR_G5_IO1_Pos (16U)
15733 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
15734 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
15735 #define TSC_IOCCR_G5_IO2_Pos (17U)
15736 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
15737 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
15738 #define TSC_IOCCR_G5_IO3_Pos (18U)
15739 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
15740 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
15741 #define TSC_IOCCR_G5_IO4_Pos (19U)
15742 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
15743 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
15744 #define TSC_IOCCR_G6_IO1_Pos (20U)
15745 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
15746 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
15747 #define TSC_IOCCR_G6_IO2_Pos (21U)
15748 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
15749 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
15750 #define TSC_IOCCR_G6_IO3_Pos (22U)
15751 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
15752 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
15753 #define TSC_IOCCR_G6_IO4_Pos (23U)
15754 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
15755 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
15756 #define TSC_IOCCR_G7_IO1_Pos (24U)
15757 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
15758 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
15759 #define TSC_IOCCR_G7_IO2_Pos (25U)
15760 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
15761 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
15762 #define TSC_IOCCR_G7_IO3_Pos (26U)
15763 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
15764 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
15765 #define TSC_IOCCR_G7_IO4_Pos (27U)
15766 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
15767 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
15768 #define TSC_IOCCR_G8_IO1_Pos (28U)
15769 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
15770 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
15771 #define TSC_IOCCR_G8_IO2_Pos (29U)
15772 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
15773 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
15774 #define TSC_IOCCR_G8_IO3_Pos (30U)
15775 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
15776 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
15777 #define TSC_IOCCR_G8_IO4_Pos (31U)
15778 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
15779 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
15780
15781 /******************* Bit definition for TSC_IOGCSR register *****************/
15782 #define TSC_IOGCSR_G1E_Pos (0U)
15783 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
15784 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
15785 #define TSC_IOGCSR_G2E_Pos (1U)
15786 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
15787 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
15788 #define TSC_IOGCSR_G3E_Pos (2U)
15789 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
15790 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
15791 #define TSC_IOGCSR_G4E_Pos (3U)
15792 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
15793 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
15794 #define TSC_IOGCSR_G5E_Pos (4U)
15795 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
15796 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
15797 #define TSC_IOGCSR_G6E_Pos (5U)
15798 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
15799 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
15800 #define TSC_IOGCSR_G7E_Pos (6U)
15801 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
15802 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
15803 #define TSC_IOGCSR_G8E_Pos (7U)
15804 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
15805 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
15806 #define TSC_IOGCSR_G1S_Pos (16U)
15807 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
15808 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
15809 #define TSC_IOGCSR_G2S_Pos (17U)
15810 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
15811 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
15812 #define TSC_IOGCSR_G3S_Pos (18U)
15813 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
15814 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
15815 #define TSC_IOGCSR_G4S_Pos (19U)
15816 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
15817 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
15818 #define TSC_IOGCSR_G5S_Pos (20U)
15819 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
15820 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
15821 #define TSC_IOGCSR_G6S_Pos (21U)
15822 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
15823 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
15824 #define TSC_IOGCSR_G7S_Pos (22U)
15825 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
15826 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
15827 #define TSC_IOGCSR_G8S_Pos (23U)
15828 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
15829 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
15830
15831 /******************* Bit definition for TSC_IOGXCR register *****************/
15832 #define TSC_IOGXCR_CNT_Pos (0U)
15833 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
15834 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
15835
15836 /******************************************************************************/
15837 /* */
15838 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
15839 /* */
15840 /******************************************************************************/
15841 /****************** Bit definition for USART_CR1 register *******************/
15842 #define USART_CR1_UE_Pos (0U)
15843 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
15844 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
15845 #define USART_CR1_UESM_Pos (1U)
15846 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
15847 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
15848 #define USART_CR1_RE_Pos (2U)
15849 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
15850 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
15851 #define USART_CR1_TE_Pos (3U)
15852 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
15853 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
15854 #define USART_CR1_IDLEIE_Pos (4U)
15855 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
15856 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
15857 #define USART_CR1_RXNEIE_Pos (5U)
15858 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
15859 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
15860 #define USART_CR1_TCIE_Pos (6U)
15861 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
15862 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
15863 #define USART_CR1_TXEIE_Pos (7U)
15864 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
15865 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
15866 #define USART_CR1_PEIE_Pos (8U)
15867 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
15868 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
15869 #define USART_CR1_PS_Pos (9U)
15870 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
15871 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
15872 #define USART_CR1_PCE_Pos (10U)
15873 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
15874 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
15875 #define USART_CR1_WAKE_Pos (11U)
15876 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
15877 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
15878 #define USART_CR1_M_Pos (12U)
15879 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
15880 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
15881 #define USART_CR1_M0_Pos (12U)
15882 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
15883 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
15884 #define USART_CR1_MME_Pos (13U)
15885 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
15886 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
15887 #define USART_CR1_CMIE_Pos (14U)
15888 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
15889 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
15890 #define USART_CR1_OVER8_Pos (15U)
15891 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
15892 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
15893 #define USART_CR1_DEDT_Pos (16U)
15894 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
15895 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
15896 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
15897 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
15898 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
15899 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
15900 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
15901 #define USART_CR1_DEAT_Pos (21U)
15902 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
15903 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
15904 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
15905 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
15906 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
15907 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
15908 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
15909 #define USART_CR1_RTOIE_Pos (26U)
15910 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
15911 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
15912 #define USART_CR1_EOBIE_Pos (27U)
15913 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
15914 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
15915 #define USART_CR1_M1_Pos (28U)
15916 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
15917 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
15918
15919 /****************** Bit definition for USART_CR2 register *******************/
15920 #define USART_CR2_ADDM7_Pos (4U)
15921 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
15922 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
15923 #define USART_CR2_LBDL_Pos (5U)
15924 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
15925 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
15926 #define USART_CR2_LBDIE_Pos (6U)
15927 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
15928 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
15929 #define USART_CR2_LBCL_Pos (8U)
15930 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
15931 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
15932 #define USART_CR2_CPHA_Pos (9U)
15933 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
15934 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
15935 #define USART_CR2_CPOL_Pos (10U)
15936 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
15937 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
15938 #define USART_CR2_CLKEN_Pos (11U)
15939 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
15940 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
15941 #define USART_CR2_STOP_Pos (12U)
15942 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
15943 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
15944 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
15945 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
15946 #define USART_CR2_LINEN_Pos (14U)
15947 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
15948 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
15949 #define USART_CR2_SWAP_Pos (15U)
15950 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
15951 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
15952 #define USART_CR2_RXINV_Pos (16U)
15953 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
15954 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
15955 #define USART_CR2_TXINV_Pos (17U)
15956 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
15957 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
15958 #define USART_CR2_DATAINV_Pos (18U)
15959 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
15960 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
15961 #define USART_CR2_MSBFIRST_Pos (19U)
15962 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
15963 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
15964 #define USART_CR2_ABREN_Pos (20U)
15965 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
15966 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
15967 #define USART_CR2_ABRMODE_Pos (21U)
15968 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
15969 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
15970 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
15971 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
15972 #define USART_CR2_RTOEN_Pos (23U)
15973 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
15974 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
15975 #define USART_CR2_ADD_Pos (24U)
15976 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
15977 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
15978
15979 /****************** Bit definition for USART_CR3 register *******************/
15980 #define USART_CR3_EIE_Pos (0U)
15981 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
15982 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
15983 #define USART_CR3_IREN_Pos (1U)
15984 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
15985 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
15986 #define USART_CR3_IRLP_Pos (2U)
15987 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
15988 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
15989 #define USART_CR3_HDSEL_Pos (3U)
15990 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
15991 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
15992 #define USART_CR3_NACK_Pos (4U)
15993 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
15994 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
15995 #define USART_CR3_SCEN_Pos (5U)
15996 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
15997 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
15998 #define USART_CR3_DMAR_Pos (6U)
15999 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
16000 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
16001 #define USART_CR3_DMAT_Pos (7U)
16002 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
16003 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
16004 #define USART_CR3_RTSE_Pos (8U)
16005 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
16006 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
16007 #define USART_CR3_CTSE_Pos (9U)
16008 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
16009 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
16010 #define USART_CR3_CTSIE_Pos (10U)
16011 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
16012 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
16013 #define USART_CR3_ONEBIT_Pos (11U)
16014 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
16015 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
16016 #define USART_CR3_OVRDIS_Pos (12U)
16017 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
16018 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
16019 #define USART_CR3_DDRE_Pos (13U)
16020 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
16021 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
16022 #define USART_CR3_DEM_Pos (14U)
16023 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
16024 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
16025 #define USART_CR3_DEP_Pos (15U)
16026 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
16027 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
16028 #define USART_CR3_SCARCNT_Pos (17U)
16029 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
16030 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
16031 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
16032 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
16033 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
16034 #define USART_CR3_WUS_Pos (20U)
16035 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
16036 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
16037 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
16038 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
16039 #define USART_CR3_WUFIE_Pos (22U)
16040 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
16041 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
16042
16043 /****************** Bit definition for USART_BRR register *******************/
16044 #define USART_BRR_DIV_FRACTION_Pos (0U)
16045 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
16046 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
16047 #define USART_BRR_DIV_MANTISSA_Pos (4U)
16048 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
16049 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
16050
16051 /****************** Bit definition for USART_GTPR register ******************/
16052 #define USART_GTPR_PSC_Pos (0U)
16053 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
16054 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
16055 #define USART_GTPR_GT_Pos (8U)
16056 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
16057 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
16058
16059
16060 /******************* Bit definition for USART_RTOR register *****************/
16061 #define USART_RTOR_RTO_Pos (0U)
16062 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
16063 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
16064 #define USART_RTOR_BLEN_Pos (24U)
16065 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
16066 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
16067
16068 /******************* Bit definition for USART_RQR register ******************/
16069 #define USART_RQR_ABRRQ_Pos (0U)
16070 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
16071 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
16072 #define USART_RQR_SBKRQ_Pos (1U)
16073 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
16074 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
16075 #define USART_RQR_MMRQ_Pos (2U)
16076 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
16077 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
16078 #define USART_RQR_RXFRQ_Pos (3U)
16079 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
16080 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
16081 #define USART_RQR_TXFRQ_Pos (4U)
16082 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
16083 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
16084
16085 /******************* Bit definition for USART_ISR register ******************/
16086 #define USART_ISR_PE_Pos (0U)
16087 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
16088 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
16089 #define USART_ISR_FE_Pos (1U)
16090 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
16091 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
16092 #define USART_ISR_NE_Pos (2U)
16093 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
16094 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
16095 #define USART_ISR_ORE_Pos (3U)
16096 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
16097 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
16098 #define USART_ISR_IDLE_Pos (4U)
16099 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
16100 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
16101 #define USART_ISR_RXNE_Pos (5U)
16102 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
16103 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
16104 #define USART_ISR_TC_Pos (6U)
16105 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
16106 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
16107 #define USART_ISR_TXE_Pos (7U)
16108 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
16109 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
16110 #define USART_ISR_LBDF_Pos (8U)
16111 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
16112 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
16113 #define USART_ISR_CTSIF_Pos (9U)
16114 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
16115 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
16116 #define USART_ISR_CTS_Pos (10U)
16117 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
16118 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
16119 #define USART_ISR_RTOF_Pos (11U)
16120 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
16121 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
16122 #define USART_ISR_EOBF_Pos (12U)
16123 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
16124 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
16125 #define USART_ISR_ABRE_Pos (14U)
16126 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
16127 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
16128 #define USART_ISR_ABRF_Pos (15U)
16129 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
16130 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
16131 #define USART_ISR_BUSY_Pos (16U)
16132 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
16133 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
16134 #define USART_ISR_CMF_Pos (17U)
16135 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
16136 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
16137 #define USART_ISR_SBKF_Pos (18U)
16138 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
16139 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
16140 #define USART_ISR_RWU_Pos (19U)
16141 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
16142 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
16143 #define USART_ISR_WUF_Pos (20U)
16144 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
16145 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
16146 #define USART_ISR_TEACK_Pos (21U)
16147 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
16148 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
16149 #define USART_ISR_REACK_Pos (22U)
16150 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
16151 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
16152
16153 /******************* Bit definition for USART_ICR register ******************/
16154 #define USART_ICR_PECF_Pos (0U)
16155 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
16156 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
16157 #define USART_ICR_FECF_Pos (1U)
16158 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
16159 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
16160 #define USART_ICR_NCF_Pos (2U)
16161 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
16162 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
16163 #define USART_ICR_ORECF_Pos (3U)
16164 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
16165 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
16166 #define USART_ICR_IDLECF_Pos (4U)
16167 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
16168 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
16169 #define USART_ICR_TCCF_Pos (6U)
16170 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
16171 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
16172 #define USART_ICR_LBDCF_Pos (8U)
16173 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
16174 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
16175 #define USART_ICR_CTSCF_Pos (9U)
16176 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
16177 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
16178 #define USART_ICR_RTOCF_Pos (11U)
16179 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
16180 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
16181 #define USART_ICR_EOBCF_Pos (12U)
16182 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
16183 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
16184 #define USART_ICR_CMCF_Pos (17U)
16185 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
16186 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
16187 #define USART_ICR_WUCF_Pos (20U)
16188 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
16189 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
16190
16191 /******************* Bit definition for USART_RDR register ******************/
16192 #define USART_RDR_RDR_Pos (0U)
16193 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
16194 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
16195
16196 /******************* Bit definition for USART_TDR register ******************/
16197 #define USART_TDR_TDR_Pos (0U)
16198 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
16199 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
16200
16201 /******************************************************************************/
16202 /* */
16203 /* Single Wire Protocol Master Interface (SWPMI) */
16204 /* */
16205 /******************************************************************************/
16206
16207 /******************* Bit definition for SWPMI_CR register ********************/
16208 #define SWPMI_CR_RXDMA_Pos (0U)
16209 #define SWPMI_CR_RXDMA_Msk (0x1U << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
16210 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
16211 #define SWPMI_CR_TXDMA_Pos (1U)
16212 #define SWPMI_CR_TXDMA_Msk (0x1U << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
16213 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
16214 #define SWPMI_CR_RXMODE_Pos (2U)
16215 #define SWPMI_CR_RXMODE_Msk (0x1U << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
16216 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
16217 #define SWPMI_CR_TXMODE_Pos (3U)
16218 #define SWPMI_CR_TXMODE_Msk (0x1U << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
16219 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
16220 #define SWPMI_CR_LPBK_Pos (4U)
16221 #define SWPMI_CR_LPBK_Msk (0x1U << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
16222 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
16223 #define SWPMI_CR_SWPACT_Pos (5U)
16224 #define SWPMI_CR_SWPACT_Msk (0x1U << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
16225 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
16226 #define SWPMI_CR_DEACT_Pos (10U)
16227 #define SWPMI_CR_DEACT_Msk (0x1U << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
16228 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
16229
16230 /******************* Bit definition for SWPMI_BRR register ********************/
16231 #define SWPMI_BRR_BR_Pos (0U)
16232 #define SWPMI_BRR_BR_Msk (0x3FU << SWPMI_BRR_BR_Pos) /*!< 0x0000003F */
16233 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[5:0] bits (Bitrate prescaler) */
16234
16235 /******************* Bit definition for SWPMI_ISR register ********************/
16236 #define SWPMI_ISR_RXBFF_Pos (0U)
16237 #define SWPMI_ISR_RXBFF_Msk (0x1U << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
16238 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
16239 #define SWPMI_ISR_TXBEF_Pos (1U)
16240 #define SWPMI_ISR_TXBEF_Msk (0x1U << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
16241 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
16242 #define SWPMI_ISR_RXBERF_Pos (2U)
16243 #define SWPMI_ISR_RXBERF_Msk (0x1U << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
16244 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
16245 #define SWPMI_ISR_RXOVRF_Pos (3U)
16246 #define SWPMI_ISR_RXOVRF_Msk (0x1U << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
16247 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
16248 #define SWPMI_ISR_TXUNRF_Pos (4U)
16249 #define SWPMI_ISR_TXUNRF_Msk (0x1U << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
16250 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
16251 #define SWPMI_ISR_RXNE_Pos (5U)
16252 #define SWPMI_ISR_RXNE_Msk (0x1U << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
16253 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
16254 #define SWPMI_ISR_TXE_Pos (6U)
16255 #define SWPMI_ISR_TXE_Msk (0x1U << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
16256 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
16257 #define SWPMI_ISR_TCF_Pos (7U)
16258 #define SWPMI_ISR_TCF_Msk (0x1U << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
16259 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
16260 #define SWPMI_ISR_SRF_Pos (8U)
16261 #define SWPMI_ISR_SRF_Msk (0x1U << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
16262 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
16263 #define SWPMI_ISR_SUSP_Pos (9U)
16264 #define SWPMI_ISR_SUSP_Msk (0x1U << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
16265 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
16266 #define SWPMI_ISR_DEACTF_Pos (10U)
16267 #define SWPMI_ISR_DEACTF_Msk (0x1U << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
16268 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
16269
16270 /******************* Bit definition for SWPMI_ICR register ********************/
16271 #define SWPMI_ICR_CRXBFF_Pos (0U)
16272 #define SWPMI_ICR_CRXBFF_Msk (0x1U << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
16273 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
16274 #define SWPMI_ICR_CTXBEF_Pos (1U)
16275 #define SWPMI_ICR_CTXBEF_Msk (0x1U << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
16276 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
16277 #define SWPMI_ICR_CRXBERF_Pos (2U)
16278 #define SWPMI_ICR_CRXBERF_Msk (0x1U << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
16279 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
16280 #define SWPMI_ICR_CRXOVRF_Pos (3U)
16281 #define SWPMI_ICR_CRXOVRF_Msk (0x1U << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
16282 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
16283 #define SWPMI_ICR_CTXUNRF_Pos (4U)
16284 #define SWPMI_ICR_CTXUNRF_Msk (0x1U << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
16285 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
16286 #define SWPMI_ICR_CTCF_Pos (7U)
16287 #define SWPMI_ICR_CTCF_Msk (0x1U << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
16288 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
16289 #define SWPMI_ICR_CSRF_Pos (8U)
16290 #define SWPMI_ICR_CSRF_Msk (0x1U << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
16291 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
16292
16293 /******************* Bit definition for SWPMI_IER register ********************/
16294 #define SWPMI_IER_SRIE_Pos (8U)
16295 #define SWPMI_IER_SRIE_Msk (0x1U << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
16296 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
16297 #define SWPMI_IER_TCIE_Pos (7U)
16298 #define SWPMI_IER_TCIE_Msk (0x1U << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
16299 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
16300 #define SWPMI_IER_TIE_Pos (6U)
16301 #define SWPMI_IER_TIE_Msk (0x1U << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
16302 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
16303 #define SWPMI_IER_RIE_Pos (5U)
16304 #define SWPMI_IER_RIE_Msk (0x1U << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
16305 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
16306 #define SWPMI_IER_TXUNRIE_Pos (4U)
16307 #define SWPMI_IER_TXUNRIE_Msk (0x1U << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
16308 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
16309 #define SWPMI_IER_RXOVRIE_Pos (3U)
16310 #define SWPMI_IER_RXOVRIE_Msk (0x1U << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
16311 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
16312 #define SWPMI_IER_RXBERIE_Pos (2U)
16313 #define SWPMI_IER_RXBERIE_Msk (0x1U << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
16314 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
16315 #define SWPMI_IER_TXBEIE_Pos (1U)
16316 #define SWPMI_IER_TXBEIE_Msk (0x1U << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
16317 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
16318 #define SWPMI_IER_RXBFIE_Pos (0U)
16319 #define SWPMI_IER_RXBFIE_Msk (0x1U << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
16320 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
16321
16322 /******************* Bit definition for SWPMI_RFL register ********************/
16323 #define SWPMI_RFL_RFL_Pos (0U)
16324 #define SWPMI_RFL_RFL_Msk (0x1FU << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
16325 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
16326 #define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
16327
16328 /******************* Bit definition for SWPMI_TDR register ********************/
16329 #define SWPMI_TDR_TD_Pos (0U)
16330 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
16331 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
16332
16333 /******************* Bit definition for SWPMI_RDR register ********************/
16334 #define SWPMI_RDR_RD_Pos (0U)
16335 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
16336 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
16337
16338 /******************* Bit definition for SWPMI_OR register ********************/
16339 #define SWPMI_OR_TBYP_Pos (0U)
16340 #define SWPMI_OR_TBYP_Msk (0x1U << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
16341 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
16342 #define SWPMI_OR_CLASS_Pos (1U)
16343 #define SWPMI_OR_CLASS_Msk (0x1U << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
16344 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP Voltage Class selection */
16345
16346 /******************************************************************************/
16347 /* */
16348 /* VREFBUF */
16349 /* */
16350 /******************************************************************************/
16351 /******************* Bit definition for VREFBUF_CSR register ****************/
16352 #define VREFBUF_CSR_ENVR_Pos (0U)
16353 #define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
16354 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
16355 #define VREFBUF_CSR_HIZ_Pos (1U)
16356 #define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
16357 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
16358 #define VREFBUF_CSR_VRS_Pos (2U)
16359 #define VREFBUF_CSR_VRS_Msk (0x1U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
16360 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
16361 #define VREFBUF_CSR_VRR_Pos (3U)
16362 #define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
16363 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
16364
16365 /******************* Bit definition for VREFBUF_CCR register ******************/
16366 #define VREFBUF_CCR_TRIM_Pos (0U)
16367 #define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
16368 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
16369
16370 /******************************************************************************/
16371 /* */
16372 /* Window WATCHDOG */
16373 /* */
16374 /******************************************************************************/
16375 /******************* Bit definition for WWDG_CR register ********************/
16376 #define WWDG_CR_T_Pos (0U)
16377 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
16378 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
16379 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
16380 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
16381 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
16382 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
16383 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
16384 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
16385 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
16386
16387 #define WWDG_CR_WDGA_Pos (7U)
16388 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
16389 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
16390
16391 /******************* Bit definition for WWDG_CFR register *******************/
16392 #define WWDG_CFR_W_Pos (0U)
16393 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
16394 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
16395 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
16396 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
16397 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
16398 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
16399 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
16400 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
16401 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
16402
16403 #define WWDG_CFR_WDGTB_Pos (7U)
16404 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
16405 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
16406 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
16407 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
16408
16409 #define WWDG_CFR_EWI_Pos (9U)
16410 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
16411 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
16412
16413 /******************* Bit definition for WWDG_SR register ********************/
16414 #define WWDG_SR_EWIF_Pos (0U)
16415 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
16416 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
16417
16418
16419 /******************************************************************************/
16420 /* */
16421 /* Debug MCU */
16422 /* */
16423 /******************************************************************************/
16424 /******************** Bit definition for DBGMCU_IDCODE register *************/
16425 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
16426 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
16427 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
16428 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
16429 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
16430 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
16431
16432 /******************** Bit definition for DBGMCU_CR register *****************/
16433 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
16434 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
16435 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
16436 #define DBGMCU_CR_DBG_STOP_Pos (1U)
16437 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
16438 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
16439 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
16440 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
16441 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
16442 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
16443 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
16444 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
16445
16446 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
16447 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
16448 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
16449 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
16450 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
16451
16452 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
16453 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
16454 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
16455 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
16456 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
16457 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
16458 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
16459 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
16460 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
16461 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
16462 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
16463 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
16464 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
16465 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
16466 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
16467 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
16468 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
16469 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
16470 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
16471 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
16472 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
16473 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
16474 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
16475 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
16476 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
16477 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
16478 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
16479 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
16480 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
16481 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
16482 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
16483 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
16484 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
16485 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
16486 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
16487 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
16488 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
16489 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
16490 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
16491 #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
16492 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
16493 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
16494 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
16495
16496 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
16497 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
16498 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
16499 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
16500
16501 /******************** Bit definition for DBGMCU_APB2FZ register ************/
16502 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
16503 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
16504 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
16505 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
16506 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
16507 #define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
16508 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
16509 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
16510 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
16511 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
16512 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
16513 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
16514 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
16515 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
16516 #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
16517
16518 /******************************************************************************/
16519 /* */
16520 /* USB_OTG */
16521 /* */
16522 /******************************************************************************/
16523 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
16524 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
16525 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
16526 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
16527 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
16528 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
16529 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
16530 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
16531 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
16532 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
16533 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
16534 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
16535 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
16536 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
16537 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
16538 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
16539 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
16540 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
16541 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
16542 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
16543 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
16544 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
16545 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
16546 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
16547 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
16548 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
16549 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
16550 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/
16551
16552 /******************** Bit definition for USB_OTG_HCFG register ********************/
16553
16554 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
16555 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
16556 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
16557 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
16558 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
16559 #define USB_OTG_HCFG_FSLSS_Pos (2U)
16560 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
16561 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
16562
16563 /******************** Bit definition for USB_OTG_DCFG register ********************/
16564
16565 #define USB_OTG_DCFG_DSPD_Pos (0U)
16566 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
16567 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
16568 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
16569 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
16570 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
16571 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
16572 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
16573 #define USB_OTG_DCFG_DAD_Pos (4U)
16574 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
16575 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
16576 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
16577 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
16578 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
16579 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
16580 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
16581 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
16582 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
16583 #define USB_OTG_DCFG_PFIVL_Pos (11U)
16584 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
16585 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
16586 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
16587 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
16588 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
16589 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
16590 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
16591 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
16592 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
16593
16594 /******************** Bit definition for USB_OTG_PCGCR register ********************/
16595 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
16596 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
16597 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
16598 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
16599 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
16600 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
16601 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
16602 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
16603 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
16604
16605 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
16606 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
16607 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
16608 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
16609 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
16610 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
16611 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
16612 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
16613 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
16614 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
16615 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
16616 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
16617 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
16618 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
16619 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
16620 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
16621 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
16622 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
16623 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
16624
16625 /******************** Bit definition for USB_OTG_DCTL register ********************/
16626 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
16627 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
16628 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
16629 #define USB_OTG_DCTL_SDIS_Pos (1U)
16630 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
16631 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
16632 #define USB_OTG_DCTL_GINSTS_Pos (2U)
16633 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
16634 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
16635 #define USB_OTG_DCTL_GONSTS_Pos (3U)
16636 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
16637 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
16638
16639 #define USB_OTG_DCTL_TCTL_Pos (4U)
16640 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
16641 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
16642 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
16643 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
16644 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
16645 #define USB_OTG_DCTL_SGINAK_Pos (7U)
16646 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
16647 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
16648 #define USB_OTG_DCTL_CGINAK_Pos (8U)
16649 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
16650 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
16651 #define USB_OTG_DCTL_SGONAK_Pos (9U)
16652 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
16653 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
16654 #define USB_OTG_DCTL_CGONAK_Pos (10U)
16655 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
16656 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
16657 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
16658 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
16659 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
16660
16661 /******************** Bit definition for USB_OTG_HFIR register ********************/
16662 #define USB_OTG_HFIR_FRIVL_Pos (0U)
16663 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
16664 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
16665
16666 /******************** Bit definition for USB_OTG_HFNUM register ********************/
16667 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
16668 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
16669 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
16670 #define USB_OTG_HFNUM_FTREM_Pos (16U)
16671 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
16672 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
16673
16674 /******************** Bit definition for USB_OTG_DSTS register ********************/
16675 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
16676 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
16677 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
16678
16679 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
16680 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
16681 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
16682 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
16683 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
16684 #define USB_OTG_DSTS_EERR_Pos (3U)
16685 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
16686 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
16687 #define USB_OTG_DSTS_FNSOF_Pos (8U)
16688 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
16689 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
16690
16691 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
16692 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
16693 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
16694 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
16695 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
16696 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
16697 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
16698 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
16699 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
16700 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
16701 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
16702 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
16703 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
16704 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
16705 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
16706 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
16707 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
16708 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
16709 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
16710 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
16711
16712 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
16713
16714 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
16715 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
16716 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
16717 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
16718 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
16719 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
16720 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
16721 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
16722 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
16723 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
16724 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
16725 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
16726 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
16727 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
16728 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
16729 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
16730 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
16731 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
16732 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
16733 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
16734 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
16735 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
16736 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
16737 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
16738 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
16739 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
16740 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
16741 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
16742 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
16743 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
16744 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
16745 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
16746 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
16747 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
16748 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
16749 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
16750 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
16751 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
16752 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
16753 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
16754 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
16755 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
16756 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
16757 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
16758 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
16759 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
16760 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
16761 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
16762 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
16763 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
16764 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
16765 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
16766 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
16767 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
16768 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
16769 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
16770 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
16771 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
16772 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
16773 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
16774 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
16775
16776 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
16777 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
16778 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
16779 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
16780 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
16781 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
16782 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
16783 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
16784 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
16785 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
16786 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
16787 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
16788 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
16789 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
16790 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
16791 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
16792 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
16793 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
16794 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
16795 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
16796 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
16797 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
16798 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
16799 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
16800 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
16801 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
16802 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
16803 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
16804 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
16805 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
16806
16807 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
16808 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
16809 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
16810 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
16811 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
16812 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
16813 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
16814 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
16815 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
16816 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
16817 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
16818 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
16819 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
16820 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
16821 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
16822 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
16823 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
16824 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
16825 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
16826 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
16827 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
16828 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
16829 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
16830 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
16831 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
16832
16833 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
16834 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
16835 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
16836 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
16837 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
16838 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
16839 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
16840 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
16841 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
16842 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
16843 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
16844 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
16845 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
16846 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
16847 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
16848
16849 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
16850 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
16851 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
16852 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
16853 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
16854 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
16855 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
16856 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
16857 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
16858 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
16859 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
16860
16861 /******************** Bit definition for USB_OTG_HAINT register ********************/
16862 #define USB_OTG_HAINT_HAINT_Pos (0U)
16863 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
16864 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
16865
16866 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
16867 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
16868 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
16869 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
16870 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
16871 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
16872 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
16873 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
16874 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
16875 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
16876 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
16877 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
16878 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
16879 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
16880 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
16881 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
16882 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
16883 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
16884 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
16885 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
16886 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
16887 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
16888
16889 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
16890 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
16891 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
16892 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
16893 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
16894 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
16895 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
16896 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
16897 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
16898 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
16899 #define USB_OTG_GINTSTS_SOF_Pos (3U)
16900 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
16901 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
16902 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
16903 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
16904 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
16905 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
16906 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
16907 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
16908 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
16909 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
16910 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
16911 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
16912 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
16913 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
16914 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
16915 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
16916 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
16917 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
16918 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
16919 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
16920 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
16921 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
16922 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
16923 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
16924 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
16925 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
16926 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
16927 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
16928 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
16929 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
16930 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
16931 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
16932 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
16933 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
16934 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
16935 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
16936 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
16937 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
16938 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
16939 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
16940 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
16941 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
16942 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
16943 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
16944 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
16945 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
16946 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
16947 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
16948 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
16949 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
16950 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
16951 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
16952 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
16953 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
16954 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
16955 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
16956 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
16957 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
16958 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
16959 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
16960 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
16961 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
16962 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
16963 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
16964 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
16965 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
16966 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
16967 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
16968 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
16969 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
16970 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
16971
16972 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
16973
16974 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
16975 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
16976 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
16977 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
16978 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
16979 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
16980 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
16981 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
16982 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
16983 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
16984 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
16985 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
16986 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
16987 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
16988 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
16989 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
16990 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
16991 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
16992 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
16993 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
16994 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
16995 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
16996 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
16997 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
16998 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
16999 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
17000 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
17001 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
17002 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
17003 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
17004 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
17005 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
17006 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
17007 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
17008 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
17009 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
17010 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
17011 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
17012 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
17013 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
17014 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
17015 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
17016 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
17017 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
17018 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
17019 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
17020 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
17021 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
17022 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
17023 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
17024 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
17025 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
17026 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
17027 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
17028 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
17029 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
17030 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
17031 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
17032 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
17033 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
17034 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
17035 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
17036 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
17037 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
17038 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
17039 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
17040 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
17041 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
17042 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
17043 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
17044 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
17045 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
17046 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
17047 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
17048 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
17049 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
17050 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
17051 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
17052 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
17053 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
17054 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
17055
17056 /******************** Bit definition for USB_OTG_DAINT register ********************/
17057 #define USB_OTG_DAINT_IEPINT_Pos (0U)
17058 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
17059 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
17060 #define USB_OTG_DAINT_OEPINT_Pos (16U)
17061 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
17062 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
17063
17064 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
17065 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
17066 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
17067 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
17068
17069 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
17070 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
17071 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
17072 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
17073 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
17074 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
17075 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
17076 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
17077 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
17078 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
17079 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
17080 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
17081 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
17082
17083 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
17084 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
17085 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
17086 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
17087 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
17088 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
17089 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
17090
17091 /******************** Bit definition for OTG register ********************/
17092
17093 #define USB_OTG_CHNUM_Pos (0U)
17094 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
17095 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
17096 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
17097 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
17098 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
17099 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
17100 #define USB_OTG_BCNT_Pos (4U)
17101 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
17102 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
17103 #define USB_OTG_DPID_Pos (15U)
17104 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
17105 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
17106 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
17107 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
17108 #define USB_OTG_PKTSTS_Pos (17U)
17109 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
17110 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
17111 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
17112 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
17113 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
17114 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
17115 #define USB_OTG_EPNUM_Pos (0U)
17116 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
17117 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
17118 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
17119 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
17120 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
17121 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
17122 #define USB_OTG_FRMNUM_Pos (21U)
17123 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
17124 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
17125 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
17126 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
17127 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
17128 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
17129
17130 /******************** Bit definition for OTG register ********************/
17131
17132 #define USB_OTG_CHNUM_Pos (0U)
17133 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
17134 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
17135 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
17136 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
17137 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
17138 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
17139 #define USB_OTG_BCNT_Pos (4U)
17140 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
17141 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
17142 #define USB_OTG_DPID_Pos (15U)
17143 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
17144 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
17145 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
17146 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
17147 #define USB_OTG_PKTSTS_Pos (17U)
17148 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
17149 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
17150 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
17151 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
17152 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
17153 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
17154 #define USB_OTG_EPNUM_Pos (0U)
17155 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
17156 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
17157 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
17158 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
17159 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
17160 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
17161 #define USB_OTG_FRMNUM_Pos (21U)
17162 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
17163 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
17164 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
17165 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
17166 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
17167 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
17168
17169 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
17170 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
17171 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
17172 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
17173
17174 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
17175 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
17176 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
17177 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
17178
17179 /******************** Bit definition for OTG register ********************/
17180 #define USB_OTG_NPTXFSA_Pos (0U)
17181 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
17182 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
17183 #define USB_OTG_NPTXFD_Pos (16U)
17184 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
17185 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
17186 #define USB_OTG_TX0FSA_Pos (0U)
17187 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
17188 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
17189 #define USB_OTG_TX0FD_Pos (16U)
17190 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
17191 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
17192
17193 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
17194 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
17195 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
17196 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
17197
17198 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
17199 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
17200 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
17201 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
17202
17203 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
17204 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
17205 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
17206 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
17207 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
17208 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
17209 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
17210 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
17211 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
17212 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
17213 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
17214
17215 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
17216 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
17217 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
17218 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
17219 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
17220 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
17221 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
17222 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
17223 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
17224 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
17225
17226 /******************** Bit definition for USB_OTG_DTHRCTL register ***************/
17227 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
17228 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
17229 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
17230 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
17231 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
17232 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
17233
17234 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
17235 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
17236 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
17237 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
17238 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
17239 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
17240 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
17241 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
17242 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
17243 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
17244 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
17245 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
17246 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
17247 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
17248 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
17249
17250 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
17251 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
17252 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
17253 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
17254 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
17255 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
17256 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
17257 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
17258 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
17259 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
17260 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
17261 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
17262 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
17263 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
17264 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
17265
17266 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
17267 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
17268 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
17269 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
17270
17271 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
17272 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
17273 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
17274 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
17275 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
17276 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
17277 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
17278
17279 /******************** Bit definition for USB_OTG_GCCFG register ********************/
17280 #define USB_OTG_GCCFG_DCDET_Pos (0U)
17281 #define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
17282 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
17283 #define USB_OTG_GCCFG_PDET_Pos (1U)
17284 #define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
17285 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
17286 #define USB_OTG_GCCFG_SDET_Pos (2U)
17287 #define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
17288 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
17289 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
17290 #define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
17291 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
17292 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
17293 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
17294 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
17295 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
17296 #define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
17297 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
17298 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
17299 #define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
17300 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
17301 #define USB_OTG_GCCFG_PDEN_Pos (19U)
17302 #define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
17303 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
17304 #define USB_OTG_GCCFG_SDEN_Pos (20U)
17305 #define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
17306 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
17307 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
17308 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
17309 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
17310
17311 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
17312 #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U)
17313 #define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
17314 #define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
17315
17316 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
17317 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
17318 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
17319 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
17320 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
17321 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
17322 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
17323
17324 /******************** Bit definition for USB_OTG_CID register ********************/
17325 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
17326 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
17327 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
17328
17329
17330 /******************** Bit definition for USB_OTG_GHWCFG3 register ********************/
17331 #define USB_OTG_GHWCFG3_LPMMode_Pos (14U)
17332 #define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
17333 #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */
17334
17335 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
17336 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
17337 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
17338 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */
17339 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
17340 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
17341 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
17342 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
17343 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
17344 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */
17345 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
17346 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
17347 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */
17348 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
17349 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
17350 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */
17351 #define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U)
17352 #define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
17353 #define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */
17354 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
17355 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
17356 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */
17357 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
17358 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
17359 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */
17360 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
17361 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
17362 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */
17363 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
17364 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
17365 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */
17366 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
17367 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
17368 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */
17369 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
17370 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
17371 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */
17372 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
17373 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
17374 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */
17375 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
17376 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
17377 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
17378 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
17379 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
17380 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */
17381
17382
17383 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
17384 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
17385 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
17386 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
17387 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
17388 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
17389 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
17390 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
17391 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
17392 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
17393 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
17394 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
17395 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
17396 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
17397 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
17398 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
17399 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
17400 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
17401 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
17402 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
17403 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
17404 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
17405 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
17406 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
17407 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
17408 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
17409 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
17410 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
17411
17412 /******************** Bit definition for USB_OTG_HPRT register ********************/
17413 #define USB_OTG_HPRT_PCSTS_Pos (0U)
17414 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
17415 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
17416 #define USB_OTG_HPRT_PCDET_Pos (1U)
17417 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
17418 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
17419 #define USB_OTG_HPRT_PENA_Pos (2U)
17420 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
17421 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
17422 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
17423 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
17424 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
17425 #define USB_OTG_HPRT_POCA_Pos (4U)
17426 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
17427 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
17428 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
17429 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
17430 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
17431 #define USB_OTG_HPRT_PRES_Pos (6U)
17432 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
17433 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
17434 #define USB_OTG_HPRT_PSUSP_Pos (7U)
17435 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
17436 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
17437 #define USB_OTG_HPRT_PRST_Pos (8U)
17438 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
17439 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
17440
17441 #define USB_OTG_HPRT_PLSTS_Pos (10U)
17442 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
17443 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
17444 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
17445 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
17446 #define USB_OTG_HPRT_PPWR_Pos (12U)
17447 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
17448 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
17449
17450 #define USB_OTG_HPRT_PTCTL_Pos (13U)
17451 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
17452 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
17453 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
17454 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
17455 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
17456 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
17457
17458 #define USB_OTG_HPRT_PSPD_Pos (17U)
17459 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
17460 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
17461 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
17462 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
17463
17464 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
17465 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
17466 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
17467 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
17468 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
17469 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
17470 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
17471 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
17472 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
17473 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
17474 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
17475 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
17476 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
17477 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
17478 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
17479 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
17480 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
17481 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
17482 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
17483 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
17484 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
17485 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
17486 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
17487 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
17488 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
17489 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
17490 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
17491 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
17492 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
17493 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
17494 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
17495 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
17496 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
17497 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
17498
17499 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
17500 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
17501 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
17502 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
17503 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
17504 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
17505 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
17506
17507 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
17508 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
17509 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
17510 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
17511 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
17512 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
17513 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
17514 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
17515 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
17516 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
17517 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
17518 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
17519 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
17520
17521 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
17522 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
17523 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
17524 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
17525 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
17526 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
17527 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
17528 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
17529
17530 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
17531 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
17532 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
17533 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
17534 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
17535 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
17536 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
17537 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
17538 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
17539 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
17540 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
17541 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
17542 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
17543 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
17544 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
17545 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
17546 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
17547 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
17548 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
17549 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
17550 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
17551 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
17552 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
17553 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
17554 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
17555
17556 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
17557 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
17558 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
17559 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
17560
17561 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
17562 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
17563 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
17564 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
17565 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
17566 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
17567 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
17568 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
17569 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
17570 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
17571 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
17572 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
17573 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
17574
17575 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
17576 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
17577 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
17578 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
17579 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
17580
17581 #define USB_OTG_HCCHAR_MC_Pos (20U)
17582 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
17583 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
17584 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
17585 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
17586
17587 #define USB_OTG_HCCHAR_DAD_Pos (22U)
17588 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
17589 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
17590 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
17591 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
17592 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
17593 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
17594 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
17595 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
17596 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
17597 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
17598 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
17599 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
17600 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
17601 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
17602 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
17603 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
17604 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
17605 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
17606
17607 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
17608
17609 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
17610 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
17611 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
17612 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
17613 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
17614 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
17615 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
17616 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
17617 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
17618 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
17619
17620 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
17621 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
17622 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
17623 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
17624 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
17625 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
17626 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
17627 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
17628 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
17629 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
17630
17631 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
17632 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
17633 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
17634 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
17635 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
17636 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
17637 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
17638 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
17639 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
17640 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
17641 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
17642
17643 /******************** Bit definition for USB_OTG_HCINT register ********************/
17644 #define USB_OTG_HCINT_XFRC_Pos (0U)
17645 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
17646 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
17647 #define USB_OTG_HCINT_CHH_Pos (1U)
17648 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
17649 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
17650 #define USB_OTG_HCINT_AHBERR_Pos (2U)
17651 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
17652 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
17653 #define USB_OTG_HCINT_STALL_Pos (3U)
17654 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
17655 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
17656 #define USB_OTG_HCINT_NAK_Pos (4U)
17657 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
17658 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
17659 #define USB_OTG_HCINT_ACK_Pos (5U)
17660 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
17661 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
17662 #define USB_OTG_HCINT_NYET_Pos (6U)
17663 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
17664 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
17665 #define USB_OTG_HCINT_TXERR_Pos (7U)
17666 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
17667 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
17668 #define USB_OTG_HCINT_BBERR_Pos (8U)
17669 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
17670 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
17671 #define USB_OTG_HCINT_FRMOR_Pos (9U)
17672 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
17673 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
17674 #define USB_OTG_HCINT_DTERR_Pos (10U)
17675 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
17676 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
17677
17678 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
17679 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
17680 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
17681 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
17682 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
17683 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
17684 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
17685 #define USB_OTG_DIEPINT_TOC_Pos (3U)
17686 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
17687 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
17688 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
17689 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
17690 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
17691 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
17692 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
17693 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
17694 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
17695 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
17696 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
17697 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
17698 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
17699 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
17700 #define USB_OTG_DIEPINT_BNA_Pos (9U)
17701 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
17702 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
17703 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
17704 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
17705 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
17706 #define USB_OTG_DIEPINT_BERR_Pos (12U)
17707 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
17708 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
17709 #define USB_OTG_DIEPINT_NAK_Pos (13U)
17710 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
17711 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
17712
17713 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
17714 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
17715 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
17716 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
17717 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
17718 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
17719 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
17720 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
17721 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
17722 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
17723 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
17724 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
17725 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
17726 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
17727 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
17728 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
17729 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
17730 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
17731 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
17732 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
17733 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
17734 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
17735 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
17736 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
17737 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
17738 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
17739 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
17740 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
17741 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
17742 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
17743 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
17744 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
17745 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
17746 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
17747
17748 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
17749
17750 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
17751 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17752 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
17753 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
17754 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17755 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
17756 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
17757 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
17758 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
17759 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
17760 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
17761 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17762 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
17763 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
17764 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17765 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
17766 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
17767 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
17768 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
17769 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
17770 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
17771 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
17772 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
17773 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
17774
17775 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
17776 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
17777 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
17778 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
17779
17780 /******************** Bit definition for USB_OTG_HCDMA register ********************/
17781 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
17782 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
17783 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
17784
17785 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
17786 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
17787 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
17788 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
17789
17790 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
17791 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
17792 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
17793 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
17794 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
17795 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
17796 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
17797
17798 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
17799
17800 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
17801 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
17802 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
17803 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
17804 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
17805 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
17806 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
17807 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
17808 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
17809 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
17810 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
17811 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
17812 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
17813 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
17814 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
17815 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
17816 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
17817 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
17818 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
17819 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
17820 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
17821 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
17822 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
17823 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
17824 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
17825 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
17826 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
17827 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
17828 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
17829 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
17830 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
17831 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
17832 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
17833 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
17834 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
17835 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
17836 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
17837 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
17838
17839 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
17840 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
17841 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
17842 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
17843 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
17844 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
17845 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
17846 #define USB_OTG_DOEPINT_STUP_Pos (3U)
17847 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
17848 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
17849 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
17850 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
17851 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
17852 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
17853 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
17854 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
17855 #define USB_OTG_DOEPINT_NYET_Pos (14U)
17856 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
17857 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
17858
17859 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
17860
17861 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
17862 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
17863 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
17864 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
17865 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
17866 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
17867
17868 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
17869 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
17870 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
17871 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
17872 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
17873
17874 /******************** Bit definition for PCGCCTL register ********************/
17875 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
17876 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
17877 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
17878 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
17879 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
17880 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
17881 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
17882 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
17883 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
17884
17885
17886 /**
17887 * @}
17888 */
17889
17890 /**
17891 * @}
17892 */
17893
17894 /** @addtogroup Exported_macros
17895 * @{
17896 */
17897
17898 /******************************* ADC Instances ********************************/
17899 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
17900 ((INSTANCE) == ADC2) || \
17901 ((INSTANCE) == ADC3))
17902
17903 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
17904
17905 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
17906
17907 /******************************** CAN Instances ******************************/
17908 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
17909
17910 /******************************** COMP Instances ******************************/
17911 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
17912 ((INSTANCE) == COMP2))
17913
17914 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
17915
17916 /******************** COMP Instances with window mode capability **************/
17917 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
17918
17919 /******************************* CRC Instances ********************************/
17920 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
17921
17922 /******************************* DAC Instances ********************************/
17923 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
17924
17925 /****************************** DFSDM Instances *******************************/
17926 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
17927 ((INSTANCE) == DFSDM1_Filter1) || \
17928 ((INSTANCE) == DFSDM1_Filter2) || \
17929 ((INSTANCE) == DFSDM1_Filter3))
17930
17931 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
17932 ((INSTANCE) == DFSDM1_Channel1) || \
17933 ((INSTANCE) == DFSDM1_Channel2) || \
17934 ((INSTANCE) == DFSDM1_Channel3) || \
17935 ((INSTANCE) == DFSDM1_Channel4) || \
17936 ((INSTANCE) == DFSDM1_Channel5) || \
17937 ((INSTANCE) == DFSDM1_Channel6) || \
17938 ((INSTANCE) == DFSDM1_Channel7))
17939
17940 /******************************** DMA Instances *******************************/
17941 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
17942 ((INSTANCE) == DMA1_Channel2) || \
17943 ((INSTANCE) == DMA1_Channel3) || \
17944 ((INSTANCE) == DMA1_Channel4) || \
17945 ((INSTANCE) == DMA1_Channel5) || \
17946 ((INSTANCE) == DMA1_Channel6) || \
17947 ((INSTANCE) == DMA1_Channel7) || \
17948 ((INSTANCE) == DMA2_Channel1) || \
17949 ((INSTANCE) == DMA2_Channel2) || \
17950 ((INSTANCE) == DMA2_Channel3) || \
17951 ((INSTANCE) == DMA2_Channel4) || \
17952 ((INSTANCE) == DMA2_Channel5) || \
17953 ((INSTANCE) == DMA2_Channel6) || \
17954 ((INSTANCE) == DMA2_Channel7))
17955
17956 /******************************* GPIO Instances *******************************/
17957 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
17958 ((INSTANCE) == GPIOB) || \
17959 ((INSTANCE) == GPIOC) || \
17960 ((INSTANCE) == GPIOD) || \
17961 ((INSTANCE) == GPIOE) || \
17962 ((INSTANCE) == GPIOF) || \
17963 ((INSTANCE) == GPIOG) || \
17964 ((INSTANCE) == GPIOH))
17965
17966 /******************************* GPIO AF Instances ****************************/
17967 /* On L4, all GPIO Bank support AF */
17968 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
17969
17970 /**************************** GPIO Lock Instances *****************************/
17971 /* On L4, all GPIO Bank support the Lock mechanism */
17972 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
17973
17974 /******************************** I2C Instances *******************************/
17975 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
17976 ((INSTANCE) == I2C2) || \
17977 ((INSTANCE) == I2C3))
17978
17979 /****************** I2C Instances : wakeup capability from stop modes *********/
17980 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
17981
17982 /******************************* LCD Instances ********************************/
17983 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
17984
17985 /******************************* HCD Instances *******************************/
17986 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
17987
17988 /****************************** OPAMP Instances *******************************/
17989 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
17990 ((INSTANCE) == OPAMP2))
17991
17992 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
17993
17994 /******************************* PCD Instances *******************************/
17995 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
17996
17997 /******************************* QSPI Instances *******************************/
17998 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
17999
18000 /******************************* RNG Instances ********************************/
18001 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
18002
18003 /****************************** RTC Instances *********************************/
18004 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
18005
18006 /******************************** SAI Instances *******************************/
18007 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
18008 ((INSTANCE) == SAI1_Block_B) || \
18009 ((INSTANCE) == SAI2_Block_A) || \
18010 ((INSTANCE) == SAI2_Block_B))
18011
18012 /****************************** SDMMC Instances *******************************/
18013 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
18014
18015 /****************************** SMBUS Instances *******************************/
18016 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
18017 ((INSTANCE) == I2C2) || \
18018 ((INSTANCE) == I2C3))
18019
18020 /******************************** SPI Instances *******************************/
18021 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
18022 ((INSTANCE) == SPI2) || \
18023 ((INSTANCE) == SPI3))
18024
18025 /******************************** SWPMI Instances *****************************/
18026 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
18027
18028 /****************** LPTIM Instances : All supported instances *****************/
18029 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
18030 ((INSTANCE) == LPTIM2))
18031
18032 /****************** TIM Instances : All supported instances *******************/
18033 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18034 ((INSTANCE) == TIM2) || \
18035 ((INSTANCE) == TIM3) || \
18036 ((INSTANCE) == TIM4) || \
18037 ((INSTANCE) == TIM5) || \
18038 ((INSTANCE) == TIM6) || \
18039 ((INSTANCE) == TIM7) || \
18040 ((INSTANCE) == TIM8) || \
18041 ((INSTANCE) == TIM15) || \
18042 ((INSTANCE) == TIM16) || \
18043 ((INSTANCE) == TIM17))
18044
18045 /****************** TIM Instances : supporting 32 bits counter ****************/
18046 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
18047 ((INSTANCE) == TIM5))
18048
18049 /****************** TIM Instances : supporting the break function *************/
18050 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18051 ((INSTANCE) == TIM8) || \
18052 ((INSTANCE) == TIM15) || \
18053 ((INSTANCE) == TIM16) || \
18054 ((INSTANCE) == TIM17))
18055
18056 /************** TIM Instances : supporting Break source selection *************/
18057 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18058 ((INSTANCE) == TIM8) || \
18059 ((INSTANCE) == TIM15) || \
18060 ((INSTANCE) == TIM16) || \
18061 ((INSTANCE) == TIM17))
18062
18063 /****************** TIM Instances : supporting 2 break inputs *****************/
18064 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18065 ((INSTANCE) == TIM8))
18066
18067 /************* TIM Instances : at least 1 capture/compare channel *************/
18068 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18069 ((INSTANCE) == TIM2) || \
18070 ((INSTANCE) == TIM3) || \
18071 ((INSTANCE) == TIM4) || \
18072 ((INSTANCE) == TIM5) || \
18073 ((INSTANCE) == TIM8) || \
18074 ((INSTANCE) == TIM15) || \
18075 ((INSTANCE) == TIM16) || \
18076 ((INSTANCE) == TIM17))
18077
18078 /************ TIM Instances : at least 2 capture/compare channels *************/
18079 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18080 ((INSTANCE) == TIM2) || \
18081 ((INSTANCE) == TIM3) || \
18082 ((INSTANCE) == TIM4) || \
18083 ((INSTANCE) == TIM5) || \
18084 ((INSTANCE) == TIM8) || \
18085 ((INSTANCE) == TIM15))
18086
18087 /************ TIM Instances : at least 3 capture/compare channels *************/
18088 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18089 ((INSTANCE) == TIM2) || \
18090 ((INSTANCE) == TIM3) || \
18091 ((INSTANCE) == TIM4) || \
18092 ((INSTANCE) == TIM5) || \
18093 ((INSTANCE) == TIM8))
18094
18095 /************ TIM Instances : at least 4 capture/compare channels *************/
18096 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18097 ((INSTANCE) == TIM2) || \
18098 ((INSTANCE) == TIM3) || \
18099 ((INSTANCE) == TIM4) || \
18100 ((INSTANCE) == TIM5) || \
18101 ((INSTANCE) == TIM8))
18102
18103 /****************** TIM Instances : at least 5 capture/compare channels *******/
18104 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18105 ((INSTANCE) == TIM8))
18106
18107 /****************** TIM Instances : at least 6 capture/compare channels *******/
18108 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18109 ((INSTANCE) == TIM8))
18110
18111 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
18112 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18113 ((INSTANCE) == TIM8) || \
18114 ((INSTANCE) == TIM15) || \
18115 ((INSTANCE) == TIM16) || \
18116 ((INSTANCE) == TIM17))
18117
18118 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
18119 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18120 ((INSTANCE) == TIM2) || \
18121 ((INSTANCE) == TIM3) || \
18122 ((INSTANCE) == TIM4) || \
18123 ((INSTANCE) == TIM5) || \
18124 ((INSTANCE) == TIM6) || \
18125 ((INSTANCE) == TIM7) || \
18126 ((INSTANCE) == TIM8) || \
18127 ((INSTANCE) == TIM15) || \
18128 ((INSTANCE) == TIM16) || \
18129 ((INSTANCE) == TIM17))
18130
18131 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
18132 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18133 ((INSTANCE) == TIM2) || \
18134 ((INSTANCE) == TIM3) || \
18135 ((INSTANCE) == TIM4) || \
18136 ((INSTANCE) == TIM5) || \
18137 ((INSTANCE) == TIM8) || \
18138 ((INSTANCE) == TIM15) || \
18139 ((INSTANCE) == TIM16) || \
18140 ((INSTANCE) == TIM17))
18141
18142 /******************** TIM Instances : DMA burst feature ***********************/
18143 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18144 ((INSTANCE) == TIM2) || \
18145 ((INSTANCE) == TIM3) || \
18146 ((INSTANCE) == TIM4) || \
18147 ((INSTANCE) == TIM5) || \
18148 ((INSTANCE) == TIM8) || \
18149 ((INSTANCE) == TIM15) || \
18150 ((INSTANCE) == TIM16) || \
18151 ((INSTANCE) == TIM17))
18152
18153 /******************* TIM Instances : output(s) available **********************/
18154 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
18155 ((((INSTANCE) == TIM1) && \
18156 (((CHANNEL) == TIM_CHANNEL_1) || \
18157 ((CHANNEL) == TIM_CHANNEL_2) || \
18158 ((CHANNEL) == TIM_CHANNEL_3) || \
18159 ((CHANNEL) == TIM_CHANNEL_4) || \
18160 ((CHANNEL) == TIM_CHANNEL_5) || \
18161 ((CHANNEL) == TIM_CHANNEL_6))) \
18162 || \
18163 (((INSTANCE) == TIM2) && \
18164 (((CHANNEL) == TIM_CHANNEL_1) || \
18165 ((CHANNEL) == TIM_CHANNEL_2) || \
18166 ((CHANNEL) == TIM_CHANNEL_3) || \
18167 ((CHANNEL) == TIM_CHANNEL_4))) \
18168 || \
18169 (((INSTANCE) == TIM3) && \
18170 (((CHANNEL) == TIM_CHANNEL_1) || \
18171 ((CHANNEL) == TIM_CHANNEL_2) || \
18172 ((CHANNEL) == TIM_CHANNEL_3) || \
18173 ((CHANNEL) == TIM_CHANNEL_4))) \
18174 || \
18175 (((INSTANCE) == TIM4) && \
18176 (((CHANNEL) == TIM_CHANNEL_1) || \
18177 ((CHANNEL) == TIM_CHANNEL_2) || \
18178 ((CHANNEL) == TIM_CHANNEL_3) || \
18179 ((CHANNEL) == TIM_CHANNEL_4))) \
18180 || \
18181 (((INSTANCE) == TIM5) && \
18182 (((CHANNEL) == TIM_CHANNEL_1) || \
18183 ((CHANNEL) == TIM_CHANNEL_2) || \
18184 ((CHANNEL) == TIM_CHANNEL_3) || \
18185 ((CHANNEL) == TIM_CHANNEL_4))) \
18186 || \
18187 (((INSTANCE) == TIM8) && \
18188 (((CHANNEL) == TIM_CHANNEL_1) || \
18189 ((CHANNEL) == TIM_CHANNEL_2) || \
18190 ((CHANNEL) == TIM_CHANNEL_3) || \
18191 ((CHANNEL) == TIM_CHANNEL_4) || \
18192 ((CHANNEL) == TIM_CHANNEL_5) || \
18193 ((CHANNEL) == TIM_CHANNEL_6))) \
18194 || \
18195 (((INSTANCE) == TIM15) && \
18196 (((CHANNEL) == TIM_CHANNEL_1) || \
18197 ((CHANNEL) == TIM_CHANNEL_2))) \
18198 || \
18199 (((INSTANCE) == TIM16) && \
18200 (((CHANNEL) == TIM_CHANNEL_1))) \
18201 || \
18202 (((INSTANCE) == TIM17) && \
18203 (((CHANNEL) == TIM_CHANNEL_1))))
18204
18205 /****************** TIM Instances : supporting complementary output(s) ********/
18206 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
18207 ((((INSTANCE) == TIM1) && \
18208 (((CHANNEL) == TIM_CHANNEL_1) || \
18209 ((CHANNEL) == TIM_CHANNEL_2) || \
18210 ((CHANNEL) == TIM_CHANNEL_3))) \
18211 || \
18212 (((INSTANCE) == TIM8) && \
18213 (((CHANNEL) == TIM_CHANNEL_1) || \
18214 ((CHANNEL) == TIM_CHANNEL_2) || \
18215 ((CHANNEL) == TIM_CHANNEL_3))) \
18216 || \
18217 (((INSTANCE) == TIM15) && \
18218 ((CHANNEL) == TIM_CHANNEL_1)) \
18219 || \
18220 (((INSTANCE) == TIM16) && \
18221 ((CHANNEL) == TIM_CHANNEL_1)) \
18222 || \
18223 (((INSTANCE) == TIM17) && \
18224 ((CHANNEL) == TIM_CHANNEL_1)))
18225
18226 /****************** TIM Instances : supporting clock division *****************/
18227 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18228 ((INSTANCE) == TIM2) || \
18229 ((INSTANCE) == TIM3) || \
18230 ((INSTANCE) == TIM4) || \
18231 ((INSTANCE) == TIM5) || \
18232 ((INSTANCE) == TIM8) || \
18233 ((INSTANCE) == TIM15) || \
18234 ((INSTANCE) == TIM16) || \
18235 ((INSTANCE) == TIM17))
18236
18237 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
18238 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18239 ((INSTANCE) == TIM2) || \
18240 ((INSTANCE) == TIM3) || \
18241 ((INSTANCE) == TIM4) || \
18242 ((INSTANCE) == TIM5) || \
18243 ((INSTANCE) == TIM8) || \
18244 ((INSTANCE) == TIM15))
18245
18246 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
18247 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18248 ((INSTANCE) == TIM2) || \
18249 ((INSTANCE) == TIM3) || \
18250 ((INSTANCE) == TIM4) || \
18251 ((INSTANCE) == TIM5) || \
18252 ((INSTANCE) == TIM8))
18253
18254 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
18255 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18256 ((INSTANCE) == TIM2) || \
18257 ((INSTANCE) == TIM3) || \
18258 ((INSTANCE) == TIM4) || \
18259 ((INSTANCE) == TIM5) || \
18260 ((INSTANCE) == TIM8) || \
18261 ((INSTANCE) == TIM15))
18262
18263 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
18264 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18265 ((INSTANCE) == TIM2) || \
18266 ((INSTANCE) == TIM3) || \
18267 ((INSTANCE) == TIM4) || \
18268 ((INSTANCE) == TIM5) || \
18269 ((INSTANCE) == TIM8) || \
18270 ((INSTANCE) == TIM15))
18271
18272 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
18273 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18274 ((INSTANCE) == TIM8))
18275
18276 /****************** TIM Instances : supporting commutation event generation ***/
18277 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18278 ((INSTANCE) == TIM8) || \
18279 ((INSTANCE) == TIM15) || \
18280 ((INSTANCE) == TIM16) || \
18281 ((INSTANCE) == TIM17))
18282
18283 /****************** TIM Instances : supporting counting mode selection ********/
18284 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18285 ((INSTANCE) == TIM2) || \
18286 ((INSTANCE) == TIM3) || \
18287 ((INSTANCE) == TIM4) || \
18288 ((INSTANCE) == TIM5) || \
18289 ((INSTANCE) == TIM8))
18290
18291 /****************** TIM Instances : supporting encoder interface **************/
18292 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18293 ((INSTANCE) == TIM2) || \
18294 ((INSTANCE) == TIM3) || \
18295 ((INSTANCE) == TIM4) || \
18296 ((INSTANCE) == TIM5) || \
18297 ((INSTANCE) == TIM8))
18298
18299 /****************** TIM Instances : supporting Hall sensor interface **********/
18300 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18301 ((INSTANCE) == TIM2) || \
18302 ((INSTANCE) == TIM3) || \
18303 ((INSTANCE) == TIM4) || \
18304 ((INSTANCE) == TIM5))
18305
18306 /**************** TIM Instances : external trigger input available ************/
18307 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18308 ((INSTANCE) == TIM2) || \
18309 ((INSTANCE) == TIM3) || \
18310 ((INSTANCE) == TIM4) || \
18311 ((INSTANCE) == TIM5) || \
18312 ((INSTANCE) == TIM8))
18313
18314 /************* TIM Instances : supporting ETR source selection ***************/
18315 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18316 ((INSTANCE) == TIM2) || \
18317 ((INSTANCE) == TIM3) || \
18318 ((INSTANCE) == TIM8))
18319
18320 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
18321 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18322 ((INSTANCE) == TIM2) || \
18323 ((INSTANCE) == TIM3) || \
18324 ((INSTANCE) == TIM4) || \
18325 ((INSTANCE) == TIM5) || \
18326 ((INSTANCE) == TIM6) || \
18327 ((INSTANCE) == TIM7) || \
18328 ((INSTANCE) == TIM8) || \
18329 ((INSTANCE) == TIM15))
18330
18331 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
18332 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18333 ((INSTANCE) == TIM2) || \
18334 ((INSTANCE) == TIM3) || \
18335 ((INSTANCE) == TIM4) || \
18336 ((INSTANCE) == TIM5) || \
18337 ((INSTANCE) == TIM8) || \
18338 ((INSTANCE) == TIM15))
18339
18340 /****************** TIM Instances : supporting OCxREF clear *******************/
18341 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18342 ((INSTANCE) == TIM2) || \
18343 ((INSTANCE) == TIM3) || \
18344 ((INSTANCE) == TIM4) || \
18345 ((INSTANCE) == TIM5) || \
18346 ((INSTANCE) == TIM8))
18347
18348 /****************** TIM Instances : remapping capability **********************/
18349 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18350 ((INSTANCE) == TIM2) || \
18351 ((INSTANCE) == TIM3) || \
18352 ((INSTANCE) == TIM8) || \
18353 ((INSTANCE) == TIM15) || \
18354 ((INSTANCE) == TIM16) || \
18355 ((INSTANCE) == TIM17))
18356
18357 /****************** TIM Instances : supporting repetition counter *************/
18358 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18359 ((INSTANCE) == TIM8) || \
18360 ((INSTANCE) == TIM15) || \
18361 ((INSTANCE) == TIM16) || \
18362 ((INSTANCE) == TIM17))
18363
18364 /****************** TIM Instances : supporting synchronization ****************/
18365 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
18366
18367 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
18368 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18369 ((INSTANCE) == TIM8))
18370
18371 /******************* TIM Instances : Timer input XOR function *****************/
18372 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18373 ((INSTANCE) == TIM2) || \
18374 ((INSTANCE) == TIM3) || \
18375 ((INSTANCE) == TIM4) || \
18376 ((INSTANCE) == TIM5) || \
18377 ((INSTANCE) == TIM8) || \
18378 ((INSTANCE) == TIM15))
18379
18380 /****************** TIM Instances : Advanced timer instances *******************/
18381 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
18382 ((INSTANCE) == TIM8))
18383
18384 /****************************** TSC Instances *********************************/
18385 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
18386
18387 /******************** USART Instances : Synchronous mode **********************/
18388 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18389 ((INSTANCE) == USART2) || \
18390 ((INSTANCE) == USART3))
18391
18392 /******************** UART Instances : Asynchronous mode **********************/
18393 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18394 ((INSTANCE) == USART2) || \
18395 ((INSTANCE) == USART3) || \
18396 ((INSTANCE) == UART4) || \
18397 ((INSTANCE) == UART5))
18398
18399 /****************** UART Instances : Auto Baud Rate detection ****************/
18400 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18401 ((INSTANCE) == USART2) || \
18402 ((INSTANCE) == USART3) || \
18403 ((INSTANCE) == UART4) || \
18404 ((INSTANCE) == UART5))
18405
18406 /****************** UART Instances : Driver Enable *****************/
18407 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18408 ((INSTANCE) == USART2) || \
18409 ((INSTANCE) == USART3) || \
18410 ((INSTANCE) == UART4) || \
18411 ((INSTANCE) == UART5) || \
18412 ((INSTANCE) == LPUART1))
18413
18414 /******************** UART Instances : Half-Duplex mode **********************/
18415 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18416 ((INSTANCE) == USART2) || \
18417 ((INSTANCE) == USART3) || \
18418 ((INSTANCE) == UART4) || \
18419 ((INSTANCE) == UART5) || \
18420 ((INSTANCE) == LPUART1))
18421
18422 /****************** UART Instances : Hardware Flow control ********************/
18423 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18424 ((INSTANCE) == USART2) || \
18425 ((INSTANCE) == USART3) || \
18426 ((INSTANCE) == UART4) || \
18427 ((INSTANCE) == UART5) || \
18428 ((INSTANCE) == LPUART1))
18429
18430 /******************** UART Instances : LIN mode **********************/
18431 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18432 ((INSTANCE) == USART2) || \
18433 ((INSTANCE) == USART3) || \
18434 ((INSTANCE) == UART4) || \
18435 ((INSTANCE) == UART5))
18436
18437 /******************** UART Instances : Wake-up from Stop mode **********************/
18438 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18439 ((INSTANCE) == USART2) || \
18440 ((INSTANCE) == USART3) || \
18441 ((INSTANCE) == UART4) || \
18442 ((INSTANCE) == UART5) || \
18443 ((INSTANCE) == LPUART1))
18444
18445 /*********************** UART Instances : IRDA mode ***************************/
18446 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18447 ((INSTANCE) == USART2) || \
18448 ((INSTANCE) == USART3) || \
18449 ((INSTANCE) == UART4) || \
18450 ((INSTANCE) == UART5))
18451
18452 /********************* USART Instances : Smard card mode ***********************/
18453 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
18454 ((INSTANCE) == USART2) || \
18455 ((INSTANCE) == USART3))
18456
18457 /******************** LPUART Instance *****************************************/
18458 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
18459
18460 /****************************** IWDG Instances ********************************/
18461 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
18462
18463 /****************************** WWDG Instances ********************************/
18464 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
18465
18466 /**
18467 * @}
18468 */
18469
18470
18471 /******************************************************************************/
18472 /* For a painless codes migration between the STM32L4xx device product */
18473 /* lines, the aliases defined below are put in place to overcome the */
18474 /* differences in the interrupt handlers and IRQn definitions. */
18475 /* No need to update developed interrupt code when moving across */
18476 /* product lines within the same STM32L4 Family */
18477 /******************************************************************************/
18478
18479 /* Aliases for __IRQn */
18480 #define ADC1_IRQn ADC1_2_IRQn
18481 #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
18482 #define TIM8_IRQn TIM8_UP_IRQn
18483 #define DFSDM0_IRQn DFSDM1_FLT0_IRQn
18484 #define DFSDM1_IRQn DFSDM1_FLT1_IRQn
18485 #define DFSDM2_IRQn DFSDM1_FLT2_IRQn
18486 #define DFSDM3_IRQn DFSDM1_FLT3_IRQn
18487
18488 /* Aliases for __IRQHandler */
18489 #define ADC1_IRQHandler ADC1_2_IRQHandler
18490 #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
18491 #define TIM8_IRQHandler TIM8_UP_IRQHandler
18492 #define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
18493 #define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
18494 #define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
18495 #define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
18496
18497 #ifdef __cplusplus
18498 }
18499 #endif /* __cplusplus */
18500
18501 #endif /* __STM32L476xx_H */
18502
18503 /**
18504 * @}
18505 */
18506
18507 /**
18508 * @}
18509 */
18510
18511 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/