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comparison l476rg/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h @ 0:32a3b1785697

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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal.h
4 * @author MCD Application Team
5 * @version V1.6.0
6 * @date 28-October-2016
7 * @brief This file contains all the functions prototypes for the HAL
8 * module driver.
9 ******************************************************************************
10 * @attention
11 *
12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
13 *
14 * Redistribution and use in source and binary forms, with or without modification,
15 * are permitted provided that the following conditions are met:
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef __STM32L4xx_HAL_H
41 #define __STM32L4xx_HAL_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32l4xx_hal_conf.h"
49
50 /** @addtogroup STM32L4xx_HAL_Driver
51 * @{
52 */
53
54 /** @addtogroup HAL
55 * @{
56 */
57
58 /* Exported types ------------------------------------------------------------*/
59 /* Exported constants --------------------------------------------------------*/
60 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
61 * @{
62 */
63
64 /** @defgroup SYSCFG_BootMode Boot Mode
65 * @{
66 */
67 #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
68 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
69
70 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
71 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1
72 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
73
74 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
75
76 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
77
78 /**
79 * @}
80 */
81
82 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
83 * @{
84 */
85 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
86 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
87 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
88 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
89 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
90 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
91
92 /**
93 * @}
94 */
95
96 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection
97 * @{
98 */
99 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
100 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
101 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
102 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
103 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
104 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
105 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
106 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
107 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
108 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
109 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
110 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
111 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
112 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
113 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
114 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
115 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
116 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
117 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
118 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
119 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
120 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
121 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
122 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
123 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
124 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
125 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
126 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
127 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
128 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
129 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
130 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
131
132 /**
133 * @}
134 */
135
136 #if defined(VREFBUF)
137 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
138 * @{
139 */
140 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
141 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
142
143 /**
144 * @}
145 */
146
147 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
148 * @{
149 */
150 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
151 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
152
153 /**
154 * @}
155 */
156 #endif /* VREFBUF */
157
158 /** @defgroup SYSCFG_flags_definition Flags
159 * @{
160 */
161
162 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */
163 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */
164
165 /**
166 * @}
167 */
168
169 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
170 * @{
171 */
172
173 /** @brief Fast-mode Plus driving capability on a specific GPIO
174 */
175 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
176 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
177 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
178 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
179 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
180 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
181 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
182 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
183
184 /**
185 * @}
186 */
187
188 /**
189 * @}
190 */
191
192 /* Exported macros -----------------------------------------------------------*/
193
194 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
195 * @{
196 */
197
198 /** @brief Freeze/Unfreeze Peripherals in Debug mode
199 */
200 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
201 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
202 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
203 #endif
204
205 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
206 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
207 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
208 #endif
209
210 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
211 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
212 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
213 #endif
214
215 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
216 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
217 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
218 #endif
219
220 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
221 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
222 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
223 #endif
224
225 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
226 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
227 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
228 #endif
229
230 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
231 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
232 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
233 #endif
234
235 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
236 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
237 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
238 #endif
239
240 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
241 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
242 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
243 #endif
244
245 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
246 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
247 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
248 #endif
249
250 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
251 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
252 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
253 #endif
254
255 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
256 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
257 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
258 #endif
259
260 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
261 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
262 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
263 #endif
264
265 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
266 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
267 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
268 #endif
269
270 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
271 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
272 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
273 #endif
274
275 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
276 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
277 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
278 #endif
279
280 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
281 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
282 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
283 #endif
284
285 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
286 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
287 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
288 #endif
289
290 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
291 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
292 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
293 #endif
294
295 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
296 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
297 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
298 #endif
299
300 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
301 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
302 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
303 #endif
304
305 /**
306 * @}
307 */
308
309 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
310 * @{
311 */
312
313 /** @brief Main Flash memory mapped at 0x00000000.
314 */
315 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
316
317 /** @brief System Flash memory mapped at 0x00000000.
318 */
319 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
320
321 /** @brief Embedded SRAM mapped at 0x00000000.
322 */
323 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
324
325 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
326
327 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
328 */
329 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
330
331 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
332
333 /** @brief QUADSPI mapped at 0x00000000.
334 */
335 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
336
337 /**
338 * @brief Return the boot mode as configured by user.
339 * @retval The boot mode as configured by user. The returned value can be one
340 * of the following values:
341 * @arg @ref SYSCFG_BOOT_MAINFLASH
342 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH
343 @if STM32L486xx
344 * @arg @ref SYSCFG_BOOT_FMC
345 @endif
346 * @arg @ref SYSCFG_BOOT_SRAM
347 * @arg @ref SYSCFG_BOOT_QUADSPI
348 */
349 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
350
351 /** @brief SRAM2 page write protection enable macro
352 * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP
353 * @note write protection can only be disabled by a system reset
354 */
355 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
356 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
357 }while(0)
358
359 /** @brief SRAM2 page write protection unlock prior to erase
360 * @note Writing a wrong key reactivates the write protection
361 */
362 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\
363 SYSCFG->SKR = 0x53;\
364 }while(0)
365
366 /** @brief SRAM2 erase
367 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
368 */
369 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
370
371 /** @brief Floating Point Unit interrupt enable/disable macros
372 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
373 */
374 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
375 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
376 }while(0)
377
378 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
379 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
380 }while(0)
381
382 /** @brief SYSCFG Break ECC lock.
383 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
384 * @note The selected configuration is locked and can be unlocked only by system reset.
385 */
386 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
387
388 /** @brief SYSCFG Break Cortex-M4 Lockup lock.
389 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
390 * @note The selected configuration is locked and can be unlocked only by system reset.
391 */
392 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
393
394 /** @brief SYSCFG Break PVD lock.
395 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
396 * @note The selected configuration is locked and can be unlocked only by system reset.
397 */
398 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
399
400 /** @brief SYSCFG Break SRAM2 parity lock.
401 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
402 * @note The selected configuration is locked and can be unlocked by system reset.
403 */
404 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
405
406 /** @brief Check SYSCFG flag is set or not.
407 * @param __FLAG__: specifies the flag to check.
408 * This parameter can be one of the following values:
409 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
410 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
411 * @retval The new state of __FLAG__ (TRUE or FALSE).
412 */
413 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
414
415 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
416 */
417 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
418
419 /** @brief Fast-mode Plus driving capability enable/disable macros
420 * @param __FASTMODEPLUS__: This parameter can be a value of :
421 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
422 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
423 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
424 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
425 */
426 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
427 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
428 }while(0)
429
430 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
431 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
432 }while(0)
433
434 /**
435 * @}
436 */
437
438 /* Private macros ------------------------------------------------------------*/
439 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
440 * @{
441 */
442
443 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
444 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
445 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
446 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
447 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
448 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
449
450 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
451 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \
452 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
453 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
454
455 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
456
457 #if defined(VREFBUF)
458 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
459 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
460
461 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
462 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
463
464 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
465 #endif /* VREFBUF */
466
467 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
468 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
469 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
470 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
471 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
472 #elif defined(SYSCFG_FASTMODEPLUS_PB8)
473 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
474 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
475 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
476 #elif defined(SYSCFG_FASTMODEPLUS_PB9)
477 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
478 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
479 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
480 #else
481 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
482 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
483 #endif
484 /**
485 * @}
486 */
487
488 /* Exported functions --------------------------------------------------------*/
489
490 /** @addtogroup HAL_Exported_Functions
491 * @{
492 */
493
494 /** @addtogroup HAL_Exported_Functions_Group1
495 * @{
496 */
497
498 /* Initialization and de-initialization functions ******************************/
499 HAL_StatusTypeDef HAL_Init(void);
500 HAL_StatusTypeDef HAL_DeInit(void);
501 void HAL_MspInit(void);
502 void HAL_MspDeInit(void);
503 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
504
505 /**
506 * @}
507 */
508
509 /** @addtogroup HAL_Exported_Functions_Group2
510 * @{
511 */
512
513 /* Peripheral Control functions ************************************************/
514 void HAL_IncTick(void);
515 void HAL_Delay(uint32_t Delay);
516 uint32_t HAL_GetTick(void);
517 void HAL_SuspendTick(void);
518 void HAL_ResumeTick(void);
519 uint32_t HAL_GetHalVersion(void);
520 uint32_t HAL_GetREVID(void);
521 uint32_t HAL_GetDEVID(void);
522
523 /**
524 * @}
525 */
526
527 /** @addtogroup HAL_Exported_Functions_Group3
528 * @{
529 */
530
531 /* DBGMCU Peripheral Control functions *****************************************/
532 void HAL_DBGMCU_EnableDBGSleepMode(void);
533 void HAL_DBGMCU_DisableDBGSleepMode(void);
534 void HAL_DBGMCU_EnableDBGStopMode(void);
535 void HAL_DBGMCU_DisableDBGStopMode(void);
536 void HAL_DBGMCU_EnableDBGStandbyMode(void);
537 void HAL_DBGMCU_DisableDBGStandbyMode(void);
538
539 /**
540 * @}
541 */
542
543 /** @addtogroup HAL_Exported_Functions_Group4
544 * @{
545 */
546
547 /* SYSCFG Control functions ****************************************************/
548 void HAL_SYSCFG_SRAM2Erase(void);
549 void HAL_SYSCFG_EnableMemorySwappingBank(void);
550 void HAL_SYSCFG_DisableMemorySwappingBank(void);
551
552 #if defined(VREFBUF)
553 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
554 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
555 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
556 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
557 void HAL_SYSCFG_DisableVREFBUF(void);
558 #endif /* VREFBUF */
559
560 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
561 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
562
563 /**
564 * @}
565 */
566
567 /**
568 * @}
569 */
570
571 /**
572 * @}
573 */
574
575 /**
576 * @}
577 */
578
579 #ifdef __cplusplus
580 }
581 #endif
582
583 #endif /* __STM32L4xx_HAL_H */
584
585 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/