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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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-1:000000000000 0:32a3b1785697
1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_pwr_ex.h
4 * @author MCD Application Team
5 * @version V1.6.0
6 * @date 28-October-2016
7 * @brief Header file of PWR HAL Extended module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L4xx_HAL_PWR_EX_H
40 #define __STM32L4xx_HAL_PWR_EX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l4xx_hal_def.h"
48
49 /** @addtogroup STM32L4xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup PWREx
54 * @{
55 */
56
57
58 /* Exported types ------------------------------------------------------------*/
59
60 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
61 * @{
62 */
63
64
65 /**
66 * @brief PWR PVM configuration structure definition
67 */
68 typedef struct
69 {
70 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
71 This parameter can be a value of @ref PWREx_PVM_Type.
72 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
73 @if STM32L486xx
74 @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
75 @endif
76 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
77 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
78
79 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
80 This parameter can be a value of @ref PWREx_PVM_Mode. */
81 }PWR_PVMTypeDef;
82
83 /**
84 * @}
85 */
86
87 /* Exported constants --------------------------------------------------------*/
88
89 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
90 * @{
91 */
92
93 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
94 * @{
95 */
96 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */
97 /**
98 * @}
99 */
100
101
102 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
103 * @{
104 */
105 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
106 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
107 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
108 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
109 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
110 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
111 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
112 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
113 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
114 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
115 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
116 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
117 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
118 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
119 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
120 /**
121 * @}
122 */
123
124 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
125 * @{
126 */
127 #if defined(PWR_CR2_PVME1)
128 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
129 #endif /* PWR_CR2_PVME1 */
130 #if defined(PWR_CR2_PVME2)
131 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
132 #endif /* PWR_CR2_PVME2 */
133 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
134 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */
135 /**
136 * @}
137 */
138
139 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
140 * @{
141 */
142 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
143 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
144 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
145 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
146 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
147 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
148 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
149 /**
150 * @}
151 */
152
153
154
155 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
156 * @{
157 */
158 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */
159 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
160 /**
161 * @}
162 */
163
164
165 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
166 * @{
167 */
168 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */
169 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
170 /**
171 * @}
172 */
173
174 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
175 * @{
176 */
177 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)
178 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
179 /**
180 * @}
181 */
182
183 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
184 * @{
185 */
186 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
187 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
188 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
189 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
190 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
191 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
192 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
193 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
194 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
195 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
196 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
197 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
198 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
199 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
200 #define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
201 #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
202 /**
203 * @}
204 */
205
206 /** @defgroup PWREx_GPIO GPIO port
207 * @{
208 */
209 #define PWR_GPIO_A 0x00000000 /*!< GPIO port A */
210 #define PWR_GPIO_B 0x00000001 /*!< GPIO port B */
211 #define PWR_GPIO_C 0x00000002 /*!< GPIO port C */
212 #if defined(GPIOD_BASE)
213 #define PWR_GPIO_D 0x00000003 /*!< GPIO port D */
214 #endif
215 #if defined(GPIOE_BASE)
216 #define PWR_GPIO_E 0x00000004 /*!< GPIO port E */
217 #endif
218 #if defined(GPIOF_BASE)
219 #define PWR_GPIO_F 0x00000005 /*!< GPIO port F */
220 #endif
221 #if defined(GPIOG_BASE)
222 #define PWR_GPIO_G 0x00000006 /*!< GPIO port G */
223 #endif
224 #define PWR_GPIO_H 0x00000007 /*!< GPIO port H */
225 /**
226 * @}
227 */
228
229 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
230 * @{
231 */
232 #if defined(PWR_CR2_PVME1)
233 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */
234 #endif /* PWR_CR2_PVME1 */
235 #if defined(PWR_CR2_PVME2)
236 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */
237 #endif /* PWR_CR2_PVME2 */
238 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */
239 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */
240 /**
241 * @}
242 */
243
244 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
245 * @{
246 */
247 #if defined(PWR_CR2_PVME1)
248 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */
249 #endif /* PWR_CR2_PVME1 */
250 #if defined(PWR_CR2_PVME2)
251 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */
252 #endif /* PWR_CR2_PVME2 */
253 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */
254 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */
255 /**
256 * @}
257 */
258
259 /** @defgroup PWREx_Flag PWR Status Flags
260 * Elements values convention: 0000 0000 0XXY YYYYb
261 * - Y YYYY : Flag position in the XX register (5 bits)
262 * - XX : Status register (2 bits)
263 * - 01: SR1 register
264 * - 10: SR2 register
265 * The only exception is PWR_FLAG_WU, encompassing all
266 * wake-up flags and set to PWR_SR1_WUF.
267 * @{
268 */
269 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */
270 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */
271 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */
272 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */
273 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */
274 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
275 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */
276 #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */
277
278 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */
279 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */
280 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */
281 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */
282 #if defined(PWR_CR2_PVME1)
283 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */
284 #endif /* PWR_CR2_PVME1 */
285 #if defined(PWR_CR2_PVME2)
286 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */
287 #endif /* PWR_CR2_PVME2 */
288 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */
289 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */
290 /**
291 * @}
292 */
293
294 /**
295 * @}
296 */
297
298 /* Exported macros -----------------------------------------------------------*/
299 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
300 * @{
301 */
302
303 #if defined(PWR_CR2_PVME1)
304 /**
305 * @brief Enable the PVM1 Extended Interrupt Line.
306 * @retval None
307 */
308 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
309
310 /**
311 * @brief Disable the PVM1 Extended Interrupt Line.
312 * @retval None
313 */
314 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
315
316 /**
317 * @brief Enable the PVM1 Event Line.
318 * @retval None
319 */
320 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
321
322 /**
323 * @brief Disable the PVM1 Event Line.
324 * @retval None
325 */
326 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
327
328 /**
329 * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
330 * @retval None
331 */
332 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
333
334 /**
335 * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
336 * @retval None
337 */
338 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
339
340 /**
341 * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
342 * @retval None
343 */
344 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
345
346
347 /**
348 * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
349 * @retval None
350 */
351 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
352
353
354 /**
355 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
356 * @retval None
357 */
358 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
359 do { \
360 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
361 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
362 } while(0)
363
364 /**
365 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
366 * @retval None
367 */
368 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
369 do { \
370 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
371 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
372 } while(0)
373
374 /**
375 * @brief Generate a Software interrupt on selected EXTI line.
376 * @retval None
377 */
378 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
379
380 /**
381 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
382 * @retval EXTI PVM1 Line Status.
383 */
384 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
385
386 /**
387 * @brief Clear the PVM1 EXTI flag.
388 * @retval None
389 */
390 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
391
392 #endif /* PWR_CR2_PVME1 */
393
394
395 #if defined(PWR_CR2_PVME2)
396 /**
397 * @brief Enable the PVM2 Extended Interrupt Line.
398 * @retval None
399 */
400 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
401
402 /**
403 * @brief Disable the PVM2 Extended Interrupt Line.
404 * @retval None
405 */
406 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
407
408 /**
409 * @brief Enable the PVM2 Event Line.
410 * @retval None
411 */
412 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
413
414 /**
415 * @brief Disable the PVM2 Event Line.
416 * @retval None
417 */
418 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
419
420 /**
421 * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
422 * @retval None
423 */
424 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
425
426 /**
427 * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
428 * @retval None
429 */
430 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
431
432 /**
433 * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
434 * @retval None
435 */
436 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
437
438
439 /**
440 * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
441 * @retval None
442 */
443 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
444
445
446 /**
447 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
448 * @retval None
449 */
450 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
451 do { \
452 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
453 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
454 } while(0)
455
456 /**
457 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
458 * @retval None
459 */
460 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
461 do { \
462 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
463 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
464 } while(0)
465
466 /**
467 * @brief Generate a Software interrupt on selected EXTI line.
468 * @retval None
469 */
470 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
471
472 /**
473 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
474 * @retval EXTI PVM2 Line Status.
475 */
476 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
477
478 /**
479 * @brief Clear the PVM2 EXTI flag.
480 * @retval None
481 */
482 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
483
484 #endif /* PWR_CR2_PVME2 */
485
486
487 /**
488 * @brief Enable the PVM3 Extended Interrupt Line.
489 * @retval None
490 */
491 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
492
493 /**
494 * @brief Disable the PVM3 Extended Interrupt Line.
495 * @retval None
496 */
497 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
498
499 /**
500 * @brief Enable the PVM3 Event Line.
501 * @retval None
502 */
503 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
504
505 /**
506 * @brief Disable the PVM3 Event Line.
507 * @retval None
508 */
509 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
510
511 /**
512 * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
513 * @retval None
514 */
515 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
516
517 /**
518 * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
519 * @retval None
520 */
521 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
522
523 /**
524 * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
525 * @retval None
526 */
527 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
528
529
530 /**
531 * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
532 * @retval None
533 */
534 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
535
536
537 /**
538 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
539 * @retval None
540 */
541 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
542 do { \
543 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
544 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
545 } while(0)
546
547 /**
548 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
549 * @retval None
550 */
551 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
552 do { \
553 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
554 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
555 } while(0)
556
557 /**
558 * @brief Generate a Software interrupt on selected EXTI line.
559 * @retval None
560 */
561 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
562
563 /**
564 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
565 * @retval EXTI PVM3 Line Status.
566 */
567 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
568
569 /**
570 * @brief Clear the PVM3 EXTI flag.
571 * @retval None
572 */
573 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
574
575
576
577
578 /**
579 * @brief Enable the PVM4 Extended Interrupt Line.
580 * @retval None
581 */
582 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
583
584 /**
585 * @brief Disable the PVM4 Extended Interrupt Line.
586 * @retval None
587 */
588 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
589
590 /**
591 * @brief Enable the PVM4 Event Line.
592 * @retval None
593 */
594 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
595
596 /**
597 * @brief Disable the PVM4 Event Line.
598 * @retval None
599 */
600 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
601
602 /**
603 * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
604 * @retval None
605 */
606 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
607
608 /**
609 * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
610 * @retval None
611 */
612 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
613
614 /**
615 * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
616 * @retval None
617 */
618 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
619
620
621 /**
622 * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
623 * @retval None
624 */
625 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
626
627
628 /**
629 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
630 * @retval None
631 */
632 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
633 do { \
634 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
635 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
636 } while(0)
637
638 /**
639 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
640 * @retval None
641 */
642 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
643 do { \
644 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
645 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
646 } while(0)
647
648 /**
649 * @brief Generate a Software interrupt on selected EXTI line.
650 * @retval None
651 */
652 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
653
654 /**
655 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
656 * @retval EXTI PVM4 Line Status.
657 */
658 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
659
660 /**
661 * @brief Clear the PVM4 EXTI flag.
662 * @retval None
663 */
664 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
665
666
667 /**
668 * @brief Configure the main internal regulator output voltage.
669 * @param __REGULATOR__: specifies the regulator output voltage to achieve
670 * a tradeoff between performance and power consumption.
671 * This parameter can be one of the following values:
672 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
673 * typical output voltage at 1.2 V,
674 * system frequency up to 80 MHz.
675 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
676 * typical output voltage at 1.0 V,
677 * system frequency up to 26 MHz.
678 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
679 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User
680 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
681 * @retval None
682 */
683 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
684 __IO uint32_t tmpreg; \
685 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
686 /* Delay after an RCC peripheral clock enabling */ \
687 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
688 UNUSED(tmpreg); \
689 } while(0)
690
691 /**
692 * @}
693 */
694
695 /* Private macros --------------------------------------------------------*/
696 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
697 * @{
698 */
699
700 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
701 ((PIN) == PWR_WAKEUP_PIN2) || \
702 ((PIN) == PWR_WAKEUP_PIN3) || \
703 ((PIN) == PWR_WAKEUP_PIN4) || \
704 ((PIN) == PWR_WAKEUP_PIN5) || \
705 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
706 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
707 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
708 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
709 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
710 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
711 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
712 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
713 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
714 ((PIN) == PWR_WAKEUP_PIN5_LOW))
715
716 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
717 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
718 ((TYPE) == PWR_PVM_2) ||\
719 ((TYPE) == PWR_PVM_3) ||\
720 ((TYPE) == PWR_PVM_4))
721 #elif defined (STM32L471xx)
722 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
723 ((TYPE) == PWR_PVM_3) ||\
724 ((TYPE) == PWR_PVM_4))
725 #endif
726
727 #if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)
728 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
729 ((TYPE) == PWR_PVM_3) ||\
730 ((TYPE) == PWR_PVM_4))
731 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)
732 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
733 ((TYPE) == PWR_PVM_4))
734 #endif
735
736 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
737 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\
738 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
739 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
740 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
741 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
742 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
743
744 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
745 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
746
747 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
748 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
749
750 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
751 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
752
753 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
754
755
756 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
757 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
758 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
759 ((GPIO) == PWR_GPIO_B) ||\
760 ((GPIO) == PWR_GPIO_C) ||\
761 ((GPIO) == PWR_GPIO_D) ||\
762 ((GPIO) == PWR_GPIO_E) ||\
763 ((GPIO) == PWR_GPIO_H))
764 #elif defined (STM32L432xx) || defined (STM32L442xx)
765 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
766 ((GPIO) == PWR_GPIO_B) ||\
767 ((GPIO) == PWR_GPIO_C) ||\
768 ((GPIO) == PWR_GPIO_H))
769 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
770 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
771 ((GPIO) == PWR_GPIO_B) ||\
772 ((GPIO) == PWR_GPIO_C) ||\
773 ((GPIO) == PWR_GPIO_D) ||\
774 ((GPIO) == PWR_GPIO_E) ||\
775 ((GPIO) == PWR_GPIO_F) ||\
776 ((GPIO) == PWR_GPIO_G) ||\
777 ((GPIO) == PWR_GPIO_H))
778 #endif
779
780
781 /**
782 * @}
783 */
784
785
786 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
787 * @{
788 */
789
790 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
791 * @{
792 */
793
794
795 /* Peripheral Control functions **********************************************/
796 uint32_t HAL_PWREx_GetVoltageRange(void);
797 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
798 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
799 void HAL_PWREx_DisableBatteryCharging(void);
800 #if defined(PWR_CR2_USV)
801 void HAL_PWREx_EnableVddUSB(void);
802 void HAL_PWREx_DisableVddUSB(void);
803 #endif /* PWR_CR2_USV */
804 #if defined(PWR_CR2_IOSV)
805 void HAL_PWREx_EnableVddIO2(void);
806 void HAL_PWREx_DisableVddIO2(void);
807 #endif /* PWR_CR2_IOSV */
808 void HAL_PWREx_EnableInternalWakeUpLine(void);
809 void HAL_PWREx_DisableInternalWakeUpLine(void);
810 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
811 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
812 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
813 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
814 void HAL_PWREx_EnablePullUpPullDownConfig(void);
815 void HAL_PWREx_DisablePullUpPullDownConfig(void);
816 void HAL_PWREx_EnableSRAM2ContentRetention(void);
817 void HAL_PWREx_DisableSRAM2ContentRetention(void);
818 #if defined(PWR_CR2_PVME1)
819 void HAL_PWREx_EnablePVM1(void);
820 void HAL_PWREx_DisablePVM1(void);
821 #endif /* PWR_CR2_PVME1 */
822 #if defined(PWR_CR2_PVME2)
823 void HAL_PWREx_EnablePVM2(void);
824 void HAL_PWREx_DisablePVM2(void);
825 #endif /* PWR_CR2_PVME2 */
826 void HAL_PWREx_EnablePVM3(void);
827 void HAL_PWREx_DisablePVM3(void);
828 void HAL_PWREx_EnablePVM4(void);
829 void HAL_PWREx_DisablePVM4(void);
830 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
831
832
833 /* Low Power modes configuration functions ************************************/
834 void HAL_PWREx_EnableLowPowerRunMode(void);
835 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
836 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
837 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
838 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
839 void HAL_PWREx_EnterSHUTDOWNMode(void);
840
841 void HAL_PWREx_PVD_PVM_IRQHandler(void);
842 #if defined(PWR_CR2_PVME1)
843 void HAL_PWREx_PVM1Callback(void);
844 #endif /* PWR_CR2_PVME1 */
845 #if defined(PWR_CR2_PVME2)
846 void HAL_PWREx_PVM2Callback(void);
847 #endif /* PWR_CR2_PVME2 */
848 void HAL_PWREx_PVM3Callback(void);
849 void HAL_PWREx_PVM4Callback(void);
850
851 /**
852 * @}
853 */
854
855 /**
856 * @}
857 */
858
859 /**
860 * @}
861 */
862
863 /**
864 * @}
865 */
866
867 #ifdef __cplusplus
868 }
869 #endif
870
871
872 #endif /* __STM32L4xx_HAL_PWR_EX_H */
873
874 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/