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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_tim.h
4 * @author MCD Application Team
5 * @version V1.6.0
6 * @date 28-October-2016
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L4xx_HAL_TIM_H
40 #define __STM32L4xx_HAL_TIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l4xx_hal_def.h"
48
49 /** @addtogroup STM32L4xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup TIM
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup TIM_Exported_Types TIM Exported Types
59 * @{
60 */
61
62 /**
63 * @brief TIM Time base Configuration Structure definition
64 */
65 typedef struct
66 {
67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
69
70 uint32_t CounterMode; /*!< Specifies the counter mode.
71 This parameter can be a value of @ref TIM_Counter_Mode */
72
73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
74 Auto-Reload Register at the next update event.
75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
76
77 uint32_t ClockDivision; /*!< Specifies the clock division.
78 This parameter can be a value of @ref TIM_ClockDivision */
79
80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
81 reaches zero, an update event is generated and counting restarts
82 from the RCR value (N).
83 This means in PWM mode that (N+1) corresponds to:
84 - the number of PWM periods in edge-aligned mode
85 - the number of half PWM period in center-aligned mode
86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
87 @note This parameter is valid only for TIM1 and TIM8. */
88 } TIM_Base_InitTypeDef;
89
90 /**
91 * @brief TIM Output Compare Configuration Structure definition
92 */
93 typedef struct
94 {
95 uint32_t OCMode; /*!< Specifies the TIM mode.
96 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
97
98 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
99 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
100
101 uint32_t OCPolarity; /*!< Specifies the output polarity.
102 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
103
104 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
105 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
106 @note This parameter is valid only for TIM1 and TIM8. */
107
108 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
109 This parameter can be a value of @ref TIM_Output_Fast_State
110 @note This parameter is valid only in PWM1 and PWM2 mode. */
111
112
113 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
114 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
115 @note This parameter is valid only for TIM1 and TIM8. */
116
117 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
118 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
119 @note This parameter is valid only for TIM1 and TIM8. */
120 } TIM_OC_InitTypeDef;
121
122 /**
123 * @brief TIM One Pulse Mode Configuration Structure definition
124 */
125 typedef struct
126 {
127 uint32_t OCMode; /*!< Specifies the TIM mode.
128 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
129
130 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
131 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
132
133 uint32_t OCPolarity; /*!< Specifies the output polarity.
134 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
135
136 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
137 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
138 @note This parameter is valid only for TIM1 and TIM8. */
139
140 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
141 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
142 @note This parameter is valid only for TIM1 and TIM8. */
143
144 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
145 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
146 @note This parameter is valid only for TIM1 and TIM8. */
147
148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
150
151 uint32_t ICSelection; /*!< Specifies the input.
152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
153
154 uint32_t ICFilter; /*!< Specifies the input capture filter.
155 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
156 } TIM_OnePulse_InitTypeDef;
157
158
159 /**
160 * @brief TIM Input Capture Configuration Structure definition
161 */
162 typedef struct
163 {
164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
166
167 uint32_t ICSelection; /*!< Specifies the input.
168 This parameter can be a value of @ref TIM_Input_Capture_Selection */
169
170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
172
173 uint32_t ICFilter; /*!< Specifies the input capture filter.
174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
175 } TIM_IC_InitTypeDef;
176
177 /**
178 * @brief TIM Encoder Configuration Structure definition
179 */
180 typedef struct
181 {
182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
183 This parameter can be a value of @ref TIM_Encoder_Mode */
184
185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
187
188 uint32_t IC1Selection; /*!< Specifies the input.
189 This parameter can be a value of @ref TIM_Input_Capture_Selection */
190
191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
193
194 uint32_t IC1Filter; /*!< Specifies the input capture filter.
195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
196
197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
199
200 uint32_t IC2Selection; /*!< Specifies the input.
201 This parameter can be a value of @ref TIM_Input_Capture_Selection */
202
203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
205
206 uint32_t IC2Filter; /*!< Specifies the input capture filter.
207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
208 } TIM_Encoder_InitTypeDef;
209
210
211 /**
212 * @brief Clock Configuration Handle Structure definition
213 */
214 typedef struct
215 {
216 uint32_t ClockSource; /*!< TIM clock sources
217 This parameter can be a value of @ref TIM_Clock_Source */
218 uint32_t ClockPolarity; /*!< TIM clock polarity
219 This parameter can be a value of @ref TIM_Clock_Polarity */
220 uint32_t ClockPrescaler; /*!< TIM clock prescaler
221 This parameter can be a value of @ref TIM_Clock_Prescaler */
222 uint32_t ClockFilter; /*!< TIM clock filter
223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
224 }TIM_ClockConfigTypeDef;
225
226 /**
227 * @brief Clear Input Configuration Handle Structure definition
228 */
229 typedef struct
230 {
231 uint32_t ClearInputState; /*!< TIM clear Input state
232 This parameter can be ENABLE or DISABLE */
233 uint32_t ClearInputSource; /*!< TIM clear Input sources
234 This parameter can be a value of @ref TIM_ClearInput_Source */
235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
236 This parameter can be a value of @ref TIM_ClearInput_Polarity */
237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
240 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
241 }TIM_ClearInputConfigTypeDef;
242
243 /**
244 * @brief TIM Master configuration Structure definition
245 * @note Advanced timers provide TRGO2 internal line which is redirected
246 * to the ADC
247 */
248 typedef struct {
249 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
250 This parameter can be a value of @ref TIM_Master_Mode_Selection */
251 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
252 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
253 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
254 This parameter can be a value of @ref TIM_Master_Slave_Mode */
255 }TIM_MasterConfigTypeDef;
256
257 /**
258 * @brief TIM Slave configuration Structure definition
259 */
260 typedef struct {
261 uint32_t SlaveMode; /*!< Slave mode selection
262 This parameter can be a value of @ref TIM_Slave_Mode */
263 uint32_t InputTrigger; /*!< Input Trigger source
264 This parameter can be a value of @ref TIM_Trigger_Selection */
265 uint32_t TriggerPolarity; /*!< Input Trigger polarity
266 This parameter can be a value of @ref TIM_Trigger_Polarity */
267 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
268 This parameter can be a value of @ref TIM_Trigger_Prescaler */
269 uint32_t TriggerFilter; /*!< Input trigger filter
270 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
271
272 }TIM_SlaveConfigTypeDef;
273
274 /**
275 * @brief TIM Break input(s) and Dead time configuration Structure definition
276 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
277 * filter and polarity.
278 */
279 typedef struct
280 {
281 uint32_t OffStateRunMode; /*!< TIM off state in run mode
282 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
283 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
284 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
285 uint32_t LockLevel; /*!< TIM Lock level
286 This parameter can be a value of @ref TIM_Lock_level */
287 uint32_t DeadTime; /*!< TIM dead Time
288 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
289 uint32_t BreakState; /*!< TIM Break State
290 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
291 uint32_t BreakPolarity; /*!< TIM Break input polarity
292 This parameter can be a value of @ref TIM_Break_Polarity */
293 uint32_t BreakFilter; /*!< Specifies the break input filter.
294 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
295 uint32_t Break2State; /*!< TIM Break2 State
296 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
297 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
298 This parameter can be a value of @ref TIM_Break2_Polarity */
299 uint32_t Break2Filter; /*!< TIM break2 input filter.
300 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
301 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
302 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
303 } TIM_BreakDeadTimeConfigTypeDef;
304
305 /**
306 * @brief HAL State structures definition
307 */
308 typedef enum
309 {
310 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
311 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
312 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
313 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
314 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
315 }HAL_TIM_StateTypeDef;
316
317 /**
318 * @brief HAL Active channel structures definition
319 */
320 typedef enum
321 {
322 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
323 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
324 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
325 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
326 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, /*!< The active channel is 5 */
327 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, /*!< The active channel is 6 */
328 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
329 }HAL_TIM_ActiveChannel;
330
331 /**
332 * @brief TIM Time Base Handle Structure definition
333 */
334 typedef struct
335 {
336 TIM_TypeDef *Instance; /*!< Register base address */
337 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
338 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
339 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
340 This array is accessed by a @ref DMA_Handle_index */
341 HAL_LockTypeDef Lock; /*!< Locking object */
342 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
343 }TIM_HandleTypeDef;
344
345 /**
346 * @}
347 */
348 /* End of exported types -----------------------------------------------------*/
349
350 /* Exported constants --------------------------------------------------------*/
351 /** @defgroup TIM_Exported_Constants TIM Exported Constants
352 * @{
353 */
354
355 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
356 * @{
357 */
358 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
359 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
360 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
361 /**
362 * @}
363 */
364
365 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
366 * @{
367 */
368 #define TIM_DMABASE_CR1 (0x00000000)
369 #define TIM_DMABASE_CR2 (0x00000001)
370 #define TIM_DMABASE_SMCR (0x00000002)
371 #define TIM_DMABASE_DIER (0x00000003)
372 #define TIM_DMABASE_SR (0x00000004)
373 #define TIM_DMABASE_EGR (0x00000005)
374 #define TIM_DMABASE_CCMR1 (0x00000006)
375 #define TIM_DMABASE_CCMR2 (0x00000007)
376 #define TIM_DMABASE_CCER (0x00000008)
377 #define TIM_DMABASE_CNT (0x00000009)
378 #define TIM_DMABASE_PSC (0x0000000A)
379 #define TIM_DMABASE_ARR (0x0000000B)
380 #define TIM_DMABASE_RCR (0x0000000C)
381 #define TIM_DMABASE_CCR1 (0x0000000D)
382 #define TIM_DMABASE_CCR2 (0x0000000E)
383 #define TIM_DMABASE_CCR3 (0x0000000F)
384 #define TIM_DMABASE_CCR4 (0x00000010)
385 #define TIM_DMABASE_BDTR (0x00000011)
386 #define TIM_DMABASE_DCR (0x00000012)
387 #define TIM_DMABASE_DMAR (0x00000013)
388 #define TIM_DMABASE_OR1 (0x00000014)
389 #define TIM_DMABASE_CCMR3 (0x00000015)
390 #define TIM_DMABASE_CCR5 (0x00000016)
391 #define TIM_DMABASE_CCR6 (0x00000017)
392 #define TIM_DMABASE_OR2 (0x00000018)
393 #define TIM_DMABASE_OR3 (0x00000019)
394 /**
395 * @}
396 */
397
398 /** @defgroup TIM_Event_Source TIM Extended Event Source
399 * @{
400 */
401 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
402 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
403 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
404 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
405 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
406 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
407 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
408 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
409 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
410 /**
411 * @}
412 */
413
414 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
415 * @{
416 */
417 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
418 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
419 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
420 /**
421 * @}
422 */
423
424 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
425 * @{
426 */
427 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
428 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
429 /**
430 * @}
431 */
432
433 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
434 * @{
435 */
436 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
437 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
438 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
439 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
440 /**
441 * @}
442 */
443
444 /** @defgroup TIM_Counter_Mode TIM Counter Mode
445 * @{
446 */
447 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
448 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
449 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
450 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
451 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
452 /**
453 * @}
454 */
455
456 /** @defgroup TIM_ClockDivision TIM Clock Division
457 * @{
458 */
459 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
460 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
461 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
462 /**
463 * @}
464 */
465
466 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
467 * @{
468 */
469 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
470 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
471 /**
472 * @}
473 */
474
475 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
476 * @{
477 */
478 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
479 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
480 /**
481 * @}
482 */
483
484 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
485 * @{
486 */
487 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
488 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
489 /**
490 * @}
491 */
492
493 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
494 * @{
495 */
496 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
497 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
498 /**
499 * @}
500 */
501
502 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
503 * @{
504 */
505 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
506 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
507 /**
508 * @}
509 */
510
511 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
512 * @{
513 */
514 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
515 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
516 /**
517 * @}
518 */
519
520 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
521 * @{
522 */
523 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
524 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
525 /**
526 * @}
527 */
528
529 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
530 * @{
531 */
532 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
533 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
534 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
535 /**
536 * @}
537 */
538
539 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
540 * @{
541 */
542 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
543 connected to IC1, IC2, IC3 or IC4, respectively */
544 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
545 connected to IC2, IC1, IC4 or IC3, respectively */
546 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
547 /**
548 * @}
549 */
550
551 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
552 * @{
553 */
554 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
555 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
556 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
557 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
558 /**
559 * @}
560 */
561
562 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
563 * @{
564 */
565 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
566 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
567 /**
568 * @}
569 */
570
571 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
572 * @{
573 */
574 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
575 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
576 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
577 /**
578 * @}
579 */
580
581 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
582 * @{
583 */
584 #define TIM_IT_UPDATE (TIM_DIER_UIE)
585 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
586 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
587 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
588 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
589 #define TIM_IT_COM (TIM_DIER_COMIE)
590 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
591 #define TIM_IT_BREAK (TIM_DIER_BIE)
592 /**
593 * @}
594 */
595
596 /** @defgroup TIM_Commutation_Source TIM Commutation Source
597 * @{
598 */
599 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
600 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
601 /**
602 * @}
603 */
604
605 /** @defgroup TIM_DMA_sources TIM DMA Sources
606 * @{
607 */
608 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
609 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
610 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
611 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
612 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
613 #define TIM_DMA_COM (TIM_DIER_COMDE)
614 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
615 /**
616 * @}
617 */
618
619 /** @defgroup TIM_Flag_definition TIM Flag Definition
620 * @{
621 */
622 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
623 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
624 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
625 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
626 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
627 #define TIM_FLAG_CC5 (TIM_SR_CC5IF)
628 #define TIM_FLAG_CC6 (TIM_SR_CC6IF)
629 #define TIM_FLAG_COM (TIM_SR_COMIF)
630 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
631 #define TIM_FLAG_BREAK (TIM_SR_BIF)
632 #define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
633 #define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF)
634 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
635 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
636 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
637 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
638 /**
639 * @}
640 */
641
642 /** @defgroup TIM_Channel TIM Channel
643 * @{
644 */
645 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
646 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
647 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
648 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
649 #define TIM_CHANNEL_5 ((uint32_t)0x0010)
650 #define TIM_CHANNEL_6 ((uint32_t)0x0014)
651 #define TIM_CHANNEL_ALL ((uint32_t)0x003C)
652 /**
653 * @}
654 */
655
656 /** @defgroup TIM_Clock_Source TIM Clock Source
657 * @{
658 */
659 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
660 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
661 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
662 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
663 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
664 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
665 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
666 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
667 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
668 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
669 /**
670 * @}
671 */
672
673 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
674 * @{
675 */
676 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
677 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
678 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
679 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
680 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
681 /**
682 * @}
683 */
684
685 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
686 * @{
687 */
688 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
689 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
690 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
691 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
692 /**
693 * @}
694 */
695
696 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
697 * @{
698 */
699 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
700 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
701 /**
702 * @}
703 */
704
705 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
706 * @{
707 */
708 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
709 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
710 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
711 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
712 /**
713 * @}
714 */
715
716 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
717 * @{
718 */
719 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
720 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
721 /**
722 * @}
723 */
724
725 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
726 * @{
727 */
728 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
729 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
730 /**
731 * @}
732 */
733 /** @defgroup TIM_Lock_level TIM Lock level
734 * @{
735 */
736 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
737 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
738 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
739 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
740 /**
741 * @}
742 */
743
744 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
745 * @{
746 */
747 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
748 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
749 /**
750 * @}
751 */
752
753 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
754 * @{
755 */
756 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
757 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
758 /**
759 * @}
760 */
761
762 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
763 * @{
764 */
765 #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
766 #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
767 /**
768 * @}
769 */
770
771 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
772 * @{
773 */
774 #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
775 #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
776 /**
777 * @}
778 */
779
780 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
781 * @{
782 */
783 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
784 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
785 /**
786 * @}
787 */
788
789 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
790 * @{
791 */
792 #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
793 #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
794 #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
795 #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
801 * @{
802 */
803 #define TIM_TRGO_RESET ((uint32_t)0x0000)
804 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
805 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
806 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
807 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
808 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
809 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
810 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
811 /**
812 * @}
813 */
814
815 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
816 * @{
817 */
818 #define TIM_TRGO2_RESET ((uint32_t)0x00000000)
819 #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
820 #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
821 #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
822 #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
823 #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
824 #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
825 #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
826 #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
827 #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
828 #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
829 #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
830 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
831 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
832 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
833 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
834 /**
835 * @}
836 */
837
838 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
839 * @{
840 */
841 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
842 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
843 /**
844 * @}
845 */
846
847 /** @defgroup TIM_Slave_Mode TIM Slave mode
848 * @{
849 */
850 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
851 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
852 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
853 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
854 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
855 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
856 /**
857 * @}
858 */
859
860 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
861 * @{
862 */
863 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
864 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
865 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
866 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
867 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
868 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
869 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
870 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
871
872 #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
873 #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
874 #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
875 #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
876 #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
877 #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
878 /**
879 * @}
880 */
881
882 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
883 * @{
884 */
885 #define TIM_TS_ITR0 ((uint32_t)0x0000)
886 #define TIM_TS_ITR1 ((uint32_t)0x0010)
887 #define TIM_TS_ITR2 ((uint32_t)0x0020)
888 #define TIM_TS_ITR3 ((uint32_t)0x0030)
889 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
890 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
891 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
892 #define TIM_TS_ETRF ((uint32_t)0x0070)
893 #define TIM_TS_NONE ((uint32_t)0xFFFF)
894 /**
895 * @}
896 */
897
898 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
899 * @{
900 */
901 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
902 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
903 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
904 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
905 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
906 /**
907 * @}
908 */
909
910 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
911 * @{
912 */
913 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
914 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
915 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
916 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
917 /**
918 * @}
919 */
920
921 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
922 * @{
923 */
924 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
925 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
926 /**
927 * @}
928 */
929
930 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
931 * @{
932 */
933 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
934 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
935 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
936 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
937 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
938 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
939 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
940 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
941 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
942 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
943 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
944 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
945 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
946 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
947 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
948 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
949 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
950 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
951 /**
952 * @}
953 */
954
955 /** @defgroup DMA_Handle_index TIM DMA Handle Index
956 * @{
957 */
958 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
959 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
960 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
961 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
962 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
963 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
964 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
965 /**
966 * @}
967 */
968
969 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
970 * @{
971 */
972 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
973 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
974 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
975 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
976 /**
977 * @}
978 */
979
980 /** @defgroup TIM_Break_System TIM Break System
981 * @{
982 */
983 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
984 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
985 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */
986 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */
987 /**
988 * @}
989 */
990
991 /**
992 * @}
993 */
994 /* End of exported constants -------------------------------------------------*/
995
996 /* Exported macros -----------------------------------------------------------*/
997 /** @defgroup TIM_Exported_Macros TIM Exported Macros
998 * @{
999 */
1000
1001 /** @brief Reset TIM handle state.
1002 * @param __HANDLE__: TIM handle.
1003 * @retval None
1004 */
1005 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1006
1007 /**
1008 * @brief Enable the TIM peripheral.
1009 * @param __HANDLE__: TIM handle
1010 * @retval None
1011 */
1012 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1013
1014 /**
1015 * @brief Enable the TIM main Output.
1016 * @param __HANDLE__: TIM handle
1017 * @retval None
1018 */
1019 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1020
1021 /**
1022 * @brief Disable the TIM peripheral.
1023 * @param __HANDLE__: TIM handle
1024 * @retval None
1025 */
1026 #define __HAL_TIM_DISABLE(__HANDLE__) \
1027 do { \
1028 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
1029 { \
1030 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
1031 { \
1032 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1033 } \
1034 } \
1035 } while(0)
1036
1037 /**
1038 * @brief Disable the TIM main Output.
1039 * @param __HANDLE__: TIM handle
1040 * @retval None
1041 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
1042 */
1043 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1044 do { \
1045 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
1046 { \
1047 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
1048 { \
1049 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1050 } \
1051 } \
1052 } while(0)
1053
1054 /** @brief Enable the specified TIM interrupt.
1055 * @param __HANDLE__: specifies the TIM Handle.
1056 * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
1057 * This parameter can be one of the following values:
1058 * @arg TIM_IT_UPDATE: Update interrupt
1059 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1060 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1061 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1062 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1063 * @arg TIM_IT_COM: Commutation interrupt
1064 * @arg TIM_IT_TRIGGER: Trigger interrupt
1065 * @arg TIM_IT_BREAK: Break interrupt
1066 * @retval None
1067 */
1068 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1069
1070
1071 /** @brief Disable the specified TIM interrupt.
1072 * @param __HANDLE__: specifies the TIM Handle.
1073 * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
1074 * This parameter can be one of the following values:
1075 * @arg TIM_IT_UPDATE: Update interrupt
1076 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1077 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1078 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1079 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1080 * @arg TIM_IT_COM: Commutation interrupt
1081 * @arg TIM_IT_TRIGGER: Trigger interrupt
1082 * @arg TIM_IT_BREAK: Break interrupt
1083 * @retval None
1084 */
1085 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1086
1087 /** @brief Enable the specified DMA request.
1088 * @param __HANDLE__: specifies the TIM Handle.
1089 * @param __DMA__: specifies the TIM DMA request to enable.
1090 * This parameter can be one of the following values:
1091 * @arg TIM_DMA_UPDATE: Update DMA request
1092 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1093 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1094 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1095 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1096 * @arg TIM_DMA_COM: Commutation DMA request
1097 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1098 * @arg TIM_DMA_BREAK: Break DMA request
1099 * @retval None
1100 */
1101 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1102
1103 /** @brief Disable the specified DMA request.
1104 * @param __HANDLE__: specifies the TIM Handle.
1105 * @param __DMA__: specifies the TIM DMA request to disable.
1106 * This parameter can be one of the following values:
1107 * @arg TIM_DMA_UPDATE: Update DMA request
1108 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1109 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1110 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1111 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1112 * @arg TIM_DMA_COM: Commutation DMA request
1113 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1114 * @arg TIM_DMA_BREAK: Break DMA request
1115 * @retval None
1116 */
1117 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1118
1119 /** @brief Check whether the specified TIM interrupt flag is set or not.
1120 * @param __HANDLE__: specifies the TIM Handle.
1121 * @param __FLAG__: specifies the TIM interrupt flag to check.
1122 * This parameter can be one of the following values:
1123 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1124 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1125 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1126 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1127 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1128 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1129 * @arg TIM_FLAG_CC6: Compare 5 interrupt flag
1130 * @arg TIM_FLAG_COM: Commutation interrupt flag
1131 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1132 * @arg TIM_FLAG_BREAK: Break interrupt flag
1133 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1134 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1135 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1136 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1137 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1138 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1139 * @retval The new state of __FLAG__ (TRUE or FALSE).
1140 */
1141 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1142
1143 /** @brief Clear the specified TIM interrupt flag.
1144 * @param __HANDLE__: specifies the TIM Handle.
1145 * @param __FLAG__: specifies the TIM interrupt flag to clear.
1146 * This parameter can be one of the following values:
1147 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1148 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1149 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1150 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1151 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1152 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1153 * @arg TIM_FLAG_CC6: Compare 5 interrupt flag
1154 * @arg TIM_FLAG_COM: Commutation interrupt flag
1155 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1156 * @arg TIM_FLAG_BREAK: Break interrupt flag
1157 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1158 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1159 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1160 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1161 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1162 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1163 * @retval The new state of __FLAG__ (TRUE or FALSE).
1164 */
1165 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1166
1167 /**
1168 * @brief Check whether the specified TIM interrupt source is enabled or not.
1169 * @param __HANDLE__: TIM handle
1170 * @param __INTERRUPT__: specifies the TIM interrupt source to check.
1171 * This parameter can be one of the following values:
1172 * @arg TIM_IT_UPDATE: Update interrupt
1173 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1174 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1175 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1176 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1177 * @arg TIM_IT_COM: Commutation interrupt
1178 * @arg TIM_IT_TRIGGER: Trigger interrupt
1179 * @arg TIM_IT_BREAK: Break interrupt
1180 * @retval The state of TIM_IT (SET or RESET).
1181 */
1182 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1183
1184 /** @brief Clear the TIM interrupt pending bits.
1185 * @param __HANDLE__: TIM handle
1186 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
1187 * This parameter can be one of the following values:
1188 * @arg TIM_IT_UPDATE: Update interrupt
1189 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1190 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1191 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1192 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1193 * @arg TIM_IT_COM: Commutation interrupt
1194 * @arg TIM_IT_TRIGGER: Trigger interrupt
1195 * @arg TIM_IT_BREAK: Break interrupt
1196 * @retval None
1197 */
1198 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1199
1200 /**
1201 * @brief Indicates whether or not the TIM Counter is used as downcounter.
1202 * @param __HANDLE__: TIM handle.
1203 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1204 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
1205 mode.
1206 */
1207 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1208
1209
1210 /**
1211 * @brief Set the TIM Prescaler on runtime.
1212 * @param __HANDLE__: TIM handle.
1213 * @param __PRESC__: specifies the Prescaler new value.
1214 * @retval None
1215 */
1216 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1217
1218 /**
1219 * @brief Set the TIM Counter Register value on runtime.
1220 * @param __HANDLE__: TIM handle.
1221 * @param __COUNTER__: specifies the Counter register new value.
1222 * @retval None
1223 */
1224 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1225
1226 /**
1227 * @brief Get the TIM Counter Register value on runtime.
1228 * @param __HANDLE__: TIM handle.
1229 * @retval None
1230 */
1231 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
1232 ((__HANDLE__)->Instance->CNT)
1233
1234 /**
1235 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
1236 * @param __HANDLE__: TIM handle.
1237 * @param __AUTORELOAD__: specifies the Counter register new value.
1238 * @retval None
1239 */
1240 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1241 do{ \
1242 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1243 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1244 } while(0)
1245
1246 /**
1247 * @brief Get the TIM Autoreload Register value on runtime.
1248 * @param __HANDLE__: TIM handle.
1249 * @retval None
1250 */
1251 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
1252 ((__HANDLE__)->Instance->ARR)
1253
1254 /**
1255 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
1256 * @param __HANDLE__: TIM handle.
1257 * @param __CKD__: specifies the clock division value.
1258 * This parameter can be one of the following value:
1259 * @arg TIM_CLOCKDIVISION_DIV1
1260 * @arg TIM_CLOCKDIVISION_DIV2
1261 * @arg TIM_CLOCKDIVISION_DIV4
1262 * @retval None
1263 */
1264 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1265 do{ \
1266 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1267 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1268 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1269 } while(0)
1270
1271 /**
1272 * @brief Get the TIM Clock Division value on runtime.
1273 * @param __HANDLE__: TIM handle.
1274 * @retval None
1275 */
1276 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
1277 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1278
1279 /**
1280 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
1281 * @param __HANDLE__: TIM handle.
1282 * @param __CHANNEL__: TIM Channels to be configured.
1283 * This parameter can be one of the following values:
1284 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1285 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1286 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1287 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1288 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1289 * This parameter can be one of the following values:
1290 * @arg TIM_ICPSC_DIV1: no prescaler
1291 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1292 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1293 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1294 * @retval None
1295 */
1296 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1297 do{ \
1298 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1299 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1300 } while(0)
1301
1302 /**
1303 * @brief Get the TIM Input Capture prescaler on runtime.
1304 * @param __HANDLE__: TIM handle.
1305 * @param __CHANNEL__: TIM Channels to be configured.
1306 * This parameter can be one of the following values:
1307 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1308 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1309 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1310 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1311 * @retval None
1312 */
1313 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1314 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1315 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
1316 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1317 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
1318
1319 /**
1320 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
1321 * @param __HANDLE__: TIM handle.
1322 * @param __CHANNEL__: TIM Channels to be configured.
1323 * This parameter can be one of the following values:
1324 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1325 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1326 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1327 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1328 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1329 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1330 * @param __COMPARE__: specifies the Capture Compare register new value.
1331 * @retval None
1332 */
1333 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1334 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1335 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1336 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1337 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1338 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1339 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1340
1341 /**
1342 * @brief Get the TIM Capture Compare Register value on runtime.
1343 * @param __HANDLE__: TIM handle.
1344 * @param __CHANNEL__: TIM Channel associated with the capture compare register
1345 * This parameter can be one of the following values:
1346 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1347 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1348 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1349 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1350 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
1351 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
1352 * @retval None
1353 */
1354 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1355 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1356 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1357 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1358 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1359 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1360 ((__HANDLE__)->Instance->CCR6))
1361
1362 /**
1363 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
1364 * @param __HANDLE__: TIM handle.
1365 * @note When the USR bit of the TIMx_CR1 register is set, only counter
1366 * overflow/underflow generates an update interrupt or DMA request (if
1367 * enabled)
1368 * @retval None
1369 */
1370 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1371 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
1372
1373 /**
1374 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
1375 * @param __HANDLE__: TIM handle.
1376 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
1377 * following events generate an update interrupt or DMA request (if
1378 * enabled):
1379 * _ Counter overflow underflow
1380 * _ Setting the UG bit
1381 * _ Update generation through the slave mode controller
1382 * @retval None
1383 */
1384 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1385 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
1386
1387 /**
1388 * @brief Set the TIM Capture x input polarity on runtime.
1389 * @param __HANDLE__: TIM handle.
1390 * @param __CHANNEL__: TIM Channels to be configured.
1391 * This parameter can be one of the following values:
1392 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1393 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1394 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1395 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1396 * @param __POLARITY__: Polarity for TIx source
1397 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1398 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1399 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1400 * @retval None
1401 */
1402 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1403 do{ \
1404 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1405 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1406 }while(0)
1407
1408 /**
1409 * @}
1410 */
1411 /* End of exported macros ----------------------------------------------------*/
1412
1413 /* Private constants ---------------------------------------------------------*/
1414 /** @defgroup TIM_Private_Constants TIM Private Constants
1415 * @{
1416 */
1417 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1418 channels have been disabled */
1419 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1420 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1421 /**
1422 * @}
1423 */
1424 /* End of private constants --------------------------------------------------*/
1425
1426 /* Private macros ------------------------------------------------------------*/
1427 /** @defgroup TIM_Private_Macros TIM Private Macros
1428 * @{
1429 */
1430
1431 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
1432 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
1433 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
1434
1435 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1436 ((__BASE__) == TIM_DMABASE_CR2) || \
1437 ((__BASE__) == TIM_DMABASE_SMCR) || \
1438 ((__BASE__) == TIM_DMABASE_DIER) || \
1439 ((__BASE__) == TIM_DMABASE_SR) || \
1440 ((__BASE__) == TIM_DMABASE_EGR) || \
1441 ((__BASE__) == TIM_DMABASE_CCMR1) || \
1442 ((__BASE__) == TIM_DMABASE_CCMR2) || \
1443 ((__BASE__) == TIM_DMABASE_CCER) || \
1444 ((__BASE__) == TIM_DMABASE_CNT) || \
1445 ((__BASE__) == TIM_DMABASE_PSC) || \
1446 ((__BASE__) == TIM_DMABASE_ARR) || \
1447 ((__BASE__) == TIM_DMABASE_RCR) || \
1448 ((__BASE__) == TIM_DMABASE_CCR1) || \
1449 ((__BASE__) == TIM_DMABASE_CCR2) || \
1450 ((__BASE__) == TIM_DMABASE_CCR3) || \
1451 ((__BASE__) == TIM_DMABASE_CCR4) || \
1452 ((__BASE__) == TIM_DMABASE_BDTR) || \
1453 ((__BASE__) == TIM_DMABASE_CCMR3) || \
1454 ((__BASE__) == TIM_DMABASE_CCR5) || \
1455 ((__BASE__) == TIM_DMABASE_CCR6) || \
1456 ((__BASE__) == TIM_DMABASE_OR1) || \
1457 ((__BASE__) == TIM_DMABASE_OR2) || \
1458 ((__BASE__) == TIM_DMABASE_OR3))
1459
1460
1461 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
1462
1463
1464 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1465 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1466 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1467 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1468 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1469
1470 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1471 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1472 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1473
1474 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1475 ((__STATE__) == TIM_OCFAST_ENABLE))
1476
1477 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1478 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1479
1480 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1481 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1482
1483 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1484 ((__STATE__) == TIM_OCIDLESTATE_RESET))
1485
1486 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1487 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1488
1489 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1490 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1491 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1492
1493 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1494 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1495 ((__SELECTION__) == TIM_ICSELECTION_TRC))
1496
1497 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1498 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1499 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1500 ((__PRESCALER__) == TIM_ICPSC_DIV8))
1501
1502 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1503 ((__MODE__) == TIM_OPMODE_REPETITIVE))
1504
1505 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1506 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1507 ((__MODE__) == TIM_ENCODERMODE_TI12))
1508
1509 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
1510
1511 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1512 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1513 ((__CHANNEL__) == TIM_CHANNEL_3) || \
1514 ((__CHANNEL__) == TIM_CHANNEL_4) || \
1515 ((__CHANNEL__) == TIM_CHANNEL_5) || \
1516 ((__CHANNEL__) == TIM_CHANNEL_6) || \
1517 ((__CHANNEL__) == TIM_CHANNEL_ALL))
1518
1519 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1520 ((__CHANNEL__) == TIM_CHANNEL_2))
1521
1522 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1523 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1524 ((__CHANNEL__) == TIM_CHANNEL_3))
1525
1526 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1527 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1528 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1529 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1530 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1531 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1532 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1533 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1534 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1535 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1536
1537 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1538 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1539 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1540 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1541 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1542
1543 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1544 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1545 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1546 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1547
1548 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
1549
1550 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1551 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1552
1553 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1554 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1555 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1556 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1557
1558 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
1559
1560
1561 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1562 ((__STATE__) == TIM_OSSR_DISABLE))
1563
1564 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1565 ((__STATE__) == TIM_OSSI_DISABLE))
1566
1567 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1568 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1569 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1570 ((__LEVEL__) == TIM_LOCKLEVEL_3))
1571
1572 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF)
1573
1574
1575 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1576 ((__STATE__) == TIM_BREAK_DISABLE))
1577
1578 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1579 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1580
1581 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
1582 ((__STATE__) == TIM_BREAK2_DISABLE))
1583
1584 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
1585 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1586
1587 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1588 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1589
1590 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000))
1591
1592 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1593 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1594 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1595 ((__SOURCE__) == TIM_TRGO_OC1) || \
1596 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1597 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1598 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1599 ((__SOURCE__) == TIM_TRGO_OC4REF))
1600
1601 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
1602 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
1603 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
1604 ((__SOURCE__) == TIM_TRGO2_OC1) || \
1605 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
1606 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
1607 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1608 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1609 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
1610 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
1611 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
1612 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
1613 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
1614 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
1615 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
1616 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
1617 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
1618
1619 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1620 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1621
1622 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1623 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1624 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1625 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1626 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
1627 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
1628
1629 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1630 ((__MODE__) == TIM_OCMODE_PWM2) || \
1631 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
1632 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
1633 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
1634 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
1635
1636 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1637 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1638 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1639 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1640 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1641 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
1642 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
1643 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
1644
1645 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1646 ((__SELECTION__) == TIM_TS_ITR1) || \
1647 ((__SELECTION__) == TIM_TS_ITR2) || \
1648 ((__SELECTION__) == TIM_TS_ITR3) || \
1649 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1650 ((__SELECTION__) == TIM_TS_TI1FP1) || \
1651 ((__SELECTION__) == TIM_TS_TI2FP2) || \
1652 ((__SELECTION__) == TIM_TS_ETRF))
1653
1654 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1655 ((__SELECTION__) == TIM_TS_ITR1) || \
1656 ((__SELECTION__) == TIM_TS_ITR2) || \
1657 ((__SELECTION__) == TIM_TS_ITR3) || \
1658 ((__SELECTION__) == TIM_TS_NONE))
1659
1660
1661 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1662 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1663 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1664 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1665 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1666
1667 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1668 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1669 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1670 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1671
1672 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
1673
1674 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1675 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
1676
1677 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1678 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1679 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1680 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1681 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1682 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1683 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1684 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1685 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1686 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1687 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1688 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1689 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1690 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1691 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1692 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1693 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1694 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
1695
1696 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
1697
1698 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
1699
1700 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
1701 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
1702 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \
1703 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
1704
1705 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1706 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1707 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
1708 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1709 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
1710
1711 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1712 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1713 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1714 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1715 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1716
1717 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1718 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1719 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
1720 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
1721 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
1722
1723 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1724 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1725 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1726 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
1727 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
1728
1729 /**
1730 * @}
1731 */
1732 /* End of private macros -----------------------------------------------------*/
1733
1734 /* Include TIM HAL Extended module */
1735 #include "stm32l4xx_hal_tim_ex.h"
1736
1737 /* Exported functions --------------------------------------------------------*/
1738 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
1739 * @{
1740 */
1741
1742 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
1743 * @brief Time Base functions
1744 * @{
1745 */
1746 /* Time Base functions ********************************************************/
1747 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1748 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1749 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1750 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1751 /* Blocking mode: Polling */
1752 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1753 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1754 /* Non-Blocking mode: Interrupt */
1755 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1756 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1757 /* Non-Blocking mode: DMA */
1758 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1759 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1760 /**
1761 * @}
1762 */
1763
1764 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
1765 * @brief Time Output Compare functions
1766 * @{
1767 */
1768 /* Timer Output Compare functions *********************************************/
1769 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1770 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1771 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1772 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1773 /* Blocking mode: Polling */
1774 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1775 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1776 /* Non-Blocking mode: Interrupt */
1777 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1778 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1779 /* Non-Blocking mode: DMA */
1780 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1781 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1782 /**
1783 * @}
1784 */
1785
1786 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
1787 * @brief Time PWM functions
1788 * @{
1789 */
1790 /* Timer PWM functions ********************************************************/
1791 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1792 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1793 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1794 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1795 /* Blocking mode: Polling */
1796 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1797 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1798 /* Non-Blocking mode: Interrupt */
1799 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1800 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1801 /* Non-Blocking mode: DMA */
1802 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1803 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1804 /**
1805 * @}
1806 */
1807
1808 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
1809 * @brief Time Input Capture functions
1810 * @{
1811 */
1812 /* Timer Input Capture functions **********************************************/
1813 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1814 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1815 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1816 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1817 /* Blocking mode: Polling */
1818 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1819 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1820 /* Non-Blocking mode: Interrupt */
1821 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1822 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1823 /* Non-Blocking mode: DMA */
1824 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1825 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1826 /**
1827 * @}
1828 */
1829
1830 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
1831 * @brief Time One Pulse functions
1832 * @{
1833 */
1834 /* Timer One Pulse functions **************************************************/
1835 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1836 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1837 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1838 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1839 /* Blocking mode: Polling */
1840 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1841 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1842 /* Non-Blocking mode: Interrupt */
1843 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1844 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1845 /**
1846 * @}
1847 */
1848
1849 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
1850 * @brief Time Encoder functions
1851 * @{
1852 */
1853 /* Timer Encoder functions ****************************************************/
1854 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1855 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1856 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1857 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1858 /* Blocking mode: Polling */
1859 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1860 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1861 /* Non-Blocking mode: Interrupt */
1862 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1863 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1864 /* Non-Blocking mode: DMA */
1865 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1866 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1867 /**
1868 * @}
1869 */
1870
1871 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
1872 * @brief IRQ handler management
1873 * @{
1874 */
1875 /* Interrupt Handler functions ***********************************************/
1876 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1877 /**
1878 * @}
1879 */
1880
1881 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
1882 * @brief Peripheral Control functions
1883 * @{
1884 */
1885 /* Control functions *********************************************************/
1886 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1887 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1888 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1889 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1890 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1891 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1892 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1893 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1894 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1895 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1896 uint32_t *BurstBuffer, uint32_t BurstLength);
1897 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1898 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1899 uint32_t *BurstBuffer, uint32_t BurstLength);
1900 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1901 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1902 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1903 /**
1904 * @}
1905 */
1906
1907 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
1908 * @brief TIM Callbacks functions
1909 * @{
1910 */
1911 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1912 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1913 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1914 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1915 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1916 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1917 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1918 /**
1919 * @}
1920 */
1921
1922 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
1923 * @brief Peripheral State functions
1924 * @{
1925 */
1926 /* Peripheral State functions ************************************************/
1927 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1928 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1929 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1930 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1931 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1932 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1933 /**
1934 * @}
1935 */
1936
1937 /**
1938 * @}
1939 */
1940 /* End of exported functions -------------------------------------------------*/
1941
1942 /* Private functions----------------------------------------------------------*/
1943 /** @defgroup TIM_Private_Functions TIM Private Functions
1944 * @{
1945 */
1946 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1947 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1948 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1949 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
1950 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
1951
1952 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1953 void TIM_DMAError(DMA_HandleTypeDef *hdma);
1954 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1955 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1956 /**
1957 * @}
1958 */
1959 /* End of private functions --------------------------------------------------*/
1960
1961 /**
1962 * @}
1963 */
1964
1965 /**
1966 * @}
1967 */
1968
1969 #ifdef __cplusplus
1970 }
1971 #endif
1972
1973 #endif /* __STM32L4xx_HAL_TIM_H */
1974
1975 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/