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comparison l476rg/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c @ 0:32a3b1785697

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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_flash_ex.c
4 * @author MCD Application Team
5 * @version V1.6.0
6 * @date 28-October-2016
7 * @brief Extended FLASH HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the FLASH extended peripheral:
10 * + Extended programming operations functions
11 *
12 @verbatim
13 ==============================================================================
14 ##### Flash Extended features #####
15 ==============================================================================
16
17 [..] Comparing to other previous devices, the FLASH interface for STM32L4xx
18 devices contains the following additional features
19
20 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
21 capability (RWW)
22 (+) Dual bank memory organization
23 (+) PCROP protection for all banks
24
25 ##### How to use this driver #####
26 ==============================================================================
27 [..] This driver provides functions to configure and program the FLASH memory
28 of all STM32L4xx devices. It includes
29 (#) Flash Memory Erase functions:
30 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
31 HAL_FLASH_Lock() functions
32 (++) Erase function: Erase page, erase all sectors
33 (++) There are two modes of erase :
34 (+++) Polling Mode using HAL_FLASHEx_Erase()
35 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
36
37 (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
38 (++) Set/Reset the write protection
39 (++) Set the Read protection Level
40 (++) Program the user Option Bytes
41 (++) Configure the PCROP protection
42
43 (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
44 (++) Get the value of a write protection area
45 (++) Know if the read protection is activated
46 (++) Get the value of the user Option Bytes
47 (++) Get the value of a PCROP area
48
49 @endverbatim
50 ******************************************************************************
51 * @attention
52 *
53 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
54 *
55 * Redistribution and use in source and binary forms, with or without modification,
56 * are permitted provided that the following conditions are met:
57 * 1. Redistributions of source code must retain the above copyright notice,
58 * this list of conditions and the following disclaimer.
59 * 2. Redistributions in binary form must reproduce the above copyright notice,
60 * this list of conditions and the following disclaimer in the documentation
61 * and/or other materials provided with the distribution.
62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
63 * may be used to endorse or promote products derived from this software
64 * without specific prior written permission.
65 *
66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
76 *
77 ******************************************************************************
78 */
79
80 /* Includes ------------------------------------------------------------------*/
81 #include "stm32l4xx_hal.h"
82
83 /** @addtogroup STM32L4xx_HAL_Driver
84 * @{
85 */
86
87 /** @defgroup FLASHEx FLASHEx
88 * @brief FALSH Extended HAL module driver
89 * @{
90 */
91
92 #ifdef HAL_FLASH_MODULE_ENABLED
93
94 /* Private typedef -----------------------------------------------------------*/
95 /* Private define ------------------------------------------------------------*/
96 /* Private macro -------------------------------------------------------------*/
97 /* Private variables ---------------------------------------------------------*/
98 /** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables
99 * @{
100 */
101 extern FLASH_ProcessTypeDef pFlash;
102 /**
103 * @}
104 */
105
106 /* Private function prototypes -----------------------------------------------*/
107 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
108 * @{
109 */
110 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
111 void FLASH_PageErase(uint32_t Page, uint32_t Banks);
112 static void FLASH_MassErase(uint32_t Banks);
113 void FLASH_FlushCaches(void);
114 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
115 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
116 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
117 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
118 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);
119 static uint32_t FLASH_OB_GetRDP(void);
120 static uint32_t FLASH_OB_GetUser(void);
121 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);
122 /**
123 * @}
124 */
125
126 /* Exported functions -------------------------------------------------------*/
127 /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
128 * @{
129 */
130
131 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
132 * @brief Extended IO operation functions
133 *
134 @verbatim
135 ===============================================================================
136 ##### Extended programming operation functions #####
137 ===============================================================================
138 [..]
139 This subsection provides a set of functions allowing to manage the Extended FLASH
140 programming operations Operations.
141
142 @endverbatim
143 * @{
144 */
145 /**
146 * @brief Perform a mass erase or erase the specified FLASH memory pages.
147 * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
148 * contains the configuration information for the erasing.
149 *
150 * @param[out] PageError : pointer to variable that contains the configuration
151 * information on faulty page in case of error (0xFFFFFFFF means that all
152 * the pages have been correctly erased)
153 *
154 * @retval HAL Status
155 */
156 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
157 {
158 HAL_StatusTypeDef status = HAL_ERROR;
159 uint32_t page_index = 0;
160
161 /* Process Locked */
162 __HAL_LOCK(&pFlash);
163
164 /* Check the parameters */
165 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
166
167 /* Wait for last operation to be completed */
168 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
169
170 if (status == HAL_OK)
171 {
172 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
173
174 /* Deactivate the cache if they are activated to avoid data misbehavior */
175 if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
176 {
177 /* Disable instruction cache */
178 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
179
180 if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
181 {
182 /* Disable data cache */
183 __HAL_FLASH_DATA_CACHE_DISABLE();
184 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
185 }
186 else
187 {
188 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
189 }
190 }
191 else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
192 {
193 /* Disable data cache */
194 __HAL_FLASH_DATA_CACHE_DISABLE();
195 pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
196 }
197 else
198 {
199 pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
200 }
201
202 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
203 {
204 /* Mass erase to be done */
205 FLASH_MassErase(pEraseInit->Banks);
206
207 /* Wait for last operation to be completed */
208 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
209
210 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
211 /* If the erase operation is completed, disable the MER1 and MER2 Bits */
212 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
213 #else
214 /* If the erase operation is completed, disable the MER1 Bit */
215 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
216 #endif
217 }
218 else
219 {
220 /*Initialization of PageError variable*/
221 *PageError = 0xFFFFFFFF;
222
223 for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
224 {
225 FLASH_PageErase(page_index, pEraseInit->Banks);
226
227 /* Wait for last operation to be completed */
228 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
229
230 /* If the erase operation is completed, disable the PER Bit */
231 CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
232
233 if (status != HAL_OK)
234 {
235 /* In case of error, stop erase procedure and return the faulty address */
236 *PageError = page_index;
237 break;
238 }
239 }
240 }
241
242 /* Flush the caches to be sure of the data consistency */
243 FLASH_FlushCaches();
244 }
245
246 /* Process Unlocked */
247 __HAL_UNLOCK(&pFlash);
248
249 return status;
250 }
251
252 /**
253 * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
254 * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
255 * contains the configuration information for the erasing.
256 *
257 * @retval HAL Status
258 */
259 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
260 {
261 HAL_StatusTypeDef status = HAL_OK;
262
263 /* Process Locked */
264 __HAL_LOCK(&pFlash);
265
266 /* Check the parameters */
267 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
268
269 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
270
271 /* Deactivate the cache if they are activated to avoid data misbehavior */
272 if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
273 {
274 /* Disable instruction cache */
275 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
276
277 if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
278 {
279 /* Disable data cache */
280 __HAL_FLASH_DATA_CACHE_DISABLE();
281 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
282 }
283 else
284 {
285 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
286 }
287 }
288 else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
289 {
290 /* Disable data cache */
291 __HAL_FLASH_DATA_CACHE_DISABLE();
292 pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
293 }
294 else
295 {
296 pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
297 }
298
299 /* Enable End of Operation and Error interrupts */
300 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
301
302 pFlash.Bank = pEraseInit->Banks;
303
304 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
305 {
306 /* Mass erase to be done */
307 pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
308 FLASH_MassErase(pEraseInit->Banks);
309 }
310 else
311 {
312 /* Erase by page to be done */
313 pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
314 pFlash.NbPagesToErase = pEraseInit->NbPages;
315 pFlash.Page = pEraseInit->Page;
316
317 /*Erase 1st page and wait for IT */
318 FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
319 }
320
321 return status;
322 }
323
324 /**
325 * @brief Program Option bytes.
326 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
327 * contains the configuration information for the programming.
328 *
329 * @retval HAL Status
330 */
331 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
332 {
333 HAL_StatusTypeDef status = HAL_ERROR;
334
335 /* Process Locked */
336 __HAL_LOCK(&pFlash);
337
338 /* Check the parameters */
339 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
340
341 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
342
343 /* Write protection configuration */
344 if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET)
345 {
346 /* Configure of Write protection on the selected area */
347 status = FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
348 }
349
350 /* Read protection configuration */
351 if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
352 {
353 /* Configure the Read protection level */
354 status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
355 }
356
357 /* User Configuration */
358 if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
359 {
360 /* Configure the user option bytes */
361 status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
362 }
363
364 /* PCROP Configuration */
365 if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
366 {
367 if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)
368 {
369 /* Configure the Proprietary code readout protection */
370 status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr);
371 }
372 }
373
374 /* Process Unlocked */
375 __HAL_UNLOCK(&pFlash);
376
377 return status;
378 }
379
380 /**
381 * @brief Get the Option bytes configuration.
382 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the
383 * configuration information.
384 * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
385 * which area is requested for the WRP and PCROP, else no information will be returned
386 *
387 * @retval None
388 */
389 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
390 {
391 pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
392
393 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
394 if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
395 (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
396 #else
397 if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
398 #endif
399 {
400 pOBInit->OptionType |= OPTIONBYTE_WRP;
401 /* Get write protection on the selected area */
402 FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
403 }
404
405 /* Get Read protection level */
406 pOBInit->RDPLevel = FLASH_OB_GetRDP();
407
408 /* Get the user option bytes */
409 pOBInit->USERConfig = FLASH_OB_GetUser();
410
411 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
412 if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))
413 #else
414 if(pOBInit->PCROPConfig == FLASH_BANK_1)
415 #endif
416 {
417 pOBInit->OptionType |= OPTIONBYTE_PCROP;
418 /* Get the Proprietary code readout protection */
419 FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
420 }
421 }
422
423 /**
424 * @}
425 */
426
427 /**
428 * @}
429 */
430
431 /* Private functions ---------------------------------------------------------*/
432
433 /** @addtogroup FLASHEx_Private_Functions
434 * @{
435 */
436 /**
437 * @brief Mass erase of FLASH memory.
438 * @param Banks: Banks to be erased
439 * This parameter can be one of the following values:
440 * @arg FLASH_BANK_1: Bank1 to be erased
441 * @arg FLASH_BANK_2: Bank2 to be erased
442 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
443 * @retval None
444 */
445 static void FLASH_MassErase(uint32_t Banks)
446 {
447 {
448 /* Check the parameters */
449 assert_param(IS_FLASH_BANK(Banks));
450
451 /* Set the Mass Erase Bit for the bank 1 if requested */
452 if((Banks & FLASH_BANK_1) != RESET)
453 {
454 SET_BIT(FLASH->CR, FLASH_CR_MER1);
455 }
456
457 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
458 /* Set the Mass Erase Bit for the bank 2 if requested */
459 if((Banks & FLASH_BANK_2) != RESET)
460 {
461 SET_BIT(FLASH->CR, FLASH_CR_MER2);
462 }
463 #endif
464 }
465
466 /* Proceed to erase all sectors */
467 SET_BIT(FLASH->CR, FLASH_CR_STRT);
468 }
469
470 /**
471 * @brief Erase the specified FLASH memory page.
472 * @param Page: FLASH page to erase
473 * This parameter must be a value between 0 and (max number of pages in the bank - 1)
474 * @param Banks: Bank(s) where the page will be erased
475 * This parameter can be one or a combination of the following values:
476 * @arg FLASH_BANK_1: Page in bank 1 to be erased
477 * @arg FLASH_BANK_2: Page in bank 2 to be erased
478 * @retval None
479 */
480 void FLASH_PageErase(uint32_t Page, uint32_t Banks)
481 {
482 /* Check the parameters */
483 assert_param(IS_FLASH_PAGE(Page));
484
485 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
486 {
487 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
488
489 if((Banks & FLASH_BANK_1) != RESET)
490 {
491 CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
492 }
493 else
494 {
495 SET_BIT(FLASH->CR, FLASH_CR_BKER);
496 }
497 }
498 #endif
499
500 /* Proceed to erase the page */
501 MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << POSITION_VAL(FLASH_CR_PNB)));
502 SET_BIT(FLASH->CR, FLASH_CR_PER);
503 SET_BIT(FLASH->CR, FLASH_CR_STRT);
504 }
505
506 /**
507 * @brief Flush the instruction and data caches.
508 * @retval None
509 */
510 void FLASH_FlushCaches(void)
511 {
512 /* Flush instruction cache */
513 if((pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_ENABLED) ||
514 (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
515 {
516 /* Reset instruction cache */
517 __HAL_FLASH_INSTRUCTION_CACHE_RESET();
518 /* Enable instruction cache */
519 __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
520 }
521
522 /* Flush data cache */
523 if((pFlash.CacheToReactivate == FLASH_CACHE_DCACHE_ENABLED) ||
524 (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
525 {
526 /* Reset data cache */
527 __HAL_FLASH_DATA_CACHE_RESET();
528 /* Enable data cache */
529 __HAL_FLASH_DATA_CACHE_ENABLE();
530 }
531
532 /* Reset internal variable */
533 pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
534 }
535
536 /**
537 * @brief Configure the write protection of the desired pages.
538 *
539 * @note When the memory read protection level is selected (RDP level = 1),
540 * it is not possible to program or erase Flash memory if the CPU debug
541 * features are connected (JTAG or single wire) or boot code is being
542 * executed from RAM or System flash, even if WRP is not activated.
543 * @note To configure the WRP options, the option lock bit OPTLOCK must be
544 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
545 * @note To validate the WRP options, the option bytes must be reloaded
546 * through the call of the HAL_FLASH_OB_Launch() function.
547 *
548 * @param WRPArea: specifies the area to be configured.
549 * This parameter can be one of the following values:
550 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
551 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
552 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices)
553 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices)
554 *
555 * @param WRPStartOffset: specifies the start page of the write protected area
556 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
557 *
558 * @param WRDPEndOffset: specifies the end page of the write protected area
559 * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
560 *
561 * @retval HAL Status
562 */
563 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
564 {
565 HAL_StatusTypeDef status = HAL_OK;
566
567 /* Check the parameters */
568 assert_param(IS_OB_WRPAREA(WRPArea));
569 assert_param(IS_FLASH_PAGE(WRPStartOffset));
570 assert_param(IS_FLASH_PAGE(WRDPEndOffset));
571
572 /* Wait for last operation to be completed */
573 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
574
575 if(status == HAL_OK)
576 {
577 /* Configure the write protected area */
578 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
579 {
580 MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
581 (WRPStartOffset | (WRDPEndOffset << 16)));
582 }
583 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
584 {
585 MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
586 (WRPStartOffset | (WRDPEndOffset << 16)));
587 }
588 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
589 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
590 {
591 MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),
592 (WRPStartOffset | (WRDPEndOffset << 16)));
593 }
594 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
595 {
596 MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),
597 (WRPStartOffset | (WRDPEndOffset << 16)));
598 }
599 #endif
600
601 /* Set OPTSTRT Bit */
602 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
603
604 /* Wait for last operation to be completed */
605 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
606
607 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
608 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
609 }
610
611 return status;
612 }
613
614 /**
615 * @brief Set the read protection level.
616 *
617 * @note To configure the RDP level, the option lock bit OPTLOCK must be
618 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
619 * @note To validate the RDP level, the option bytes must be reloaded
620 * through the call of the HAL_FLASH_OB_Launch() function.
621 * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
622 * to go back to level 1 or 0 !!!
623 *
624 * @param RDPLevel: specifies the read protection level.
625 * This parameter can be one of the following values:
626 * @arg OB_RDP_LEVEL_0: No protection
627 * @arg OB_RDP_LEVEL_1: Read protection of the memory
628 * @arg OB_RDP_LEVEL_2: Full chip protection
629 *
630 * @retval HAL status
631 */
632 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
633 {
634 HAL_StatusTypeDef status = HAL_OK;
635
636 /* Check the parameters */
637 assert_param(IS_OB_RDP_LEVEL(RDPLevel));
638
639 /* Wait for last operation to be completed */
640 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
641
642 if(status == HAL_OK)
643 {
644 /* Configure the RDP level in the option bytes register */
645 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
646
647 /* Set OPTSTRT Bit */
648 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
649
650 /* Wait for last operation to be completed */
651 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
652
653 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
654 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
655 }
656
657 return status;
658 }
659
660 /**
661 * @brief Program the FLASH User Option Byte.
662 *
663 * @note To configure the user option bytes, the option lock bit OPTLOCK must
664 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
665 * @note To validate the user option bytes, the option bytes must be reloaded
666 * through the call of the HAL_FLASH_OB_Launch() function.
667 *
668 * @param UserType: The FLASH User Option Bytes to be modified
669 * @param UserConfig: The FLASH User Option Bytes values:
670 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),
671 * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20),
672 * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
673 *
674 * @retval HAL status
675 */
676 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
677 {
678 uint32_t optr_reg_val = 0;
679 uint32_t optr_reg_mask = 0;
680 HAL_StatusTypeDef status = HAL_OK;
681
682 /* Check the parameters */
683 assert_param(IS_OB_USER_TYPE(UserType));
684
685 /* Wait for last operation to be completed */
686 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
687
688 if(status == HAL_OK)
689 {
690 if((UserType & OB_USER_BOR_LEV) != RESET)
691 {
692 /* BOR level option byte should be modified */
693 assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
694
695 /* Set value and mask for BOR level option byte */
696 optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
697 optr_reg_mask |= FLASH_OPTR_BOR_LEV;
698 }
699
700 if((UserType & OB_USER_nRST_STOP) != RESET)
701 {
702 /* nRST_STOP option byte should be modified */
703 assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
704
705 /* Set value and mask for nRST_STOP option byte */
706 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
707 optr_reg_mask |= FLASH_OPTR_nRST_STOP;
708 }
709
710 if((UserType & OB_USER_nRST_STDBY) != RESET)
711 {
712 /* nRST_STDBY option byte should be modified */
713 assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
714
715 /* Set value and mask for nRST_STDBY option byte */
716 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
717 optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
718 }
719
720 if((UserType & OB_USER_nRST_SHDW) != RESET)
721 {
722 /* nRST_SHDW option byte should be modified */
723 assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
724
725 /* Set value and mask for nRST_SHDW option byte */
726 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
727 optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
728 }
729
730 if((UserType & OB_USER_IWDG_SW) != RESET)
731 {
732 /* IWDG_SW option byte should be modified */
733 assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
734
735 /* Set value and mask for IWDG_SW option byte */
736 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
737 optr_reg_mask |= FLASH_OPTR_IWDG_SW;
738 }
739
740 if((UserType & OB_USER_IWDG_STOP) != RESET)
741 {
742 /* IWDG_STOP option byte should be modified */
743 assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
744
745 /* Set value and mask for IWDG_STOP option byte */
746 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
747 optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
748 }
749
750 if((UserType & OB_USER_IWDG_STDBY) != RESET)
751 {
752 /* IWDG_STDBY option byte should be modified */
753 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
754
755 /* Set value and mask for IWDG_STDBY option byte */
756 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
757 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
758 }
759
760 if((UserType & OB_USER_WWDG_SW) != RESET)
761 {
762 /* WWDG_SW option byte should be modified */
763 assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
764
765 /* Set value and mask for WWDG_SW option byte */
766 optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
767 optr_reg_mask |= FLASH_OPTR_WWDG_SW;
768 }
769
770 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
771 if((UserType & OB_USER_BFB2) != RESET)
772 {
773 /* BFB2 option byte should be modified */
774 assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
775
776 /* Set value and mask for BFB2 option byte */
777 optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
778 optr_reg_mask |= FLASH_OPTR_BFB2;
779 }
780
781 if((UserType & OB_USER_DUALBANK) != RESET)
782 {
783 /* DUALBANK option byte should be modified */
784 assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
785
786 /* Set value and mask for DUALBANK option byte */
787 optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
788 optr_reg_mask |= FLASH_OPTR_DUALBANK;
789 }
790 #endif
791
792 if((UserType & OB_USER_nBOOT1) != RESET)
793 {
794 /* nBOOT1 option byte should be modified */
795 assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
796
797 /* Set value and mask for nBOOT1 option byte */
798 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
799 optr_reg_mask |= FLASH_OPTR_nBOOT1;
800 }
801
802 if((UserType & OB_USER_SRAM2_PE) != RESET)
803 {
804 /* SRAM2_PE option byte should be modified */
805 assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
806
807 /* Set value and mask for SRAM2_PE option byte */
808 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
809 optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
810 }
811
812 if((UserType & OB_USER_SRAM2_RST) != RESET)
813 {
814 /* SRAM2_RST option byte should be modified */
815 assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
816
817 /* Set value and mask for SRAM2_RST option byte */
818 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
819 optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
820 }
821
822 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
823 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
824 if((UserType & OB_USER_nSWBOOT0) != RESET)
825 {
826 /* nSWBOOT0 option byte should be modified */
827 assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
828
829 /* Set value and mask for nSWBOOT0 option byte */
830 optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
831 optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
832 }
833
834 if((UserType & OB_USER_nBOOT0) != RESET)
835 {
836 /* nBOOT0 option byte should be modified */
837 assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
838
839 /* Set value and mask for nBOOT0 option byte */
840 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
841 optr_reg_mask |= FLASH_OPTR_nBOOT0;
842 }
843 #endif
844
845 /* Configure the option bytes register */
846 MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
847
848 /* Set OPTSTRT Bit */
849 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
850
851 /* Wait for last operation to be completed */
852 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
853
854 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
855 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
856 }
857
858 return status;
859 }
860
861 /**
862 * @brief Configure the Proprietary code readout protection of the desired addresses.
863 *
864 * @note To configure the PCROP options, the option lock bit OPTLOCK must be
865 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
866 * @note To validate the PCROP options, the option bytes must be reloaded
867 * through the call of the HAL_FLASH_OB_Launch() function.
868 *
869 * @param PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).
870 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
871 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
872 *
873 * @param PCROPStartAddr: specifies the start address of the Proprietary code readout protection
874 * This parameter can be an address between begin and end of the bank
875 *
876 * @param PCROPEndAddr: specifies the end address of the Proprietary code readout protection
877 * This parameter can be an address between PCROPStartAddr and end of the bank
878 *
879 * @retval HAL Status
880 */
881 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
882 {
883 HAL_StatusTypeDef status = HAL_OK;
884 uint32_t reg_value = 0;
885 uint32_t bank1_addr;
886 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
887 uint32_t bank2_addr;
888 #endif
889
890 /* Check the parameters */
891 assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
892 assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
893 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
894 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
895
896 /* Wait for last operation to be completed */
897 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
898
899 if(status == HAL_OK)
900 {
901 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
902 /* Get the information about the bank swapping */
903 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
904 {
905 bank1_addr = FLASH_BASE;
906 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
907 }
908 else
909 {
910 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
911 bank2_addr = FLASH_BASE;
912 }
913 #else
914 bank1_addr = FLASH_BASE;
915 #endif
916
917 {
918 /* Configure the Proprietary code readout protection */
919 if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
920 {
921 reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
922 MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
923
924 reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
925 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
926 }
927 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
928 else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
929 {
930 reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
931 MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
932
933 reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
934 MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
935 }
936 #endif
937 }
938
939 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
940
941 /* Set OPTSTRT Bit */
942 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
943
944 /* Wait for last operation to be completed */
945 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
946
947 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
948 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
949 }
950
951 return status;
952 }
953
954 /**
955 * @brief Return the FLASH Write Protection Option Bytes value.
956 *
957 * @param[in] WRPArea: specifies the area to be returned.
958 * This parameter can be one of the following values:
959 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
960 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
961 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)
962 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)
963 *
964 * @param[out] WRPStartOffset: specifies the address where to copied the start page
965 * of the write protected area
966 *
967 * @param[out] WRDPEndOffset: specifies the address where to copied the end page of
968 * the write protected area
969 *
970 * @retval None
971 */
972 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
973 {
974 /* Get the configuration of the write protected area */
975 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
976 {
977 *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
978 *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);
979 }
980 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
981 {
982 *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
983 *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
984 }
985 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
986 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
987 {
988 *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
989 *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);
990 }
991 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
992 {
993 *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
994 *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);
995 }
996 #endif
997 }
998
999 /**
1000 * @brief Return the FLASH Read Protection level.
1001 * @retval FLASH ReadOut Protection Status:
1002 * This return value can be one of the following values:
1003 * @arg OB_RDP_LEVEL_0: No protection
1004 * @arg OB_RDP_LEVEL_1: Read protection of the memory
1005 * @arg OB_RDP_LEVEL_2: Full chip protection
1006 */
1007 static uint32_t FLASH_OB_GetRDP(void)
1008 {
1009 if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) &&
1010 (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2))
1011 {
1012 return (OB_RDP_LEVEL_1);
1013 }
1014 else
1015 {
1016 return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));
1017 }
1018 }
1019
1020 /**
1021 * @brief Return the FLASH User Option Byte value.
1022 * @retval The FLASH User Option Bytes values:
1023 * For STM32L47x/STM32L48x devices :
1024 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
1025 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
1026 * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
1027 * For STM32L43x/STM32L44x devices :
1028 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
1029 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
1030 * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27).
1031 */
1032 static uint32_t FLASH_OB_GetUser(void)
1033 {
1034 uint32_t user_config = READ_REG(FLASH->OPTR);
1035 CLEAR_BIT(user_config, FLASH_OPTR_RDP);
1036
1037 return user_config;
1038 }
1039
1040 /**
1041 * @brief Return the FLASH Write Protection Option Bytes value.
1042 *
1043 * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).
1044 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
1045 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
1046 *
1047 * @param PCROPStartAddr [out]: specifies the address where to copied the start address
1048 * of the Proprietary code readout protection
1049 *
1050 * @param PCROPEndAddr [out]: specifies the address where to copied the end address of
1051 * the Proprietary code readout protection
1052 *
1053 * @retval None
1054 */
1055 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)
1056 {
1057 uint32_t reg_value = 0;
1058 uint32_t bank1_addr;
1059 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
1060 uint32_t bank2_addr;
1061 #endif
1062
1063 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
1064 /* Get the information about the bank swapping */
1065 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
1066 {
1067 bank1_addr = FLASH_BASE;
1068 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
1069 }
1070 else
1071 {
1072 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
1073 bank2_addr = FLASH_BASE;
1074 }
1075 #else
1076 bank1_addr = FLASH_BASE;
1077 #endif
1078
1079 {
1080 if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
1081 {
1082 reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
1083 *PCROPStartAddr = (reg_value << 3) + bank1_addr;
1084
1085 reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
1086 *PCROPEndAddr = (reg_value << 3) + bank1_addr;
1087 }
1088 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
1089 else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
1090 {
1091 reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
1092 *PCROPStartAddr = (reg_value << 3) + bank2_addr;
1093
1094 reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
1095 *PCROPEndAddr = (reg_value << 3) + bank2_addr;
1096 }
1097 #endif
1098 }
1099
1100 *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
1101 }
1102 /**
1103 * @}
1104 */
1105
1106 /**
1107 * @}
1108 */
1109
1110 #endif /* HAL_FLASH_MODULE_ENABLED */
1111
1112 /**
1113 * @}
1114 */
1115
1116 /**
1117 * @}
1118 */
1119
1120 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/