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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_pwr.c
4 * @author MCD Application Team
5 * @version V1.6.0
6 * @date 28-October-2016
7 * @brief PWR HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Power Controller (PWR) peripheral:
10 * + Initialization/de-initialization functions
11 * + Peripheral Control functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
17 *
18 * Redistribution and use in source and binary forms, with or without modification,
19 * are permitted provided that the following conditions are met:
20 * 1. Redistributions of source code must retain the above copyright notice,
21 * this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 ******************************************************************************
41 */
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32l4xx_hal.h"
45
46 /** @addtogroup STM32L4xx_HAL_Driver
47 * @{
48 */
49
50 /** @defgroup PWR PWR
51 * @brief PWR HAL module driver
52 * @{
53 */
54
55 #ifdef HAL_PWR_MODULE_ENABLED
56
57 /* Private typedef -----------------------------------------------------------*/
58 /* Private define ------------------------------------------------------------*/
59
60 /** @defgroup PWR_Private_Defines PWR Private Defines
61 * @{
62 */
63
64 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
65 * @{
66 */
67 #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
68 #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
69 #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
70 #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
71 /**
72 * @}
73 */
74
75 /**
76 * @}
77 */
78
79 /* Private macro -------------------------------------------------------------*/
80 /* Private variables ---------------------------------------------------------*/
81 /* Private function prototypes -----------------------------------------------*/
82 /* Exported functions --------------------------------------------------------*/
83
84 /** @defgroup PWR_Exported_Functions PWR Exported Functions
85 * @{
86 */
87
88 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
89 * @brief Initialization and de-initialization functions
90 *
91 @verbatim
92 ===============================================================================
93 ##### Initialization and de-initialization functions #####
94 ===============================================================================
95 [..]
96
97 @endverbatim
98 * @{
99 */
100
101 /**
102 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
103 * @retval None
104 */
105 void HAL_PWR_DeInit(void)
106 {
107 __HAL_RCC_PWR_FORCE_RESET();
108 __HAL_RCC_PWR_RELEASE_RESET();
109 }
110
111 /**
112 * @brief Enable access to the backup domain
113 * (RTC registers, RTC backup data registers).
114 * @note After reset, the backup domain is protected against
115 * possible unwanted write accesses.
116 * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
117 * In order to set or modify the RTC clock, the backup domain access must be
118 * disabled.
119 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
120 * back-up domain.
121 * @retval None
122 */
123 void HAL_PWR_EnableBkUpAccess(void)
124 {
125 SET_BIT(PWR->CR1, PWR_CR1_DBP);
126 }
127
128 /**
129 * @brief Disable access to the backup domain
130 * (RTC registers, RTC backup data registers).
131 * @retval None
132 */
133 void HAL_PWR_DisableBkUpAccess(void)
134 {
135 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
136 }
137
138
139
140
141 /**
142 * @}
143 */
144
145
146
147 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
148 * @brief Low Power modes configuration functions
149 *
150 @verbatim
151
152 ===============================================================================
153 ##### Peripheral Control functions #####
154 ===============================================================================
155
156 [..]
157 *** PVD configuration ***
158 =========================
159 [..]
160 (+) The PVD is used to monitor the VDD power supply by comparing it to a
161 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
162
163 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
164 than the PVD threshold. This event is internally connected to the EXTI
165 line16 and can generate an interrupt if enabled. This is done through
166 __HAL_PVD_EXTI_ENABLE_IT() macro.
167 (+) The PVD is stopped in Standby mode.
168
169
170 *** WakeUp pin configuration ***
171 ================================
172 [..]
173 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
174 The polarity of these pins can be set to configure event detection on high
175 level (rising edge) or low level (falling edge).
176
177
178
179 *** Low Power modes configuration ***
180 =====================================
181 [..]
182 The devices feature 8 low-power modes:
183 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
184 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
185 (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
186 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
187 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
188 (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
189 (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
190 (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
191 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
192
193
194 *** Low-power run mode ***
195 ==========================
196 [..]
197 (+) Entry: (from main run mode)
198 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
199
200 (+) Exit:
201 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
202 then can the system clock frequency be increased above 2 MHz.
203
204
205 *** Sleep mode / Low-power sleep mode ***
206 =========================================
207 [..]
208 (+) Entry:
209 The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
210 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
211 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
212 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
213 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
214 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
215 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
216
217 (+) WFI Exit:
218 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
219 controller (NVIC) or any wake-up event.
220
221 (+) WFE Exit:
222 (++) Any wake-up event such as an EXTI line configured in event mode.
223
224 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
225 the MCU is in Low-power Run mode.
226
227 *** Stop 0, Stop 1 and Stop 2 modes ***
228 ===============================
229 [..]
230 (+) Entry:
231 The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
232 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
233 (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
234 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
235 (++) PWR_MAINREGULATOR_ON
236 (++) PWR_LOWPOWERREGULATOR_ON
237 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
238 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
239 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
240
241 (+) WFI Exit:
242 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
243 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
244 when programmed in wakeup mode.
245 (+) WFE Exit:
246 (++) Any EXTI Line (Internal or External) configured in Event mode.
247
248 [..]
249 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
250 depending on the LPR bit setting.
251 When exiting Stop 2 mode, the MCU is in Run mode.
252
253 *** Standby mode ***
254 ====================
255 [..]
256 The Standby mode offers two options:
257 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
258 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
259 and Standby circuitry.
260 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
261 SRAM and register contents are lost except for the RTC registers, RTC backup registers
262 and Standby circuitry.
263
264 (++) Entry:
265 (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
266 SRAM1 and register contents are lost except for registers in the Backup domain and
267 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
268 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
269 to set RRS bit.
270
271 (++) Exit:
272 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
273 external reset in NRST pin, IWDG reset.
274
275 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
276
277
278 *** Shutdown mode ***
279 ======================
280 [..]
281 In Shutdown mode,
282 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
283 SRAM and registers contents are lost except for backup domain registers.
284
285 (+) Entry:
286 The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
287
288 (+) Exit:
289 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
290 external reset in NRST pin.
291
292 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
293
294
295 *** Auto-wakeup (AWU) from low-power mode ***
296 =============================================
297 [..]
298 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
299 Wakeup event, a tamper event or a time-stamp event, without depending on
300 an external interrupt (Auto-wakeup mode).
301
302 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
303
304
305 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
306 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
307
308 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
309 is necessary to configure the RTC to detect the tamper or time stamp event using the
310 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
311
312 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
313 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
314
315 @endverbatim
316 * @{
317 */
318
319
320
321 /**
322 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
323 * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
324 * configuration information.
325 * @note Refer to the electrical characteristics of your device datasheet for
326 * more details about the voltage thresholds corresponding to each
327 * detection level.
328 * @retval None
329 */
330 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
331 {
332 /* Check the parameters */
333 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
334 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
335
336 /* Set PLS bits according to PVDLevel value */
337 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
338
339 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
340 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
341 __HAL_PWR_PVD_EXTI_DISABLE_IT();
342 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
343 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
344
345 /* Configure interrupt mode */
346 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
347 {
348 __HAL_PWR_PVD_EXTI_ENABLE_IT();
349 }
350
351 /* Configure event mode */
352 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
353 {
354 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
355 }
356
357 /* Configure the edge */
358 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
359 {
360 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
361 }
362
363 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
364 {
365 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
366 }
367
368 return HAL_OK;
369 }
370
371
372 /**
373 * @brief Enable the Power Voltage Detector (PVD).
374 * @retval None
375 */
376 void HAL_PWR_EnablePVD(void)
377 {
378 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
379 }
380
381 /**
382 * @brief Disable the Power Voltage Detector (PVD).
383 * @retval None
384 */
385 void HAL_PWR_DisablePVD(void)
386 {
387 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
388 }
389
390
391
392
393 /**
394 * @brief Enable the WakeUp PINx functionality.
395 * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
396 * This parameter can be one of the following legacy values which set the default polarity
397 * i.e. detection on high level (rising edge):
398 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
399 *
400 * or one of the following value where the user can explicitly specify the enabled pin and
401 * the chosen polarity:
402 * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
403 * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
404 * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
405 * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
406 * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
407 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
408 * @retval None
409 */
410 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
411 {
412 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
413
414 /* Specifies the Wake-Up pin polarity for the event detection
415 (rising or falling edge) */
416 MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
417
418 /* Enable wake-up pin */
419 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
420
421
422 }
423
424 /**
425 * @brief Disable the WakeUp PINx functionality.
426 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
427 * This parameter can be one of the following values:
428 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
429 * @retval None
430 */
431 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
432 {
433 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
434
435 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
436 }
437
438
439 /**
440 * @brief Enter Sleep or Low-power Sleep mode.
441 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
442 * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
443 * This parameter can be one of the following values:
444 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
445 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
446 * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
447 * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
448 * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
449 * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
450 * Additionally, the clock frequency must be reduced below 2 MHz.
451 * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
452 * be done before calling HAL_PWR_EnterSLEEPMode() API.
453 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
454 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
455 * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
456 * This parameter can be one of the following values:
457 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
458 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
459 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
460 * the interrupt wake up source.
461 * @retval None
462 */
463 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
464 {
465 /* Check the parameters */
466 assert_param(IS_PWR_REGULATOR(Regulator));
467 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
468
469 /* Set Regulator parameter */
470 if (Regulator == PWR_MAINREGULATOR_ON)
471 {
472 /* If in low-power run mode at this point, exit it */
473 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
474 {
475 HAL_PWREx_DisableLowPowerRunMode();
476 }
477 /* Regulator now in main mode. */
478 }
479 else
480 {
481 /* If in run mode, first move to low-power run mode.
482 The system clock frequency must be below 2 MHz at this point. */
483 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
484 {
485 HAL_PWREx_EnableLowPowerRunMode();
486 }
487 }
488
489 /* Clear SLEEPDEEP bit of Cortex System Control Register */
490 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
491
492 /* Select SLEEP mode entry -------------------------------------------------*/
493 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
494 {
495 /* Request Wait For Interrupt */
496 __WFI();
497 }
498 else
499 {
500 /* Request Wait For Event */
501 __SEV();
502 __WFE();
503 __WFE();
504 }
505
506 }
507
508
509 /**
510 * @brief Enter Stop mode
511 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
512 * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
513 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
514 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
515 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
516 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
517 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
518 * only to the peripheral requesting it.
519 * SRAM1, SRAM2 and register contents are preserved.
520 * The BOR is available.
521 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
522 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
523 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
524 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
525 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
526 * startup delay is incurred when waking up.
527 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
528 * is higher although the startup time is reduced.
529 * @param Regulator: Specifies the regulator state in Stop mode.
530 * This parameter can be one of the following values:
531 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
532 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
533 * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
534 * This parameter can be one of the following values:
535 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
536 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
537 * @retval None
538 */
539 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
540 {
541 /* Check the parameters */
542 assert_param(IS_PWR_REGULATOR(Regulator));
543
544 if(Regulator == PWR_LOWPOWERREGULATOR_ON)
545 {
546 HAL_PWREx_EnterSTOP1Mode(STOPEntry);
547 }
548 else
549 {
550 HAL_PWREx_EnterSTOP0Mode(STOPEntry);
551 }
552 }
553
554 /**
555 * @brief Enter Standby mode.
556 * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
557 * off. The voltage regulator is disabled, except when SRAM2 content is preserved
558 * in which case the regulator is in low-power mode.
559 * SRAM1 and register contents are lost except for registers in the Backup domain and
560 * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
561 * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
562 * to set RRS bit.
563 * The BOR is available.
564 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
565 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
566 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
567 * same.
568 * These states are effective in Standby mode only if APC bit is set through
569 * HAL_PWREx_EnablePullUpPullDownConfig() API.
570 * @retval None
571 */
572 void HAL_PWR_EnterSTANDBYMode(void)
573 {
574 /* Set Stand-by mode */
575 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
576
577 /* Set SLEEPDEEP bit of Cortex System Control Register */
578 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
579
580 /* This option is used to ensure that store operations are completed */
581 #if defined ( __CC_ARM)
582 __force_stores();
583 #endif
584 /* Request Wait For Interrupt */
585 __WFI();
586 }
587
588
589
590 /**
591 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
592 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
593 * re-enters SLEEP mode when an interruption handling is over.
594 * Setting this bit is useful when the processor is expected to run only on
595 * interruptions handling.
596 * @retval None
597 */
598 void HAL_PWR_EnableSleepOnExit(void)
599 {
600 /* Set SLEEPONEXIT bit of Cortex System Control Register */
601 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
602 }
603
604
605 /**
606 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
607 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
608 * re-enters SLEEP mode when an interruption handling is over.
609 * @retval None
610 */
611 void HAL_PWR_DisableSleepOnExit(void)
612 {
613 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
614 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
615 }
616
617
618
619 /**
620 * @brief Enable CORTEX M4 SEVONPEND bit.
621 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
622 * WFE to wake up when an interrupt moves from inactive to pended.
623 * @retval None
624 */
625 void HAL_PWR_EnableSEVOnPend(void)
626 {
627 /* Set SEVONPEND bit of Cortex System Control Register */
628 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
629 }
630
631
632 /**
633 * @brief Disable CORTEX M4 SEVONPEND bit.
634 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
635 * WFE to wake up when an interrupt moves from inactive to pended.
636 * @retval None
637 */
638 void HAL_PWR_DisableSEVOnPend(void)
639 {
640 /* Clear SEVONPEND bit of Cortex System Control Register */
641 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
642 }
643
644
645
646
647
648 /**
649 * @brief PWR PVD interrupt callback
650 * @retval None
651 */
652 __weak void HAL_PWR_PVDCallback(void)
653 {
654 /* NOTE : This function should not be modified; when the callback is needed,
655 the HAL_PWR_PVDCallback can be implemented in the user file
656 */
657 }
658
659 /**
660 * @}
661 */
662
663 /**
664 * @}
665 */
666
667 #endif /* HAL_PWR_MODULE_ENABLED */
668 /**
669 * @}
670 */
671
672 /**
673 * @}
674 */
675
676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/