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comparison l476rg/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c @ 0:32a3b1785697

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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @version V1.6.0
6 * @date 28-October-2016
7 * @brief Extended PWR HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Power Controller (PWR) peripheral:
10 * + Extended Initialization and de-initialization functions
11 * + Extended Peripheral Control functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
17 *
18 * Redistribution and use in source and binary forms, with or without modification,
19 * are permitted provided that the following conditions are met:
20 * 1. Redistributions of source code must retain the above copyright notice,
21 * this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 ******************************************************************************
41 */
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32l4xx_hal.h"
45
46 /** @addtogroup STM32L4xx_HAL_Driver
47 * @{
48 */
49
50 /** @defgroup PWREx PWREx
51 * @brief PWR Extended HAL module driver
52 * @{
53 */
54
55 #ifdef HAL_PWR_MODULE_ENABLED
56
57 /* Private typedef -----------------------------------------------------------*/
58 /* Private define ------------------------------------------------------------*/
59
60 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
61 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
62 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
63 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
64 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
65 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */
66 #endif
67
68 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
69 * @{
70 */
71
72 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
73 * @{
74 */
75 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
76 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
77 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
78 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
79 /**
80 * @}
81 */
82
83 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
84 * @{
85 */
86 #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */
87 /**
88 * @}
89 */
90
91
92
93 /**
94 * @}
95 */
96
97
98
99 /* Private macro -------------------------------------------------------------*/
100 /* Private variables ---------------------------------------------------------*/
101 /* Private function prototypes -----------------------------------------------*/
102 /* Exported functions --------------------------------------------------------*/
103
104 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
105 * @{
106 */
107
108 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
109 * @brief Extended Peripheral Control functions
110 *
111 @verbatim
112 ===============================================================================
113 ##### Extended Peripheral Initialization and de-initialization functions #####
114 ===============================================================================
115 [..]
116
117 @endverbatim
118 * @{
119 */
120
121
122 /**
123 * @brief Return Voltage Scaling Range.
124 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
125 */
126 uint32_t HAL_PWREx_GetVoltageRange(void)
127 {
128 return (PWR->CR1 & PWR_CR1_VOS);
129 }
130
131
132
133 /**
134 * @brief Configure the main internal regulator output voltage.
135 * @param VoltageScaling: specifies the regulator output voltage to achieve
136 * a tradeoff between performance and power consumption.
137 * This parameter can be one of the following values:
138 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
139 * typical output voltage at 1.2 V,
140 * system frequency up to 80 MHz.
141 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
142 * typical output voltage at 1.0 V,
143 * system frequency up to 26 MHz.
144 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
145 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
146 * When moving from Range 2 to Range 1, the system frequency can be increased to
147 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
148 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
149 * cleared before returning the status. If the flag is not cleared within
150 * 50 microseconds, HAL_TIMEOUT status is reported.
151 * @retval HAL Status
152 */
153 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
154 {
155 uint32_t wait_loop_index = 0;
156
157 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
158
159 /* If Set Range 1 */
160 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
161 {
162 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
163 {
164 /* Set Range 1 */
165 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
166
167 /* Wait until VOSF is cleared */
168 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
169 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)))
170 {
171 wait_loop_index--;
172 }
173 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
174 {
175 return HAL_TIMEOUT;
176 }
177 }
178 }
179 else
180 {
181 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
182 {
183 /* Set Range 2 */
184 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
185 /* No need to wait for VOSF to be cleared for this transition */
186 }
187 }
188
189 return HAL_OK;
190 }
191
192
193 /**
194 * @brief Enable battery charging.
195 * When VDD is present, charge the external battery on VBAT thru an internal resistor.
196 * @param ResistorSelection: specifies the resistor impedance.
197 * This parameter can be one of the following values:
198 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
199 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
200 * @retval None
201 */
202 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
203 {
204 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
205
206 /* Specify resistor selection */
207 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
208
209 /* Enable battery charging */
210 SET_BIT(PWR->CR4, PWR_CR4_VBE);
211 }
212
213
214 /**
215 * @brief Disable battery charging.
216 * @retval None
217 */
218 void HAL_PWREx_DisableBatteryCharging(void)
219 {
220 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
221 }
222
223
224 #if defined(PWR_CR2_USV)
225 /**
226 * @brief Enable VDDUSB supply.
227 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
228 * @retval None
229 */
230 void HAL_PWREx_EnableVddUSB(void)
231 {
232 SET_BIT(PWR->CR2, PWR_CR2_USV);
233 }
234
235
236 /**
237 * @brief Disable VDDUSB supply.
238 * @retval None
239 */
240 void HAL_PWREx_DisableVddUSB(void)
241 {
242 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
243 }
244 #endif /* PWR_CR2_USV */
245
246 #if defined(PWR_CR2_IOSV)
247 /**
248 * @brief Enable VDDIO2 supply.
249 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
250 * @retval None
251 */
252 void HAL_PWREx_EnableVddIO2(void)
253 {
254 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
255 }
256
257
258 /**
259 * @brief Disable VDDIO2 supply.
260 * @retval None
261 */
262 void HAL_PWREx_DisableVddIO2(void)
263 {
264 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
265 }
266 #endif /* PWR_CR2_IOSV */
267
268
269 /**
270 * @brief Enable Internal Wake-up Line.
271 * @retval None
272 */
273 void HAL_PWREx_EnableInternalWakeUpLine(void)
274 {
275 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
276 }
277
278
279 /**
280 * @brief Disable Internal Wake-up Line.
281 * @retval None
282 */
283 void HAL_PWREx_DisableInternalWakeUpLine(void)
284 {
285 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
286 }
287
288
289
290 /**
291 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
292 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
293 * pull-up state in Standby and Shutdown modes.
294 * @note This state is effective in Standby and Shutdown modes only if APC bit
295 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
296 * @note The configuration is lost when exiting the Shutdown mode due to the
297 * power-on reset, maintained when exiting the Standby mode.
298 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
299 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
300 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
301 * parameter at the same time are set.
302 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
303 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
304 * @param GPIONumber: Specify the I/O pins numbers.
305 * This parameter can be one of the following values:
306 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
307 * I/O pins are available) or the logical OR of several of them to set
308 * several bits for a given port in a single API call.
309 * @retval HAL Status
310 */
311 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
312 {
313 assert_param(IS_PWR_GPIO(GPIO));
314 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
315
316 switch (GPIO)
317 {
318 case PWR_GPIO_A:
319 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
320 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
321 break;
322 case PWR_GPIO_B:
323 SET_BIT(PWR->PUCRB, GPIONumber);
324 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
325 break;
326 case PWR_GPIO_C:
327 SET_BIT(PWR->PUCRC, GPIONumber);
328 CLEAR_BIT(PWR->PDCRC, GPIONumber);
329 break;
330 #if defined(GPIOD)
331 case PWR_GPIO_D:
332 SET_BIT(PWR->PUCRD, GPIONumber);
333 CLEAR_BIT(PWR->PDCRD, GPIONumber);
334 break;
335 #endif
336 #if defined(GPIOE)
337 case PWR_GPIO_E:
338 SET_BIT(PWR->PUCRE, GPIONumber);
339 CLEAR_BIT(PWR->PDCRE, GPIONumber);
340 break;
341 #endif
342 #if defined(GPIOF)
343 case PWR_GPIO_F:
344 SET_BIT(PWR->PUCRF, GPIONumber);
345 CLEAR_BIT(PWR->PDCRF, GPIONumber);
346 break;
347 #endif
348 #if defined(GPIOG)
349 case PWR_GPIO_G:
350 SET_BIT(PWR->PUCRG, GPIONumber);
351 CLEAR_BIT(PWR->PDCRG, GPIONumber);
352 break;
353 #endif
354 case PWR_GPIO_H:
355 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
356 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
357 break;
358 default:
359 return HAL_ERROR;
360 }
361
362 return HAL_OK;
363 }
364
365
366 /**
367 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
368 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
369 * in pull-up state in Standby and Shutdown modes.
370 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
371 * parameter at the same time are reset.
372 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
373 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
374 * @param GPIONumber: Specify the I/O pins numbers.
375 * This parameter can be one of the following values:
376 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
377 * I/O pins are available) or the logical OR of several of them to reset
378 * several bits for a given port in a single API call.
379 * @retval HAL Status
380 */
381 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
382 {
383 assert_param(IS_PWR_GPIO(GPIO));
384 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
385
386 switch (GPIO)
387 {
388 case PWR_GPIO_A:
389 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
390 break;
391 case PWR_GPIO_B:
392 CLEAR_BIT(PWR->PUCRB, GPIONumber);
393 break;
394 case PWR_GPIO_C:
395 CLEAR_BIT(PWR->PUCRC, GPIONumber);
396 break;
397 #if defined(GPIOD)
398 case PWR_GPIO_D:
399 CLEAR_BIT(PWR->PUCRD, GPIONumber);
400 break;
401 #endif
402 #if defined(GPIOE)
403 case PWR_GPIO_E:
404 CLEAR_BIT(PWR->PUCRE, GPIONumber);
405 break;
406 #endif
407 #if defined(GPIOF)
408 case PWR_GPIO_F:
409 CLEAR_BIT(PWR->PUCRF, GPIONumber);
410 break;
411 #endif
412 #if defined(GPIOG)
413 case PWR_GPIO_G:
414 CLEAR_BIT(PWR->PUCRG, GPIONumber);
415 break;
416 #endif
417 case PWR_GPIO_H:
418 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
419 break;
420 default:
421 return HAL_ERROR;
422 }
423
424 return HAL_OK;
425 }
426
427
428
429 /**
430 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
431 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
432 * pull-down state in Standby and Shutdown modes.
433 * @note This state is effective in Standby and Shutdown modes only if APC bit
434 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
435 * @note The configuration is lost when exiting the Shutdown mode due to the
436 * power-on reset, maintained when exiting the Standby mode.
437 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
438 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
439 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
440 * parameter at the same time are set.
441 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
442 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
443 * @param GPIONumber: Specify the I/O pins numbers.
444 * This parameter can be one of the following values:
445 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
446 * I/O pins are available) or the logical OR of several of them to set
447 * several bits for a given port in a single API call.
448 * @retval HAL Status
449 */
450 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
451 {
452 assert_param(IS_PWR_GPIO(GPIO));
453 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
454
455 switch (GPIO)
456 {
457 case PWR_GPIO_A:
458 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
459 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
460 break;
461 case PWR_GPIO_B:
462 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
463 CLEAR_BIT(PWR->PUCRB, GPIONumber);
464 break;
465 case PWR_GPIO_C:
466 SET_BIT(PWR->PDCRC, GPIONumber);
467 CLEAR_BIT(PWR->PUCRC, GPIONumber);
468 break;
469 #if defined(GPIOD)
470 case PWR_GPIO_D:
471 SET_BIT(PWR->PDCRD, GPIONumber);
472 CLEAR_BIT(PWR->PUCRD, GPIONumber);
473 break;
474 #endif
475 #if defined(GPIOE)
476 case PWR_GPIO_E:
477 SET_BIT(PWR->PDCRE, GPIONumber);
478 CLEAR_BIT(PWR->PUCRE, GPIONumber);
479 break;
480 #endif
481 #if defined(GPIOF)
482 case PWR_GPIO_F:
483 SET_BIT(PWR->PDCRF, GPIONumber);
484 CLEAR_BIT(PWR->PUCRF, GPIONumber);
485 break;
486 #endif
487 #if defined(GPIOG)
488 case PWR_GPIO_G:
489 SET_BIT(PWR->PDCRG, GPIONumber);
490 CLEAR_BIT(PWR->PUCRG, GPIONumber);
491 break;
492 #endif
493 case PWR_GPIO_H:
494 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
495 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
496 break;
497 default:
498 return HAL_ERROR;
499 }
500
501 return HAL_OK;
502 }
503
504
505 /**
506 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
507 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
508 * in pull-down state in Standby and Shutdown modes.
509 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
510 * parameter at the same time are reset.
511 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
512 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
513 * @param GPIONumber: Specify the I/O pins numbers.
514 * This parameter can be one of the following values:
515 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
516 * I/O pins are available) or the logical OR of several of them to reset
517 * several bits for a given port in a single API call.
518 * @retval HAL Status
519 */
520 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
521 {
522 assert_param(IS_PWR_GPIO(GPIO));
523 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
524
525 switch (GPIO)
526 {
527 case PWR_GPIO_A:
528 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
529 break;
530 case PWR_GPIO_B:
531 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
532 break;
533 case PWR_GPIO_C:
534 CLEAR_BIT(PWR->PDCRC, GPIONumber);
535 break;
536 #if defined(GPIOD)
537 case PWR_GPIO_D:
538 CLEAR_BIT(PWR->PDCRD, GPIONumber);
539 break;
540 #endif
541 #if defined(GPIOE)
542 case PWR_GPIO_E:
543 CLEAR_BIT(PWR->PDCRE, GPIONumber);
544 break;
545 #endif
546 #if defined(GPIOF)
547 case PWR_GPIO_F:
548 CLEAR_BIT(PWR->PDCRF, GPIONumber);
549 break;
550 #endif
551 #if defined(GPIOG)
552 case PWR_GPIO_G:
553 CLEAR_BIT(PWR->PDCRG, GPIONumber);
554 break;
555 #endif
556 case PWR_GPIO_H:
557 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
558 break;
559 default:
560 return HAL_ERROR;
561 }
562
563 return HAL_OK;
564 }
565
566
567
568 /**
569 * @brief Enable pull-up and pull-down configuration.
570 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
571 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
572 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
573 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
574 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
575 * is no conflict when setting PUy or PDy bit.
576 * @retval None
577 */
578 void HAL_PWREx_EnablePullUpPullDownConfig(void)
579 {
580 SET_BIT(PWR->CR3, PWR_CR3_APC);
581 }
582
583
584 /**
585 * @brief Disable pull-up and pull-down configuration.
586 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
587 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
588 * @retval None
589 */
590 void HAL_PWREx_DisablePullUpPullDownConfig(void)
591 {
592 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
593 }
594
595
596
597 /**
598 * @brief Enable SRAM2 content retention in Standby mode.
599 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
600 * Standby mode and its content is kept.
601 * @retval None
602 */
603 void HAL_PWREx_EnableSRAM2ContentRetention(void)
604 {
605 SET_BIT(PWR->CR3, PWR_CR3_RRS);
606 }
607
608
609 /**
610 * @brief Disable SRAM2 content retention in Standby mode.
611 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
612 * and its content is lost.
613 * @retval None
614 */
615 void HAL_PWREx_DisableSRAM2ContentRetention(void)
616 {
617 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
618 }
619
620
621
622
623 #if defined(PWR_CR2_PVME1)
624 /**
625 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
626 * @retval None
627 */
628 void HAL_PWREx_EnablePVM1(void)
629 {
630 SET_BIT(PWR->CR2, PWR_PVM_1);
631 }
632
633 /**
634 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
635 * @retval None
636 */
637 void HAL_PWREx_DisablePVM1(void)
638 {
639 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
640 }
641 #endif /* PWR_CR2_PVME1 */
642
643
644 #if defined(PWR_CR2_PVME2)
645 /**
646 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
647 * @retval None
648 */
649 void HAL_PWREx_EnablePVM2(void)
650 {
651 SET_BIT(PWR->CR2, PWR_PVM_2);
652 }
653
654 /**
655 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
656 * @retval None
657 */
658 void HAL_PWREx_DisablePVM2(void)
659 {
660 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
661 }
662 #endif /* PWR_CR2_PVME2 */
663
664
665 /**
666 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
667 * @retval None
668 */
669 void HAL_PWREx_EnablePVM3(void)
670 {
671 SET_BIT(PWR->CR2, PWR_PVM_3);
672 }
673
674 /**
675 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
676 * @retval None
677 */
678 void HAL_PWREx_DisablePVM3(void)
679 {
680 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
681 }
682
683
684 /**
685 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
686 * @retval None
687 */
688 void HAL_PWREx_EnablePVM4(void)
689 {
690 SET_BIT(PWR->CR2, PWR_PVM_4);
691 }
692
693 /**
694 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
695 * @retval None
696 */
697 void HAL_PWREx_DisablePVM4(void)
698 {
699 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
700 }
701
702
703
704
705 /**
706 * @brief Configure the Peripheral Voltage Monitoring (PVM).
707 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
708 * PVM configuration information.
709 * @note The API configures a single PVM according to the information contained
710 * in the input structure. To configure several PVMs, the API must be singly
711 * called for each PVM used.
712 * @note Refer to the electrical characteristics of your device datasheet for
713 * more details about the voltage thresholds corresponding to each
714 * detection level and to each monitored supply.
715 * @retval HAL status
716 */
717 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
718 {
719 /* Check the parameters */
720 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
721 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
722
723
724 /* Configure EXTI 35 to 38 interrupts if so required:
725 scan thru PVMType to detect which PVMx is set and
726 configure the corresponding EXTI line accordingly. */
727 switch (sConfigPVM->PVMType)
728 {
729 #if defined(PWR_CR2_PVME1)
730 case PWR_PVM_1:
731 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
732 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
733 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
734 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
735 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
736
737 /* Configure interrupt mode */
738 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
739 {
740 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
741 }
742
743 /* Configure event mode */
744 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
745 {
746 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
747 }
748
749 /* Configure the edge */
750 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
751 {
752 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
753 }
754
755 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
756 {
757 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
758 }
759 break;
760 #endif /* PWR_CR2_PVME1 */
761
762 #if defined(PWR_CR2_PVME2)
763 case PWR_PVM_2:
764 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
765 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
766 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
767 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
768 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
769
770 /* Configure interrupt mode */
771 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
772 {
773 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
774 }
775
776 /* Configure event mode */
777 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
778 {
779 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
780 }
781
782 /* Configure the edge */
783 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
784 {
785 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
786 }
787
788 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
789 {
790 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
791 }
792 break;
793 #endif /* PWR_CR2_PVME2 */
794
795 case PWR_PVM_3:
796 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
797 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
798 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
799 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
800 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
801
802 /* Configure interrupt mode */
803 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
804 {
805 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
806 }
807
808 /* Configure event mode */
809 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
810 {
811 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
812 }
813
814 /* Configure the edge */
815 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
816 {
817 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
818 }
819
820 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
821 {
822 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
823 }
824 break;
825
826 case PWR_PVM_4:
827 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
828 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
829 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
830 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
831 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
832
833 /* Configure interrupt mode */
834 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
835 {
836 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
837 }
838
839 /* Configure event mode */
840 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
841 {
842 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
843 }
844
845 /* Configure the edge */
846 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
847 {
848 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
849 }
850
851 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
852 {
853 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
854 }
855 break;
856
857 default:
858 return HAL_ERROR;
859
860 }
861
862
863 return HAL_OK;
864 }
865
866
867
868 /**
869 * @brief Enter Low-power Run mode
870 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
871 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
872 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
873 * Additionally, the clock frequency must be reduced below 2 MHz.
874 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
875 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
876 * @retval None
877 */
878 void HAL_PWREx_EnableLowPowerRunMode(void)
879 {
880 /* Set Regulator parameter */
881 SET_BIT(PWR->CR1, PWR_CR1_LPR);
882 }
883
884
885 /**
886 * @brief Exit Low-power Run mode.
887 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
888 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
889 * returns HAL_TIMEOUT status). The system clock frequency can then be
890 * increased above 2 MHz.
891 * @retval HAL Status
892 */
893 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
894 {
895 uint32_t wait_loop_index = 0;
896
897 /* Clear LPR bit */
898 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
899
900 /* Wait until REGLPF is reset */
901 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
902 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)))
903 {
904 wait_loop_index--;
905 }
906 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
907 {
908 return HAL_TIMEOUT;
909 }
910
911 return HAL_OK;
912 }
913
914
915 /**
916 * @brief Enter Stop 0 mode.
917 * @note In Stop 0 mode, main and low voltage regulators are ON.
918 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
919 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
920 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
921 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
922 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
923 * only to the peripheral requesting it.
924 * SRAM1, SRAM2 and register contents are preserved.
925 * The BOR is available.
926 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
927 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
928 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
929 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
930 * is higher although the startup time is reduced.
931 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
932 * This parameter can be one of the following values:
933 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
934 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
935 * @retval None
936 */
937 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
938 {
939 /* Check the parameters */
940 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
941
942 /* Stop 0 mode with Main Regulator */
943 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
944
945 /* Set SLEEPDEEP bit of Cortex System Control Register */
946 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
947
948 /* Select Stop mode entry --------------------------------------------------*/
949 if(STOPEntry == PWR_STOPENTRY_WFI)
950 {
951 /* Request Wait For Interrupt */
952 __WFI();
953 }
954 else
955 {
956 /* Request Wait For Event */
957 __SEV();
958 __WFE();
959 __WFE();
960 }
961
962 /* Reset SLEEPDEEP bit of Cortex System Control Register */
963 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
964 }
965
966
967 /**
968 * @brief Enter Stop 1 mode.
969 * @note In Stop 1 mode, only low power voltage regulator is ON.
970 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
971 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
972 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
973 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
974 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
975 * only to the peripheral requesting it.
976 * SRAM1, SRAM2 and register contents are preserved.
977 * The BOR is available.
978 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
979 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
980 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
981 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
982 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
983 * This parameter can be one of the following values:
984 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
985 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
986 * @retval None
987 */
988 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
989 {
990 /* Check the parameters */
991 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
992
993 /* Stop 1 mode with Low-Power Regulator */
994 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
995
996 /* Set SLEEPDEEP bit of Cortex System Control Register */
997 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
998
999 /* Select Stop mode entry --------------------------------------------------*/
1000 if(STOPEntry == PWR_STOPENTRY_WFI)
1001 {
1002 /* Request Wait For Interrupt */
1003 __WFI();
1004 }
1005 else
1006 {
1007 /* Request Wait For Event */
1008 __SEV();
1009 __WFE();
1010 __WFE();
1011 }
1012
1013 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1014 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1015 }
1016
1017
1018 /**
1019 * @brief Enter Stop 2 mode.
1020 * @note In Stop 2 mode, only low power voltage regulator is ON.
1021 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
1022 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
1023 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
1024 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
1025 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
1026 * to the peripheral requesting it.
1027 * SRAM1, SRAM2 and register contents are preserved.
1028 * The BOR is available.
1029 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
1030 * Otherwise, Stop 1 mode is entered.
1031 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
1032 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
1033 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
1034 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
1035 * This parameter can be one of the following values:
1036 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
1037 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
1038 * @retval None
1039 */
1040 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
1041 {
1042 /* Check the parameter */
1043 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
1044
1045 /* Set Stop mode 2 */
1046 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
1047
1048 /* Set SLEEPDEEP bit of Cortex System Control Register */
1049 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1050
1051 /* Select Stop mode entry --------------------------------------------------*/
1052 if(STOPEntry == PWR_STOPENTRY_WFI)
1053 {
1054 /* Request Wait For Interrupt */
1055 __WFI();
1056 }
1057 else
1058 {
1059 /* Request Wait For Event */
1060 __SEV();
1061 __WFE();
1062 __WFE();
1063 }
1064
1065 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1066 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1067 }
1068
1069
1070
1071
1072
1073 /**
1074 * @brief Enter Shutdown mode.
1075 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
1076 * off. The voltage regulator is disabled and Vcore domain is powered off.
1077 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
1078 * The BOR is not available.
1079 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
1080 * @retval None
1081 */
1082 void HAL_PWREx_EnterSHUTDOWNMode(void)
1083 {
1084
1085 /* Set Shutdown mode */
1086 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
1087
1088 /* Set SLEEPDEEP bit of Cortex System Control Register */
1089 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1090
1091 /* This option is used to ensure that store operations are completed */
1092 #if defined ( __CC_ARM)
1093 __force_stores();
1094 #endif
1095 /* Request Wait For Interrupt */
1096 __WFI();
1097 }
1098
1099
1100
1101
1102 /**
1103 * @brief This function handles the PWR PVD/PVMx interrupt request.
1104 * @note This API should be called under the PVD_PVM_IRQHandler().
1105 * @retval None
1106 */
1107 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1108 {
1109 /* Check PWR exti flag */
1110 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
1111 {
1112 /* PWR PVD interrupt user callback */
1113 HAL_PWR_PVDCallback();
1114
1115 /* Clear PVD exti pending bit */
1116 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
1117 }
1118 /* Next, successively check PVMx exti flags */
1119 #if defined(PWR_CR2_PVME1)
1120 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET)
1121 {
1122 /* PWR PVM1 interrupt user callback */
1123 HAL_PWREx_PVM1Callback();
1124
1125 /* Clear PVM1 exti pending bit */
1126 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
1127 }
1128 #endif /* PWR_CR2_PVME1 */
1129 #if defined(PWR_CR2_PVME2)
1130 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET)
1131 {
1132 /* PWR PVM2 interrupt user callback */
1133 HAL_PWREx_PVM2Callback();
1134
1135 /* Clear PVM2 exti pending bit */
1136 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
1137 }
1138 #endif /* PWR_CR2_PVME2 */
1139 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET)
1140 {
1141 /* PWR PVM3 interrupt user callback */
1142 HAL_PWREx_PVM3Callback();
1143
1144 /* Clear PVM3 exti pending bit */
1145 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
1146 }
1147 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET)
1148 {
1149 /* PWR PVM4 interrupt user callback */
1150 HAL_PWREx_PVM4Callback();
1151
1152 /* Clear PVM4 exti pending bit */
1153 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
1154 }
1155 }
1156
1157
1158 #if defined(PWR_CR2_PVME1)
1159 /**
1160 * @brief PWR PVM1 interrupt callback
1161 * @retval None
1162 */
1163 __weak void HAL_PWREx_PVM1Callback(void)
1164 {
1165 /* NOTE : This function should not be modified; when the callback is needed,
1166 HAL_PWREx_PVM1Callback() API can be implemented in the user file
1167 */
1168 }
1169 #endif /* PWR_CR2_PVME1 */
1170
1171 #if defined(PWR_CR2_PVME2)
1172 /**
1173 * @brief PWR PVM2 interrupt callback
1174 * @retval None
1175 */
1176 __weak void HAL_PWREx_PVM2Callback(void)
1177 {
1178 /* NOTE : This function should not be modified; when the callback is needed,
1179 HAL_PWREx_PVM2Callback() API can be implemented in the user file
1180 */
1181 }
1182 #endif /* PWR_CR2_PVME2 */
1183
1184 /**
1185 * @brief PWR PVM3 interrupt callback
1186 * @retval None
1187 */
1188 __weak void HAL_PWREx_PVM3Callback(void)
1189 {
1190 /* NOTE : This function should not be modified; when the callback is needed,
1191 HAL_PWREx_PVM3Callback() API can be implemented in the user file
1192 */
1193 }
1194
1195 /**
1196 * @brief PWR PVM4 interrupt callback
1197 * @retval None
1198 */
1199 __weak void HAL_PWREx_PVM4Callback(void)
1200 {
1201 /* NOTE : This function should not be modified; when the callback is needed,
1202 HAL_PWREx_PVM4Callback() API can be implemented in the user file
1203 */
1204 }
1205
1206
1207 /**
1208 * @}
1209 */
1210
1211 /**
1212 * @}
1213 */
1214
1215 #endif /* HAL_PWR_MODULE_ENABLED */
1216 /**
1217 * @}
1218 */
1219
1220 /**
1221 * @}
1222 */
1223
1224 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/