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a rough draft of Hardware Abstraction Layer for C++ STM32L476RG drivers
author cin
date Thu, 12 Jan 2017 02:45:43 +0300
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1 /**
2 ******************************************************************************
3 * @file system_stm32l4xx.c
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 28-October-2016
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
8 *
9 * This file provides two functions and one global variable to be called from
10 * user application:
11 * - SystemInit(): This function is called at startup just after reset and
12 * before branch to main program. This call is made inside
13 * the "startup_stm32l4xx.s" file.
14 *
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 * by the user application to setup the SysTick
17 * timer or configure other parameters.
18 *
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 * be called whenever the core clock is changed
21 * during program execution.
22 *
23 * After each device reset the MSI (4 MHz) is used as system clock source.
24 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
25 * configure the system clock before to branch to main program.
26 *
27 * This file configures the system clock as follows:
28 *=============================================================================
29 *-----------------------------------------------------------------------------
30 * System Clock source | MSI
31 *-----------------------------------------------------------------------------
32 * SYSCLK(Hz) | 4000000
33 *-----------------------------------------------------------------------------
34 * HCLK(Hz) | 4000000
35 *-----------------------------------------------------------------------------
36 * AHB Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB1 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * APB2 Prescaler | 1
41 *-----------------------------------------------------------------------------
42 * PLL_M | 1
43 *-----------------------------------------------------------------------------
44 * PLL_N | 8
45 *-----------------------------------------------------------------------------
46 * PLL_P | 7
47 *-----------------------------------------------------------------------------
48 * PLL_Q | 2
49 *-----------------------------------------------------------------------------
50 * PLL_R | 2
51 *-----------------------------------------------------------------------------
52 * PLLSAI1_P | NA
53 *-----------------------------------------------------------------------------
54 * PLLSAI1_Q | NA
55 *-----------------------------------------------------------------------------
56 * PLLSAI1_R | NA
57 *-----------------------------------------------------------------------------
58 * PLLSAI2_P | NA
59 *-----------------------------------------------------------------------------
60 * PLLSAI2_Q | NA
61 *-----------------------------------------------------------------------------
62 * PLLSAI2_R | NA
63 *-----------------------------------------------------------------------------
64 * Require 48MHz for USB OTG FS, | Disabled
65 * SDIO and RNG clock |
66 *-----------------------------------------------------------------------------
67 *=============================================================================
68 ******************************************************************************
69 * @attention
70 *
71 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
72 *
73 * Redistribution and use in source and binary forms, with or without modification,
74 * are permitted provided that the following conditions are met:
75 * 1. Redistributions of source code must retain the above copyright notice,
76 * this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright notice,
78 * this list of conditions and the following disclaimer in the documentation
79 * and/or other materials provided with the distribution.
80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
81 * may be used to endorse or promote products derived from this software
82 * without specific prior written permission.
83 *
84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
94 *
95 ******************************************************************************
96 */
97
98 /** @addtogroup CMSIS
99 * @{
100 */
101
102 /** @addtogroup stm32l4xx_system
103 * @{
104 */
105
106 /** @addtogroup STM32L4xx_System_Private_Includes
107 * @{
108 */
109
110 #include "stm32l4xx.h"
111
112 #if !defined (HSE_VALUE)
113 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
114 #endif /* HSE_VALUE */
115
116 #if !defined (MSI_VALUE)
117 #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
118 #endif /* MSI_VALUE */
119
120 #if !defined (HSI_VALUE)
121 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
122 #endif /* HSI_VALUE */
123
124 /**
125 * @}
126 */
127
128 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
129 * @{
130 */
131
132 /**
133 * @}
134 */
135
136 /** @addtogroup STM32L4xx_System_Private_Defines
137 * @{
138 */
139
140 /************************* Miscellaneous Configuration ************************/
141 /*!< Uncomment the following line if you need to relocate your vector Table in
142 Internal SRAM. */
143 /* #define VECT_TAB_SRAM */
144 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
145 This value must be a multiple of 0x200. */
146 /******************************************************************************/
147 /**
148 * @}
149 */
150
151 /** @addtogroup STM32L4xx_System_Private_Macros
152 * @{
153 */
154
155 /**
156 * @}
157 */
158
159 /** @addtogroup STM32L4xx_System_Private_Variables
160 * @{
161 */
162 /* The SystemCoreClock variable is updated in three ways:
163 1) by calling CMSIS function SystemCoreClockUpdate()
164 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
165 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
166 Note: If you use this function to configure the system clock; then there
167 is no need to call the 2 first functions listed above, since SystemCoreClock
168 variable is updated automatically.
169 */
170 uint32_t SystemCoreClock = 4000000;
171
172 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
173 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
174 const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
175 4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
176 /**
177 * @}
178 */
179
180 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
181 * @{
182 */
183
184 /**
185 * @}
186 */
187
188 /** @addtogroup STM32L4xx_System_Private_Functions
189 * @{
190 */
191
192 /**
193 * @brief Setup the microcontroller system.
194 * @param None
195 * @retval None
196 */
197
198 void SystemInit(void)
199 {
200 /* FPU settings ------------------------------------------------------------*/
201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
202 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
203 #endif
204 /* Reset the RCC clock configuration to the default reset state ------------*/
205 /* Set MSION bit */
206 RCC->CR |= RCC_CR_MSION;
207
208 /* Reset CFGR register */
209 RCC->CFGR = 0x00000000;
210
211 /* Reset HSEON, CSSON , HSION, and PLLON bits */
212 RCC->CR &= (uint32_t)0xEAF6FFFF;
213
214 /* Reset PLLCFGR register */
215 RCC->PLLCFGR = 0x00001000;
216
217 /* Reset HSEBYP bit */
218 RCC->CR &= (uint32_t)0xFFFBFFFF;
219
220 /* Disable all interrupts */
221 RCC->CIER = 0x00000000;
222
223 /* Configure the Vector Table location add offset address ------------------*/
224 #ifdef VECT_TAB_SRAM
225 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
226 #else
227 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
228 #endif
229 }
230
231 /**
232 * @brief Update SystemCoreClock variable according to Clock Register Values.
233 * The SystemCoreClock variable contains the core clock (HCLK), it can
234 * be used by the user application to setup the SysTick timer or configure
235 * other parameters.
236 *
237 * @note Each time the core clock (HCLK) changes, this function must be called
238 * to update SystemCoreClock variable value. Otherwise, any configuration
239 * based on this variable will be incorrect.
240 *
241 * @note - The system frequency computed by this function is not the real
242 * frequency in the chip. It is calculated based on the predefined
243 * constant and the selected clock source:
244 *
245 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
246 *
247 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
248 *
249 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
250 *
251 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
252 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
253 *
254 * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
255 * 4 MHz) but the real value may vary depending on the variations
256 * in voltage and temperature.
257 *
258 * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
259 * 16 MHz) but the real value may vary depending on the variations
260 * in voltage and temperature.
261 *
262 * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
263 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
264 * frequency of the crystal used. Otherwise, this function may
265 * have wrong result.
266 *
267 * - The result of this function could be not correct when using fractional
268 * value for HSE crystal.
269 *
270 * @param None
271 * @retval None
272 */
273 void SystemCoreClockUpdate(void)
274 {
275 uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
276
277 /* Get MSI Range frequency--------------------------------------------------*/
278 if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
279 { /* MSISRANGE from RCC_CSR applies */
280 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
281 }
282 else
283 { /* MSIRANGE from RCC_CR applies */
284 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
285 }
286 /*MSI frequency range in HZ*/
287 msirange = MSIRangeTable[msirange];
288
289 /* Get SYSCLK source -------------------------------------------------------*/
290 switch (RCC->CFGR & RCC_CFGR_SWS)
291 {
292 case 0x00: /* MSI used as system clock source */
293 SystemCoreClock = msirange;
294 break;
295
296 case 0x04: /* HSI used as system clock source */
297 SystemCoreClock = HSI_VALUE;
298 break;
299
300 case 0x08: /* HSE used as system clock source */
301 SystemCoreClock = HSE_VALUE;
302 break;
303
304 case 0x0C: /* PLL used as system clock source */
305 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
306 SYSCLK = PLL_VCO / PLLR
307 */
308 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
309 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
310
311 switch (pllsource)
312 {
313 case 0x02: /* HSI used as PLL clock source */
314 pllvco = (HSI_VALUE / pllm);
315 break;
316
317 case 0x03: /* HSE used as PLL clock source */
318 pllvco = (HSE_VALUE / pllm);
319 break;
320
321 default: /* MSI used as PLL clock source */
322 pllvco = (msirange / pllm);
323 break;
324 }
325 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
326 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
327 SystemCoreClock = pllvco/pllr;
328 break;
329
330 default:
331 SystemCoreClock = msirange;
332 break;
333 }
334 /* Compute HCLK clock frequency --------------------------------------------*/
335 /* Get HCLK prescaler */
336 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
337 /* HCLK clock frequency */
338 SystemCoreClock >>= tmp;
339 }
340
341
342 /**
343 * @}
344 */
345
346 /**
347 * @}
348 */
349
350 /**
351 * @}
352 */
353
354 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/