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1 /**
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2 ******************************************************************************
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3 * @file stm32f1xx_hal_dma.h
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4 * @author MCD Application Team
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5 * @version V1.0.4
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6 * @date 29-April-2016
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7 * @brief Header file of DMA HAL module.
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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12 *
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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23 *
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 *
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35 ******************************************************************************
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36 */
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37
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F1xx_HAL_DMA_H
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40 #define __STM32F1xx_HAL_DMA_H
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41
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42 #ifdef __cplusplus
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43 extern "C" {
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44 #endif
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f1xx_hal_def.h"
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48
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49 /** @addtogroup STM32F1xx_HAL_Driver
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50 * @{
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51 */
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52
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53 /** @addtogroup DMA
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54 * @{
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55 */
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56
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57 /* Exported types ------------------------------------------------------------*/
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58
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59 /** @defgroup DMA_Exported_Types DMA Exported Types
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60 * @{
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61 */
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62
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63 /**
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64 * @brief DMA Configuration Structure definition
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65 */
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66 typedef struct
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67 {
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68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
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69 from memory to memory or from peripheral to memory.
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70 This parameter can be a value of @ref DMA_Data_transfer_direction */
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71
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72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
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74
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75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
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76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
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77
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78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
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79 This parameter can be a value of @ref DMA_Peripheral_data_size */
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80
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81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
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82 This parameter can be a value of @ref DMA_Memory_data_size */
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83
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84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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85 This parameter can be a value of @ref DMA_mode
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86 @note The circular buffer mode cannot be used if the memory-to-memory
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87 data transfer is configured on the selected Channel */
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88
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89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
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90 This parameter can be a value of @ref DMA_Priority_level */
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91 } DMA_InitTypeDef;
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92
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93 /**
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94 * @brief DMA Configuration enumeration values definition
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95 */
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96 typedef enum
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97 {
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98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
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99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
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100
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101 } DMA_ControlTypeDef;
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102
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103 /**
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104 * @brief HAL DMA State structures definition
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105 */
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106 typedef enum
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107 {
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108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
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109 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
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110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
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111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
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112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
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113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
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114 }HAL_DMA_StateTypeDef;
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115
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116 /**
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117 * @brief HAL DMA Error Code structure definition
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118 */
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119 typedef enum
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120 {
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121 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
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122 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
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123 }HAL_DMA_LevelCompleteTypeDef;
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124
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125 /**
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126 * @brief DMA handle Structure definition
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127 */
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128 typedef struct __DMA_HandleTypeDef
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129 {
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130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
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131
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132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
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133
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134 HAL_LockTypeDef Lock; /*!< DMA locking object */
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135
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136 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
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137
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138 void *Parent; /*!< Parent object state */
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139
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140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
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141
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142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
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143
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144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
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145
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146 __IO uint32_t ErrorCode; /*!< DMA Error code */
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147 } DMA_HandleTypeDef;
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148 /**
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149 * @}
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150 */
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151
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152 /* Exported constants --------------------------------------------------------*/
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153
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154 /** @defgroup DMA_Exported_Constants DMA Exported Constants
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155 * @{
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156 */
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157
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158 /** @defgroup DMA_Error_Code DMA Error Code
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159 * @{
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160 */
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161 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
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162 #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */
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163 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
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164
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165 /**
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166 * @}
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167 */
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168
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169 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
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170 * @{
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171 */
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172 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
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173 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
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174 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
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175
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176 /**
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177 * @}
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178 */
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179
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180 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
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181 * @{
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182 */
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183 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
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184 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
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185 /**
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186 * @}
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187 */
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188
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189 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
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190 * @{
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191 */
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192 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
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193 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
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194 /**
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195 * @}
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196 */
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197
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198 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
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199 * @{
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200 */
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201 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
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202 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
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203 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
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204 /**
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205 * @}
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206 */
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207
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208 /** @defgroup DMA_Memory_data_size DMA Memory data size
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209 * @{
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210 */
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211 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
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212 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
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213 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
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214 /**
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215 * @}
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216 */
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217
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218 /** @defgroup DMA_mode DMA mode
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219 * @{
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220 */
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221 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
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222 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
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223 /**
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224 * @}
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225 */
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226
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227 /** @defgroup DMA_Priority_level DMA Priority level
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228 * @{
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229 */
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230 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
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231 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
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232 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
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233 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
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234 /**
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235 * @}
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236 */
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237
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238
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239 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
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240 * @{
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241 */
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242 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
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243 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
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244 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
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245 /**
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246 * @}
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247 */
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248
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249 /** @defgroup DMA_flag_definitions DMA flag definitions
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250 * @{
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251 */
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252 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
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253 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
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254 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
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255 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
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256 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
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257 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
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258 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
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259 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
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260 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
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261 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
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262 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
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263 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
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264 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
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265 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
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266 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
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267 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
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268 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
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269 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
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270 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
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271 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
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272 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
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273 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
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274 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
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275 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
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276 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
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277 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
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278 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
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279 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
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280 /**
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281 * @}
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282 */
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283
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284 /**
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285 * @}
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286 */
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287
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288
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289 /* Exported macro ------------------------------------------------------------*/
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290 /** @defgroup DMA_Exported_Macros DMA Exported Macros
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291 * @{
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292 */
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293
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294 /** @brief Reset DMA handle state
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295 * @param __HANDLE__: DMA handle.
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296 * @retval None
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297 */
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298 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
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299
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300 /**
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301 * @brief Enable the specified DMA Channel.
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302 * @param __HANDLE__: DMA handle
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303 * @retval None.
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304 */
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305 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
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306
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307 /**
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308 * @brief Disable the specified DMA Channel.
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309 * @param __HANDLE__: DMA handle
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310 * @retval None.
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311 */
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312 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
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313
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314
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315 /* Interrupt & Flag management */
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316
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317 /**
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318 * @brief Enables the specified DMA Channel interrupts.
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319 * @param __HANDLE__: DMA handle
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320 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
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321 * This parameter can be any combination of the following values:
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322 * @arg DMA_IT_TC: Transfer complete interrupt mask
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323 * @arg DMA_IT_HT: Half transfer complete interrupt mask
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324 * @arg DMA_IT_TE: Transfer error interrupt mask
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325 * @retval None
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326 */
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327 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
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328
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329 /**
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330 * @brief Disables the specified DMA Channel interrupts.
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331 * @param __HANDLE__: DMA handle
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332 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
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333 * This parameter can be any combination of the following values:
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334 * @arg DMA_IT_TC: Transfer complete interrupt mask
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335 * @arg DMA_IT_HT: Half transfer complete interrupt mask
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336 * @arg DMA_IT_TE: Transfer error interrupt mask
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337 * @retval None
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338 */
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339 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
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340
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341 /**
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342 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
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343 * @param __HANDLE__: DMA handle
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344 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
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345 * This parameter can be one of the following values:
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346 * @arg DMA_IT_TC: Transfer complete interrupt mask
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347 * @arg DMA_IT_HT: Half transfer complete interrupt mask
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348 * @arg DMA_IT_TE: Transfer error interrupt mask
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349 * @retval The state of DMA_IT (SET or RESET).
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350 */
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351 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
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352
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353 /**
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354 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
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355 * @param __HANDLE__: DMA handle
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356 *
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357 * @retval The number of remaining data units in the current DMA Channel transfer.
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358 */
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359 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
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360
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361 /**
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362 * @}
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363 */
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364
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365 /* Include DMA HAL Extension module */
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366 #include "stm32f1xx_hal_dma_ex.h"
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367
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368 /* Exported functions --------------------------------------------------------*/
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369 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
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370 * @{
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371 */
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372
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373 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
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374 * @{
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375 */
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376 /* Initialization and de-initialization functions *****************************/
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377 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
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378 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
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379 /**
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380 * @}
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381 */
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382
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383 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
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384 * @{
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385 */
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386 /* IO operation functions *****************************************************/
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387 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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388 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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389 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
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390 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
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391 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
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392 /**
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393 * @}
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394 */
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395
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396 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
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397 * @{
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398 */
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399 /* Peripheral State and Error functions ***************************************/
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400 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
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401 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
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402 /**
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403 * @}
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404 */
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405
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406 /**
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407 * @}
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408 */
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409
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410 /* Private Constants -------------------------------------------------------------*/
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411 /** @defgroup DMA_Private_Constants DMA Private Constants
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412 * @brief DMA private defines and constants
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413 * @{
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414 */
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415 /**
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416 * @}
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417 */
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418
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419 /* Private macros ------------------------------------------------------------*/
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420 /** @defgroup DMA_Private_Macros DMA Private Macros
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421 * @brief DMA private macros
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422 * @{
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423 */
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424
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425 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
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426
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427 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
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428 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
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429 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
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430
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431 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
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432 ((STATE) == DMA_PINC_DISABLE))
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433
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434 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
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435 ((STATE) == DMA_MINC_DISABLE))
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436
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437 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
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438 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
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439 ((SIZE) == DMA_PDATAALIGN_WORD))
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440
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441 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
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442 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
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443 ((SIZE) == DMA_MDATAALIGN_WORD ))
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444
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445 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
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446 ((MODE) == DMA_CIRCULAR))
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447
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448 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
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449 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
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450 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
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451 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
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452
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453 /**
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454 * @}
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455 */
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456
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457 /* Private functions ---------------------------------------------------------*/
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458 /** @defgroup DMA_Private_Functions DMA Private Functions
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459 * @brief DMA private functions
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460 * @{
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461 */
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462 /**
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463 * @}
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464 */
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465
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466 /**
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467 * @}
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468 */
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469
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470 /**
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471 * @}
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472 */
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473
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474 #ifdef __cplusplus
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475 }
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476 #endif
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477
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478 #endif /* __STM32F1xx_HAL_DMA_H */
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479
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480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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