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1 /**
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2 ******************************************************************************
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3 * @file system_stm32f1xx.c
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4 * @author MCD Application Team
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5 * @version V4.1.0
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6 * @date 29-April-2016
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7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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8 *
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9 * 1. This file provides two functions and one global variable to be called from
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10 * user application:
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11 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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12 * factors, AHB/APBx prescalers and Flash settings).
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13 * This function is called at startup just after reset and
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14 * before branch to main program. This call is made inside
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15 * the "startup_stm32f1xx_xx.s" file.
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16 *
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17 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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18 * by the user application to setup the SysTick
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19 * timer or configure other parameters.
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20 *
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21 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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22 * be called whenever the core clock is changed
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23 * during program execution.
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24 *
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25 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
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26 * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
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27 * configure the system clock before to branch to main program.
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28 *
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29 * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
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30 * the product used), refer to "HSE_VALUE".
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31 * When HSE is used as system clock source, directly or through PLL, and you
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32 * are using different crystal you have to adapt the HSE value to your own
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33 * configuration.
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34 *
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35 ******************************************************************************
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36 * @attention
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37 *
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38 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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39 *
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40 * Redistribution and use in source and binary forms, with or without modification,
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41 * are permitted provided that the following conditions are met:
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42 * 1. Redistributions of source code must retain the above copyright notice,
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43 * this list of conditions and the following disclaimer.
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44 * 2. Redistributions in binary form must reproduce the above copyright notice,
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45 * this list of conditions and the following disclaimer in the documentation
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46 * and/or other materials provided with the distribution.
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47 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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48 * may be used to endorse or promote products derived from this software
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49 * without specific prior written permission.
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50 *
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51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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52 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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54 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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58 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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59 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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61 *
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62 ******************************************************************************
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63 */
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64
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65 /** @addtogroup CMSIS
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66 * @{
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67 */
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68
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69 /** @addtogroup stm32f1xx_system
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70 * @{
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71 */
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72
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73 /** @addtogroup STM32F1xx_System_Private_Includes
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74 * @{
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75 */
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76
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77 #include "stm32f1xx.h"
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78
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79 /**
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80 * @}
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81 */
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82
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83 /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
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84 * @{
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85 */
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86
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87 /**
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88 * @}
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89 */
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90
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91 /** @addtogroup STM32F1xx_System_Private_Defines
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92 * @{
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93 */
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94
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95 #if !defined (HSE_VALUE)
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96 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
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97 This value can be provided and adapted by the user application. */
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98 #endif /* HSE_VALUE */
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99
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100 #if !defined (HSI_VALUE)
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101 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
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102 This value can be provided and adapted by the user application. */
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103 #endif /* HSI_VALUE */
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104
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105 /*!< Uncomment the following line if you need to use external SRAM */
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106 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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107 /* #define DATA_IN_ExtSRAM */
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108 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
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109
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110 /*!< Uncomment the following line if you need to relocate your vector Table in
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111 Internal SRAM. */
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112 /* #define VECT_TAB_SRAM */
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113 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
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114 This value must be a multiple of 0x200. */
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115
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116
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117 /**
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118 * @}
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119 */
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120
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121 /** @addtogroup STM32F1xx_System_Private_Macros
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122 * @{
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123 */
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124
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125 /**
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126 * @}
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127 */
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128
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129 /** @addtogroup STM32F1xx_System_Private_Variables
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130 * @{
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131 */
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132
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133 /*******************************************************************************
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134 * Clock Definitions
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135 *******************************************************************************/
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136 #if defined(STM32F100xB) ||defined(STM32F100xE)
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137 uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */
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138 #else /*!< HSI Selected as System Clock source */
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139 uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */
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140 #endif
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141
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142 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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143 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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144
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145 /**
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146 * @}
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147 */
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148
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149 /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
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150 * @{
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151 */
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152
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153 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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154 #ifdef DATA_IN_ExtSRAM
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155 static void SystemInit_ExtMemCtl(void);
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156 #endif /* DATA_IN_ExtSRAM */
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157 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
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158
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159 /**
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160 * @}
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161 */
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162
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163 /** @addtogroup STM32F1xx_System_Private_Functions
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164 * @{
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165 */
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166
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167 /**
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168 * @brief Setup the microcontroller system
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169 * Initialize the Embedded Flash Interface, the PLL and update the
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170 * SystemCoreClock variable.
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171 * @note This function should be used only after reset.
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172 * @param None
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173 * @retval None
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174 */
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175 void SystemInit (void)
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176 {
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177 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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178 /* Set HSION bit */
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179 RCC->CR |= (uint32_t)0x00000001;
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180
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181 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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182 #if !defined(STM32F105xC) && !defined(STM32F107xC)
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183 RCC->CFGR &= (uint32_t)0xF8FF0000;
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184 #else
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185 RCC->CFGR &= (uint32_t)0xF0FF0000;
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186 #endif /* STM32F105xC */
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187
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188 /* Reset HSEON, CSSON and PLLON bits */
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189 RCC->CR &= (uint32_t)0xFEF6FFFF;
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190
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191 /* Reset HSEBYP bit */
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192 RCC->CR &= (uint32_t)0xFFFBFFFF;
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193
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194 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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195 RCC->CFGR &= (uint32_t)0xFF80FFFF;
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196
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197 #if defined(STM32F105xC) || defined(STM32F107xC)
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198 /* Reset PLL2ON and PLL3ON bits */
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199 RCC->CR &= (uint32_t)0xEBFFFFFF;
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200
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201 /* Disable all interrupts and clear pending bits */
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202 RCC->CIR = 0x00FF0000;
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203
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204 /* Reset CFGR2 register */
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205 RCC->CFGR2 = 0x00000000;
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206 #elif defined(STM32F100xB) || defined(STM32F100xE)
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207 /* Disable all interrupts and clear pending bits */
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208 RCC->CIR = 0x009F0000;
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209
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210 /* Reset CFGR2 register */
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211 RCC->CFGR2 = 0x00000000;
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212 #else
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213 /* Disable all interrupts and clear pending bits */
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214 RCC->CIR = 0x009F0000;
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215 #endif /* STM32F105xC */
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216
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217 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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218 #ifdef DATA_IN_ExtSRAM
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219 SystemInit_ExtMemCtl();
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220 #endif /* DATA_IN_ExtSRAM */
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221 #endif
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222
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223 #ifdef VECT_TAB_SRAM
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224 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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225 #else
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226 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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227 #endif
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228 }
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229
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230 /**
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231 * @brief Update SystemCoreClock variable according to Clock Register Values.
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232 * The SystemCoreClock variable contains the core clock (HCLK), it can
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233 * be used by the user application to setup the SysTick timer or configure
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234 * other parameters.
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235 *
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236 * @note Each time the core clock (HCLK) changes, this function must be called
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237 * to update SystemCoreClock variable value. Otherwise, any configuration
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238 * based on this variable will be incorrect.
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239 *
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240 * @note - The system frequency computed by this function is not the real
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241 * frequency in the chip. It is calculated based on the predefined
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242 * constant and the selected clock source:
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243 *
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244 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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245 *
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246 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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247 *
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248 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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249 * or HSI_VALUE(*) multiplied by the PLL factors.
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250 *
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251 * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
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252 * 8 MHz) but the real value may vary depending on the variations
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253 * in voltage and temperature.
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254 *
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255 * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
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256 * 8 MHz or 25 MHz, depending on the product used), user has to ensure
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257 * that HSE_VALUE is same as the real frequency of the crystal used.
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258 * Otherwise, this function may have wrong result.
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259 *
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260 * - The result of this function could be not correct when using fractional
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261 * value for HSE crystal.
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262 * @param None
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263 * @retval None
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264 */
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265 void SystemCoreClockUpdate (void)
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266 {
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267 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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268
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269 #if defined(STM32F105xC) || defined(STM32F107xC)
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270 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
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271 #endif /* STM32F105xC */
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272
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273 #if defined(STM32F100xB) || defined(STM32F100xE)
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274 uint32_t prediv1factor = 0;
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275 #endif /* STM32F100xB or STM32F100xE */
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276
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277 /* Get SYSCLK source -------------------------------------------------------*/
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278 tmp = RCC->CFGR & RCC_CFGR_SWS;
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279
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280 switch (tmp)
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281 {
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282 case 0x00: /* HSI used as system clock */
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283 SystemCoreClock = HSI_VALUE;
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284 break;
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285 case 0x04: /* HSE used as system clock */
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286 SystemCoreClock = HSE_VALUE;
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287 break;
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288 case 0x08: /* PLL used as system clock */
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289
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290 /* Get PLL clock source and multiplication factor ----------------------*/
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291 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
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292 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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293
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294 #if !defined(STM32F105xC) && !defined(STM32F107xC)
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295 pllmull = ( pllmull >> 18) + 2;
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296
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297 if (pllsource == 0x00)
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298 {
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299 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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300 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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301 }
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302 else
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303 {
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304 #if defined(STM32F100xB) || defined(STM32F100xE)
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305 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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306 /* HSE oscillator clock selected as PREDIV1 clock entry */
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307 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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308 #else
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309 /* HSE selected as PLL clock entry */
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310 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
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311 {/* HSE oscillator clock divided by 2 */
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312 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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313 }
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314 else
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315 {
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316 SystemCoreClock = HSE_VALUE * pllmull;
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317 }
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318 #endif
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319 }
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320 #else
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321 pllmull = pllmull >> 18;
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322
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323 if (pllmull != 0x0D)
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324 {
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325 pllmull += 2;
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326 }
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327 else
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328 { /* PLL multiplication factor = PLL input clock * 6.5 */
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329 pllmull = 13 / 2;
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330 }
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331
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332 if (pllsource == 0x00)
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333 {
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334 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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335 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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336 }
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337 else
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338 {/* PREDIV1 selected as PLL clock entry */
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339
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340 /* Get PREDIV1 clock source and division factor */
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341 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
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342 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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343
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344 if (prediv1source == 0)
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345 {
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346 /* HSE oscillator clock selected as PREDIV1 clock entry */
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347 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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348 }
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349 else
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350 {/* PLL2 clock selected as PREDIV1 clock entry */
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351
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352 /* Get PREDIV2 division factor and PLL2 multiplication factor */
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353 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
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354 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
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355 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
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356 }
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357 }
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358 #endif /* STM32F105xC */
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359 break;
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360
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361 default:
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362 SystemCoreClock = HSI_VALUE;
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363 break;
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364 }
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365
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366 /* Compute HCLK clock frequency ----------------*/
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367 /* Get HCLK prescaler */
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368 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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369 /* HCLK clock frequency */
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370 SystemCoreClock >>= tmp;
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371 }
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372
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373 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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374 /**
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375 * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
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376 * before jump to __main
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377 * @param None
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378 * @retval None
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379 */
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380 #ifdef DATA_IN_ExtSRAM
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381 /**
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382 * @brief Setup the external memory controller.
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383 * Called in startup_stm32f1xx_xx.s/.c before jump to main.
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384 * This function configures the external SRAM mounted on STM3210E-EVAL
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385 * board (STM32 High density devices). This SRAM will be used as program
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386 * data memory (including heap and stack).
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387 * @param None
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388 * @retval None
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389 */
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390 void SystemInit_ExtMemCtl(void)
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391 {
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392 __IO uint32_t tmpreg;
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393 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
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394 required, then adjust the Register Addresses */
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395
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396 /* Enable FSMC clock */
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397 RCC->AHBENR = 0x00000114;
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398
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399 /* Delay after an RCC peripheral clock enabling */
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400 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
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401
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402 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
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403 RCC->APB2ENR = 0x000001E0;
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404
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405 /* Delay after an RCC peripheral clock enabling */
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406 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
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407
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408 (void)(tmpreg);
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409
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410 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
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411 /*---------------- SRAM Address lines configuration -------------------------*/
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412 /*---------------- NOE and NWE configuration --------------------------------*/
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413 /*---------------- NE3 configuration ----------------------------------------*/
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414 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
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415
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416 GPIOD->CRL = 0x44BB44BB;
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417 GPIOD->CRH = 0xBBBBBBBB;
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418
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419 GPIOE->CRL = 0xB44444BB;
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420 GPIOE->CRH = 0xBBBBBBBB;
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421
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422 GPIOF->CRL = 0x44BBBBBB;
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423 GPIOF->CRH = 0xBBBB4444;
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424
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425 GPIOG->CRL = 0x44BBBBBB;
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426 GPIOG->CRH = 0x444B4B44;
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427
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428 /*---------------- FSMC Configuration ---------------------------------------*/
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429 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
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430
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431 FSMC_Bank1->BTCR[4] = 0x00001091;
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432 FSMC_Bank1->BTCR[5] = 0x00110212;
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433 }
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434 #endif /* DATA_IN_ExtSRAM */
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435 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
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436
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437 /**
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438 * @}
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439 */
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440
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441 /**
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442 * @}
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443 */
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444
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445 /**
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446 * @}
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447 */
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448 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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