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1 /**
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2 ******************************************************************************
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3 * @file stm32l4xx_hal_rcc.h
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4 * @author MCD Application Team
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5 * @version V1.6.0
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6 * @date 28-October-2016
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7 * @brief Header file of RCC HAL module.
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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12 *
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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23 *
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 *
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35 ******************************************************************************
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36 */
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37
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32L4xx_HAL_RCC_H
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40 #define __STM32L4xx_HAL_RCC_H
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41
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42 #ifdef __cplusplus
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43 extern "C" {
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44 #endif
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32l4xx_hal_def.h"
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48
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49 /** @addtogroup STM32L4xx_HAL_Driver
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50 * @{
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51 */
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52
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53 /** @addtogroup RCC
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54 * @{
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55 */
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56
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57 /* Exported types ------------------------------------------------------------*/
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58 /** @defgroup RCC_Exported_Types RCC Exported Types
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59 * @{
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60 */
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61
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62 /**
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63 * @brief RCC PLL configuration structure definition
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64 */
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65 typedef struct
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66 {
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67 uint32_t PLLState; /*!< The new state of the PLL.
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68 This parameter can be a value of @ref RCC_PLL_Config */
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69
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70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
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71 This parameter must be a value of @ref RCC_PLL_Clock_Source */
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72
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73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
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74 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
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75
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76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
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77 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
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78
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79 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
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80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
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81
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82 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
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83 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
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84
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85 uint32_t PLLR; /*!< PLLR: Division for the main system clock.
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86 User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
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87 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
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88
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89 }RCC_PLLInitTypeDef;
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90
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91 /**
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92 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
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93 */
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94 typedef struct
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95 {
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96 uint32_t OscillatorType; /*!< The oscillators to be configured.
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97 This parameter can be a value of @ref RCC_Oscillator_Type */
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98
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99 uint32_t HSEState; /*!< The new state of the HSE.
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100 This parameter can be a value of @ref RCC_HSE_Config */
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101
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102 uint32_t LSEState; /*!< The new state of the LSE.
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103 This parameter can be a value of @ref RCC_LSE_Config */
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104
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105 uint32_t HSIState; /*!< The new state of the HSI.
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106 This parameter can be a value of @ref RCC_HSI_Config */
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107
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108 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
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109 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.
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110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */
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111
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112 uint32_t LSIState; /*!< The new state of the LSI.
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113 This parameter can be a value of @ref RCC_LSI_Config */
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114
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115 uint32_t MSIState; /*!< The new state of the MSI.
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116 This parameter can be a value of @ref RCC_MSI_Config */
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117
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118 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
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119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
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120
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121 uint32_t MSIClockRange; /*!< The MSI frequency range.
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122 This parameter can be a value of @ref RCC_MSI_Clock_Range */
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123
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124 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L45x/STM32L46x devices).
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125 This parameter can be a value of @ref RCC_HSI48_Config */
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126
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127 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
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128
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129 }RCC_OscInitTypeDef;
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130
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131 /**
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132 * @brief RCC System, AHB and APB busses clock configuration structure definition
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133 */
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134 typedef struct
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135 {
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136 uint32_t ClockType; /*!< The clock to be configured.
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137 This parameter can be a value of @ref RCC_System_Clock_Type */
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138
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139 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
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140 This parameter can be a value of @ref RCC_System_Clock_Source */
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141
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142 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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143 This parameter can be a value of @ref RCC_AHB_Clock_Source */
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144
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145 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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146 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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147
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148 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
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149 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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150
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151 }RCC_ClkInitTypeDef;
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152
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153 /**
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154 * @}
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155 */
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156
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157 /* Exported constants --------------------------------------------------------*/
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158 /** @defgroup RCC_Exported_Constants RCC Exported Constants
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159 * @{
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160 */
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161
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162 /** @defgroup RCC_Timeout_Value Timeout Values
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163 * @{
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164 */
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165 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
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166 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
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167 /**
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168 * @}
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169 */
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170
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171 /** @defgroup RCC_Oscillator_Type Oscillator Type
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172 * @{
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173 */
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174 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */
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175 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */
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176 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */
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177 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */
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178 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */
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179 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */
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180 #if defined(RCC_HSI48_SUPPORT)
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181 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /*!< HSI48 to configure */
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182 #endif /* RCC_HSI48_SUPPORT */
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183 /**
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184 * @}
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185 */
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186
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187 /** @defgroup RCC_HSE_Config HSE Config
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188 * @{
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189 */
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190 #define RCC_HSE_OFF ((uint32_t)0x00000000U) /*!< HSE clock deactivation */
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191 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
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192 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
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193 /**
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194 * @}
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195 */
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196
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197 /** @defgroup RCC_LSE_Config LSE Config
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198 * @{
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199 */
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200 #define RCC_LSE_OFF ((uint32_t)0x00000000U) /*!< LSE clock deactivation */
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201 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
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202 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
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203 /**
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204 * @}
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205 */
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206
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207 /** @defgroup RCC_HSI_Config HSI Config
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208 * @{
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209 */
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210 #define RCC_HSI_OFF ((uint32_t)0x00000000U) /*!< HSI clock deactivation */
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211 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
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212
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213 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
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214 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
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215 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
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216 #else
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217 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x40U) /* Default HSI calibration trimming value */
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218 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
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219 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
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220 /**
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221 * @}
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222 */
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223
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224 /** @defgroup RCC_LSI_Config LSI Config
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225 * @{
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226 */
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227 #define RCC_LSI_OFF ((uint32_t)0x00000000U) /*!< LSI clock deactivation */
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228 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
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229 /**
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230 * @}
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231 */
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232
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233 /** @defgroup RCC_MSI_Config MSI Config
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234 * @{
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235 */
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236 #define RCC_MSI_OFF ((uint32_t)0x00000000U) /*!< MSI clock deactivation */
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237 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */
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238
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239 #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /*!< Default MSI calibration trimming value */
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240 /**
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241 * @}
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242 */
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243
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244 #if defined(RCC_HSI48_SUPPORT)
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245 /** @defgroup RCC_HSI48_Config HSI48 Config
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246 * @{
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247 */
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248 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
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249 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
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250 /**
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251 * @}
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252 */
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253 #else
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254 /** @defgroup RCC_HSI48_Config HSI48 Config
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255 * @{
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256 */
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257 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */
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258 /**
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259 * @}
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260 */
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261 #endif /* RCC_HSI48_SUPPORT */
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262
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263 /** @defgroup RCC_PLL_Config PLL Config
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264 * @{
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265 */
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266 #define RCC_PLL_NONE ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */
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267 #define RCC_PLL_OFF ((uint32_t)0x00000001U) /*!< PLL deactivation */
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268 #define RCC_PLL_ON ((uint32_t)0x00000002U) /*!< PLL activation */
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269 /**
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270 * @}
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271 */
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272
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273 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
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274 * @{
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275 */
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276 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
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277 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /*!< PLLP division factor = 2 */
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278 #define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /*!< PLLP division factor = 3 */
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279 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /*!< PLLP division factor = 4 */
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280 #define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /*!< PLLP division factor = 5 */
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281 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /*!< PLLP division factor = 6 */
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282 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */
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283 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /*!< PLLP division factor = 8 */
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284 #define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /*!< PLLP division factor = 9 */
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285 #define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */
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286 #define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */
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287 #define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */
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288 #define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */
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289 #define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */
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290 #define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */
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291 #define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */
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292 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
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293 #define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */
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294 #define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */
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295 #define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */
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296 #define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */
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297 #define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */
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298 #define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */
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299 #define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */
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300 #define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */
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301 #define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */
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302 #define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */
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303 #define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */
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304 #define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */
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305 #define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */
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306 #define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */
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307 #else
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308 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */
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309 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */
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310 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
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311 /**
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312 * @}
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313 */
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314
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315 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
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316 * @{
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317 */
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318 #define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */
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319 #define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */
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320 #define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */
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321 #define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */
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322 /**
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323 * @}
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324 */
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325
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326 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
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327 * @{
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328 */
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329 #define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */
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330 #define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */
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331 #define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */
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332 #define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */
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333 /**
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334 * @}
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335 */
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336
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337 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
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338 * @{
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339 */
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340 #define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as PLL entry clock source */
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341 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
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342 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
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343 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
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344 /**
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345 * @}
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346 */
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347
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348 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
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349 * @{
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350 */
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351 #if defined(RCC_PLLSAI2_SUPPORT)
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352 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */
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353 #else
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354 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */
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355 #endif /* RCC_PLLSAI2_SUPPORT */
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356 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
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357 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */
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358 /**
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359 * @}
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360 */
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361
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362 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
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363 * @{
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364 */
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365 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */
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366 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */
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367 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */
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368 /**
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369 * @}
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370 */
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371
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372 #if defined(RCC_PLLSAI2_SUPPORT)
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373
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374 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
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375 * @{
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376 */
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377 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */
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378 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */
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379 /**
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380 * @}
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381 */
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382
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383 #endif /* RCC_PLLSAI2_SUPPORT */
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384
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385 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range
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386 * @{
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387 */
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388 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
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389 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
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390 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
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391 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
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392 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
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393 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
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394 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
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395 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
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396 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
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397 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
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398 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
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399 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
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400 /**
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401 * @}
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402 */
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403
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404 /** @defgroup RCC_System_Clock_Type System Clock Type
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405 * @{
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406 */
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407 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */
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408 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */
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409 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */
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410 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */
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411 /**
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412 * @}
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413 */
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414
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415 /** @defgroup RCC_System_Clock_Source System Clock Source
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416 * @{
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417 */
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418 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
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419 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
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420 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
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421 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
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422 /**
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423 * @}
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424 */
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425
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426 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
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427 * @{
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428 */
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429 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
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430 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
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431 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
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432 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
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433 /**
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434 * @}
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435 */
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436
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437 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
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438 * @{
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439 */
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440 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
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441 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
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442 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
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443 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
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444 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
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445 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
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446 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
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447 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
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448 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
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449 /**
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450 * @}
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451 */
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452
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453 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
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454 * @{
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455 */
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456 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
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457 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
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458 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
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459 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
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460 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
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461 /**
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462 * @}
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463 */
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464
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465 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
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466 * @{
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467 */
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468 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */
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469 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
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470 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
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471 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
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472 /**
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473 * @}
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474 */
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475
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476 /** @defgroup RCC_MCO_Index MCO Index
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477 * @{
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478 */
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479 #define RCC_MCO1 ((uint32_t)0x00000000U)
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480 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
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481 /**
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482 * @}
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483 */
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484
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485 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
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486 * @{
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487 */
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488 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */
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489 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
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490 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
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491 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
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492 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
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493 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
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494 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
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495 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
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496 #if defined(RCC_HSI48_SUPPORT)
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497 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */
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498 #endif /* RCC_HSI48_SUPPORT */
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499 /**
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500 * @}
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501 */
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502
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503 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
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504 * @{
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505 */
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506 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
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507 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
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508 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
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509 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
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510 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
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511 /**
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512 * @}
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513 */
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514
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515 /** @defgroup RCC_Interrupt Interrupts
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516 * @{
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517 */
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518 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
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519 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
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520 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
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521 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
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522 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
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523 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
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524 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
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525 #if defined(RCC_PLLSAI2_SUPPORT)
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526 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
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527 #endif /* RCC_PLLSAI2_SUPPORT */
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528 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
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529 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
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|
530 #if defined(RCC_HSI48_SUPPORT)
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531 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
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532 #endif /* RCC_HSI48_SUPPORT */
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|
533 /**
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|
534 * @}
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|
|
535 */
|
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536
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|
|
537 /** @defgroup RCC_Flag Flags
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|
538 * Elements values convention: XXXYYYYYb
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|
|
539 * - YYYYY : Flag position in the register
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|
540 * - XXX : Register index
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|
541 * - 001: CR register
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542 * - 010: BDCR register
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543 * - 011: CSR register
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|
544 * - 100: CRRCR register
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|
545 * @{
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546 */
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|
547 /* Flags in the CR register */
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|
|
548 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */
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|
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549 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */
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550 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */
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|
551 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */
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552 #define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */
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|
553 #if defined(RCC_PLLSAI2_SUPPORT)
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|
554 #define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */
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555 #endif /* RCC_PLLSAI2_SUPPORT */
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556
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|
557 /* Flags in the BDCR register */
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|
|
558 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */
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|
559 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */
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560
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|
561 /* Flags in the CSR register */
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|
|
562 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< LSI Ready flag */
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563 #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */
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|
564 #define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF))) /*!< Firewall reset flag */
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565 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Option Byte Loader reset flag */
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|
|
566 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
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|
567 #define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF))) /*!< BOR reset flag */
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|
|
568 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
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|
|
569 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
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|
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570 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
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|
571 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
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|
572
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|
573 #if defined(RCC_HSI48_SUPPORT)
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|
574 /* Flags in the CRRCR register */
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|
|
575 #define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */
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|
|
576 #endif /* RCC_HSI48_SUPPORT */
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|
577 /**
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|
578 * @}
|
|
|
579 */
|
|
|
580
|
|
|
581 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
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|
|
582 * @{
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|
|
583 */
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|
|
584 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< LSE low drive capability */
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|
|
585 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
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|
|
586 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
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|
|
587 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
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|
|
588 /**
|
|
|
589 * @}
|
|
|
590 */
|
|
|
591
|
|
|
592 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
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|
|
593 * @{
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|
|
594 */
|
|
|
595 #define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */
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|
|
596 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
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|
|
597 /**
|
|
|
598 * @}
|
|
|
599 */
|
|
|
600
|
|
|
601 /**
|
|
|
602 * @}
|
|
|
603 */
|
|
|
604
|
|
|
605 /* Exported macros -----------------------------------------------------------*/
|
|
|
606
|
|
|
607 /** @defgroup RCC_Exported_Macros RCC Exported Macros
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|
|
608 * @{
|
|
|
609 */
|
|
|
610
|
|
|
611 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
|
|
|
612 * @brief Enable or disable the AHB1 peripheral clock.
|
|
|
613 * @note After reset, the peripheral clock (used for registers read/write access)
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|
|
614 * is disabled and the application software has to enable this clock before
|
|
|
615 * using it.
|
|
|
616 * @{
|
|
|
617 */
|
|
|
618
|
|
|
619 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
|
|
|
620 __IO uint32_t tmpreg; \
|
|
|
621 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
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|
|
622 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
623 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
|
|
|
624 UNUSED(tmpreg); \
|
|
|
625 } while(0)
|
|
|
626
|
|
|
627 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
|
|
|
628 __IO uint32_t tmpreg; \
|
|
|
629 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
|
|
|
630 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
631 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
|
|
|
632 UNUSED(tmpreg); \
|
|
|
633 } while(0)
|
|
|
634
|
|
|
635 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \
|
|
|
636 __IO uint32_t tmpreg; \
|
|
|
637 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
|
|
|
638 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
639 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
|
|
|
640 UNUSED(tmpreg); \
|
|
|
641 } while(0)
|
|
|
642
|
|
|
643 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
|
|
|
644 __IO uint32_t tmpreg; \
|
|
|
645 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
|
|
|
646 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
647 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
|
|
|
648 UNUSED(tmpreg); \
|
|
|
649 } while(0)
|
|
|
650
|
|
|
651 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
|
|
|
652 __IO uint32_t tmpreg; \
|
|
|
653 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
|
|
|
654 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
655 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
|
|
|
656 UNUSED(tmpreg); \
|
|
|
657 } while(0)
|
|
|
658
|
|
|
659
|
|
|
660 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
|
|
|
661
|
|
|
662 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
|
|
|
663
|
|
|
664 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
|
|
|
665
|
|
|
666 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
|
|
|
667
|
|
|
668 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
|
|
|
669
|
|
|
670 /**
|
|
|
671 * @}
|
|
|
672 */
|
|
|
673
|
|
|
674 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
|
|
|
675 * @brief Enable or disable the AHB2 peripheral clock.
|
|
|
676 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
677 * is disabled and the application software has to enable this clock before
|
|
|
678 * using it.
|
|
|
679 * @{
|
|
|
680 */
|
|
|
681
|
|
|
682 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
|
|
|
683 __IO uint32_t tmpreg; \
|
|
|
684 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
|
|
|
685 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
686 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
|
|
|
687 UNUSED(tmpreg); \
|
|
|
688 } while(0)
|
|
|
689
|
|
|
690 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
|
|
|
691 __IO uint32_t tmpreg; \
|
|
|
692 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
|
|
|
693 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
694 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
|
|
|
695 UNUSED(tmpreg); \
|
|
|
696 } while(0)
|
|
|
697
|
|
|
698 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
|
|
|
699 __IO uint32_t tmpreg; \
|
|
|
700 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
|
|
|
701 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
702 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
|
|
|
703 UNUSED(tmpreg); \
|
|
|
704 } while(0)
|
|
|
705
|
|
|
706 #if defined(GPIOD)
|
|
|
707 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
|
|
|
708 __IO uint32_t tmpreg; \
|
|
|
709 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
|
|
|
710 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
711 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
|
|
|
712 UNUSED(tmpreg); \
|
|
|
713 } while(0)
|
|
|
714 #endif /* GPIOD */
|
|
|
715
|
|
|
716 #if defined(GPIOE)
|
|
|
717 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
|
|
|
718 __IO uint32_t tmpreg; \
|
|
|
719 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
|
|
|
720 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
721 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
|
|
|
722 UNUSED(tmpreg); \
|
|
|
723 } while(0)
|
|
|
724 #endif /* GPIOE */
|
|
|
725
|
|
|
726 #if defined(GPIOF)
|
|
|
727 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
|
|
|
728 __IO uint32_t tmpreg; \
|
|
|
729 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
|
|
|
730 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
731 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
|
|
|
732 UNUSED(tmpreg); \
|
|
|
733 } while(0)
|
|
|
734 #endif /* GPIOF */
|
|
|
735
|
|
|
736 #if defined(GPIOG)
|
|
|
737 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
|
|
|
738 __IO uint32_t tmpreg; \
|
|
|
739 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
|
|
|
740 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
741 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
|
|
|
742 UNUSED(tmpreg); \
|
|
|
743 } while(0)
|
|
|
744 #endif /* GPIOG */
|
|
|
745
|
|
|
746 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
|
|
|
747 __IO uint32_t tmpreg; \
|
|
|
748 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
|
|
|
749 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
750 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
|
|
|
751 UNUSED(tmpreg); \
|
|
|
752 } while(0)
|
|
|
753
|
|
|
754 #if defined(USB_OTG_FS)
|
|
|
755 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
|
|
|
756 __IO uint32_t tmpreg; \
|
|
|
757 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
|
|
|
758 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
759 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
|
|
|
760 UNUSED(tmpreg); \
|
|
|
761 } while(0)
|
|
|
762 #endif /* USB_OTG_FS */
|
|
|
763
|
|
|
764 #define __HAL_RCC_ADC_CLK_ENABLE() do { \
|
|
|
765 __IO uint32_t tmpreg; \
|
|
|
766 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
|
|
|
767 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
768 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
|
|
|
769 UNUSED(tmpreg); \
|
|
|
770 } while(0)
|
|
|
771
|
|
|
772 #if defined(AES)
|
|
|
773 #define __HAL_RCC_AES_CLK_ENABLE() do { \
|
|
|
774 __IO uint32_t tmpreg; \
|
|
|
775 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
|
|
|
776 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
777 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
|
|
|
778 UNUSED(tmpreg); \
|
|
|
779 } while(0)
|
|
|
780 #endif /* AES */
|
|
|
781
|
|
|
782 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
|
|
|
783 __IO uint32_t tmpreg; \
|
|
|
784 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
|
|
|
785 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
786 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
|
|
|
787 UNUSED(tmpreg); \
|
|
|
788 } while(0)
|
|
|
789
|
|
|
790
|
|
|
791 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
|
|
|
792
|
|
|
793 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
|
|
|
794
|
|
|
795 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
|
|
|
796
|
|
|
797 #if defined(GPIOD)
|
|
|
798 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
|
|
|
799 #endif /* GPIOD */
|
|
|
800
|
|
|
801 #if defined(GPIOE)
|
|
|
802 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
|
|
|
803 #endif /* GPIOE */
|
|
|
804
|
|
|
805 #if defined(GPIOF)
|
|
|
806 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
|
|
|
807 #endif /* GPIOF */
|
|
|
808
|
|
|
809 #if defined(GPIOG)
|
|
|
810 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
|
|
|
811 #endif /* GPIOG */
|
|
|
812
|
|
|
813 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
|
|
|
814
|
|
|
815 #if defined(USB_OTG_FS)
|
|
|
816 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
|
|
|
817 #endif /* USB_OTG_FS */
|
|
|
818
|
|
|
819 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
|
|
|
820
|
|
|
821 #if defined(AES)
|
|
|
822 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
|
|
|
823 #endif /* AES */
|
|
|
824
|
|
|
825 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
|
|
|
826
|
|
|
827 /**
|
|
|
828 * @}
|
|
|
829 */
|
|
|
830
|
|
|
831 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
|
|
|
832 * @brief Enable or disable the AHB3 peripheral clock.
|
|
|
833 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
834 * is disabled and the application software has to enable this clock before
|
|
|
835 * using it.
|
|
|
836 * @{
|
|
|
837 */
|
|
|
838
|
|
|
839 #if defined(FMC_BANK1)
|
|
|
840 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
|
|
|
841 __IO uint32_t tmpreg; \
|
|
|
842 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
|
|
|
843 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
844 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
|
|
|
845 UNUSED(tmpreg); \
|
|
|
846 } while(0)
|
|
|
847 #endif /* FMC_BANK1 */
|
|
|
848
|
|
|
849 #if defined(QUADSPI)
|
|
|
850 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
|
|
|
851 __IO uint32_t tmpreg; \
|
|
|
852 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
|
|
|
853 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
854 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
|
|
|
855 UNUSED(tmpreg); \
|
|
|
856 } while(0)
|
|
|
857 #endif /* QUADSPI */
|
|
|
858
|
|
|
859 #if defined(FMC_BANK1)
|
|
|
860 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
|
|
|
861 #endif /* FMC_BANK1 */
|
|
|
862
|
|
|
863 #if defined(QUADSPI)
|
|
|
864 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
|
|
|
865 #endif /* QUADSPI */
|
|
|
866
|
|
|
867 /**
|
|
|
868 * @}
|
|
|
869 */
|
|
|
870
|
|
|
871 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
|
|
|
872 * @brief Enable or disable the APB1 peripheral clock.
|
|
|
873 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
874 * is disabled and the application software has to enable this clock before
|
|
|
875 * using it.
|
|
|
876 * @{
|
|
|
877 */
|
|
|
878
|
|
|
879 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
|
|
|
880 __IO uint32_t tmpreg; \
|
|
|
881 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
|
|
|
882 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
883 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
|
|
|
884 UNUSED(tmpreg); \
|
|
|
885 } while(0)
|
|
|
886
|
|
|
887 #if defined(TIM3)
|
|
|
888 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
|
|
|
889 __IO uint32_t tmpreg; \
|
|
|
890 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
|
|
|
891 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
892 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
|
|
|
893 UNUSED(tmpreg); \
|
|
|
894 } while(0)
|
|
|
895 #endif /* TIM3 */
|
|
|
896
|
|
|
897 #if defined(TIM4)
|
|
|
898 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
|
|
|
899 __IO uint32_t tmpreg; \
|
|
|
900 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
|
|
|
901 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
902 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
|
|
|
903 UNUSED(tmpreg); \
|
|
|
904 } while(0)
|
|
|
905 #endif /* TIM4 */
|
|
|
906
|
|
|
907 #if defined(TIM5)
|
|
|
908 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
|
|
|
909 __IO uint32_t tmpreg; \
|
|
|
910 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
|
|
|
911 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
912 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
|
|
|
913 UNUSED(tmpreg); \
|
|
|
914 } while(0)
|
|
|
915 #endif /* TIM5 */
|
|
|
916
|
|
|
917 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
|
|
|
918 __IO uint32_t tmpreg; \
|
|
|
919 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
|
|
|
920 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
921 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
|
|
|
922 UNUSED(tmpreg); \
|
|
|
923 } while(0)
|
|
|
924
|
|
|
925 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
|
|
|
926 __IO uint32_t tmpreg; \
|
|
|
927 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
|
|
|
928 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
929 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
|
|
|
930 UNUSED(tmpreg); \
|
|
|
931 } while(0)
|
|
|
932
|
|
|
933 #if defined(LCD)
|
|
|
934 #define __HAL_RCC_LCD_CLK_ENABLE() do { \
|
|
|
935 __IO uint32_t tmpreg; \
|
|
|
936 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
|
|
|
937 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
938 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
|
|
|
939 UNUSED(tmpreg); \
|
|
|
940 } while(0)
|
|
|
941 #endif /* LCD */
|
|
|
942
|
|
|
943 #if defined(RCC_APB1ENR1_RTCAPBEN)
|
|
|
944 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
|
|
|
945 __IO uint32_t tmpreg; \
|
|
|
946 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
|
|
|
947 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
948 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
|
|
|
949 UNUSED(tmpreg); \
|
|
|
950 } while(0)
|
|
|
951 #endif /* RCC_APB1ENR1_RTCAPBEN */
|
|
|
952
|
|
|
953 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
|
|
|
954 __IO uint32_t tmpreg; \
|
|
|
955 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
|
|
|
956 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
957 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
|
|
|
958 UNUSED(tmpreg); \
|
|
|
959 } while(0)
|
|
|
960
|
|
|
961 #if defined(SPI2)
|
|
|
962 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
|
|
|
963 __IO uint32_t tmpreg; \
|
|
|
964 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
|
|
|
965 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
966 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
|
|
|
967 UNUSED(tmpreg); \
|
|
|
968 } while(0)
|
|
|
969 #endif /* SPI2 */
|
|
|
970
|
|
|
971 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
|
|
|
972 __IO uint32_t tmpreg; \
|
|
|
973 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
|
|
|
974 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
975 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
|
|
|
976 UNUSED(tmpreg); \
|
|
|
977 } while(0)
|
|
|
978
|
|
|
979 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
|
|
|
980 __IO uint32_t tmpreg; \
|
|
|
981 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
|
|
|
982 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
983 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
|
|
|
984 UNUSED(tmpreg); \
|
|
|
985 } while(0)
|
|
|
986
|
|
|
987 #if defined(USART3)
|
|
|
988 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
|
|
|
989 __IO uint32_t tmpreg; \
|
|
|
990 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
|
|
|
991 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
992 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
|
|
|
993 UNUSED(tmpreg); \
|
|
|
994 } while(0)
|
|
|
995 #endif /* USART3 */
|
|
|
996
|
|
|
997 #if defined(UART4)
|
|
|
998 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
|
|
|
999 __IO uint32_t tmpreg; \
|
|
|
1000 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
|
|
|
1001 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1002 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
|
|
|
1003 UNUSED(tmpreg); \
|
|
|
1004 } while(0)
|
|
|
1005 #endif /* UART4 */
|
|
|
1006
|
|
|
1007 #if defined(UART5)
|
|
|
1008 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
|
|
|
1009 __IO uint32_t tmpreg; \
|
|
|
1010 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
|
|
|
1011 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1012 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
|
|
|
1013 UNUSED(tmpreg); \
|
|
|
1014 } while(0)
|
|
|
1015 #endif /* UART5 */
|
|
|
1016
|
|
|
1017 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
|
|
|
1018 __IO uint32_t tmpreg; \
|
|
|
1019 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
|
|
|
1020 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1021 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
|
|
|
1022 UNUSED(tmpreg); \
|
|
|
1023 } while(0)
|
|
|
1024
|
|
|
1025 #if defined(I2C2)
|
|
|
1026 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
|
|
|
1027 __IO uint32_t tmpreg; \
|
|
|
1028 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
|
|
|
1029 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1030 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
|
|
|
1031 UNUSED(tmpreg); \
|
|
|
1032 } while(0)
|
|
|
1033 #endif /* I2C2 */
|
|
|
1034
|
|
|
1035 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
|
|
|
1036 __IO uint32_t tmpreg; \
|
|
|
1037 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
|
|
|
1038 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1039 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
|
|
|
1040 UNUSED(tmpreg); \
|
|
|
1041 } while(0)
|
|
|
1042
|
|
|
1043 #if defined(I2C4)
|
|
|
1044 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
|
|
|
1045 __IO uint32_t tmpreg; \
|
|
|
1046 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
|
|
|
1047 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1048 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
|
|
|
1049 UNUSED(tmpreg); \
|
|
|
1050 } while(0)
|
|
|
1051 #endif /* I2C4 */
|
|
|
1052
|
|
|
1053 #if defined(CRS)
|
|
|
1054 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
|
|
|
1055 __IO uint32_t tmpreg; \
|
|
|
1056 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
|
|
|
1057 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1058 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
|
|
|
1059 UNUSED(tmpreg); \
|
|
|
1060 } while(0)
|
|
|
1061 #endif /* CRS */
|
|
|
1062
|
|
|
1063 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
|
|
|
1064 __IO uint32_t tmpreg; \
|
|
|
1065 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
|
|
|
1066 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1067 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
|
|
|
1068 UNUSED(tmpreg); \
|
|
|
1069 } while(0)
|
|
|
1070
|
|
|
1071 #if defined(USB)
|
|
|
1072 #define __HAL_RCC_USB_CLK_ENABLE() do { \
|
|
|
1073 __IO uint32_t tmpreg; \
|
|
|
1074 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
|
|
|
1075 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1076 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
|
|
|
1077 UNUSED(tmpreg); \
|
|
|
1078 } while(0)
|
|
|
1079 #endif /* USB */
|
|
|
1080
|
|
|
1081 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
|
|
|
1082 __IO uint32_t tmpreg; \
|
|
|
1083 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
|
|
|
1084 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1085 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
|
|
|
1086 UNUSED(tmpreg); \
|
|
|
1087 } while(0)
|
|
|
1088
|
|
|
1089 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
|
|
|
1090 __IO uint32_t tmpreg; \
|
|
|
1091 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
|
|
|
1092 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1093 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
|
|
|
1094 UNUSED(tmpreg); \
|
|
|
1095 } while(0)
|
|
|
1096
|
|
|
1097 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
|
|
|
1098 __IO uint32_t tmpreg; \
|
|
|
1099 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
|
|
|
1100 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1101 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
|
|
|
1102 UNUSED(tmpreg); \
|
|
|
1103 } while(0)
|
|
|
1104
|
|
|
1105 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
|
|
|
1106 __IO uint32_t tmpreg; \
|
|
|
1107 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
|
|
|
1108 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1109 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
|
|
|
1110 UNUSED(tmpreg); \
|
|
|
1111 } while(0)
|
|
|
1112
|
|
|
1113 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
|
|
|
1114 __IO uint32_t tmpreg; \
|
|
|
1115 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
|
|
|
1116 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1117 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
|
|
|
1118 UNUSED(tmpreg); \
|
|
|
1119 } while(0)
|
|
|
1120
|
|
|
1121 #if defined(SWPMI1)
|
|
|
1122 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
|
|
|
1123 __IO uint32_t tmpreg; \
|
|
|
1124 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
|
|
|
1125 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1126 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
|
|
|
1127 UNUSED(tmpreg); \
|
|
|
1128 } while(0)
|
|
|
1129 #endif /* SWPMI1 */
|
|
|
1130
|
|
|
1131 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
|
|
|
1132 __IO uint32_t tmpreg; \
|
|
|
1133 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
|
|
|
1134 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1135 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
|
|
|
1136 UNUSED(tmpreg); \
|
|
|
1137 } while(0)
|
|
|
1138
|
|
|
1139
|
|
|
1140 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
|
|
|
1141
|
|
|
1142 #if defined(TIM3)
|
|
|
1143 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
|
|
|
1144 #endif /* TIM3 */
|
|
|
1145
|
|
|
1146 #if defined(TIM4)
|
|
|
1147 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
|
|
|
1148 #endif /* TIM4 */
|
|
|
1149
|
|
|
1150 #if defined(TIM5)
|
|
|
1151 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
|
|
|
1152 #endif /* TIM5 */
|
|
|
1153
|
|
|
1154 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
|
|
|
1155
|
|
|
1156 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
|
|
|
1157
|
|
|
1158 #if defined(LCD)
|
|
|
1159 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
|
|
|
1160 #endif /* LCD */
|
|
|
1161
|
|
|
1162 #if defined(RCC_APB1ENR1_RTCAPBEN)
|
|
|
1163 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
|
|
|
1164 #endif /* RCC_APB1ENR1_RTCAPBEN */
|
|
|
1165
|
|
|
1166 #if defined(SPI2)
|
|
|
1167 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
|
|
|
1168 #endif /* SPI2 */
|
|
|
1169
|
|
|
1170 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
|
|
|
1171
|
|
|
1172 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
|
|
|
1173
|
|
|
1174 #if defined(USART3)
|
|
|
1175 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
|
|
|
1176 #endif /* USART3 */
|
|
|
1177
|
|
|
1178 #if defined(UART4)
|
|
|
1179 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
|
|
|
1180 #endif /* UART4 */
|
|
|
1181
|
|
|
1182 #if defined(UART5)
|
|
|
1183 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
|
|
|
1184 #endif /* UART5 */
|
|
|
1185
|
|
|
1186 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
|
|
|
1187
|
|
|
1188 #if defined(I2C2)
|
|
|
1189 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
|
|
|
1190 #endif /* I2C2 */
|
|
|
1191
|
|
|
1192 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
|
|
|
1193
|
|
|
1194 #if defined(I2C4)
|
|
|
1195 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
|
|
|
1196 #endif /* I2C4 */
|
|
|
1197
|
|
|
1198 #if defined(CRS)
|
|
|
1199 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
|
|
|
1200 #endif /* CRS */
|
|
|
1201
|
|
|
1202 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
|
|
|
1203
|
|
|
1204 #if defined(USB)
|
|
|
1205 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
|
|
|
1206 #endif /* USB */
|
|
|
1207
|
|
|
1208 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
|
|
|
1209
|
|
|
1210 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
|
|
|
1211
|
|
|
1212 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
|
|
|
1213
|
|
|
1214 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
|
|
|
1215
|
|
|
1216 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
|
|
|
1217
|
|
|
1218 #if defined(SWPMI1)
|
|
|
1219 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
|
|
|
1220 #endif /* SWPMI1 */
|
|
|
1221
|
|
|
1222 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
|
|
|
1223
|
|
|
1224 /**
|
|
|
1225 * @}
|
|
|
1226 */
|
|
|
1227
|
|
|
1228 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
|
|
|
1229 * @brief Enable or disable the APB2 peripheral clock.
|
|
|
1230 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
1231 * is disabled and the application software has to enable this clock before
|
|
|
1232 * using it.
|
|
|
1233 * @{
|
|
|
1234 */
|
|
|
1235
|
|
|
1236 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
|
|
|
1237 __IO uint32_t tmpreg; \
|
|
|
1238 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
|
|
|
1239 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1240 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
|
|
|
1241 UNUSED(tmpreg); \
|
|
|
1242 } while(0)
|
|
|
1243
|
|
|
1244 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
|
|
|
1245 __IO uint32_t tmpreg; \
|
|
|
1246 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
|
|
|
1247 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1248 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
|
|
|
1249 UNUSED(tmpreg); \
|
|
|
1250 } while(0)
|
|
|
1251
|
|
|
1252 #if defined(SDMMC1)
|
|
|
1253 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
|
|
|
1254 __IO uint32_t tmpreg; \
|
|
|
1255 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
|
|
|
1256 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1257 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
|
|
|
1258 UNUSED(tmpreg); \
|
|
|
1259 } while(0)
|
|
|
1260 #endif /* SDMMC1 */
|
|
|
1261
|
|
|
1262 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
|
|
|
1263 __IO uint32_t tmpreg; \
|
|
|
1264 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
|
|
|
1265 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1266 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
|
|
|
1267 UNUSED(tmpreg); \
|
|
|
1268 } while(0)
|
|
|
1269
|
|
|
1270 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
|
|
|
1271 __IO uint32_t tmpreg; \
|
|
|
1272 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
|
|
|
1273 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1274 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
|
|
|
1275 UNUSED(tmpreg); \
|
|
|
1276 } while(0)
|
|
|
1277
|
|
|
1278 #if defined(TIM8)
|
|
|
1279 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
|
|
|
1280 __IO uint32_t tmpreg; \
|
|
|
1281 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
|
|
|
1282 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1283 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
|
|
|
1284 UNUSED(tmpreg); \
|
|
|
1285 } while(0)
|
|
|
1286 #endif /* TIM8 */
|
|
|
1287
|
|
|
1288 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
|
|
|
1289 __IO uint32_t tmpreg; \
|
|
|
1290 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
|
|
|
1291 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1292 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
|
|
|
1293 UNUSED(tmpreg); \
|
|
|
1294 } while(0)
|
|
|
1295
|
|
|
1296
|
|
|
1297 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
|
|
|
1298 __IO uint32_t tmpreg; \
|
|
|
1299 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
|
|
|
1300 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1301 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
|
|
|
1302 UNUSED(tmpreg); \
|
|
|
1303 } while(0)
|
|
|
1304
|
|
|
1305 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
|
|
|
1306 __IO uint32_t tmpreg; \
|
|
|
1307 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
|
|
|
1308 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1309 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
|
|
|
1310 UNUSED(tmpreg); \
|
|
|
1311 } while(0)
|
|
|
1312
|
|
|
1313 #if defined(TIM17)
|
|
|
1314 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
|
|
|
1315 __IO uint32_t tmpreg; \
|
|
|
1316 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
|
|
|
1317 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1318 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
|
|
|
1319 UNUSED(tmpreg); \
|
|
|
1320 } while(0)
|
|
|
1321 #endif /* TIM17 */
|
|
|
1322
|
|
|
1323 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
|
|
|
1324 __IO uint32_t tmpreg; \
|
|
|
1325 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
|
|
|
1326 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1327 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
|
|
|
1328 UNUSED(tmpreg); \
|
|
|
1329 } while(0)
|
|
|
1330
|
|
|
1331 #if defined(SAI2)
|
|
|
1332 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
|
|
|
1333 __IO uint32_t tmpreg; \
|
|
|
1334 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
|
|
|
1335 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1336 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
|
|
|
1337 UNUSED(tmpreg); \
|
|
|
1338 } while(0)
|
|
|
1339 #endif /* SAI2 */
|
|
|
1340
|
|
|
1341 #if defined(DFSDM1_Filter0)
|
|
|
1342 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
|
|
|
1343 __IO uint32_t tmpreg; \
|
|
|
1344 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
|
|
|
1345 /* Delay after an RCC peripheral clock enabling */ \
|
|
|
1346 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
|
|
|
1347 UNUSED(tmpreg); \
|
|
|
1348 } while(0)
|
|
|
1349 #endif /* DFSDM1_Filter0 */
|
|
|
1350
|
|
|
1351
|
|
|
1352 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
|
|
|
1353
|
|
|
1354 #if defined(SDMMC1)
|
|
|
1355 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
|
|
|
1356 #endif /* SDMMC1 */
|
|
|
1357
|
|
|
1358 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
|
|
|
1359
|
|
|
1360 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
|
|
|
1361
|
|
|
1362 #if defined(TIM8)
|
|
|
1363 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
|
|
|
1364 #endif /* TIM8 */
|
|
|
1365
|
|
|
1366 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
|
|
|
1367
|
|
|
1368 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
|
|
|
1369
|
|
|
1370 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
|
|
|
1371
|
|
|
1372 #if defined(TIM17)
|
|
|
1373 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
|
|
|
1374 #endif /* TIM17 */
|
|
|
1375
|
|
|
1376 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
|
|
|
1377
|
|
|
1378 #if defined(SAI2)
|
|
|
1379 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
|
|
|
1380 #endif /* SAI2 */
|
|
|
1381
|
|
|
1382 #if defined(DFSDM1_Filter0)
|
|
|
1383 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
|
|
|
1384 #endif /* DFSDM1_Filter0 */
|
|
|
1385
|
|
|
1386 /**
|
|
|
1387 * @}
|
|
|
1388 */
|
|
|
1389
|
|
|
1390 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
|
|
|
1391 * @brief Check whether the AHB1 peripheral clock is enabled or not.
|
|
|
1392 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
1393 * is disabled and the application software has to enable this clock before
|
|
|
1394 * using it.
|
|
|
1395 * @{
|
|
|
1396 */
|
|
|
1397
|
|
|
1398 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
|
|
|
1399
|
|
|
1400 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
|
|
|
1401
|
|
|
1402 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
|
|
|
1403
|
|
|
1404 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
|
|
|
1405
|
|
|
1406 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
|
|
|
1407
|
|
|
1408
|
|
|
1409 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
|
|
|
1410
|
|
|
1411 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
|
|
|
1412
|
|
|
1413 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
|
|
|
1414
|
|
|
1415 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
|
|
|
1416
|
|
|
1417 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
|
|
|
1418
|
|
|
1419 /**
|
|
|
1420 * @}
|
|
|
1421 */
|
|
|
1422
|
|
|
1423 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
|
|
|
1424 * @brief Check whether the AHB2 peripheral clock is enabled or not.
|
|
|
1425 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
1426 * is disabled and the application software has to enable this clock before
|
|
|
1427 * using it.
|
|
|
1428 * @{
|
|
|
1429 */
|
|
|
1430
|
|
|
1431 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
|
|
|
1432
|
|
|
1433 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
|
|
|
1434
|
|
|
1435 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
|
|
|
1436
|
|
|
1437 #if defined(GPIOD)
|
|
|
1438 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
|
|
|
1439 #endif /* GPIOD */
|
|
|
1440
|
|
|
1441 #if defined(GPIOE)
|
|
|
1442 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
|
|
|
1443 #endif /* GPIOE */
|
|
|
1444
|
|
|
1445 #if defined(GPIOF)
|
|
|
1446 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
|
|
|
1447 #endif /* GPIOF */
|
|
|
1448
|
|
|
1449 #if defined(GPIOG)
|
|
|
1450 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
|
|
|
1451 #endif /* GPIOG */
|
|
|
1452
|
|
|
1453 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
|
|
|
1454
|
|
|
1455 #if defined(USB_OTG_FS)
|
|
|
1456 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
|
|
|
1457 #endif /* USB_OTG_FS */
|
|
|
1458
|
|
|
1459 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
|
|
|
1460
|
|
|
1461 #if defined(AES)
|
|
|
1462 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
|
|
|
1463 #endif /* AES */
|
|
|
1464
|
|
|
1465 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
|
|
|
1466
|
|
|
1467
|
|
|
1468 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
|
|
|
1469
|
|
|
1470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
|
|
|
1471
|
|
|
1472 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
|
|
|
1473
|
|
|
1474 #if defined(GPIOD)
|
|
|
1475 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
|
|
|
1476 #endif /* GPIOD */
|
|
|
1477
|
|
|
1478 #if defined(GPIOE)
|
|
|
1479 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
|
|
|
1480 #endif /* GPIOE */
|
|
|
1481
|
|
|
1482 #if defined(GPIOF)
|
|
|
1483 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
|
|
|
1484 #endif /* GPIOF */
|
|
|
1485
|
|
|
1486 #if defined(GPIOG)
|
|
|
1487 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
|
|
|
1488 #endif /* GPIOG */
|
|
|
1489
|
|
|
1490 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
|
|
|
1491
|
|
|
1492 #if defined(USB_OTG_FS)
|
|
|
1493 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
|
|
|
1494 #endif /* USB_OTG_FS */
|
|
|
1495
|
|
|
1496 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
|
|
|
1497
|
|
|
1498 #if defined(AES)
|
|
|
1499 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
|
|
|
1500 #endif /* AES */
|
|
|
1501
|
|
|
1502 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
|
|
|
1503
|
|
|
1504 /**
|
|
|
1505 * @}
|
|
|
1506 */
|
|
|
1507
|
|
|
1508 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
|
|
|
1509 * @brief Check whether the AHB3 peripheral clock is enabled or not.
|
|
|
1510 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
1511 * is disabled and the application software has to enable this clock before
|
|
|
1512 * using it.
|
|
|
1513 * @{
|
|
|
1514 */
|
|
|
1515
|
|
|
1516 #if defined(FMC_BANK1)
|
|
|
1517 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
|
|
|
1518 #endif /* FMC_BANK1 */
|
|
|
1519
|
|
|
1520 #if defined(QUADSPI)
|
|
|
1521 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
|
|
|
1522 #endif /* QUADSPI */
|
|
|
1523
|
|
|
1524 #if defined(FMC_BANK1)
|
|
|
1525 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
|
|
|
1526 #endif /* FMC_BANK1 */
|
|
|
1527
|
|
|
1528 #if defined(QUADSPI)
|
|
|
1529 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
|
|
|
1530 #endif /* QUADSPI */
|
|
|
1531
|
|
|
1532 /**
|
|
|
1533 * @}
|
|
|
1534 */
|
|
|
1535
|
|
|
1536 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
|
|
|
1537 * @brief Check whether the APB1 peripheral clock is enabled or not.
|
|
|
1538 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
1539 * is disabled and the application software has to enable this clock before
|
|
|
1540 * using it.
|
|
|
1541 * @{
|
|
|
1542 */
|
|
|
1543
|
|
|
1544 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
|
|
|
1545
|
|
|
1546 #if defined(TIM3)
|
|
|
1547 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
|
|
|
1548 #endif /* TIM3 */
|
|
|
1549
|
|
|
1550 #if defined(TIM4)
|
|
|
1551 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
|
|
|
1552 #endif /* TIM4 */
|
|
|
1553
|
|
|
1554 #if defined(TIM5)
|
|
|
1555 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
|
|
|
1556 #endif /* TIM5 */
|
|
|
1557
|
|
|
1558 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
|
|
|
1559
|
|
|
1560 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
|
|
|
1561
|
|
|
1562 #if defined(LCD)
|
|
|
1563 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
|
|
|
1564 #endif /* LCD */
|
|
|
1565
|
|
|
1566 #if defined(RCC_APB1ENR1_RTCAPBEN)
|
|
|
1567 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET)
|
|
|
1568 #endif /* RCC_APB1ENR1_RTCAPBEN */
|
|
|
1569
|
|
|
1570 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
|
|
|
1571
|
|
|
1572 #if defined(SPI2)
|
|
|
1573 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
|
|
|
1574 #endif /* SPI2 */
|
|
|
1575
|
|
|
1576 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
|
|
|
1577
|
|
|
1578 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
|
|
|
1579
|
|
|
1580 #if defined(USART3)
|
|
|
1581 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
|
|
|
1582 #endif /* USART3 */
|
|
|
1583
|
|
|
1584 #if defined(UART4)
|
|
|
1585 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
|
|
|
1586 #endif /* UART4 */
|
|
|
1587
|
|
|
1588 #if defined(UART5)
|
|
|
1589 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
|
|
|
1590 #endif /* UART5 */
|
|
|
1591
|
|
|
1592 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
|
|
|
1593
|
|
|
1594 #if defined(I2C2)
|
|
|
1595 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
|
|
|
1596 #endif /* I2C2 */
|
|
|
1597
|
|
|
1598 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
|
|
|
1599
|
|
|
1600 #if defined(I2C4)
|
|
|
1601 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET)
|
|
|
1602 #endif /* I2C4 */
|
|
|
1603
|
|
|
1604 #if defined(CRS)
|
|
|
1605 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET)
|
|
|
1606 #endif /* CRS */
|
|
|
1607
|
|
|
1608 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
|
|
|
1609
|
|
|
1610 #if defined(USB)
|
|
|
1611 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET)
|
|
|
1612 #endif /* USB */
|
|
|
1613
|
|
|
1614 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
|
|
|
1615
|
|
|
1616 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
|
|
|
1617
|
|
|
1618 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
|
|
|
1619
|
|
|
1620 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
|
|
|
1621
|
|
|
1622 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
|
|
|
1623
|
|
|
1624 #if defined(SWPMI1)
|
|
|
1625 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
|
|
|
1626 #endif /* SWPMI1 */
|
|
|
1627
|
|
|
1628 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
|
|
|
1629
|
|
|
1630
|
|
|
1631 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
|
|
|
1632
|
|
|
1633 #if defined(TIM3)
|
|
|
1634 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
|
|
|
1635 #endif /* TIM3 */
|
|
|
1636
|
|
|
1637 #if defined(TIM4)
|
|
|
1638 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
|
|
|
1639 #endif /* TIM4 */
|
|
|
1640
|
|
|
1641 #if defined(TIM5)
|
|
|
1642 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
|
|
|
1643 #endif /* TIM5 */
|
|
|
1644
|
|
|
1645 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
|
|
|
1646
|
|
|
1647 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
|
|
|
1648
|
|
|
1649 #if defined(LCD)
|
|
|
1650 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
|
|
|
1651 #endif /* LCD */
|
|
|
1652
|
|
|
1653 #if defined(RCC_APB1ENR1_RTCAPBEN)
|
|
|
1654 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET)
|
|
|
1655 #endif /* RCC_APB1ENR1_RTCAPBEN */
|
|
|
1656
|
|
|
1657 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
|
|
|
1658
|
|
|
1659 #if defined(SPI2)
|
|
|
1660 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
|
|
|
1661 #endif /* SPI2 */
|
|
|
1662
|
|
|
1663 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
|
|
|
1664
|
|
|
1665 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
|
|
|
1666
|
|
|
1667 #if defined(USART3)
|
|
|
1668 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
|
|
|
1669 #endif /* USART3 */
|
|
|
1670
|
|
|
1671 #if defined(UART4)
|
|
|
1672 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
|
|
|
1673 #endif /* UART4 */
|
|
|
1674
|
|
|
1675 #if defined(UART5)
|
|
|
1676 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
|
|
|
1677 #endif /* UART5 */
|
|
|
1678
|
|
|
1679 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
|
|
|
1680
|
|
|
1681 #if defined(I2C2)
|
|
|
1682 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
|
|
|
1683 #endif /* I2C2 */
|
|
|
1684
|
|
|
1685 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
|
|
|
1686
|
|
|
1687 #if defined(I2C4)
|
|
|
1688 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET)
|
|
|
1689 #endif /* I2C4 */
|
|
|
1690
|
|
|
1691 #if defined(CRS)
|
|
|
1692 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET)
|
|
|
1693 #endif /* CRS */
|
|
|
1694
|
|
|
1695 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
|
|
|
1696
|
|
|
1697 #if defined(USB)
|
|
|
1698 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET)
|
|
|
1699 #endif /* USB */
|
|
|
1700
|
|
|
1701 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
|
|
|
1702
|
|
|
1703 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
|
|
|
1704
|
|
|
1705 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
|
|
|
1706
|
|
|
1707 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
|
|
|
1708
|
|
|
1709 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
|
|
|
1710
|
|
|
1711 #if defined(SWPMI1)
|
|
|
1712 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
|
|
|
1713 #endif /* SWPMI1 */
|
|
|
1714
|
|
|
1715 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
|
|
|
1716
|
|
|
1717 /**
|
|
|
1718 * @}
|
|
|
1719 */
|
|
|
1720
|
|
|
1721 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
|
|
|
1722 * @brief Check whether the APB2 peripheral clock is enabled or not.
|
|
|
1723 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
1724 * is disabled and the application software has to enable this clock before
|
|
|
1725 * using it.
|
|
|
1726 * @{
|
|
|
1727 */
|
|
|
1728
|
|
|
1729 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
|
|
|
1730
|
|
|
1731 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
|
|
|
1732
|
|
|
1733 #if defined(SDMMC1)
|
|
|
1734 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
|
|
|
1735 #endif /* SDMMC1 */
|
|
|
1736
|
|
|
1737 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
|
|
|
1738
|
|
|
1739 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
|
|
|
1740
|
|
|
1741 #if defined(TIM8)
|
|
|
1742 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
|
|
|
1743 #endif /* TIM8 */
|
|
|
1744
|
|
|
1745 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
|
|
|
1746
|
|
|
1747 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
|
|
|
1748
|
|
|
1749 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
|
|
|
1750
|
|
|
1751 #if defined(TIM17)
|
|
|
1752 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
|
|
|
1753 #endif /* TIM17 */
|
|
|
1754
|
|
|
1755 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
|
|
|
1756
|
|
|
1757 #if defined(SAI2)
|
|
|
1758 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
|
|
|
1759 #endif /* SAI2 */
|
|
|
1760
|
|
|
1761 #if defined(DFSDM1_Filter0)
|
|
|
1762 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
|
|
|
1763 #endif /* DFSDM1_Filter0 */
|
|
|
1764
|
|
|
1765
|
|
|
1766 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
|
|
|
1767
|
|
|
1768 #if defined(SDMMC1)
|
|
|
1769 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
|
|
|
1770 #endif /* SDMMC1 */
|
|
|
1771
|
|
|
1772 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
|
|
|
1773
|
|
|
1774 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
|
|
|
1775
|
|
|
1776 #if defined(TIM8)
|
|
|
1777 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
|
|
|
1778 #endif /* TIM8 */
|
|
|
1779
|
|
|
1780 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
|
|
|
1781
|
|
|
1782 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
|
|
|
1783
|
|
|
1784 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
|
|
|
1785
|
|
|
1786 #if defined(TIM17)
|
|
|
1787 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
|
|
|
1788 #endif /* TIM17 */
|
|
|
1789
|
|
|
1790 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
|
|
|
1791
|
|
|
1792 #if defined(SAI2)
|
|
|
1793 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
|
|
|
1794 #endif /* SAI2 */
|
|
|
1795
|
|
|
1796 #if defined(DFSDM1_Filter0)
|
|
|
1797 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
|
|
|
1798 #endif /* DFSDM1_Filter0 */
|
|
|
1799
|
|
|
1800 /**
|
|
|
1801 * @}
|
|
|
1802 */
|
|
|
1803
|
|
|
1804 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
|
|
|
1805 * @brief Force or release AHB1 peripheral reset.
|
|
|
1806 * @{
|
|
|
1807 */
|
|
|
1808 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
|
|
|
1809
|
|
|
1810 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
|
|
|
1811
|
|
|
1812 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
|
|
|
1813
|
|
|
1814 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
|
|
|
1815
|
|
|
1816 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
|
|
|
1817
|
|
|
1818 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
|
|
|
1819
|
|
|
1820
|
|
|
1821 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
|
|
|
1822
|
|
|
1823 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
|
|
|
1824
|
|
|
1825 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
|
|
|
1826
|
|
|
1827 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
|
|
|
1828
|
|
|
1829 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
|
|
|
1830
|
|
|
1831 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
|
|
|
1832
|
|
|
1833 /**
|
|
|
1834 * @}
|
|
|
1835 */
|
|
|
1836
|
|
|
1837 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
|
|
|
1838 * @brief Force or release AHB2 peripheral reset.
|
|
|
1839 * @{
|
|
|
1840 */
|
|
|
1841 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
|
|
|
1842
|
|
|
1843 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
|
|
|
1844
|
|
|
1845 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
|
|
|
1846
|
|
|
1847 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
|
|
|
1848
|
|
|
1849 #if defined(GPIOD)
|
|
|
1850 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
|
|
|
1851 #endif /* GPIOD */
|
|
|
1852
|
|
|
1853 #if defined(GPIOE)
|
|
|
1854 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
|
|
|
1855 #endif /* GPIOE */
|
|
|
1856
|
|
|
1857 #if defined(GPIOF)
|
|
|
1858 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
|
|
|
1859 #endif /* GPIOF */
|
|
|
1860
|
|
|
1861 #if defined(GPIOG)
|
|
|
1862 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
|
|
|
1863 #endif /* GPIOG */
|
|
|
1864
|
|
|
1865 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
|
|
|
1866
|
|
|
1867 #if defined(USB_OTG_FS)
|
|
|
1868 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
|
|
|
1869 #endif /* USB_OTG_FS */
|
|
|
1870
|
|
|
1871 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
|
|
|
1872
|
|
|
1873 #if defined(AES)
|
|
|
1874 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
|
|
|
1875 #endif /* AES */
|
|
|
1876
|
|
|
1877 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
|
|
|
1878
|
|
|
1879
|
|
|
1880 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
|
|
|
1881
|
|
|
1882 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
|
|
|
1883
|
|
|
1884 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
|
|
|
1885
|
|
|
1886 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
|
|
|
1887
|
|
|
1888 #if defined(GPIOD)
|
|
|
1889 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
|
|
|
1890 #endif /* GPIOD */
|
|
|
1891
|
|
|
1892 #if defined(GPIOE)
|
|
|
1893 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
|
|
|
1894 #endif /* GPIOE */
|
|
|
1895
|
|
|
1896 #if defined(GPIOF)
|
|
|
1897 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
|
|
|
1898 #endif /* GPIOF */
|
|
|
1899
|
|
|
1900 #if defined(GPIOG)
|
|
|
1901 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
|
|
|
1902 #endif /* GPIOG */
|
|
|
1903
|
|
|
1904 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
|
|
|
1905
|
|
|
1906 #if defined(USB_OTG_FS)
|
|
|
1907 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
|
|
|
1908 #endif /* USB_OTG_FS */
|
|
|
1909
|
|
|
1910 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
|
|
|
1911
|
|
|
1912 #if defined(AES)
|
|
|
1913 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
|
|
|
1914 #endif /* AES */
|
|
|
1915
|
|
|
1916 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
|
|
|
1917
|
|
|
1918 /**
|
|
|
1919 * @}
|
|
|
1920 */
|
|
|
1921
|
|
|
1922 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
|
|
|
1923 * @brief Force or release AHB3 peripheral reset.
|
|
|
1924 * @{
|
|
|
1925 */
|
|
|
1926 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
|
|
|
1927
|
|
|
1928 #if defined(FMC_BANK1)
|
|
|
1929 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
|
|
|
1930 #endif /* FMC_BANK1 */
|
|
|
1931
|
|
|
1932 #if defined(QUADSPI)
|
|
|
1933 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
|
|
|
1934 #endif /* QUADSPI */
|
|
|
1935
|
|
|
1936 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
|
|
|
1937
|
|
|
1938 #if defined(FMC_BANK1)
|
|
|
1939 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
|
|
|
1940 #endif /* FMC_BANK1 */
|
|
|
1941
|
|
|
1942 #if defined(QUADSPI)
|
|
|
1943 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
|
|
|
1944 #endif /* QUADSPI */
|
|
|
1945
|
|
|
1946 /**
|
|
|
1947 * @}
|
|
|
1948 */
|
|
|
1949
|
|
|
1950 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
|
|
|
1951 * @brief Force or release APB1 peripheral reset.
|
|
|
1952 * @{
|
|
|
1953 */
|
|
|
1954 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
|
|
|
1955
|
|
|
1956 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
|
|
|
1957
|
|
|
1958 #if defined(TIM3)
|
|
|
1959 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
|
|
|
1960 #endif /* TIM3 */
|
|
|
1961
|
|
|
1962 #if defined(TIM4)
|
|
|
1963 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
|
|
|
1964 #endif /* TIM4 */
|
|
|
1965
|
|
|
1966 #if defined(TIM5)
|
|
|
1967 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
|
|
|
1968 #endif /* TIM5 */
|
|
|
1969
|
|
|
1970 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
|
|
|
1971
|
|
|
1972 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
|
|
|
1973
|
|
|
1974 #if defined(LCD)
|
|
|
1975 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
|
|
|
1976 #endif /* LCD */
|
|
|
1977
|
|
|
1978 #if defined(SPI2)
|
|
|
1979 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
|
|
|
1980 #endif /* SPI2 */
|
|
|
1981
|
|
|
1982 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
|
|
|
1983
|
|
|
1984 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
|
|
|
1985
|
|
|
1986 #if defined(USART3)
|
|
|
1987 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
|
|
|
1988 #endif /* USART3 */
|
|
|
1989
|
|
|
1990 #if defined(UART4)
|
|
|
1991 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
|
|
|
1992 #endif /* UART4 */
|
|
|
1993
|
|
|
1994 #if defined(UART5)
|
|
|
1995 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
|
|
|
1996 #endif /* UART5 */
|
|
|
1997
|
|
|
1998 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
|
|
|
1999
|
|
|
2000 #if defined(I2C2)
|
|
|
2001 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
|
|
|
2002 #endif /* I2C2 */
|
|
|
2003
|
|
|
2004 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
|
|
|
2005
|
|
|
2006 #if defined(I2C4)
|
|
|
2007 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
|
|
|
2008 #endif /* I2C4 */
|
|
|
2009
|
|
|
2010 #if defined(CRS)
|
|
|
2011 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
|
|
|
2012 #endif /* CRS */
|
|
|
2013
|
|
|
2014 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
|
|
|
2015
|
|
|
2016 #if defined(USB)
|
|
|
2017 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
|
|
|
2018 #endif /* USB */
|
|
|
2019
|
|
|
2020 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
|
|
|
2021
|
|
|
2022 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
|
|
|
2023
|
|
|
2024 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
|
|
|
2025
|
|
|
2026 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
|
|
|
2027
|
|
|
2028 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
|
|
|
2029
|
|
|
2030 #if defined(SWPMI1)
|
|
|
2031 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
|
|
|
2032 #endif /* SWPMI1 */
|
|
|
2033
|
|
|
2034 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
|
|
|
2035
|
|
|
2036
|
|
|
2037 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
|
|
|
2038
|
|
|
2039 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
|
|
|
2040
|
|
|
2041 #if defined(TIM3)
|
|
|
2042 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
|
|
|
2043 #endif /* TIM3 */
|
|
|
2044
|
|
|
2045 #if defined(TIM4)
|
|
|
2046 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
|
|
|
2047 #endif /* TIM4 */
|
|
|
2048
|
|
|
2049 #if defined(TIM5)
|
|
|
2050 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
|
|
|
2051 #endif /* TIM5 */
|
|
|
2052
|
|
|
2053 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
|
|
|
2054
|
|
|
2055 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
|
|
|
2056
|
|
|
2057 #if defined(LCD)
|
|
|
2058 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
|
|
|
2059 #endif /* LCD */
|
|
|
2060
|
|
|
2061 #if defined(SPI2)
|
|
|
2062 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
|
|
|
2063 #endif /* SPI2 */
|
|
|
2064
|
|
|
2065 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
|
|
|
2066
|
|
|
2067 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
|
|
|
2068
|
|
|
2069 #if defined(USART3)
|
|
|
2070 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
|
|
|
2071 #endif /* USART3 */
|
|
|
2072
|
|
|
2073 #if defined(UART4)
|
|
|
2074 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
|
|
|
2075 #endif /* UART4 */
|
|
|
2076
|
|
|
2077 #if defined(UART5)
|
|
|
2078 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
|
|
|
2079 #endif /* UART5 */
|
|
|
2080
|
|
|
2081 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
|
|
|
2082
|
|
|
2083 #if defined(I2C2)
|
|
|
2084 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
|
|
|
2085 #endif /* I2C2 */
|
|
|
2086
|
|
|
2087 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
|
|
|
2088
|
|
|
2089 #if defined(I2C4)
|
|
|
2090 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
|
|
|
2091 #endif /* I2C4 */
|
|
|
2092
|
|
|
2093 #if defined(CRS)
|
|
|
2094 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
|
|
|
2095 #endif /* CRS */
|
|
|
2096
|
|
|
2097 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
|
|
|
2098
|
|
|
2099 #if defined(USB)
|
|
|
2100 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
|
|
|
2101 #endif /* USB */
|
|
|
2102
|
|
|
2103 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
|
|
|
2104
|
|
|
2105 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
|
|
|
2106
|
|
|
2107 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
|
|
|
2108
|
|
|
2109 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
|
|
|
2110
|
|
|
2111 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
|
|
|
2112
|
|
|
2113 #if defined(SWPMI1)
|
|
|
2114 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
|
|
|
2115 #endif /* SWPMI1 */
|
|
|
2116
|
|
|
2117 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
|
|
|
2118
|
|
|
2119 /**
|
|
|
2120 * @}
|
|
|
2121 */
|
|
|
2122
|
|
|
2123 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
|
|
|
2124 * @brief Force or release APB2 peripheral reset.
|
|
|
2125 * @{
|
|
|
2126 */
|
|
|
2127 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
|
|
|
2128
|
|
|
2129 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
|
|
|
2130
|
|
|
2131 #if defined(SDMMC1)
|
|
|
2132 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
|
|
|
2133 #endif /* SDMMC1 */
|
|
|
2134
|
|
|
2135 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
|
|
|
2136
|
|
|
2137 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
|
|
|
2138
|
|
|
2139 #if defined(TIM8)
|
|
|
2140 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
|
|
|
2141 #endif /* TIM8 */
|
|
|
2142
|
|
|
2143 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
|
|
|
2144
|
|
|
2145 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
|
|
|
2146
|
|
|
2147 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
|
|
|
2148
|
|
|
2149 #if defined(TIM17)
|
|
|
2150 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
|
|
|
2151 #endif /* TIM17 */
|
|
|
2152
|
|
|
2153 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
|
|
|
2154
|
|
|
2155 #if defined(SAI2)
|
|
|
2156 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
|
|
|
2157 #endif /* SAI2 */
|
|
|
2158
|
|
|
2159 #if defined(DFSDM1_Filter0)
|
|
|
2160 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
|
|
|
2161 #endif /* DFSDM1_Filter0 */
|
|
|
2162
|
|
|
2163
|
|
|
2164 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
|
|
|
2165
|
|
|
2166 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
|
|
|
2167
|
|
|
2168 #if defined(SDMMC1)
|
|
|
2169 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
|
|
|
2170 #endif /* SDMMC1 */
|
|
|
2171
|
|
|
2172 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
|
|
|
2173
|
|
|
2174 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
|
|
|
2175
|
|
|
2176 #if defined(TIM8)
|
|
|
2177 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
|
|
|
2178 #endif /* TIM8 */
|
|
|
2179
|
|
|
2180 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
|
|
|
2181
|
|
|
2182 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
|
|
|
2183
|
|
|
2184 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
|
|
|
2185
|
|
|
2186 #if defined(TIM17)
|
|
|
2187 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
|
|
|
2188 #endif /* TIM17 */
|
|
|
2189
|
|
|
2190 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
|
|
|
2191
|
|
|
2192 #if defined(SAI2)
|
|
|
2193 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
|
|
|
2194 #endif /* SAI2 */
|
|
|
2195
|
|
|
2196 #if defined(DFSDM1_Filter0)
|
|
|
2197 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
|
|
|
2198 #endif /* DFSDM1_Filter0 */
|
|
|
2199
|
|
|
2200 /**
|
|
|
2201 * @}
|
|
|
2202 */
|
|
|
2203
|
|
|
2204 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
|
|
|
2205 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
|
|
|
2206 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2207 * power consumption.
|
|
|
2208 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2209 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2210 * @{
|
|
|
2211 */
|
|
|
2212
|
|
|
2213 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
|
|
|
2214
|
|
|
2215 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
|
|
|
2216
|
|
|
2217 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
|
|
|
2218
|
|
|
2219 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
|
|
|
2220
|
|
|
2221 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
|
|
|
2222
|
|
|
2223 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
|
|
|
2224
|
|
|
2225
|
|
|
2226 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
|
|
|
2227
|
|
|
2228 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
|
|
|
2229
|
|
|
2230 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
|
|
|
2231
|
|
|
2232 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
|
|
|
2233
|
|
|
2234 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
|
|
|
2235
|
|
|
2236 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
|
|
|
2237
|
|
|
2238 /**
|
|
|
2239 * @}
|
|
|
2240 */
|
|
|
2241
|
|
|
2242 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
|
|
|
2243 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
|
|
|
2244 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2245 * power consumption.
|
|
|
2246 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2247 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2248 * @{
|
|
|
2249 */
|
|
|
2250
|
|
|
2251 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
|
|
|
2252
|
|
|
2253 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
|
|
|
2254
|
|
|
2255 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
|
|
|
2256
|
|
|
2257 #if defined(GPIOD)
|
|
|
2258 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
|
|
|
2259 #endif /* GPIOD */
|
|
|
2260
|
|
|
2261 #if defined(GPIOE)
|
|
|
2262 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
|
|
|
2263 #endif /* GPIOE */
|
|
|
2264
|
|
|
2265 #if defined(GPIOF)
|
|
|
2266 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
|
|
|
2267 #endif /* GPIOF */
|
|
|
2268
|
|
|
2269 #if defined(GPIOG)
|
|
|
2270 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
|
|
|
2271 #endif /* GPIOG */
|
|
|
2272
|
|
|
2273 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
|
|
|
2274
|
|
|
2275 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
|
|
|
2276
|
|
|
2277 #if defined(USB_OTG_FS)
|
|
|
2278 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
|
|
|
2279 #endif /* USB_OTG_FS */
|
|
|
2280
|
|
|
2281 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
|
|
|
2282
|
|
|
2283 #if defined(AES)
|
|
|
2284 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
|
|
|
2285 #endif /* AES */
|
|
|
2286
|
|
|
2287 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
|
|
|
2288
|
|
|
2289
|
|
|
2290 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
|
|
|
2291
|
|
|
2292 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
|
|
|
2293
|
|
|
2294 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
|
|
|
2295
|
|
|
2296 #if defined(GPIOD)
|
|
|
2297 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
|
|
|
2298 #endif /* GPIOD */
|
|
|
2299
|
|
|
2300 #if defined(GPIOE)
|
|
|
2301 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
|
|
|
2302 #endif /* GPIOE */
|
|
|
2303
|
|
|
2304 #if defined(GPIOF)
|
|
|
2305 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
|
|
|
2306 #endif /* GPIOF */
|
|
|
2307
|
|
|
2308 #if defined(GPIOG)
|
|
|
2309 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
|
|
|
2310 #endif /* GPIOG */
|
|
|
2311
|
|
|
2312 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
|
|
|
2313
|
|
|
2314 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
|
|
|
2315
|
|
|
2316 #if defined(USB_OTG_FS)
|
|
|
2317 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
|
|
|
2318 #endif /* USB_OTG_FS */
|
|
|
2319
|
|
|
2320 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
|
|
|
2321
|
|
|
2322 #if defined(AES)
|
|
|
2323 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
|
|
|
2324 #endif /* AES */
|
|
|
2325
|
|
|
2326 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
|
|
|
2327
|
|
|
2328 /**
|
|
|
2329 * @}
|
|
|
2330 */
|
|
|
2331
|
|
|
2332 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
|
|
|
2333 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
|
|
|
2334 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2335 * power consumption.
|
|
|
2336 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2337 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2338 * @{
|
|
|
2339 */
|
|
|
2340
|
|
|
2341 #if defined(QUADSPI)
|
|
|
2342 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
|
|
|
2343 #endif /* QUADSPI */
|
|
|
2344
|
|
|
2345 #if defined(FMC_BANK1)
|
|
|
2346 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
|
|
|
2347 #endif /* FMC_BANK1 */
|
|
|
2348
|
|
|
2349 #if defined(QUADSPI)
|
|
|
2350 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
|
|
|
2351 #endif /* QUADSPI */
|
|
|
2352
|
|
|
2353 #if defined(FMC_BANK1)
|
|
|
2354 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
|
|
|
2355 #endif /* FMC_BANK1 */
|
|
|
2356
|
|
|
2357 /**
|
|
|
2358 * @}
|
|
|
2359 */
|
|
|
2360
|
|
|
2361 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
|
|
|
2362 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
|
|
|
2363 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2364 * power consumption.
|
|
|
2365 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2366 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2367 * @{
|
|
|
2368 */
|
|
|
2369
|
|
|
2370 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
|
|
|
2371
|
|
|
2372 #if defined(TIM3)
|
|
|
2373 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
|
|
|
2374 #endif /* TIM3 */
|
|
|
2375
|
|
|
2376 #if defined(TIM4)
|
|
|
2377 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
|
|
|
2378 #endif /* TIM4 */
|
|
|
2379
|
|
|
2380 #if defined(TIM5)
|
|
|
2381 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
|
|
|
2382 #endif /* TIM5 */
|
|
|
2383
|
|
|
2384 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
|
|
|
2385
|
|
|
2386 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
|
|
|
2387
|
|
|
2388 #if defined(LCD)
|
|
|
2389 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
|
|
|
2390 #endif /* LCD */
|
|
|
2391
|
|
|
2392 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
|
|
|
2393 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
|
|
|
2394 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
|
|
|
2395
|
|
|
2396 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
|
|
|
2397
|
|
|
2398 #if defined(SPI2)
|
|
|
2399 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
|
|
|
2400 #endif /* SPI2 */
|
|
|
2401
|
|
|
2402 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
|
|
|
2403
|
|
|
2404 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
|
|
|
2405
|
|
|
2406 #if defined(USART3)
|
|
|
2407 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
|
|
|
2408 #endif /* USART3 */
|
|
|
2409
|
|
|
2410 #if defined(UART4)
|
|
|
2411 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
|
|
|
2412 #endif /* UART4 */
|
|
|
2413
|
|
|
2414 #if defined(UART5)
|
|
|
2415 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
|
|
|
2416 #endif /* UART5 */
|
|
|
2417
|
|
|
2418 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
|
|
|
2419
|
|
|
2420 #if defined(I2C2)
|
|
|
2421 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
|
|
|
2422 #endif /* I2C2 */
|
|
|
2423
|
|
|
2424 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
|
|
|
2425
|
|
|
2426 #if defined(I2C4)
|
|
|
2427 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
|
|
|
2428 #endif /* I2C4 */
|
|
|
2429
|
|
|
2430 #if defined(CRS)
|
|
|
2431 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
|
|
|
2432 #endif /* CRS */
|
|
|
2433
|
|
|
2434 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
|
|
|
2435
|
|
|
2436 #if defined(USB)
|
|
|
2437 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
|
|
|
2438 #endif /* USB */
|
|
|
2439
|
|
|
2440 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
|
|
|
2441
|
|
|
2442 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
|
|
|
2443
|
|
|
2444 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
|
|
|
2445
|
|
|
2446 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
|
|
|
2447
|
|
|
2448 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
|
|
|
2449
|
|
|
2450 #if defined(SWPMI1)
|
|
|
2451 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
|
|
|
2452 #endif /* SWPMI1 */
|
|
|
2453
|
|
|
2454 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
|
|
|
2455
|
|
|
2456
|
|
|
2457 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
|
|
|
2458
|
|
|
2459 #if defined(TIM3)
|
|
|
2460 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
|
|
|
2461 #endif /* TIM3 */
|
|
|
2462
|
|
|
2463 #if defined(TIM4)
|
|
|
2464 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
|
|
|
2465 #endif /* TIM4 */
|
|
|
2466
|
|
|
2467 #if defined(TIM5)
|
|
|
2468 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
|
|
|
2469 #endif /* TIM5 */
|
|
|
2470
|
|
|
2471 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
|
|
|
2472
|
|
|
2473 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
|
|
|
2474
|
|
|
2475 #if defined(LCD)
|
|
|
2476 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
|
|
|
2477 #endif /* LCD */
|
|
|
2478
|
|
|
2479 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
|
|
|
2480 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
|
|
|
2481 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
|
|
|
2482
|
|
|
2483 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
|
|
|
2484
|
|
|
2485 #if defined(SPI2)
|
|
|
2486 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
|
|
|
2487 #endif /* SPI2 */
|
|
|
2488
|
|
|
2489 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
|
|
|
2490
|
|
|
2491 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
|
|
|
2492
|
|
|
2493 #if defined(USART3)
|
|
|
2494 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
|
|
|
2495 #endif /* USART3 */
|
|
|
2496
|
|
|
2497 #if defined(UART4)
|
|
|
2498 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
|
|
|
2499 #endif /* UART4 */
|
|
|
2500
|
|
|
2501 #if defined(UART5)
|
|
|
2502 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
|
|
|
2503 #endif /* UART5 */
|
|
|
2504
|
|
|
2505 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
|
|
|
2506
|
|
|
2507 #if defined(I2C2)
|
|
|
2508 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
|
|
|
2509 #endif /* I2C2 */
|
|
|
2510
|
|
|
2511 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
|
|
|
2512
|
|
|
2513 #if defined(I2C4)
|
|
|
2514 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
|
|
|
2515 #endif /* I2C4 */
|
|
|
2516
|
|
|
2517 #if defined(CRS)
|
|
|
2518 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
|
|
|
2519 #endif /* CRS */
|
|
|
2520
|
|
|
2521 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
|
|
|
2522
|
|
|
2523 #if defined(USB)
|
|
|
2524 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
|
|
|
2525 #endif /* USB */
|
|
|
2526
|
|
|
2527 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
|
|
|
2528
|
|
|
2529 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
|
|
|
2530
|
|
|
2531 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
|
|
|
2532
|
|
|
2533 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
|
|
|
2534
|
|
|
2535 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
|
|
|
2536
|
|
|
2537 #if defined(SWPMI1)
|
|
|
2538 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
|
|
|
2539 #endif /* SWPMI1 */
|
|
|
2540
|
|
|
2541 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
|
|
|
2542
|
|
|
2543 /**
|
|
|
2544 * @}
|
|
|
2545 */
|
|
|
2546
|
|
|
2547 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
|
|
|
2548 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
|
|
|
2549 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2550 * power consumption.
|
|
|
2551 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2552 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2553 * @{
|
|
|
2554 */
|
|
|
2555
|
|
|
2556 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
|
|
|
2557
|
|
|
2558 #if defined(SDMMC1)
|
|
|
2559 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
|
|
|
2560 #endif /* SDMMC1 */
|
|
|
2561
|
|
|
2562 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
|
|
|
2563
|
|
|
2564 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
|
|
|
2565
|
|
|
2566 #if defined(TIM8)
|
|
|
2567 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
|
|
|
2568 #endif /* TIM8 */
|
|
|
2569
|
|
|
2570 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
|
|
|
2571
|
|
|
2572 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
|
|
|
2573
|
|
|
2574 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
|
|
|
2575
|
|
|
2576 #if defined(TIM17)
|
|
|
2577 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
|
|
|
2578 #endif /* TIM17 */
|
|
|
2579
|
|
|
2580 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
|
|
|
2581
|
|
|
2582 #if defined(SAI2)
|
|
|
2583 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
|
|
|
2584 #endif /* SAI2 */
|
|
|
2585
|
|
|
2586 #if defined(DFSDM1_Filter0)
|
|
|
2587 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
|
|
|
2588 #endif /* DFSDM1_Filter0 */
|
|
|
2589
|
|
|
2590
|
|
|
2591 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
|
|
|
2592
|
|
|
2593 #if defined(SDMMC1)
|
|
|
2594 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
|
|
|
2595 #endif /* SDMMC1 */
|
|
|
2596
|
|
|
2597 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
|
|
|
2598
|
|
|
2599 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
|
|
|
2600
|
|
|
2601 #if defined(TIM8)
|
|
|
2602 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
|
|
|
2603 #endif /* TIM8 */
|
|
|
2604
|
|
|
2605 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
|
|
|
2606
|
|
|
2607 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
|
|
|
2608
|
|
|
2609 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
|
|
|
2610
|
|
|
2611 #if defined(TIM17)
|
|
|
2612 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
|
|
|
2613 #endif /* TIM17 */
|
|
|
2614
|
|
|
2615 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
|
|
|
2616
|
|
|
2617 #if defined(SAI2)
|
|
|
2618 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
|
|
|
2619 #endif /* SAI2 */
|
|
|
2620
|
|
|
2621 #if defined(DFSDM1_Filter0)
|
|
|
2622 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
|
|
|
2623 #endif /* DFSDM1_Filter0 */
|
|
|
2624
|
|
|
2625 /**
|
|
|
2626 * @}
|
|
|
2627 */
|
|
|
2628
|
|
|
2629 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
|
|
|
2630 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
|
|
2631 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2632 * power consumption.
|
|
|
2633 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2634 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2635 * @{
|
|
|
2636 */
|
|
|
2637
|
|
|
2638 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
|
|
|
2639
|
|
|
2640 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
|
|
|
2641
|
|
|
2642 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
|
|
|
2643
|
|
|
2644 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
|
|
|
2645
|
|
|
2646 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
|
|
|
2647
|
|
|
2648 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
|
|
|
2649
|
|
|
2650
|
|
|
2651 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
|
|
|
2652
|
|
|
2653 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
|
|
|
2654
|
|
|
2655 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
|
|
|
2656
|
|
|
2657 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
|
|
|
2658
|
|
|
2659 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
|
|
|
2660
|
|
|
2661 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
|
|
|
2662
|
|
|
2663 /**
|
|
|
2664 * @}
|
|
|
2665 */
|
|
|
2666
|
|
|
2667 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
|
|
|
2668 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
|
|
2669 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2670 * power consumption.
|
|
|
2671 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2672 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2673 * @{
|
|
|
2674 */
|
|
|
2675
|
|
|
2676 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
|
|
|
2677
|
|
|
2678 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
|
|
|
2679
|
|
|
2680 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
|
|
|
2681
|
|
|
2682 #if defined(GPIOD)
|
|
|
2683 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
|
|
|
2684 #endif /* GPIOD */
|
|
|
2685
|
|
|
2686 #if defined(GPIOE)
|
|
|
2687 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
|
|
|
2688 #endif /* GPIOE */
|
|
|
2689
|
|
|
2690 #if defined(GPIOF)
|
|
|
2691 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
|
|
|
2692 #endif /* GPIOF */
|
|
|
2693
|
|
|
2694 #if defined(GPIOG)
|
|
|
2695 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
|
|
|
2696 #endif /* GPIOG */
|
|
|
2697
|
|
|
2698 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
|
|
|
2699
|
|
|
2700 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
|
|
|
2701
|
|
|
2702 #if defined(USB_OTG_FS)
|
|
|
2703 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
|
|
|
2704 #endif /* USB_OTG_FS */
|
|
|
2705
|
|
|
2706 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
|
|
|
2707
|
|
|
2708 #if defined(AES)
|
|
|
2709 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
|
|
|
2710 #endif /* AES */
|
|
|
2711
|
|
|
2712 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
|
|
|
2713
|
|
|
2714
|
|
|
2715 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
|
|
|
2716
|
|
|
2717 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
|
|
|
2718
|
|
|
2719 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
|
|
|
2720
|
|
|
2721 #if defined(GPIOD)
|
|
|
2722 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
|
|
|
2723 #endif /* GPIOD */
|
|
|
2724
|
|
|
2725 #if defined(GPIOE)
|
|
|
2726 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
|
|
|
2727 #endif /* GPIOE */
|
|
|
2728
|
|
|
2729 #if defined(GPIOF)
|
|
|
2730 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
|
|
|
2731 #endif /* GPIOF */
|
|
|
2732
|
|
|
2733 #if defined(GPIOG)
|
|
|
2734 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
|
|
|
2735 #endif /* GPIOG */
|
|
|
2736
|
|
|
2737 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
|
|
|
2738
|
|
|
2739 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
|
|
|
2740
|
|
|
2741 #if defined(USB_OTG_FS)
|
|
|
2742 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
|
|
|
2743 #endif /* USB_OTG_FS */
|
|
|
2744
|
|
|
2745 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
|
|
|
2746
|
|
|
2747 #if defined(AES)
|
|
|
2748 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
|
|
|
2749 #endif /* AES */
|
|
|
2750
|
|
|
2751 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
|
|
|
2752
|
|
|
2753 /**
|
|
|
2754 * @}
|
|
|
2755 */
|
|
|
2756
|
|
|
2757 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
|
|
|
2758 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
|
|
2759 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2760 * power consumption.
|
|
|
2761 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2762 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2763 * @{
|
|
|
2764 */
|
|
|
2765
|
|
|
2766 #if defined(QUADSPI)
|
|
|
2767 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
|
|
|
2768 #endif /* QUADSPI */
|
|
|
2769
|
|
|
2770 #if defined(FMC_BANK1)
|
|
|
2771 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
|
|
|
2772 #endif /* FMC_BANK1 */
|
|
|
2773
|
|
|
2774 #if defined(QUADSPI)
|
|
|
2775 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
|
|
|
2776 #endif /* QUADSPI */
|
|
|
2777
|
|
|
2778 #if defined(FMC_BANK1)
|
|
|
2779 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
|
|
|
2780 #endif /* FMC_BANK1 */
|
|
|
2781
|
|
|
2782 /**
|
|
|
2783 * @}
|
|
|
2784 */
|
|
|
2785
|
|
|
2786 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
|
|
|
2787 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
|
|
2788 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2789 * power consumption.
|
|
|
2790 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2791 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2792 * @{
|
|
|
2793 */
|
|
|
2794
|
|
|
2795 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
|
|
|
2796
|
|
|
2797 #if defined(TIM3)
|
|
|
2798 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
|
|
|
2799 #endif /* TIM3 */
|
|
|
2800
|
|
|
2801 #if defined(TIM4)
|
|
|
2802 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
|
|
|
2803 #endif /* TIM4 */
|
|
|
2804
|
|
|
2805 #if defined(TIM5)
|
|
|
2806 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
|
|
|
2807 #endif /* TIM5 */
|
|
|
2808
|
|
|
2809 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
|
|
|
2810
|
|
|
2811 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
|
|
|
2812
|
|
|
2813 #if defined(LCD)
|
|
|
2814 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
|
|
|
2815 #endif /* LCD */
|
|
|
2816
|
|
|
2817 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
|
|
|
2818 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
|
|
|
2819 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
|
|
|
2820
|
|
|
2821 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
|
|
|
2822
|
|
|
2823 #if defined(SPI2)
|
|
|
2824 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
|
|
|
2825 #endif /* SPI2 */
|
|
|
2826
|
|
|
2827 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
|
|
|
2828
|
|
|
2829 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
|
|
|
2830
|
|
|
2831 #if defined(USART3)
|
|
|
2832 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
|
|
|
2833 #endif /* USART3 */
|
|
|
2834
|
|
|
2835 #if defined(UART4)
|
|
|
2836 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
|
|
|
2837 #endif /* UART4 */
|
|
|
2838
|
|
|
2839 #if defined(UART5)
|
|
|
2840 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
|
|
|
2841 #endif /* UART5 */
|
|
|
2842
|
|
|
2843 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
|
|
|
2844
|
|
|
2845 #if defined(I2C2)
|
|
|
2846 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
|
|
|
2847 #endif /* I2C2 */
|
|
|
2848
|
|
|
2849 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
|
|
|
2850
|
|
|
2851 #if defined(I2C4)
|
|
|
2852 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET)
|
|
|
2853 #endif /* I2C4 */
|
|
|
2854
|
|
|
2855 #if defined(CRS)
|
|
|
2856 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
|
|
|
2857 #endif /* CRS */
|
|
|
2858
|
|
|
2859 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
|
|
|
2860
|
|
|
2861 #if defined(USB)
|
|
|
2862 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET)
|
|
|
2863 #endif /* USB */
|
|
|
2864
|
|
|
2865 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
|
|
|
2866
|
|
|
2867 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
|
|
|
2868
|
|
|
2869 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
|
|
|
2870
|
|
|
2871 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
|
|
|
2872
|
|
|
2873 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
|
|
|
2874
|
|
|
2875 #if defined(SWPMI1)
|
|
|
2876 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
|
|
|
2877 #endif /* SWPMI1 */
|
|
|
2878
|
|
|
2879 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
|
|
|
2880
|
|
|
2881
|
|
|
2882 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
|
|
|
2883
|
|
|
2884 #if defined(TIM3)
|
|
|
2885 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
|
|
|
2886 #endif /* TIM3 */
|
|
|
2887
|
|
|
2888 #if defined(TIM4)
|
|
|
2889 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
|
|
|
2890 #endif /* TIM4 */
|
|
|
2891
|
|
|
2892 #if defined(TIM5)
|
|
|
2893 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
|
|
|
2894 #endif /* TIM5 */
|
|
|
2895
|
|
|
2896 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
|
|
|
2897
|
|
|
2898 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
|
|
|
2899
|
|
|
2900 #if defined(LCD)
|
|
|
2901 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
|
|
|
2902 #endif /* LCD */
|
|
|
2903
|
|
|
2904 #if defined(RCC_APB1SMENR1_RTCAPBSMEN)
|
|
|
2905 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
|
|
|
2906 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */
|
|
|
2907
|
|
|
2908 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
|
|
|
2909
|
|
|
2910 #if defined(SPI2)
|
|
|
2911 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
|
|
|
2912 #endif /* SPI2 */
|
|
|
2913
|
|
|
2914 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
|
|
|
2915
|
|
|
2916 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
|
|
|
2917
|
|
|
2918 #if defined(USART3)
|
|
|
2919 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
|
|
|
2920 #endif /* USART3 */
|
|
|
2921
|
|
|
2922 #if defined(UART4)
|
|
|
2923 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
|
|
|
2924 #endif /* UART4 */
|
|
|
2925
|
|
|
2926 #if defined(UART5)
|
|
|
2927 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
|
|
|
2928 #endif /* UART5 */
|
|
|
2929
|
|
|
2930 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
|
|
|
2931
|
|
|
2932 #if defined(I2C2)
|
|
|
2933 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
|
|
|
2934 #endif /* I2C2 */
|
|
|
2935
|
|
|
2936 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
|
|
|
2937
|
|
|
2938 #if defined(I2C4)
|
|
|
2939 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET)
|
|
|
2940 #endif /* I2C4 */
|
|
|
2941
|
|
|
2942 #if defined(CRS)
|
|
|
2943 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
|
|
|
2944 #endif /* CRS */
|
|
|
2945
|
|
|
2946 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
|
|
|
2947
|
|
|
2948 #if defined(USB)
|
|
|
2949 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET)
|
|
|
2950 #endif /* USB */
|
|
|
2951
|
|
|
2952 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
|
|
|
2953
|
|
|
2954 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
|
|
|
2955
|
|
|
2956 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
|
|
|
2957
|
|
|
2958 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
|
|
|
2959
|
|
|
2960 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
|
|
|
2961
|
|
|
2962 #if defined(SWPMI1)
|
|
|
2963 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
|
|
|
2964 #endif /* SWPMI1 */
|
|
|
2965
|
|
|
2966 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
|
|
|
2967
|
|
|
2968 /**
|
|
|
2969 * @}
|
|
|
2970 */
|
|
|
2971
|
|
|
2972 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
|
|
|
2973 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
|
|
2974 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
|
|
2975 * power consumption.
|
|
|
2976 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
|
|
2977 * @note By default, all peripheral clocks are enabled during SLEEP mode.
|
|
|
2978 * @{
|
|
|
2979 */
|
|
|
2980
|
|
|
2981 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
|
|
|
2982
|
|
|
2983 #if defined(SDMMC1)
|
|
|
2984 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
|
|
|
2985 #endif /* SDMMC1 */
|
|
|
2986
|
|
|
2987 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
|
|
|
2988
|
|
|
2989 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
|
|
|
2990
|
|
|
2991 #if defined(TIM8)
|
|
|
2992 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
|
|
|
2993 #endif /* TIM8 */
|
|
|
2994
|
|
|
2995 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
|
|
|
2996
|
|
|
2997 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
|
|
|
2998
|
|
|
2999 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
|
|
|
3000
|
|
|
3001 #if defined(TIM17)
|
|
|
3002 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
|
|
|
3003 #endif /* TIM17 */
|
|
|
3004
|
|
|
3005 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
|
|
|
3006
|
|
|
3007 #if defined(SAI2)
|
|
|
3008 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
|
|
|
3009 #endif /* SAI2 */
|
|
|
3010
|
|
|
3011 #if defined(DFSDM1_Filter0)
|
|
|
3012 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
|
|
|
3013 #endif /* DFSDM1_Filter0 */
|
|
|
3014
|
|
|
3015
|
|
|
3016 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
|
|
|
3017
|
|
|
3018 #if defined(SDMMC1)
|
|
|
3019 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
|
|
|
3020 #endif /* SDMMC1 */
|
|
|
3021
|
|
|
3022 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
|
|
|
3023
|
|
|
3024 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
|
|
|
3025
|
|
|
3026 #if defined(TIM8)
|
|
|
3027 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
|
|
|
3028 #endif /* TIM8 */
|
|
|
3029
|
|
|
3030 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
|
|
|
3031
|
|
|
3032 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
|
|
|
3033
|
|
|
3034 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
|
|
|
3035
|
|
|
3036 #if defined(TIM17)
|
|
|
3037 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
|
|
|
3038 #endif /* TIM17 */
|
|
|
3039
|
|
|
3040 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
|
|
|
3041
|
|
|
3042 #if defined(SAI2)
|
|
|
3043 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
|
|
|
3044 #endif /* SAI2 */
|
|
|
3045
|
|
|
3046 #if defined(DFSDM1_Filter0)
|
|
|
3047 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
|
|
|
3048 #endif /* DFSDM1_Filter0 */
|
|
|
3049
|
|
|
3050 /**
|
|
|
3051 * @}
|
|
|
3052 */
|
|
|
3053
|
|
|
3054 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
|
|
|
3055 * @{
|
|
|
3056 */
|
|
|
3057
|
|
|
3058 /** @brief Macros to force or release the Backup domain reset.
|
|
|
3059 * @note This function resets the RTC peripheral (including the backup registers)
|
|
|
3060 * and the RTC clock source selection in RCC_CSR register.
|
|
|
3061 * @note The BKPSRAM is not affected by this reset.
|
|
|
3062 * @retval None
|
|
|
3063 */
|
|
|
3064 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
|
|
|
3065
|
|
|
3066 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
|
|
|
3067
|
|
|
3068 /**
|
|
|
3069 * @}
|
|
|
3070 */
|
|
|
3071
|
|
|
3072 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
|
|
|
3073 * @{
|
|
|
3074 */
|
|
|
3075
|
|
|
3076 /** @brief Macros to enable or disable the RTC clock.
|
|
|
3077 * @note As the RTC is in the Backup domain and write access is denied to
|
|
|
3078 * this domain after reset, you have to enable write access using
|
|
|
3079 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
|
|
|
3080 * (to be done once after reset).
|
|
|
3081 * @note These macros must be used after the RTC clock source was selected.
|
|
|
3082 * @retval None
|
|
|
3083 */
|
|
|
3084 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
|
|
|
3085
|
|
|
3086 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
|
|
|
3087
|
|
|
3088 /**
|
|
|
3089 * @}
|
|
|
3090 */
|
|
|
3091
|
|
|
3092 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
|
|
|
3093 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
|
|
|
3094 * It is used (enabled by hardware) as system clock source after startup
|
|
|
3095 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
|
|
|
3096 * of the HSE used directly or indirectly as system clock (if the Clock
|
|
|
3097 * Security System CSS is enabled).
|
|
|
3098 * @note HSI can not be stopped if it is used as system clock source. In this case,
|
|
|
3099 * you have to select another source of the system clock then stop the HSI.
|
|
|
3100 * @note After enabling the HSI, the application software should wait on HSIRDY
|
|
|
3101 * flag to be set indicating that HSI clock is stable and can be used as
|
|
|
3102 * system clock source.
|
|
|
3103 * This parameter can be: ENABLE or DISABLE.
|
|
|
3104 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
|
|
|
3105 * clock cycles.
|
|
|
3106 * @retval None
|
|
|
3107 */
|
|
|
3108 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
|
|
|
3109
|
|
|
3110 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
|
|
|
3111
|
|
|
3112 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
|
|
|
3113 * @note The calibration is used to compensate for the variations in voltage
|
|
|
3114 * and temperature that influence the frequency of the internal HSI RC.
|
|
|
3115 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
|
|
|
3116 * (default is RCC_HSICALIBRATION_DEFAULT).
|
|
|
3117 * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).
|
|
|
3118 * @retval None
|
|
|
3119 */
|
|
|
3120 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
|
|
|
3121 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
|
|
|
3122
|
|
|
3123 /**
|
|
|
3124 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
|
|
|
3125 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
|
|
|
3126 * @note The enable of this function has not effect on the HSION bit.
|
|
|
3127 * This parameter can be: ENABLE or DISABLE.
|
|
|
3128 * @retval None
|
|
|
3129 */
|
|
|
3130 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
|
|
|
3131
|
|
|
3132 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
|
|
|
3133
|
|
|
3134 /**
|
|
|
3135 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
|
|
|
3136 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
|
|
|
3137 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
|
|
|
3138 * speed because of the HSI startup time.
|
|
|
3139 * @note The enable of this function has not effect on the HSION bit.
|
|
|
3140 * This parameter can be: ENABLE or DISABLE.
|
|
|
3141 * @retval None
|
|
|
3142 */
|
|
|
3143 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
|
|
|
3144
|
|
|
3145 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
|
|
|
3146
|
|
|
3147 /**
|
|
|
3148 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
|
|
|
3149 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
|
|
|
3150 * It is used (enabled by hardware) as system clock source after
|
|
|
3151 * startup from Reset, wakeup from STOP and STANDBY mode, or in case
|
|
|
3152 * of failure of the HSE used directly or indirectly as system clock
|
|
|
3153 * (if the Clock Security System CSS is enabled).
|
|
|
3154 * @note MSI can not be stopped if it is used as system clock source.
|
|
|
3155 * In this case, you have to select another source of the system
|
|
|
3156 * clock then stop the MSI.
|
|
|
3157 * @note After enabling the MSI, the application software should wait on
|
|
|
3158 * MSIRDY flag to be set indicating that MSI clock is stable and can
|
|
|
3159 * be used as system clock source.
|
|
|
3160 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
|
|
|
3161 * clock cycles.
|
|
|
3162 * @retval None
|
|
|
3163 */
|
|
|
3164 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
|
|
|
3165
|
|
|
3166 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
|
|
|
3167
|
|
|
3168 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
|
|
|
3169 * @note The calibration is used to compensate for the variations in voltage
|
|
|
3170 * and temperature that influence the frequency of the internal MSI RC.
|
|
|
3171 * Refer to the Application Note AN3300 for more details on how to
|
|
|
3172 * calibrate the MSI.
|
|
|
3173 * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
|
|
|
3174 * (default is RCC_MSICALIBRATION_DEFAULT).
|
|
|
3175 * This parameter must be a number between 0 and 255.
|
|
|
3176 * @retval None
|
|
|
3177 */
|
|
|
3178 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
|
|
|
3179 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
|
|
|
3180
|
|
|
3181 /**
|
|
|
3182 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
|
|
|
3183 * @note After restart from Reset , the MSI clock is around 4 MHz.
|
|
|
3184 * After stop the startup clock can be MSI (at any of its possible
|
|
|
3185 * frequencies, the one that was used before entering stop mode) or HSI.
|
|
|
3186 * After Standby its frequency can be selected between 4 possible values
|
|
|
3187 * (1, 2, 4 or 8 MHz).
|
|
|
3188 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
|
|
|
3189 * (MSIRDY=1).
|
|
|
3190 * @note The MSI clock range after reset can be modified on the fly.
|
|
|
3191 * @param __MSIRANGEVALUE__: specifies the MSI clock range.
|
|
|
3192 * This parameter must be one of the following values:
|
|
|
3193 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
|
|
|
3194 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
|
|
|
3195 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
|
|
|
3196 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
|
|
|
3197 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
|
|
|
3198 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
|
|
|
3199 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
|
|
|
3200 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
|
|
|
3201 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
|
|
|
3202 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
|
|
|
3203 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
|
|
|
3204 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
|
|
|
3205 * @retval None
|
|
|
3206 */
|
|
|
3207 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
|
|
|
3208 do { \
|
|
|
3209 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
|
|
|
3210 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
|
|
|
3211 } while(0)
|
|
|
3212
|
|
|
3213 /**
|
|
|
3214 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
|
|
|
3215 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
|
|
|
3216 * @param __MSIRANGEVALUE__: specifies the MSI clock range.
|
|
|
3217 * This parameter must be one of the following values:
|
|
|
3218 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
|
|
|
3219 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
|
|
|
3220 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
|
|
|
3221 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
|
|
|
3222 * @retval None
|
|
|
3223 */
|
|
|
3224 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
|
|
|
3225 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
|
|
|
3226
|
|
|
3227 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
|
|
|
3228 * @retval MSI clock range.
|
|
|
3229 * This parameter must be one of the following values:
|
|
|
3230 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
|
|
|
3231 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
|
|
|
3232 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
|
|
|
3233 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
|
|
|
3234 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
|
|
|
3235 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
|
|
|
3236 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
|
|
|
3237 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
|
|
|
3238 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
|
|
|
3239 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
|
|
|
3240 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
|
|
|
3241 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
|
|
|
3242 */
|
|
|
3243 #define __HAL_RCC_GET_MSI_RANGE() \
|
|
|
3244 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
|
|
|
3245 (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
|
|
|
3246 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
|
|
|
3247
|
|
|
3248 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
|
|
|
3249 * @note After enabling the LSI, the application software should wait on
|
|
|
3250 * LSIRDY flag to be set indicating that LSI clock is stable and can
|
|
|
3251 * be used to clock the IWDG and/or the RTC.
|
|
|
3252 * @note LSI can not be disabled if the IWDG is running.
|
|
|
3253 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
|
|
|
3254 * clock cycles.
|
|
|
3255 * @retval None
|
|
|
3256 */
|
|
|
3257 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
|
|
|
3258
|
|
|
3259 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
|
|
|
3260
|
|
|
3261 /**
|
|
|
3262 * @brief Macro to configure the External High Speed oscillator (HSE).
|
|
|
3263 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
|
|
|
3264 * supported by this macro. User should request a transition to HSE Off
|
|
|
3265 * first and then HSE On or HSE Bypass.
|
|
|
3266 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
|
|
|
3267 * software should wait on HSERDY flag to be set indicating that HSE clock
|
|
|
3268 * is stable and can be used to clock the PLL and/or system clock.
|
|
|
3269 * @note HSE state can not be changed if it is used directly or through the
|
|
|
3270 * PLL as system clock. In this case, you have to select another source
|
|
|
3271 * of the system clock then change the HSE state (ex. disable it).
|
|
|
3272 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
|
|
|
3273 * @note This function reset the CSSON bit, so if the clock security system(CSS)
|
|
|
3274 * was previously enabled you have to enable it again after calling this
|
|
|
3275 * function.
|
|
|
3276 * @param __STATE__: specifies the new state of the HSE.
|
|
|
3277 * This parameter can be one of the following values:
|
|
|
3278 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
|
|
|
3279 * 6 HSE oscillator clock cycles.
|
|
|
3280 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
|
|
|
3281 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
|
|
|
3282 * @retval None
|
|
|
3283 */
|
|
|
3284 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
|
|
|
3285 do { \
|
|
|
3286 if((__STATE__) == RCC_HSE_ON) \
|
|
|
3287 { \
|
|
|
3288 SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
|
3289 } \
|
|
|
3290 else if((__STATE__) == RCC_HSE_BYPASS) \
|
|
|
3291 { \
|
|
|
3292 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
|
|
3293 SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
|
3294 } \
|
|
|
3295 else \
|
|
|
3296 { \
|
|
|
3297 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
|
3298 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
|
|
3299 } \
|
|
|
3300 } while(0)
|
|
|
3301
|
|
|
3302 /**
|
|
|
3303 * @brief Macro to configure the External Low Speed oscillator (LSE).
|
|
|
3304 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
|
|
|
3305 * supported by this macro. User should request a transition to LSE Off
|
|
|
3306 * first and then LSE On or LSE Bypass.
|
|
|
3307 * @note As the LSE is in the Backup domain and write access is denied to
|
|
|
3308 * this domain after reset, you have to enable write access using
|
|
|
3309 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
|
|
3310 * (to be done once after reset).
|
|
|
3311 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
|
|
|
3312 * software should wait on LSERDY flag to be set indicating that LSE clock
|
|
|
3313 * is stable and can be used to clock the RTC.
|
|
|
3314 * @param __STATE__: specifies the new state of the LSE.
|
|
|
3315 * This parameter can be one of the following values:
|
|
|
3316 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
|
|
|
3317 * 6 LSE oscillator clock cycles.
|
|
|
3318 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
|
|
|
3319 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
|
|
|
3320 * @retval None
|
|
|
3321 */
|
|
|
3322 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
|
|
|
3323 do { \
|
|
|
3324 if((__STATE__) == RCC_LSE_ON) \
|
|
|
3325 { \
|
|
|
3326 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
|
3327 } \
|
|
|
3328 else if((__STATE__) == RCC_LSE_BYPASS) \
|
|
|
3329 { \
|
|
|
3330 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
|
3331 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
|
3332 } \
|
|
|
3333 else \
|
|
|
3334 { \
|
|
|
3335 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
|
3336 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
|
3337 } \
|
|
|
3338 } while(0)
|
|
|
3339
|
|
|
3340 #if defined(RCC_HSI48_SUPPORT)
|
|
|
3341
|
|
|
3342 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
|
|
|
3343 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
|
|
|
3344 * @note After enabling the HSI48, the application software should wait on HSI48RDY
|
|
|
3345 * flag to be set indicating that HSI48 clock is stable.
|
|
|
3346 * This parameter can be: ENABLE or DISABLE.
|
|
|
3347 * @retval None
|
|
|
3348 */
|
|
|
3349 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
|
|
|
3350
|
|
|
3351 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
|
|
|
3352
|
|
|
3353 #endif /* RCC_HSI48_SUPPORT */
|
|
|
3354
|
|
|
3355 /** @brief Macros to configure the RTC clock (RTCCLK).
|
|
|
3356 * @note As the RTC clock configuration bits are in the Backup domain and write
|
|
|
3357 * access is denied to this domain after reset, you have to enable write
|
|
|
3358 * access using the Power Backup Access macro before to configure
|
|
|
3359 * the RTC clock source (to be done once after reset).
|
|
|
3360 * @note Once the RTC clock is configured it cannot be changed unless the
|
|
|
3361 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
|
|
|
3362 * a Power On Reset (POR).
|
|
|
3363 *
|
|
|
3364 * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
|
|
|
3365 * This parameter can be one of the following values:
|
|
|
3366 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
|
|
|
3367 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
|
|
|
3368 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
|
|
|
3369 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
|
|
|
3370 *
|
|
|
3371 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
|
|
|
3372 * work in STOP and STANDBY modes, and can be used as wakeup source.
|
|
|
3373 * However, when the HSE clock is used as RTC clock source, the RTC
|
|
|
3374 * cannot be used in STOP and STANDBY modes.
|
|
|
3375 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
|
|
|
3376 * RTC clock source).
|
|
|
3377 * @retval None
|
|
|
3378 */
|
|
|
3379 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
|
|
|
3380 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
|
|
|
3381
|
|
|
3382
|
|
|
3383 /** @brief Macro to get the RTC clock source.
|
|
|
3384 * @retval The returned value can be one of the following:
|
|
|
3385 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
|
|
|
3386 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
|
|
|
3387 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
|
|
|
3388 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
|
|
|
3389 */
|
|
|
3390 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
|
|
|
3391
|
|
|
3392 /** @brief Macros to enable or disable the main PLL.
|
|
|
3393 * @note After enabling the main PLL, the application software should wait on
|
|
|
3394 * PLLRDY flag to be set indicating that PLL clock is stable and can
|
|
|
3395 * be used as system clock source.
|
|
|
3396 * @note The main PLL can not be disabled if it is used as system clock source
|
|
|
3397 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
|
|
|
3398 * @retval None
|
|
|
3399 */
|
|
|
3400 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
|
|
|
3401
|
|
|
3402 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
|
|
|
3403
|
|
|
3404 /** @brief Macro to configure the PLL clock source.
|
|
|
3405 * @note This function must be used only when the main PLL is disabled.
|
|
|
3406 * @param __PLLSOURCE__: specifies the PLL entry clock source.
|
|
|
3407 * This parameter can be one of the following values:
|
|
|
3408 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
|
|
|
3409 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
|
|
|
3410 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
|
|
|
3411 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
|
|
|
3412 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
|
|
|
3413 * @retval None
|
|
|
3414 *
|
|
|
3415 */
|
|
|
3416 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
|
|
|
3417 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
|
|
|
3418
|
|
|
3419 /** @brief Macro to configure the PLL source division factor M.
|
|
|
3420 * @note This function must be used only when the main PLL is disabled.
|
|
|
3421 * @param __PLLM__: specifies the division factor for PLL VCO input clock
|
|
|
3422 * This parameter must be a number between Min_Data = 1 and Max_Data = 8.
|
|
|
3423 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
|
|
|
3424 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
|
|
|
3425 * of 16 MHz to limit PLL jitter.
|
|
|
3426 * @retval None
|
|
|
3427 *
|
|
|
3428 */
|
|
|
3429 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
|
|
|
3430 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
|
|
|
3431
|
|
|
3432 /**
|
|
|
3433 * @brief Macro to configure the main PLL clock source, multiplication and division factors.
|
|
|
3434 * @note This function must be used only when the main PLL is disabled.
|
|
|
3435 *
|
|
|
3436 * @param __PLLSOURCE__: specifies the PLL entry clock source.
|
|
|
3437 * This parameter can be one of the following values:
|
|
|
3438 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
|
|
|
3439 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
|
|
|
3440 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
|
|
|
3441 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
|
|
|
3442 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
|
|
|
3443 *
|
|
|
3444 * @param __PLLM__: specifies the division factor for PLL VCO input clock.
|
|
|
3445 * This parameter must be a number between 1 and 8.
|
|
|
3446 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
|
|
|
3447 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
|
|
|
3448 * of 16 MHz to limit PLL jitter.
|
|
|
3449 *
|
|
|
3450 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
|
|
|
3451 * This parameter must be a number between 8 and 86.
|
|
|
3452 * @note You have to set the PLLN parameter correctly to ensure that the VCO
|
|
|
3453 * output frequency is between 64 and 344 MHz.
|
|
|
3454 *
|
|
|
3455 * @param __PLLP__: specifies the division factor for SAI clock.
|
|
|
3456 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
|
|
|
3457 * else (2 to 31).
|
|
|
3458 *
|
|
|
3459 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
|
|
|
3460 * This parameter must be in the range (2, 4, 6 or 8).
|
|
|
3461 * @note If the USB OTG FS is used in your application, you have to set the
|
|
|
3462 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
|
|
|
3463 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
|
|
|
3464 * correctly.
|
|
|
3465 * @param __PLLR__: specifies the division factor for the main system clock.
|
|
|
3466 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
|
|
|
3467 * This parameter must be in the range (2, 4, 6 or 8).
|
|
|
3468 * @retval None
|
|
|
3469 */
|
|
|
3470 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
|
|
|
3471
|
|
|
3472 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
|
|
|
3473 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \
|
|
|
3474 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \
|
|
|
3475 (uint32_t)((__PLLP__) << 27U))
|
|
|
3476
|
|
|
3477 #else
|
|
|
3478
|
|
|
3479 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
|
|
|
3480 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \
|
|
|
3481 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
|
|
|
3482
|
|
|
3483 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
|
|
|
3484
|
|
|
3485 /** @brief Macro to get the oscillator used as PLL clock source.
|
|
|
3486 * @retval The oscillator used as PLL clock source. The returned value can be one
|
|
|
3487 * of the following:
|
|
|
3488 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
|
|
|
3489 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
|
|
|
3490 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
|
|
|
3491 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
|
|
|
3492 */
|
|
|
3493 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
|
|
|
3494
|
|
|
3495 /**
|
|
|
3496 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
|
|
|
3497 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
|
|
|
3498 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
|
|
|
3499 * be stopped if used as System Clock.
|
|
|
3500 * @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
|
|
|
3501 * This parameter can be one or a combination of the following values:
|
|
|
3502 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
|
|
|
3503 * high-quality audio performance on SAI interface in case.
|
|
|
3504 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
|
|
|
3505 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
|
|
|
3506 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
|
|
|
3507 * @retval None
|
|
|
3508 */
|
|
|
3509 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
|
|
|
3510
|
|
|
3511 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
|
|
|
3512
|
|
|
3513 /**
|
|
|
3514 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
|
|
|
3515 * @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
|
|
|
3516 * This parameter can be one of the following values:
|
|
|
3517 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
|
|
|
3518 * high-quality audio performance on SAI interface in case.
|
|
|
3519 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
|
|
|
3520 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
|
|
|
3521 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
|
|
|
3522 * @retval SET / RESET
|
|
|
3523 */
|
|
|
3524 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
|
|
|
3525
|
|
|
3526 /**
|
|
|
3527 * @brief Macro to configure the system clock source.
|
|
|
3528 * @param __SYSCLKSOURCE__: specifies the system clock source.
|
|
|
3529 * This parameter can be one of the following values:
|
|
|
3530 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
|
|
|
3531 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
|
|
|
3532 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
|
|
|
3533 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
|
|
|
3534 * @retval None
|
|
|
3535 */
|
|
|
3536 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
|
|
|
3537 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
|
|
|
3538
|
|
|
3539 /** @brief Macro to get the clock source used as system clock.
|
|
|
3540 * @retval The clock source used as system clock. The returned value can be one
|
|
|
3541 * of the following:
|
|
|
3542 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
|
|
|
3543 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
|
|
|
3544 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
|
|
|
3545 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
|
|
|
3546 */
|
|
|
3547 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
|
|
|
3548
|
|
|
3549 /**
|
|
|
3550 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
|
|
|
3551 * @note As the LSE is in the Backup domain and write access is denied to
|
|
|
3552 * this domain after reset, you have to enable write access using
|
|
|
3553 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
|
|
3554 * (to be done once after reset).
|
|
|
3555 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
|
|
|
3556 * This parameter can be one of the following values:
|
|
|
3557 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
|
|
|
3558 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
|
|
|
3559 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
|
|
|
3560 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
|
|
|
3561 * @retval None
|
|
|
3562 */
|
|
|
3563 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
|
|
|
3564 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
|
|
|
3565
|
|
|
3566 /**
|
|
|
3567 * @brief Macro to configure the wake up from stop clock.
|
|
|
3568 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
|
|
|
3569 * This parameter can be one of the following values:
|
|
|
3570 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
|
|
|
3571 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
|
|
|
3572 * @retval None
|
|
|
3573 */
|
|
|
3574 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
|
|
|
3575 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
|
|
|
3576
|
|
|
3577
|
|
|
3578 /** @brief Macro to configure the MCO clock.
|
|
|
3579 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
|
|
3580 * This parameter can be one of the following values:
|
|
|
3581 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
|
|
|
3582 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
|
|
|
3583 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
|
|
|
3584 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
|
|
|
3585 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
|
|
|
3586 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
|
|
|
3587 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
|
|
|
3588 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
|
|
|
3589 @if STM32L443xx
|
|
|
3590 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
|
|
|
3591 @endif
|
|
|
3592 @if STM32L462xx
|
|
|
3593 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
|
|
|
3594 @endif
|
|
|
3595 * @param __MCODIV__ specifies the MCO clock prescaler.
|
|
|
3596 * This parameter can be one of the following values:
|
|
|
3597 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
|
|
|
3598 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
|
|
|
3599 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
|
|
|
3600 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
|
|
|
3601 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
|
|
|
3602 */
|
|
|
3603 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
|
|
|
3604 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
|
|
|
3605
|
|
|
3606 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
|
|
|
3607 * @brief macros to manage the specified RCC Flags and interrupts.
|
|
|
3608 * @{
|
|
|
3609 */
|
|
|
3610
|
|
|
3611 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
|
|
|
3612 * the selected interrupts).
|
|
|
3613 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
|
|
|
3614 * This parameter can be any combination of the following values:
|
|
|
3615 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
|
|
3616 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
|
|
3617 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
|
|
|
3618 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
|
|
3619 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
|
|
3620 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
|
|
|
3621 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
|
|
|
3622 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
|
|
|
3623 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
|
|
|
3624 @if STM32L443xx
|
|
|
3625 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
|
|
3626 @endif
|
|
|
3627 @if STM32L462xx
|
|
|
3628 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
|
|
3629 @endif
|
|
|
3630 * @retval None
|
|
|
3631 */
|
|
|
3632 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
|
|
|
3633
|
|
|
3634 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
|
|
|
3635 * the selected interrupts).
|
|
|
3636 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
|
|
|
3637 * This parameter can be any combination of the following values:
|
|
|
3638 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
|
|
3639 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
|
|
3640 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt
|
|
|
3641 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
|
|
3642 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
|
|
3643 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
|
|
|
3644 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
|
|
|
3645 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
|
|
|
3646 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
|
|
|
3647 @if STM32L443xx
|
|
|
3648 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
|
|
3649 @endif
|
|
|
3650 @if STM32L462xx
|
|
|
3651 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
|
|
3652 @endif
|
|
|
3653 * @retval None
|
|
|
3654 */
|
|
|
3655 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
|
|
|
3656
|
|
|
3657 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
|
|
|
3658 * bits to clear the selected interrupt pending bits.
|
|
|
3659 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
|
|
3660 * This parameter can be any combination of the following values:
|
|
|
3661 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
|
|
3662 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
|
|
3663 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
|
|
|
3664 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
|
|
3665 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
|
|
3666 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
|
|
|
3667 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
|
|
|
3668 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
|
|
|
3669 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
|
|
|
3670 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
|
|
|
3671 @if STM32L443xx
|
|
|
3672 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
|
|
3673 @endif
|
|
|
3674 @if STM32L462xx
|
|
|
3675 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
|
|
3676 @endif
|
|
|
3677 * @retval None
|
|
|
3678 */
|
|
|
3679 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
|
|
|
3680
|
|
|
3681 /** @brief Check whether the RCC interrupt has occurred or not.
|
|
|
3682 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
|
|
|
3683 * This parameter can be one of the following values:
|
|
|
3684 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
|
|
3685 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
|
|
3686 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt
|
|
|
3687 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
|
|
3688 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
|
|
3689 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
|
|
|
3690 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
|
|
|
3691 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
|
|
|
3692 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
|
|
|
3693 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
|
|
|
3694 @if STM32L443xx
|
|
|
3695 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
|
|
3696 @endif
|
|
|
3697 @if STM32L462xx
|
|
|
3698 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
|
|
3699 @endif
|
|
|
3700 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
|
|
3701 */
|
|
|
3702 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
|
|
|
3703
|
|
|
3704 /** @brief Set RMVF bit to clear the reset flags.
|
|
|
3705 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
|
|
|
3706 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
|
|
|
3707 * @retval None
|
|
|
3708 */
|
|
|
3709 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
|
|
|
3710
|
|
|
3711 /** @brief Check whether the selected RCC flag is set or not.
|
|
|
3712 * @param __FLAG__: specifies the flag to check.
|
|
|
3713 * This parameter can be one of the following values:
|
|
|
3714 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
|
|
|
3715 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
|
|
|
3716 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
|
|
|
3717 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
|
|
|
3718 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready
|
|
|
3719 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
|
|
|
3720 @if STM32L443xx
|
|
|
3721 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
|
|
|
3722 @endif
|
|
|
3723 @if STM32L462xx
|
|
|
3724 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
|
|
|
3725 @endif
|
|
|
3726 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
|
|
|
3727 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
|
|
|
3728 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
|
|
|
3729 * @arg @ref RCC_FLAG_BORRST BOR reset
|
|
|
3730 * @arg @ref RCC_FLAG_OBLRST OBLRST reset
|
|
|
3731 * @arg @ref RCC_FLAG_PINRST Pin reset
|
|
|
3732 * @arg @ref RCC_FLAG_FWRST FIREWALL reset
|
|
|
3733 * @arg @ref RCC_FLAG_RMVF Remove reset Flag
|
|
|
3734 * @arg @ref RCC_FLAG_SFTRST Software reset
|
|
|
3735 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
|
|
|
3736 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
|
|
|
3737 * @arg @ref RCC_FLAG_LPWRRST Low Power reset
|
|
|
3738 * @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
|
3739 */
|
|
|
3740 #if defined(RCC_HSI48_SUPPORT)
|
|
|
3741 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
|
|
|
3742 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
|
|
|
3743 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
|
|
|
3744 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
|
|
|
3745 ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
|
|
|
3746 ? 1U : 0U)
|
|
|
3747 #else
|
|
|
3748 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
|
|
|
3749 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
|
|
|
3750 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
|
|
|
3751 ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
|
|
|
3752 ? 1U : 0U)
|
|
|
3753 #endif /* RCC_HSI48_SUPPORT */
|
|
|
3754
|
|
|
3755 /**
|
|
|
3756 * @}
|
|
|
3757 */
|
|
|
3758
|
|
|
3759 /**
|
|
|
3760 * @}
|
|
|
3761 */
|
|
|
3762
|
|
|
3763 /* Private constants ---------------------------------------------------------*/
|
|
|
3764 /** @defgroup RCC_Private_Constants RCC Private Constants
|
|
|
3765 * @{
|
|
|
3766 */
|
|
|
3767 /* Defines used for Flags */
|
|
|
3768 #define CR_REG_INDEX ((uint32_t)1U)
|
|
|
3769 #define BDCR_REG_INDEX ((uint32_t)2U)
|
|
|
3770 #define CSR_REG_INDEX ((uint32_t)3U)
|
|
|
3771 #if defined(RCC_HSI48_SUPPORT)
|
|
|
3772 #define CRRCR_REG_INDEX ((uint32_t)4U)
|
|
|
3773 #endif /* RCC_HSI48_SUPPORT */
|
|
|
3774
|
|
|
3775 #define RCC_FLAG_MASK ((uint32_t)0x1FU)
|
|
|
3776 /**
|
|
|
3777 * @}
|
|
|
3778 */
|
|
|
3779
|
|
|
3780 /* Private macros ------------------------------------------------------------*/
|
|
|
3781 /** @addtogroup RCC_Private_Macros
|
|
|
3782 * @{
|
|
|
3783 */
|
|
|
3784
|
|
|
3785 #if defined(RCC_HSI48_SUPPORT)
|
|
|
3786 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
|
|
|
3787 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
|
|
|
3788 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
|
|
|
3789 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
|
|
|
3790 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
|
|
|
3791 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
|
|
|
3792 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
|
|
|
3793 #else
|
|
|
3794 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
|
|
|
3795 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
|
|
|
3796 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
|
|
|
3797 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
|
|
|
3798 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
|
|
|
3799 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
|
|
|
3800 #endif /* RCC_HSI48_SUPPORT */
|
|
|
3801
|
|
|
3802 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
|
|
|
3803 ((__HSE__) == RCC_HSE_BYPASS))
|
|
|
3804
|
|
|
3805 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
|
|
|
3806 ((__LSE__) == RCC_LSE_BYPASS))
|
|
|
3807
|
|
|
3808 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
|
|
|
3809
|
|
|
3810 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> POSITION_VAL(RCC_ICSCR_HSITRIM)))
|
|
|
3811
|
|
|
3812 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
|
|
|
3813
|
|
|
3814 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
|
|
|
3815
|
|
|
3816 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
|
|
|
3817
|
|
|
3818 #if defined(RCC_HSI48_SUPPORT)
|
|
|
3819 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
|
|
|
3820 #endif /* RCC_HSI48_SUPPORT */
|
|
|
3821
|
|
|
3822 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
|
|
|
3823 ((__PLL__) == RCC_PLL_ON))
|
|
|
3824
|
|
|
3825 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
|
|
|
3826 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
|
|
|
3827 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
|
|
|
3828 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
|
|
|
3829
|
|
|
3830 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
|
|
|
3831
|
|
|
3832 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
|
|
|
3833
|
|
|
3834 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
|
|
|
3835 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
|
|
|
3836 #else
|
|
|
3837 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
|
|
|
3838 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */
|
|
|
3839
|
|
|
3840 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
|
|
|
3841 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
|
|
|
3842
|
|
|
3843 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
|
|
|
3844 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
|
|
|
3845
|
|
|
3846 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \
|
|
|
3847 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \
|
|
|
3848 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
|
|
|
3849 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U))
|
|
|
3850
|
|
|
3851 #if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
3852 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \
|
|
|
3853 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
|
|
|
3854 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U))
|
|
|
3855 #endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
3856
|
|
|
3857 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
|
|
|
3858 ((__RANGE__) == RCC_MSIRANGE_1) || \
|
|
|
3859 ((__RANGE__) == RCC_MSIRANGE_2) || \
|
|
|
3860 ((__RANGE__) == RCC_MSIRANGE_3) || \
|
|
|
3861 ((__RANGE__) == RCC_MSIRANGE_4) || \
|
|
|
3862 ((__RANGE__) == RCC_MSIRANGE_5) || \
|
|
|
3863 ((__RANGE__) == RCC_MSIRANGE_6) || \
|
|
|
3864 ((__RANGE__) == RCC_MSIRANGE_7) || \
|
|
|
3865 ((__RANGE__) == RCC_MSIRANGE_8) || \
|
|
|
3866 ((__RANGE__) == RCC_MSIRANGE_9) || \
|
|
|
3867 ((__RANGE__) == RCC_MSIRANGE_10) || \
|
|
|
3868 ((__RANGE__) == RCC_MSIRANGE_11))
|
|
|
3869
|
|
|
3870 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \
|
|
|
3871 ((__RANGE__) == RCC_MSIRANGE_5) || \
|
|
|
3872 ((__RANGE__) == RCC_MSIRANGE_6) || \
|
|
|
3873 ((__RANGE__) == RCC_MSIRANGE_7))
|
|
|
3874
|
|
|
3875 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
|
|
|
3876
|
|
|
3877 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
|
|
|
3878 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
|
|
|
3879 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
|
|
|
3880 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
|
|
|
3881
|
|
|
3882 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
|
|
|
3883 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
|
|
|
3884 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
|
|
|
3885 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
|
|
|
3886 ((__HCLK__) == RCC_SYSCLK_DIV512))
|
|
|
3887
|
|
|
3888 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
|
|
|
3889 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
|
|
|
3890 ((__PCLK__) == RCC_HCLK_DIV16))
|
|
|
3891
|
|
|
3892 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
|
|
|
3893 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
|
|
|
3894 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
|
|
|
3895 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
|
|
|
3896
|
|
|
3897 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
|
|
|
3898
|
|
|
3899 #if defined(RCC_HSI48_SUPPORT)
|
|
|
3900 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
|
|
|
3901 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
|
|
|
3902 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
|
|
|
3903 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
|
|
|
3904 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
|
|
|
3905 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
|
|
|
3906 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
|
|
|
3907 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
|
|
|
3908 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
|
|
|
3909 #else
|
|
|
3910 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
|
|
|
3911 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
|
|
|
3912 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
|
|
|
3913 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
|
|
|
3914 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
|
|
|
3915 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
|
|
|
3916 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
|
|
|
3917 ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
|
|
|
3918 #endif /* RCC_HSI48_SUPPORT */
|
|
|
3919
|
|
|
3920 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
|
|
|
3921 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
|
|
|
3922 ((__DIV__) == RCC_MCODIV_16))
|
|
|
3923
|
|
|
3924 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
|
|
|
3925 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
|
|
|
3926 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
|
|
|
3927 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
|
|
|
3928
|
|
|
3929 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
|
|
|
3930 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
|
|
|
3931 /**
|
|
|
3932 * @}
|
|
|
3933 */
|
|
|
3934
|
|
|
3935 /* Include RCC HAL Extended module */
|
|
|
3936 #include "stm32l4xx_hal_rcc_ex.h"
|
|
|
3937
|
|
|
3938 /* Exported functions --------------------------------------------------------*/
|
|
|
3939 /** @addtogroup RCC_Exported_Functions
|
|
|
3940 * @{
|
|
|
3941 */
|
|
|
3942
|
|
|
3943
|
|
|
3944 /** @addtogroup RCC_Exported_Functions_Group1
|
|
|
3945 * @{
|
|
|
3946 */
|
|
|
3947
|
|
|
3948 /* Initialization and de-initialization functions ******************************/
|
|
|
3949 void HAL_RCC_DeInit(void);
|
|
|
3950 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
|
|
3951 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
|
|
|
3952
|
|
|
3953 /**
|
|
|
3954 * @}
|
|
|
3955 */
|
|
|
3956
|
|
|
3957 /** @addtogroup RCC_Exported_Functions_Group2
|
|
|
3958 * @{
|
|
|
3959 */
|
|
|
3960
|
|
|
3961 /* Peripheral Control functions ************************************************/
|
|
|
3962 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
|
|
|
3963 void HAL_RCC_EnableCSS(void);
|
|
|
3964 uint32_t HAL_RCC_GetSysClockFreq(void);
|
|
|
3965 uint32_t HAL_RCC_GetHCLKFreq(void);
|
|
|
3966 uint32_t HAL_RCC_GetPCLK1Freq(void);
|
|
|
3967 uint32_t HAL_RCC_GetPCLK2Freq(void);
|
|
|
3968 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
|
|
3969 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
|
|
|
3970 /* CSS NMI IRQ handler */
|
|
|
3971 void HAL_RCC_NMI_IRQHandler(void);
|
|
|
3972 /* User Callbacks in non blocking mode (IT mode) */
|
|
|
3973 void HAL_RCC_CSSCallback(void);
|
|
|
3974
|
|
|
3975 /**
|
|
|
3976 * @}
|
|
|
3977 */
|
|
|
3978
|
|
|
3979 /**
|
|
|
3980 * @}
|
|
|
3981 */
|
|
|
3982
|
|
|
3983 /**
|
|
|
3984 * @}
|
|
|
3985 */
|
|
|
3986
|
|
|
3987 /**
|
|
|
3988 * @}
|
|
|
3989 */
|
|
|
3990
|
|
|
3991 #ifdef __cplusplus
|
|
|
3992 }
|
|
|
3993 #endif
|
|
|
3994
|
|
|
3995 #endif /* __STM32L4xx_HAL_RCC_H */
|
|
|
3996
|
|
|
3997 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
