|
0
|
1 /**
|
|
|
2 ******************************************************************************
|
|
|
3 * @file stm32l4xx_hal_tim_ex.c
|
|
|
4 * @author MCD Application Team
|
|
|
5 * @version V1.6.0
|
|
|
6 * @date 28-October-2016
|
|
|
7 * @brief TIM HAL module driver.
|
|
|
8 * This file provides firmware functions to manage the following
|
|
|
9 * functionalities of the Timer Extended peripheral:
|
|
|
10 * + Time Hall Sensor Interface Initialization
|
|
|
11 * + Time Hall Sensor Interface Start
|
|
|
12 * + Time Complementary signal break and dead time configuration
|
|
|
13 * + Time Master and Slave synchronization configuration
|
|
|
14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
|
|
|
15 * + Time OCRef clear configuration
|
|
|
16 * + Timer remapping capabilities configuration
|
|
|
17 @verbatim
|
|
|
18 ==============================================================================
|
|
|
19 ##### TIMER Extended features #####
|
|
|
20 ==============================================================================
|
|
|
21 [..]
|
|
|
22 The Timer Extended features include:
|
|
|
23 (#) Complementary outputs with programmable dead-time for :
|
|
|
24 (++) Output Compare
|
|
|
25 (++) PWM generation (Edge and Center-aligned Mode)
|
|
|
26 (++) One-pulse mode output
|
|
|
27 (#) Synchronization circuit to control the timer with external signals and to
|
|
|
28 interconnect several timers together.
|
|
|
29 (#) Break input to put the timer output signals in reset state or in a known state.
|
|
|
30 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
|
|
|
31 positioning purposes
|
|
|
32
|
|
|
33 ##### How to use this driver #####
|
|
|
34 ==============================================================================
|
|
|
35 [..]
|
|
|
36 (#) Initialize the TIM low level resources by implementing the following functions
|
|
|
37 depending on the selected feature:
|
|
|
38 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
|
|
|
39
|
|
|
40 (#) Initialize the TIM low level resources :
|
|
|
41 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
|
|
|
42 (##) TIM pins configuration
|
|
|
43 (+++) Enable the clock for the TIM GPIOs using the following function:
|
|
|
44 __HAL_RCC_GPIOx_CLK_ENABLE();
|
|
|
45 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
|
|
|
46
|
|
|
47 (#) The external Clock can be configured, if needed (the default clock is the
|
|
|
48 internal clock from the APBx), using the following function:
|
|
|
49 HAL_TIM_ConfigClockSource, the clock configuration should be done before
|
|
|
50 any start function.
|
|
|
51
|
|
|
52 (#) Configure the TIM in the desired functioning mode using one of the
|
|
|
53 initialization function of this driver:
|
|
|
54 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the
|
|
|
55 Timer Hall Sensor Interface and the commutation event with the corresponding
|
|
|
56 Interrupt and DMA request if needed (Note that One Timer is used to interface
|
|
|
57 with the Hall sensor Interface and another Timer should be used to use
|
|
|
58 the commutation event).
|
|
|
59
|
|
|
60 (#) Activate the TIM peripheral using one of the start functions:
|
|
|
61 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
|
|
|
62 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
|
|
|
63 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
|
|
|
64 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
|
|
|
65
|
|
|
66
|
|
|
67 @endverbatim
|
|
|
68 ******************************************************************************
|
|
|
69 * @attention
|
|
|
70 *
|
|
|
71 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
|
|
72 *
|
|
|
73 * Redistribution and use in source and binary forms, with or without modification,
|
|
|
74 * are permitted provided that the following conditions are met:
|
|
|
75 * 1. Redistributions of source code must retain the above copyright notice,
|
|
|
76 * this list of conditions and the following disclaimer.
|
|
|
77 * 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
|
78 * this list of conditions and the following disclaimer in the documentation
|
|
|
79 * and/or other materials provided with the distribution.
|
|
|
80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
|
81 * may be used to endorse or promote products derived from this software
|
|
|
82 * without specific prior written permission.
|
|
|
83 *
|
|
|
84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
|
85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
|
86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
|
87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
|
88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
|
89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
|
90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
|
91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
|
92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
94 *
|
|
|
95 ******************************************************************************
|
|
|
96 */
|
|
|
97
|
|
|
98 /* Includes ------------------------------------------------------------------*/
|
|
|
99 #include "stm32l4xx_hal.h"
|
|
|
100
|
|
|
101 /** @addtogroup STM32L4xx_HAL_Driver
|
|
|
102 * @{
|
|
|
103 */
|
|
|
104
|
|
|
105 /** @defgroup TIMEx TIMEx
|
|
|
106 * @brief TIM Extended HAL module driver
|
|
|
107 * @{
|
|
|
108 */
|
|
|
109
|
|
|
110 #ifdef HAL_TIM_MODULE_ENABLED
|
|
|
111
|
|
|
112 /* Private typedef -----------------------------------------------------------*/
|
|
|
113 /* Private define ------------------------------------------------------------*/
|
|
|
114 #define BDTR_BKF_SHIFT (16)
|
|
|
115 #define BDTR_BK2F_SHIFT (20)
|
|
|
116 #define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000)
|
|
|
117
|
|
|
118 /* Private macro -------------------------------------------------------------*/
|
|
|
119 /* Private variables ---------------------------------------------------------*/
|
|
|
120 /* Private function prototypes -----------------------------------------------*/
|
|
|
121 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
|
|
|
122
|
|
|
123 /* Private functions ---------------------------------------------------------*/
|
|
|
124
|
|
|
125 /* Exported functions --------------------------------------------------------*/
|
|
|
126 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
|
|
127 * @{
|
|
|
128 */
|
|
|
129
|
|
|
130 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
|
|
131 * @brief Timer Hall Sensor functions
|
|
|
132 *
|
|
|
133 @verbatim
|
|
|
134 ==============================================================================
|
|
|
135 ##### Timer Hall Sensor functions #####
|
|
|
136 ==============================================================================
|
|
|
137 [..]
|
|
|
138 This section provides functions allowing to:
|
|
|
139 (+) Initialize and configure TIM HAL Sensor.
|
|
|
140 (+) De-initialize TIM HAL Sensor.
|
|
|
141 (+) Start the Hall Sensor Interface.
|
|
|
142 (+) Stop the Hall Sensor Interface.
|
|
|
143 (+) Start the Hall Sensor Interface and enable interrupts.
|
|
|
144 (+) Stop the Hall Sensor Interface and disable interrupts.
|
|
|
145 (+) Start the Hall Sensor Interface and enable DMA transfers.
|
|
|
146 (+) Stop the Hall Sensor Interface and disable DMA transfers.
|
|
|
147
|
|
|
148 @endverbatim
|
|
|
149 * @{
|
|
|
150 */
|
|
|
151 /**
|
|
|
152 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
|
|
|
153 * @param htim: TIM Encoder Interface handle
|
|
|
154 * @param sConfig: TIM Hall Sensor configuration structure
|
|
|
155 * @retval HAL status
|
|
|
156 */
|
|
|
157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
|
|
|
158 {
|
|
|
159 TIM_OC_InitTypeDef OC_Config;
|
|
|
160
|
|
|
161 /* Check the TIM handle allocation */
|
|
|
162 if(htim == NULL)
|
|
|
163 {
|
|
|
164 return HAL_ERROR;
|
|
|
165 }
|
|
|
166
|
|
|
167 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
|
|
|
168 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
|
169 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
|
170 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
|
|
|
171 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
|
|
|
172 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
|
|
|
173
|
|
|
174 if(htim->State == HAL_TIM_STATE_RESET)
|
|
|
175 {
|
|
|
176 /* Allocate lock resource and initialize it */
|
|
|
177 htim->Lock = HAL_UNLOCKED;
|
|
|
178
|
|
|
179 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
|
180 HAL_TIMEx_HallSensor_MspInit(htim);
|
|
|
181 }
|
|
|
182
|
|
|
183 /* Set the TIM state */
|
|
|
184 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
185
|
|
|
186 /* Configure the Time base in the Encoder Mode */
|
|
|
187 TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
|
188
|
|
|
189 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
|
|
|
190 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
|
|
|
191
|
|
|
192 /* Reset the IC1PSC Bits */
|
|
|
193 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
|
|
|
194 /* Set the IC1PSC value */
|
|
|
195 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
|
|
|
196
|
|
|
197 /* Enable the Hall sensor interface (XOR function of the three inputs) */
|
|
|
198 htim->Instance->CR2 |= TIM_CR2_TI1S;
|
|
|
199
|
|
|
200 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
|
|
|
201 htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
|
|
202 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
|
|
|
203
|
|
|
204 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
|
|
|
205 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
|
|
|
206 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
|
|
|
207
|
|
|
208 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
|
|
|
209 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
|
|
|
210 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
|
|
|
211 OC_Config.OCMode = TIM_OCMODE_PWM2;
|
|
|
212 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
|
|
|
213 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
|
|
|
214 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
|
215 OC_Config.Pulse = sConfig->Commutation_Delay;
|
|
|
216
|
|
|
217 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
|
|
|
218
|
|
|
219 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
|
|
|
220 register to 101 */
|
|
|
221 htim->Instance->CR2 &= ~TIM_CR2_MMS;
|
|
|
222 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
|
|
|
223
|
|
|
224 /* Initialize the TIM state*/
|
|
|
225 htim->State= HAL_TIM_STATE_READY;
|
|
|
226
|
|
|
227 return HAL_OK;
|
|
|
228 }
|
|
|
229
|
|
|
230 /**
|
|
|
231 * @brief DeInitialize the TIM Hall Sensor interface
|
|
|
232 * @param htim: TIM Hall Sensor handle
|
|
|
233 * @retval HAL status
|
|
|
234 */
|
|
|
235 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
|
|
|
236 {
|
|
|
237 /* Check the parameters */
|
|
|
238 assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
239
|
|
|
240 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
241
|
|
|
242 /* Disable the TIM Peripheral Clock */
|
|
|
243 __HAL_TIM_DISABLE(htim);
|
|
|
244
|
|
|
245 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
|
|
246 HAL_TIMEx_HallSensor_MspDeInit(htim);
|
|
|
247
|
|
|
248 /* Change TIM state */
|
|
|
249 htim->State = HAL_TIM_STATE_RESET;
|
|
|
250
|
|
|
251 /* Release Lock */
|
|
|
252 __HAL_UNLOCK(htim);
|
|
|
253
|
|
|
254 return HAL_OK;
|
|
|
255 }
|
|
|
256
|
|
|
257 /**
|
|
|
258 * @brief Initializes the TIM Hall Sensor MSP.
|
|
|
259 * @param htim: TIM handle
|
|
|
260 * @retval None
|
|
|
261 */
|
|
|
262 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
|
|
|
263 {
|
|
|
264 /* Prevent unused argument(s) compilation warning */
|
|
|
265 UNUSED(htim);
|
|
|
266
|
|
|
267 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
268 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
|
|
|
269 */
|
|
|
270 }
|
|
|
271
|
|
|
272 /**
|
|
|
273 * @brief DeInitialize TIM Hall Sensor MSP.
|
|
|
274 * @param htim: TIM handle
|
|
|
275 * @retval None
|
|
|
276 */
|
|
|
277 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
|
|
|
278 {
|
|
|
279 /* Prevent unused argument(s) compilation warning */
|
|
|
280 UNUSED(htim);
|
|
|
281
|
|
|
282 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
283 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
|
|
|
284 */
|
|
|
285 }
|
|
|
286
|
|
|
287 /**
|
|
|
288 * @brief Starts the TIM Hall Sensor Interface.
|
|
|
289 * @param htim : TIM Hall Sensor handle
|
|
|
290 * @retval HAL status
|
|
|
291 */
|
|
|
292 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
|
|
|
293 {
|
|
|
294 /* Check the parameters */
|
|
|
295 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
|
|
|
296
|
|
|
297 /* Enable the Input Capture channels 1
|
|
|
298 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
|
|
299 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
300
|
|
|
301 /* Enable the Peripheral */
|
|
|
302 __HAL_TIM_ENABLE(htim);
|
|
|
303
|
|
|
304 /* Return function status */
|
|
|
305 return HAL_OK;
|
|
|
306 }
|
|
|
307
|
|
|
308 /**
|
|
|
309 * @brief Stops the TIM Hall sensor Interface.
|
|
|
310 * @param htim : TIM Hall Sensor handle
|
|
|
311 * @retval HAL status
|
|
|
312 */
|
|
|
313 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
|
|
|
314 {
|
|
|
315 /* Check the parameters */
|
|
|
316 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
|
|
|
317
|
|
|
318 /* Disable the Input Capture channels 1, 2 and 3
|
|
|
319 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
|
|
320 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
321
|
|
|
322 /* Disable the Peripheral */
|
|
|
323 __HAL_TIM_DISABLE(htim);
|
|
|
324
|
|
|
325 /* Return function status */
|
|
|
326 return HAL_OK;
|
|
|
327 }
|
|
|
328
|
|
|
329 /**
|
|
|
330 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
|
|
|
331 * @param htim : TIM Hall Sensor handle
|
|
|
332 * @retval HAL status
|
|
|
333 */
|
|
|
334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
|
|
|
335 {
|
|
|
336 /* Check the parameters */
|
|
|
337 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
|
|
|
338
|
|
|
339 /* Enable the capture compare Interrupts 1 event */
|
|
|
340 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
341
|
|
|
342 /* Enable the Input Capture channels 1
|
|
|
343 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
|
|
344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
345
|
|
|
346 /* Enable the Peripheral */
|
|
|
347 __HAL_TIM_ENABLE(htim);
|
|
|
348
|
|
|
349 /* Return function status */
|
|
|
350 return HAL_OK;
|
|
|
351 }
|
|
|
352
|
|
|
353 /**
|
|
|
354 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
|
|
|
355 * @param htim : TIM handle
|
|
|
356 * @retval HAL status
|
|
|
357 */
|
|
|
358 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
|
|
|
359 {
|
|
|
360 /* Check the parameters */
|
|
|
361 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
|
|
|
362
|
|
|
363 /* Disable the Input Capture channels 1
|
|
|
364 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
|
|
365 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
366
|
|
|
367 /* Disable the capture compare Interrupts event */
|
|
|
368 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
369
|
|
|
370 /* Disable the Peripheral */
|
|
|
371 __HAL_TIM_DISABLE(htim);
|
|
|
372
|
|
|
373 /* Return function status */
|
|
|
374 return HAL_OK;
|
|
|
375 }
|
|
|
376
|
|
|
377 /**
|
|
|
378 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
|
|
|
379 * @param htim : TIM Hall Sensor handle
|
|
|
380 * @param pData: The destination Buffer address.
|
|
|
381 * @param Length: The length of data to be transferred from TIM peripheral to memory.
|
|
|
382 * @retval HAL status
|
|
|
383 */
|
|
|
384 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
|
|
|
385 {
|
|
|
386 /* Check the parameters */
|
|
|
387 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
|
|
|
388
|
|
|
389 if((htim->State == HAL_TIM_STATE_BUSY))
|
|
|
390 {
|
|
|
391 return HAL_BUSY;
|
|
|
392 }
|
|
|
393 else if((htim->State == HAL_TIM_STATE_READY))
|
|
|
394 {
|
|
|
395 if(((uint32_t)pData == 0 ) && (Length > 0))
|
|
|
396 {
|
|
|
397 return HAL_ERROR;
|
|
|
398 }
|
|
|
399 else
|
|
|
400 {
|
|
|
401 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
402 }
|
|
|
403 }
|
|
|
404 /* Enable the Input Capture channels 1
|
|
|
405 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
|
|
406 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
|
407
|
|
|
408 /* Set the DMA Input Capture 1 Callback */
|
|
|
409 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
|
|
|
410 /* Set the DMA error callback */
|
|
|
411 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
412
|
|
|
413 /* Enable the DMA channel for Capture 1*/
|
|
|
414 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
|
|
|
415
|
|
|
416 /* Enable the capture compare 1 Interrupt */
|
|
|
417 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
418
|
|
|
419 /* Enable the Peripheral */
|
|
|
420 __HAL_TIM_ENABLE(htim);
|
|
|
421
|
|
|
422 /* Return function status */
|
|
|
423 return HAL_OK;
|
|
|
424 }
|
|
|
425
|
|
|
426 /**
|
|
|
427 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
|
|
|
428 * @param htim : TIM handle
|
|
|
429 * @retval HAL status
|
|
|
430 */
|
|
|
431 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
|
|
|
432 {
|
|
|
433 /* Check the parameters */
|
|
|
434 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
|
|
|
435
|
|
|
436 /* Disable the Input Capture channels 1
|
|
|
437 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
|
|
|
438 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
|
|
|
439
|
|
|
440
|
|
|
441 /* Disable the capture compare Interrupts 1 event */
|
|
|
442 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
443
|
|
|
444 /* Disable the Peripheral */
|
|
|
445 __HAL_TIM_DISABLE(htim);
|
|
|
446
|
|
|
447 /* Return function status */
|
|
|
448 return HAL_OK;
|
|
|
449 }
|
|
|
450
|
|
|
451 /**
|
|
|
452 * @}
|
|
|
453 */
|
|
|
454
|
|
|
455 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
|
|
456 * @brief Timer Complementary Output Compare functions
|
|
|
457 *
|
|
|
458 @verbatim
|
|
|
459 ==============================================================================
|
|
|
460 ##### Timer Complementary Output Compare functions #####
|
|
|
461 ==============================================================================
|
|
|
462 [..]
|
|
|
463 This section provides functions allowing to:
|
|
|
464 (+) Start the Complementary Output Compare/PWM.
|
|
|
465 (+) Stop the Complementary Output Compare/PWM.
|
|
|
466 (+) Start the Complementary Output Compare/PWM and enable interrupts.
|
|
|
467 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
|
|
|
468 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
|
|
|
469 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
|
|
|
470
|
|
|
471 @endverbatim
|
|
|
472 * @{
|
|
|
473 */
|
|
|
474
|
|
|
475 /**
|
|
|
476 * @brief Starts the TIM Output Compare signal generation on the complementary
|
|
|
477 * output.
|
|
|
478 * @param htim : TIM Output Compare handle
|
|
|
479 * @param Channel : TIM Channel to be enabled
|
|
|
480 * This parameter can be one of the following values:
|
|
|
481 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
482 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
483 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
484 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
485 * @retval HAL status
|
|
|
486 */
|
|
|
487 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
488 {
|
|
|
489 /* Check the parameters */
|
|
|
490 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
491
|
|
|
492 /* Enable the Capture compare channel N */
|
|
|
493 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
494
|
|
|
495 /* Enable the Main Ouput */
|
|
|
496 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
497
|
|
|
498 /* Enable the Peripheral */
|
|
|
499 __HAL_TIM_ENABLE(htim);
|
|
|
500
|
|
|
501 /* Return function status */
|
|
|
502 return HAL_OK;
|
|
|
503 }
|
|
|
504
|
|
|
505 /**
|
|
|
506 * @brief Stops the TIM Output Compare signal generation on the complementary
|
|
|
507 * output.
|
|
|
508 * @param htim : TIM handle
|
|
|
509 * @param Channel : TIM Channel to be disabled
|
|
|
510 * This parameter can be one of the following values:
|
|
|
511 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
512 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
513 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
514 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
515 * @retval HAL status
|
|
|
516 */
|
|
|
517 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
518 {
|
|
|
519 /* Check the parameters */
|
|
|
520 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
521
|
|
|
522 /* Disable the Capture compare channel N */
|
|
|
523 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
524
|
|
|
525 /* Disable the Main Ouput */
|
|
|
526 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
527
|
|
|
528 /* Disable the Peripheral */
|
|
|
529 __HAL_TIM_DISABLE(htim);
|
|
|
530
|
|
|
531 /* Return function status */
|
|
|
532 return HAL_OK;
|
|
|
533 }
|
|
|
534
|
|
|
535 /**
|
|
|
536 * @brief Starts the TIM Output Compare signal generation in interrupt mode
|
|
|
537 * on the complementary output.
|
|
|
538 * @param htim : TIM OC handle
|
|
|
539 * @param Channel : TIM Channel to be enabled
|
|
|
540 * This parameter can be one of the following values:
|
|
|
541 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
542 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
543 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
544 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
545 * @retval HAL status
|
|
|
546 */
|
|
|
547 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
548 {
|
|
|
549 /* Check the parameters */
|
|
|
550 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
551
|
|
|
552 switch (Channel)
|
|
|
553 {
|
|
|
554 case TIM_CHANNEL_1:
|
|
|
555 {
|
|
|
556 /* Enable the TIM Output Compare interrupt */
|
|
|
557 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
558 }
|
|
|
559 break;
|
|
|
560
|
|
|
561 case TIM_CHANNEL_2:
|
|
|
562 {
|
|
|
563 /* Enable the TIM Output Compare interrupt */
|
|
|
564 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
565 }
|
|
|
566 break;
|
|
|
567
|
|
|
568 case TIM_CHANNEL_3:
|
|
|
569 {
|
|
|
570 /* Enable the TIM Output Compare interrupt */
|
|
|
571 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
|
|
572 }
|
|
|
573 break;
|
|
|
574
|
|
|
575 case TIM_CHANNEL_4:
|
|
|
576 {
|
|
|
577 /* Enable the TIM Output Compare interrupt */
|
|
|
578 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
|
|
579 }
|
|
|
580 break;
|
|
|
581
|
|
|
582 default:
|
|
|
583 break;
|
|
|
584 }
|
|
|
585
|
|
|
586 /* Enable the TIM Break interrupt */
|
|
|
587 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
|
|
|
588
|
|
|
589 /* Enable the Capture compare channel N */
|
|
|
590 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
591
|
|
|
592 /* Enable the Main Ouput */
|
|
|
593 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
594
|
|
|
595 /* Enable the Peripheral */
|
|
|
596 __HAL_TIM_ENABLE(htim);
|
|
|
597
|
|
|
598 /* Return function status */
|
|
|
599 return HAL_OK;
|
|
|
600 }
|
|
|
601
|
|
|
602 /**
|
|
|
603 * @brief Stops the TIM Output Compare signal generation in interrupt mode
|
|
|
604 * on the complementary output.
|
|
|
605 * @param htim : TIM Output Compare handle
|
|
|
606 * @param Channel : TIM Channel to be disabled
|
|
|
607 * This parameter can be one of the following values:
|
|
|
608 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
609 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
610 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
611 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
612 * @retval HAL status
|
|
|
613 */
|
|
|
614 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
615 {
|
|
|
616 uint32_t tmpccer = 0;
|
|
|
617
|
|
|
618 /* Check the parameters */
|
|
|
619 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
620
|
|
|
621 switch (Channel)
|
|
|
622 {
|
|
|
623 case TIM_CHANNEL_1:
|
|
|
624 {
|
|
|
625 /* Disable the TIM Output Compare interrupt */
|
|
|
626 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
627 }
|
|
|
628 break;
|
|
|
629
|
|
|
630 case TIM_CHANNEL_2:
|
|
|
631 {
|
|
|
632 /* Disable the TIM Output Compare interrupt */
|
|
|
633 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
634 }
|
|
|
635 break;
|
|
|
636
|
|
|
637 case TIM_CHANNEL_3:
|
|
|
638 {
|
|
|
639 /* Disable the TIM Output Compare interrupt */
|
|
|
640 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
|
|
641 }
|
|
|
642 break;
|
|
|
643
|
|
|
644 case TIM_CHANNEL_4:
|
|
|
645 {
|
|
|
646 /* Disable the TIM Output Compare interrupt */
|
|
|
647 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
|
|
648 }
|
|
|
649 break;
|
|
|
650
|
|
|
651 default:
|
|
|
652 break;
|
|
|
653 }
|
|
|
654
|
|
|
655 /* Disable the Capture compare channel N */
|
|
|
656 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
657
|
|
|
658 /* Disable the TIM Break interrupt (only if no more channel is active) */
|
|
|
659 tmpccer = htim->Instance->CCER;
|
|
|
660 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
|
|
|
661 {
|
|
|
662 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
|
|
663 }
|
|
|
664
|
|
|
665 /* Disable the Main Ouput */
|
|
|
666 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
667
|
|
|
668 /* Disable the Peripheral */
|
|
|
669 __HAL_TIM_DISABLE(htim);
|
|
|
670
|
|
|
671 /* Return function status */
|
|
|
672 return HAL_OK;
|
|
|
673 }
|
|
|
674
|
|
|
675 /**
|
|
|
676 * @brief Starts the TIM Output Compare signal generation in DMA mode
|
|
|
677 * on the complementary output.
|
|
|
678 * @param htim : TIM Output Compare handle
|
|
|
679 * @param Channel : TIM Channel to be enabled
|
|
|
680 * This parameter can be one of the following values:
|
|
|
681 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
682 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
683 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
684 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
685 * @param pData: The source Buffer address.
|
|
|
686 * @param Length: The length of data to be transferred from memory to TIM peripheral
|
|
|
687 * @retval HAL status
|
|
|
688 */
|
|
|
689 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
|
|
690 {
|
|
|
691 /* Check the parameters */
|
|
|
692 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
693
|
|
|
694 if((htim->State == HAL_TIM_STATE_BUSY))
|
|
|
695 {
|
|
|
696 return HAL_BUSY;
|
|
|
697 }
|
|
|
698 else if((htim->State == HAL_TIM_STATE_READY))
|
|
|
699 {
|
|
|
700 if(((uint32_t)pData == 0 ) && (Length > 0))
|
|
|
701 {
|
|
|
702 return HAL_ERROR;
|
|
|
703 }
|
|
|
704 else
|
|
|
705 {
|
|
|
706 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
707 }
|
|
|
708 }
|
|
|
709 switch (Channel)
|
|
|
710 {
|
|
|
711 case TIM_CHANNEL_1:
|
|
|
712 {
|
|
|
713 /* Set the DMA Period elapsed callback */
|
|
|
714 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
715
|
|
|
716 /* Set the DMA error callback */
|
|
|
717 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
718
|
|
|
719 /* Enable the DMA channel */
|
|
|
720 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
|
|
|
721
|
|
|
722 /* Enable the TIM Output Compare DMA request */
|
|
|
723 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
724 }
|
|
|
725 break;
|
|
|
726
|
|
|
727 case TIM_CHANNEL_2:
|
|
|
728 {
|
|
|
729 /* Set the DMA Period elapsed callback */
|
|
|
730 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
731
|
|
|
732 /* Set the DMA error callback */
|
|
|
733 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
734
|
|
|
735 /* Enable the DMA channel */
|
|
|
736 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
|
|
|
737
|
|
|
738 /* Enable the TIM Output Compare DMA request */
|
|
|
739 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
740 }
|
|
|
741 break;
|
|
|
742
|
|
|
743 case TIM_CHANNEL_3:
|
|
|
744 {
|
|
|
745 /* Set the DMA Period elapsed callback */
|
|
|
746 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
747
|
|
|
748 /* Set the DMA error callback */
|
|
|
749 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
|
|
750
|
|
|
751 /* Enable the DMA channel */
|
|
|
752 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
|
|
|
753
|
|
|
754 /* Enable the TIM Output Compare DMA request */
|
|
|
755 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
756 }
|
|
|
757 break;
|
|
|
758
|
|
|
759 case TIM_CHANNEL_4:
|
|
|
760 {
|
|
|
761 /* Set the DMA Period elapsed callback */
|
|
|
762 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
763
|
|
|
764 /* Set the DMA error callback */
|
|
|
765 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
|
|
766
|
|
|
767 /* Enable the DMA channel */
|
|
|
768 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
|
|
|
769
|
|
|
770 /* Enable the TIM Output Compare DMA request */
|
|
|
771 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
772 }
|
|
|
773 break;
|
|
|
774
|
|
|
775 default:
|
|
|
776 break;
|
|
|
777 }
|
|
|
778
|
|
|
779 /* Enable the Capture compare channel N */
|
|
|
780 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
781
|
|
|
782 /* Enable the Main Ouput */
|
|
|
783 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
784
|
|
|
785 /* Enable the Peripheral */
|
|
|
786 __HAL_TIM_ENABLE(htim);
|
|
|
787
|
|
|
788 /* Return function status */
|
|
|
789 return HAL_OK;
|
|
|
790 }
|
|
|
791
|
|
|
792 /**
|
|
|
793 * @brief Stops the TIM Output Compare signal generation in DMA mode
|
|
|
794 * on the complementary output.
|
|
|
795 * @param htim : TIM Output Compare handle
|
|
|
796 * @param Channel : TIM Channel to be disabled
|
|
|
797 * This parameter can be one of the following values:
|
|
|
798 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
799 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
800 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
801 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
802 * @retval HAL status
|
|
|
803 */
|
|
|
804 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
805 {
|
|
|
806 /* Check the parameters */
|
|
|
807 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
808
|
|
|
809 switch (Channel)
|
|
|
810 {
|
|
|
811 case TIM_CHANNEL_1:
|
|
|
812 {
|
|
|
813 /* Disable the TIM Output Compare DMA request */
|
|
|
814 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
815 }
|
|
|
816 break;
|
|
|
817
|
|
|
818 case TIM_CHANNEL_2:
|
|
|
819 {
|
|
|
820 /* Disable the TIM Output Compare DMA request */
|
|
|
821 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
822 }
|
|
|
823 break;
|
|
|
824
|
|
|
825 case TIM_CHANNEL_3:
|
|
|
826 {
|
|
|
827 /* Disable the TIM Output Compare DMA request */
|
|
|
828 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
829 }
|
|
|
830 break;
|
|
|
831
|
|
|
832 case TIM_CHANNEL_4:
|
|
|
833 {
|
|
|
834 /* Disable the TIM Output Compare interrupt */
|
|
|
835 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
836 }
|
|
|
837 break;
|
|
|
838
|
|
|
839 default:
|
|
|
840 break;
|
|
|
841 }
|
|
|
842
|
|
|
843 /* Disable the Capture compare channel N */
|
|
|
844 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
845
|
|
|
846 /* Disable the Main Ouput */
|
|
|
847 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
848
|
|
|
849 /* Disable the Peripheral */
|
|
|
850 __HAL_TIM_DISABLE(htim);
|
|
|
851
|
|
|
852 /* Change the htim state */
|
|
|
853 htim->State = HAL_TIM_STATE_READY;
|
|
|
854
|
|
|
855 /* Return function status */
|
|
|
856 return HAL_OK;
|
|
|
857 }
|
|
|
858
|
|
|
859 /**
|
|
|
860 * @}
|
|
|
861 */
|
|
|
862
|
|
|
863 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
|
|
864 * @brief Timer Complementary PWM functions
|
|
|
865 *
|
|
|
866 @verbatim
|
|
|
867 ==============================================================================
|
|
|
868 ##### Timer Complementary PWM functions #####
|
|
|
869 ==============================================================================
|
|
|
870 [..]
|
|
|
871 This section provides functions allowing to:
|
|
|
872 (+) Start the Complementary PWM.
|
|
|
873 (+) Stop the Complementary PWM.
|
|
|
874 (+) Start the Complementary PWM and enable interrupts.
|
|
|
875 (+) Stop the Complementary PWM and disable interrupts.
|
|
|
876 (+) Start the Complementary PWM and enable DMA transfers.
|
|
|
877 (+) Stop the Complementary PWM and disable DMA transfers.
|
|
|
878 (+) Start the Complementary Input Capture measurement.
|
|
|
879 (+) Stop the Complementary Input Capture.
|
|
|
880 (+) Start the Complementary Input Capture and enable interrupts.
|
|
|
881 (+) Stop the Complementary Input Capture and disable interrupts.
|
|
|
882 (+) Start the Complementary Input Capture and enable DMA transfers.
|
|
|
883 (+) Stop the Complementary Input Capture and disable DMA transfers.
|
|
|
884 (+) Start the Complementary One Pulse generation.
|
|
|
885 (+) Stop the Complementary One Pulse.
|
|
|
886 (+) Start the Complementary One Pulse and enable interrupts.
|
|
|
887 (+) Stop the Complementary One Pulse and disable interrupts.
|
|
|
888
|
|
|
889 @endverbatim
|
|
|
890 * @{
|
|
|
891 */
|
|
|
892
|
|
|
893 /**
|
|
|
894 * @brief Starts the PWM signal generation on the complementary output.
|
|
|
895 * @param htim : TIM handle
|
|
|
896 * @param Channel : TIM Channel to be enabled
|
|
|
897 * This parameter can be one of the following values:
|
|
|
898 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
899 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
900 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
901 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
902 * @retval HAL status
|
|
|
903 */
|
|
|
904 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
905 {
|
|
|
906 /* Check the parameters */
|
|
|
907 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
908
|
|
|
909 /* Enable the complementary PWM output */
|
|
|
910 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
911
|
|
|
912 /* Enable the Main Ouput */
|
|
|
913 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
914
|
|
|
915 /* Enable the Peripheral */
|
|
|
916 __HAL_TIM_ENABLE(htim);
|
|
|
917
|
|
|
918 /* Return function status */
|
|
|
919 return HAL_OK;
|
|
|
920 }
|
|
|
921
|
|
|
922 /**
|
|
|
923 * @brief Stops the PWM signal generation on the complementary output.
|
|
|
924 * @param htim : TIM handle
|
|
|
925 * @param Channel : TIM Channel to be disabled
|
|
|
926 * This parameter can be one of the following values:
|
|
|
927 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
928 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
929 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
930 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
931 * @retval HAL status
|
|
|
932 */
|
|
|
933 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
934 {
|
|
|
935 /* Check the parameters */
|
|
|
936 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
937
|
|
|
938 /* Disable the complementary PWM output */
|
|
|
939 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
940
|
|
|
941 /* Disable the Main Ouput */
|
|
|
942 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
943
|
|
|
944 /* Disable the Peripheral */
|
|
|
945 __HAL_TIM_DISABLE(htim);
|
|
|
946
|
|
|
947 /* Return function status */
|
|
|
948 return HAL_OK;
|
|
|
949 }
|
|
|
950
|
|
|
951 /**
|
|
|
952 * @brief Starts the PWM signal generation in interrupt mode on the
|
|
|
953 * complementary output.
|
|
|
954 * @param htim : TIM handle
|
|
|
955 * @param Channel : TIM Channel to be disabled
|
|
|
956 * This parameter can be one of the following values:
|
|
|
957 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
958 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
959 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
960 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
961 * @retval HAL status
|
|
|
962 */
|
|
|
963 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
964 {
|
|
|
965 /* Check the parameters */
|
|
|
966 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
967
|
|
|
968 switch (Channel)
|
|
|
969 {
|
|
|
970 case TIM_CHANNEL_1:
|
|
|
971 {
|
|
|
972 /* Enable the TIM Capture/Compare 1 interrupt */
|
|
|
973 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
974 }
|
|
|
975 break;
|
|
|
976
|
|
|
977 case TIM_CHANNEL_2:
|
|
|
978 {
|
|
|
979 /* Enable the TIM Capture/Compare 2 interrupt */
|
|
|
980 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
981 }
|
|
|
982 break;
|
|
|
983
|
|
|
984 case TIM_CHANNEL_3:
|
|
|
985 {
|
|
|
986 /* Enable the TIM Capture/Compare 3 interrupt */
|
|
|
987 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
|
|
|
988 }
|
|
|
989 break;
|
|
|
990
|
|
|
991 case TIM_CHANNEL_4:
|
|
|
992 {
|
|
|
993 /* Enable the TIM Capture/Compare 4 interrupt */
|
|
|
994 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
|
|
|
995 }
|
|
|
996 break;
|
|
|
997
|
|
|
998 default:
|
|
|
999 break;
|
|
|
1000 }
|
|
|
1001
|
|
|
1002 /* Enable the TIM Break interrupt */
|
|
|
1003 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
|
|
|
1004
|
|
|
1005 /* Enable the complementary PWM output */
|
|
|
1006 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
1007
|
|
|
1008 /* Enable the Main Ouput */
|
|
|
1009 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
1010
|
|
|
1011 /* Enable the Peripheral */
|
|
|
1012 __HAL_TIM_ENABLE(htim);
|
|
|
1013
|
|
|
1014 /* Return function status */
|
|
|
1015 return HAL_OK;
|
|
|
1016 }
|
|
|
1017
|
|
|
1018 /**
|
|
|
1019 * @brief Stops the PWM signal generation in interrupt mode on the
|
|
|
1020 * complementary output.
|
|
|
1021 * @param htim : TIM handle
|
|
|
1022 * @param Channel : TIM Channel to be disabled
|
|
|
1023 * This parameter can be one of the following values:
|
|
|
1024 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1025 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1026 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1027 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1028 * @retval HAL status
|
|
|
1029 */
|
|
|
1030 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1031 {
|
|
|
1032 uint32_t tmpccer = 0;
|
|
|
1033
|
|
|
1034 /* Check the parameters */
|
|
|
1035 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
1036
|
|
|
1037 switch (Channel)
|
|
|
1038 {
|
|
|
1039 case TIM_CHANNEL_1:
|
|
|
1040 {
|
|
|
1041 /* Disable the TIM Capture/Compare 1 interrupt */
|
|
|
1042 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
1043 }
|
|
|
1044 break;
|
|
|
1045
|
|
|
1046 case TIM_CHANNEL_2:
|
|
|
1047 {
|
|
|
1048 /* Disable the TIM Capture/Compare 2 interrupt */
|
|
|
1049 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
1050 }
|
|
|
1051 break;
|
|
|
1052
|
|
|
1053 case TIM_CHANNEL_3:
|
|
|
1054 {
|
|
|
1055 /* Disable the TIM Capture/Compare 3 interrupt */
|
|
|
1056 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
|
|
|
1057 }
|
|
|
1058 break;
|
|
|
1059
|
|
|
1060 case TIM_CHANNEL_4:
|
|
|
1061 {
|
|
|
1062 /* Disable the TIM Capture/Compare 3 interrupt */
|
|
|
1063 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
|
|
|
1064 }
|
|
|
1065 break;
|
|
|
1066
|
|
|
1067 default:
|
|
|
1068 break;
|
|
|
1069 }
|
|
|
1070
|
|
|
1071 /* Disable the complementary PWM output */
|
|
|
1072 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
1073
|
|
|
1074
|
|
|
1075 /* Disable the TIM Break interrupt (only if no more channel is active) */
|
|
|
1076 tmpccer = htim->Instance->CCER;
|
|
|
1077 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
|
|
|
1078 {
|
|
|
1079 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
|
|
1080 }
|
|
|
1081
|
|
|
1082 /* Disable the Main Ouput */
|
|
|
1083 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
1084
|
|
|
1085 /* Disable the Peripheral */
|
|
|
1086 __HAL_TIM_DISABLE(htim);
|
|
|
1087
|
|
|
1088 /* Return function status */
|
|
|
1089 return HAL_OK;
|
|
|
1090 }
|
|
|
1091
|
|
|
1092 /**
|
|
|
1093 * @brief Starts the TIM PWM signal generation in DMA mode on the
|
|
|
1094 * complementary output
|
|
|
1095 * @param htim : TIM handle
|
|
|
1096 * @param Channel : TIM Channel to be enabled
|
|
|
1097 * This parameter can be one of the following values:
|
|
|
1098 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1099 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1100 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1101 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1102 * @param pData: The source Buffer address.
|
|
|
1103 * @param Length: The length of data to be transferred from memory to TIM peripheral
|
|
|
1104 * @retval HAL status
|
|
|
1105 */
|
|
|
1106 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
|
|
|
1107 {
|
|
|
1108 /* Check the parameters */
|
|
|
1109 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
1110
|
|
|
1111 if((htim->State == HAL_TIM_STATE_BUSY))
|
|
|
1112 {
|
|
|
1113 return HAL_BUSY;
|
|
|
1114 }
|
|
|
1115 else if((htim->State == HAL_TIM_STATE_READY))
|
|
|
1116 {
|
|
|
1117 if(((uint32_t)pData == 0 ) && (Length > 0))
|
|
|
1118 {
|
|
|
1119 return HAL_ERROR;
|
|
|
1120 }
|
|
|
1121 else
|
|
|
1122 {
|
|
|
1123 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
1124 }
|
|
|
1125 }
|
|
|
1126 switch (Channel)
|
|
|
1127 {
|
|
|
1128 case TIM_CHANNEL_1:
|
|
|
1129 {
|
|
|
1130 /* Set the DMA Period elapsed callback */
|
|
|
1131 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
1132
|
|
|
1133 /* Set the DMA error callback */
|
|
|
1134 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
|
|
|
1135
|
|
|
1136 /* Enable the DMA channel */
|
|
|
1137 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
|
|
|
1138
|
|
|
1139 /* Enable the TIM Capture/Compare 1 DMA request */
|
|
|
1140 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
1141 }
|
|
|
1142 break;
|
|
|
1143
|
|
|
1144 case TIM_CHANNEL_2:
|
|
|
1145 {
|
|
|
1146 /* Set the DMA Period elapsed callback */
|
|
|
1147 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
1148
|
|
|
1149 /* Set the DMA error callback */
|
|
|
1150 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
|
|
|
1151
|
|
|
1152 /* Enable the DMA channel */
|
|
|
1153 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
|
|
|
1154
|
|
|
1155 /* Enable the TIM Capture/Compare 2 DMA request */
|
|
|
1156 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
1157 }
|
|
|
1158 break;
|
|
|
1159
|
|
|
1160 case TIM_CHANNEL_3:
|
|
|
1161 {
|
|
|
1162 /* Set the DMA Period elapsed callback */
|
|
|
1163 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
1164
|
|
|
1165 /* Set the DMA error callback */
|
|
|
1166 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
|
|
|
1167
|
|
|
1168 /* Enable the DMA channel */
|
|
|
1169 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
|
|
|
1170
|
|
|
1171 /* Enable the TIM Capture/Compare 3 DMA request */
|
|
|
1172 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
1173 }
|
|
|
1174 break;
|
|
|
1175
|
|
|
1176 case TIM_CHANNEL_4:
|
|
|
1177 {
|
|
|
1178 /* Set the DMA Period elapsed callback */
|
|
|
1179 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
|
|
|
1180
|
|
|
1181 /* Set the DMA error callback */
|
|
|
1182 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
|
|
|
1183
|
|
|
1184 /* Enable the DMA channel */
|
|
|
1185 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
|
|
|
1186
|
|
|
1187 /* Enable the TIM Capture/Compare 4 DMA request */
|
|
|
1188 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
1189 }
|
|
|
1190 break;
|
|
|
1191
|
|
|
1192 default:
|
|
|
1193 break;
|
|
|
1194 }
|
|
|
1195
|
|
|
1196 /* Enable the complementary PWM output */
|
|
|
1197 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
|
|
|
1198
|
|
|
1199 /* Enable the Main Ouput */
|
|
|
1200 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
1201
|
|
|
1202 /* Enable the Peripheral */
|
|
|
1203 __HAL_TIM_ENABLE(htim);
|
|
|
1204
|
|
|
1205 /* Return function status */
|
|
|
1206 return HAL_OK;
|
|
|
1207 }
|
|
|
1208
|
|
|
1209 /**
|
|
|
1210 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
|
|
|
1211 * output
|
|
|
1212 * @param htim : TIM handle
|
|
|
1213 * @param Channel : TIM Channel to be disabled
|
|
|
1214 * This parameter can be one of the following values:
|
|
|
1215 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1216 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1217 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
|
1218 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
|
1219 * @retval HAL status
|
|
|
1220 */
|
|
|
1221 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
|
1222 {
|
|
|
1223 /* Check the parameters */
|
|
|
1224 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
|
|
|
1225
|
|
|
1226 switch (Channel)
|
|
|
1227 {
|
|
|
1228 case TIM_CHANNEL_1:
|
|
|
1229 {
|
|
|
1230 /* Disable the TIM Capture/Compare 1 DMA request */
|
|
|
1231 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
|
|
|
1232 }
|
|
|
1233 break;
|
|
|
1234
|
|
|
1235 case TIM_CHANNEL_2:
|
|
|
1236 {
|
|
|
1237 /* Disable the TIM Capture/Compare 2 DMA request */
|
|
|
1238 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
|
|
|
1239 }
|
|
|
1240 break;
|
|
|
1241
|
|
|
1242 case TIM_CHANNEL_3:
|
|
|
1243 {
|
|
|
1244 /* Disable the TIM Capture/Compare 3 DMA request */
|
|
|
1245 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
|
|
|
1246 }
|
|
|
1247 break;
|
|
|
1248
|
|
|
1249 case TIM_CHANNEL_4:
|
|
|
1250 {
|
|
|
1251 /* Disable the TIM Capture/Compare 4 DMA request */
|
|
|
1252 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
|
|
|
1253 }
|
|
|
1254 break;
|
|
|
1255
|
|
|
1256 default:
|
|
|
1257 break;
|
|
|
1258 }
|
|
|
1259
|
|
|
1260 /* Disable the complementary PWM output */
|
|
|
1261 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
|
|
|
1262
|
|
|
1263 /* Disable the Main Ouput */
|
|
|
1264 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
1265
|
|
|
1266 /* Disable the Peripheral */
|
|
|
1267 __HAL_TIM_DISABLE(htim);
|
|
|
1268
|
|
|
1269 /* Change the htim state */
|
|
|
1270 htim->State = HAL_TIM_STATE_READY;
|
|
|
1271
|
|
|
1272 /* Return function status */
|
|
|
1273 return HAL_OK;
|
|
|
1274 }
|
|
|
1275
|
|
|
1276 /**
|
|
|
1277 * @}
|
|
|
1278 */
|
|
|
1279
|
|
|
1280 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
|
|
1281 * @brief Timer Complementary One Pulse functions
|
|
|
1282 *
|
|
|
1283 @verbatim
|
|
|
1284 ==============================================================================
|
|
|
1285 ##### Timer Complementary One Pulse functions #####
|
|
|
1286 ==============================================================================
|
|
|
1287 [..]
|
|
|
1288 This section provides functions allowing to:
|
|
|
1289 (+) Start the Complementary One Pulse generation.
|
|
|
1290 (+) Stop the Complementary One Pulse.
|
|
|
1291 (+) Start the Complementary One Pulse and enable interrupts.
|
|
|
1292 (+) Stop the Complementary One Pulse and disable interrupts.
|
|
|
1293
|
|
|
1294 @endverbatim
|
|
|
1295 * @{
|
|
|
1296 */
|
|
|
1297
|
|
|
1298 /**
|
|
|
1299 * @brief Starts the TIM One Pulse signal generation on the complementary
|
|
|
1300 * output.
|
|
|
1301 * @param htim : TIM One Pulse handle
|
|
|
1302 * @param OutputChannel : TIM Channel to be enabled
|
|
|
1303 * This parameter can be one of the following values:
|
|
|
1304 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1305 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1306 * @retval HAL status
|
|
|
1307 */
|
|
|
1308 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
|
1309 {
|
|
|
1310 /* Check the parameters */
|
|
|
1311 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
|
|
1312
|
|
|
1313 /* Enable the complementary One Pulse output */
|
|
|
1314 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
|
|
|
1315
|
|
|
1316 /* Enable the Main Ouput */
|
|
|
1317 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
1318
|
|
|
1319 /* Return function status */
|
|
|
1320 return HAL_OK;
|
|
|
1321 }
|
|
|
1322
|
|
|
1323 /**
|
|
|
1324 * @brief Stops the TIM One Pulse signal generation on the complementary
|
|
|
1325 * output.
|
|
|
1326 * @param htim : TIM One Pulse handle
|
|
|
1327 * @param OutputChannel : TIM Channel to be disabled
|
|
|
1328 * This parameter can be one of the following values:
|
|
|
1329 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1330 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1331 * @retval HAL status
|
|
|
1332 */
|
|
|
1333 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
|
1334 {
|
|
|
1335
|
|
|
1336 /* Check the parameters */
|
|
|
1337 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
|
|
1338
|
|
|
1339 /* Disable the complementary One Pulse output */
|
|
|
1340 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
|
|
|
1341
|
|
|
1342 /* Disable the Main Ouput */
|
|
|
1343 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
1344
|
|
|
1345 /* Disable the Peripheral */
|
|
|
1346 __HAL_TIM_DISABLE(htim);
|
|
|
1347
|
|
|
1348 /* Return function status */
|
|
|
1349 return HAL_OK;
|
|
|
1350 }
|
|
|
1351
|
|
|
1352 /**
|
|
|
1353 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
|
|
|
1354 * complementary channel.
|
|
|
1355 * @param htim : TIM One Pulse handle
|
|
|
1356 * @param OutputChannel : TIM Channel to be enabled
|
|
|
1357 * This parameter can be one of the following values:
|
|
|
1358 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1359 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1360 * @retval HAL status
|
|
|
1361 */
|
|
|
1362 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
|
1363 {
|
|
|
1364 /* Check the parameters */
|
|
|
1365 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
|
|
1366
|
|
|
1367 /* Enable the TIM Capture/Compare 1 interrupt */
|
|
|
1368 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
|
|
|
1369
|
|
|
1370 /* Enable the TIM Capture/Compare 2 interrupt */
|
|
|
1371 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
|
|
|
1372
|
|
|
1373 /* Enable the complementary One Pulse output */
|
|
|
1374 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
|
|
|
1375
|
|
|
1376 /* Enable the Main Ouput */
|
|
|
1377 __HAL_TIM_MOE_ENABLE(htim);
|
|
|
1378
|
|
|
1379 /* Return function status */
|
|
|
1380 return HAL_OK;
|
|
|
1381 }
|
|
|
1382
|
|
|
1383 /**
|
|
|
1384 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
|
|
|
1385 * complementary channel.
|
|
|
1386 * @param htim : TIM One Pulse handle
|
|
|
1387 * @param OutputChannel : TIM Channel to be disabled
|
|
|
1388 * This parameter can be one of the following values:
|
|
|
1389 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
|
1390 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
|
1391 * @retval HAL status
|
|
|
1392 */
|
|
|
1393 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
|
|
|
1394 {
|
|
|
1395 /* Check the parameters */
|
|
|
1396 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
|
|
|
1397
|
|
|
1398 /* Disable the TIM Capture/Compare 1 interrupt */
|
|
|
1399 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
|
|
|
1400
|
|
|
1401 /* Disable the TIM Capture/Compare 2 interrupt */
|
|
|
1402 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
|
|
|
1403
|
|
|
1404 /* Disable the complementary One Pulse output */
|
|
|
1405 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
|
|
|
1406
|
|
|
1407 /* Disable the Main Ouput */
|
|
|
1408 __HAL_TIM_MOE_DISABLE(htim);
|
|
|
1409
|
|
|
1410 /* Disable the Peripheral */
|
|
|
1411 __HAL_TIM_DISABLE(htim);
|
|
|
1412
|
|
|
1413 /* Return function status */
|
|
|
1414 return HAL_OK;
|
|
|
1415 }
|
|
|
1416
|
|
|
1417 /**
|
|
|
1418 * @}
|
|
|
1419 */
|
|
|
1420
|
|
|
1421 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
|
|
1422 * @brief Peripheral Control functions
|
|
|
1423 *
|
|
|
1424 @verbatim
|
|
|
1425 ==============================================================================
|
|
|
1426 ##### Peripheral Control functions #####
|
|
|
1427 ==============================================================================
|
|
|
1428 [..]
|
|
|
1429 This section provides functions allowing to:
|
|
|
1430 (+) Configure the commutation event in case of use of the Hall sensor interface.
|
|
|
1431 (+) Configure Output channels for OC and PWM mode.
|
|
|
1432
|
|
|
1433 (+) Configure Complementary channels, break features and dead time.
|
|
|
1434 (+) Configure Master synchronization.
|
|
|
1435 (+) Configure timer remapping capabilities.
|
|
|
1436 (+) Enable or disable channel grouping
|
|
|
1437
|
|
|
1438 @endverbatim
|
|
|
1439 * @{
|
|
|
1440 */
|
|
|
1441
|
|
|
1442 /**
|
|
|
1443 * @brief Configure the TIM commutation event sequence.
|
|
|
1444 * @note This function is mandatory to use the commutation event in order to
|
|
|
1445 * update the configuration at each commutation detection on the TRGI input of the Timer,
|
|
|
1446 * the typical use of this feature is with the use of another Timer(interface Timer)
|
|
|
1447 * configured in Hall sensor interface, this interface Timer will generate the
|
|
|
1448 * commutation at its TRGO output (connected to Timer used in this function) each time
|
|
|
1449 * the TI1 of the Interface Timer detect a commutation at its input TI1.
|
|
|
1450 * @param htim: TIM handle
|
|
|
1451 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
|
|
|
1452 * This parameter can be one of the following values:
|
|
|
1453 * @arg TIM_TS_ITR0: Internal trigger 0 selected
|
|
|
1454 * @arg TIM_TS_ITR1: Internal trigger 1 selected
|
|
|
1455 * @arg TIM_TS_ITR2: Internal trigger 2 selected
|
|
|
1456 * @arg TIM_TS_ITR3: Internal trigger 3 selected
|
|
|
1457 * @arg TIM_TS_NONE: No trigger is needed
|
|
|
1458 * @param CommutationSource : the Commutation Event source
|
|
|
1459 * This parameter can be one of the following values:
|
|
|
1460 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
|
|
|
1461 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
|
|
|
1462 * @retval HAL status
|
|
|
1463 */
|
|
|
1464 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
|
|
|
1465 {
|
|
|
1466 /* Check the parameters */
|
|
|
1467 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
|
|
|
1468 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
|
|
|
1469
|
|
|
1470 __HAL_LOCK(htim);
|
|
|
1471
|
|
|
1472 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
|
|
|
1473 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
|
|
|
1474 {
|
|
|
1475 /* Select the Input trigger */
|
|
|
1476 htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
|
|
1477 htim->Instance->SMCR |= InputTrigger;
|
|
|
1478 }
|
|
|
1479
|
|
|
1480 /* Select the Capture Compare preload feature */
|
|
|
1481 htim->Instance->CR2 |= TIM_CR2_CCPC;
|
|
|
1482 /* Select the Commutation event source */
|
|
|
1483 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
|
|
|
1484 htim->Instance->CR2 |= CommutationSource;
|
|
|
1485
|
|
|
1486 __HAL_UNLOCK(htim);
|
|
|
1487
|
|
|
1488 return HAL_OK;
|
|
|
1489 }
|
|
|
1490
|
|
|
1491 /**
|
|
|
1492 * @brief Configure the TIM commutation event sequence with interrupt.
|
|
|
1493 * @note This function is mandatory to use the commutation event in order to
|
|
|
1494 * update the configuration at each commutation detection on the TRGI input of the Timer,
|
|
|
1495 * the typical use of this feature is with the use of another Timer(interface Timer)
|
|
|
1496 * configured in Hall sensor interface, this interface Timer will generate the
|
|
|
1497 * commutation at its TRGO output (connected to Timer used in this function) each time
|
|
|
1498 * the TI1 of the Interface Timer detect a commutation at its input TI1.
|
|
|
1499 * @param htim: TIM handle
|
|
|
1500 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
|
|
|
1501 * This parameter can be one of the following values:
|
|
|
1502 * @arg TIM_TS_ITR0: Internal trigger 0 selected
|
|
|
1503 * @arg TIM_TS_ITR1: Internal trigger 1 selected
|
|
|
1504 * @arg TIM_TS_ITR2: Internal trigger 2 selected
|
|
|
1505 * @arg TIM_TS_ITR3: Internal trigger 3 selected
|
|
|
1506 * @arg TIM_TS_NONE: No trigger is needed
|
|
|
1507 * @param CommutationSource : the Commutation Event source
|
|
|
1508 * This parameter can be one of the following values:
|
|
|
1509 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
|
|
|
1510 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
|
|
|
1511 * @retval HAL status
|
|
|
1512 */
|
|
|
1513 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
|
|
|
1514 {
|
|
|
1515 /* Check the parameters */
|
|
|
1516 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
|
|
|
1517 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
|
|
|
1518
|
|
|
1519 __HAL_LOCK(htim);
|
|
|
1520
|
|
|
1521 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
|
|
|
1522 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
|
|
|
1523 {
|
|
|
1524 /* Select the Input trigger */
|
|
|
1525 htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
|
|
1526 htim->Instance->SMCR |= InputTrigger;
|
|
|
1527 }
|
|
|
1528
|
|
|
1529 /* Select the Capture Compare preload feature */
|
|
|
1530 htim->Instance->CR2 |= TIM_CR2_CCPC;
|
|
|
1531 /* Select the Commutation event source */
|
|
|
1532 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
|
|
|
1533 htim->Instance->CR2 |= CommutationSource;
|
|
|
1534
|
|
|
1535 /* Enable the Commutation Interrupt Request */
|
|
|
1536 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
|
|
|
1537
|
|
|
1538 __HAL_UNLOCK(htim);
|
|
|
1539
|
|
|
1540 return HAL_OK;
|
|
|
1541 }
|
|
|
1542
|
|
|
1543 /**
|
|
|
1544 * @brief Configure the TIM commutation event sequence with DMA.
|
|
|
1545 * @note This function is mandatory to use the commutation event in order to
|
|
|
1546 * update the configuration at each commutation detection on the TRGI input of the Timer,
|
|
|
1547 * the typical use of this feature is with the use of another Timer(interface Timer)
|
|
|
1548 * configured in Hall sensor interface, this interface Timer will generate the
|
|
|
1549 * commutation at its TRGO output (connected to Timer used in this function) each time
|
|
|
1550 * the TI1 of the Interface Timer detect a commutation at its input TI1.
|
|
|
1551 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
|
|
|
1552 * @param htim: TIM handle
|
|
|
1553 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
|
|
|
1554 * This parameter can be one of the following values:
|
|
|
1555 * @arg TIM_TS_ITR0: Internal trigger 0 selected
|
|
|
1556 * @arg TIM_TS_ITR1: Internal trigger 1 selected
|
|
|
1557 * @arg TIM_TS_ITR2: Internal trigger 2 selected
|
|
|
1558 * @arg TIM_TS_ITR3: Internal trigger 3 selected
|
|
|
1559 * @arg TIM_TS_NONE: No trigger is needed
|
|
|
1560 * @param CommutationSource : the Commutation Event source
|
|
|
1561 * This parameter can be one of the following values:
|
|
|
1562 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
|
|
|
1563 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
|
|
|
1564 * @retval HAL status
|
|
|
1565 */
|
|
|
1566 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
|
|
|
1567 {
|
|
|
1568 /* Check the parameters */
|
|
|
1569 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
|
|
|
1570 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
|
|
|
1571
|
|
|
1572 __HAL_LOCK(htim);
|
|
|
1573
|
|
|
1574 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
|
|
|
1575 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
|
|
|
1576 {
|
|
|
1577 /* Select the Input trigger */
|
|
|
1578 htim->Instance->SMCR &= ~TIM_SMCR_TS;
|
|
|
1579 htim->Instance->SMCR |= InputTrigger;
|
|
|
1580 }
|
|
|
1581
|
|
|
1582 /* Select the Capture Compare preload feature */
|
|
|
1583 htim->Instance->CR2 |= TIM_CR2_CCPC;
|
|
|
1584 /* Select the Commutation event source */
|
|
|
1585 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
|
|
|
1586 htim->Instance->CR2 |= CommutationSource;
|
|
|
1587
|
|
|
1588 /* Enable the Commutation DMA Request */
|
|
|
1589 /* Set the DMA Commutation Callback */
|
|
|
1590 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
|
|
|
1591 /* Set the DMA error callback */
|
|
|
1592 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
|
|
|
1593
|
|
|
1594 /* Enable the Commutation DMA Request */
|
|
|
1595 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
|
|
|
1596
|
|
|
1597 __HAL_UNLOCK(htim);
|
|
|
1598
|
|
|
1599 return HAL_OK;
|
|
|
1600 }
|
|
|
1601
|
|
|
1602 /**
|
|
|
1603 * @brief Configures the TIM in master mode.
|
|
|
1604 * @param htim: TIM handle.
|
|
|
1605 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
|
|
|
1606 * contains the selected trigger output (TRGO) and the Master/Slave
|
|
|
1607 * mode.
|
|
|
1608 * @retval HAL status
|
|
|
1609 */
|
|
|
1610 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
|
1611 TIM_MasterConfigTypeDef * sMasterConfig)
|
|
|
1612 {
|
|
|
1613 uint32_t tmpcr2;
|
|
|
1614 uint32_t tmpsmcr;
|
|
|
1615
|
|
|
1616 /* Check the parameters */
|
|
|
1617 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
|
|
|
1618 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
|
1619 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
1620
|
|
|
1621 /* Check input state */
|
|
|
1622 __HAL_LOCK(htim);
|
|
|
1623
|
|
|
1624 /* Get the TIMx CR2 register value */
|
|
|
1625 tmpcr2 = htim->Instance->CR2;
|
|
|
1626
|
|
|
1627 /* Get the TIMx SMCR register value */
|
|
|
1628 tmpsmcr = htim->Instance->SMCR;
|
|
|
1629
|
|
|
1630 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
|
1631 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
|
1632 {
|
|
|
1633 /* Check the parameters */
|
|
|
1634 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
1635
|
|
|
1636 /* Clear the MMS2 bits */
|
|
|
1637 tmpcr2 &= ~TIM_CR2_MMS2;
|
|
|
1638 /* Select the TRGO2 source*/
|
|
|
1639 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
|
1640 }
|
|
|
1641
|
|
|
1642 /* Reset the MMS Bits */
|
|
|
1643 tmpcr2 &= ~TIM_CR2_MMS;
|
|
|
1644 /* Select the TRGO source */
|
|
|
1645 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
|
1646
|
|
|
1647 /* Reset the MSM Bit */
|
|
|
1648 tmpsmcr &= ~TIM_SMCR_MSM;
|
|
|
1649 /* Set master mode */
|
|
|
1650 tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
|
1651
|
|
|
1652 /* Update TIMx CR2 */
|
|
|
1653 htim->Instance->CR2 = tmpcr2;
|
|
|
1654
|
|
|
1655 /* Update TIMx SMCR */
|
|
|
1656 htim->Instance->SMCR = tmpsmcr;
|
|
|
1657
|
|
|
1658 __HAL_UNLOCK(htim);
|
|
|
1659
|
|
|
1660 return HAL_OK;
|
|
|
1661 }
|
|
|
1662
|
|
|
1663 /**
|
|
|
1664 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
|
|
|
1665 * and the AOE(automatic output enable).
|
|
|
1666 * @param htim: TIM handle
|
|
|
1667 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
|
|
|
1668 * contains the BDTR Register configuration information for the TIM peripheral.
|
|
|
1669 * @retval HAL status
|
|
|
1670 */
|
|
|
1671 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|
|
1672 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
|
|
|
1673 {
|
|
|
1674 uint32_t tmpbdtr = 0;
|
|
|
1675
|
|
|
1676 /* Check the parameters */
|
|
|
1677 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
|
|
|
1678 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
|
|
|
1679 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
|
|
|
1680 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
|
|
|
1681 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
|
|
|
1682 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
|
|
|
1683 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
|
|
|
1684 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
|
|
|
1685 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
|
|
|
1686
|
|
|
1687 /* Check input state */
|
|
|
1688 __HAL_LOCK(htim);
|
|
|
1689
|
|
|
1690 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
|
|
|
1691 the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
|
|
1692
|
|
|
1693 /* Set the BDTR bits */
|
|
|
1694 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
|
|
|
1695 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
|
|
|
1696 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
|
|
|
1697 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
|
|
|
1698 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
|
|
|
1699 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
|
|
1700 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
|
1701 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
|
1702 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
|
|
|
1703
|
|
|
1704 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
|
|
|
1705 {
|
|
|
1706 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
|
|
|
1707 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
|
|
|
1708 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
|
|
|
1709
|
|
|
1710 /* Set the BREAK2 input related BDTR bits */
|
|
|
1711 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
|
|
|
1712 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
|
|
|
1713 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
|
|
|
1714 }
|
|
|
1715
|
|
|
1716 /* Set TIMx_BDTR */
|
|
|
1717 htim->Instance->BDTR = tmpbdtr;
|
|
|
1718
|
|
|
1719 __HAL_UNLOCK(htim);
|
|
|
1720
|
|
|
1721 return HAL_OK;
|
|
|
1722 }
|
|
|
1723
|
|
|
1724 /**
|
|
|
1725 * @brief Configures the break input source.
|
|
|
1726 * @param htim: TIM handle.
|
|
|
1727 * @param BreakInput: Break input to configure
|
|
|
1728 * This parameter can be one of the following values:
|
|
|
1729 * @arg TIM_BREAKINPUT_BRK: Timer break input
|
|
|
1730 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
|
|
|
1731 * @param sBreakInputConfig: Break input source configuration
|
|
|
1732 * @retval HAL status
|
|
|
1733 */
|
|
|
1734 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
|
|
|
1735 uint32_t BreakInput,
|
|
|
1736 TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
|
|
|
1737
|
|
|
1738 {
|
|
|
1739 uint32_t tmporx = 0;
|
|
|
1740 uint32_t bkin_enable_mask = 0;
|
|
|
1741 uint32_t bkin_polarity_mask = 0;
|
|
|
1742 uint32_t bkin_enable_bitpos = 0;
|
|
|
1743 uint32_t bkin_polarity_bitpos = 0;
|
|
|
1744
|
|
|
1745 /* Check the parameters */
|
|
|
1746 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
|
|
|
1747 assert_param(IS_TIM_BREAKINPUT(BreakInput));
|
|
|
1748 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
|
|
|
1749 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
|
|
|
1750
|
|
|
1751 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
|
|
|
1752 defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
1753 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
|
|
|
1754 {
|
|
|
1755 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
|
|
|
1756 }
|
|
|
1757 #else
|
|
|
1758 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
|
|
|
1759 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
|
|
|
1760 /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
1761
|
|
|
1762 /* Check input state */
|
|
|
1763 __HAL_LOCK(htim);
|
|
|
1764
|
|
|
1765 switch(sBreakInputConfig->Source)
|
|
|
1766 {
|
|
|
1767 case TIM_BREAKINPUTSOURCE_BKIN:
|
|
|
1768 {
|
|
|
1769 bkin_enable_mask = TIM1_OR2_BKINE;
|
|
|
1770 bkin_enable_bitpos = 0;
|
|
|
1771 bkin_polarity_mask = TIM1_OR2_BKINP;
|
|
|
1772 bkin_polarity_bitpos = 9;
|
|
|
1773 }
|
|
|
1774 break;
|
|
|
1775 case TIM_BREAKINPUTSOURCE_COMP1:
|
|
|
1776 {
|
|
|
1777 bkin_enable_mask = TIM1_OR2_BKCMP1E;
|
|
|
1778 bkin_enable_bitpos = 1;
|
|
|
1779 bkin_polarity_mask = TIM1_OR2_BKCMP1P;
|
|
|
1780 bkin_polarity_bitpos = 10;
|
|
|
1781 }
|
|
|
1782 break;
|
|
|
1783 case TIM_BREAKINPUTSOURCE_COMP2:
|
|
|
1784 {
|
|
|
1785 bkin_enable_mask = TIM1_OR2_BKCMP2E;
|
|
|
1786 bkin_enable_bitpos = 2;
|
|
|
1787 bkin_polarity_mask = TIM1_OR2_BKCMP2P;
|
|
|
1788 bkin_polarity_bitpos = 11;
|
|
|
1789 }
|
|
|
1790 break;
|
|
|
1791
|
|
|
1792 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
|
|
|
1793 defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
1794 case TIM_BREAKINPUTSOURCE_DFSDM1:
|
|
|
1795 {
|
|
|
1796 bkin_enable_mask = TIM1_OR2_BKDF1BK0E;
|
|
|
1797 bkin_enable_bitpos = 8;
|
|
|
1798 }
|
|
|
1799 break;
|
|
|
1800 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
|
|
|
1801 /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
1802
|
|
|
1803 default:
|
|
|
1804 break;
|
|
|
1805 }
|
|
|
1806
|
|
|
1807 switch(BreakInput)
|
|
|
1808 {
|
|
|
1809 case TIM_BREAKINPUT_BRK:
|
|
|
1810 {
|
|
|
1811 /* Get the TIMx_OR2 register value */
|
|
|
1812 tmporx = htim->Instance->OR2;
|
|
|
1813
|
|
|
1814 /* Enable the break input */
|
|
|
1815 tmporx &= ~bkin_enable_mask;
|
|
|
1816 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
|
|
|
1817
|
|
|
1818 /* Set the break input polarity */
|
|
|
1819 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
|
|
|
1820 defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
1821 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
|
|
|
1822 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
|
|
|
1823 /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
1824 {
|
|
|
1825 tmporx &= ~bkin_polarity_mask;
|
|
|
1826 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
|
|
|
1827 }
|
|
|
1828
|
|
|
1829 /* Set TIMx_OR2 */
|
|
|
1830 htim->Instance->OR2 = tmporx;
|
|
|
1831 }
|
|
|
1832 break;
|
|
|
1833 case TIM_BREAKINPUT_BRK2:
|
|
|
1834 {
|
|
|
1835 /* Get the TIMx_OR3 register value */
|
|
|
1836 tmporx = htim->Instance->OR3;
|
|
|
1837
|
|
|
1838 /* Enable the break input */
|
|
|
1839 tmporx &= ~bkin_enable_mask;
|
|
|
1840 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
|
|
|
1841
|
|
|
1842 /* Set the break input polarity */
|
|
|
1843 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L471xx) || \
|
|
|
1844 defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
|
|
|
1845 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
|
|
|
1846 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L471xx */
|
|
|
1847 /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
1848 {
|
|
|
1849 tmporx &= ~bkin_polarity_mask;
|
|
|
1850 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
|
|
|
1851 }
|
|
|
1852
|
|
|
1853 /* Set TIMx_OR3 */
|
|
|
1854 htim->Instance->OR3 = tmporx;
|
|
|
1855 }
|
|
|
1856 break;
|
|
|
1857 default:
|
|
|
1858 break;
|
|
|
1859 }
|
|
|
1860
|
|
|
1861 __HAL_UNLOCK(htim);
|
|
|
1862
|
|
|
1863 return HAL_OK;
|
|
|
1864 }
|
|
|
1865
|
|
|
1866 /**
|
|
|
1867 * @brief Configures the TIMx Remapping input capabilities.
|
|
|
1868 * @param htim: TIM handle.
|
|
|
1869 * @param Remap: specifies the TIM remapping source.
|
|
|
1870 *
|
|
|
1871 @if STM32L486xx
|
|
|
1872 * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
|
|
|
1873 *
|
|
|
1874 * field1 can have the following values:
|
|
|
1875 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
|
|
|
1876 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
|
|
|
1877 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
|
|
|
1878 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
|
|
|
1879 *
|
|
|
1880 * field2 can have the following values:
|
|
|
1881 * @arg TIM_TIM1_ETR_ADC3_NONE: TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
|
|
|
1882 * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1
|
|
|
1883 * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2
|
|
|
1884 * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3
|
|
|
1885 *
|
|
|
1886 * field3 can have the following values:
|
|
|
1887 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
|
|
|
1888 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
|
|
|
1889 *
|
|
|
1890 * field4 can have the following values:
|
|
|
1891 * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
|
|
|
1892 * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
|
|
|
1893 * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant
|
|
|
1894 @endif
|
|
|
1895 @if STM32L443xx
|
|
|
1896 * For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
|
|
1897 *
|
|
|
1898 * field1 can have the following values:
|
|
|
1899 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
|
|
|
1900 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
|
|
|
1901 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
|
|
|
1902 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
|
|
|
1903 *
|
|
|
1904 * field2 can have the following values:
|
|
|
1905 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
|
|
|
1906 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
|
|
|
1907 *
|
|
|
1908 * field3 can have the following values:
|
|
|
1909 * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output
|
|
|
1910 * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output
|
|
|
1911 *
|
|
|
1912 * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant
|
|
|
1913 *
|
|
|
1914 @endif
|
|
|
1915 @if STM32L486xx
|
|
|
1916 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
|
|
1917 *
|
|
|
1918 * field1 can have the following values:
|
|
|
1919 * @arg TIM_TIM2_ITR1_TIM8_TRGO: TIM2_ITR1 is connected to TIM8_TRGO
|
|
|
1920 * @arg TIM_TIM2_ITR1_OTG_FS_SOF: TIM2_ITR1 is connected to OTG_FS SOF
|
|
|
1921 *
|
|
|
1922 * field2 can have the following values:
|
|
|
1923 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
|
|
|
1924 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
|
|
|
1925 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
|
|
|
1926 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
|
|
|
1927 *
|
|
|
1928 * field3 can have the following values:
|
|
|
1929 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
|
|
|
1930 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
|
|
|
1931 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
|
|
|
1932 * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
|
|
|
1933 @endif
|
|
|
1934 @if STM32L443xx
|
|
|
1935 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
|
|
1936 *
|
|
|
1937 * field1 can have the following values:
|
|
|
1938 * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1
|
|
|
1939 * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF
|
|
|
1940 *
|
|
|
1941 * field2 can have the following values:
|
|
|
1942 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
|
|
|
1943 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
|
|
|
1944 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
|
|
|
1945 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output
|
|
|
1946 *
|
|
|
1947 * field3 can have the following values:
|
|
|
1948 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
|
|
|
1949 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output
|
|
|
1950 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output
|
|
|
1951 * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
|
|
|
1952 *
|
|
|
1953 @endif
|
|
|
1954 @if STM32L486xx
|
|
|
1955 * For TIM3, the parameter is a combination 2 fields(field1 | field2):
|
|
|
1956 *
|
|
|
1957 * field1 can have the following values:
|
|
|
1958 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
|
|
|
1959 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
|
|
|
1960 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output
|
|
|
1961 * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
|
|
|
1962 *
|
|
|
1963 * field2 can have the following values:
|
|
|
1964 * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO
|
|
|
1965 * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output
|
|
|
1966 *
|
|
|
1967 @endif
|
|
|
1968 @if STM32L486xx
|
|
|
1969 * For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
|
|
1970 *
|
|
|
1971 * field1 can have the following values:
|
|
|
1972 * @arg TIM_TIM8_ETR_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
|
|
|
1973 * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
|
|
|
1974 * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
|
|
|
1975 * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
|
|
|
1976 *
|
|
|
1977 * field2 can have the following values:
|
|
|
1978 * @arg TIM_TIM8_ETR_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
|
|
|
1979 * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
|
|
|
1980 * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
|
|
|
1981 * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
|
|
|
1982 *
|
|
|
1983 * field3 can have the following values:
|
|
|
1984 * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
|
|
|
1985 * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
|
|
|
1986 *
|
|
|
1987 * field4 can have the following values:
|
|
|
1988 * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output
|
|
|
1989 * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output
|
|
|
1990 * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant
|
|
|
1991 *
|
|
|
1992 @endif
|
|
|
1993 * For TIM15, the parameter is a combination of 3 fields (field1 | field2):
|
|
|
1994 *
|
|
|
1995 * field1 can have the following values:
|
|
|
1996 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
|
|
|
1997 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
|
|
|
1998 *
|
|
|
1999 * field2 can have the following values:
|
|
|
2000 * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection
|
|
|
2001 * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
|
|
2002 * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
|
|
2003 * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
|
|
2004 *
|
|
|
2005 @if STM32L486xx
|
|
|
2006 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
|
|
|
2007 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
|
|
|
2008 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
|
|
|
2009 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
|
|
|
2010 *
|
|
|
2011 @endif
|
|
|
2012 @if STM32L443xx
|
|
|
2013 * For TIM16, the parameter can have the following values:
|
|
|
2014 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
|
|
|
2015 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
|
|
|
2016 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
|
|
|
2017 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
|
|
|
2018 * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock)
|
|
|
2019 * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source)
|
|
|
2020 * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO
|
|
|
2021 *
|
|
|
2022 @endif
|
|
|
2023 @if STM32L486xx
|
|
|
2024 * For TIM17, the parameter can have the following values:
|
|
|
2025 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
|
|
|
2026 * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock)
|
|
|
2027 * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
|
|
|
2028 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
|
|
|
2029 @endif
|
|
|
2030 *
|
|
|
2031 * @retval HAL status
|
|
|
2032 */
|
|
|
2033 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
|
|
|
2034 {
|
|
|
2035 uint32_t tmpor1 = 0;
|
|
|
2036 uint32_t tmpor2 = 0;
|
|
|
2037
|
|
|
2038 __HAL_LOCK(htim);
|
|
|
2039
|
|
|
2040 /* Check parameters */
|
|
|
2041 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
|
|
|
2042 assert_param(IS_TIM_REMAP(Remap));
|
|
|
2043
|
|
|
2044 /* Set ETR_SEL bit field (if required) */
|
|
|
2045 if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
|
|
|
2046 {
|
|
|
2047 tmpor2 = htim->Instance->OR2;
|
|
|
2048 tmpor2 &= ~TIMx_ETRSEL_MASK;
|
|
|
2049 tmpor2 |= (Remap & TIMx_ETRSEL_MASK);
|
|
|
2050
|
|
|
2051 /* Set TIMx_OR2 */
|
|
|
2052 htim->Instance->OR2 = tmpor2;
|
|
|
2053 }
|
|
|
2054
|
|
|
2055 /* Set other remapping capabilities */
|
|
|
2056 tmpor1 = Remap;
|
|
|
2057 tmpor1 &= ~TIMx_ETRSEL_MASK;
|
|
|
2058
|
|
|
2059 /* Set TIMx_OR1 */
|
|
|
2060 htim->Instance->OR1 = Remap;
|
|
|
2061
|
|
|
2062 /* Set TIMx_OR1 */
|
|
|
2063 htim->Instance->OR1 = tmpor1;
|
|
|
2064
|
|
|
2065 htim->State = HAL_TIM_STATE_READY;
|
|
|
2066
|
|
|
2067 __HAL_UNLOCK(htim);
|
|
|
2068
|
|
|
2069 return HAL_OK;
|
|
|
2070 }
|
|
|
2071
|
|
|
2072 /**
|
|
|
2073 * @brief Group channel 5 and channel 1, 2 or 3
|
|
|
2074 * @param htim: TIM handle.
|
|
|
2075 * @param Channels: specifies the reference signal(s) the OC5REF is combined with.
|
|
|
2076 * This parameter can be any combination of the following values:
|
|
|
2077 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
|
|
|
2078 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
|
|
|
2079 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
|
|
|
2080 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
|
|
|
2081 * @retval HAL status
|
|
|
2082 */
|
|
|
2083 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
|
|
|
2084 {
|
|
|
2085 /* Check parameters */
|
|
|
2086 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
|
|
|
2087 assert_param(IS_TIM_GROUPCH5(Channels));
|
|
|
2088
|
|
|
2089 /* Process Locked */
|
|
|
2090 __HAL_LOCK(htim);
|
|
|
2091
|
|
|
2092 htim->State = HAL_TIM_STATE_BUSY;
|
|
|
2093
|
|
|
2094 /* Clear GC5Cx bit fields */
|
|
|
2095 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
|
|
|
2096
|
|
|
2097 /* Set GC5Cx bit fields */
|
|
|
2098 htim->Instance->CCR5 |= Channels;
|
|
|
2099
|
|
|
2100 htim->State = HAL_TIM_STATE_READY;
|
|
|
2101
|
|
|
2102 __HAL_UNLOCK(htim);
|
|
|
2103
|
|
|
2104 return HAL_OK;
|
|
|
2105 }
|
|
|
2106
|
|
|
2107 /**
|
|
|
2108 * @}
|
|
|
2109 */
|
|
|
2110
|
|
|
2111 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
|
|
2112 * @brief Extended Callbacks functions
|
|
|
2113 *
|
|
|
2114 @verbatim
|
|
|
2115 ==============================================================================
|
|
|
2116 ##### Extended Callbacks functions #####
|
|
|
2117 ==============================================================================
|
|
|
2118 [..]
|
|
|
2119 This section provides Extended TIM callback functions:
|
|
|
2120 (+) Timer Commutation callback
|
|
|
2121 (+) Timer Break callback
|
|
|
2122
|
|
|
2123 @endverbatim
|
|
|
2124 * @{
|
|
|
2125 */
|
|
|
2126
|
|
|
2127 /**
|
|
|
2128 * @brief Hall commutation changed callback in non-blocking mode
|
|
|
2129 * @param htim : TIM handle
|
|
|
2130 * @retval None
|
|
|
2131 */
|
|
|
2132 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
|
|
|
2133 {
|
|
|
2134 /* Prevent unused argument(s) compilation warning */
|
|
|
2135 UNUSED(htim);
|
|
|
2136
|
|
|
2137 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
2138 the HAL_TIMEx_CommutationCallback could be implemented in the user file
|
|
|
2139 */
|
|
|
2140 }
|
|
|
2141
|
|
|
2142 /**
|
|
|
2143 * @brief Hall Break detection callback in non-blocking mode
|
|
|
2144 * @param htim : TIM handle
|
|
|
2145 * @retval None
|
|
|
2146 */
|
|
|
2147 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
|
2148 {
|
|
|
2149 /* Prevent unused argument(s) compilation warning */
|
|
|
2150 UNUSED(htim);
|
|
|
2151
|
|
|
2152 /* NOTE : This function should not be modified, when the callback is needed,
|
|
|
2153 the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
|
2154 */
|
|
|
2155 }
|
|
|
2156
|
|
|
2157 /**
|
|
|
2158 * @}
|
|
|
2159 */
|
|
|
2160
|
|
|
2161 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
|
|
2162 * @brief Extended Peripheral State functions
|
|
|
2163 *
|
|
|
2164 @verbatim
|
|
|
2165 ==============================================================================
|
|
|
2166 ##### Extended Peripheral State functions #####
|
|
|
2167 ==============================================================================
|
|
|
2168 [..]
|
|
|
2169 This subsection permits to get in run-time the status of the peripheral
|
|
|
2170 and the data flow.
|
|
|
2171
|
|
|
2172 @endverbatim
|
|
|
2173 * @{
|
|
|
2174 */
|
|
|
2175
|
|
|
2176 /**
|
|
|
2177 * @brief Return the TIM Hall Sensor interface handle state.
|
|
|
2178 * @param htim: TIM Hall Sensor handle
|
|
|
2179 * @retval HAL state
|
|
|
2180 */
|
|
|
2181 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
|
|
|
2182 {
|
|
|
2183 return htim->State;
|
|
|
2184 }
|
|
|
2185
|
|
|
2186 /**
|
|
|
2187 * @}
|
|
|
2188 */
|
|
|
2189
|
|
|
2190 /**
|
|
|
2191 * @brief TIM DMA Commutation callback.
|
|
|
2192 * @param hdma : pointer to DMA handle.
|
|
|
2193 * @retval None
|
|
|
2194 */
|
|
|
2195 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
|
|
|
2196 {
|
|
|
2197 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
|
2198
|
|
|
2199 htim->State= HAL_TIM_STATE_READY;
|
|
|
2200
|
|
|
2201 HAL_TIMEx_CommutationCallback(htim);
|
|
|
2202 }
|
|
|
2203
|
|
|
2204 /**
|
|
|
2205 * @brief Enables or disables the TIM Capture Compare Channel xN.
|
|
|
2206 * @param TIMx to select the TIM peripheral
|
|
|
2207 * @param Channel: specifies the TIM Channel
|
|
|
2208 * This parameter can be one of the following values:
|
|
|
2209 * @arg TIM_Channel_1: TIM Channel 1
|
|
|
2210 * @arg TIM_Channel_2: TIM Channel 2
|
|
|
2211 * @arg TIM_Channel_3: TIM Channel 3
|
|
|
2212 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
|
|
|
2213 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
|
|
|
2214 * @retval None
|
|
|
2215 */
|
|
|
2216 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
|
|
|
2217 {
|
|
|
2218 uint32_t tmp = 0;
|
|
|
2219
|
|
|
2220 tmp = TIM_CCER_CC1NE << Channel;
|
|
|
2221
|
|
|
2222 /* Reset the CCxNE Bit */
|
|
|
2223 TIMx->CCER &= ~tmp;
|
|
|
2224
|
|
|
2225 /* Set or reset the CCxNE Bit */
|
|
|
2226 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
|
|
|
2227 }
|
|
|
2228
|
|
|
2229 /**
|
|
|
2230 * @}
|
|
|
2231 */
|
|
|
2232
|
|
|
2233 #endif /* HAL_TIM_MODULE_ENABLED */
|
|
|
2234 /**
|
|
|
2235 * @}
|
|
|
2236 */
|
|
|
2237
|
|
|
2238 /**
|
|
|
2239 * @}
|
|
|
2240 */
|
|
|
2241
|
|
|
2242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
