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1 /**
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2 ******************************************************************************
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3 * @file stm32f1xx_hal_rcc.h
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4 * @author MCD Application Team
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5 * @version V1.0.4
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6 * @date 29-April-2016
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7 * @brief Header file of RCC HAL module.
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8 ******************************************************************************
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9 * @attention
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10 *
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11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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12 *
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13 * Redistribution and use in source and binary forms, with or without modification,
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14 * are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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17 * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 * this list of conditions and the following disclaimer in the documentation
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19 * and/or other materials provided with the distribution.
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20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 * may be used to endorse or promote products derived from this software
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22 * without specific prior written permission.
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23 *
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 *
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35 ******************************************************************************
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36 */
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37
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38 /* Define to prevent recursive inclusion -------------------------------------*/
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39 #ifndef __STM32F1xx_HAL_RCC_H
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40 #define __STM32F1xx_HAL_RCC_H
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41
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42 #ifdef __cplusplus
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43 extern "C" {
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44 #endif
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f1xx_hal_def.h"
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48
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49 /** @addtogroup STM32F1xx_HAL_Driver
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50 * @{
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51 */
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52
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53 /** @addtogroup RCC
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54 * @{
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55 */
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56
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57 /** @addtogroup RCC_Private_Constants
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58 * @{
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59 */
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60
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61 /** @defgroup RCC_Timeout RCC Timeout
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62 * @{
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63 */
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64
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65 /* Disable Backup domain write protection state change timeout */
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66 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
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67 /* LSE state change timeout */
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68 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
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69 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
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70 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
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71 #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
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72 #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
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73 #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
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74 #define LSI_VALUE ((uint32_t)40000) /* 40kHz */
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75 /**
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76 * @}
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77 */
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78
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79 /** @defgroup RCC_Register_Offset Register offsets
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80 * @{
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81 */
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82 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
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83 #define RCC_CR_OFFSET 0x00
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84 #define RCC_CFGR_OFFSET 0x04
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85 #define RCC_CIR_OFFSET 0x08
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86 #define RCC_BDCR_OFFSET 0x20
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87 #define RCC_CSR_OFFSET 0x24
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88
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89 /**
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90 * @}
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91 */
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92
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93 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
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94 * @brief RCC registers bit address in the alias region
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95 * @{
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96 */
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97 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
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98 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
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99 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
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100 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
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101 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
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102
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103 /* --- CR Register ---*/
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104 /* Alias word address of HSION bit */
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105 #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
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106 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
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107 /* Alias word address of HSEON bit */
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108 #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
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109 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
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110 /* Alias word address of CSSON bit */
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111 #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
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112 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
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113 /* Alias word address of PLLON bit */
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114 #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
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115 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
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116
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117 /* --- CSR Register ---*/
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118 /* Alias word address of LSION bit */
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119 #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
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120 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
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121
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122 /* Alias word address of RMVF bit */
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123 #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
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124 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
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125
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126 /* --- BDCR Registers ---*/
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127 /* Alias word address of LSEON bit */
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128 #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
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129 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
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130
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131 /* Alias word address of LSEON bit */
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132 #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
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133 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
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134
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135 /* Alias word address of RTCEN bit */
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136 #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
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137 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
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138
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139 /* Alias word address of BDRST bit */
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140 #define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
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141 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4)))
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142
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143 /**
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144 * @}
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145 */
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146
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147 /* CR register byte 2 (Bits[23:16]) base address */
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148 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
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149
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150 /* CIR register byte 1 (Bits[15:8]) base address */
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151 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
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152
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153 /* CIR register byte 2 (Bits[23:16]) base address */
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154 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
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155
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156 /* Defines used for Flags */
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157 #define CR_REG_INDEX ((uint8_t)1)
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158 #define BDCR_REG_INDEX ((uint8_t)2)
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159 #define CSR_REG_INDEX ((uint8_t)3)
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160
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161 #define RCC_FLAG_MASK ((uint8_t)0x1F)
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162
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163 /**
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164 * @}
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165 */
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166
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167 /** @addtogroup RCC_Private_Macros
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168 * @{
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169 */
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170 /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
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171 * @{
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172 */
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173 #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
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174 #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
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175 #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
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176 #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
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177 /**
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178 * @}
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179 */
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180
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181 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
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182 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
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183 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
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184 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
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185 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
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186 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
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187 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
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188 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
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189 ((__HSE__) == RCC_HSE_BYPASS))
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190 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
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191 ((__LSE__) == RCC_LSE_BYPASS))
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192 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
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193 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
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194 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
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195 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
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196 ((__PLL__) == RCC_PLL_ON))
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197
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198 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
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199 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
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200 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
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201 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
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202 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
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203 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
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204 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
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205 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
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206 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
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207 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
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208 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
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209 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
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210 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
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211 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
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212 ((__HCLK__) == RCC_SYSCLK_DIV512))
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213 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
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214 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
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215 ((__PCLK__) == RCC_HCLK_DIV16))
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216 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
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217 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
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218 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
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219 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
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220 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
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221 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
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222
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223 /**
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224 * @}
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225 */
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226
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227 /* Exported types ------------------------------------------------------------*/
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228
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229 /** @defgroup RCC_Exported_Types RCC Exported Types
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230 * @{
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231 */
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232
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233 /**
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234 * @brief RCC PLL configuration structure definition
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235 */
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236 typedef struct
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237 {
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238 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
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239 This parameter can be a value of @ref RCC_PLL_Config */
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240
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241 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
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242 This parameter must be a value of @ref RCC_PLL_Clock_Source */
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243
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244 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
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245 This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
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246 } RCC_PLLInitTypeDef;
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247
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248 /**
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249 * @brief RCC System, AHB and APB busses clock configuration structure definition
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250 */
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251 typedef struct
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252 {
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253 uint32_t ClockType; /*!< The clock to be configured.
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254 This parameter can be a value of @ref RCC_System_Clock_Type */
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255
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256 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
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257 This parameter can be a value of @ref RCC_System_Clock_Source */
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258
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259 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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260 This parameter can be a value of @ref RCC_AHB_Clock_Source */
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261
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262 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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263 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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264
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265 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
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266 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
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267 } RCC_ClkInitTypeDef;
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268
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269 /**
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270 * @}
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271 */
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272
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273 /* Exported constants --------------------------------------------------------*/
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274 /** @defgroup RCC_Exported_Constants RCC Exported Constants
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275 * @{
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276 */
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277
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278 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
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279 * @{
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280 */
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281
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282 #define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
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283 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
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284
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285 /**
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286 * @}
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287 */
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288
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289 /** @defgroup RCC_Oscillator_Type Oscillator Type
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290 * @{
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291 */
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292 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
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293 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
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294 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
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295 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
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296 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
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297 /**
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298 * @}
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299 */
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300
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301 /** @defgroup RCC_HSE_Config HSE Config
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302 * @{
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303 */
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304 #define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
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305 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
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306 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
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307 /**
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308 * @}
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309 */
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310
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311 /** @defgroup RCC_LSE_Config LSE Config
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312 * @{
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313 */
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314 #define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
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315 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
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316 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
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317
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318 /**
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319 * @}
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320 */
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321
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322 /** @defgroup RCC_HSI_Config HSI Config
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323 * @{
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324 */
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325 #define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
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326 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
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327
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328 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
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329
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330 /**
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331 * @}
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332 */
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333
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334 /** @defgroup RCC_LSI_Config LSI Config
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335 * @{
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336 */
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337 #define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
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338 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
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339
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340 /**
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341 * @}
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342 */
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343
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344 /** @defgroup RCC_PLL_Config PLL Config
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345 * @{
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346 */
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347 #define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
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348 #define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
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349 #define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
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350
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351 /**
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352 * @}
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353 */
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354
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355 /** @defgroup RCC_System_Clock_Type System Clock Type
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356 * @{
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357 */
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358 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
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359 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
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360 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
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361 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
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362
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363 /**
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364 * @}
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365 */
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366
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367 /** @defgroup RCC_System_Clock_Source System Clock Source
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368 * @{
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369 */
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370 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
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371 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
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372 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
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373
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374 /**
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375 * @}
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376 */
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377
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378 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
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379 * @{
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380 */
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381 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
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382 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
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383 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
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384
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385 /**
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386 * @}
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387 */
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388
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389 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
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390 * @{
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391 */
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392 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
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393 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
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394 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
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395 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
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396 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
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397 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
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398 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
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399 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
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400 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
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401
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402 /**
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403 * @}
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404 */
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405
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406 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
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407 * @{
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408 */
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409 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
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410 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
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411 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
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412 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
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413 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
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414
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415 /**
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416 * @}
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417 */
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418
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419 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
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420 * @{
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421 */
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422 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
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423 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
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424 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
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425 #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
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426 /**
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427 * @}
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428 */
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429
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430
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431 /** @defgroup RCC_MCO_Index MCO Index
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432 * @{
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433 */
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434 #define RCC_MCO1 ((uint32_t)0x00000000)
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435 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
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436
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437 /**
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438 * @}
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439 */
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440
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441 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
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442 * @{
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443 */
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444 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
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445
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446 /**
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447 * @}
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448 */
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449
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450 /** @defgroup RCC_Interrupt Interrupts
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451 * @{
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452 */
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453 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
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454 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
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455 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
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456 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
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457 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
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458 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
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459 /**
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460 * @}
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461 */
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462
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463 /** @defgroup RCC_Flag Flags
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464 * Elements values convention: XXXYYYYYb
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465 * - YYYYY : Flag position in the register
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466 * - XXX : Register index
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467 * - 001: CR register
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468 * - 010: BDCR register
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469 * - 011: CSR register
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470 * @{
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471 */
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472 /* Flags in the CR register */
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473 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
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474 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
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475 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
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476
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477 /* Flags in the CSR register */
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478 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
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479 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
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480 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
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481 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
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482 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
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483 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
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484 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
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485
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486 /* Flags in the BDCR register */
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487 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
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488
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489 /**
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490 * @}
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491 */
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492
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493 /**
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494 * @}
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495 */
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496
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497 /* Exported macro ------------------------------------------------------------*/
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498
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499 /** @defgroup RCC_Exported_Macros RCC Exported Macros
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500 * @{
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501 */
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502
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503 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
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504 * @brief Enable or disable the AHB1 peripheral clock.
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505 * @note After reset, the peripheral clock (used for registers read/write access)
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506 * is disabled and the application software has to enable this clock before
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507 * using it.
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508 * @{
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509 */
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510 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
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511 __IO uint32_t tmpreg; \
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512 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
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513 /* Delay after an RCC peripheral clock enabling */\
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514 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
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515 UNUSED(tmpreg); \
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|
|
516 } while(0)
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517
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518 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \
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519 __IO uint32_t tmpreg; \
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520 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
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521 /* Delay after an RCC peripheral clock enabling */\
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522 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
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523 UNUSED(tmpreg); \
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|
524 } while(0)
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525
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526 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \
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|
527 __IO uint32_t tmpreg; \
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528 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
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529 /* Delay after an RCC peripheral clock enabling */\
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530 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
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|
531 UNUSED(tmpreg); \
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|
532 } while(0)
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533
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|
534 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
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|
535 __IO uint32_t tmpreg; \
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|
536 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
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|
537 /* Delay after an RCC peripheral clock enabling */\
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|
538 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
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|
539 UNUSED(tmpreg); \
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|
|
540 } while(0)
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|
541
|
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|
542 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
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|
|
543 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
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|
544 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
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|
|
545 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
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546
|
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547 /**
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|
|
548 * @}
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|
|
549 */
|
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|
550
|
|
|
551 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
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|
|
552 * @brief Get the enable or disable status of the AHB peripheral clock.
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553 * @note After reset, the peripheral clock (used for registers read/write access)
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|
|
554 * is disabled and the application software has to enable this clock before
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|
|
555 * using it.
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|
556 * @{
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|
|
557 */
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558
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559 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
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|
560 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
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|
561 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
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|
562 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
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563 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
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564 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
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|
565 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
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|
|
566 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
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567
|
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568 /**
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|
|
569 * @}
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|
570 */
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|
571
|
|
|
572 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
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|
|
573 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
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|
|
574 * @note After reset, the peripheral clock (used for registers read/write access)
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|
575 * is disabled and the application software has to enable this clock before
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|
576 * using it.
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|
577 * @{
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|
578 */
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|
579 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
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|
580 __IO uint32_t tmpreg; \
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|
|
581 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
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|
|
582 /* Delay after an RCC peripheral clock enabling */\
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|
|
583 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
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|
|
584 UNUSED(tmpreg); \
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|
|
585 } while(0)
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|
586
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|
587 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
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|
|
588 __IO uint32_t tmpreg; \
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|
589 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
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|
590 /* Delay after an RCC peripheral clock enabling */\
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|
591 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
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|
592 UNUSED(tmpreg); \
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|
|
593 } while(0)
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594
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|
|
595 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
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|
|
596 __IO uint32_t tmpreg; \
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|
597 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
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598 /* Delay after an RCC peripheral clock enabling */\
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|
599 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
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|
600 UNUSED(tmpreg); \
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|
601 } while(0)
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602
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603 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
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|
604 __IO uint32_t tmpreg; \
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|
|
605 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
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|
606 /* Delay after an RCC peripheral clock enabling */\
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|
607 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
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|
|
608 UNUSED(tmpreg); \
|
|
|
609 } while(0)
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|
|
610
|
|
|
611 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
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|
|
612 __IO uint32_t tmpreg; \
|
|
|
613 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
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|
|
614 /* Delay after an RCC peripheral clock enabling */\
|
|
|
615 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
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|
|
616 UNUSED(tmpreg); \
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|
|
617 } while(0)
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|
|
618
|
|
|
619 #define __HAL_RCC_BKP_CLK_ENABLE() do { \
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|
|
620 __IO uint32_t tmpreg; \
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|
|
621 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
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|
|
622 /* Delay after an RCC peripheral clock enabling */\
|
|
|
623 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
|
|
|
624 UNUSED(tmpreg); \
|
|
|
625 } while(0)
|
|
|
626
|
|
|
627 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
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|
|
628 __IO uint32_t tmpreg; \
|
|
|
629 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
|
|
630 /* Delay after an RCC peripheral clock enabling */\
|
|
|
631 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
|
|
632 UNUSED(tmpreg); \
|
|
|
633 } while(0)
|
|
|
634
|
|
|
635 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
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|
|
636 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
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|
|
637 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
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|
|
638 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
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|
|
639 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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|
|
640
|
|
|
641 #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
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|
|
642 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
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|
|
643
|
|
|
644 /**
|
|
|
645 * @}
|
|
|
646 */
|
|
|
647
|
|
|
648 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
|
|
|
649 * @brief Get the enable or disable status of the APB1 peripheral clock.
|
|
|
650 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
651 * is disabled and the application software has to enable this clock before
|
|
|
652 * using it.
|
|
|
653 * @{
|
|
|
654 */
|
|
|
655
|
|
|
656 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
|
|
|
657 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
|
|
|
658 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
|
|
|
659 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
|
|
|
660 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
|
|
|
661 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
|
|
|
662 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
|
|
|
663 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
|
|
|
664 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
|
|
|
665 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
|
|
|
666 #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
|
|
|
667 #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
|
|
|
668 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
|
|
|
669 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
|
|
|
670
|
|
|
671 /**
|
|
|
672 * @}
|
|
|
673 */
|
|
|
674
|
|
|
675 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
|
|
|
676 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
|
|
|
677 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
678 * is disabled and the application software has to enable this clock before
|
|
|
679 * using it.
|
|
|
680 * @{
|
|
|
681 */
|
|
|
682 #define __HAL_RCC_AFIO_CLK_ENABLE() do { \
|
|
|
683 __IO uint32_t tmpreg; \
|
|
|
684 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
|
|
|
685 /* Delay after an RCC peripheral clock enabling */\
|
|
|
686 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
|
|
|
687 UNUSED(tmpreg); \
|
|
|
688 } while(0)
|
|
|
689
|
|
|
690 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
|
|
|
691 __IO uint32_t tmpreg; \
|
|
|
692 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
|
|
|
693 /* Delay after an RCC peripheral clock enabling */\
|
|
|
694 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
|
|
|
695 UNUSED(tmpreg); \
|
|
|
696 } while(0)
|
|
|
697
|
|
|
698 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
|
|
|
699 __IO uint32_t tmpreg; \
|
|
|
700 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
|
|
|
701 /* Delay after an RCC peripheral clock enabling */\
|
|
|
702 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
|
|
|
703 UNUSED(tmpreg); \
|
|
|
704 } while(0)
|
|
|
705
|
|
|
706 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
|
|
|
707 __IO uint32_t tmpreg; \
|
|
|
708 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
|
|
|
709 /* Delay after an RCC peripheral clock enabling */\
|
|
|
710 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
|
|
|
711 UNUSED(tmpreg); \
|
|
|
712 } while(0)
|
|
|
713
|
|
|
714 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
|
|
|
715 __IO uint32_t tmpreg; \
|
|
|
716 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
|
|
|
717 /* Delay after an RCC peripheral clock enabling */\
|
|
|
718 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
|
|
|
719 UNUSED(tmpreg); \
|
|
|
720 } while(0)
|
|
|
721
|
|
|
722 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
|
|
|
723 __IO uint32_t tmpreg; \
|
|
|
724 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
|
|
725 /* Delay after an RCC peripheral clock enabling */\
|
|
|
726 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
|
|
727 UNUSED(tmpreg); \
|
|
|
728 } while(0)
|
|
|
729
|
|
|
730 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
|
|
|
731 __IO uint32_t tmpreg; \
|
|
|
732 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
|
|
|
733 /* Delay after an RCC peripheral clock enabling */\
|
|
|
734 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
|
|
|
735 UNUSED(tmpreg); \
|
|
|
736 } while(0)
|
|
|
737
|
|
|
738 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
|
|
|
739 __IO uint32_t tmpreg; \
|
|
|
740 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
|
|
741 /* Delay after an RCC peripheral clock enabling */\
|
|
|
742 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
|
|
743 UNUSED(tmpreg); \
|
|
|
744 } while(0)
|
|
|
745
|
|
|
746 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
|
|
|
747 __IO uint32_t tmpreg; \
|
|
|
748 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
|
|
749 /* Delay after an RCC peripheral clock enabling */\
|
|
|
750 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
|
|
751 UNUSED(tmpreg); \
|
|
|
752 } while(0)
|
|
|
753
|
|
|
754 #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
|
|
|
755 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
|
|
|
756 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
|
|
|
757 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
|
|
|
758 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
|
|
|
759 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
|
|
|
760
|
|
|
761 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
|
|
|
762 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
|
|
|
763 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
|
|
|
764
|
|
|
765 /**
|
|
|
766 * @}
|
|
|
767 */
|
|
|
768
|
|
|
769 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
|
|
|
770 * @brief Get the enable or disable status of the APB2 peripheral clock.
|
|
|
771 * @note After reset, the peripheral clock (used for registers read/write access)
|
|
|
772 * is disabled and the application software has to enable this clock before
|
|
|
773 * using it.
|
|
|
774 * @{
|
|
|
775 */
|
|
|
776
|
|
|
777 #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
|
|
|
778 #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
|
|
|
779 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
|
|
|
780 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
|
|
|
781 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
|
|
|
782 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
|
|
|
783 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
|
|
|
784 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
|
|
|
785 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
|
|
|
786 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
|
|
|
787 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
|
|
|
788 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
|
|
|
789 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
|
|
|
790 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
|
|
|
791 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
|
|
|
792 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
|
|
|
793 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
|
|
|
794 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
|
|
|
795
|
|
|
796 /**
|
|
|
797 * @}
|
|
|
798 */
|
|
|
799
|
|
|
800 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
|
|
|
801 * @brief Force or release APB1 peripheral reset.
|
|
|
802 * @{
|
|
|
803 */
|
|
|
804 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
|
|
|
805 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
|
|
|
806 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
|
|
|
807 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
|
|
|
808 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
|
|
|
809 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
|
|
|
810
|
|
|
811 #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
|
|
|
812 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
|
|
|
813
|
|
|
814 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
|
|
|
815 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
|
|
|
816 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
|
|
|
817 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
|
|
|
818 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
|
|
|
819 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
|
|
|
820
|
|
|
821 #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
|
|
|
822 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
|
|
|
823
|
|
|
824 /**
|
|
|
825 * @}
|
|
|
826 */
|
|
|
827
|
|
|
828 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
|
|
|
829 * @brief Force or release APB2 peripheral reset.
|
|
|
830 * @{
|
|
|
831 */
|
|
|
832 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
|
|
|
833 #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
|
|
|
834 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
|
|
|
835 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
|
|
|
836 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
|
|
|
837 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
|
|
|
838 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
|
|
|
839
|
|
|
840 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
|
|
|
841 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
|
|
|
842 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
|
|
|
843
|
|
|
844 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
|
|
|
845 #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
|
|
|
846 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
|
|
|
847 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
|
|
|
848 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
|
|
|
849 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
|
|
|
850 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
|
|
|
851
|
|
|
852 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
|
|
|
853 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
|
|
|
854 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
|
|
|
855
|
|
|
856 /**
|
|
|
857 * @}
|
|
|
858 */
|
|
|
859
|
|
|
860 /** @defgroup RCC_HSI_Configuration HSI Configuration
|
|
|
861 * @{
|
|
|
862 */
|
|
|
863
|
|
|
864 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
|
|
|
865 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
|
|
|
866 * @note HSI can not be stopped if it is used as system clock source. In this case,
|
|
|
867 * you have to select another source of the system clock then stop the HSI.
|
|
|
868 * @note After enabling the HSI, the application software should wait on HSIRDY
|
|
|
869 * flag to be set indicating that HSI clock is stable and can be used as
|
|
|
870 * system clock source.
|
|
|
871 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
|
|
|
872 * clock cycles.
|
|
|
873 */
|
|
|
874 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
|
|
|
875 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
|
|
|
876
|
|
|
877 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
|
|
|
878 * @note The calibration is used to compensate for the variations in voltage
|
|
|
879 * and temperature that influence the frequency of the internal HSI RC.
|
|
|
880 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
|
|
|
881 * (default is RCC_HSICALIBRATION_DEFAULT).
|
|
|
882 * This parameter must be a number between 0 and 0x1F.
|
|
|
883 */
|
|
|
884 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
|
|
|
885 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
|
|
|
886
|
|
|
887 /**
|
|
|
888 * @}
|
|
|
889 */
|
|
|
890
|
|
|
891 /** @defgroup RCC_LSI_Configuration LSI Configuration
|
|
|
892 * @{
|
|
|
893 */
|
|
|
894
|
|
|
895 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
|
|
|
896 * @note After enabling the LSI, the application software should wait on
|
|
|
897 * LSIRDY flag to be set indicating that LSI clock is stable and can
|
|
|
898 * be used to clock the IWDG and/or the RTC.
|
|
|
899 */
|
|
|
900 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
|
|
|
901
|
|
|
902 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
|
|
|
903 * @note LSI can not be disabled if the IWDG is running.
|
|
|
904 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
|
|
|
905 * clock cycles.
|
|
|
906 */
|
|
|
907 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
|
|
|
908
|
|
|
909 /**
|
|
|
910 * @}
|
|
|
911 */
|
|
|
912
|
|
|
913 /** @defgroup RCC_HSE_Configuration HSE Configuration
|
|
|
914 * @{
|
|
|
915 */
|
|
|
916
|
|
|
917 /**
|
|
|
918 * @brief Macro to configure the External High Speed oscillator (HSE).
|
|
|
919 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
|
|
|
920 * supported by this macro. User should request a transition to HSE Off
|
|
|
921 * first and then HSE On or HSE Bypass.
|
|
|
922 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
|
|
|
923 * software should wait on HSERDY flag to be set indicating that HSE clock
|
|
|
924 * is stable and can be used to clock the PLL and/or system clock.
|
|
|
925 * @note HSE state can not be changed if it is used directly or through the
|
|
|
926 * PLL as system clock. In this case, you have to select another source
|
|
|
927 * of the system clock then change the HSE state (ex. disable it).
|
|
|
928 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
|
|
|
929 * @note This function reset the CSSON bit, so if the clock security system(CSS)
|
|
|
930 * was previously enabled you have to enable it again after calling this
|
|
|
931 * function.
|
|
|
932 * @param __STATE__ specifies the new state of the HSE.
|
|
|
933 * This parameter can be one of the following values:
|
|
|
934 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
|
|
|
935 * 6 HSE oscillator clock cycles.
|
|
|
936 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
|
|
|
937 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
|
|
|
938 */
|
|
|
939 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
|
|
|
940 do{ \
|
|
|
941 if ((__STATE__) == RCC_HSE_ON) \
|
|
|
942 { \
|
|
|
943 SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
|
944 } \
|
|
|
945 else if ((__STATE__) == RCC_HSE_OFF) \
|
|
|
946 { \
|
|
|
947 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
|
948 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
|
|
949 } \
|
|
|
950 else if ((__STATE__) == RCC_HSE_BYPASS) \
|
|
|
951 { \
|
|
|
952 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
|
|
953 SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
|
954 } \
|
|
|
955 else \
|
|
|
956 { \
|
|
|
957 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
|
|
|
958 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
|
|
959 } \
|
|
|
960 }while(0)
|
|
|
961
|
|
|
962 /**
|
|
|
963 * @}
|
|
|
964 */
|
|
|
965
|
|
|
966 /** @defgroup RCC_LSE_Configuration LSE Configuration
|
|
|
967 * @{
|
|
|
968 */
|
|
|
969
|
|
|
970 /**
|
|
|
971 * @brief Macro to configure the External Low Speed oscillator (LSE).
|
|
|
972 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
|
|
|
973 * @note As the LSE is in the Backup domain and write access is denied to
|
|
|
974 * this domain after reset, you have to enable write access using
|
|
|
975 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
|
|
976 * (to be done once after reset).
|
|
|
977 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
|
|
|
978 * software should wait on LSERDY flag to be set indicating that LSE clock
|
|
|
979 * is stable and can be used to clock the RTC.
|
|
|
980 * @param __STATE__ specifies the new state of the LSE.
|
|
|
981 * This parameter can be one of the following values:
|
|
|
982 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
|
|
|
983 * 6 LSE oscillator clock cycles.
|
|
|
984 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
|
|
|
985 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
|
|
|
986 */
|
|
|
987 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
|
|
|
988 do{ \
|
|
|
989 if ((__STATE__) == RCC_LSE_ON) \
|
|
|
990 { \
|
|
|
991 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
|
992 } \
|
|
|
993 else if ((__STATE__) == RCC_LSE_OFF) \
|
|
|
994 { \
|
|
|
995 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
|
996 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
|
997 } \
|
|
|
998 else if ((__STATE__) == RCC_LSE_BYPASS) \
|
|
|
999 { \
|
|
|
1000 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
|
1001 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
|
1002 } \
|
|
|
1003 else \
|
|
|
1004 { \
|
|
|
1005 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
|
1006 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
|
1007 } \
|
|
|
1008 }while(0)
|
|
|
1009
|
|
|
1010 /**
|
|
|
1011 * @}
|
|
|
1012 */
|
|
|
1013
|
|
|
1014 /** @defgroup RCC_PLL_Configuration PLL Configuration
|
|
|
1015 * @{
|
|
|
1016 */
|
|
|
1017
|
|
|
1018 /** @brief Macro to enable the main PLL.
|
|
|
1019 * @note After enabling the main PLL, the application software should wait on
|
|
|
1020 * PLLRDY flag to be set indicating that PLL clock is stable and can
|
|
|
1021 * be used as system clock source.
|
|
|
1022 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
|
|
|
1023 */
|
|
|
1024 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
|
|
|
1025
|
|
|
1026 /** @brief Macro to disable the main PLL.
|
|
|
1027 * @note The main PLL can not be disabled if it is used as system clock source
|
|
|
1028 */
|
|
|
1029 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
|
|
|
1030
|
|
|
1031 /** @brief Macro to configure the main PLL clock source and multiplication factors.
|
|
|
1032 * @note This function must be used only when the main PLL is disabled.
|
|
|
1033 *
|
|
|
1034 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
|
|
|
1035 * This parameter can be one of the following values:
|
|
|
1036 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
|
|
|
1037 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
|
|
|
1038 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
|
|
|
1039 * This parameter can be one of the following values:
|
|
|
1040 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
|
|
|
1041 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
|
|
|
1042 @if STM32F105xC
|
|
|
1043 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
|
|
|
1044 @elseif STM32F107xC
|
|
|
1045 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
|
|
|
1046 @else
|
|
|
1047 * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
|
|
|
1048 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
|
|
|
1049 * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
|
|
|
1050 * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
|
|
|
1051 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
|
|
|
1052 * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
|
|
|
1053 * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
|
|
|
1054 * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
|
|
|
1055 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
|
|
|
1056 @endif
|
|
|
1057 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
|
|
|
1058 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
|
|
|
1059 *
|
|
|
1060 */
|
|
|
1061 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
|
|
|
1062 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
|
|
|
1063
|
|
|
1064 /** @brief Get oscillator clock selected as PLL input clock
|
|
|
1065 * @retval The clock source used for PLL entry. The returned value can be one
|
|
|
1066 * of the following:
|
|
|
1067 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
|
|
|
1068 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
|
|
|
1069 */
|
|
|
1070 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
|
|
|
1071
|
|
|
1072 /**
|
|
|
1073 * @}
|
|
|
1074 */
|
|
|
1075
|
|
|
1076 /** @defgroup RCC_Get_Clock_source Get Clock source
|
|
|
1077 * @{
|
|
|
1078 */
|
|
|
1079
|
|
|
1080 /**
|
|
|
1081 * @brief Macro to configure the system clock source.
|
|
|
1082 * @param __SYSCLKSOURCE__ specifies the system clock source.
|
|
|
1083 * This parameter can be one of the following values:
|
|
|
1084 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
|
|
|
1085 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
|
|
|
1086 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
|
|
|
1087 */
|
|
|
1088 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
|
|
|
1089 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
|
|
|
1090
|
|
|
1091 /** @brief Macro to get the clock source used as system clock.
|
|
|
1092 * @retval The clock source used as system clock. The returned value can be one
|
|
|
1093 * of the following:
|
|
|
1094 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
|
|
|
1095 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
|
|
|
1096 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
|
|
|
1097 */
|
|
|
1098 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
|
|
|
1099
|
|
|
1100 /**
|
|
|
1101 * @}
|
|
|
1102 */
|
|
|
1103
|
|
|
1104 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
|
|
|
1105 * @{
|
|
|
1106 */
|
|
|
1107
|
|
|
1108 #if defined(RCC_CFGR_MCO_3)
|
|
|
1109 /** @brief Macro to configure the MCO clock.
|
|
|
1110 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
|
|
1111 * This parameter can be one of the following values:
|
|
|
1112 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
|
|
|
1113 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
|
|
|
1114 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
|
|
|
1115 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
|
|
|
1116 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
|
|
|
1117 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
|
|
|
1118 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
|
|
|
1119 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
|
|
|
1120 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
|
|
|
1121 * @param __MCODIV__ specifies the MCO clock prescaler.
|
|
|
1122 * This parameter can be one of the following values:
|
|
|
1123 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
|
|
|
1124 */
|
|
|
1125 #else
|
|
|
1126 /** @brief Macro to configure the MCO clock.
|
|
|
1127 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
|
|
1128 * This parameter can be one of the following values:
|
|
|
1129 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
|
|
|
1130 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
|
|
|
1131 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
|
|
|
1132 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
|
|
|
1133 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
|
|
|
1134 * @param __MCODIV__ specifies the MCO clock prescaler.
|
|
|
1135 * This parameter can be one of the following values:
|
|
|
1136 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
|
|
|
1137 */
|
|
|
1138 #endif
|
|
|
1139
|
|
|
1140 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
|
|
|
1141 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
|
|
|
1142
|
|
|
1143
|
|
|
1144 /**
|
|
|
1145 * @}
|
|
|
1146 */
|
|
|
1147
|
|
|
1148 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
|
|
|
1149 * @{
|
|
|
1150 */
|
|
|
1151
|
|
|
1152 /** @brief Macro to configure the RTC clock (RTCCLK).
|
|
|
1153 * @note As the RTC clock configuration bits are in the Backup domain and write
|
|
|
1154 * access is denied to this domain after reset, you have to enable write
|
|
|
1155 * access using the Power Backup Access macro before to configure
|
|
|
1156 * the RTC clock source (to be done once after reset).
|
|
|
1157 * @note Once the RTC clock is configured it can't be changed unless the
|
|
|
1158 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
|
|
|
1159 * a Power On Reset (POR).
|
|
|
1160 *
|
|
|
1161 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
|
|
|
1162 * This parameter can be one of the following values:
|
|
|
1163 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
|
|
|
1164 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
|
|
|
1165 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
|
|
|
1166 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
|
|
|
1167 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
|
|
|
1168 * work in STOP and STANDBY modes, and can be used as wakeup source.
|
|
|
1169 * However, when the HSE clock is used as RTC clock source, the RTC
|
|
|
1170 * cannot be used in STOP and STANDBY modes.
|
|
|
1171 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
|
|
|
1172 * RTC clock source).
|
|
|
1173 */
|
|
|
1174 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
|
|
|
1175
|
|
|
1176 /** @brief Macro to get the RTC clock source.
|
|
|
1177 * @retval The clock source can be one of the following values:
|
|
|
1178 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
|
|
|
1179 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
|
|
|
1180 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
|
|
|
1181 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
|
|
|
1182 */
|
|
|
1183 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
|
|
|
1184
|
|
|
1185 /** @brief Macro to enable the the RTC clock.
|
|
|
1186 * @note These macros must be used only after the RTC clock source was selected.
|
|
|
1187 */
|
|
|
1188 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
|
|
|
1189
|
|
|
1190 /** @brief Macro to disable the the RTC clock.
|
|
|
1191 * @note These macros must be used only after the RTC clock source was selected.
|
|
|
1192 */
|
|
|
1193 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
|
|
|
1194
|
|
|
1195 /** @brief Macro to force the Backup domain reset.
|
|
|
1196 * @note This function resets the RTC peripheral (including the backup registers)
|
|
|
1197 * and the RTC clock source selection in RCC_BDCR register.
|
|
|
1198 */
|
|
|
1199 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
|
|
|
1200
|
|
|
1201 /** @brief Macros to release the Backup domain reset.
|
|
|
1202 */
|
|
|
1203 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
|
|
|
1204
|
|
|
1205 /**
|
|
|
1206 * @}
|
|
|
1207 */
|
|
|
1208
|
|
|
1209 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
|
|
|
1210 * @brief macros to manage the specified RCC Flags and interrupts.
|
|
|
1211 * @{
|
|
|
1212 */
|
|
|
1213
|
|
|
1214 /** @brief Enable RCC interrupt.
|
|
|
1215 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
|
|
|
1216 * This parameter can be any combination of the following values:
|
|
|
1217 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
|
|
1218 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
|
|
1219 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
|
|
1220 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
|
|
1221 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
|
|
|
1222 @if STM32F105xx
|
|
|
1223 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
|
1224 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
|
1225 @elsif STM32F107xx
|
|
|
1226 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
|
1227 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
|
1228 @endif
|
|
|
1229 */
|
|
|
1230 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
|
|
|
1231
|
|
|
1232 /** @brief Disable RCC interrupt.
|
|
|
1233 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
|
|
|
1234 * This parameter can be any combination of the following values:
|
|
|
1235 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
|
|
1236 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
|
|
1237 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
|
|
1238 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
|
|
1239 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
|
|
|
1240 @if STM32F105xx
|
|
|
1241 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
|
1242 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
|
1243 @elsif STM32F107xx
|
|
|
1244 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
|
1245 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
|
1246 @endif
|
|
|
1247 */
|
|
|
1248 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
|
|
|
1249
|
|
|
1250 /** @brief Clear the RCC's interrupt pending bits.
|
|
|
1251 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
|
|
1252 * This parameter can be any combination of the following values:
|
|
|
1253 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
|
|
|
1254 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
|
|
|
1255 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
|
|
|
1256 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
|
|
|
1257 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
|
|
|
1258 @if STM32F105xx
|
|
|
1259 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
|
1260 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
|
1261 @elsif STM32F107xx
|
|
|
1262 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
|
1263 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
|
1264 @endif
|
|
|
1265 * @arg @ref RCC_IT_CSS Clock Security System interrupt
|
|
|
1266 */
|
|
|
1267 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
|
|
|
1268
|
|
|
1269 /** @brief Check the RCC's interrupt has occurred or not.
|
|
|
1270 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
|
|
|
1271 * This parameter can be one of the following values:
|
|
|
1272 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
|
|
|
1273 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
|
|
|
1274 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
|
|
|
1275 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
|
|
|
1276 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
|
|
|
1277 @if STM32F105xx
|
|
|
1278 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
|
1279 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
|
1280 @elsif STM32F107xx
|
|
|
1281 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
|
|
|
1282 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
|
|
|
1283 @endif
|
|
|
1284 * @arg @ref RCC_IT_CSS Clock Security System interrupt
|
|
|
1285 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
|
|
1286 */
|
|
|
1287 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
|
|
|
1288
|
|
|
1289 /** @brief Set RMVF bit to clear the reset flags.
|
|
|
1290 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
|
|
|
1291 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
|
|
|
1292 */
|
|
|
1293 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
|
|
|
1294
|
|
|
1295 /** @brief Check RCC flag is set or not.
|
|
|
1296 * @param __FLAG__ specifies the flag to check.
|
|
|
1297 * This parameter can be one of the following values:
|
|
|
1298 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
|
|
|
1299 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
|
|
|
1300 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
|
|
|
1301 @if STM32F105xx
|
|
|
1302 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
|
|
|
1303 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
|
|
|
1304 @elsif STM32F107xx
|
|
|
1305 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
|
|
|
1306 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
|
|
|
1307 @endif
|
|
|
1308 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
|
|
|
1309 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
|
|
|
1310 * @arg @ref RCC_FLAG_PINRST Pin reset.
|
|
|
1311 * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
|
|
|
1312 * @arg @ref RCC_FLAG_SFTRST Software reset.
|
|
|
1313 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
|
|
|
1314 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
|
|
|
1315 * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
|
|
|
1316 * @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
|
1317 */
|
|
|
1318 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
|
|
|
1319 ((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
|
|
|
1320 RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
|
|
|
1321
|
|
|
1322 /**
|
|
|
1323 * @}
|
|
|
1324 */
|
|
|
1325
|
|
|
1326 /**
|
|
|
1327 * @}
|
|
|
1328 */
|
|
|
1329
|
|
|
1330 /* Include RCC HAL Extension module */
|
|
|
1331 #include "stm32f1xx_hal_rcc_ex.h"
|
|
|
1332
|
|
|
1333 /* Exported functions --------------------------------------------------------*/
|
|
|
1334 /** @addtogroup RCC_Exported_Functions
|
|
|
1335 * @{
|
|
|
1336 */
|
|
|
1337
|
|
|
1338 /** @addtogroup RCC_Exported_Functions_Group1
|
|
|
1339 * @{
|
|
|
1340 */
|
|
|
1341
|
|
|
1342 /* Initialization and de-initialization functions ******************************/
|
|
|
1343 void HAL_RCC_DeInit(void);
|
|
|
1344 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
|
|
1345 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
|
|
|
1346
|
|
|
1347 /**
|
|
|
1348 * @}
|
|
|
1349 */
|
|
|
1350
|
|
|
1351 /** @addtogroup RCC_Exported_Functions_Group2
|
|
|
1352 * @{
|
|
|
1353 */
|
|
|
1354
|
|
|
1355 /* Peripheral Control functions ************************************************/
|
|
|
1356 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
|
|
|
1357 void HAL_RCC_EnableCSS(void);
|
|
|
1358 void HAL_RCC_DisableCSS(void);
|
|
|
1359 uint32_t HAL_RCC_GetSysClockFreq(void);
|
|
|
1360 uint32_t HAL_RCC_GetHCLKFreq(void);
|
|
|
1361 uint32_t HAL_RCC_GetPCLK1Freq(void);
|
|
|
1362 uint32_t HAL_RCC_GetPCLK2Freq(void);
|
|
|
1363 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
|
|
1364 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
|
|
|
1365
|
|
|
1366 /* CSS NMI IRQ handler */
|
|
|
1367 void HAL_RCC_NMI_IRQHandler(void);
|
|
|
1368
|
|
|
1369 /* User Callbacks in non blocking mode (IT mode) */
|
|
|
1370 void HAL_RCC_CSSCallback(void);
|
|
|
1371
|
|
|
1372 /**
|
|
|
1373 * @}
|
|
|
1374 */
|
|
|
1375
|
|
|
1376 /**
|
|
|
1377 * @}
|
|
|
1378 */
|
|
|
1379
|
|
|
1380 /**
|
|
|
1381 * @}
|
|
|
1382 */
|
|
|
1383
|
|
|
1384 /**
|
|
|
1385 * @}
|
|
|
1386 */
|
|
|
1387
|
|
|
1388 #ifdef __cplusplus
|
|
|
1389 }
|
|
|
1390 #endif
|
|
|
1391
|
|
|
1392 #endif /* __STM32F1xx_HAL_RCC_H */
|
|
|
1393
|
|
|
1394 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
|
1395
|
